PIC16LF1454T-ESSQTP_技术文档

PIC16(L)F1454/5/9

Data Sheet

14/20-Pin Flash, 8-Bit USB Microcontrollers

with XLP Technology

 2012 Microchip Technology Inc.

Preliminary

DS41639A

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 9781620763476

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

DS41639A-page 2

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

14/20-Pin, 8-Bit Flash USB Microcontroller with

XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• Only 49 Instructions

• 14 Kbytes Linear Program Memory Addressing

• 1024 Bytes Linear Data Memory Addressing

• Operating Speed:

Extreme Low-Power Management

PIC16LF145X with XLP:

• Sleep mode: 25 nA @ 1.8V, typical

• Watchdog Timer Current: 290 nA @ 1.8V, typical

• Timer1 Oscillator: 600 nA @ 32 kHz, typical

• Operating Current: 25 A/MHz @ 1.8V, typical

- DC – 48 MHz clock input

Flexible Oscillator Structure:

- DC – 83 ns instruction cycle

- Selectable 3x or 4x PLL for specific frequencies

• Interrupt Capability with Automatic Context

Saving

• 16-Level Deep Hardware Stack with Optional

Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

capable of accessing both data or program

memory

• 16 MHz Internal Oscillator Block:

- Factory calibrated to ±0.25%, typical

- Software selectable frequency range from

16 MHz to 31 kHz

- Tunable to 0.25% across temperature range

- 48 MHz with 3x PLL

• 31 kHz Low-Power Internal Oscillator

• Clock Switching with run from:

- Primary Oscillator

- Secondary Oscillator (SOSC)

- Internal Oscillator

- FSRs can read program and data memory

Special Microcontroller Features:

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF145X)

- 2.3V to 5.5V (PIC16F145X)

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Programmable Brown-Out Reset (BOR)

• Low-Power BOR (LPBOR)

• Extended Watchdog Timer (WDT):

- Programmable period from 1 ms to 256s

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via Two

Pins

• Clock Reference Output:

- Clock Prescaler

- CLKOUT

(1)

Analog Features :

• Analog-to-Digital Converter (ADC):

- 10-bit resolution

- Up to nine external channels

- Two internal channels:

- Fixed Voltage Reference channel

- DAC output channel

- Auto acquisition capability

- Conversion available during Sleep

• Two Comparators:

• Enhanced Low-Voltage Programming (LVP)

• Power-Saving Sleep mode:

- Rail-to-rail inputs

- Power mode control

- Software controllable hysteresis

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

• Up to One Rail-to-Rail Resistive 5-Bit DAC with

Positive Reference Selection

Universal Serial Bus (USB) Features:

• Self-Tuning from USB Host

(eliminates need for external crystal)

• USB V2.0 Compliant SIE

• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)

• Supports Control, Interrupt, Isochronous and Bulk

Transfers

• Supports up to Eight Bidirectional Endpoints

• 512-Byte Dual Access RAM for USB

• Interrupt-on-Change (IOC) on D+/D- for USB Host

Detection

Note 1: Analog features are not available on

PIC16(L)F1454 devices.

• Configurable Internal Pull-up Resistors for use

with USB

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 3

PIC16(L)F145X

Peripheral Features:

• Up to 14 I/O Pins and Three Input-only Pins:

- High current sink/source 25 mA/25 mA

- Individually programmable weak pull-ups

- Individually programmable

Interrupt-On-Change (IOC) pins

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

• Timer2: 8-Bit Timer/Counter with 8-Bit Period

Register, Prescaler and Postscaler

• Two 10-bit PWM modules

• Complementary Waveform Generator (CWG)⁽¹⁾

- Up to four selectable signal sources

- Selectable falling and rising edge dead-band

control

:

- Polarity control

- Up to four auto-shutdown sources

- Multiple input sources: PWM, Comparators

• Master Synchronous Serial Port (MSSP) with SPI

and I²C™ with:

- 7-bit address masking

- SMBus/PMBus™ compatibility

• Enhanced Universal Synchronous

Asynchronous Receiver Transmitter (EUSART):

- RS-232, RS-485 and LIN compatible

- Auto-baud detect

- Auto-wake-up on Start

Note 1: Not available on PIC16(L)F1454 devices.

PIC16(L)F145X Family Types

Device

PIC16(L)F1454 (1) 8192 1024 11

PIC16(L)F1455 (1) 8192 1024 11

PIC16(L)F1459 (1) 8192 1024 17

—

5

—

2

—

1

2/1

2

1

—

1

I/H

Y

9

2

1

Note 1: I - Debugging, Integrated on Chip; H - Debugging, Available using Debug Header;

E - Emulation, Available using Emulation Header.

2: Three pins are input-only.

Data Sheet Index:

1: DS41639 PIC16(L)F1454/1455/1459 Data Sheet, 14/20-Pin Flash, 8-Bit USB Microcontrollers.

Note:

For other small form-factor package availability and marking information, please visit

www.microchip.com/packaging or contact your local sales office.

DS41639A-page 4

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F145X

FIGURE 1:

14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1454/1455

PDIP, SOIC, TSSOP

VDD

RA5

1

VSS

14

13

12

11

10

9

RA0/D+/ICSPDAT⁽¹⁾

2

3

4

RA1/D-/ICSPCLK⁽¹⁾

RA4

MCLR/VPP/RA3

VUSB3V3

RC5

RC4

RC3

RC0/ICSPDAT

5

6

7

RC1/ICSPCLK

RC2

8

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Table 1 and Table 2 for location of all peripheral functions.

FIGURE 2:

QFN (4x4)

16-PIN QFN DIAGRAM FOR PIC16(L)F1454/1455

16 15 14 13

RA0/D+/ICSPDAT⁽¹⁾

RA5

RA4

1

12

RA1/D-/ICSPCLK⁽¹⁾

VUSB3V3

2

3

4

11

10

9

PIC16(L)F1454

PIC16(L)F1455

MCLR/VPP/RA3

RC5

RC0/ICSPDAT

5

6

7

8

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Table 1 and Table 2 for location of all peripheral functions.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 5

PIC16(L)F145X

FIGURE 3:

20-PIN PDIP, SOIC, SSOP DIAGRAM FOR PIC16(L)F1459

PDIP, SOIC, SSOP

VDD

1

VSS

20

19

18

RA0/D+/ICSPDAT⁽¹⁾

RA5

2

3

4

RA1/D-/ICSPCLK⁽¹⁾

RA4

17 VUSB3V3

MCLR/VPP/RA3

RC5

RC4

RC3

RC6

RC7

RB7

16

15

14

13

12

RC0/ICSPDAT

5

6

7

8

RC1/ICSPCLK

RC2

RB4

RB5

9

10

11 RB6

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Table 3 for location of all peripheral functions.

FIGURE 4:

20-PIN QFN DIAGRAM FOR PIC16(L)F1459

QFN (4x4)

20 19 18 17 16

15 RA1/D-/ICSPCLK⁽¹⁾

14

13 RC0/ICSPDAT

MCLR/VPP/RA3

1

2

3

4

5

RC5

RC4

RC3

VUSB3V3

PIC16(L)F1459

12

11

RC1/ICSPCLK

RC2

RC6

6

7 8 9 10

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Table 3 for location of all peripheral functions.

DS41639A-page 6

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F145X

TABLE 1:

14-PIN ALLOCATION TABLE (PIC16(L)F1454)

RA0

RA1

RA2

RA3

13

12

—

4

12

11

—

3

—

D+

D-

—

IOC

—

ICSPDAT⁽³⁾

ICSPCLK⁽³⁾

—

T1G⁽²⁾

—

SS⁽²⁾

IOC

MCLR

VPP

RA4

3

2

—

SOSCO

T1G⁽¹⁾

—

SDO⁽²⁾

IOC

CLKOUT

OSC2

CLKR⁽¹⁾

RA5

RC0

RC1

2

10

9

1

9

8

—

SOSCI

T1CKI

—

PWM2⁽²⁾

—

IOC

—

CLKIN

OSC1

—

SCL

SCK

ICSPDAT

—

SDA

SDI

INT

ICSPCLK

RC2

RC3

RC4

8

7

6

7

6

5

—

PWM2⁽¹⁾

—

SDO⁽¹⁾

SS⁽¹⁾

—

CLKR⁽²⁾

—

TK

CK

RC5

5

4

—

T0CKI

—

RX

DT

PWM1

—

VDD

VSS

1

16

13

10

—

VDD

VSS

—

14

VUSB3V3 11

VUSB3V3

Note 1:

Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

Alternate location for peripheral pin function selected by the APFCON register.

LVP support for PIC18(L)F1XK50 legacy designs.

2:

3:

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 7

PIC16(L)F145X

TABLE 2:

14-PIN ALLOCATION TABLE (PIC16(L)F1455)

RA0

RA1

RA2

RA3

13

12

—

4

12

11

—

3

—

D+

D-

—

IOC

—

ICSPDAT⁽³⁾

ICSPCLK⁽³⁾

—

T1G⁽²⁾

—

SS⁽²⁾

IOC

MCLR

VPP

RA4

3

2

AN3

—

SOSCO

T1G⁽¹⁾

—

SDO⁽²⁾

IOC

CLKOUT

OSC2

CLKR⁽¹⁾

RA5

RC0

RC1

RC2

RC3

RC4

RC5

2

10

9

1

9

8

7

6

5

4

—

AN4

AN5

AN6

AN7

—

VREF+

—

SOSCI

T1CKI

—

PWM2⁽²⁾

—

IOC

—

CLKIN

OSC1

C1IN+

C2IN+

—

SCL

SCK

ICSPDAT

ICSPCLK

—

C1IN1-

C2IN1-

—

CWGFLT

—

SDA

SDI

INT

—

8

DACOUT1

DACOUT2

—

C1IN2-

C2IN2-

—

SDO⁽¹⁾

SS⁽¹⁾

—

7

C1IN3-

C2IN3-

—

PWM2⁽¹⁾

—

CLKR⁽²⁾

—

6

C1OUT

C2OUT

—

CWG1B

CWG1A

TK

CK

—

5

—

T0CKI

RX

DT

PWM1

—

VDD

VSS

1

16

13

10

—

VDD

VSS

—

14

VUSB3V3 11

VUSB3V3

Note 1:

Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

Alternate location for peripheral pin function selected by the APFCON register.

LVP support for PIC18(L)F1XK50 legacy designs.

2:

3:

DS41639A-page 8

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F145X

TABLE 3:

20-PIN ALLOCATION TABLE (PIC16(L)F1459)

RA0

RA1

RA2

RA3

19

18

—

4

16

15

—

1

—

D+

D-

—

IOC

—

ICSPDAT⁽³⁾

ICSPCLK⁽³⁾

—

T1G⁽²⁾

—

SS⁽²⁾

IOC

MCLR

VPP

RA4

3

20

19

AN3

—

SOSCO

T1G⁽¹⁾

—

IOC

OSC2

CLKOUT

CLKR⁽¹⁾

RA5

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

2

—

SOSCI

T1CKI

—

IOC

—

OSC1

CLKIN

13

12

11

10

16

15

14

7

10 AN10

—

SDA

SDI

—

9

8

AN11

—

RX

DX

—

SCL

SCK

7

—

VREF+

—

TX

CK

—

13

12

11

4

AN4

AN5

AN6

AN7

—

C1IN+

C2IN+

—

ICSPDAT

ICSPCLK

—

C1IN1-

C2IN1-

—

CWGFLT

—

INT

—

DACOUT1

DACOUT2

—

C1IN2-

C2IN2-

—

C1IN3-

C2IN3-

—

CLKR⁽²⁾

—

6

3

C1OUT

C2OUT

—

CWG1B

CWG1A

—

5

2

—

T0CKI

PWM1

—

RC6

RC7

VDD

VSS

8

9

5

AN8

AN9

—

PWM2

—

SS⁽¹⁾

SDO

—

6

1

18

17

14

—

VDD

VSS

—

20

—

VUSB3V3 17

—

VUSB3V3

—

Note 1:

Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

Alternate location for peripheral pin function selected by the APFCON register.

LVP support for PIC18(L)F1XK50 legacy designs.

2:

3:

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 9

PIC16(L)F145X

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 21

3.0 Memory Organization................................................................................................................................................................. 23

4.0 Device Configuration .................................................................................................................................................................. 51

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 57

6.0 Resets ........................................................................................................................................................................................ 79

7.0 Reference Clock Module ............................................................................................................................................................ 87

8.0 Interrupts .................................................................................................................................................................................... 91

9.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 103

10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 107

11.0 Flash Program Memory Control ............................................................................................................................................... 112

12.0 I/O Ports ................................................................................................................................................................................... 129

13.0 Interrupt-On-Change ................................................................................................................................................................ 143

14.0 Fixed Voltage Reference (FVR) (PIC16(L)F1455/9 only)......................................................................................................... 149

15.0 Temperature Indicator Module (PIC16(L)F1455/9 only)........................................................................................................... 151

16.0 Analog-to-Digital Converter (ADC) Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 153

17.0 Digital-to-Analog Converter (DAC) Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 169

18.0 Comparator Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 173

19.0 Timer0 Module ......................................................................................................................................................................... 183

20.0 Timer1 Module with Gate Control............................................................................................................................................. 187

21.0 Timer2 Module ......................................................................................................................................................................... 199

22.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 203

23.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 257

24.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 287

25.0 Complementary Waveform Generator (CWG) Module

(PIC16(L)F1455/9 only)293

26.0 Universal Serial Bus (USB) ...................................................................................................................................................... 309

27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 337

28.0 Instruction Set Summary.......................................................................................................................................................... 339

29.0 Electrical Specifications............................................................................................................................................................ 353

30.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 383

31.0 Development Support............................................................................................................................................................... 385

32.0 Packaging Information.............................................................................................................................................................. 389

Appendix A: Data Sheet Revision History.......................................................................................................................................... 407

Index .................................................................................................................................................................................................. 409

The Microchip Web Site..................................................................................................................................................................... 415

Customer Change Notification Service .............................................................................................................................................. 415

Customer Support.............................................................................................................................................................................. 415

Reader Response .............................................................................................................................................................................. 416

Product Identification System............................................................................................................................................................. 417

DS41639A-page 10

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F145X

TO OUR VALUED CUSTOMERS

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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

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welcome your feedback.

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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 11

PIC16(L)F145X

NOTES:

DS41639A-page 12

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

1.0

DEVICE OVERVIEW

The PIC16(L)F1454/5/9 are described within this data

sheet. They are available in 14/20-pin packages.

Figure 1-1 shows

a

block diagram of the

PIC16(L)F1454/5/9 devices. Tables 1-2, 1-3 and 1-4

show the pinout descriptions.

Reference Table 1-1 for peripherals available per

device.

TABLE 1-1:

Peripheral

DEVICE PERIPHERAL SUMMARY

Analog-to-Digital Converter (ADC)

Clock Reference

●

Complementary Wave Generator (CWG)

Digital-to-Analog Converter (DAC)

Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter

(EUSART)

Fixed Voltage Reference (FVR)

Temperature Indicator

Universal Serial Bus (USB)

Comparators

●

C1

C2

●

Master Synchronous Serial Ports

MSSP1

●

PWM Modules

Timers

PWM1

PWM2

●

Timer0

Timer1

Timer2

●

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 13

PIC16(L)F1454/5/9

FIGURE 1-1:

PIC16(L)F1454/5/9 BLOCK DIAGRAM

Program

Flash Memory

RAM

Timing

Generation

OSC2/CLKOUT

PORTA

CPU

OSC1/CLKIN

INTRC

Oscillator

PORTB⁽²⁾

(Figure 2-1)

MCLR

PORTC

C1⁽¹⁾

C2⁽¹⁾

CWG1

(1)

Timer0

Timer1

PWM1

Timer2

PWM2

USB

CLKR

Temp.

Indicator⁽¹⁾

ADC

10-Bit⁽¹⁾

FVR⁽¹⁾

DAC⁽¹⁾

MSSP1

EUSART

Note 1:

2:

PIC16(L)F1455/9 only.

PIC16(L)F1459 only.

DS41639A-page 14

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 1-2:

PIC16(L)F1454 PINOUT DESCRIPTION

Input Output

Function

Name

Description

Type

(3)

RA0/D+/ICSPDAT

RA0

D+

TTL

XTAL

ST

CMOS General purpose I/O.

XTAL USB differential plus line.

CMOS ICSP™ Data I/O.

ICSPDAT

RA1

(3)

RA1/D-/ICSPCLK

TTL

XTAL

ST

CMOS General purpose I/O.

XTAL USB differential minus line.

D-

ICSPCLK

RA3

—

ICSP Programming Clock.

General purpose input with IOC and WPU.

Programming voltage.

(2)

RA3/VPP/T1G /SS /MCLR

TTL

HV

VPP

T1G

ST

Timer1 Gate input.

SS

ST

Slave Select input.

MCLR

RA4

ST

Master Clear with internal pull-up.

RA4/SOSCO/CLKOUT/

T1G /SDO /CLKR /OSC2

TTL

XTAL

—

CMOS General purpose I/O.

XTAL Secondary Oscillator Connection.

CMOS FOSC/4 output.

(1)

(2)

(1)

SOSCO

CLKOUT

T1G

ST

—

Timer1 Gate input.

SDO

—

CMOS SPI data output.

CLKR

OSC2

RA5

—

CMOS Clock reference output.

XTAL Primary Oscillator connection.

CMOS General purpose I/O.

XTAL

TTL

CMOS

XTAL

ST

RA5/CLKIN/SOSCI/T1CKI/

PWM2 /OSC1

(2)

CLKIN

SOSCI

T1CKI

PWM2

OSC1

RC0

—

External clock input (EC mode).

XTAL Secondary Oscillator Connection.

Timer1 clock input.

—

CMOS PWM output.

XTAL

TTL

XTAL Primary Oscillator Connection.

RC0/SCL/SCK/ICSPDAT

CMOS General purpose I/O.

2

SCL

I C

OD

I C™ clock.

SCK

ST

CMOS SPI clock.

ICSPDAT

RC1

CMOS ICSP™ Data I/O.

RC1/SDA/SDI/INT/ICSPCLK

TTL

CMOS General purpose I/O.

2

SDA

I C

OD

—

I C data input/output.

SPI data input.

SDI

CMOS

ST

INT

—

External input.

ICSPCLK

RC2

ST

—

ICSP Programming Clock.

(1)

RC2/SDO

TTL

—

CMOS General purpose I/O.

CMOS SPI data output.

CMOS General purpose I/O.

CMOS PWM output.

SDO

(1)

(2)

RC3/PWM2 /SS /CLKR

RC3

TTL

—

PWM2

SS

ST

—

Slave Select input.

CLKR

—

CMOS Clock reference output.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

3: LVP support for PIC18(L)F1XK50 legacy designs.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 15

PIC16(L)F1454/5/9

TABLE 1-2:

PIC16(L)F1454 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

RC4/TX/CK

RC4

TX

TTL

—

CMOS General purpose I/O.

CMOS USART asynchronous transmit.

CMOS USART synchronous clock.

CMOS General purpose I/O.

CK

ST

RC5/T0CKI/RX/DT/PWM1

RC5

T0CKI

RX

TTL

ST

—

Timer0 clock input.

ST

USART asynchronous input.

DT

ST

CMOS USART synchronous data.

CMOS PWM output.

PWM1

VDD

—

VDD

Power

—

Positive supply.

VSS

Ground reference.

VUSB3V3

Positive supply for USB transceiver.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

3: LVP support for PIC18(L)F1XK50 legacy designs.

DS41639A-page 16

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 1-3:

PIC16(L)F1455 PINOUT DESCRIPTION

Input Output

Function

Name

Description

Type

(3)

RA0/D+/ICSPDAT

RA0

D+

TTL

XTAL

ST

CMOS General purpose I/O.

XTAL USB differential plus line.

CMOS ICSP™ Data I/O.

ICSPDAT

RA1

(3)

RA1/D-/ICSPCLK

TTL

XTAL

ST

CMOS General purpose I/O.

XTAL USB differential minus line.

D-

ICSPCLK

RA3

—

ICSP Programming Clock.

General purpose input with IOC and WPU.

Programming voltage.

(2)

RA3/VPP/T1G /SS /MCLR

TTL

HV

VPP

T1G

ST

Timer1 Gate input.

SS

ST

Slave Select input.

MCLR

RA4

ST

Master Clear with internal pull-up.

RA4/AN3/SOSCO/CLKOUT/

T1G /SDO /CLKR /OSC2

TTL

AN

CMOS General purpose I/O.

A/D Channel input.

(1)

(2)

(1)

AN3

—

SOSCO

CLKOUT

T1G

XTAL

—

XTAL Secondary Oscillator Connection.

CMOS FOSC/4 output.

ST

—

Timer1 Gate input.

SDO

—

CMOS SPI data output.

CLKR

OSC2

RA5

—

CMOS Clock reference output.

XTAL Primary Oscillator connection.

CMOS General purpose I/O.

XTAL

TTL

CMOS

XTAL

ST

RA5/CLKIN/SOSCI/T1CKI/

PWM2 /OSC1

(2)

CLKIN

SOSCI

T1CKI

PWM2

OSC1

RC0

—

External clock input (EC mode).

XTAL Secondary Oscillator Connection.

Timer1 clock input.

—

CMOS PWM output.

XTAL

TTL

AN

XTAL Primary Oscillator Connection.

CMOS General purpose I/O.

RC0/AN4/VREF+/C1IN+/C2IN+/

SCL/SCK/ICSPDAT

AN4

—

A/D Channel input.

VREF+

C1IN+

C2IN+

SCL

AN

Positive Voltage Reference input.

Comparator positive input.

AN

—

AN

—

2

I C

OD

I C™ clock.

SCK

ST

CMOS SPI clock.

ICSPDAT

CMOS ICSP™ Data I/O.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

3: LVP support for PIC18(L)F1XK50 legacy designs.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 17

PIC16(L)F1454/5/9

TABLE 1-3:

PIC16(L)F1455 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

RC1/AN5/C1IN1-/

C2IN1-/CWGFLT/SDA/

SDI/INT/ICSPCLK

RC1

AN5

TTL

AN

ST

CMOS General purpose I/O.

—

OD

—

A/D Channel input.

C1IN1-

C2IN1-

CWGFLT

SDA

Comparator negative input.

Complementary Waveform Generator Fault input.

2

I C

I C™ data input/output.

SDI

CMOS

ST

SPI data input.

INT

External input.

ICSPCLK

RC2

ST

ICSP™ Programming Clock.

RC2/AN6/DACOUT1/

C1IN2-/C2IN2-/SDO

TTL

AN

—

CMOS General purpose I/O.

(1)

AN6

—

AN

—

A/D Channel input.

DACOUT1

C1IN2-

C2IN2-

SDO

Digital-to-Analog Converter output.

Comparator negative input.

AN

—

CMOS SPI data output.

RC3/AN7/DACOUT2/

RC3

TTL

AN

—

CMOS General purpose I/O.

(1)

C1IN3-/C2IN3-/PWM2

/

AN7

—

AN

—

A/D Channel input.

(1)

(2)

SS /CLKR

DACOUT2

C1IN3-

C2IN3-

PWM2

CLC2IN0

CLKR

RC4

Digital-to-Analog Converter output.

Comparator negative input.

AN

—

CMOS PWM output.

ST

—

Configurable Logic Cell source input.

—

CMOS Clock reference output.

CMOS General purpose I/O.

CMOS Comparator output.

CMOS CWG complementary output.

CMOS USART asynchronous transmit.

CMOS USART synchronous clock.

CMOS General purpose I/O.

RC4/C1OUT/C2OUT/

CWG1B/TX/CK

TTL

—

C1OUT

C2OUT

CWG1B

TX

—

CK

ST

RC5/T0CKI/CWG1A/RX/DT/

PWM1

RC5

TTL

ST

T0CKI

CWG1A

RX

—

Timer0 clock input.

CMOS CWG complementary output.

USART asynchronous input.

—

ST

—

DT

ST

CMOS USART synchronous data.

CMOS PWM output.

PWM1

VDD

—

VDD

Power

—

Positive supply.

VSS

Ground reference.

VUSB3V3

Positive supply for USB transceiver.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

3: LVP support for PIC18(L)F1XK50 legacy designs.

DS41639A-page 18

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 1-4:

PIC16(L)F1459 PINOUT DESCRIPTION

Input Output

Function

Name

Description

Type

(3)

RA0/D+/ICSPDAT

RA0

D+

TTL

XTAL

ST

CMOS General purpose I/O.

XTAL USB differential plus line.

CMOS ICSP™ Data I/O.

ICSPDAT

RA1

(3)

RA1/D-/ICSPCLK

TTL

XTAL

ST

CMOS General purpose I/O.

XTAL USB differential minus line.

D-

ICSPCLK

RA3

—

ICSP Programming Clock.

General purpose input with IOC and WPU.

Programming voltage.

(2)

RA3/VPP/T1G /SS /MCLR

TTL

HV

VPP

T1G

ST

Timer1 Gate input.

SS

ST

Slave Select input.

MCLR

RA4

ST

Master Clear with internal pull-up.

RA4/AN3/SOSCO/CLKOUT/

T1G /CLKR /OSC2

TTL

AN

CMOS General purpose I/O.

A/D Channel input.

(1)

AN3

—

SOSCO

CLKOUT

T1G

XTAL

—

XTAL Secondary Oscillator Connection.

CMOS FOSC/4 output.

ST

—

Timer1 Gate input.

CLKR

OSC2

RA5

—

CMOS Clock reference output.

XTAL Primary Oscillator connection.

CMOS General purpose I/O.

XTAL

TTL

CMOS

XTAL

ST

RA5/CLKIN/SOSCI/T1CKI/

OSC1

CLKIN

SOSCI

T1CKI

OSC1

RB4

—

External clock input (EC mode).

XTAL Secondary Oscillator Connection.

Timer1 clock input.

—

XTAL

TTL

AN

XTAL Primary Oscillator Connection.

CMOS General purpose I/O.

RB4/AN10/SDA/SDI

RB5/AN11/RX/DT

AN10

SDA

—

OD

—

A/D Channel input.

2

I C

I C data input/output.

SDI

CMOS

TTL

AN

SPI data input.

RB5

CMOS General purpose I/O.

AN11

RX

—

A/D Channel input.

ST

USART asynchronous input.

DT

ST

CMOS USART synchronous data.

RB6/SCL/SCK

RB7/TX/CK

RB6

TTL

CMOS General purpose I/O.

2

SCL

I C

OD

I C™ clock.

SCK

ST

TTL

—

CMOS SPI clock.

RB7

CMOS General purpose I/O.

CMOS USART asynchronous transmit.

CMOS USART synchronous clock.

TX

CK

ST

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

3: LVP support for PIC18(L)F1XK50 legacy designs.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 19

PIC16(L)F1454/5/9

TABLE 1-4:

PIC16(L)F1459 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

RC0/AN4/VREF+/C1IN+/C2IN+/

ICSPDAT

RC0

AN4

TTL

AN

ST

CMOS General purpose I/O.

—

A/D Channel input.

VREF+

C1IN+

C2IN+

ICSPDAT

RC1

Positive Voltage Reference input.

Comparator positive input.

CMOS ICSP™ Data I/O.

RC1/AN5/C1IN1-/C2IN1-/

CWGFLT/INT/ICSPCLK

TTL

AN

ST

CMOS General purpose I/O.

AN5

—

A/D Channel input.

C1IN1-

C2IN1-

CWGFLT

INT

Comparator negative input.

Complementary Waveform Generator Fault input.

External input.

ST

ICSPCLK

RC2

ST

ICSP Programming Clock.

RC2/AN6/DACOUT1/

C1IN2-/C2IN2-

TTL

AN

—

CMOS General purpose I/O.

AN6

—

AN

—

A/D Channel input.

DACOUT1

C1IN2-

C2IN2-

RC3

Digital-to-Analog Converter output.

Comparator negative input.

AN

TTL

AN

—

RC3/AN7/DACOUT2/

C1IN3-/C2IN3-/CLKR

CMOS General purpose I/O.

(2)

AN7

—

AN

—

A/D Channel input.

DACOUT2

C1IN3-

C2IN3-

CLKR

RC4

Digital-to-Analog Converter output.

Comparator negative input.

AN

—

CMOS Clock reference output.

CMOS General purpose I/O.

CMOS Comparator output.

CMOS CWG complementary output.

CMOS General purpose I/O.

RC4/C1OUT/C2OUT/

CWG1B

TTL

—

C1OUT

C2OUT

CWG1B

RC5

—

RC5/T0CKI/CWG1A/PWM1

TTL

ST

T0CKI

CWG1A

PWM1

RC6

—

Timer0 clock input.

—

CMOS CWG complementary output.

CMOS PWM output.

—

(1)

RC6/AN8/SS /PWM2

TTL

AN

ST

CMOS General purpose I/O.

AN8

—

A/D Channel input.

Slave Select input.

SS

PWM2

RC7

—

CMOS PWM output.

RC7/AN9/SDO

TTL

AN

—

CMOS General purpose I/O.

AN9

—

A/D Channel input.

SDO

CMOS SPI data output.

VDD

Power

—

Positive supply.

VSS

Ground reference.

VUSB3V3

Positive supply for USB transceiver.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.

3: LVP support for PIC18(L)F1XK50 legacy designs.

DS41639A-page 20

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Relative Addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read

program and data memory.

2.0

ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

FIGURE 2-1:

CORE BLOCK DIAGRAM

15

Configuration

15

8

Data Bus

Program Counter

Flash

Program

Memory

186-LLeevveellSStatacckk

(153-bit)

RAM

Program

Bus

14

RAM Addr

Program Memory

Read (PMR)

12

Addr MUX

IInnssttrruuccttiioonnRreegg

Indirect

Addr

7

Direct Addr

12

5

BSR Reg

FSR reg

15

FSR0 Reg

reg

FSR1 Reg

FSR reg

15

SSTTAATTUUSSRreegg

8

3

MUX

Power-up

Timer

Instruction

DDeeccooddeea&nd

Control

ALU

Power-on

Reset

OSC1/CLKIN

8

Watchdog

Timer

Timing

Generation

W Reg

OSC2/CLKOUT

Brown-out

Reset

Internal

Oscillator

Block

VDD

VSS

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 21

PIC16(L)F1454/5/9

2.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 8.5 “Automatic Context Saving”,

for more information.

2.2

16-Level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Under-

flow will set the appropriate bit (STKOVF or STKUNF)

in the PCON register, and if enabled will cause a soft-

ware Reset. See section Section 3.5 “Stack” for more

details.

2.3

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.6 “Indirect Addressing” for more details.

2.4

Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 28.0 “Instruction Set Summary” for more

details.

DS41639A-page 22

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

The following features are associated with access and

control of program memory and data memory:

3.0

MEMORY ORGANIZATION

These devices contain the following types of memory:

• PCL and PCLATH

• Stack

• Program Memory

- Configuration Words

- Device ID

• Indirect Addressing

- User ID

3.1

Program Memory Organization

- Flash Program Memory

• Data Memory

The enhanced mid-range core has a 15-bit program

counter capable of addressing a 32K x 14 program

memory space. Table 3-1 shows the memory sizes

- Core Registers

- Special Function Registers

- Dual-Port General Purpose RAM

- General Purpose RAM

- Common RAM

implemented. Accessing

boundaries will cause

implemented memory space. The Reset vector is at

0000h and the interrupt vector is at 0004h (See

Figure 3-1).

a

location above these

wrap-around within the

a

TABLE 3-1:

Device

DEVICE SIZES AND ADDRESSES

Program Memory

Space (Words)

Last Program Memory

Address

High-Endurance Flash

Memory Address Range ⁽¹⁾

PIC16F1454

PIC16LF1454

8,192

1FFFh

1F80h-1FFFh

PIC16F1455

PIC16LF1455

PIC16F1459

PIC16LF1459

Note 1: High-endurance Flash applies to low byte of each address in the range.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 23

PIC16(L)F1454/5/9

FIGURE 3-1:

PROGRAM MEMORY MAP

AND STACK FOR

3.1.1

READING PROGRAM MEMORY AS

DATA

PIC16(L)F1454/5/9

There are two methods of accessing constants in pro-

gram memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

PC<14:0>

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

15

3.1.1.1

RETLWInstruction

The RETLWinstruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

EXAMPLE 3-1:

constants

BRW

RETLW INSTRUCTION

;Add Index in W to

;program counter to

;select data

0000h

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

;Index0 data

;Index1 data

Interrupt Vector

Page 0

0004h

0005h

07FFh

0800h

my_function

Page 1

Page 2

On-chip

Program

Memory

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

0FFFh

1000h

;… THE CONSTANT IS IN W

17FFh

1800h

The BRWinstruction makes this type of table very sim-

ple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRWinstruction is not available so the older table read

method must be used.

Page 3

1FFFh

2000h

Rollover to Page 0

Rollover to Page 3

7FFFh

DS41639A-page 24

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

3.1.1.2

Indirect Read with FSR

The program memory can be accessed as data by set-

ting bit 7 of the FSRxH register and reading the match-

ing INDFx register. The MOVIWinstruction will place the

lower eight bits of the addressed word in the W register.

Writes to the program memory cannot be performed via

the INDF registers. Instructions that access the pro-

gram memory via the FSR require one extra instruction

cycle to complete. Example 3-2 demonstrates access-

ing the program memory via an FSR.

The High directive will set bit<7> if a label points to a

location in program memory.

EXAMPLE 3-2:

ACCESSING PROGRAM

MEMORY VIA FSR

constants

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

my_function

;Index0 data

;Index1 data

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 25

PIC16(L)F1454/5/9

3.2.1

CORE REGISTERS

3.2

Data Memory Organization

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in Table 3-2. For detailed

information, see Table 3-11.

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

TABLE 3-2:

CORE REGISTERS

• Up to 80 bytes of Dual-Port General Purpose

RAM (DPR)

• 16 bytes of common RAM

Addresses

BANKx

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

x00h or x80h

x01h or x81h

x02h or x82h

x03h or x83h

x04h or x84h

x05h or x85h

x06h or x86h

x07h or x87h

x08h or x88h

x09h or x89h

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

Data memory uses a 12-bit address. The upper 7-bits

of the address define the Bank address and the lower

5-bits select the registers/RAM in that bank.

WREG

PCLATH

INTCON

x0Ah or x8Ah

x0Bh or x8Bh

DS41639A-page 26

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u= unchanged).

3.2.1.1

STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 28.0

“Instruction Set Summary”).

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

3.3

Register Definitions: Status

REGISTER 3-1:

STATUS: STATUS REGISTER

U-0

—

U-0

—

U-0

—

R-1/q

TO

R-1/q

PD

R/W-0/u

Z

R/W-0/u

DC⁽¹⁾

R/W-0/u

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-5

bit 4

Unimplemented: Read as ‘0’

TO: Time-Out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

bit 3

bit 2

bit 1

bit 0

PD: Power-Down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 27

PIC16(L)F1454/5/9

3.3.1

SPECIAL FUNCTION REGISTER

3.3.3

DUAL-PORT RAM

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch

through x1Fh/x9Fh). The registers associated with the

operation of the peripherals are described in the appro-

priate peripheral chapter of this data sheet.

Part of the data memory is mapped to a special dual

access RAM. When the USB module is disabled, the

GPRs in these banks are used like any other GPR in

the data memory space.

When the USB module is enabled, the memory in these

banks is allocated as buffer RAM for USB operation.

This area is shared between the microcontroller core

and the USB Serial Interface Engine (SIE) and is used

to transfer data directly between the two.

3.3.2

GENERAL PURPOSE RAM

It is theoretically possible to use the areas of USB RAM

that are not allocated as USB buffers for normal

scratchpad memory or other variable storage. In practice,

the dynamic nature of buffer allocation makes this risky at

best. Additional information on USB RAM and buffer

operation is provided in Section 26.0 “Universal Serial

Bus (USB)”.

There are up to 80 bytes of GPR in each data memory

bank. The Special Function Registers occupy the 20

bytes after the core registers of every data memory

bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1

Linear Access to GPR

The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section 3.6.2

“Linear Data Memory” for more information.

3.3.4

COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

Refer to Table 3-3 for Dual Port and USB addressing

information.

TABLE 3-3:

DUAL PORT RAM ADDRESSING

Port 0

Port 1

CPU Banked Address

CPU Linear Address

USB Banked Address

USB Linear Address

020 - 06F

0A0 - 0EF

120 - 16F

1A0 - 1EF

220 - 26F

2A0 - 2EF

320 - 32F

370 - 37F

2000 - 204F

2050 - 209F

20A0 - 20EF

20F0 - 213F

2140 - 218F

2190 - 21DF

21E0 - 21EF

(1)

020 - 06F

0A0 - 0EF

120 - 16F

1A0 - 1EF

220 - 26F

2A0 - 2EF

320 - 32F

370 - 37F

2000 - 204F

2050 - 209F

20A0 - 20EF

20F0 - 213F

2140 - 218F

2190 - 21DF

21E0 - 21EF

(1)

Note 1: Accessible from banked memory only.

DS41639A-page 28

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 3-2:

BANKED MEMORY

PARTITIONING

3.3.5

DEVICE MEMORY MAPS

The memory maps for PIC16(L)F1454/5/9 are as

shown in Table 3-8 and Table 3-9.

Memory Region

7-bit Bank Offset

00h

Core Registers

(12 bytes)

0Bh

0Ch

Special Function Registers

(20 bytes maximum)

1Fh

20h

(1)

Dual Port RAM

(80 bytes maximum)

OR

General Purpose RAM

(80 bytes maximum)

6Fh

70h

Common RAM

(16 bytes)

7Fh

Note 1: If the USB module is disabled, data

memory is GPR. If enabled, data

memory can be DPR. Refer to Mem-

ory Map for RAM type details.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 29

PIC16(L)F1454/5/9

TABLE 3-10: PIC16(L)F1454/5/9 MEMORY

MAP, BANK 30-31

Bank 31

F8Ch

Unimplemented

Read as ‘0’

FE3h

STATUS_SHAD

WREG_SHAD

BSR_SHAD

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

FECh

FEDh

FEEh

FEFh

PCLATH_SHAD

FSR0L_SHAD

FSR0H_SHAD

FSR1L_SHAD

FSR1H_SHAD

—

STKPTR

TOSL

TOSH

Legend:

= Unimplemented data memory locations,

read as ‘0’.

DS41639A-page 36

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

3.3.6

CORE FUNCTION REGISTERS

SUMMARY

The Core Function registers listed in Table 3-11 can be

addressed from any Bank.

TABLE 3-11: CORE FUNCTION REGISTERS SUMMARY

Value on

POR, BOR other Resets

Value on all

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0-31

x00h or

x80h

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

INDF0

INDF1

PCL

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 0000 0000 0000

x01h or

x81h

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

x02h or

x82h

Program Counter (PC) Least Significant Byte

x03h or

x83h

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

x04h or

x84h

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

x05h or

x85h

x06h or

x86h

x07h or

x87h

x08h or

x88h

—

BSR<4:0>

x09h or

x89h

WREG

PCLATH

INTCON

Working Register

x0Ahor

x8Ah

—

Write Buffer for the upper 7 bits of the Program Counter

PEIE TMR0IE INTE IOCIE TMR0IF

x0Bhor

x8Bh

GIE

INTF

IOCIF

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 37

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY

Value on all

other

Resets

Addres

s

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0

00Ch

PORTA

—

RA5

RB5

RC5

RA4

RB4

RC4

RA3

—

RA1

—

RA0

—

--xx x-xx --xx x-xx

xxxx ---- xxxx ----

xxxx xxxx xxxx xxxx

00Dh

00Eh

00Fh

010h

011h

012h

013h

014h

015h

016h

017h

018h

019h

PORTB⁽¹⁾

PORTC

—

RB7

RC7⁽¹⁾

RB6

RC6⁽¹⁾

RC3

RC2

RC1

RC0

Unimplemented

TMR1GIF

—

PIR1

ADIF

C2IF

RCIF

C1IF

TXIF

—

SSP1IF

BCL1IF

—

TMR2IF

ACTIF

TMR1IF

—

0000 0-00 0000 0-00

000- 000- 000- 000-

PIR2

OSFIF

USBIF

—

Unimplemented

—

TMR0

TMR1L

TMR1H

T1CON

T1GCON

Holding Register for the 8-bit Timer0 Count

xxxx xxxx uuuu uuuu

0000 00-0 uuuu uu-u

0000 0x00 uuuu uxuu

Holding Register for the Least Significant Byte of the 16-bit TMR1 Count

Holding Register for the Most Significant Byte of the 16-bit TMR1 Count

TMR1CS<1:0>

TMR1GE T1GPOL

T1CKPS<1:0>

T1GTM T1GSPM

T1OSCEN T1SYNC

—

TMR1ON

T1GGO/

DONE

T1GVAL

T1GSS<1:0>

01Ah

01Bh

01Ch

01Dh

01Eh

01Fh

TMR2

PR2

T2CON

—

Timer2 Module Register

Timer2 Period Register

—

0000 0000 0000 0000

1111 1111 1111 1111

-000 0000 -000 0000

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

Unimplemented

—

Bank 1

(2)

08Ch

08Dh

08Eh

08Fh

090h

091h

092h

093h

094h

095h

096h

097h

098h

099h

09Ah

09Bh

09Ch

09Dh

09Eh

09Fh

TRISA

TRISB⁽¹⁾

—

TRISA5

TRISA4

TRISB4

TRISC4

—

--11 ---- --11 ----

1111 ---- 1111 ----

1111 1111 1111 1111

TRISB7

TRISC7⁽¹⁾TRISC6⁽¹⁾

TRISB6

TRISB5

TRISC5

—

TRISC

TRISC3

TRISC2

TRISC1

TRISC0

—

Unimplemented

—

Unimplemented

PIE1

TMR1GIE

ADIE

C2IE

RCIE

C1IE

TXIE

—

SSP1IE

BCL1IE

—

TMR2IE

ACTIE

TMR1IE

—

0000 0-00 0000 0-00

000- 000- 000- 000-

PIE2

OSFIE

USBIE

—

Unimplemented

—

OPTION_REG

PCON

WPUEN

STKOVF

—

INTEDG

STKUNF

—

TMR0CS

—

TMR0SE

RWDT

PSA

PS<2:0>

POR

1111 1111 1111 1111

00-1 11qq qq-q qquu

--01 0110 --01 0110

-000 0000 -uuu uuuu

0011 1100 0011 1100

00q0 --00 qqqq --qq

xxxx xxxx uuuu uuuu

-000 0000 -000 0000

0000 --00 0000 --00

-000 ---- -000 ----

RMCLR

RI

—

BOR

WDTCON

OSCTUNE

OSCCON

OSCSTAT

ADRESL⁽²⁾

ADRESH⁽²⁾

ADCON0⁽²⁾

ADCON1⁽²⁾

ADCON2⁽²⁾

WDTPS<4:0>

TUN<6:0>

SWDTEN

—

SPLLEN SPLLMULT

SOSCR PLLRDY

IRCF<3:0>

SCS<1:0>

OSTS

HFIOFR

—

LFIOFR

HFIOFS

A/D Result Register Low

A/D Result Register High

—

CHS<4:0>

GO/DONE

—

ADON

ADFM

ADCS<2:0>

—

ADPREF<1:0>

—

TRIGSEL<2:0>

—

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

Note 1:

PIC16(L)F1459 only.

2:

3:

PIC16(L)F1455/9 only.

Unimplemented, read as ‘1’.

DS41639A-page 38

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Addres

s

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 2

10Ch

10Dh

10Eh

10Fh

110h

111h

LATA

LATB⁽¹⁾

—

LATA5

LATB5

LATC5

LATA4

LATB4

LATC4

—

--xx ---- --uu ----

xxxx ---- uuuu ----

xxxx xxxx uuuu uuuu

LATB7

LATC7⁽¹⁾

LATB6

LATC6⁽¹⁾

LATC

LATC3

LATC2

LATC1

LATC0

—

Unimplemented

—

CM1CON0⁽²⁾

CM1CON1⁽²⁾

CM2CON0⁽²⁾

CM2CON1⁽²⁾

CMOUT⁽²⁾

BORCON

FVRCON⁽²⁾

DACCON0⁽²⁾

DACCON1⁽²⁾

C1ON

C1INTP

C2ON

C2INTP

—

C1OUT

C1OE

C1POL

C2POL

—

C1SP

C2SP

C1HYS

C1NCH<2:0>

C2HYS

C1SYNC

C2SYNC

0000 -100 0000 -100

0000 -000 0000 -000

0000 -100 0000 -100

0000 -000 0000 -000

---- --00 ---- --00

10-- ---q uu-- ---u

0q00 0000 0q00 0000

0-00 00-- 0-00 00--

---0 0000 ---0 0000

112h

113h

114h

115h

116h

117h

118h

119h

C1INTN

C2OUT

C2INTN

—

C1PCH<1:0>

C2OE

C2PCH<1:0>

C2NCH<2:0>

MC2OUT

—

MC1OUT

BORRDY

SBOREN

FVREN

DACEN

—

BORFS

FVRRDY

—

TSEN

DACOE1

—

TSRNG

DACOE2

CDAFVR<1:0>

DACPSS<1:0>

DACR<4:0>

ADFVR<1:0>

—

11Ah

to

—

Unimplemented

—

11Ch

11Dh

APFCON

CLKRSEL SDOSEL⁽¹⁾

SSSEL

T1GSEL

P2SEL⁽¹⁾

000- --00 000- --00

—

11Eh

11Fh

Bank 3

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

—

Unimplemented

—

ANSELA⁽²⁾

ANSELB⁽¹⁾

ANSELC⁽²⁾

—

ANSB5

—

ANSA4

ANSB4

—

---1 ---- ---1 ----

--11 ---- --11 ----

11-- 1111 11-- 1111

ANSC7⁽¹⁾ANSC6⁽¹⁾

ANSC3

ANSC2

ANSC1

ANSC0

Unimplemented

—

Unimplemented

PMADRL

PMADRH

PMDATL

PMDATH

PMCON1

PMCON2

VREGCON⁽¹⁾

—

Flash Program Memory Address Register Low Byte

0000 0000 0000 0000

1000 0000 1000 0000

xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

1000 x000 1000 q000

0000 0000 0000 0000

---- --01 ---- --01

(2)

—

Flash Program Memory Address Register High Byte

Flash Program Memory Read Data Register Low Byte

—

Flash Program Memory Read Data Register High Byte

(2)

—

CFGS

LWLO

FREE

WRERR

WREN

WR

RD

Flash Program Memory Control Register 2

—

VREGPM

Reserved

Unimplemented

—

RCREG

TXREG

USART Receive Data Register

0000 0000 0000 0000

0000 000x 0000 000x

0000 0010 0000 0010

01-0 0-00 01-0 0-00

USART Transmit Data Register

SPBRGL

SPBRGH

RCSTA

Baud Rate Generator Data Register Low

Baud Rate Generator Data Register High

SPEN

CSRC

RX9

TX9

SREN

TXEN

—

CREN

SYNC

SCKP

ADDEN

SENDB

BRG16

FERR

BRGH

—

OERR

TRMT

WUE

RX9D

TX9D

TXSTA

BAUDCON

ABDOVF

RCIDL

ABDEN

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

Note 1:

PIC16(L)F1459 only.

2:

3:

PIC16(L)F1455/9 only.

Unimplemented, read as ‘1’.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 39

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Addres

s

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 4

20Ch

20Dh

20Eh

WPUA

WPUB⁽¹⁾

—

WPUA5

WPUB5

WPUA4

WPUB4

WPUA3

—

--11 1--- --11 1---

1111 ---- 1111 ----

WPUB7

WPUB6

to

—

Unimplemented

—

210h

211h

SSP1BUF

SSP1ADD

SSP1MSK

SSP1STAT

SSP1CON1

SSP1CON2

SSP1CON3

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

212h

213h

214h

215h

216h

217h

ADD<7:0>

MSK<7:0>

SMP

WCOL

GCEN

ACKTIM

CKE

SSPOV

ACKSTAT

PCIE

D/A

P

S

R/W

UA

BF

SSPEN

ACKDT

SCIE

CKP

SSPM<3:0>

ACKEN

BOEN

RCEN

PEN

RSEN

AHEN

SEN

SDAHT

SBCDE

DHEN

218h

to

21Fh

—

Unimplemented

—

Bank 5

28Ch

to

29Fh

Bank 6

30Ch

to

31Fh

Bank 7

38Ch

to

390h

391h

IOCAP

—

IOCAP5

IOCAN5

IOCAF5

IOCBP5

IOCBN5

IOCBF5

IOCAP4

IOCAN4

IOCAF4

IOCBP4

IOCBN4

IOCBF4

IOCAP3

IOCAN3

IOCAF3

—

IOCAP1

IOCAN1

IOCAF1

—

IOCAP0

IOCAN0

IOCAF0

—

--00 0-00 --00 0-00

0000 ---- 0000 ----

392h

393h

394h

395h

396h

IOCAN

IOCAF

IOCBP⁽¹⁾

IOCBN⁽¹⁾

IOCBF⁽¹⁾

IOCBP7

IOCBN7

IOCBF7

IOCBP6

IOCBN6

IOCBF6

—

397h

to

—

Unimplemented

—

399h

39Ah

39Bh

39Ch

CLKRCON

ACTCON

CLKREN

ACTEN

CLKROE CLKRSLR

ACTUD

CLKRDC<1:0>

ACTSRC ACTLOCK

CLKRDIV<2:0>

ACTORS

0011 0000 0011 0000

00-0 0-0- 00-0 0-0-

—

to

39Fh

—

Unimplemented

—

Bank 8

40Ch

to

41Fh

Bank 9

48Ch

to

49Fh

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

Note 1:

PIC16(L)F1459 only.

2:

3:

PIC16(L)F1455/9 only.

Unimplemented, read as ‘1’.

DS41639A-page 40

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Addres

s

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 10

50Ch

to

51Fh

—

Unimplemented

—

Bank 11

58Ch

to

59Fh

—

Bank 12

60Ch

to

—

610h

611h

PWM1DCL

PWM1DCH

PWM1CON0

PWM2DCL

PWM2DCH

PWM2CON0

PWM1DCL<7:6>

—

00-- ---- 00-- ----

xxxx xxxx uuuu uuuu

0000 ---- 0000 ----

00-- ---- 00-- ----

xxxx xxxx uuuu uuuu

0000 ---- 0000 ----

612h

613h

614h

615h

616h

PWM1DCH<7:0>

PWM1EN PWM1OE PWM1OUT PWM1POL

PWM2DCL<7:6>

—

PWM2DCH<7:0>

PWM2EN PWM2OE PWM2OUT PWM2POL

—

617h

to

—

Unimplemented

—

61Fh

Bank 13

68Ch

to

—

Unimplemented

—

690h

691h

CWG1DBR⁽²⁾

CWG1DBF⁽²⁾

CWG1CON0⁽²⁾

CWG1CON1⁽²⁾

CWG1CON2⁽²⁾

—

CWG1DBR<5:0>

CWG1DBF<5:0>

--00 0000 --00 0000

--xx xxxx --xx xxxx

0000 0--0 0000 0--0

0000 --00 0000 --00

00-- 0001 00-- 000-

692h

693h

694h

695h

G1EN

G1OEB

G1OEA

G1POLB

—

G1POLA

—

G1CS0

—

G1ASDLB<1:0>

G1ASE G1ARSEN

G1ASDLA<1:0>

—

G1IS<1:0>

—

G1ASDC2 G1ASDC1 G1ASDSFLT

696h

to

—

Unimplemented

—

69Fh

Banks 14-28

x0Ch/

—

Unimplemented

—

x8Ch

—

x1Fh/

x9Fh

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

Note 1:

PIC16(L)F1459 only.

2:

3:

PIC16(L)F1455/9 only.

Unimplemented, read as ‘1’.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 41

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Addres

s

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 29

E8Ch

—

Unimplemented

—

E8Dh

E8Eh

—

-0x0 000- -0u0 000-

-xxx xxx- -uuu uuu-

-000 0000 -000 0000

00-0 -000 00-0 -000

-000 0000 -000 0000

0--0 -000 0--0 -000

---- -xxx ---- -uuu

xxxx xxxx uuuu uuuu

-000 0000 -000 0000

0--0 0000 0--0 0000

---0 0000 ---0 0000

UCON

USTAT

UIR

PPBRST

SE0

PKTDIS

USBEN

RESUME

DIR

SUSPND

PPBI

E8Fh

E90h

E91h

E92h

E93h

E94h

E95h

E96h

E97h

E98h

E99h

E9Ah

E9Bh

E9Ch

E9Dh

E9Eh

E9Fh

—

ENDP<3:0>

SOFIF

STALLIF

—

IDLEIF

UPUEN

IDLEIE

TRNIF

Reserved

TRNIE

ACTVIF

FSEN

UERRIF

URSTIF

UCFG

UIE

UTEYE

—

Reserved

PPB<1:0>

SOFIE

—

STALLIE

—

ACTVIE

UERRIE

CRC5EF

FRM9

URSTIE

PIDEF

UEIR

BTSEF

—

BTOEF

—

DFN8EF CRC16EF

—

UFRMH

UFRML

UADDR

UEIE

FRM10

FRM8

FRM7

—

FRM6

FRM5

FRM4

ADDR4

BTOEE

EPHSHK

FRM3

FRM2

FRM1

FRM0

ADDR6

—

ADDR5

—

ADDR3

ADDR2

ADDR1

CRC5EE

EPINEN

ADDR0

BTSEE

–

DFN8EE CRC16EE

EPCONDIS

PIDEE

–

UEP7

UEP6

UEP5

UEP4

UEP3

UEP2

UEP1

UEP0

EPOUTEN

EPSTALL

–

EPHSHK EPCONDIS EPOUTEN

EPCONDIS

EPHSHK

EPOUTEN

EPHSHK EPCONDIS EPOUTEN

EPCONDIS

EPHSHK

EPOUTEN

EPHSHK EPCONDIS EPOUTEN

Bank 30

F0Ch

—

Unimplemented

—

F1Fh

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

Note 1:

PIC16(L)F1459 only.

2:

3:

PIC16(L)F1455/9 only.

Unimplemented, read as ‘1’.

DS41639A-page 42

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Addres

s

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 31

F8Ch

—

FE3h

—

Unimplemented

—

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

STATUS_

SHAD

—

Z_SHAD

DC_SHAD

C_SHAD

---- -xxx ---- -uuu

xxxx xxxx uuuu uuuu

---x xxxx ---u uuuu

-xxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

WREG_

SHAD

BSR_

Working Register Shadow

—

Bank Select Register Shadow

SHAD

PCLATH_

SHAD

Program Counter Latch High Register Shadow

FSR0L_

SHAD

Indirect Data Memory Address 0 Low Pointer Shadow

Indirect Data Memory Address 0 High Pointer Shadow

Indirect Data Memory Address 1 Low Pointer Shadow

Indirect Data Memory Address 1 High Pointer Shadow

Unimplemented

FSR0H_

SHAD

FSR1L_

SHAD

FSR1H_

SHAD

—

FECh

FEDh

FEEh

FEFh

—

Current Stack Pointer

---1 1111 ---1 1111

xxxx xxxx uuuu uuuu

-xxx xxxx -uuu uuuu

STKPTR

TOSL

Top-of-Stack Low byte

Top-of-Stack High byte

—

TOSH

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

Note 1:

PIC16(L)F1459 only.

2:

3:

PIC16(L)F1455/9 only.

Unimplemented, read as ‘1’.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 43

PIC16(L)F1454/5/9

3.4.2

COMPUTED GOTO

3.4

PCL and PCLATH

A computed GOTOis accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTOmethod, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application

Note AN556, “Implementing a Table Read” (DS00556).

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 3-3 shows the five

situations for the loading of the PC.

3.4.3

COMPUTED FUNCTION CALLS

FIGURE 3-3:

LOADING OF PC IN

A computed function CALLallows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

DIFFERENT SITUATIONS

Instruction with

14

0

PCH

7

PCL

PCL as

PC

Destination

8

6

0

PCLATH

ALU Result

If using the CALLinstruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

14

0

PCH

PCL

GOTO, CALL

PC

The CALLWinstruction enables computed calls by com-

bining PCLATH and W to form the destination address.

A computed CALLWis accomplished by loading the W

register with the desired address and executing CALLW.

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

11

4

6

0

PCLATH

OPCODE <10:0>

14

0

PCH

7

PCL

CALLW

PC

8

6

0

3.4.4

BRANCHING

PCLATH

W

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

14

PCH

PCL

PC

BRW

BRA

15

PC + W

14

PCH

PCL

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

PC

15

PC + OPCODE <8:0>

If using BRA, the entire PC will be loaded with PC + 1 +,

the signed value of the operand of the BRAinstruction.

3.4.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program Coun-

ter PC<14:8> bits (PCH) to be replaced by the contents

of the PCLATH register. This allows the entire contents

of the program counter to be changed by writing the

desired upper seven bits to the PCLATH register. When

the lower eight bits are written to the PCL register, all

15 bits of the program counter will change to the values

contained in the PCLATH register and those being writ-

ten to the PCL register.

DS41639A-page 44

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

3.5.1

ACCESSING THE STACK

3.5

Stack

The stack is available through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS

is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR,

which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is five bits to allow detection of

overflow and underflow.

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figures 3-4 through 3-7). The stack

space is not part of either program or data space. The

PC is PUSHed onto the stack when CALL or CALLW

instructions are executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN,

RETLWor a RETFIEinstruction execution. PCLATH is

not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN

bit is programmed to ‘0‘(Configuration Words). This

means that after the stack has been PUSHed sixteen

times, the seventeenth PUSH overwrites the value that

was stored from the first PUSH. The eighteenth PUSH

overwrites the second PUSH (and so on). The

STKOVF and STKUNF flag bits will be set on an Over-

flow/Underflow, regardless of whether the Reset is

enabled.

Note:

Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLWand

Interrupts will increment STKPTR while RETLW,

RETURN, and RETFIEwill decrement STKPTR. At any

time STKPTR can be inspected to see how much stack

is left. The STKPTR always points at the currently used

place on the stack. Therefore, a CALL or CALLW will

increment the STKPTR and then write the PC, and a

return will unload the PC and then decrement the

STKPTR.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, CALLW, RETURN, RETLW and

RETFIE instructions or the vectoring to

an interrupt address.

Reference Figure 3-4 through Figure 3-7 for examples

of accessing the stack.

FIGURE 3-4:

ACCESSING THE STACK EXAMPLE 1

Stack Reset Disabled

STKPTR = 0x1F

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x1F

(STVREN = 0)

Initial Stack Configuration:

After Reset, the stack is empty. The

empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL registers will return ‘0’. If

the Stack Overflow/Underflow Reset is

disabled, the TOSH/TOSL registers will

return the contents of stack address 0x0F.

Stack Reset Enabled

STKPTR = 0x1F

TOSH:TOSL

0x0000

(STVREN = 1)

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 45

PIC16(L)F1454/5/9

FIGURE 3-5:

ACCESSING THE STACK EXAMPLE 2

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

This figure shows the stack configuration

after the first CALLor a single interrupt.

If a RETURN instruction is executed, the

return address will be placed in the

Program Counter and the Stack Pointer

decremented to the empty state (0x1F).

TOSH:TOSL

Return Address

STKPTR = 0x00

FIGURE 3-6:

ACCESSING THE STACK EXAMPLE 3

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

After seven CALLs or six CALLs and an

interrupt, the stack looks like the figure

on the left. A series of RETURNinstructions

will repeatedly place the return addresses

into the Program Counter and pop the stack.

STKPTR = 0x06

TOSH:TOSL

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

DS41639A-page 46

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 3-7:

ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

When the stack is full, the next CALLor

an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00

so the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

TOSH:TOSL

STKPTR = 0x10

3.5.2

OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is

programmed to ‘1’, the device will be reset if the stack

is PUSHed beyond the sixteenth level or POPed

beyond the first level, setting the appropriate bits

(STKOVF or STKUNF, respectively) in the PCON

register.

3.6

Indirect Addressing

The INDFn registers are not physical registers. Any

instruction that accesses an INDFn register actually

accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address

specifies one of the two INDFn registers, the read will

return ‘0’ and the write will not occur (though Status bits

may be affected). The FSRn register value is created

by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an

addressing space with 65536 locations. These locations

are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 47

PIC16(L)F1454/5/9

FIGURE 3-8:

INDIRECT ADDRESSING

0x0000

Traditional

Data Memory

0x0FFF

0x1000

0x1FFF

0x2000

Reserved

Linear

Data Memory

0x29AF

0x29B0

Reserved

0x0000

FSR

Address

Range

0x7FFF

0x8000

Program

Flash Memory

0xFFFF

0x7FFF

Note:

Not all memory regions are completely implemented. Consult device memory tables for memory limits.

DS41639A-page 48

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

3.6.1

TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR

address 0x000 to FSR address 0xFFF. The addresses

correspond to the absolute addresses of all SFR, GPR,

DPR and common registers.

FIGURE 3-9:

TRADITIONAL DATA MEMORY MAP

Direct Addressing

From Opcode

Indirect Addressing

4

BSR

6

7

FSRxH

0

7

FSRxL

0

0 0 0 0

Location Select

Bank Select

Location Select

00000 00001 00010

11111

0x00

0x7F

Bank 0 Bank 1 Bank 2

Bank 31

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 49

PIC16(L)F1454/5/9

3.6.2

LINEAR DATA MEMORY

3.6.3

PROGRAM FLASH MEMORY

The linear data memory is the region from FSR

address 0x2000 to FSR address 0x29AF. This region is

a virtual region that points back to the 80-byte blocks of

DPR or GPR memory in all the banks.

To make constant data access easier, the entire

program Flash memory is mapped to the upper half of

the FSR address space. When the MSB of FSRnH is

set, the lower 15 bits are the address in program

memory which will be accessed through INDF. Only the

lower eight bits of each memory location is accessible

via INDF. Writing to the program Flash memory cannot

be accomplished via the FSR/INDF interface. All

instructions that access program Flash memory via the

FSR/INDF interface will require one additional

instruction cycle to complete.

Unimplemented memory reads as 0x00. Use of the

linear data memory region allows buffers to be larger

than 80 bytes because incrementing the FSR beyond

one bank will go directly to the DPR or GPR memory of

the next bank.

The 16 bytes of common memory are not included in

the linear data memory region.

FIGURE 3-11:

PROGRAM FLASH

MEMORY MAP

FIGURE 3-10:

LINEAR DATA MEMORY

MAP

7

0

FSRnH

FSRnL

7

1

7

0

FSRnH

FSRnL

0 0 1

Location Select

0x8000

0x0000

Location Select

0x2000

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Program

Flash

Memory

(low 8

bits)

Bank 2

0x16F

0xF20

Bank 30

0x7FFF

0xFFFF

0xF6F

0x29AF

DS41639A-page 50

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

4.0

DEVICE CONFIGURATION

Device configuration consists of Configuration Words,

Code Protection and Device ID.

4.1

Configuration Words

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1 at

8007h and Configuration Word 2 at 8008h.

Note:

The DEBUG bit in Configuration Words is

managed automatically by device

development tools including debuggers

and programmers. For normal device

operation, this bit should be maintained as

a '1'.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 51

PIC16(L)F1454/5/9

4.2

Register Definitions: Configuration Words

REGISTER 4-1:

CONFIG1: CONFIGURATION WORD 1

R/P-1

IESO

R/P-1

U-1

—

FCMEN

CLKOUTEN

BOREN<1:0>

bit 13

bit 8

R/P-1

bit 0

R/P-1

CP

R/P-1

MCLRE

PWRTE

WDTE<1:0>

FOSC<2:0>

bit 7

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared

-n = Value when blank or after Bulk Erase

bit 13

bit 12

bit 11

FCMEN: Fail-Safe Clock Monitor Enable bit

1= Fail-Safe Clock Monitor is enabled

0= Fail-Safe Clock Monitor is disabled

IESO: Internal External Switchover bit

1= Internal/External Switchover mode is enabled

0= Internal/External Switchover mode is disabled

CLKOUTEN: Clock Out Enable bit

1= CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin

0= CLKOUT function is enabled on the CLKOUT pin

bit 10-9

BOREN<1:0>: Brown-out Reset Enable bits⁽¹⁾

11= BOR enabled

10= BOR enabled during operation and disabled in Sleep

01= BOR controlled by SBOREN bit of the BORCON register

00= BOR disabled

bit 8

bit 7

Unimplemented: Read as ‘1’

CP: Code Protection bit⁽²⁾

1= Program memory code protection is disabled

0= Program memory code protection is enabled

bit 6

MCLRE: MCLR/VPP Pin Function Select bit

If LVP bit = 1:

This bit is ignored.

If LVP bit = 0:

1= MCLR/VPP pin function is MCLR; Weak pull-up enabled.

0= MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUA register.

bit 5

PWRTE: Power-Up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

bit 4-3

WDTE<1:0>: Watchdog Timer Enable bits

11= WDT enabled

10= WDT enabled while running and disabled in Sleep

01= WDT controlled by the SWDTEN bit in the WDTCON register

00= WDT disabled

DS41639A-page 52

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 4-1:

CONFIG1: CONFIGURATION WORD 1 (CONTINUED)

bit 2-0

FOSC<2:0>: Oscillator Selection bits

111= ECH: External clock, High-Power mode: on CLKIN pin

110= ECM: External clock, Medium-Power mode: on CLKIN pin

101= ECL: External clock, Low-Power mode: on CLKIN pin

100= INTOSC oscillator: I/O function on OSC1 pin

011= EXTRC oscillator: RC function connected to CLKIN pin

010= HS oscillator: High-speed crystal/resonator on OSC1 and OSC2 pins

001= XT oscillator: Crystal/resonator on OSC1 and OSC2 pins

000= LP oscillator: Low-power crystal on OSC1 and OSC2 pins

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: Once enabled (CP = 0), code-protect can only be disabled by bulk erasing the device.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 53

PIC16(L)F1454/5/9

REGISTER 4-2:

CONFIG2: CONFIGURATION WORD 2

R/P-1

LVP

R/P-1

BORV

R/P-1

(3)

DEBUG

LPBOR

STVREN

PLLEN

bit 13

bit 8

R/P-1

USBLSCLK

R/P-1

U-1

—

U-1

—

R/P-1

WRT<1:0>

PLLMULT

bit 7

CPUDIV<1:0>

bit 0

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

-n = Value when blank or after Bulk Erase

‘0’ = Bit is cleared

(1)

bit 13

bit 12

bit 11

bit 10

bit 9

LVP: Low-Voltage Programming Enable bit

1= Low-voltage programming enabled

0= High-voltage on MCLR must be used for programming

(3)

DEBUG: In-Circuit Debugger Mode bit

1= In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins

0= In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

LPBOR: Low-Power BOR Enable bit

1= Low-Power Brown-out Reset is disabled

0= Low-Power Brown-out Reset is enabled

(2)

BORV: Brown-out Reset Voltage Selection bit

1= Brown-out Reset voltage (Vbor), low trip point selected

0= Brown-out Reset voltage (Vbor, high trip point selected

STVREN: Stack Overflow/Underflow Reset Enable bit

1= Stack Overflow or Underflow will cause a Reset

0= Stack Overflow or Underflow will not cause a Reset

bit 8

PLLEN: PLL Enable bit

1= PLL is enabled

0= PLL is disabled

bit 7

PLLMULT: PLL Multiplier Selection bit

1= 3x PLL Output Frequency is selected

0= 4x PLL Output Frequency is selected

bit 6

USBLSCLK: USB Low-Speed Clock Selection bit

1= USB Clock divide-by 8 (48 MHz system input clock expected)

0= USB Clock divide-by 4 (24 MHz system input clock expected)

bit 5-4

CPUDIV<1:0>: CPU System Clock Selection bits

11= CPU system clock divided by 6

10= CPU system clock divided by 3

01= CPU system clock divided by 2

00= No CPU system clock divide

bit 3-2

bit 1-0

Unimplemented: Read as ‘1’

WRT<1:0>: Flash Memory Self-Write Protection bits

8 kW Flash memory:

11= Write protection off

10= 000h to 01FFh write-protected, 0200h to 1FFFh may be modified

01= 000h to 0FFFh write-protected, 1000h to 1FFFh may be modified

00= 000h to 1FFFh write-protected, no addresses may be modified

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: See Vbor parameter for specific trip point voltages.

3: The DEBUG bit in Configuration Words is managed automatically by device development tools including

debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.

DS41639A-page 54

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

4.3

Code Protection

Code protection allows the device to be protected from

unauthorized access. Internal access to the program

memory is unaffected by any code protection setting.

4.3.1

PROGRAM MEMORY PROTECTION

The entire program memory space is protected from

external reads and writes by the CP bit in Configuration

Words. When CP = 0, external reads and writes of

program memory are inhibited and a read will return all

‘0’s. The CPU can continue to read program memory,

regardless of the protection bit settings. Writing the

program memory is dependent upon the write

protection

setting.

See

Section 4.4

“Write

Protection” for more information.

4.4

Write Protection

Write protection allows the device to be protected from

unintended self-writes. Applications, such as

bootloader software, can be protected while allowing

other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the

size of the program memory block that is protected.

4.5

User ID

Four memory locations (8000h-8003h) are designated as

ID locations where the user can store checksum or other

code identification numbers. These locations are

readable and writable during normal execution. See

Section 11.4 “User ID, Device ID and Configuration

Word Access” for more information on accessing these

memory locations. For more information on checksum

calculation, see the “PIC16(L)F1454/5/9 Memory

Programming Specification” (DS41620).

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 55

PIC16(L)F1454/5/9

4.6

Device ID and Revision ID

The memory location 8005h and 8006h are where the

Device ID and Revision ID are stored. See

Section 11.4 “User ID, Device ID and Configuration

Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and

debuggers, may be used to read the Device ID and

Revision ID.

4.7

Register Definitions: Revision and Device

REGISTER 4-3:

DEVID: DEVICE ID REGISTER

R

DEV<13:8>

bit 13

bit 8

bit 0

R

DEV<7:0>

bit 7

Legend:

R = Readable bit

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 13-0

DEV<13:0>: Device ID bits

Device

DEVICEID<13:0> Values

PIC16F1454

PIC16LF1454

PIC16F1455

PIC16LF1455

PIC16F1459

PIC16LF1459

11 0000 0010 0000 (3020h)

11 0000 0010 0100 (3024h)

11 0000 0010 0001 (3021h)

11 0000 0010 0101 (3025h)

11 0000 0010 0011 (3023h)

11 0000 0010 0111 (3027h)

REGISTER 4-4:

REVID: REVISION ID REGISTER

R

REV<13:8>

bit 13

bit 8

bit 0

R

REV<7:0>

bit 7

Legend:

R = Readable bit

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 13-0

REV<13:0>: Revision ID bits

DS41639A-page 56

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

The oscillator module can be configured in one of eight

clock modes.

5.0

5.1

OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

1. ECL – External Clock Low-Power mode

(0 MHz to 0.5 MHz)

Overview

2. ECM – External Clock Medium-Power mode

(0.5 MHz to 4 MHz)

The oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 5-1

illustrates a block diagram of the oscillator module.

3. ECH – External Clock High-Power mode

(4 MHz to 20 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode (up to 4 MHz)

Clock sources can be supplied from external oscillators,

quartz crystal resonators, ceramic resonators and

Resistor-Capacitor (RC) circuits. In addition, the system

clock source can be supplied from one of two internal

oscillators, with a choice of speeds selectable via

software. Additional clock features include:

6. HS – High Gain Crystal or Ceramic Resonator

mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC).

8. INTOSC – Internal oscillator (31 kHz to 16 MHz).

Clock Source modes are selected by the FOSC<2:0>

bits in the Configuration Words. The FOSC bits

determine the type of oscillator that will be used when

the device is first powered.

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

The EC clock mode relies on an external logic level

signal as the device clock source. The LP, XT, and HS

clock modes require an external crystal or resonator to

be connected to the device. Each mode is optimized for

a different frequency range. The RC clock mode

requires an external resistor and capacitor to set the

oscillator frequency.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch

automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

The INTOSC internal oscillator block produces a low

and high-frequency clock source, designated

LFINTOSC and HFINTOSC. (see Internal Oscillator

Block, Figure 5-1). A wide selection of device clock

frequencies may be derived from these two clock

sources.

• Fast start-up oscillator allows internal circuits to

power up and stabilize before switching to the 16

MHz HFINTOSC

• 3x/4x selectable Phase Lock Frequency Multiplier

allows operation at 24, 32 or 48 MHz.

• USB with configurable Full/Low speed operation.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 57

PIC16(L)F1454/5/9

FIGURE 5-1:

SIMPLIFIED PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

SPLLMULT

PLLMULT

SPLLEN

PLLEN

FOSC<2:0>

3

CLKIN/ OSC1/

INTOSC

SOSCI/ T1CKI

(16 or 8 MHz)

CPUDIV<1:0>

3x/4x PLL

Primary

Oscillator

(OSC)

FOSC

to

CPU and

Peripherals

CPU

Divider

Primary Clock

1

0

CLKOUT / OSC2

SOSCO/ T1G

SOSC_clk

Secondary Clock

INTOSC

FSEN

Secondary

Oscillator

(SOSC)

48 MHz

6 MHz

1

USB

Clock

Source

IRCF<3:0>

USB

Divider

4

0

Active Clock

Tuning

16 MHz

8 MHz

USBLSCLK

Sleep

4 MHz

2 MHz

1 MHz

16 MHz

Internal OSC

Clock

Control

HFINTOSC

500 kHz

250 kHz

125 kHz

62.5 kHz

31.25 kHz

31 kHz

Start-Up

OSC

2

Start-up

Control Logic

SCS<1:0>

3

FOSC<2:0>

to WDT, PWRT

and other Modules

LFINTOSC

31 kHz

Source

DS41639A-page 58

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

5.2

Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the

clock source to function. Examples are: oscillator mod-

ules (EC mode), quartz crystal resonators or ceramic

resonators (LP, XT and HS modes) and Resis-

tor-Capacitor (RC) mode circuits.

Internal clock sources are contained within the oscillator

module. The internal oscillator block has two internal

oscillators that are used to generate the internal system

clock sources: the 16 MHz High-Frequency Internal

Oscillator and the 31 kHz Low-Frequency Internal

Oscillator (LFINTOSC).

FIGURE 5-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

OSC1/CLKIN

PIC^®MCU

Clock from

Ext. System

The system clock can be selected between external or

internal clock sources via the System Clock Select

(SCS) bits in the OSCCON register. See Section 5.3

“CPU Clock Divider” for additional information.

OSC2/CLKOUT

I/O⁽¹⁾

FOSC/4 or

Note 1: Output depends upon CLKOUTEN bit of the

5.2.1

EXTERNAL CLOCK SOURCES

Configuration Words.

An external clock source can be used as the device

system clock by performing one of the following

actions:

5.2.1.2

LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 5-3). The three modes select

a low, medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

• Program the FOSC<2:0> bits in the Configuration

Words to select an external clock source that will

be used as the default system clock upon a

device Reset.

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to:

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is designed to

drive only 32.768 kHz tuning-fork type crystals (watch

crystals).

- Secondary oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

See Section 5.3 “CPU Clock Divider”for more infor-

mation.

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

5.2.1.1

EC Mode

The External Clock (EC) mode allows an externally

generated logic level signal to be the system clock

source. When operating in this mode, an external clock

source is connected to the OSC1 input.

OSC2/CLKOUT is available for general purpose I/O or

CLKOUT. Figure 5-2 shows the pin connections for EC

mode.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require a high drive setting.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

EC mode has three power modes to select from through

Configuration Words:

• High power, 4-20 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low power, 0-0.5 MHz (FOSC = 101)

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 59

PIC16(L)F1454/5/9

FIGURE 5-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 5-4:

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

PIC^®MCU

OSC1/CLKIN

C1

To Internal

Logic

To Internal

Logic

Quartz

Crystal

(2)

Sleep

RF

(3)

(2)

RP

RF

Sleep

OSC2/CLKOUT

(1)

C2

RS

OSC2/CLKOUT

(1)

C2

RS

Ceramic

Resonator

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

Note 1: Quartz

crystal

characteristics

vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

5.2.1.3

Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts 1024

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

oscillations from OSC1. This occurs following

a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended unless

either FSCM or Two-Speed Start-Up are enabled. In this

case, code will continue to execute at the selected

INTOSC frequency while the OST is counting . The OST

ensures that the oscillator circuit, using a quartz crystal

resonator or ceramic resonator, has started and is

providing a stable system clock to the oscillator module.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 5.6

“Two-Speed Clock Start-up Mode”).

DS41639A-page 60

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

5.2.1.4

3x PLL or 4x PLL

Note 1: Quartz

crystal

characteristics

vary

The oscillator module contains a PLL that can be used

with both external and internal clock sources to provide a

system clock source. By setting the SPLLMULT bit of the

OSCCON register, 3x PLL is selected. By clearing the

SPLLMULT bit of the OSCCON register, 4x PLL is

selected. The input frequency for the PLL must fall within

specifications. See the PLL Clock Timing Specifications in

Section 29.0 “Electrical Specifications”.

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, reference

The PLL may be enabled for use by one of two methods:

the following Microchip Applications Notes:

1. Program the PLLEN bit in Configuration Words

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

to a ‘1’.

2. Write the SPLLEN bit in the OSCCON register to

a ‘1’. If the PLLEN bit in Configuration Words is

programmed to a ‘1’, then the value of SPLLEN

is ignored.

Analysis and Design” (DS00943)

HFINTOSC

(MHz)

ECH/HS

(MHz)

System

Clock (MHz)

• AN949, “Making Your Oscillator Work”

(DS00949)

PLL

4x

3x

8

8 - 12

8 - 16

32 - 48

24 - 48

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS” (DS91097)

16, 8

• AN1288, “Design Practices for

Low-Power External Oscillators”

(DS01288)

5.2.1.5

Secondary Oscillator

The secondary oscillator is a separate crystal oscillator

that is associated with the Timer1 peripheral. It is opti-

mized for timekeeping operations with a 32.768 kHz

crystal connected between the SOSCO and SOSCI

device pins.

The secondary oscillator can be used as an alternate

system clock source and can be selected during

run-time using clock switching. Refer to Section 5.3

“CPU Clock Divider” for more information.

FIGURE 5-5:

QUARTZ CRYSTAL

OPERATION

(SECONDARY

OSCILLATOR)

PIC^®MCU

SOSCI

C1

C2

To Internal

Logic

32.768 kHz

Quartz

Crystal

SOSCO

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 61

PIC16(L)F1454/5/9

5.2.1.6

External RC Mode

5.2.2

INTERNAL CLOCK SOURCES

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required.

The device may be configured to use the internal oscil-

lator block as the system clock by performing one of the

following actions:

• Program the FOSC<2:0> bits in Configuration

Words to select the INTOSC clock source, which

will be used as the default system clock upon a

device Reset.

The RC circuit connects to OSC1. OSC2/CLKOUT is

available for general purpose I/O or CLKOUT. The

function of the OSC2/CLKOUT pin is determined by the

CLKOUTEN bit in Configuration Words.

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to the internal

oscillator during run-time. See Section 5.3 “CPU

Clock Divider”for more information.

Figure 5-6 shows the external RC mode connections.

FIGURE 5-6:

EXTERNAL RC MODES

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT is available for general

purpose I/O or CLKOUT.

VDD

PIC^®MCU

The function of the OSC2/CLKOUT pin is determined

by the CLKOUTEN bit in Configuration Words.

REXT

OSC1/CLKIN

Internal

Clock

The internal oscillator block has two independent

oscillators that provides the internal system clock

source.

CEXT

VSS

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

16 MHz. The frequency of the HFINTOSC can be

user-adjusted via software using the OSCTUNE

register (Register 5-3).

OSC2/CLKOUT

FOSC/4 or I/O⁽¹⁾

Recommended values: 10 k  REXT  100 k, <3V

3 k  REXT  100 k, 3-5V

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at

31 kHz.

CEXT > 20 pF, 2-5V

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

5.2.2.1

HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 16 MHz internal clock source. The

frequency of the HFINTOSC can be altered via

software using the OSCTUNE register (Register 5-3).

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). The frequency derived

from the HFINTOSC can be selected via software using

the IRCF<3:0> bits of the OSCCON register. See

Section 5.2.2.4 “Internal Oscillator Frequency

Selection” for more information.

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The user also needs to take into account variation due

to tolerance of the external RC components used.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired HF frequency, and

• FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’.

A fast start-up oscillator allows internal circuits to

power-up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit

(HFIOFR) of the OSCSTAT register indicates when the

HFINTOSC is running.

The High-Frequency Internal Oscillator Stable bit

(HFIOFS) of the OSCSTAT register indicates when the

HFINTOSC is running within 0.5% of its final value.

DS41639A-page 62

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

5.2.2.2

Internal Oscillator Frequency

Adjustment

5.2.2.4

Internal Oscillator Frequency

Selection

The 16 MHz internal oscillator is factory calibrated.

This internal oscillator can be adjusted in software by

writing to the OSCTUNE register (Register 5-3). Since

all HFINTOSC clock sources are derived from the

16 MHz internal oscillator a change in the OSCTUNE

register value will apply to all HFINTOSC frequencies.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 5-1). The Internal Oscillator Frequency

Select bits IRCF<3:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

the following frequencies can be selected via software:

The default value of the OSCTUNE register is ‘0’. The

value is a 7-bit two’s complement number. A value of

3Fh will provide an adjustment to the maximum

frequency. A value of 40h will provide an adjustment to

the minimum frequency.

• HFINTOSC

- 48 MHz (requires 3x PLL)

- 32 MHz (requires 4x PLL)

- 24 MHz (requires 3x PLL)

- 16 MHz

When the OSCTUNE register is modified, the oscillator

frequency will begin shifting to the new frequency. Code

execution continues during this shift. There is no

indication that the shift has occurred.

- 8 MHz

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

- 4 MHz

- 2 MHz

- 1 MHz

- 500 kHz (Default after Reset)

- 250 kHz

- 125 kHz

5.2.2.3

LFINTOSC

- 62.5 kHz

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

- 31.25 kHz

• LFINTOSC

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). Select 31 kHz, via

software, using the IRCF<3:0> bits of the OSCCON

register. See Section 5.2.2.4 “Internal Oscillator

Frequency Selection” for more information. The

LFINTOSC is also the frequency for the Power-up Timer

(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock

Monitor (FSCM).

- 31 kHz

Note:

Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’

and the frequency selection is set to

500 kHz. The user can modify the IRCF

bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These dupli-

cate choices can offer system design trade-offs. Lower

power consumption can be obtained when changing

oscillator sources for a given frequency. Faster transi-

tion times can be obtained between frequency changes

that use the same oscillator source.

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register = 000) as the

system clock source (SCS bits of the OSCCON

register = 1x), or when any of the following are

enabled:

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired LF frequency, and

• FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low-Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 63

PIC16(L)F1454/5/9

5.2.2.5

Internal Oscillator Frequency

Selection Using the PLL

5.2.2.6

Internal Oscillator Clock Switch

Timing

The Internal Oscillator Block can be used with the PLL

associated with the External Oscillator Block to

produce a 24 MHz, 32 MHz or 48 MHz internal system

clock source. The following settings are required to use

the PLL internal clock sources:

When switching between the HFINTOSC and the

LFINTOSC, the new oscillator may already be shut

down to save power (see Figure 5-7). If this is the case,

there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC and

LFINTOSC oscillators. The sequence of a frequency

selection is as follows:

• The FOSC bits of the Configuration Words must

be set to use the INTOSC source as the device

system clock (FOSC<2:0> = 100).

• The SCS bits of the OSCCON register must be

cleared to use the clock determined by

FOSC<2:0> in Configuration Words

(SCS<1:0> = 00).

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

• For 24 MHz or 32 MHz, the IRCF bits of the

OSCCON register must be set to the 8 MHz

HFINTOSC set to use (IRCF<3:0> = 1110).

3. Clock switch circuitry waits for a falling edge of

the current clock.

• For 48 MHz, the IRCF bits of the OSCCON regis-

ter must be set to the 16 MHz HFINTOSC set to

use (IRCF<3:0> = 1111).

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

• For 24 MHz or 48 MHz, the 3x PLL is required.

The SPLLMULT of the OSCCON register must be

set to use (SPLLMULT = 1).

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

• For 32 MHz, the 4x PLL is required. The

SPLLMULT of the OSCCON register must be

clear to use (SPLLMULT = 0).

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 5-3.

• The SPLLEN bit of the OSCCON register must be

set to enable the PLL, or the PLLEN bit of the

Configuration Words must be programmed to a

'1'.

Start-up delay specifications are located in the

oscillator tables of Section 29.0 “Electrical

Specifications”.

Note:

When using the PLLEN bit of the

Configuration Words, the PLL cannot be

disabled by software. The 8 MHz and 16

MHz HFINTOSC options will no longer be

available.

The PLL is not available for use with the internal oscil-

lator when the SCS bits of the OSCCON register are

set to '1x'. The SCS bits must be set to '00' to use the

PLL with the internal oscillator.

DS41639A-page 64

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 5-7:

HFINTOSC

INTERNAL OSCILLATOR SWITCH TIMING

LFINTOSC (FSCM and WDT disabled)

HFINTOSC

Start-up Time

2-cycle Sync

Running

LFINTOSC

0

0

IRCF <3:0>

System Clock

HFINTOSC

LFINTOSC (Either FSCM or WDT enabled)

HFINTOSC

2-cycle Sync

Running

LFINTOSC

IRCF <3:0>

0

0

System Clock

LFINTOSC

HFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

Running

LFINTOSC

Start-up Time 2-cycle Sync

HFINTOSC

IRCF <3:0>

= 0

 0

System Clock

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 65

PIC16(L)F1454/5/9

5.4.1

LOW-SPEED OPERATION

5.3

CPU Clock Divider

For low-speed USB Operation, a 24 MHz clock is

required for the USB module. To generate the 24 MHz

clock, the following Oscillator modes are allowed:

The CPU Clock divider allows the system clock to run

at a slower speed than the Low/Full-Speed USB

module clock, while sharing the same clock source.

Only the oscillator defined by the settings of the FOSC

bits of the Configuration Words may be used with the

CPU clock divider. the CPU clock divider is controlled

by the CPUDIV<1:0> bits of the Configuration Words.

• HFINTOSC with PLL

• ECH mode

• HS mode

Table 5-1 shows the recommended Clock mode for

low-speed operation.

Setting the CPUDIV bits will set the system clock to:

• Equal the clock speed of the USB module

• Half the clock speed of the USB module

• One third the clock speed of the USB Module

• One sixth clock speed of the USB module

5.4.2

HIGH-SPEED OPERATION

For full-speed USB operation, a 48 MHz clock is

required for the USB module. To generate the 48 MHz

clock, the following oscillator modes are allowed:

For more information on the CPU Clock Divider, see

Figure 5-1 and Configuration Words.

• HFINTOSC with PLL

• ECH mode

• HS mode

5.4

USB Operation

Table 5-1 shows the recommended Clock mode for

full-speed operation.

The USB module is designed to operate in two different

modes:

• Low Speed

• Full Speed

To achieve the timing requirements imposed by the

USB specifications, the internal oscillator or the primary

external oscillator are required for the USB module.

The FOSC bits of the Configuration Words must be set

to INTOSC, ECH or HS mode with a clock frequency of

6, 12, or 16 MHz.

TABLE 5-1:

Clock Mode

LOW-SPEED USB CLOCK SETTINGS

Clock

System Clock

Frequency

(MHz)

PLL Value

USBLSCLK

CPUDIV<1:0>

Frequency

11

10

01

00

8

16

24

48

16 MHz

3x

1

0

1

0

HFINTOSC

11

10

01

00

4

8

12

24

8 MHz

16 MHz

12 MHz

8 MHz

3x

4x

3x

11

10

01

00

8

16

24

48

11

10

01

00

8

16

24

48

ECH or HS mode

11

10

01

00

4

8

12

24

DS41639A-page 66

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 5-2:

Clock Mode

HIGH-SPEED USB CLOCK SETTINGS

Clock

System Clock

Frequency

(MHz)

PLL Value

USBLSCLK

CPUDIV<1:0>

Frequency

11

10

01

00

8

16

24

48

HFINTOSC

16 MHz

3x

0

11

10

01

00

8

16

24

48

16 MHz

12 MHz

3x

4x

ECH or HS mode

11

10

01

00

8

16

24

48

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 67

PIC16(L)F1454/5/9

5.5.3

SECONDARY OSCILLATOR

5.5

Clock Switching

The secondary oscillator is a separate crystal oscillator

associated with the Timer1 peripheral. It is optimized

for timekeeping operations with a 32.768 kHz crystal

connected between the SOSCO and SOSCI device

pins.

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bits of the OSCCON

register. The following clock sources can be selected

using the SCS bits:

The secondary oscillator is enabled using the

T1OSCEN control bit in the T1CON register. See

Section 20.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

• Default system oscillator determined by FOSC

bits in Configuration Words

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

5.5.4

SECONDARY OSCILLATOR READY

(SOSCR) BIT

5.5.1

SYSTEM CLOCK SELECT (SCS)

BITS

The user must ensure that the secondary oscillator is

ready to be used before it is selected as a system clock

source. The Secondary Oscillator Ready (SOSCR) bit

of the OSCSTAT register indicates whether the

secondary oscillator is ready to be used. After the

SOSCR bit is set, the SCS bits can be configured to

select the secondary oscillator.

The System Clock Select (SCS) bits of the OSCCON

register selects the system clock source that is used for

the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of

the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the secondary

oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<3:0>

bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always

cleared.

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or

Fail-Safe Clock Monitor, does not update

the SCS bits of the OSCCON register. The

user can monitor the OSTS bit of the

OSCSTAT register to determine the current

system clock source.

When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 5-3.

5.5.2

OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT

The Oscillator Start-up Timer Status (OSTS) bit of the

OSCSTAT register indicates whether the system clock

is running from the external clock source, as defined by

the FOSC<2:0> bits in the Configuration Words, or

from the internal clock source. In particular, OSTS

indicates that the Oscillator Start-up Timer (OST) has

timed out for LP, XT or HS modes. The OST does not

reflect the status of the secondary oscillator.

DS41639A-page 68

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

5.6.1

TWO-SPEED START-UP MODE

CONFIGURATION

5.6

Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device. This mode

allows the application to wake-up from Sleep, perform

a few instructions using the INTOSC internal oscillator

block as the clock source and go back to Sleep without

waiting for the external oscillator to become stable.

Two-Speed Start-up mode is configured by the

following settings:

• IESO (of the Configuration Words) = 1; Inter-

nal/External Switchover bit (Two-Speed Start-up

mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

Two-Speed Start-up provides benefits when the oscil-

lator module is configured for LP, XT, or HS modes.

The Oscillator Start-up Timer (OST) is enabled for

these modes and must count 1024 oscillations before

the oscillator can be used as the system clock source.

• Wake-up from Sleep.

Note:

When FSCM is enabled, Two-Speed

Start-Up will automatically be enabled.

If the oscillator module is configured for any mode

other than LP, XT or HS mode, then Two-Speed

Start-up is disabled. This is because the external clock

oscillator does not require any stabilization time after

POR or an exit from Sleep.

If the OST count reaches 1024 before the device

enters Sleep mode, the OSTS bit of the OSCSTAT reg-

ister is set and program execution switches to the

external oscillator. However, the system may never

operate from the external oscillator if the time spent

awake is very short.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCSTAT register to

remain clear.

TABLE 5-3:

OSCILLATOR SWITCHING DELAYS

Switch From

Switch To

Frequency

Oscillator Delay

(1)

31 kHz

LFINTOSC

Sleep/POR

Oscillator Warm-up Delay (TWARM)

31.25 kHz-16 MHz

HFINTOSC

Sleep/POR

LFINTOSC

EC, RC

DC – 20 MHz

2 cycles

EC, RC

DC – 20 MHz

1 cycle of each

SecondaryOscillator,

LP, XT, HS

Sleep/POR

32 kHz-20 MHz

1024 Clock Cycles (OST)

(1)

Any clock source

PLL Inactive

HFINTOSC

31.25 kHz-16 MHz

31 kHz

2 s (approx.)

(1)

LFINTOSC

1 cycle of each

Secondary Oscillator 32 kHz

PLL Active 24-48 MHz

1024 Clock Cycles (OST)

2 ms (approx.)

Note 1: PLL inactive.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 69

PIC16(L)F1454/5/9

5.6.2

TWO-SPEED START-UP

SEQUENCE

5.6.3

CHECKING TWO-SPEED CLOCK

STATUS

1. Wake-up from Power-on Reset or Sleep.

Checking the state of the OSTS bit of the OSCSTAT

register will confirm if the microcontroller is running

from the external clock source, as defined by the

FOSC<2:0> bits in the Configuration Words, or the

internal oscillator.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0>

bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 5-8:

TWO-SPEED START-UP

INTOSC

TOST

OSC1

0

1

1022 1023

OSC2

Program Counter

PC - N

PC + 1

PC

System Clock

DS41639A-page 70

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

5.7.3

FAIL-SAFE CONDITION CLEARING

5.7

Fail-Safe Clock Monitor

The Fail-Safe condition is cleared after a Reset,

executing a SLEEPinstruction or changing the SCS bits

of the OSCCON register. When the SCS bits are

changed, the OST is restarted. While the OST is

running, the device continues to operate from the

INTOSC selected in OSCCON. When the OST times

out, the Fail-Safe condition is cleared after successfully

switching to the external clock source. The OSFIF bit

should be cleared prior to switching to the external

clock source. If the Fail-Safe condition still exists, the

OSFIF flag will again become set by hardware.

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Configuration Words. The FSCM is applicable to all

external Oscillator modes (LP, XT, HS, EC, RC and

secondary oscillator).

FIGURE 5-9:

FSCM BLOCK DIAGRAM

Clock Monitor

Latch

5.7.4

RESET OR WAKE-UP FROM SLEEP

External

Clock

S

Q

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled. Therefore, the device will always be executing

code while the OST is operating.

LFINTOSC

Oscillator

÷ 64

R

Q

31 kHz

(~32 s)

488 Hz

(~2 ms)

Sample Clock

Clock

Failure

Detected

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

Status bits in the OSCSTAT register to

verify the oscillator start-up and that the

system clock switchover has successfully

completed.

5.7.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 5-9. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire

half-cycle of the sample clock elapses before the

external clock goes low.

5.7.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit

flag OSFIF of the PIR2 register. Setting this flag will

generate an interrupt if the OSFIE bit of the PIE2

register is also set. The device firmware can then take

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation.

The internal clock source chosen by the FSCM is

determined by the IRCF<3:0> bits of the OSCCON

register. This allows the internal oscillator to be

configured before a failure occurs.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 71

PIC16(L)F1454/5/9

FIGURE 5-10:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSCFIF

Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

DS41639A-page 72

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

5.8.2

ACTIVE CLOCK TUNING SOURCE

SELECTION

5.8

Active Clock Tuning (ACT)

The Active Clock Tuning (ACT) continuously adjusts

the 16 MHz Internal Oscillator, using an available

external reference, to achieve ± 0.20% accuracy. This

eliminates the need for a high-speed, high-accuracy

external crystal when the system has an available

lower speed, lower power, high-accuracy clock source

available.

The ACT reference clock is selected with the ACTSRC

bit of the ACTCON register. The reference clock

sources are provided by the:

•

USB module in full-speed operation (ACT_clk)

• Secondary clock at 32.768 kHz (SOSC_clk)

5.8.3

ACT LOCK STATUS

Systems implementing a Real-Time Clock Calendar

(RTCC) or a full-speed USB application can take full

advantage of the ACT.

The ACTLOCK bit will be set to '1', when the 16 MHz

Internal Oscillator is successfully tuned.

The bit will be cleared by the following conditions:

• Out of Lock condition

5.8.1

ACTIVE CLOCK TUNING

OPERATION

• Device Reset

The ACT defaults to the disabled state after any Reset.

When the ACT is disabled, the user can write to the

TUN<6:0> bits in the OSCTUNE register to manually

adjust the 16 MHz Internal Oscillator.

• ACT is disabled

5.8.4

ACT OUT-OF-RANGE STATUS

The ACT is enabled by setting the ACTEN bit of the

ACTCON register. When enabled, the ACT takes

control of the OSCTUNE register. The ACT uses the

selected ACT reference clock to tune the 16 MHz

Internal Oscillator to an accuracy of 16MHz ± 0.2%.

The tuning automatically adjusts the OSCTUNE

register every reference clock cycle.

If the ACT requires an OSCTUNE value outside the

range to achieve ± 0.20% accuracy, then

the ACT Out-of-Range (ACTOR) Status bit will be set

to '1'.

An out-of-range status can occur:

• When the 16 MHz internal oscillator is tuned to its

lowest frequency and the next ACT_clk event

requests a lower frequency.

Note 1: When the ACT is enabled, the

OSCTUNE register is only updated by

the ACT. Writes to the OSCTUNE regis-

ter by the user are inhibited, but reading

the register is permitted.

• When the 16 MHz internal oscillator is tuned to its

highest frequency and the next ACT_clk event

requests a higher frequency.

When the ACT out-of-range event occurs, the 16 MHz

internal oscillator will continue to use the last written

OSCTUNE value. When the OSCTUNE value moves

back within the tunable range and ACTLOCK is

established, the ACTOR bit is cleared to '0'.

2: After disabling the ACT, the user should

wait three instructions before writing to

the OSCTUNE register.

FIGURE 5-11:

ACTIVE CLOCK TUNING BLOCK DIAGRAM

ACTEN

ACTSRC

Enable

1

0

FSUSB_clk

SOSC_clk

ACT_clk

16 MHz

Internal OSC

Active

Clock

Tuning

ACT data

sfr data

7

Write

OSCTUNE

ACTEN

OSCTUNE<6:0>

ACTUD

ACTEN

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 73

PIC16(L)F1454/5/9

5.8.5

ACTIVE CLOCK TUNING UPDATE

DISABLE

When the ACT is enabled, the OSCTUNE register is

continuously updated every ACT_clk period. Setting

the ACT Update Disable bit can be used to suspend

updates to the OSCTUNE register, without disabling

the ACT. If the 16 MHz internal oscillator drifts out of the

accuracy range, the ACT Status bits will change and an

interrupt can be generated to notify the application.

Clearing the ACTUD bit will engage the ACT updates

to OSCTUNE and an interrupt can be generated to

notify the application.

5.8.6

INTERRUPTS

The ACT will set the ACT Interrupt Flag, (ACTIF) when

either of the ACT Status bits (ACTLOCK or ACTORS)

change state, regardless if the interrupt is enabled,

(ACTIE = 1). The ACTIF and ACTIE bits are in the PIRx

and PIEx registers, respectively. When ACTIE = 1, an

interrupt will be generated whenever the ACT Status

bits change.

The ACTIF bit must be cleared in software, regardless

of the interrupt enable setting.

5.8.7

OPERATION DURING SLEEP

This ACT does not run during Sleep and will not gener-

ate interrupts during Sleep.

DS41639A-page 74

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

5.9

Register Definitions: Oscillator Control

REGISTER 5-1:

OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0

SPLLMULT

R/W-0/0

R/W-1/1

R/W-0/0

SPLLEN

bit 7

IRCF<3:0>

SCS<1:0>

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = 1:

SPLLEN bit is ignored. PLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Words = 0:

1= PLL is enabled

0= PLL is disabled

bit 6

SPLLMULT: Software PLL Multiplier Select bit

1= 3x PLL is enabled

0= 4x PLL is enabled

bit 5-2

IRCF<3:0>: Internal Oscillator Frequency Select bits

1111= 16 MHz or 48 MHz HF (see Section 5.2.2.1 “HFINTOSC”)

1110= 8 MHz or 24 MHz HF (3x PLL) or 32 MHz HF (4x PLL) (see Section 5.2.2.1 “HFINTOSC”)

1101= 4 MHz

1100= 2 MHz

1011= 1 MHz

1010= 500 kHz⁽¹⁾

1001= 250 kHz⁽¹⁾

1000= 125 kHz⁽¹⁾

0111= 500 kHz (default upon Reset)

0110= 250 kHz

0101= 125 kHz

0100= 62.5 kHz

001x= 31.25 kHz⁽¹⁾

000x= 31 kHz LF

bit 1-0

SCS<1:0>: System Clock Select bits

1x= Internal oscillator block

01= Secondary oscillator

00= Clock determined by FOSC<2:0> in Configuration Words.

Note 1: Duplicate frequency derived from HFINTOSC.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 75

PIC16(L)F1454/5/9

REGISTER 5-2:

OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q

SOSCR

bit 7

R-0/q

R-q/q

R-0/q

U-0

—

U-0

—

R-0/q

PLLRDY

OSTS

HFIOFR

LFIOFR

HFIOFS

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Conditional

bit 7

SOSCR: Secondary Oscillator Ready bit

If T1OSCEN = 1:

1= Secondary oscillator is ready

0= Secondary oscillator is not ready

If T1OSCEN = 0:

1= Timer1 clock source is always ready

bit 6

bit 5

bit 4

PLLRDY: PLL Ready bit

1= PLL is ready

0= PLL is not ready

OSTS: Oscillator Start-up Timer Status bit

1= Running from the clock defined by the FOSC<2:0> bits of the Configuration Words

0= Running from an internal oscillator (FOSC<2:0> = 100)

HFIOFR: High-Frequency Internal Oscillator Ready bit

1= HFINTOSC is ready

0= HFINTOSC is not ready

bit 3-2

bit 1

Unimplemented: Read as ‘0’

LFIOFR: Low-Frequency Internal Oscillator Ready bit

1= LFINTOSC is ready

0= LFINTOSC is not ready

bit 0

HFIOFS: High-Frequency Internal Oscillator Stable bit

1= HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC

0= HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC

DS41639A-page 76

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

(1,2)

REGISTER 5-3:

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

—

R/W-0/0

bit 0

TUN<6:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-0

TUN<6:0>: Frequency Tuning bits

1000000= Minimum frequency

•

1111111=

0000000= Oscillator module is running at the factory-calibrated frequency.

0000001=

•

0111110=

0111111= Maximum frequency

Note 1: When active clock tuning is enabled (ACTSEL = 1) the oscillator is tuned automatically, the user cannot

write to OSCTUNE.

2: Oscillator is tuned monotonically.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 77

PIC16(L)F1454/5/9

REGISTER 5-4:

ACTCON: ACTIVE CLOCK TUNING (ACT) CONTROL REGISTER

R/W-0/0

ACTEN

bit 7

R/W-0/0

ACTUD

U-0

—

R/W-0/0

ACTSRC⁽¹⁾ACTLOCK

R-0/0

U-0

—

R-0/0

U-0

—

ACTORS

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

ACTEN: Active Clock Tuning Selection bit

1= ACT is enabled, updates to OSCTUNE are exclusive to the ACT

0= ACT is disabled

ACTUD: Active Clock Tuning Update Disable bit

1= Updates to the OSCTUNE register from ACT are disabled

0= Updates to the OSCTUNE register from ACT are enabled

bit 5

bit 4

Unimplemented: Read as ‘0’

ACTSRC: Active Clock Tuning Source Selection bit

1= The HFINTOSC oscillator is tuned using Fll-speed USB events

0= The HFINTOSC oscillator is tuned using the 32.768 kHz oscillator (SOSC) clock source

bit 3

ACTLOCK: Active Clock Tuning Lock Status bit

1= Locked; 16 MHz internal oscillator is within ± 0.20%.Locked

0= Not locked; 16 MHz internal oscillator tuning has not stabilized within ± 0.20%

bit 2

bit 1

Unimplemented: Read as ‘0’

ACTORS: Active Clock Tuning Out-of-Range Status bit

1= Out-of-range; oscillator frequency is outside of the OSCTUNE range

0= In-range; oscillator frequency is within the OSCTUNE range

bit 0

Unimplemented: Read as ‘0’

Note 1: The ACTSRC bit should only be changed when ACTEN = 0.

TABLE 5-4:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ACTEN

ACTUD

—

ACTSRC

ACTLOCK

—

ACTORS

—

ACTCON

OSCCON

OSCSTAT

OSCTUNE

PIR2

75

SPLLEN SPLLMULT

IRCF<3:0>

SCS<1:0>

SOSCR

—

PLLRDY

OSTS

HFIOFR

—

LFIOFR

HFIOFS

76

TUNE<6:0>

BCL1IF

77

OSFIF

OSFIE

C2IF

C2IE

C1IF

C1IE

—

USBIF

USBIE

ACTIF

ACTIE

—

98

BCL1IE

PIE2

100

195

T1CON

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN

T1SYNC

TMR1ON

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

TABLE 5-5:

SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

—

FCMEN

PWRTE

IESO

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

13:8

7:0

—

CONFIG1

52

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

DS41639A-page 78

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

6.0

RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

• MCLR Reset

• WDT Reset

• RESETinstruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional Power-up Timer

can be enabled to extend the Reset time after a BOR

or POR event.

A simplified block diagram of the on-chip Reset circuit

is shown in Figure 6-1.

FIGURE 6-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

ICSP™ Programming Mode Exit

RESETInstruction

Stack

Pointer

MCLRE

Sleep

MCLR

WDT

Time-out

Device

Reset

Power-on

Reset

VDD

Brown-out

Reset

PWRT

R

Done

LPBOR

Reset

PWRTE

LFINTOSC

BOR

Active⁽¹⁾

Note 1: See Table 6-1 for BOR active conditions.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 79

PIC16(L)F1454/5/9

6.1

Power-On Reset (POR)

6.2

Brown-Out Reset (BOR)

The POR circuit holds the device in Reset until VDD has

reached an acceptable level for minimum operation.

Slow rising VDD, fast operating speeds or analog

performance may require greater than minimum VDD.

The PWRT, BOR or MCLR features can be used to

extend the start-up period until all device operation

conditions have been met.

The BOR circuit holds the device in Reset when VDD

reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for

execution protection can be implemented.

The Brown-out Reset module has four operating

modes controlled by the BOREN<1:0> bits in Configu-

ration Words. The four operating modes are:

• BOR is always on

6.1.1

POWER-UP TIMER (PWRT)

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

The Power-up Timer provides a nominal 64 ms time-

out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the VDD to

rise to an acceptable level. The Power-up Timer is

enabled by clearing the PWRTE bit in Configuration

Words.

Refer to Table 6-1 for more information.

The Brown-out Reset voltage level is selectable by

configuring the BORV bit in Configuration Words.

A VDD noise rejection filter prevents the BOR from trig-

gering on small events. If VDD falls below VBOR for a

duration greater than parameter TBORDC, the device

will reset. See Figure 6-2 for more information.

The Power-up Timer starts after the release of the POR

and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 6-1:

BOREN<1:0>

11

BOR OPERATING MODES

Instruction Execution upon:

Release of POR or Wake-up from Sleep

SBOREN

Device Mode

BOR Mode

X

Active

Waits for BOR ready⁽¹⁾

(BORRDY = 1)

Awake

Sleep

Active

Disabled

Active

Waits for BOR ready

10

X

1

(BORRDY = 1)

Waits for BOR ready⁽¹⁾

X

(BORRDY = 1)

01

00

0

X

Disabled

Begins immediately

(BORRDY = x)

Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR

circuit is forced on by the BOREN<1:0> bits.

BOR protection is not active during Sleep. The device

wake-up will be delayed until the BOR is ready.

6.2.1

BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are pro-

grammed to ‘11’, the BOR is always on. The device

start-up will be delayed until the BOR is ready and VDD

is higher than the BOR threshold.

6.2.3

BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are

programmed to ‘01’, the BOR is controlled by the

SBOREN bit of the BORCON register. The device

start-up is not delayed by the BOR ready condition or

the VDD level.

BOR protection is active during Sleep. The BOR does

not delay wake-up from Sleep.

6.2.2

BOR IS OFF IN SLEEP

BOR protection begins as soon as the BOR circuit is

ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

When the BOREN bits of Configuration Words are pro-

grammed to ‘10’, the BOR is on, except in Sleep. The

device start-up will be delayed until the BOR is ready

and VDD is higher than the BOR threshold.

BOR protection is unchanged by Sleep.

DS41639A-page 80

Preliminary

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PIC16(L)F1454/5/9

FIGURE 6-2:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

TPWRT

VDD

VBOR

Internal

Reset

< TPWRT

(1)

TPWRT

VDD

VBOR

Internal

Reset

(1)

TPWRT

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

6.3

Register Definitions: BOR Control

REGISTER 6-1:

BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u

SBOREN

bit 7

R/W-0/u

BORFS

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R-q/u

—

BORRDY

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Words = 01:

1= BOR Enabled

0= BOR Disabled

If BOREN <1:0> in Configuration Words  00:

SBOREN is read/write, but has no effect on the BOR.

(1)

BORFS: Brown-out Reset Fast Start bit

If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

1= Band gap is forced on always (covers sleep/wake-up/operating cases)

0= Band gap operates normally, and may turn off

If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)

BORFS is Read/Write, but has no effect.

bit 5-1

bit 0

Unimplemented: Read as ‘0’

BORRDY: Brown-out Reset Circuit Ready Status bit

1= The Brown-out Reset circuit is active

0= The Brown-out Reset circuit is inactive

Note 1: BOREN<1:0> bits are located in Configuration Words.

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Preliminary

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PIC16(L)F1454/5/9

6.4

Low-Power Brown-out Reset

(LPBOR)

6.6

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDTinstruction within the time-out

period. The TO and PD bits in the STATUS register are

changed to indicate the WDT Reset. See Section 10.0

“Watchdog Timer (WDT)” for more information.

The Low-Power Brown-Out Reset (LPBOR) is an

essential part of the Reset subsystem. Refer to

Figure 6-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external VDD pin.

When too low of a voltage is detected, the device is

held in Reset. When this occurs, a register bit (BOR) is

changed to indicate that a BOR Reset has occurred.

The same bit is set for both the BOR and the LPBOR.

Refer to Register 6-2.

6.7

RESET Instruction

A RESETinstruction will cause a device Reset. The RI

bit in the PCON register will be set to ‘0’. See Table 6-4

for default conditions after a RESET instruction has

occurred.

6.4.1

ENABLING LPBOR

6.8

Stack Overflow/Underflow Reset

The LPBOR is controlled by the LPBOR bit of

Configuration Words. When the device is erased, the

LPBOR module defaults to disabled.

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON

register indicate the Reset condition. These Resets are

enabled by setting the STVREN bit in Configuration

Words. See Section 3.5.2 “Overflow/Underflow

Reset” for more information.

6.4.1.1

LPBOR Module Output

The output of the LPBOR module is a signal indicating

whether or not a Reset is to be asserted. This signal is

OR’d together with the Reset signal of the BOR mod-

ule to provide the generic BOR signal which goes to

the PCON register and to the power control block.

6.9

Programming Mode Exit

Upon exit of Programming mode, the device will

behave as if a POR had just occurred.

6.5

MCLR

6.10 Power-Up Timer

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Words and the LVP bit of

Configuration Words (Table 6-2).

The Power-up Timer optionally delays device execution

after a BOR or POR event. This timer is typically used to

allow VDD to stabilize before allowing the device to start

running.

TABLE 6-2:

MCLRE

MCLR CONFIGURATION

The Power-up Timer is controlled by the PWRTE bit of

Configuration Words.

LVP

MCLR

0

1

x

0

1

Disabled

Enabled

6.11 Start-up Sequence

Upon the release of a POR or BOR, the following must

occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. MCLR must be released (if enabled).

6.5.1

MCLR ENABLED

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

The total time-out will vary based on oscillator configu-

ration and Power-up Timer configuration. See

Section 6.0 “Active Clock Tuning (ACT) Module” for

more information.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

The Power-up Timer runs independently of MCLR

Reset. If MCLR is kept low long enough, the Power-up

Timer will expire. Upon bringing MCLR high, the device

will begin execution immediately (see Figure 6-3). This

is useful for testing purposes or to synchronize more

than one device operating in parallel.

Note:

A Reset does not drive the MCLR pin low.

6.5.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 12.3 “PORTA Regis-

ters” for more information.

DS41639A-page 82

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 6-3:

RESET START-UP SEQUENCE

VDD

Internal POR

TPWRT

Power-Up Timer

MCLR

TMCLR

Internal RESET

Internal Oscillator

Oscillator

FOSC

External Clock (EC)

CLKIN

FOSC

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Preliminary

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PIC16(L)F1454/5/9

6.12 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON registers are updated to indicate the cause of

the Reset. Table 6-3 and Table 6-4 show the Reset

conditions of these registers.

TABLE 6-3:

RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR

RI

POR

BOR

TO

PD

Condition

Power-on Reset

0

u

1

u

0

u

1

u

0

u

1

u

0

u

1

u

0

u

0

u

x

0

u

1

0

x

1

0

1

u

1

u

1

x

0

1

u

0

u

0

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

u RESETInstruction Executed

u

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

(2)

TABLE 6-4:

RESET CONDITION FOR SPECIAL REGISTERS

Program

STATUS

Register

PCON

Register

Condition

Counter

Power-on Reset

0000h

---1 1000

---u uuuu

00-- 110x

uu-- 0uuu

MCLR Reset during normal operation

0000h

MCLR Reset during Sleep

WDT Reset

0000h

---1 0uuu

---0 uuuu

---0 0uuu

---1 1uuu

---1 0uuu

---u uuuu

uu-- 0uuu

uu-- uuuu

00-- 11u0

uu-- uuuu

uu-- u0uu

1u-- uuuu

u1-- uuuu

WDT Wake-up from Sleep

Brown-out Reset

PC + 1

0000h

Interrupt Wake-up from Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

PC + 1⁽¹⁾

0000h

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is

pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

DS41639A-page 84

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

6.13 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

• MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON register bits are shown in Register 6-2.

6.14 Register Definitions: Power Control

REGISTER 6-2:

PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q

U-0

—

R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF

bit 7

STKUNF

RWDT

RMCLR

RI

POR

BOR

bit 0

Legend:

HC = Bit is cleared by hardware

HS = Bit is set by hardware

U = Unimplemented bit, read as ‘0’

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

STKOVF: Stack Overflow Flag bit

1= A Stack Overflow occurred

0= A Stack Overflow has not occurred or cleared by firmware

STKUNF: Stack Underflow Flag bit

1= A Stack Underflow occurred

0= A Stack Underflow has not occurred or cleared by firmware

bit 5

bit 4

Unimplemented: Read as ‘0’

RWDT: Watchdog Timer Reset Flag bit

1= A Watchdog Timer Reset has not occurred or set by firmware

0= A Watchdog Timer Reset has occurred (cleared by hardware)

bit 3

bit 2

bit 1

bit 0

RMCLR: MCLR Reset Flag bit

1= A MCLR Reset has not occurred or set by firmware

0= A MCLR Reset has occurred (cleared by hardware)

RI: RESETInstruction Flag bit

1= A RESETinstruction has not been executed or set by firmware

0= A RESETinstruction has been executed (cleared by hardware)

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

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PIC16(L)F1454/5/9

TABLE 6-5:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BORCON SBOREN BORFS

—

RWDT

TO

—

RMCLR

PD

—

RI

Z

—

POR

DC

BORRDY

BOR

81

85

PCON

STKOVF STKUNF

STATUS

WDTCON

—

C

27

WDTPS<4:0>

SWDTEN

110

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

TABLE 6-6:

SUMMARY OF CONFIGURATION WORD WITH RESETS

Register

on Page

Name

Bits Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

FCMEN

PWRTE

LVP

IESO

13:8

7:0

—

CP

—

MCLRE

—

CLKOUTEN

BOREN<1:0>

—

CONFIG1

52

54

FOSC<2:0>

STVREN

WDTE<1:0>

PLLEN

13:8

7:0

DEBUG

LPBOR

—

BORV

—

CONFIG2

PLLMULT USBLSCLK

CPUDIV<1:0>

WRT<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

DS41639A-page 86

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PIC16(L)F1454/5/9

7.3

Conflicts with the CLKR Pin

7.0

REFERENCE CLOCK MODULE

There are two cases when the reference clock output

signal cannot be output to the CLKR pin, if:

The reference clock module provides the ability to send

a divided clock to the clock output pin of the device

(CLKR). This module is available in all oscillator config-

urations and allows the user to select a greater range

of clock submultiples to drive external devices in the

application. The reference clock module includes the

following features:

• LP, XT or HS Oscillator mode is selected.

• CLKOUT function is enabled.

7.3.1

OSCILLATOR MODES

If LP, XT or HS Oscillator modes are selected, the

OSC2/CLKR pin must be used as an oscillator input pin

and the CLKR output cannot be enabled. See

Section 5.2 “Clock Source Types” for more informa-

tion on different oscillator modes.

• System clock is the source

• Available in all oscillator configurations

• Programmable clock divider

• Output enable to a port pin

• Selectable duty cycle

7.3.2

CLKOUT FUNCTION

• Slew rate control

The CLKOUT function has a higher priority than the ref-

erence clock module. Therefore, if the CLKOUT func-

tion is enabled by the CLKOUTEN bit in Configuration

Words, FOSC/4 will always be output on the port pin.

Reference Section 4.0 “Device Configuration” for

more information.

The reference clock module is controlled by the

CLKRCON register (Register 7-1) and is enabled when

setting the CLKREN bit. To output the divided clock sig-

nal to the CLKR port pin, the CLKROE bit must be set.

The CLKRDIV<2:0> bits enable the selection of eight

different clock divider options. The CLKRDC<1:0> bits

can be used to modify the duty cycle of the output

clock⁽¹⁾. The CLKRSLR bit controls slew rate limiting.

7.4

Operation During Sleep

As the reference clock module relies on the system

clock as its source, and the system clock is disabled in

Sleep, the module does not function in Sleep, even if

an external clock source or the Timer1 clock source is

configured as the system clock. The module outputs

will remain in their current state until the device exits

Sleep.

Note 1: If the base clock rate is selected without

a divider, the output clock will always

have a duty cycle equal to that of the

source clock, unless a 0% duty cycle is

selected. If the clock divider is set to base

clock/2, then 25% and 75% duty cycle

accuracy will be dependent upon the

source clock.

7.1

Slew Rate

The slew rate limitation on the output port pin can be

disabled. The slew rate limitation can be removed by

clearing the CLKRSLR bit in the CLKRCON register.

7.2

Effects of a Reset

Upon any device Reset, the reference clock module is

disabled. The user's firmware is responsible for

initializing the module before enabling the output. The

registers are reset to their default values.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 87

PIC16(L)F1454/5/9

7.5

Register Definition: Reference Clock Control

REGISTER 7-1:

CLKRCON: REFERENCE CLOCK CONTROL REGISTER

R/W-0/0

CLKREN

bit 7

R/W-0/0

R/W-1/1

R/W-0/0

CLKROE

CLKRSLR

CLKRDC<1:0>

CLKRDIV<2:0>

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CLKREN: Reference Clock Module Enable bit

1= Reference clock module is enabled

0= Reference clock module is disabled

bit 6

CLKROE: Reference Clock Output Enable bit⁽³⁾

1= Reference clock output is enabled on CLKR pin

0= Reference clock output disabled on CLKR pin

bit 5

CLKRSLR: Reference Clock Slew Rate Control limiting enable bit

1= Slew rate limiting is enabled

0= Slew rate limiting is disabled

bit 4-3

CLKRDC<1:0>: Reference Clock Duty Cycle bits

11= Clock outputs duty cycle of 75%

10= Clock outputs duty cycle of 50%

01= Clock outputs duty cycle of 25%

00= Clock outputs duty cycle of 0%

bit 2-0

CLKRDIV<2:0> Reference Clock Divider bits

111= Base clock value divided by 128

110= Base clock value divided by 64

101= Base clock value divided by 32

100= Base clock value divided by 16

011= Base clock value divided by 8

010= Base clock value divided by 4

001= Base clock value divided by 2⁽¹⁾

000= Base clock value⁽²⁾

Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.

2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%

is selected.

3: To route CLKR to pin, CLKOUTEN of Configuration Words = 1is required. CLKOUTEN of Configuration

Words = 0will result in FOSC/4. See Section 7.3 “Conflicts with the CLKR Pin” for details.

DS41639A-page 88

Preliminary

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PIC16(L)F1454/5/9

TABLE 7-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

CLKRCON

CLKREN

CLKROE CLKRSLR

CLKRDC<1:0>

CLKRDIV<2:0>

88

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

TABLE 7-2:

SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

CPD

CONFIG1

52

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 89

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 90

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

8.0

INTERRUPTS

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

This chapter contains the following information for

Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

• INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the

corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 8-1.

FIGURE 8-1:

INTERRUPT LOGIC

TMR0IF

TMR0IE

Wake-up

(If in Sleep mode)

INTF

INTE

Peripheral Interrupts

(TMR1IF) PIR1<0>

IOCIF

IOCIE

Interrupt

to CPU

(TMR1IF) PIR1<0>

PEIE

GIE

PIRn<7>

PIEn<7>

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Preliminary

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PIC16(L)F1454/5/9

8.1

Operation

8.2

Interrupt Latency

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The latency for synchronous

interrupts is three or four instruction cycles. For asyn-

chronous interrupts, the latency is three to five instruc-

tion cycles, depending on when the interrupt occurs.

See Figure 8-2 and Figure 8.3 for more details.

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIE1 and PIE2 registers)

The INTCON, PIR1 and PIR2 registers record individ-

ual interrupts via interrupt flag bits. Interrupt flag bits will

be set, regardless of the status of the GIE, PEIE and

individual interrupt enable bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

shadow registers (See “Section 8.5 “Automatic

Context Saving”.”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

DS41639A-page 92

Preliminary

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PIC16(L)F1454/5/9

FIGURE 8-2:

INTERRUPT LATENCY

Fosc

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKR

Interrupt Sampled

during Q1

Interrupt

GIE

PC-1

PC

PC+1

0004h

0005h

PC

1 Cycle Instruction at PC

Execute

Inst(PC)

NOP

Inst(0004h)

Interrupt

GIE

PC+1/FSR

ADDR

New PC/

PC+1

PC-1

PC

0004h

0005h

PC

Execute

2 Cycle Instruction at PC

Inst(PC)

NOP

Inst(0004h)

Interrupt

GIE

PC-1

PC

FSR ADDR

INST(PC)

PC+1

PC+2

0004h

0005h

PC

Execute

3 Cycle Instruction at PC

NOP

Inst(0004h)

Inst(0005h)

Interrupt

GIE

PC-1

PC

FSR ADDR

INST(PC)

PC+1

PC+2

0004h

0005h

PC

NOP

Execute

3 Cycle Instruction at PC

NOP

Inst(0004h)

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 93

PIC16(L)F1454/5/9

FIGURE 8-3:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(3)

CLKOUT

(4)

INT pin

INTF

(1)

(2)

(5)

Interrupt Latency

GIE

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Forced NOP

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

DS41639A-page 94

Preliminary

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PIC16(L)F1454/5/9

8.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEPinstruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to Section 9.0 “Power-

Down Mode (Sleep)” for more details.

8.4

INT Pin

The INT pin can be used to generate an asynchronous

edge-triggered interrupt. This interrupt is enabled by

setting the INTE bit of the INTCON register. The

INTEDG bit of the OPTION_REG register determines on

which edge the interrupt will occur. When the INTEDG

bit is set, the rising edge will cause the interrupt. When

the INTEDG bit is clear, the falling edge will cause the

interrupt. The INTF bit of the INTCON register will be set

when a valid edge appears on the INT pin. If the GIE and

INTE bits are also set, the processor will redirect

program execution to the interrupt vector.

8.5

Automatic Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these regis-

ters are automatically restored. Any modifications to

these registers during the ISR will be lost. If modifica-

tions to any of these registers are desired, the corre-

sponding shadow register should be modified and the

value will be restored when exiting the ISR. The

shadow registers are available in Bank 31 and are

readable and writable. Depending on the user’s appli-

cation, other registers may also need to be saved.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 95

PIC16(L)F1454/5/9

8.6

Register Definitions: Interrupt Control

REGISTER 8-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

GIE

R/W-0/0

PEIE

R/W-0/0

TMR0IE

R/W-0/0

INTE

R/W-0/0

IOCIE

R/W-0/0

TMR0IF

R/W-0/0

INTF

R-0/0

IOCIF⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

GIE: Global Interrupt Enable bit

1= Enables all active interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit

1= Enables all active peripheral interrupts

0= Disables all peripheral interrupts

TMR0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: INT External Interrupt Enable bit

1= Enables the INT external interrupt

0= Disables the INT external interrupt

IOCIE: Interrupt-on-Change Enable bit

1= Enables the interrupt-on-change

0= Disables the interrupt-on-change

TMR0IF: Timer0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed

0= TMR0 register did not overflow

INTF: INT External Interrupt Flag bit

1= The INT external interrupt occurred

0= The INT external interrupt did not occur

IOCIF: Interrupt-on-Change Interrupt Flag bit⁽¹⁾

1= When at least one of the interrupt-on-change pins changed state

0= None of the interrupt-on-change pins have changed state

Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register

have been cleared by software.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

DS41639A-page 96

Preliminary

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PIC16(L)F1454/5/9

REGISTER 8-2:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0

TMR1GIE

bit 7

R/W-0/0

ADIE⁽¹⁾

R/W-0/0

RCIE

R/W-0/0

TXIE

R/W-0/0

SSP1IE

U-0

—

R/W-0/0

TMR2IE

R/W-0/0

TMR1IE

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

TMR1GIE: Timer1 Gate Interrupt Enable bit

1= Enables the Timer1 gate acquisition interrupt

0= Disables the Timer1 gate acquisition interrupt

ADIE: A/D Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1= Enables the MSSP interrupt

0= Disables the MSSP interrupt

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

bit 0

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

Note 1: PIC16(L)F1455/9 only.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 97

PIC16(L)F1454/5/9

REGISTER 8-3:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

OSFIE

bit 7

R/W-0/0

C2IE

R/W-0/0

C1IE

U-0

—

R/W-0/0

BCL1IE

R/W-0/0

USBIE

R/W-0/0

ACTIE

U-0

—

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

bit 5

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enables the Oscillator Fail interrupt

0= Disables the Oscillator Fail interrupt

C2IE: Comparator C2 Interrupt Enable bit

1= Enables the Comparator C2 interrupt

0= Disables the Comparator C2 interrupt

C1IE: Comparator C1 Interrupt Enable bit

1= Enables the Comparator C1 interrupt

0= Disables the Comparator C1 interrupt

bit 4

bit 3

Unimplemented: Read as ‘0’

BCL1IE: MSSP Bus Collision Interrupt Enable bit

1= Enables the MSSP Bus Collision Interrupt

0= Disables the MSSP Bus Collision Interrupt

bit 2

bit 1

bit 0

USBIE: USB Interrupt Enable bit

1= Enables the USB interrupt

0= Disables the USB interrupt

ACTIE: Active Clock Tuning Interrupt Enable bit

1= Enables the Active Clock Tuning interrupt

0= Disables the Active Clock Tuning interrupt

Unimplemented: Read as ‘0’

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

DS41639A-page 98

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 8-4:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0

TMR1GIF

bit 7

R/W-0/0

ADIF⁽¹⁾

R/W-0/0

RCIF

R/W-0/0

TXIF

R/W-0/0

SSP1IF

U-0

—

R/W-0/0

TMR2IF

R/W-0/0

TMR1IF

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

TMR1GIF: Timer1 Gate Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

ADIF: A/D Converter Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

RCIF: USART Receive Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

TXIF: USART Transmit Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR2IF: Timer2 to PR2 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 0

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

Note 1: PIC16(L)F1455/9 only.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 99

PIC16(L)F1454/5/9

REGISTER 8-5:

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

OSFIF

R/W-0/0

C2IF

R/W-0/0

C1IF

U-0

—

R/W-0/0

BCL1IF

R/W-0/0

USBIF

R/W-0/0

ACTIF

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

bit 5

OSFIF: Oscillator Fail Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

C2IF: Numerically Controlled Oscillator Flag bit

1= Interrupt is pending

0= Interrupt is not pending

C1IF: Numerically Controlled Oscillator Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 4

bit 3

Unimplemented: Read as ‘0’

BCL1IF: MSSP Bus Collision Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 2

bit 1

bit 0

USBIF: USB Flag bit

1= Interrupt is pending

0= Interrupt is not pending

ACTIF: Active Clock Tuning Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

Unimplemented: Read as ‘0’

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

DS41639A-page 100

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 8-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

PSA

TMR0IF

INTF

IOCIF

96

185

97

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE

PS<2:0>

PIE1

PIE2

PIR1

PIR2

TMR1GIE ADIE⁽¹⁾

OSFIE C2IE

TMR1GIF ADIF⁽¹⁾

OSFIF C2IF

RCIE

C1IE

RCIF

C1IF

TXIE

—

SSP1IE

BCL1IE

SSP1IF

BCL1IF

—

TMR2IE TMR1IE

ACTIE

TMR2IF TMR1IF

ACTIF

USBIE

—

98

TXIF

—

99

USBIF

—

100

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

Note 1: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 101

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 102

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

9.1

Wake-up from Sleep

9.0

POWER-DOWN MODE (SLEEP)

The device can wake-up from Sleep through one of the

following events:

The Power-Down mode is entered by executing a

SLEEPinstruction.

1. External Reset input on MCLR pin, if enabled

2. BOR Reset, if enabled

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

2. PD bit of the STATUS register is cleared.

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

6. Interrupts by peripherals capable of running dur-

ing Sleep (see individual peripheral for more

information)

5. 31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in

Sleep.

The first three events will cause a device Reset. The

last three events are considered a continuation of pro-

gram execution. To determine whether a device Reset

or wake-up event occurred, refer to Section 6.12

“Determining the Cause of a Reset”.

6. ADC is unaffected, if the dedicated FRC clock is

selected.

7. I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or high-

impedance).

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEPinstruction, the device will then call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

8. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following

conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

• CWG module using HFINTOSC

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching

currents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include the FVR module. See Section 14.0

“Fixed Voltage Reference (FVR) (PIC16(L)F1455/9

only)” for more information on this module.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 103

PIC16(L)F1454/5/9

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

9.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEPinstruction

- SLEEPinstruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

- PD bit of the STATUS register will not be

cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction

- SLEEPinstruction will be completely exe-

cuted

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared

FIGURE 9-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN⁽¹⁾

(3)

CLKOUT⁽²⁾

T1OSC

Interrupt Latency⁽⁴⁾

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Forced NOP

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

External clock. High, Medium, Low mode assumed.

CLKOUT is shown here for timing reference.

T1OSC; See Section 29.0 “Electrical Specifications”.

GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

2:

3:

4:

DS41639A-page 104

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

9.2.2

PERIPHERAL USAGE IN SLEEP

9.2

Low-Power Sleep Mode

Some peripherals that can operate in Sleep mode will

not operate properly with the Low-Power Sleep mode

selected. The LDO will remain in the Normal-Power

mode when those peripherals are enabled. The Low-

Power Sleep mode is intended for use with these

peripherals:

The PIC16F1454/5/9 device contains an internal Low

Dropout (LDO) voltage regulator, which allows the

device I/O pins to operate at voltages up to 5.5V while

the internal device logic operates at a lower voltage.

The LDO and its associated reference circuitry must

remain active when the device is in Sleep mode. The

PIC16F1454/5/9 allows the user to optimize the

operating current in Sleep, depending on the

application requirements.

• Brown-Out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/Interrupt-on-change pins

• Timer1 (with external clock source)

A Low-Power Sleep mode can be selected by setting

the VREGPM bit of the VREGCON register. With this

bit set, the LDO and reference circuitry are placed in a

low-power state when the device is in Sleep.

The Complementary Waveform Generator (CWG)

module can utilize the HFINTOSC oscillator as either

a clock source or as an input source. Under certain

conditions, when the HFINTOSC is selected for use

with the CWG module, the HFINTOSC will remain

active during Sleep. This will have a direct effect on

the Sleep mode current.

9.2.1

SLEEP CURRENT VS. WAKE-UP

TIME

In the default operating mode, the LDO and reference

circuitry remain in the normal configuration while in

Sleep. The device is able to exit Sleep mode quickly

since all circuits remain active. In Low-Power Sleep

mode, when waking up from Sleep, an extra delay time

is required for these circuits to return to the normal con-

figuration and stabilize.

Please refer to section 25.10 “Operation During

Sleep” for more information.

Note:

The PIC16LF1454/5/9 does not have a

configurable Low-Power Sleep mode.

PIC16LF1454/5/9 is an unregulated

device and is always in the lowest power

state when in Sleep, with no wake-up time

penalty. This device has a lower maximum

VDD and I/O voltage than the

PIC16LF1454/5/9. See Section 29.0

“Electrical Specifications” for more

information.

The Low-Power Sleep mode is beneficial for applica-

tions that stay in Sleep mode for long periods of time.

The Normal mode is beneficial for applications that

need to wake from Sleep quickly and frequently.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 105

PIC16(L)F1454/5/9

9.3

Register Definitions: Voltage Regulator Control

(1)

REGISTER 9-1:

VREGCON: VOLTAGE REGULATOR CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

R/W-1/1

VREGPM

Reserved

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-2

bit 1

Unimplemented: Read as ‘0’

VREGPM: Voltage Regulator Power Mode Selection bit

1= Low-Power Sleep mode enabled in Sleep⁽²⁾

Draws lowest current in Sleep, slower wake-up

0= Normal-Power mode enabled in Sleep⁽²⁾

Draws higher current in Sleep, faster wake-up

bit 0

Reserved: Read as ‘1’. Maintain this bit set.

Note 1: PIC16LF1454/5/9 only.

2: See Section 29.0 “Electrical Specifications”.

TABLE 9-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on

Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

IOCAF

GIE

—

PEIE

—

TMR0IE

INTE

IOCIE

TMR0IF

—

INTF

IOCIF

96

IOCAF5 IOCAF4 IOCAF3

IOCAN5 IOCAN4 IOCAN3

IOCAP5 IOCAP4 IOCAP3

IOCAF1 IOCAF0

IOCAN1 IOCAN0

IOCAP1 IOCAP0

146

145

147

146

IOCAN

IOCAP

IOCBF⁽²⁾

—

IOCBF7 IOCBF6 IOCBF5 IOCBF4

—

IOCBN⁽²⁾IOCBN7 IOCBN6 IOCBN5 IOCBN4

IOCBP⁽²⁾

—

IOCBP7 IOCBP6 IOCBP5 IOCBP4

—

PIE1

TMR1GIE ADIE⁽¹⁾

OSFIE C2IE

TMR1GIF ADIF⁽¹⁾

RCIE

C1IE

RCIF

C1IF

—

TXIE

—

SSP1IE

BCL1IE

SSP1IF

BCL1IF

PD

—

TMR2IE TMR1IE

ACTIE

TMR2IF TMR1IF

97

98

PIE2

USBIE

—

PIR1

TXIF

—

99

PIR2

OSFIF

—

C2IF

—

USBIF

Z

ACTIF

DC

—

C

100

27

STATUS

WDTCON

TO

—

WDTPS<4:0>

SWDTEN

110

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.

Note 1: PIC16(L)F1455/9 only.

2: PIC16(L)F1459 only.

DS41639A-page 106

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PIC16(L)F1454/5/9

10.0 WATCHDOG TIMER (WDT)

The Watchdog Timer is a system timer that generates

a Reset if the firmware does not issue a CLRWDT

instruction within the time-out period. The Watchdog

Timer is typically used to recover the system from

unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (nominal)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 10-1:

WATCHDOG TIMER BLOCK DIAGRAM

WDTE<1:0> = 01

SWDTEN

23-bit Programmable

WDT Time-out

WDTE<1:0> = 11

LFINTOSC

Prescaler WDT

WDTE<1:0> = 10

Sleep

WDTPS<4:0>

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 107

PIC16(L)F1454/5/9

10.1 Independent Clock Source

10.4 Clearing the WDT

The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator. Time intervals in this

chapter are based on a nominal interval of 1 ms. See

Section 29.0 “Electrical Specifications” for the

LFINTOSC tolerances.

The WDT is cleared when any of the following condi-

tions occur:

• Any Reset

• CLRWDTinstruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail

10.2 WDT Operating Modes

The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration

Words. See Table 10-1.

• WDT is disabled

• Oscillator Start-up Timer (OST) is running

See Table 10-2 for more information.

10.2.1

WDT IS ALWAYS ON

10.5 Operation During Sleep

When the WDTE bits of Configuration Words are set to

‘11’, the WDT is always on.

When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes

counting.

WDT protection is active during Sleep.

10.2.2

WDT IS OFF IN SLEEP

When the device exits Sleep, the WDT is cleared

again. The WDT remains clear until the OST, if

enabled, completes. See Section 5.0 “Oscillator

Module (With Fail-Safe Clock Monitor)” for more

information on the OST.

When the WDTE bits of Configuration Words are set to

‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

10.2.3

WDT CONTROLLED BY SOFTWARE

The WDT remains clear until the OST, if enabled, com-

pletes. See Section 5.0 “Oscillator Module (With

Fail-Safe Clock Monitor)” for more information on the

OST. (add with start-up timer oscillators)

When the WDTE bits of Configuration Words are set to

‘01’, the WDT is controlled by the SWDTEN bit of the

WDTCON register.

WDT protection is unchanged by Sleep. See

Table 10-1 for more details.

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits

in the STATUS register are changed to indicate the

event. The RWDT bit in the PCON register can also be

used. See Section 3.0 “Memory Organization” for

more information.

TABLE 10-1: WDT OPERATING MODES

Device

Mode

WDT

Mode

WDTE<1:0>

SWDTEN

11

10

X

Active

Awake

Sleep Disabled

1

0

X

Active

X

01

00

Disabled

X

Disabled

10.3 Time-Out Period

The WDTPS bits of the WDTCON register set the

time-out period from 1 ms to 256 seconds (nominal).

After a Reset, the default time-out period is two

seconds.

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TABLE 10-2: WDT CLEARING CONDITIONS

Conditions

WDT

WDTE<1:0> = 00

WDTE<1:0> = 01 and SWDTEN = 0

WDTE<1:0> = 10 and enter Sleep

CLRWDTCommand

Cleared

Oscillator Fail Detected

Exit Sleep + System Clock = EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Change INTOSC divider (IRCF bits)

Cleared until the end of OST

Unaffected

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10.6 Register Definitions: Watchdog Control

REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

R/W-0/0

R/W-1/1

R/W-0/0

R/W-1/1

R/W-0/0

WDTPS<4:0>

SWDTEN

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-1

Unimplemented: Read as ‘0’

WDTPS<4:0>: Watchdog Timer Period Select bits⁽¹⁾

Bit Value = Prescale Rate

00000 = 1:32 (Interval 1 ms nominal)

00001 = 1:64 (Interval 2 ms nominal)

00010 = 1:128 (Interval 4 ms nominal)

00011 = 1:256 (Interval 8 ms nominal)

00100 = 1:512 (Interval 16 ms nominal)

00101 = 1:1024 (Interval 32 ms nominal)

00110 = 1:2048 (Interval 64 ms nominal)

00111 = 1:4096 (Interval 128 ms nominal)

01000 = 1:8192 (Interval 256 ms nominal)

01001 = 1:16384 (Interval 512 ms nominal)

01010 = 1:32768 (Interval 1s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value)

01100 = 1:131072 (2¹⁷) (Interval 4s nominal)

01101 = 1:262144 (2¹⁸) (Interval 8s nominal)

01110 = 1:524288 (2¹⁹) (Interval 16s nominal)

01111 = 1:1048576 (2²⁰) (Interval 32s nominal)

10000 = 1:2097152 (2²¹) (Interval 64s nominal)

10001 = 1:4194304 (2²²) (Interval 128s nominal)

10010 = 1:8388608 (2²³) (Interval 256s nominal)

10011 = Reserved. Results in minimum interval (1:32)

•

11111 = Reserved. Results in minimum interval (1:32)

bit 0

SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = 00:

This bit is ignored.

If WDTE<1:0> = 01:

1= WDT is turned on

0= WDT is turned off

If WDTE<1:0> = 1x:

This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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TABLE 10-3:

SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON

PCON

SPLLEN SPLLMULT

IRCF<3:0>

SCS<1:0>

75

85

STKOVF

STKUNF

—

RWDT

TO

RMCLR

PD

RI

Z

POR

DC

BOR

C

STATUS

WDTCON

—

27

WDTPS<4:0>

SWDTEN

110

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

FCMEN

PWRTE

IESO

13:8

7:0

—

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

—

CONFIG1

52

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

 2012 Microchip Technology Inc.

Preliminary

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PIC16(L)F1454/5/9

11.1.1

PMCON1 AND PMCON2

REGISTERS

11.0 FLASH PROGRAM MEMORY

CONTROL

PMCON1 is the control register for Flash program

memory accesses.

The Flash program memory is readable and writable

during normal operation over the full VDD range.

Program memory is indirectly addressed using Special

Function Registers (SFRs). The SFRs used to access

program memory are:

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared by hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

• PMCON1

• PMCON2

• PMDATL

• PMDATH

• PMADRL

• PMADRH

The WREN bit, when set, will allow a write operation to

occur. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted

by a Reset during normal operation. In these situations,

following Reset, the user can check the WRERR bit

and execute the appropriate error handling routine.

When accessing the program memory, the

PMDATH:PMDATL register pair forms a 2-byte word

that holds the 14-bit data for read/write, and the

PMADRH:PMADRL register pair forms a 2-byte word

that holds the 15-bit address of the program memory

location being read.

The PMCON2 register is a write-only register. Attempting

to read the PMCON2 register will return all ‘0’s.

To enable writes to the program memory, a specific

pattern (the unlock sequence), must be written to the

PMCON2 register. The required unlock sequence

prevents inadvertent writes to the program memory

write latches and Flash program memory.

The write time is controlled by an on-chip timer. The write/

erase voltages are generated by an on-chip charge pump

rated to operate over the operating voltage range of the

device.

11.2 Flash Program Memory Overview

The Flash program memory can be protected in two

ways; by code protection (CP bit in Configuration Words)

and write protection (WRT<1:0> bits in Configuration

Words).

Code protection (CP = 0)⁽¹⁾, disables access, reading

and writing, to the Flash program memory via external

device programmers. Code protection does not affect

the self-write and erase functionality. Code protection

can only be reset by a device programmer performing

a Bulk Erase to the device, clearing all Flash program

memory, Configuration bits and User IDs.

It is important to understand the Flash program memory

structure for erase and programming operations. Flash

program memory is arranged in rows. A row consists of

a fixed number of 14-bit program memory words. A row

is the minimum size that can be erased by user software.

After a row has been erased, the user can reprogram

all or a portion of this row. Data to be written into the

program memory row is written to 14-bit wide data write

latches. These write latches are not directly accessible

to the user, but may be loaded via sequential writes to

the PMDATH:PMDATL register pair.

Write protection prohibits self-write and erase to a

portion or all of the Flash program memory as defined

by the bits WRT<1:0>. Write protection does not affect

a device programmers ability to read, write or erase the

device.

Note:

If the user wants to modify only a portion

of a previously programmed row, then the

contents of the entire row must be read

and saved in RAM prior to the erase.

Then, new data and retained data can be

written into the write latches to reprogram

the row of Flash program memory. How-

ever, any unprogrammed locations can be

written without first erasing the row. In this

case, it is not necessary to save and

rewrite the other previously programmed

locations.

Note 1: Code protection of the entire Flash

program memory array is enabled by

clearing the CP bit of Configuration Words.

11.1 PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up

to a maximum of 32K words of program memory. When

selecting a program address value, the MSB of the

address is written to the PMADRH register and the LSB

is written to the PMADRL register.

See Table 11-1 for Erase Row size and the number of

write latches for Flash program memory.

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FIGURE 11-1:

FLASH PROGRAM

MEMORY READ

FLOWCHART

TABLE 11-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Write

Latches

(words)

Row Erase

(words)

Device

Start

Read Operation

PIC16(L)F1454/5/9

32

Select

Program or Configuration Memory

(CFGS)

11.2.1

READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must:

1. Write the desired address to the

PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register.

Select

Word Address

(PMADRH:PMADRL)

3. Then, set control bit RD of the PMCON1 register.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to

read the data. This causes the second instruction

immediately following the “BSF PMCON1,RD” instruction

to be ignored. The data is available in the very next cycle,

in the PMDATH:PMDATL register pair; therefore, it can

be read as two bytes in the following instructions.

Initiate Read operation

(RD = 1)

Instruction Fetched ignored

NOPexecution forced

PMDATH:PMDATL register pair will hold this value until

another read or until it is written to by the user.

Instruction Fetched ignored

Note:

The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

two-cycle instruction on the next

instruction after the RD bit is set.

NOPexecution forced

Data read now in

PMDATH:PMDATL

End

Read Operation

 2012 Microchip Technology Inc.

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DS41639A-page 113

PIC16(L)F1454/5/9

FIGURE 11-2:

FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

PC + 1

PMADRH,PMADRL

PC + 3

PC+3

PC + 4

PC + 5

Flash ADDR

Flash Data

INSTR (PC)

INSTR (PC + 1)

PMDATH,PMDATL

INSTR (PC + 3)

INSTR (PC + 4)

INSTR(PC + 1)

INSTR(PC + 2)

instruction ignored instruction ignored

BSF PMCON1,RD

executed here

INSTR(PC - 1)

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

Forced NOP

executed here

RD bit

PMDATH

PMDATL

Register

EXAMPLE 11-1:

FLASH PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI: PROG_ADDR_LO

*

data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL

; Select Bank for PMCON registers

MOVLW

MOVWF

MOVLW

MOVWF

PROG_ADDR_LO

PMADRL

PROG_ADDR_HI

PMADRH

;

; Store LSB of address

;

; Store MSB of address

BCF

BSF

NOP

PMCON1,CFGS

PMCON1,RD

; Do not select Configuration Space

; Initiate read

; Ignored (Figure 11-2)

MOVF

PMDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

PMDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

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PIC16(L)F1454/5/9

11.2.2

FLASH MEMORY UNLOCK

SEQUENCE

FIGURE 11-3:

FLASH PROGRAM

MEMORY UNLOCK

SEQUENCE FLOWCHART

The unlock sequence is a mechanism that protects the

Flash program memory from unintended self-write pro-

gramming or erasing. The sequence must be executed

and completed without interruption to successfully

complete any of the following operations:

Start

Unlock Sequence

• Row Erase

• Load program memory write latches

Write 055h to

PMCON2

• Write of program memory write latches to pro-

gram memory

• Write of program memory write latches to User

IDs

Write 0AAh to

PMCON2

The unlock sequence consists of the following steps:

1. Write 55h to PMCON2

Initiate

Write or Erase operation

(WR = 1)

2. Write AAh to PMCON2

3. Set the WR bit in PMCON1

4. NOPinstruction

5. NOPinstruction

Instruction Fetched ignored

NOP execution forced

Once the WR bit is set, the processor will always force

two NOP instructions. When an Erase Row or Program

Row operation is being performed, the processor will stall

internal operations (typical 2 ms), until the operation is

complete and then resume with the next instruction.

When the operation is loading the program memory write

latches, the processor will always force the two NOP

instructions and continue uninterrupted with the next

instruction.

Instruction Fetched ignored

NOPexecution forced

End

Unlock Sequence

Since the unlock sequence must not be interrupted,

global interrupts should be disabled prior to the unlock

sequence and re-enabled after the unlock sequence is

completed.

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Preliminary

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11.2.3

ERASING FLASH PROGRAM

MEMORY

FIGURE 11-4:

FLASH PROGRAM

MEMORY ERASE

FLOWCHART

While executing code, program memory can only be

erased by rows. To erase a row:

1. Load the PMADRH:PMADRL register pair with

any address within the row to be erased.

Start

Erase Operation

2. Clear the CFGS bit of the PMCON1 register.

3. Set the FREE and WREN bits of the PMCON1

register.

Disable Interrupts

(GIE = 0)

4. Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

5. Set control bit WR of the PMCON1 register to

begin the erase operation.

Select

Program or Configuration Memory

(CFGS)

See Example 11-2.

After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The

user must place two NOPinstructions immediately fol-

lowing the WR bit set instruction. The processor will

halt internal operations for the typical 2 ms erase time.

This is not Sleep mode as the clocks and peripherals

will continue to run. After the erase cycle, the processor

will resume operation with the third instruction after the

PMCON1 write instruction.

Select Row Address

(PMADRH:PMADRL)

Select Erase Operation

(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence

Figure 11-3

(FIGURE x x)

CPU stalls while

Erase operation completes

(2ms typical)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

DS41639A-page 116

Preliminary

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PIC16(L)F1454/5/9

EXAMPLE 11-2:

ERASING ONE ROW OF PROGRAM MEMORY

; This row erase routine assumes the following:

; 1. A valid address within the erase row is loaded in ADDRH:ADDRL

; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF

INTCON,GIE

PMADRL

ADDRL,W

PMADRL

ADDRH,W

; Disable ints so required sequences will execute properly

; Load lower 8 bits of erase address boundary

; Load upper 6 bits of erase address boundary

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

BCF

PMADRH

PMCON1,CFGS

PMCON1,FREE

PMCON1,WREN

; Not configuration space

; Specify an erase operation

; Enable writes

BSF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required sequence to initiate erase

; Write 55h

;

; Write AAh

; Set WR bit to begin erase

NOP

; NOP instructions are forced as processor starts

; row erase of program memory.

;

; The processor stalls until the erase process is complete

; after erase processor continues with 3rd instruction

BCF

BSF

PMCON1,WREN

INTCON,GIE

; Disable writes

; Enable interrupts

 2012 Microchip Technology Inc.

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DS41639A-page 117

PIC16(L)F1454/5/9

The following steps should be completed to load the

write latches and program a row of program memory.

These steps are divided into two parts. First, each write

latch is loaded with data from the PMDATH:PMDATL

using the unlock sequence with LWLO = 1. When the

last word to be loaded into the write latch is ready, the

LWLO bit is cleared and the unlock sequence

executed. This initiates the programming operation,

writing all the latches into Flash program memory.

11.2.4

WRITING TO FLASH PROGRAM

MEMORY

Program memory is programmed using the following

steps:

1. Load the address in PMADRH:PMADRL of the

row to be programmed.

2. Load each write latch with data.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

Note:

The special unlock sequence is required

to load a write latch with data or initiate a

Flash programming operation. If the

unlock sequence is interrupted, writing to

the latches or program memory will not be

initiated.

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten. Pro-

gram memory can only be erased one row at a time. No

automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at

a time. The maximum number of words written at one

time is equal to the number of write latches. See

Figure 11-5 (row writes to program memory with 32

write latches) for more details.

1. Set the WREN bit of the PMCON1 register.

2. Clear the CFGS bit of the PMCON1 register.

3. Set the LWLO bit of the PMCON1 register.

When the LWLO bit of the PMCON1 register is

‘1’, the write sequence will only load the write

latches and will not initiate the write to Flash

program memory.

The write latches are aligned to the Flash row address

boundary defined by the upper 10-bits of

PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)

with the lower 5-bits of PMADRL, (PMADRL<4:0>)

determining the write latch being loaded. Write opera-

tions do not cross these boundaries. At the completion

of a program memory write operation, the data in the

write latches is reset to contain 0x3FFF.

4. Load the PMADRH:PMADRL register pair with

the address of the location to be written.

5. Load the PMDATH:PMDATL register pair with

the program memory data to be written.

6. Execute the unlock sequence (Section 11.2.2

“Flash Memory Unlock Sequence”). The write

latch is now loaded.

7. Increment the PMADRH:PMADRL register pair

to point to the next location.

8. Repeat steps 5 through 7 until all but the last

write latch has been loaded.

9. Clear the LWLO bit of the PMCON1 register.

When the LWLO bit of the PMCON1 register is

‘0’, the write sequence will initiate the write to

Flash program memory.

10. Load the PMDATH:PMDATL register pair with

the program memory data to be written.

11. Execute the unlock sequence (Section 11.2.2

“Flash Memory Unlock Sequence”). The

entire program memory latch content is now

written to Flash program memory.

Note:

The program memory write latches are

reset to the blank state (0x3FFF) at the

completion of every write or erase

operation. As a result, it is not necessary

to load all the program memory write

latches. Unloaded latches will remain in

the blank state.

An example of the complete write sequence is shown in

Example 11-3. The initial address is loaded into the

PMADRH:PMADRL register pair; the data is loaded

using indirect addressing.

DS41639A-page 118

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PIC16(L)F1454/5/9

FIGURE 11-6:

FLASH PROGRAM MEMORY WRITE FLOWCHART

Start

Write Operation

Determine number of words

to be written into Program or

Configuration Memory.

The number of words cannot

exceed the number of words

per row.

Enable Write/Erase

Operation (WREN = 1)

Load the value to write

(PMDATH:PMDATL)

(word_cnt)

Update the word counter

(word_cnt--)

Write Latches to Flash

Disable Interrupts

(LWLO = 0)

(GIE = 0)

Unlock Sequence

(Figure x-x)

Figure 11-3

Select

Program or Config. Memory

(CFGS)

Yes

Last word to

write ?

CPU stalls while Write

operation completes

(2ms typical)

No

Select Row Address

(PMADRH:PMADRL)

Unlock Sequence

(Figure x-x)

Figure 11-3

Select Write Operation

(FREE = 0)

Disable

Write/Erase Operation

(WREN = 0)

No delay when writing to

Program Memory Latches

Load Write Latches Only

(LWLO = 1)

Re-enable Interrupts

(GIE = 1)

Increment Address

(PMADRH:PMADRL++)

End

Write Operation

DS41639A-page 120

Preliminary

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PIC16(L)F1454/5/9

EXAMPLE 11-3:

WRITING TO FLASH PROGRAM MEMORY

; This write routine assumes the following:

; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

;

BCF

INTCON,GIE

PMADRH

ADDRH,W

PMADRH

ADDRL,W

PMADRL

; Disable ints so required sequences will execute properly

; Bank 3

; Load initial address

;

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

LOW DATA_ADDR ; Load initial data address

FSR0L

HIGH DATA_ADDR ; Load initial data address

;

FSR0H

;

PMCON1,CFGS

PMCON1,WREN

PMCON1,LWLO

; Not configuration space

; Enable writes

; Only Load Write Latches

BSF

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

FSR0++

PMDATL

FSR0++

PMDATH

; Load first data byte into lower

;

; Load second data byte into upper

;

MOVF

PMADRL,W

0x1F

STATUS,Z

START_WRITE

; Check if lower bits of address are '00000'

; Check if we're on the last of 32 addresses

;

; Exit if last of 32 words,

;

XORLW

ANDLW

BTFSC

GOTO

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required write sequence:

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; NOP instructions are forced as processor

; loads program memory write latches

;

NOP

INCF

GOTO

PMADRL,F

LOOP

; Still loading latches Increment address

; Write next latches

START_WRITE

BCF

PMCON1,LWLO

; No more loading latches - Actually start Flash program

; memory write

MOVLW

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required write sequence:

; Write 55h

;

MOVWF

MOVLW

MOVWF

BSF

; Write AAh

; Set WR bit to begin write

; NOP instructions are forced as processor writes

; all the program memory write latches simultaneously

; to program memory.

NOP

; After NOPs, the processor

; stalls until the self-write process in complete

; after write processor continues with 3rd instruction

; Disable writes

BCF

BSF

PMCON1,WREN

INTCON,GIE

; Enable interrupts

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 121

PIC16(L)F1454/5/9

FIGURE 11-7:

FLASH PROGRAM

MEMORY MODIFY

FLOWCHART

11.3 Modifying Flash Program Memory

When modifying existing data in a program memory

row, and data within that row must be preserved, it must

first be read and saved in a RAM image. Program

memory is modified using the following steps:

Start

Modify Operation

1. Load the starting address of the row to be

modified.

2. Read the existing data from the row into a RAM

image.

Read Operation

(Figure x.x)

Figure 11-2

3. Modify the RAM image to contain the new data

to be written into program memory.

4. Load the starting address of the row to be

rewritten.

An image of the entire row read

must be stored in RAM

5. Erase the program memory row.

6. Load the write latches with data from the RAM

image.

7. Initiate a programming operation.

Modify Image

The words to be modified are

changed in the RAM image

Erase Operation

(Figure x.x)

Figure 11-4

WRITE Operation

use RAM image

(Figure x.x)

Figure 11-5

End

Modify Operation

DS41639A-page 122

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

11.4 User ID, Device ID and

Configuration Word Access

Instead of accessing program memory, the User ID’s,

Device ID/Revision ID and Configuration Words can be

accessed when CFGS = 1 in the PMCON1 register.

This is the region that would be pointed to by

PC<15> = 1, but not all addresses are accessible.

Different access may exist for reads and writes. Refer

to Table 11-2.

When read access is initiated on an address outside

the

parameters

listed

in

Table 11-2,

the

PMDATH:PMDATL register pair is cleared, reading

back ‘0’s.

TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)

Address

Function

Read Access

Write Access

8000h-8003h

8005h-8006h

8007h-8008h

User IDs

Yes

No

Revision ID-Device ID

Configuration Words 1 and 2

EXAMPLE 11-4:

CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:

*

PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL

; Select correct Bank

;

; Store LSB of address

; Clear MSB of address

MOVLW

MOVWF

CLRF

PROG_ADDR_LO

PMADRL

PMADRH

BSF

BCF

BSF

NOP

BSF

PMCON1,CFGS

INTCON,GIE

PMCON1,RD

; Select Configuration Space

; Disable interrupts

; Initiate read

; Executed (See Figure 11-2)

; Ignored (See Figure 11-2)

; Restore interrupts

INTCON,GIE

MOVF

PMDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

PMDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 123

PIC16(L)F1454/5/9

11.5 Write Verify

It is considered good programming practice to verify that

program memory writes agree with the intended value.

Since program memory is stored as a full page then the

stored program memory contents are compared with the

intended data stored in RAM after the last write is

complete.

FIGURE 11-8:

FLASH PROGRAM

MEMORY VERIFY

FLOWCHART

Start

Verify Operation

This routine assumes that the last row

of data written was from an image

saved in RAM. This image will be used

to verify the data currently stored in

Flash Program Memory.

Read Operation

(Figure x.x)

Figure 11-2

PMDAT =

RAM image

?

No

Fail

Verify Operation

Yes

No

Last

Word ?

Yes

End

Verify Operation

DS41639A-page 124

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

11.6 Register Definitions: Flash Program Memory Control

REGISTER 11-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u

bit 0

PMDAT<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

PMDAT<7:0>: Read/write value for Least Significant bits of program memory

REGISTER 11-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0

—

U-0

—

R/W-x/u

bit 0

PMDAT<13:8>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

PMDAT<13:8>: Read/write value for Most Significant bits of program memory

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 125

PIC16(L)F1454/5/9

REGISTER 11-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0

PMADR<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

PMADR<7:0>: Specifies the Least Significant bits for program memory address

REGISTER 11-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1⁽¹⁾

—

R/W-0/0

bit 0

PMADR<14:8>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘1’

PMADR<14:8>: Specifies the Most Significant bits for program memory address

bit 6-0

Note 1: Unimplemented bit, read as ‘1’.

DS41639A-page 126

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-1⁽¹⁾

—

R/W-0/0

CFGS

R/W-0/0

LWLO

R/W/HC-0/0 R/W/HC-x/q⁽²⁾

FREE WRERR

R/W-0/0

WREN

R/S/HC-0/0 R/S/HC-0/0

WR RD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

S = Bit can only be set

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

bit 6

Unimplemented: Read as ‘1’

CFGS: Configuration Select bit

1= Access Configuration, User ID and Device ID Registers

0= Access Flash program memory

bit 5

LWLO: Load Write Latches Only bit⁽³⁾

1= Only the addressed program memory write latch is loaded/updated on the next WR command

0= The addressed program memory write latch is loaded/updated and a write of all program memory

write latches will be initiated on the next WR command

bit 4

bit 3

FREE: Program Flash Erase Enable bit

1= Performs an erase operation on the next WR command (hardware cleared upon completion)

0= Performs a write operation on the next WR command

WRERR: Program/Erase Error Flag bit

1= Condition indicates an improper program or erase sequence attempt or termination (bit is set

automatically on any set attempt (write ‘1’) of the WR bit).

0= The program or erase operation completed normally.

bit 2

bit 1

WREN: Program/Erase Enable bit

1= Allows program/erase cycles

0= Inhibits programming/erasing of program Flash

WR: Write Control bit

1= Initiates a program Flash program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

0= Program/erase operation to the Flash is complete and inactive.

bit 0

RD: Read Control bit

1= Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can

only be set (not cleared) in software.

0= Does not initiate a program Flash read.

Note 1: Unimplemented bit, read as ‘1’.

2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is

started (WR = 1).

3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 127

PIC16(L)F1454/5/9

REGISTER 11-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0

bit 0

Program Memory Control Register 2

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

S = Bit can only be set

‘1’ = Bit is set

bit 7-0

Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

PMCON1 register. The value written to this register is used to unlock the writes. There are specific

timing requirements on these writes.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PMCON1

PMCON2

PMADRL

GIE

PEIE

TMR0IE

LWLO

INTE

IOCIE

TMR0IF

WREN

INTF

WR

IOCIF

RD

96

(1)

CFGS

FREE

WRERR

—

127

128

126

125

Program Memory Control Register 2

PMADRL<7:0>

(1)

PMADRH

PMDATL

—

PMADRH<6:0>

PMDATL<7:0>

PMDATH

—

PMDATH<5:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

Note 1: Unimplemented, read as ‘1’.

TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

FCMEN

PWRTE

LVP

IESO

13:8

7:0

—

CP

—

MCLRE

—

CLKOUTEN

BOREN<1:0>

—

CONFIG1

52

54

WDTE<1:0>

FOSC<2:0>

STVREN

13:8

DEBUG

LPBOR

—

BORV

—

PLLEN

CONFIG2

7:0 PLLMULT USBLSCLK

CPUDIV<1:0>

WRT<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

DS41639A-page 128

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 12-1:

GENERIC I/O PORT

OPERATION

12.0 I/O PORTS

Each port has three standard registers for its operation.

These registers are:

• TRISx registers (data direction)

Read LATx

• PORTx registers (reads the levels on the pins of

the device)

TRISx

D

Q

• LATx registers (output latch)

Write LATx

Write PORTx

Some ports may have one or more of the following

additional registers. These registers are:

CK

Data Register

VDD

• ANSELx (analog select)

• WPUx (weak pull-up)

Data Bus

In general, when a peripheral is enabled on a port pin,

that pin cannot be used as a general purpose output.

However, the pin can still be read.

I/O pin

Read PORTx

To peripherals

VSS

ANSELx

TABLE 12-1: PORT AVAILABILITY PER

DEVICE

EXAMPLE 12-1:

INITIALIZING PORTA

Device

; This code example illustrates

; initializing the PORTA register. The

; other ports are initialized in the same

; manner.

PIC16(L)F1454/5

PIC16(L)F1459

●

BANKSEL PORTA

CLRF PORTA

BANKSEL LATA

CLRF LATA

BANKSEL ANSELA

CLRF ANSELA

BANKSEL TRISA

;

The Data Latch (LATx registers) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

;Init PORTA

;Data Latch

;

;digital I/O

;

A write operation to the LATx register has the same

effect as a write to the corresponding PORTx register.

A read of the LATx register reads of the values held in

the I/O PORT latches, while a read of the PORTx

register reads the actual I/O pin value.

MOVLW

MOVWF

B'00111000' ;Set RA<5:3> as inputs

TRISA

;and set RA<2:0> as

;outputs

Ports that support analog inputs have an associated

ANSELx register. When an ANSEL bit is set, the digital

input buffer associated with that bit is disabled.

Disabling the input buffer prevents analog signal levels

on the pin between a logic high and low from causing

excessive current in the logic input circuitry. A

simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 12-1.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 129

PIC16(L)F1454/5/9

12.1 Alternate Pin Function

The Alternate Pin Function Control register is used to

steer specific peripheral input and output functions

between different pins. The APFCON register is shown

in Register 12-1. For this device family, the following

functions can be moved between different pins.

• CLKR

• SDO

• SS

• T1G

• P2

These bits have no effect on the values of any TRIS

register. PORT and TRIS overrides will be routed to the

correct pin. The unselected pin will be unaffected.

12.2 Register Definitions: Alternate Pin Function Control

REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

R/W-0/0

SDOSEL⁽¹⁾

R/W-0/0

SSSEL

U-0

—

R/W-0/0

T1GSEL

R/W-0/0

P2SEL⁽¹⁾

U-0

—

U-0

—

CLKRSEL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

bit 5

CLKRSEL: Pin Selection bit

1= CLKR function is on RC3

0= CLKR function is on RA4

SDOSEL: Pin Selection bit⁽¹⁾

1= SDO function is on RA4

0= SDO function is on RC2

SSSEL: Pin Selection bit

For 14-Pin Devices (PIC16(L)F1454/5):

1= SS function is on RA3

0= SS function is on RC3

For 20-Pin Devices (PIC16(L)F1455/9):

1= SS function is on RA3

0= SS function is on RC6

bit 4

bit 3

Unimplemented: Read as ‘0’

T1GSEL: Pin Selection bit

1= T1G function is on RA3

0= T1G function is on RA4

bit 2

P2SEL: Pin Selection bit⁽¹⁾

1= T1G function is on RA5

0= T1G function is on RC3

bit 1-0

Unimplemented: Read as ‘0’

Note 1: PIC16(L)F1454/5 only.

DS41639A-page 130

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

EXAMPLE 12-2:

INITIALIZING PORTA

12.3 PORTA Registers

BANKSEL PORTA

CLRF PORTA

BANKSEL LATA

CLRF LATA

BANKSEL ANSELA

CLRF ANSELA

BANKSEL TRISA

;

12.3.1

DATA REGISTER

5-bit wide, bidirectional port. The

;Init PORTA

;Data Latch

;

;digital I/O

;

PORTA is

a

corresponding data direction register is TRISA

(Register 12-3). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). The exception is RA0, RA1 and

RA3, which are input only and its TRIS bit will always

read as ‘1’. Example 12-2 shows how to initialize an I/O

port.

MOVLW

MOVWF

B'00111000' ;Set RA<5:3> as inputs

TRISA

;and set RA<2:0> as

;outputs

12.3.4

PORTA FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTA pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 12-2.

Reading the PORTA register (Register 12-2) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATA).

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input functions, such as ADC and comparator

inputs, are not shown in the priority lists. These inputs

are active when the I/O pin is set for Analog mode using

the ANSELx registers. Digital output functions may

control the pin when it is in Analog mode with the

priority shown below in Table 12-2.

12.3.2

DIRECTION CONTROL

The TRISA register (Register 12-3) controls the

PORTA pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISA register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

TABLE 12-2: PORTA OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

12.3.3

ANALOG CONTROL

RA0

RA1

RA2

RA3

RA4

ICSPDAT⁽⁴⁾

The ANSELA register (Register 12-5) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

ICSPCLK⁽⁴⁾

VUSB3V3

None

CLKOUT

SOSCO

CLKR⁽²⁾

SDO⁽³⁾

RA4

The state of the ANSELA bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

RA5

PWM2⁽³⁾

RA5

Note 1: Priority listed from highest to lowest.

2: Default pin (see APFCON register).

3: Alternate pin (see APFCON register).

4: LVP only.

Note:

The ANSELA bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 131

PIC16(L)F1454/5/9

12.4 Register Definitions: PORTA

REGISTER 12-2: PORTA: PORTA REGISTER

U-0

—

U-0

—

R/W-x/x

RA5

R/W-x/x

RA4

R-x/x

RA3

U-0

—

R-x/x

RA1

R-x/x

RA0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-3

Unimplemented: Read as ‘0’

RA<5:3>: PORTA I/O Value bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

bit 2

Unimplemented: Read as ‘0’

bit 1-0

RA<1:0>: PORTA I/O Value bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return

of actual I/O pin values.

REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER

U-0

—

U-0

—

R/W-1/1

TRISA5

R/W-1/1

TRISA4

U-1

U-0

—

U-1

(1)

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

TRISA<5:4>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

bit 3

Unimplemented: Read as ‘1’

Unimplemented: Read as ‘0’

Unimplemented: Read as ‘1’

bit 2

bit 1-0

Note 1: Unimplemented, read as ‘1’.

DS41639A-page 132

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER

U-0

—

U-0

—

R/W-x/u

LATA5

R/W-x/u

LATA4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

LATA<5:4>: RA<5:4> Output Latch Value bits⁽¹⁾

Unimplemented: Read as ‘0’

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return

of actual I/O pin values.

(2)

REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER

U-0

—

U-0

—

U-0

—

R/W-1/1

ANSA4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4

Unimplemented: Read as ‘0’

ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

bit 3-0

Unimplemented: Read as ‘0’

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

2: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 133

PIC16(L)F1454/5/9

REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER

U-0

—

U-0

—

R/W-1/1

WPUA5

R/W-1/1

WPUA4

R/W-1/1

WPUA3

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-3

Unimplemented: Read as ‘0’

WPUA<5:3>: Weak Pull-up Register bits⁽³⁾

1= Pull-up enabled

0= Pull-up disabled

bit 2-0

Unimplemented: Read as ‘0’

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is configured as an output.

3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.

TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA⁽³⁾

APFCON

LATA

—

ANSA4

—

133

130

133

185

132

134

CLKRSEL SDOSEL⁽²⁾

SSSEL

T1GSEL

P2SEL⁽²⁾

—

WPUEN

—

INTEDG

—

LATA5

TMR0CS

RA5

LATA4

TMR0SE

RA4

—

OPTION_REG

PORTA

PSA

RA3

PS<2:0>

RA1

—

RA0

(1)

TRISA

—

TRISA5

WPUA5

TRISA4

WPUA4

—

WPUA

—

WPUA3

—

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1454/5 only.

3: PIC16(L)F1455/9 only.

TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

FCMEN

PWRTE

IESO

13:8

7:0

—

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

—

CONFIG1

52

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

DS41639A-page 134

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

12.5.4

PORTB FUNCTIONS AND OUTPUT

PRIORITIES

12.5 PORTB Registers

(PIC16(L)F1455/9 only)

Each PORTB pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 12-2.

12.5.1

DATA REGISTER

4-bit wide, bidirectional port. The

PORTB is

a

corresponding data direction register is TRISB

(Register 12-3). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., disable the

output driver). Clearing a TRISB bit (= 0) will make the

corresponding PORTB pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). Example 12-2 shows how to

initialize an I/O port.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input functions, such as ADC and comparator

inputs, are not shown in the priority lists. These inputs

are active when the I/O pin is set for Analog mode using

the ANSELx registers. Digital output functions may

control the pin when it is in Analog mode with the

priority shown below in Table 12-2.

Reading the PORTB register (Register 12-2) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATB).

TABLE 12-5: PORTB OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

RB4

SDA

RB4

12.5.2

DIRECTION CONTROL

RB5

RB6

RX

RB5

The TRISB register (Register 12-3) controls the

PORTB pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISB register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

SCL

SCK

RB6

RB7

TX

RB7

Note 1: Priority listed from highest to lowest.

2: Default pin (see APFCON register).

3: Alternate pin (see APFCON register).

12.5.3

ANALOG CONTROL

The ANSELB register (Register 12-5) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELB bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

Note:

The ANSELB bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 135

PIC16(L)F1454/5/9

12.6 Register Definitions: PORTB

REGISTER 12-7: PORTB: PORTB REGISTER

R/W-x/x

RB7

R/W-x/x

RB6

R/W-x/x

RB5

R/W-x/x

RB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

RB<7:4>: PORTB I/O Value bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

bit 3-0

Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is

return of actual I/O pin values.

REGISTER 12-8: TRISB: PORTB TRI-STATE REGISTER

R/W-1/1

TRISB7

R/W-1/1

TRISB6

R/W-1/1

TRISB5

R/W-1/1

TRISB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

bit 3-0

TRISB<7:4>: PORTB Tri-State Control bits

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

Unimplemented: Read as ‘0’

DS41639A-page 136

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 12-9: LATB: PORTB DATA LATCH REGISTER

R/W-x/u

LATB7

R/W-x/u

LATB6

R/W-x/u

LATB5

R/W-x/u

LATB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

bit 3-0

LATB<7:4>: RB<7:4> Output Latch Value bits⁽¹⁾

Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is

return of actual I/O pin values.

REGISTER 12-10: ANSELB: PORTB ANALOG SELECT REGISTER

U-0

—

U-0

—

R/W-1/1

ANSB5

R/W-1/1

ANSB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

bit 3-0

Unimplemented: Read as ‘0’

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 137

PIC16(L)F1454/5/9

REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1/1

WPUB7

R/W-1/1

WPUB6

R/W-1/1

WPUB5

R/W-1/1

WPUB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

WPUB<7:4>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is configured as an output.

(1)

TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

—

ANSB5

SSSEL

ANSB4

—

137

130

137

185

136

138

CLKRSEL SDOSEL⁽¹⁾

T1GSEL

P2SEL⁽¹⁾

APFCON

LATB

—

LATB7

WPUEN

RB7

LATB6

INTEDG

RB6

LATB5

TMR0CS

RB5

LATB4

TMR0SE

RB4

—

PSA

—

OPTION_REG

PORTB

TRISB

PS<2:0>

—

TRISB7

WPUB7

TRISB6

WPUB6

TRISB5

WPUB5

TRISB4

WPUB4

—

WPUB

—

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

Note 1: PIC16(L)F1459 only.

TABLE 12-7: SUMMARY OF CONFIGURATION WORD WITH PORTB

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

—

CONFIG1

52

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTB.

DS41639A-page 138

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

12.7.4

PORTC FUNCTIONS AND OUTPUT

PRIORITIES

12.7 PORTC Registers

12.7.1 DATA REGISTER

Each PORTC pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 12-8.

PORTC is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC

(Register 12-13). Setting a TRISC bit (= 1) will make

the corresponding PORTC pin an input (i.e., put the

corresponding output driver in a High-Impedance

mode). Clearing a TRISC bit (= 0) will make the

corresponding PORTC pin an output (i.e., enable the

output driver and put the contents of the output latch

on the selected pin). Example 12-2 shows how to

initialize an I/O port.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not

included in the output priority list. These input functions

can remain active when the pin is configured as an

output. Certain digital input functions override other

port functions and are included in the output priority list.

Reading the PORTC register (Register 12-12) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATC).

TABLE 12-8: PORTC OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

RC0

ICSPDAT

SCL⁽⁴⁾

SCK⁽⁴⁾

12.7.2

DIRECTION CONTROL

RC1

ICSPCLK

SDA⁽⁴⁾

SDI⁽⁴⁾

The TRISC register (Register 12-13) controls the

PORTC pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISC register are maintained set when using them

as analog inputs. I/O pins configured as analog input

always read ‘0’.

RC1

RC2

RC3

DACOUT1

SDO⁽²⁾

RC2

DACOUT2

CLKR⁽³⁾

PWM2⁽²⁾

RC3

12.7.3

ANALOG CONTROL

The ANSELC register (Register 12-15) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELC bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

RC4

RC5

CWG1B

C1OUT

C2OUT

TX⁽⁴⁾

The state of the ANSELC bits has no effect on digital out-

put functions. A pin with TRIS clear and ANSELC set will

still operate as a digital output, but the Input mode will be

analog. This can cause unexpected behavior when exe-

cuting read-modify-write instructions on the affected

port.

RC4

CWG1A

PWM1

RX⁽⁴⁾

RC5

Note:

The ANSELC bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

RC6

RC7

PWM2⁽⁵⁾

RC6

SDO⁽⁵⁾

RC7

Note 1: Priority listed from highest to lowest.

2: Default pin (see APFCON register).

3: Alternate pin (see APFCON register).

4: PIC16(L)F1454/5 only.

5: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 139

PIC16(L)F1454/5/9

12.8 Register Definitions: PORTC

REGISTER 12-12: PORTC: PORTC REGISTER

R/W-x/u

RC7⁽¹⁾

R/W-x/u

RC6⁽¹⁾

R/W-x/u

RC5

R/W-x/u

RC4

R/W-x/u

RC3

R/W-x/u

RC2

R/W-x/u

RC1

R/W-x/u

RC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

RC<7:0>: PORTC General Purpose I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: PIC16(L)F1459 only.

REGISTER 12-13: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1

TRISC7⁽¹⁾

R/W-1/1

TRISC6⁽¹⁾

R/W-1/1

TRISC5

R/W-1/1

TRISC4

R/W-1/1

TRISC3

R/W-1/1

TRISC2

R/W-1/1

TRISC1

R/W-1/1

TRISC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

Note 1: PIC16(L)F1459 only.

DS41639A-page 140

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 12-14: LATC: PORTC DATA LATCH REGISTER

R/W-x/u

LATC7⁽¹⁾

R/W-x/u

LATC6⁽¹⁾

R/W-x/u

LATC5

R/W-x/u

LATC4

R/W-x/u

LATC3

R/W-x/u

LATC2

R/W-x/u

LATC1

R/W-x/u

LATC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

LATC<7:0>: PORTC Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is

return of actual I/O pin values.

2: PIC16(L)F1459 only.

REGISTER 12-15: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1/1

ANSC7⁽¹⁾

R/W-1/1

ANSC6⁽¹⁾

U-0

—

U-0

—

R/W-1/1

ANSC3

R/W-1/1

ANSC2

R/W-1/1

ANSC1

R/W-1/1

ANSC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-6

ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

2: PIC16(L)F1459 only.

TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

ANSELC⁽²⁾

LATC

ANSC7

ANSC6

—

ANSC3

LATC3

RC3

ANSC2

LATC2

RC2

ANSC1

LATC1

RC1

ANSC0

LATC0

RC0

141

140

(1)

LATC7

LATC6

LATC5

RC5

LATC4

RC4

(1)

PORTC

TRISC

RC7

RC6

(1)

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

Legend:

x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

Note 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 141

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 142

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

13.3 Interrupt Flags

13.0 INTERRUPT-ON-CHANGE

The IOCAFx and IOCBFx bits located in the IOCAF and

IOCBF registers, respectively, are status flags that

correspond to the interrupt-on-change pins of the

associated port. If an expected edge is detected on an

appropriately enabled pin, then the status flag for that pin

will be set, and an interrupt will be generated if the IOCIE

bit is set. The IOCIF bit of the INTCON register reflects

the status of all IOCAFx and IOCBFx bits.

The PORTA and PORTB pins can be configured to

operate as Interrupt-On-Change (IOC) pins. An interrupt

can be generated by detecting a signal that has either a

rising edge or a falling edge. Any individual port pin, or

combination of port pins, can be configured to generate

an interrupt. The interrupt-on-change module has the

following features:

• Interrupt-on-Change enable (Master Switch)

• Individual pin configuration

13.4 Clearing Interrupt Flags

• Rising and falling edge detection

• Individual pin interrupt flags

The individual status flags, (IOCAFx and IOCBFx bits),

can be cleared by resetting them to zero. If another edge

is detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

Figure 13-1 is a block diagram of the IOC module.

13.1 Enabling the Module

To allow individual port pins to generate an interrupt, the

IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will

still occur, but an interrupt will not be generated.

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

EXAMPLE 13-1:

CLEARING INTERRUPT

FLAGS

(PORTA EXAMPLE)

13.2 Individual Pin Configuration

For each port pin, a rising edge detector and a falling

edge detector are present. To enable a pin to detect a

rising edge, the associated bit of the IOCxP register is

set. To enable a pin to detect a falling edge, the

associated bit of the IOCxN register is set.

MOVLW 0xff

XORWF IOCAF, W

ANDWF IOCAF, F

A pin can be configured to detect rising and falling

edges simultaneously by setting both associated bits of

the IOCxP and IOCxN registers, respectively.

13.5 Operation in Sleep

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCxF

register will be updated prior to the first instruction

executed out of Sleep.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 143

PIC16(L)F1454/5/9

FIGURE 13-1:

INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)

Q4Q1

IOCANx

D

Q

CK

Edge

Detect

R

RAx

Data Bus =

0 or 1

S

To Data Bus

IOCAFx

IOCAPx

D

Q

Write IOCAFx

CK

IOCIE

R

Q2

From all other

IOCAFx individual

Pin Detectors

IOC interrupt

to CPU core

Q1

Q2

Q3

Q2

Q3

Q4

Q4Q1

Q4

Q4Q1

DS41639A-page 144

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

13.6 Register Definitions: Interrupt-on-change Control

REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

U-0

—

U-0

—

R/W-0/0

IOCAP5

R/W-0/0

IOCAP4

R/W-0/0

IOCAP3

U-0

—

R/W-0/0

IOCAP1

R/W-0/0

IOCAP0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-3

Unimplemented: Read as ‘0’

IOCAP<5:3>: Interrupt-on-Change PORTA Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

IOCAP<1:0>: Interrupt-on-Change PORTA Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER

U-0

—

U-0

—

R/W-0/0

IOCAN5

R/W-0/0

IOCAN4

R/W-0/0

IOCAN3

U-0

—

R/W-0/0

IOCAN1

R/W-0/0

IOCAN0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-3

Unimplemented: Read as ‘0’

IOCAN<5:3>: Interrupt-on-Change PORTA Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

IOCAN<1:0>: Interrupt-on-Change PORTA Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 145

PIC16(L)F1454/5/9

REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

U-0

—

U-0

—

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

U-0

—

R/W/HS-0/0 R/W/HS-0/0

IOCAF1 IOCAF0

bit 0

IOCAF5

IOCAF4

IOCAF3

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-6

bit 5-3

Unimplemented: Read as ‘0’

IOCAF<5:3>: Interrupt-on-Change PORTA Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCAPx = 1and a rising edge was detected on RAx, or when IOCANx = 1and a falling

edge was detected on RAx.

0= No change was detected, or the user cleared the detected change.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

IOCAF<‘:0>: Interrupt-on-Change PORTA Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCAPx = 1and a rising edge was detected on RAx, or when IOCANx = 1and a falling

edge was detected on RAx.

0= No change was detected, or the user cleared the detected change.

(1)

REGISTER 13-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER

R/W-0/0

IOCBP7

R/W-0/0

IOCBP6

R/W-0/0

IOCBP5

R/W-0/0

IOCBP4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

bit 3-0

Unimplemented: Read as ‘0’

Note 1: PIC16(L)F1459 only.

DS41639A-page 146

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

(1)

REGISTER 13-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER

R/W-0/0

IOCBN7

R/W-0/0

IOCBN6

R/W-0/0

IOCBN5

R/W-0/0

IOCBN4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

bit 3-0

Unimplemented: Read as ‘0’

Note 1: PIC16(L)F1459 only.

(1)

REGISTER 13-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

U-0

—

U-0

—

U-0

—

IOCBF7

bit 7

IOCBF6

IOCBF5

IOCBF4

—

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-4

IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling

edge was detected on RBx.

0= No change was detected, or the user cleared the detected change.

bit 3-0

Unimplemented: Read as ‘0’

Note 1: PIC16(L)F1459 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 147

PIC16(L)F1454/5/9

TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA⁽³⁾

INTCON

IOCAF

—

GIE

—

PEIE

—

ANSA4

INTE

—

IOCIE

IOCAF3

IOCAN3

IOCAP3

—

TMR0IF

—

INTF

—

IOCIF

IOCAF0

IOCAN0

IOCAP0

—

133

96

TMR0IE

IOCAF5

IOCAN5

IOCAP5

IOCBF5

IOCBN5

IOCBP5

TRISA5

TRISB5

—

IOCAF4

IOCAN4

IOCAP4

IOCBF4

IOCBN4

IOCBP4

TRISA4

TRISB4

IOCAF1

IOCAN1

IOCAP1

—

146

145

147

146

132

136

IOCAN

—

IOCAP

—

IOCBF⁽²⁾

IOCBN⁽²⁾

IOCBP⁽²⁾

TRISA

IOCBF7

IOCBN7

IOCBP7

—

IOCBF6

IOCBN6

IOCBP6

—

—(1)

—

—(1)

—

—(1)

—

TRISB⁽²⁾

TRISB7

TRISB6

—

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1459 only.

3: PIC16(L)F1455/9 only.

DS41639A-page 148

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the ADC module. Refer-

ence Section 16.0 “Analog-to-Digital Converter

(ADC) Module (PIC16(L)F1455/9 only)” for additional

information.

14.0 FIXED VOLTAGE REFERENCE

(FVR) (PIC16(L)F1455/9 ONLY)

The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,

2.048V or 4.096V selectable output levels. The output

of the FVR can be configured to supply a reference

voltage to the following:

The CDAFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the comparator modules.

Reference Section 18.0 “Comparator Module

(PIC16(L)F1455/9 only)” for additional information.

• ADC input channel

• ADC positive reference

• DAC input channel

• Comparator positive input

• Comparator negative input

14.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to

stabilize. Once the circuits stabilize and are ready for use,

the FVRRDY bit of the FVRCON register will be set. See

Section 29.0 “Electrical Specifications” for the

minimum delay requirement.

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

14.1 Independent Gain Amplifier

The output of the FVR supplied to the ADC and

comparators is routed through a programmable gain

amplifier. Each amplifier can be programmed for a gain

of 1x, 2x or 4x, to produce the three possible voltage

levels.

FIGURE 14-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

2

X1

X2

X4

FVR BUFFER1

(To ADC Module)

CDAFVR<1:0>

2

X1

X2

X4

FVR BUFFER2

(To Comparators, DAC)

+

_

FVREN

FVRRDY

Any peripheral requiring the

Fixed Reference

(See Table 14-1)

TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Peripheral

Conditions

Description

HFINTOSC

FOSC<2:0> = 010and

IRCF<3:0> = 000x

INTOSC is active and device is not in Sleep.

BOREN<1:0> = 11

BOR always enabled.

BOR

LDO

BOREN<1:0> = 10and BORFS = 1

BOREN<1:0> = 01and BORFS = 1

BOR disabled in Sleep mode, BOR Fast Start enabled.

BOR under software control, BOR Fast Start enabled.

All PIC16F1454/5/9 devices, when

VREGPM = 1and not in Sleep

The device runs off of the Low-Power Regulator when in

Sleep mode.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 149

PIC16(L)F1454/5/9

14.3 Register Definitions: FVR Control

REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0

FVREN

R-q/q

FVRRDY⁽¹⁾

R/W-0/0

TSEN

R/W-0/0

TSRNG

R/W-0/0

CDAFVR<1:0>

ADFVR<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

bit 4

bit 3-2

FVREN: Fixed Voltage Reference Enable bit

1= Fixed Voltage Reference is enabled

0= Fixed Voltage Reference is disabled

FVRRDY: Fixed Voltage Reference Ready Flag bit⁽¹⁾

1= Fixed Voltage Reference output is ready for use

0= Fixed Voltage Reference output is not ready or not enabled

TSEN: Temperature Indicator Enable bit⁽³⁾

1= Temperature Indicator is enabled

0= Temperature Indicator is disabled

TSRNG: Temperature Indicator Range Selection bit⁽³⁾

1= VOUT = VDD - 4VT (High Range)

0= VOUT = VDD - 2VT (Low Range)

CDAFVR<1:0>: Comparator Fixed Voltage Reference Selection bits

11= Comparator Fixed Voltage Reference Peripheral output is 4x (4.096V)⁽²⁾

10= Comparator Fixed Voltage Reference Peripheral output is 2x (2.048V)⁽²⁾

01= Comparator Fixed Voltage Reference Peripheral output is 1x (1.024V)

00= Comparator Fixed Voltage Reference Peripheral output is off

bit 1-0

ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit

11= ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)⁽²⁾

10= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)⁽²⁾

01= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)

00= ADC Fixed Voltage Reference Peripheral output is off

Note 1: FVRRDY is always ‘1’ for the PIC16F1455/9 devices.

2: Fixed Voltage Reference output cannot exceed VDD.

3: See Section 15.0 “Temperature Indicator Module (PIC16(L)F1455/9 only)” for additional information.

TABLE 14-2: SUMMARYOF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

FVREN

FVRRDY

TSEN

TSRNG

CDAFVR>1:0>

ADFVR<1:0>

150

Legend:

Shaded cells are unused by the Fixed Voltage Reference module.

DS41639A-page 150

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 15-1:

TEMPERATURE CIRCUIT

DIAGRAM

15.0 TEMPERATURE INDICATOR

MODULE (PIC16(L)F1455/9

ONLY)

VDD

This family of devices is equipped with a temperature

circuit designed to measure the operating temperature

of the silicon die. The circuit’s range of operating

temperature falls between -40°C and +85°C. The

output is a voltage that is proportional to the device

temperature. The output of the temperature indicator is

internally connected to the device ADC.

TSEN

TSRNG

The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,

depending on the level of calibration performed. A one-

point calibration allows the circuit to indicate a

temperature closely surrounding that point. A two-point

calibration allows the circuit to sense the entire range

of temperature more accurately. Reference Application

Note AN1333, “Use and Calibration of the Internal

Temperature Indicator” (DS01333) for more details

regarding the calibration process.

VOUT

To ADC

15.2 Minimum Operating VDD

15.1 Circuit Operation

When the temperature circuit is operated in low range,

the device may be operated at any operating voltage

that is within specifications.

Figure 15-1 shows a simplified block diagram of the

temperature circuit. The proportional voltage output is

achieved by measuring the forward voltage drop across

multiple silicon junctions.

When the temperature circuit is operated in high range,

the device operating voltage, VDD, must be high

enough to ensure that the temperature circuit is cor-

rectly biased.

Equation 15-1 describes the output characteristics of

the temperature indicator.

Table 15-1 shows the recommended minimum VDD vs.

range setting.

EQUATION 15-1: VOUT RANGES

TABLE 15-1: RECOMMENDED VDD VS.

RANGE

High Range: VOUT = VDD - 4VT

Low Range: VOUT = VDD - 2VT

Min. VDD, TSRNG = 1

Min. VDD, TSRNG = 0

3.6V

1.8V

The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See

Section Register 14-1: “FVRCON: Fixed Voltage

Reference Control Register” for more information.

15.3 Temperature Output

The output of the circuit is measured using the internal

Analog-to-Digital Converter. A channel is reserved for

the temperature circuit output. Refer to Section 16.0

The circuit is enabled by setting the TSEN bit of the

FVRCON register. When disabled, the circuit draws no

current.

“Analog-to-Digital

Converter

(ADC)

Module

(PIC16(L)F1455/9 only)” for detailed information.

The circuit operates in either high or low range. The high

range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This

provides more resolution over the temperature range,

but may be less consistent from part to part. This range

requires a higher bias voltage to operate and thus, a

higher VDD is needed.

15.4 ADC Acquisition Time

To ensure accurate temperature measurements, the

user must wait at least 200 s after the ADC input

multiplexer is connected to the temperature indicator

output before the conversion is performed. In addition,

the user must wait 200 s between sequential

conversions of the temperature indicator output.

The low range is selected by clearing the TSRNG bit of

the FVRCON register. The low range generates a lower

voltage drop and thus, a lower bias voltage is needed to

operate the circuit. The low range is provided for low

voltage operation.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 151

PIC16(L)F1454/5/9

TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

FVREN

FVRRDY

TSEN

TSRNG

CDAFVR<1:0>

ADFVR<1:0>

118

Legend:

Shaded cells are unused by the temperature indicator module.

DS41639A-page 152

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

16.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

(PIC16(L)F1455/9 ONLY)

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates

a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 16-1 shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be

either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 153

PIC16(L)F1454/5/9

FIGURE 16-1:

ADC BLOCK DIAGRAM

VDD

ADPREF = 00

VREF+

ADPREF = 10

VREF- = VSS

VREF+

Reserved

00000

Reserved

AN3

00001

00010

00011

00100

00101

00110

VREF+/AN4

AN5

AN6

ref-

ref+

AN7

AN8

00111

01000

01001

ADC

AN9

AN10

10

GO/DONE

01010

0= Left Justify

1= Right Justify

AN11

01011

01100

ADFM

Reserved

ADON

16

ADRESH ADRESL

VSS

11100

11101

11110

11111

Reserved

Temp Indicator

DAC

FVR Buffer1

CHS<4:0>

Note 1: When ADON = 0, all multiplexer inputs are disconnected.

DS41639A-page 154

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

16.1.4

CONVERSION CLOCK

16.1 ADC Configuration

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• FOSC/2

• Channel selection

• FOSC/4

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• FOSC/8

• FOSC/16

• FOSC/32

• Result formatting

• FOSC/64

16.1.1

PORT CONFIGURATION

• FRC (dedicated internal oscillator)

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to

Section 12.0 “I/O Ports” for more information.

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11.5 TAD peri-

ods as shown in Figure 16-2.

For correct conversion, the appropriate TAD specifica-

tion must be met. Refer to the A/D conversion require-

ments in Section 29.0 “Electrical Specifications” for

more information. Table 16-1 gives examples of appro-

priate ADC clock selections.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input buf-

fer to conduct excess current.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

16.1.2

CHANNEL SELECTION

There are 12 channel selections available:

• AN<11:3> pins

• Temperature Indicator

• DAC

• FVR (Fixed Voltage Reference) Output

Refer to Section 14.0 “Fixed Voltage Reference (FVR)

(PIC16(L)F1455/9 only)” and Section 15.0 “Tempera-

ture Indicator Module (PIC16(L)F1455/9 only)” for

more information on these channel selections.

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 16.2

“ADC Operation” for more information.

16.1.3

ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive

voltage reference can be:

• VREF+ pin

• VDD

See Section 14.0 “Fixed Voltage Reference (FVR)

(PIC16(L)F1455/9 only)” for more details on the Fixed

Voltage Reference.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 155

PIC16(L)F1454/5/9

TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC

ADCS<2:0>

Clock Source

20 MHz

16 MHz

8 MHz

4 MHz

1 MHz

Fosc/2

Fosc/4

Fosc/8

Fosc/16

Fosc/32

Fosc/64

FRC

000

100

001

101

010

110

x11

100 ns⁽²⁾

200 ns⁽²⁾

400 ns⁽²⁾

800 ns

125 ns⁽²⁾

250 ns⁽²⁾

0.5 s⁽²⁾

1.0 s

250 ns⁽²⁾

500 ns⁽²⁾

1.0 s

500 ns⁽²⁾

1.0 s

2.0 s

4.0 s

8.0 s⁽³⁾

16.0 s⁽³⁾

32.0 s⁽³⁾

64.0 s⁽³⁾

1.0-6.0 s^(1,4)

2.0 s

4.0 s

1.6 s

2.0 s

4.0 s

8.0 s⁽³⁾

1.0-6.0 s^(1,4)

8.0 s⁽³⁾

16.0 s⁽³⁾

1.0-6.0 s^(1,4)

3.2 s

1.0-6.0 s^(1,4)

4.0 s

1.0-6.0 s^(1,4)

Legend:

Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the

system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the

device in Sleep mode.

FIGURE 16-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY - TAD

TAD8 TAD9 TAD10 TAD11

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7

b4

b1

b0

b9

b8

b7

b6

b5

b3

b2

Conversion starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

On the following cycle:

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

DS41639A-page 156

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

16.1.5

INTERRUPTS

16.1.6

RESULT FORMATTING

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON1 register controls the output format.

Figure 16-3 shows the two output formats.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the FRC oscillator is selected.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEPinstruc-

tion is always executed. If the user is attempting to

wake-up from Sleep and resume in-line code execu-

tion, the GIE and PEIE bits of the INTCON register

must be disabled. If the GIE and PEIE bits of the

INTCON register are enabled, execution will switch to

the Interrupt Service Routine.

FIGURE 16-3:

10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

ADRESL

LSB

(ADFM = 0)

MSB

bit 7

bit 0

bit 7

bit 0

10-bit A/D Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 0

bit 7

Unimplemented: Read as ‘0’

10-bit A/D Result

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 157

PIC16(L)F1454/5/9

16.2.4

ADC OPERATION DURING SLEEP

16.2 ADC Operation

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

16.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 16.2.6 “A/D Conver-

sion Procedure”.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

16.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

16.2.5

AUTO-CONVERSION TRIGGER

• Update the ADRESH and ADRESL registers with

new conversion result

The auto-conversion trigger allows periodic ADC mea-

surements without software intervention. When a rising

edge of the selected source occurs, the GO/DONE bit

is set by hardware.

16.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH and ADRESL registers will be updated with

the partially complete Analog-to-Digital conversion

sample. Incomplete bits will match the last bit

converted.

The auto-conversion trigger source is selected with the

TRIGSEL<2:0> bits of the ADCON2 register.

Using the auto-conversion trigger does not assure

proper ADC timing. It is the user’s responsibility to

ensure that the ADC timing requirements are met.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

Auto-Conversion sources are:

• TMR0

• TMR1

• TMR2

• C1

• C2

DS41639A-page 158

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

16.2.6

A/D CONVERSION PROCEDURE

EXAMPLE 16-1:

A/D CONVERSION

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

;This code block configures the ADC

;for polling, Vdd and Vss references, Frc

;clock and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

register)

• Configure pin as analog (Refer to the ANSEL

register)

BANKSEL

MOVLW

ADCON1

;

B’11110000’ ;Right justify, Frc

;clock

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

CALL

ADCON1

TRISA

TRISA,0

ANSEL

ANSEL,0

ADCON0

;Vdd and Vss Vref+

;

;Set RA0 to input

;

;Set RA0 to analog

;

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

B’00000001’ ;Select channel AN0

ADCON0

SampleTime

;Turn ADC On

;Acquisiton delay

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

BANKSEL

MOVF

ADCON0,ADGO ;Start conversion

ADCON0,ADGO ;Is conversion done?

$-1

ADRESH

;No, test again

;

.

5. Start conversion by setting the GO/DONE bit.

ADRESH,W

RESULTHI

ADRESL

;Read upper 2 bits

;store in GPR space

;

6. Wait for ADC conversion to complete by one of

the following:

ADRESL,W

RESULTLO

;Read lower 8 bits

;Store in GPR space

• Polling the GO/DONE bit

MOVWF

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 16.4 “A/D Acquisition

Requirements”.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 159

PIC16(L)F1454/5/9

16.3 Register Definitions: ADC Control

REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0

U-0

—

R/W-0/0

ADON

CHS<4:0>

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-2

CHS<4:0>: Analog Channel Select bits

00000= Reserved. No channel connected.

00001= Reserved. No channel connected.

00010= Reserved. No channel connected.

00011= AN3

00100= AN4

00101= AN5

00110= AN6

00111= AN7

01000= AN8

01001= AN9

01010= AN10

01011= AN11

01100= Reserved. No channel connected.

•

11100= Reserved. No channel connected.

11101= Temperature Indicator⁽¹⁾

11110= DAC (Digital-to-Analog Converter)⁽²⁾

11111=FVR (Fixed Voltage Reference) Buffer 1 Output⁽³⁾

GO/DONE: A/D Conversion Status bit

bit 1

bit 0

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

Note 1: See Section 15.0 “Temperature Indicator Module (PIC16(L)F1455/9 only)” for more information.

2: See Section 17.0 “Digital-to-Analog Converter (DAC) Module (PIC16(L)F1455/9 only)” for more infor-

mation.

3: See Section 14.0 “Fixed Voltage Reference (FVR) (PIC16(L)F1455/9 only)” for more information.

DS41639A-page 160

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1

R/W-0/0

ADFM

R/W-0/0

U-0

—

U-0

—

R/W-0/0

ADCS<2:0>

ADPREF<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

ADFM: A/D Result Format Select bit

1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is

loaded.

0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is

loaded.

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

011= FRC (clock supplied from a dedicated RC oscillator)

100= FOSC/4

101= FOSC/16

110= FOSC/64

111= FRC (clock supplied from a dedicated RC oscillator)

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits

00= VREF+ is connected to VDD

01= Reserved

10= VREF+ is connected to external VREF+ pin⁽¹⁾

11= VREF+ is connected to internal Fixed Voltage Reference (FVR) module

Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage

specification exists. See Section 29.0 “Electrical Specifications” for details.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 161

PIC16(L)F1454/5/9

REGISTER 16-3: ADCON2: A/D CONTROL REGISTER 2

R/W-0/0

—

R/W-0/0

U-0

—

U-0

—

U-0

—

U-0

—

TRIGSEL<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

TRIGSEL<2:0>: Auto-Conversion Trigger Selection bits⁽¹⁾

bit 6-4

000=

001=

010=

011=

100=

101=

110=

111=

No auto-conversion trigger selected

Reserved

TMR0 Overflow⁽²⁾

TMR1 Overflow⁽²⁾

TMR2 Match to PR2⁽²⁾

sync_C1OUT

sync_C2OUT

bit 3-0

Unimplemented: Read as ‘0’

Note 1: This is a rising edge sensitive input for all sources.

2: Signal also sets its corresponding interrupt flag.

DS41639A-page 162

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 16-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u

bit 0

ADRES<9:2>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

REGISTER 16-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

ADRES<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result

Reserved: Do not use.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 163

PIC16(L)F1454/5/9

REGISTER 16-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

ADRES<9:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-2

bit 1-0

Reserved: Do not use.

ADRES<9:8>: ADC Result Register bits

Upper two bits of 10-bit conversion result

REGISTER 16-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u

bit 0

ADRES<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

DS41639A-page 164

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (or changed), an A/D acquisition must be

done before the conversion can be started. To calculate

the minimum acquisition time, Equation 16-1 may be

used. This equation assumes that 1/2 LSb error is used

(1,024 steps for the ADC). The 1/2 LSb error is the

maximum error allowed for the ADC to meet its

specified resolution.

16.4 A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 16-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 16-4. The maximum recommended

impedance for analog sources is 10 k. As the

EQUATION 16-1: ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + Temperature - 25°C0.05µs/°C

The value for TC can be approximated with the following equations:

1





;[1] VCHOLD charged to within 1/2 lsb

^VAPPLIED^{1 – -------------------------- = VCHOLD}



2^{n + 1} – 1

–TC

---------





RC

VAPPLIED 1 – e

= V^CHOLD







;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]



–Tc

--------









RC

1







^{= VAPPLIED}^{1 – --------------------------}

2^{n + 1} – 1

VAPPLIED 1 – e





Note: Where n = number of bits of the ADC.

Solving for TC:

TC = –CHOLDRIC + RSS + RS ln(1/2047)

= –12.5pF1k + 7k + 10k ln(0.0004885)

= 1.12µs

Therefore:

TACQ = 5µs + 1.12µs + 50°C- 25°C0.05µs/°C

= 7.37µs

Note 1: The reference voltage (VREF+) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 165

PIC16(L)F1454/5/9

FIGURE 16-4:

ANALOG INPUT MODEL

VDD

Analog

Input

Sampling

Switch

VT  0.6V

SS

RIC  1k

Rss

Rs

(1)

CPIN

5 pF

VA

I LEAKAGE

CHOLD = 10 pF

VREF-

VT  0.6V

6V

5V

RSS

VDD 4V

3V

Legend:

CHOLD

CPIN

= Sample/Hold Capacitance

= Input Capacitance

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

5 6 7 8 9 1011

Sampling Switch

RIC

RSS

SS

VT

= Interconnect Resistance

= Resistance of Sampling Switch

= Sampling Switch

(k)

= Threshold Voltage

Note 1: Refer to Section 29.0 “Electrical Specifications”.

FIGURE 16-5:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

03h

02h

01h

00h

Analog Input Voltage

1.5 LSB

0.5 LSB

Zero-Scale

Transition

VREF-

Full-Scale

Transition

VREF+

DS41639A-page 166

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

(3)

TABLE 16-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

ADCON1

ADCON2

ADRESH

ADRESL

ANSELA⁽³⁾

ANSELB⁽²⁾

ANSELC⁽³⁾

INTCON

PIE1

—

ADFM

—

CHS<4:0>

GO/DONE

ADON

160

161

ADCS<2:0>

—

ADPREF<1:0>

TRIGSEL<2:0>

—

162

163, 164

133

A/D Result Register Low

—

ANSA4

ANSB4

—

ANSB5

—

137

ANSC7⁽¹⁾ANSC6⁽¹⁾

ANSC3

IOCIE

SSP1IE

ANSC2

TMR0IF

—

ANSC1

INTF

ANSC0

IOCIF

TMR1IE

141

GIE

TMR1GIE

TMR1GIF

—

PEIE

ADIE⁽³⁾

ADIF⁽³⁾

—

TMR0IE

RCIE

INTE

96

TXIE

TMR2IE

97

PIR1

RCIF

TXIF

SSP1IF

—

TMR2IF

TMR1IF

99

—(1)

TRISA

TRISB⁽²⁾

TRISA5

TRISB5

TRISC5

TSEN

TRISA4

TRISB4

TRISC4

TSRNG

—

132

TRISB7

TRISC7⁽²⁾TRISC6⁽²⁾

TRISB6

—

136

TRISC

TRISC3

TRISC2

TRISC1

TRISC0

140

FVRCON

Legend:

FVREN FVRRDY

CDAFVR<1:0>

ADFVR<1:0>

150

x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not

used for ADC module.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1459 only.

3: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 167

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 168

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

17.1 Output Voltage Selection

17.0 DIGITAL-TO-ANALOG

CONVERTER (DAC) MODULE

(PIC16(L)F1455/9 ONLY)

The DAC has 32 voltage level ranges. The 32 levels

are set with the DACR<4:0> bits of the DACCON1

register.

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,

with 32 selectable output levels.

The DAC output voltage is determined by the following

equations:

The input of the DAC can be connected to:

• External VREF+ pin

• VDD supply voltage

The output of the DAC can be configured to supply a

reference voltage to the following:

• Comparator positive input

• ADC input channel

• DACOUT1 pin

• DACOUT2 pin

The Digital-to-Analog Converter (DAC) can be enabled

by setting the DACEN bit of the DACCON0 register.

EQUATION 17-1: DAC OUTPUT VOLTAGE

IF DACEN = 1

DACR4:0





VOUT = VSOURCE+ – VSOURCE-  ----------------------------- + VSOURCE-

2⁵





IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111

VOUT = VSOURCE +

IF DACEN = 0 and DACLPS = 0 and DACR[4:0] = 00000

VOUT = VSOURCE –

VSOURCE+ = VDD, VREF, or FVR BUFFER 2

VSOURCE- = VSS

17.2 Ratiometric Output Level

17.3 DAC Voltage Reference Output

The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage

of either input source fluctuates, a similar fluctuation will

result in the DAC output value.

The DAC voltage can be output to the DACOUT1 and

DACOUT2 pins by setting the respective DACOE1 and

DACOE2 pins of the DACCON0 register. Selecting the

DAC reference voltage for output on either DACOUTx

pin automatically overrides the digital output buffer and

digital input threshold detector functions of that pin.

Reading the DACOUTx pin when it has been config-

ured for DAC reference voltage output will always

return a ‘0’.

The value of the individual resistors within the ladder

can be found in Section 29.0 “Electrical

Specifications”.

Due to the limited current drive capability, a buffer must

be used on the DAC voltage reference output for

external connections to either DACOUTx pin.

Figure 17-2 shows an example buffering technique.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 169

PIC16(L)F1454/5/9

FIGURE 17-1:

DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

Digital-to-Analog Converter (DAC)

VSOURCE+

VDD

DACR<4:0>

5

VREF+

R

DACPSS

DACEN

R

32

Steps

DAC

(To Comparator and

ADC Module)

R

DACOUT1

DACOE1

VSOURCE-

DACOUT2

DACOE2

FIGURE 17-2:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC^®MCU

DAC

Module

R

+

–

Buffered DAC Output

DACOUTX

Voltage

Reference

Output

Impedance

DS41639A-page 170

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

17.4 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the DACCON0 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

17.5 Effects of a Reset

A device Reset affects the following:

• DAC is disabled.

• DAC output voltage is removed from the

DACOUT pin.

• The DACR<4:0> range select bits are cleared.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 171

PIC16(L)F1454/5/9

17.6 Register Definitions: DAC Control

REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0

DACEN

U-0

—

R/W-0/0

U-0

—

U-0

—

DACOE1

DACOE2

DACPSS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

DACEN: DAC Enable bit

1= DAC is enabled

0= DAC is disabled

bit 6

bit 5

Unimplemented: Read as ‘0’

DACOE1: DAC Voltage Output Enable bit

1= DAC voltage level is also an output on the DACOUT1 pin

0= DAC voltage level is disconnected from the DACOUT1 pin

bit 4

DACOE2: DAC Voltage Output Enable bit

1= DAC voltage level is also an output on the DACOUT2 pin

0= DAC voltage level is disconnected from the DACOUT2 pin

bit 3-2

DACPSS<1:0>: DAC Positive Source Select bit

11= Reserved

10= Comparator FVR output

01= VREF+ pin

00= VDD

bit 1-0

Unimplemented: Read as ‘0’

REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0/0

DACR<4:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

DACR<4:0>: DAC Voltage Output Select bits

(1)

TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

DACCON0

DACCON1

Legend:

FVREN

DACEN

—

FVRRDY

TSEN

TSRNG

CDAFVR<1:0>

DACPSS<1:0>

DACR<4:0>

ADFVR<1:0>

356

172

—

DACOE1 DACOE2

—

— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

Note 1: PIC16(L)F1455/9 only.

DS41639A-page 172

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 18-1:

SINGLE COMPARATOR

18.0 COMPARATOR MODULE

(PIC16(L)F1455/9 ONLY)

VIN+

VIN-

+

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

Comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of program execution. The analog

comparator module includes the following features:

Output

–

VIN-

VIN+

• Independent comparator control

• Programmable input selection

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

Output

• Wake-up from Sleep

• Programmable Speed/Power optimization

• PWM shutdown

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

• Programmable and fixed voltage reference

18.1

Comparator Overview

A single comparator is shown in Figure 18-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

The comparators available for this device are located in

Table 18-1.

TABLE 18-1: COMPARATORAVAILABILITY

PER DEVICE

Device

C1

C2

PIC16(L)F1455

PIC16(L)F1459

●

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 173

PIC16(L)F1454/5/9

FIGURE 18-2:

COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM

CxNCH<2:0>

CxON⁽¹⁾

3

CxINTP

Interrupt

det

0

Reserved

CXIN1-

CXIN2-

CXIN3-

Set CxIF

1

CxINTN

Interrupt

det

MUX

(2)

2

3

4

CXPOL

CxVN

CxVP

-

CXOUT

FVR Buffer2

D

Q

Cx

MCXOUT

+

Q1

EN

0

CXIN+

CxHYS

MUX

1

DAC

(2)

CxSP

async_CxOUT

To CWG

CXOE

FVR Buffer2

2

3

CXSYNC

CxON

TRIS bit

CXOUT

CXPCH<1:0>

0

1

2

D

Q

(from Timer1)

T1CLK

SYNCCXOUT

To Timer1,

ADC

Note 1:

2:

When CxON = 0, the Comparator will produce a ‘0’ at the output

When CxON = 0, all multiplexer inputs are disconnected.

DS41639A-page 174

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

18.2.3

COMPARATOR OUTPUT POLARITY

18.2 Comparator Control

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

Each comparator has two control registers: CMxCON0

and CMxCON1.

The CMxCON0 registers (see Register 18-1) contain

Control and Status bits for the following:

• Enable

Table 18-2 shows the output state versus input

conditions, including polarity control.

• Output selection

• Output polarity

TABLE 18-2: COMPARATOR OUTPUT

STATE VS. INPUT

• Speed/Power selection

• Hysteresis enable

• Output synchronization

CONDITIONS

Input Condition

CxPOL

CxOUT

The CMxCON1 registers (see Register 18-2) contain

Control bits for the following:

CxVN > CxVP

CxVN < CxVP

CxVN > CxVP

CxVN < CxVP

0

1

0

1

0

• Interrupt enable

• Interrupt edge polarity

• Positive input channel selection

• Negative input channel selection

18.2.4

COMPARATOR SPEED/POWER

SELECTION

18.2.1

COMPARATOR ENABLE

The trade-off between speed or power can be opti-

mized during program execution with the CxSP control

bit. The default state for this bit is ‘1’ which selects the

Normal-Speed mode. Device power consumption can

be optimized at the cost of slower comparator propaga-

tion delay by clearing the CxSP bit to ‘0’.

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

18.2.2

COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CMOUT register. In order to

make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

Note 1: The CxOE bit of the CMxCON0 register

overrides the PORT data latch. Setting

the CxON bit of the CMxCON0 register

has no impact on the port override.

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 175

PIC16(L)F1454/5/9

18.3 Comparator Hysteresis

18.5 Comparator Interrupt

A selectable amount of separation voltage can be

added to the input pins of each comparator to provide a

hysteresis function to the overall operation. Hysteresis

is enabled by setting the CxHYS bit of the CMxCON0

register.

An interrupt can be generated upon a change in the

output value of the comparator for each comparator, a

rising edge detector and a falling edge detector are

present.

When either edge detector is triggered and its associ-

ated enable bit is set (CxINTP and/or CxINTN bits of

the CMxCON1 register), the Corresponding Interrupt

Flag bit (CxIF bit of the PIR2 register) will be set.

See Section 29.0 “Electrical Specifications” for

more information.

18.4 Timer1 Gate Operation

To enable the interrupt, you must set the following bits:

• CxON, CxPOL and CxSP bits of the CMxCON0

register

The output resulting from a comparator operation can

be used as a source for gate control of Timer1. See

Section 20.6 “Timer1 Gate” for more information.

This feature is useful for timing the duration or interval

of an analog event.

• CxIE bit of the PIE2 register

• CxINTP bit of the CMxCON1 register (for a rising

edge detection)

It is recommended that the comparator output be syn-

chronized to Timer1. This ensures that Timer1 does not

increment while a change in the comparator is occur-

ring.

• CxINTN bit of the CMxCON1 register (for a falling

edge detection)

• PEIE and GIE bits of the INTCON register

The associated interrupt flag bit, CxIF bit of the PIR2

register, must be cleared in software. If another edge is

detected while this flag is being cleared, the flag will still

be set at the end of the sequence.

18.4.1

COMPARATOR OUTPUT

SYNCHRONIZATION

The output from either comparator, C1 or C2, can be

synchronized with Timer1 by setting the CxSYNC bit of

the CMxCON0 register.

Note:

Although a comparator is disabled, an

interrupt can be generated by changing

the output polarity with the CxPOL bit of

the CMxCON0 register, or by switching

the comparator on or off with the CxON bit

of the CMxCON0 register.

Once enabled, the comparator output is latched on the

falling edge of the Timer1 source clock. If a prescaler is

used with Timer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagram (Figure 18-2) and the Timer1 Block

Diagram (Figure 20-1) for more information.

18.6 Comparator Positive Input

Selection

Configuring the CxPCH<1:0> bits of the CMxCON1

register directs an internal voltage reference or an

analog pin to the non-inverting input of the comparator:

• CxIN+ analog pin

• DAC output

• FVR (Fixed Voltage Reference)

• VSS (Ground)

See Section 14.0 “Fixed Voltage Reference (FVR)

(PIC16(L)F1455/9 only)” for more information on the

Fixed Voltage Reference module.

See Section 17.0 “Digital-to-Analog Converter

(DAC) Module (PIC16(L)F1455/9 only)” for more

information on the DAC input signal.

Any time the comparator is disabled (CxON = 0), all

comparator inputs are disabled.

DS41639A-page 176

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

18.7 Comparator Negative Input

Selection

18.10 Analog Input Connection

Considerations

The CxNCH<2:0> bits of the CMxCON0 register direct

one of the input sources to the comparator inverting

input.

A simplified circuit for an analog input is shown in

Figure 18-3. Since the analog input pins share their

connection with a digital input, they have reverse

biased ESD protection diodes to VDD and VSS. The

analog input, therefore, must be between VSS and VDD.

If the input voltage deviates from this range by more

than 0.6V in either direction, one of the diodes is for-

ward biased and a latch-up may occur.

Note:

To use CxIN+ and CxINx- pins as analog

input, the appropriate bits must be set in

the ANSEL register and the correspond-

ing TRIS bits must also be set to disable

the output drivers.

A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

18.8 Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the comparator

differs from the settling time of the voltage reference.

Therefore, both of these times must be considered when

determining the total response time to a comparator

input change. See the Comparator and Voltage Refer-

ence Specifications in Section 29.0 “Electrical Specifi-

cations” for more details.

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

18.9 Interaction with ECCP Logic

The C1 and C2 comparators can be used as general

purpose comparators. Their outputs can be brought

out to the C1OUT and C2OUT pins. When the ECCP

Auto-Shutdown is active it can use one or both

comparator signals. If auto-restart is also enabled, the

comparators can be configured as a closed loop

analog feedback to the ECCP, thereby, creating an

analog controlled PWM.

Note:

When the comparator module is first

initialized the output state is unknown.

Upon initialization, the user should verify

the output state of the comparator prior to

relying on the result, primarily when using

the result in connection with other

peripheral features, such as the ECCP

Auto-Shutdown mode.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 177

PIC16(L)F1454/5/9

FIGURE 18-3:

ANALOG INPUT MODEL

VDD

Analog

Input

VT  0.6V

RIC

Rs < 10K

To Comparator

(1)

ILEAKAGE

CPIN

5 pF

VA

VT  0.6V

Vss

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

VT

= Threshold Voltage

Note 1: See Section 29.0 “Electrical Specifications”.

DS41639A-page 178

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

18.11 Register Definitions: Comparator Control

REGISTER 18-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0

CxON

R-0/0

R/W-0/0

CxOE

R/W-0/0

CxPOL

U-0

—

R/W-1/1

CxSP

R/W-0/0

CxHYS

R/W-0/0

CxSYNC

CxOUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

CxON: Comparator Enable bit

1= Comparator is enabled and consumes no active power

0= Comparator is disabled

CxOUT: Comparator Output bit

If CxPOL = 1 (inverted polarity):

1= CxVP < CxVN

0= CxVP > CxVN

If CxPOL = 0 (non-inverted polarity):

1= CxVP > CxVN

0= CxVP < CxVN

bit 5

bit 4

CxOE: Comparator Output Enable bit

1= CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually

drive the pin. Not affected by CxON.

0= CxOUT is internal only

CxPOL: Comparator Output Polarity Select bit

1= Comparator output is inverted

0= Comparator output is not inverted

bit 3

bit 2

Unimplemented: Read as ‘0’

CxSP: Comparator Speed/Power Select bit

1= Comparator operates in Normal-Power, Higher Speed mode

0= Comparator operates in Low-Power, Low-Speed mode

bit 1

bit 0

CxHYS: Comparator Hysteresis Enable bit

1= Comparator hysteresis enabled

0= Comparator hysteresis disabled

CxSYNC: Comparator Output Synchronous Mode bit

1= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.

Output updated on the falling edge of Timer1 clock source.

0= Comparator output to Timer1 and I/O pin is asynchronous

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 179

PIC16(L)F1454/5/9

REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

R/W-0/0

CxINTP

R/W-0/0

CxINTN

R/W-0/0

U-0

—

R/W-0/0

CxPCH<1:0>

CxNCH<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit

0= No interrupt flag will be set on a positive going edge of the CxOUT bit

bit 6

CxINTN: Comparator Interrupt on Negative Going Edge Enable bits

1= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit

0= No interrupt flag will be set on a negative going edge of the CxOUT bit

bit 5-4

CxPCH<1:0>: Comparator Positive Input Channel Select bits

11= CxVP connects to VSS

10= CxVP connects to FVR Voltage Reference

01= CxVP connects to DAC Voltage Reference

00= CxVP connects to CxIN+ pin

bit 3

Unimplemented: Read as ‘0’

bit 2-0

CxNCH<2:0>: Comparator Negative Input Channel Select bits

111= Reserved

110= Reserved

101= Reserved

100= CxVN connects to FVR Voltage reference

011= CxVN connects to CxIN3- pin

010= CxVN connects to CxIN2- pin

001= CxVN connects to CxIN1- pin

000= Reserved

REGISTER 18-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0/0

MC2OUT

MC1OUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-2

bit 1

Unimplemented: Read as ‘0’

MC2OUT: Mirror Copy of C2OUT bit

MC1OUT: Mirror Copy of C1OUT bit

bit 0

DS41639A-page 180

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

(3)

TABLE 18-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

ANSELC

CM1CON0

CM2CON0

CM1CON1

CM2CON1

CMOUT

DACCON0

DACCON1

FVRCON

INTCON

PIE2

—

ANSC7⁽²⁾

C1ON

C2ON

C1NTP

C2NTP

—

ANSC6⁽²⁾

C1OUT

C2OUT

C1INTN

C2INTN

—

ANSA4

—

ANSC3

—

133

141

179

180

172

150

96

—

ANSC2

C1SP

C2SP

ANSC1

ANSC0

C1SYNC

C2SYNC

C1OE

C2OE

C1POL

C2POL

C1HYS

—

C2HYS

C1PCH<1:0>

C2PCH<1:0>

—

C1NCH<2:0>

C2NCH<2:0>

—

MC2OUT MC1OUT

DACEN

—

DACOE1

—

DACOE2

DACPSS<1:0>

—

DACR<4:0>

FVREN

GIE

FVRRDY

PEIE

TSEN

TMR0IE

C1IE

TSRNG

INTE

—

CDAFVR<1:0>

ADFVR<1:0>

IOCIE

BCL1IE

BCL1IF

RA3

TMR0IF

USBIE

USBIF

INTF

ACTIE

ACTIF

RA1

IOCIF

—

OSFIE

OSFIF

C2IE

98

C2IF

C1IF

PIR2

—

100

132

140

133

141

132

140

PORTA

RA5

RA4

RA0

RC0

—

RC7⁽²⁾

—

RC6⁽²⁾

—

RC2

—

PORTC

LATA

RC5

RC4

RC3

RC1

LATA5

LATC5

TRISA5

TRISC5

LATA4

LATC4

TRISA4

TRISC4

—

LATC

LATC7⁽²⁾

LATC6⁽²⁾

LATC3

LATC2

—

LATC1

LATC0

(1)

—

TRISA

—

TRISC

TRISC7⁽²⁾

TRISC6⁽²⁾

TRISC3

TRISC2

TRISC1

TRISC0

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1459 only.

3: PIC16(L)F1455/9 only,

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 181

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 182

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

19.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the

following features:

Note:

The value written to the TMR0 register

can be adjusted, in order to account for

the two instruction cycle delay when

TMR0 is written.

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

19.1.2

8-BIT COUNTER MODE

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin.

• TMR0 can be used to gate Timer1

8-Bit Counter mode using the T0CKI pin is selected by

Figure 19-1 is a block diagram of the Timer0 module.

setting the TMR0CS bit in the OPTION_REG register to

‘1’.

19.1 Timer0 Operation

The rising or falling transition of the incrementing edge

for either input source is determined by the TMR0SE bit

in the OPTION_REG register.

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

19.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-bit Timer mode is

selected by clearing the TMR0CS bit of the

OPTION_REG register.

FIGURE 19-1:

BLOCK DIAGRAM OF THE TIMER0

FOSC/4

Data Bus

0

1

8

T0CKI

1

Sync

TMR0

2 TCY

0

Set Flag bit TMR0IF

on Overflow

PSA

TMR0SE

TMR0CS

8-bit

Prescaler

Overflow to Timer1

8

PS<2:0>

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 183

PIC16(L)F1454/5/9

19.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A software programmable prescaler is available for

exclusive use with Timer0. The prescaler is enabled by

clearing the PSA bit of the OPTION_REG register.

Note:

The Watchdog Timer (WDT) uses its own

independent prescaler.

There are eight prescaler options for the Timer0 mod-

ule ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION_REG

register. In order to have a 1:1 prescaler value for the

Timer0 module, the prescaler must be disabled by set-

ting the PSA bit of the OPTION_REG register.

The prescaler is not readable or writable. All instructions

writing to the TMR0 register will clear the prescaler.

19.1.4

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The TMR0IF

interrupt flag bit of the INTCON register is set every

time the TMR0 register overflows, regardless of

whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The Timer0

interrupt enable is the TMR0IE bit of the INTCON

register.

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

19.1.5

8-BIT COUNTER MODE

SYNCHRONIZATION

When in 8-Bit Counter mode, the incrementing edge on

the T0CKI pin must be synchronized to the instruction

clock. Synchronization can be accomplished by

sampling the prescaler output on the Q2 and Q4 cycles

of the instruction clock. The high and low periods of the

external clocking source must meet the timing

requirements as shown in Section 29.0 “Electrical

Specifications”.

19.1.6

OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain

unchanged while the processor is in Sleep mode.

DS41639A-page 184

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

19.2 Register Definitions: Option Register

REGISTER 19-1: OPTION_REG: OPTION REGISTER

R/W-1/1

WPUEN

R/W-1/1

INTEDG

R/W-1/1

PSA

R/W-1/1

PS<2:0>

R/W-1/1

bit 0

TMR0CS

TMR0SE

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

WPUEN: Weak Pull-Up Enable bit

1= All weak pull-ups are disabled (except MCLR, if it is enabled)

0= Weak pull-ups are enabled by individual WPUx latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

TMR0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

TMR0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is not assigned to the Timer0 module

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON2⁽²⁾

INTCON

—

INTF

—

TRIGSEL<2:0>

TMR0IE

162

96

GIE

PEIE

INTE

IOCIE

PSA

TMR0IF

IOCIF

OPTION_REG

TMR0

WPUEN

INTEDG TMR0CS TMR0SE

PS<2:0>

185

183*

132

Holding Register for the 8-bit Timer0 Count

TRISA5 TRISA4

(1)

TRISA

—

Legend:

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.

*

Page provides register information.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 185

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 186

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

• Gate Single-pulse mode

20.0 TIMER1 MODULE WITH GATE

CONTROL

• Gate Value Status

• Gate Event Interrupt

The Timer1 module is a 16-bit timer/counter with the

following features:

Figure 20-1 is a block diagram of the Timer1 module.

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Optionally synchronized comparator out

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Auto-conversion Trigger (with CCP)

• Selectable Gate Source Polarity

• Gate Toggle mode

FIGURE 20-1:

TIMER1 BLOCK DIAGRAM

T1GSS<1:0>

T1G

T1GSPM

00

From Timer0

Overflow

0

01

10

11

t1g_in

Data Bus

T1GVAL

0

1

D

Q

Single-Pulse

Acq. Control

RD

sync_C1OUT

sync_C2OUT

1

T1GCON

Q1 EN

D

Q

Interrupt

Set

TMR1GIF

T1GGO/DONE

CK

TMR1ON

T1GTM

det

R

T1GPOL

TMR1GE

Set flag bit

TMR1IF on

Overflow

TMR1ON

To Comparator Module⁽⁴⁾

Synchronized

TMR1⁽²⁾

EN

D

0

To ADC Auto-Conversion

clock input

T1CLK

TMR1H

TMR1L

Q

1

TMR1CS<1:0>

LFINTOSC

T1SYNC

T1OSO

T1OSI

OUT

11

10

Synchronize⁽³⁾

det

T1OSC

EN

Prescaler

1, 2, 4, 8

1

0

2

T1CKPS<1:0>

FOSC

Internal

Clock

01

00

FOSC/2

Internal

Clock

T1OSCEN

T1CKI

Sleep input

FOSC/4

Internal

Clock

(1)

To Clock Switching Modules

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

4: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 187

PIC16(L)F1454/5/9

20.1 Timer1 Operation

20.2 Clock Source Selection

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

The TMR1CS<1:0> bits of the T1CON register are used

to select the clock source for Timer1. Table 20-2

displays the clock source selections.

20.2.1

INTERNAL CLOCK SOURCE

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and incre-

ments on every selected edge of the external source.

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

When the FOSC internal clock source is selected, the

Timer1 register value will increment by four counts every

instruction clock cycle. Due to this condition, a two LSB

error in resolution will occur when reading the Timer1

value. To utilize the full resolution of Timer1, an

asynchronous input signal must be used to gate the

Timer1 clock input.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 20-1 displays the Timer1 enable

selections.

TABLE 20-1: TIMER1 ENABLE

SELECTIONS

The following asynchronous sources may be used:

• Asynchronous event on the T1G pin to Timer1

gate

Timer1

Operation

TMR1ON

TMR1GE

• C1 or C2 comparator input to Timer1 gate

0

1

0

1

0

1

Off

20.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

Always On

Count Enabled

When enabled to count, Timer1 is incremented on the

rising edge of the external clock input T1CKI, The

external clock source can be synchronized to the

microcontroller system clock or it can run

asynchronously.

When used as a timer with a clock oscillator, an

external 32.768 kHz crystal can be used in conjunction

with the dedicated internal oscillator circuit.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON=1) when T1CKI is

low.

TABLE 20-2: CLOCK SOURCE SELECTIONS

TMR1CS<1:0>

T1OSCEN

Clock Source

11

10

01

00

x

0

x

LFINTOSC

External Clocking on T1CKI Pin

System Clock (FOSC)

Instruction Clock (FOSC/4)

DS41639A-page 188

Preliminary

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PIC16(L)F1454/5/9

20.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

20.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

20.4 Timer1 Oscillator

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins T1OSI (input) and T1OSO

(amplifier output). This internal circuit is to be used in

conjunction with an external 32.768 kHz crystal.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator will

continue to run during Sleep.

20.6 Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 Gate Enable.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to using Timer1. A

suitable delay similar to the OST delay

can be implemented in software by

clearing the TMR1IF bit then presetting

the TMR1H:TMR1L register pair to

FC00h. The TMR1IF flag will be set when

1024 clock cycles have elapsed, thereby

indicating that the oscillator is running and

reasonably stable.

Timer1 gate can also be driven by multiple selectable

sources.

20.6.1

TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 20-4 for timing details.

20.5 Timer1 Operation in

Asynchronous Counter Mode

If the control bit T1SYNC of the T1CON register is set,

the external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If the external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 20.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

TABLE 20-3: TIMER1 GATE ENABLE

SELECTIONS

T1CLK T1GPOL

T1G

Timer1 Operation



0

1

0

1

0

1

Counts

Holds Count

Counts

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 189

PIC16(L)F1454/5/9

20.6.2

TIMER1 GATE SOURCE

SELECTION

20.6.3

TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possi-

ble to measure the full-cycle length of a Timer1 gate

signal, as opposed to the duration of a single level

pulse.

Timer1 gate source selections are shown in Table 20-4.

Source selection is controlled by the T1GSS bits of the

T1GCON register. The polarity for each available source

is also selectable. Polarity selection is controlled by the

T1GPOL bit of the T1GCON register.

The Timer1 gate source is routed through a flip-flop that

changes state on every incrementing edge of the sig-

nal. See Figure 20-4 for timing details.

TABLE 20-4: TIMER1 GATE SOURCES

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

T1GSS

Timer1 Gate Source

Timer1 Gate Pin

00

01

Overflow of Timer0

(TMR0 increments from FFh to 00h)

Note:

Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

10

11

Comparator 1 Output sync_C1OUT

(optionally Timer1 synchronized output)

Comparator 2 Output sync_C2OUT

(optionally Timer1 synchronized output)

20.6.4

TIMER1 GATE SINGLE-PULSE

MODE

20.6.2.1

T1G Pin Gate Operation

When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single-pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the T1GGO/

DONE bit in the T1GCON register must be set. The

Timer1 will be fully enabled on the next incrementing

edge. On the next trailing edge of the pulse, the T1GGO/

DONE bit will automatically be cleared. No other gate

events will be allowed to increment Timer1 until the

T1GGO/DONE bit is once again set in software. See

Figure 20-5 for timing details.

The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1

gate circuitry.

20.6.2.2

Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a low-to-

high pulse will automatically be generated and inter-

nally supplied to the Timer1 gate circuitry.

20.6.2.3

Comparator C1 Gate Operation

The output resulting from a Comparator 1 operation can

be selected as a source for Timer1 gate control. The

If the Single-Pulse Gate mode is disabled by clearing the

T1GSPM bit in the T1GCON register, the T1GGO/DONE

bit should also be cleared.

Comparator

1

output (sync_C1OUT) can be

synchronized to the Timer1 clock or left asynchronous.

For more information see Section 18.4.1 “Comparator

Output Synchronization”.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1 gate

source to be measured. See Figure 20-6 for timing

details.

20.6.2.4

Comparator C2 Gate Operation

The output resulting from a Comparator 2 operation

can be selected as a source for Timer1 gate control.

The Comparator 2 output (sync_C2OUT) can be

synchronized to the Timer1 clock or left asynchronous.

For more information see Section 18.4.1 “Comparator

Output Synchronization”

20.6.5

TIMER1 GATE VALUE STATUS

When Timer1 Gate Value Status is utilized, it is possible

to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON

register. The T1GVAL bit is valid even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

20.6.6

TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is pos-

sible to generate an interrupt upon the completion of a

gate event. When the falling edge of T1GVAL occurs,

the TMR1GIF flag bit in the PIR1 register will be set. If

the TMR1GIE bit in the PIE1 register is set, then an

interrupt will be recognized.

The TMR1GIF flag bit operates even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

DS41639A-page 190

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PIC16(L)F1454/5/9

20.7 Timer1 Interrupt

20.8 Timer1 Operation During Sleep

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

• TMR1CS bits of the T1CON register must be

configured

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

• T1OSCEN bit of the T1CON register must be

configured

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine.

Timer1 oscillator will continue to operate in Sleep

regardless of the T1SYNC bit setting.

FIGURE 20-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 191

PIC16(L)F1454/5/9

FIGURE 20-3:

TIMER1 GATE ENABLE MODE

TMR1GE

T1GPOL

t1g_in

T1CKI

T1GVAL

Timer1

N

N + 1

N + 2

N + 3

N + 4

FIGURE 20-4:

TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

t1g_in

T1CKI

T1GVAL

Timer1

N

N + 1 N + 2 N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

DS41639A-page 192

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 20-5:

TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

t1g_in

T1CKI

T1GVAL

Timer1

N

N + 1

N + 2

Cleared by

software

Set by hardware on

falling edge of T1GVAL

Cleared by software

TMR1GIF

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 193

PIC16(L)F1454/5/9

FIGURE 20-6:

TMR1GE

T1GPOL

TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

T1GSPM

T1GTM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

t1g_in

T1CKI

T1GVAL

Timer1

N + 4

N + 2 N + 3

N

N + 1

Set by hardware on

falling edge of T1GVAL

Cleared by

software

Cleared by software

TMR1GIF

DS41639A-page 194

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

20.9 Register Definitions: Timer1 Control

REGISTER 20-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u

T1SYNC

U-0

—

R/W-0/u

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

TMR1CS<1:0>: Timer1 Clock Source Select bits

11=Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)

10=Timer1 clock source is pin or oscillator:

If T1OSCEN = 0:

External clock from T1CKI pin (on the rising edge)

If T1OSCEN = 1:

Crystal oscillator on T1OSI/T1OSO pins

01=Timer1 clock source is system clock (FOSC)

00=Timer1 clock source is instruction clock (FOSC/4)

bit 5-4

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T1OSCEN: LP Oscillator Enable Control bit

1= Dedicated Timer1 oscillator circuit enabled

0= Dedicated Timer1 oscillator circuit disabled

T1SYNC: Timer1 Synchronization Control bit

1= Do not synchronize asynchronous clock input

0= Synchronize asynchronous clock input with system clock (FOSC)

bit 1

bit 0

Unimplemented: Read as ‘0’

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1 and clears Timer1 gate flip-flop

 2012 Microchip Technology Inc.

Preliminary

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PIC16(L)F1454/5/9

REGISTER 20-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u

T1GPOL

R/W-0/u

T1GTM

R/W-0/u

R/W/HC-0/u

R-x/x

R/W-0/u

TMR1GE

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 counting is controlled by the Timer1 gate function

0= Timer1 counts regardless of Timer1 gate function

bit 6

bit 5

T1GPOL: Timer1 Gate Polarity bit

1= Timer1 gate is active-high (Timer1 counts when gate is high)

0= Timer1 gate is active-low (Timer1 counts when gate is low)

T1GTM: Timer1 Gate Toggle Mode bit

1= Timer1 Gate Toggle mode is enabled

0= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4

T1GSPM: Timer1 Gate Single-Pulse Mode bit

1= Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate

0= Timer1 Gate Single-Pulse mode is disabled

bit 3

T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1= Timer1 gate single-pulse acquisition is ready, waiting for an edge

0= Timer1 gate single-pulse acquisition has completed or has not been started

bit 2

T1GVAL: Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

bit 1-0

T1GSS<1:0>: Timer1 Gate Source Select bits

11= Comparator 2 optionally synchronized output (sync_C2OUT)

10= Comparator 1 optionally synchronized output (sync_C1OUT)

01= Timer0 overflow output

00= Timer1 gate pin

DS41639A-page 196

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 20-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA⁽³⁾

APFCON

INTCON

PIE1

—

ANSA4

—

P2SEL⁽²⁾

TMR0IF

—

133

130

96

CLKRSEL SDOSEL⁽²⁾

SSSEL

TMR0IE

RCIE

T1GSEL

IOCIE

—

GIE

PEIE

INTE

TXIE

TXIF

INTF

IOCIF

TMR1IE

TMR1IF

TMR1GIE

TMR1GIF

ADIE⁽³⁾

ADIF⁽³⁾

SSP1IE

SSP1IF

TMR2IE

TMR2IF

97

PIR1

RCIF

—

99

TMR1H

TMR1L

TRISA

Holding Register for the Most Significant Byte of the 16-bit TMR1 Count

187*

132

195

196

Holding Register for the Least Significant Byte of the 16-bit TMR1 Count

(1)

—

TRISA5

TRISA4

—

T1CON

T1GCON

TMR1CS<1:0>

TMR1GE T1GPOL

T1CKPS<1:0>

T1OSCEN

T1SYNC

T1GVAL

—

TMR1ON

T1GTM

T1GSPM

T1GGO/

DONE

T1GSS<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.

*

Page provides register information.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1455 only.

3: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 197

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 198

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

21.0 TIMER2 MODULE

The Timer2 module incorporates the following features:

• 8-bit Timer and Period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16,

and 1:64)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match with PR2, respectively

• Optional use as the shift clock for the MSSP

module (Timer2 only)

See Figure 21-1 for a block diagram of Timer2.

FIGURE 21-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

Output

TMR2

Prescaler

Reset

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16, 1:64

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS<1:0>

4

T2OUTPS<3:0>

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 199

PIC16(L)F1454/5/9

21.1 Timer2 Operation

21.3 Timer2 Output

The clock input to the Timer2 module is the system

instruction clock (FOSC/4).

The unscaled output of TMR2 is available primarily to

the PWM module, where it is used as a time base for

operation.

TMR2 increments from 00h on each clock edge.

Timer2 can be optionally used as the shift clock source

for the MSSP module operating in SPI mode.

Additional information is provided in Section 22.1

“Master SSP (MSSP) Module Overview”.

A 4-bit counter/prescaler on the clock input allows direct

input, divide-by-4 and divide-by-16 prescale options.

These options are selected by the prescaler control bits,

T2CKPS<1:0> of the T2CON register. The value of

TMR2 is compared to that of the Period register, PR2, on

each clock cycle. When the two values match, the

comparator generates a match signal as the timer

output. This signal also resets the value of TMR2 to 00h

on the next cycle and drives the output counter/

postscaler (see Section 21.2 “Timer2 Interrupt”).

21.4 Timer2 Operation During Sleep

Timer2 cannot be operated while the processor is in

Sleep mode. The contents of the TMR2 and PR2

registers will remain unchanged while the processor is

in Sleep mode.

The TMR2 and PR2 registers are both directly readable

and writable. The TMR2 register is cleared on any

device Reset, whereas the PR2 register initializes to

FFh. Both the prescaler and postscaler counters are

cleared on the following events:

• a write to the TMR2 register

• a write to the T2CON register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• MCLR Reset

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

• RESETInstruction

Note:

TMR2 is not cleared when T2CON is

written.

21.2 Timer2 Interrupt

Timer2 can also generate an optional device interrupt.

The Timer2 output signal (TMR2-to-PR2 match)

provides the input for the 4-bit counter/postscaler. This

counter generates the TMR2 match interrupt flag which

is latched in TMR2IF of the PIR1 register. The interrupt

is enabled by setting the TMR2 Match Interrupt Enable

bit, TMR2IE of the PIE1 register.

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, T2OUTPS<3:0>, of the T2CON register.

DS41639A-page 200

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

21.5 Register Definitions: Timer2 Control

REGISTER 21-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

R/W-0/0

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-3

T2OUTPS<3:0>: Timer2 Output Postscaler Select bits

1111= 1:16 Postscaler

1110= 1:15 Postscaler

1101= 1:14 Postscaler

1100= 1:13 Postscaler

1011= 1:12 Postscaler

1010= 1:11 Postscaler

1001= 1:10 Postscaler

1000= 1:9 Postscaler

0111= 1:8 Postscaler

0110= 1:7 Postscaler

0101= 1:6 Postscaler

0100= 1:5 Postscaler

0011= 1:4 Postscaler

0010= 1:3 Postscaler

0001= 1:2 Postscaler

0000= 1:1 Postscaler

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

11= Prescaler is 64

10= Prescaler is 16

01= Prescaler is 4

00= Prescaler is 1

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 201

PIC16(L)F1454/5/9

TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

TMR0IE

RCIE

INTE

TXIE

TXIF

IOCIE

SSP1IE

SSP1IF

TMR0IF

INTF

IOCIF

96

97

TMR1GIE

TMR1GIF

ADIE⁽¹⁾

ADIF⁽¹⁾

—

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

RCIF

99

PR2

Timer2 Module Period Register

199*

291

201

199*

PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL

PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL

—

T2CON

TMR2

—

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

Holding Register for the 8-bit TMR2 Count

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.

*

Page provides register information.

Note 1: PIC16(L)F1455/9 only.

DS41639A-page 202

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

22.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

22.1 Master SSP (MSSP) Module

Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSPx module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

The SPI interface supports the following modes and

features:

• Master mode

• Slave mode

• Clock Parity

• Slave Select Synchronization (Slave mode only)

• Daisy-chain connection of slave devices

Figure 22-1 is a block diagram of the SPI interface

module.

FIGURE 22-1:

MSSP BLOCK DIAGRAM (SPI MODE)

Data Bus

Read

Write

SSPBUF Reg

SSPSR Reg

SDI

SDO_out

Shift

Clock

bit 0

SDO

SS

Control

Enable

SS

2 (CKP, CKE)

Clock Select

Edge

Select

SCK_out

SSPM<3:0>

4

TMR2 Output

2

(

)

SCK

TOSC

Prescaler

4, 16, 64

Edge

Select

Baud Rate

Generator

(SSPADD)

TRIS bit

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 203

PIC16(L)F1454/5/9

The I²C interface supports the following modes and

features:

• Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited Multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

• Clock stretching

• Bus collision detection

• General call address matching

• Address masking

• Address Hold and Data Hold modes

• Selectable SDA hold times

Figure 22-2 is a block diagram of the I²C interface mod-

ule in Master mode. Figure 22-3 is a diagram of the I²C

interface module in Slave mode.

2

FIGURE 22-2:

MSSP BLOCK DIAGRAM (I C™ MASTER MODE)

Internal

Data Bus

[SSPM<3:0>]

Read

Write

SSP1BUF

SSPSR

Baud Rate

Generator

(SSPADD)

SDA

Shift

Clock

SDA in

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate (SSPCON2)

SCL

Start bit detect,

Stop bit detect

SCL in

Bus Collision

Write collision detect

Clock arbitration

State counter for

Set/Reset: S, P, SSP1STAT, WCOL, SSPOV

Reset SEN, PEN (SSPCON2)

Set SSPIF, BCLIF

end of XMIT/RCV

Address Match detect

DS41639A-page 204

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

2

FIGURE 22-3:

MSSP BLOCK DIAGRAM (I C™ SLAVE MODE)

Internal

Data Bus

Read

Write

SSPBUF Reg

SSPSR Reg

SCL

SDA

Shift

Clock

MSb

LSb

SSPMSK Reg

Match Detect

SSPADD Reg

Addr Match

Set, Reset

S, P bits

(SSPSTAT Reg)

Start and

Stop bit Detect

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 205

PIC16(L)F1454/5/9

its SDO pin) and the slave device is reading this bit and

saving it as the LSb of its shift register, that the slave

device is also sending out the MSb from its shift register

(on its SDO pin) and the master device is reading this

bit and saving it as the LSb of its shift register.

22.2 SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is

a

synchronous serial data communication bus that

operates in Full-Duplex mode. Devices communicate

in a master/slave environment where the master device

After eight bits have been shifted out, the master and

slave have exchanged register values.

initiates the communication.

A slave device is

controlled through a Chip Select known as Slave

Select.

If there is more data to exchange, the shift registers are

loaded with new data and the process repeats itself.

The SPI bus specifies four signal connections:

Whether the data is meaningful or not (dummy data),

depends on the application software. This leads to

three scenarios for data transmission:

• Serial Clock (SCK)

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Slave Select (SS)

• Master sends useful data and slave sends dummy

data.

Figure 22-1 shows the block diagram of the MSSP

module when operating in SPI mode.

• Master sends useful data and slave sends useful

data.

The SPI bus operates with a single master device and

one or more slave devices. When multiple slave

devices are used, an independent Slave Select con-

nection is required from the master device to each

slave device.

• Master sends dummy data and slave sends useful

data.

Transmissions may involve any number of clock

cycles. When there is no more data to be transmitted,

the master stops sending the clock signal and it dese-

lects the slave.

Figure 22-4 shows a typical connection between a

master device and multiple slave devices.

Every slave device connected to the bus that has not

been selected through its slave select line must disre-

gard the clock and transmission signals and must not

transmit out any data of its own.

The master selects only one slave at a time. Most slave

devices have tri-state outputs so their output signal

appears disconnected from the bus when they are not

selected.

Transmissions involve two shift registers, eight bits in

size, one in the master and one in the slave. With either

the master or the slave device, data is always shifted

out one bit at a time, with the Most Significant bit (MSb)

shifted out first. At the same time, a new Least

Significant bit (LSb) is shifted into the same register.

Figure 22-5 shows a typical connection between two

processors configured as master and slave devices.

Data is shifted out of both shift registers on the pro-

grammed clock edge and latched on the opposite edge

of the clock.

The master device transmits information out on its SDO

output pin which is connected to, and received by, the

slave's SDI input pin. The slave device transmits infor-

mation out on its SDO output pin, which is connected

to, and received by, the master's SDI input pin.

To begin communication, the master device first sends

out the clock signal. Both the master and the slave

devices should be configured for the same clock polar-

ity.

The master device starts a transmission by sending out

the MSb from its shift register. The slave device reads

this bit from that same line and saves it into the LSb

position of its shift register.

During each SPI clock cycle, a full-duplex data

transmission occurs. This means that while the master

device is sending out the MSb from its shift register (on

DS41639A-page 206

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 22-4:

SPI MASTER AND MULTIPLE SLAVE CONNECTION

SCK

SDO

SCK

SDI

SDO

SS

SPI Master

SPI Slave

#1

SDI

General I/O

SCK

SDI

SDO

SS

SPI Slave

#2

SCK

SDI

SDO

SS

SPI Slave

#3

22.2.1 SPI MODE REGISTERS

The MSSP module has five registers for SPI mode

operation. These are:

• MSSP STATUS register (SSPSTAT)

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 3 (SSPCON3)

• MSSP Data Buffer register (SSPBUF)

• MSSP Address register (SSPADD)

• MSSP Shift register (SSPSR)

(Not directly accessible)

SSPCON1 and SSPSTAT are the control and STATUS

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower six bits of the

SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

In one SPI master mode, SSPADD can be loaded with

a value used in the Baud Rate Generator. More infor-

mation on the Baud Rate Generator is available in

Section 22.7 “Baud Rate Generator”.

SSPSR is the shift register used for shifting data in and

out. SSPBUF provides indirect access to the SSPSR

register. SSPBUF is the buffer register to which data

bytes are written, and from which data bytes are read.

In receive operations, SSPSR and SSPBUF together

create a buffered receiver. When SSPSR receives a

complete byte, it is transferred to SSPBUF and the

SSPIF interrupt is set.

During transmission, the SSPBUF is not buffered. A

write to SSPBUF will write to both SSPBUF and

SSPSR.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 207

PIC16(L)F1454/5/9

22.2.2 SPI MODE OPERATION

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the eight bits of

data have been received, that byte is moved to the

SSPBUF register. Then, the Buffer Full Detect bit, BF

of the SSPSTAT register, and the interrupt flag bit,

SSPIF, are set. This double-buffering of the received

data (SSPBUF) allows the next byte to start reception

before reading the data that was just received. Any

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

write

to

the

SSPBUF

register

during

• Clock Edge (output data on rising/falling edge of

SCK)

transmission/reception of data will be ignored and the

write collision detect bit WCOL of the SSPCON1

register, will be set. User software must clear the

WCOL bit to allow the following write(s) to the SSPBUF

register to complete successfully.

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port, SSP Enable bit, SSPEN of the

SSPCON1 register, must be set. To reset or reconfig-

ure SPI mode, clear the SSPEN bit, re-initialize the

SSPCONx registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed as follows:

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF of the SSPSTAT register, indicates

when SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. If the interrupt method is not going to

be used, then software polling can be done to ensure

that a write collision does not occur.

• SDI must have corresponding TRIS bit set

• SDO must have corresponding TRIS bit cleared

• SCK (Master mode) must have corresponding

TRIS bit cleared

• SCK (Slave mode) must have corresponding

TRIS bit set

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the SSPSTAT register indicates the

various Status conditions.

• SS must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

FIGURE 22-5:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xx

= 1010

SPI Slave SSPM<3:0> = 010x

SDO

SDI

Serial Input Buffer

(SSPBUF)

(BUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

SS

Slave Select

(optional)

General I/O

Processor 2

Processor 1

DS41639A-page 208

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

The clock polarity is selected by appropriately

programming the CKP bit of the SSPCON1 register

and the CKE bit of the SSPSTAT register. This then,

would give waveforms for SPI communication as

shown in Figure 22-6, Figure 22-8, Figure 22-9 and

Figure 22-10, where the MSB is transmitted first. In

Master mode, the SPI clock rate (bit rate) is user

programmable to be one of the following:

22.2.3

SPI MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK line. The master

determines when the slave (Processor 2, Figure 22-5)

is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal present on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and Status bits

appropriately set).

• FOSC/4 (or TCY)

• FOSC/16 (or 4 * TCY)

• FOSC/64 (or 16 * TCY)

• Timer2 output/2

• Fosc/(4 * (SSPADD + 1))

Figure 22-6 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

FIGURE 22-6:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

(CKE = 0)

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPIF

SSPSR to

SSPBUF

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 209

PIC16(L)F1454/5/9

22.2.4

SPI SLAVE MODE

22.2.5

SLAVE SELECT

SYNCHRONIZATION

In Slave mode, the data is transmitted and received as

external clock pulses appear on SCK. When the last

bit is latched, the SSPIF interrupt flag bit is set.

The Slave Select can also be used to synchronize com-

munication. The Slave Select line is held high until the

master device is ready to communicate. When the

Slave Select line is pulled low, the slave knows that a

new transmission is starting.

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCK pin. The Idle state is

determined by the CKP bit of the SSPCON1 register.

If the slave fails to receive the communication properly,

it will be reset at the end of the transmission, when the

Slave Select line returns to a high state. The slave is

then ready to receive a new transmission when the

Slave Select line is pulled low again. If the Slave Select

line is not used, there is a risk that the slave will even-

tually become out of sync with the master. If the slave

misses a bit, it will always be one bit off in future trans-

missions. Use of the Slave Select line allows the slave

and master to align themselves at the beginning of

each transmission.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. The shift register is clocked from the SCK pin

input and when a byte is received, the device will gen-

erate an interrupt. If enabled, the device will wake-up

from Sleep.

22.2.4.1 Daisy-Chain Configuration

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSPCON1<3:0> = 0100).

The SPI bus can sometimes be connected in a

daisy-chain configuration. The first slave output is con-

nected to the second slave input, the second slave

output is connected to the third slave input, and so on.

The final slave output is connected to the master input.

Each slave sends out, during a second group of clock

pulses, an exact copy of what was received during the

first group of clock pulses. The whole chain acts as

one large communication shift register. The

daisy-chain feature only requires a single Slave Select

line from the master device.

When the SS pin is low, transmission and reception are

enabled and the SDO pin is driven.

When the SS pin goes high, the SDO pin is no longer

driven, even if in the middle of a transmitted byte and

becomes a floating output. External pull-up/pull-down

resistors may be desirable depending on the applica-

tion.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPCON1<3:0>

=

Figure 22-7 shows the block diagram of a typical

daisy-chain connection when operating in SPI Mode.

0100), the SPI module will reset if the SS

pin is set to VDD.

In a daisy-chain configuration, only the most recent

byte on the bus is required by the slave. Setting the

BOEN bit of the SSPCON3 register will enable writes

to the SSPBUF register, even if the previous byte has

not been read. This allows the software to ignore data

that may not apply to it.

2: When the SPI is used in Slave mode with

CKE set; the user must enable SS pin

control.

3: While operated in SPI Slave mode the

SMP bit of the SSPSTAT register must

remain clear.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

DS41639A-page 210

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 22-7:

SPI DAISY-CHAIN CONNECTION

SCK

SPI Master

SDO

SDI

SDO

SS

SPI Slave

#1

General I/O

SCK

SDI

SDO

SS

SPI Slave

#2

SCK

SDI

SDO

SS

SPI Slave

#3

FIGURE 22-8:

SLAVE SELECT SYNCHRONOUS WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

Shift register SSPSR

and bit count are reset

SSPBUF to

SSPSR

bit 6

bit 7

bit 0

SDO

SDI

bit 7

bit 0

bit 7

Input

Sample

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 211

PIC16(L)F1454/5/9

FIGURE 22-9:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

Valid

bit 6

bit 2

bit 5

bit 4

bit 3

bit 1

bit 0

SDO

bit 7

SDI

bit 0

bit 7

Input

Sample

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

Write Collision

detection active

FIGURE 22-10:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

Valid

bit 6

bit 3

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

SDI

bit 0

Input

Sample

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

Write Collision

detection active

DS41639A-page 212

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

22.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmis-

sion/reception will remain in that state until the device

wakes. After the device returns to Run mode, the mod-

ule will resume transmitting and receiving data.

In SPI Master mode, module clocks may be operating

at a different speed than when in full power mode; in

the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the MSSP

clock is much faster than the system clock.

In SPI Slave mode, the SPI Transmit/Receive Shift

register operates asynchronously to the device. This

allows the device to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

register. When all eight bits have been received, the

MSSP interrupt flag bit will be set and if enabled, will

wake the device.

In Slave mode, when MSSP interrupts are enabled,

after the master completes sending data, an MSSP

interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSP inter-

rupts should be disabled.

TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA⁽³⁾

INTCON

PIE1

—

ANSA4

INTE

TXIE

—

TMR0IF

—

133

96

GIE

PEIE

TMR0IE

RCIE

IOCIE

SSP1IE

SSP1IF

INTF

IOCIF

TMR1GIE

TMR1GIF

ADIE⁽³⁾

ADIF⁽³⁾

TMR2IE

TMR2IF

TMR1IE

TMR1IF

97

PIR1

RCIF

TXIF

—

99

SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register

207*

253

255

251

132

140

SSP1CON1

WCOL

SSPOV

PCIE

CKE

—

SSPEN

SCIE

CKP

BOEN

P

SSPM<3:0>

SSP1CON3 ACKTIM

SDAHT

S

SBCDE

R/W

AHEN

DHEN

BF

SSP1STAT

TRISA

SMP

—

D/A

UA

(1)

—

TRISA5

TRISC5

TRISA4

TRISC4

—

TRISC

TRISC7⁽²⁾TRISC6⁽²⁾

TRISC3

TRISC2

TRISC1

TRISC0

Legend:

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

*

Page provides register information.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1459 only.

3: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 213

PIC16(L)F1454/5/9

2

FIGURE 22-11:

I C MASTER/

22.3 I C MODE OVERVIEW

SLAVE CONNECTION

The Inter-Integrated Circuit Bus (I²C) is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment where the master

devices initiate the communication. A Slave device is

controlled through addressing.

VDD

SCL

The I²C bus specifies two signal connections:

VDD

• Serial Clock (SCL)

• Serial Data (SDA)

Master

Slave

SDA

Figure 22-11 shows the block diagram of the MSSP

module when operating in I²C mode.

Both the SCL and SDA connections are bidirectional

open-drain lines, each requiring pull-up resistors for the

supply voltage. Pulling the line to ground is considered

a logical zero and letting the line float is considered a

logical one.

The Acknowledge bit (ACK) is an active-low signal,

which holds the SDA line low to indicate to the transmit-

ter that the slave device has received the transmitted

data and is ready to receive more.

Figure 22-11 shows a typical connection between two

processors configured as master and slave devices.

The I²C bus can operate with one or more master

devices and one or more slave devices.

The transition of a data bit is always performed while

the SCL line is held low. Transitions that occur while the

SCL line is held high are used to indicate Start and Stop

bits.

If the master intends to write to the slave, then it repeat-

edly sends out a byte of data, with the slave responding

after each byte with an ACK bit. In this example, the

master device is in Master Transmit mode and the

slave is in Slave Receive mode.

There are four potential modes of operation for a given

device:

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

If the master intends to read from the slave, then it

repeatedly receives a byte of data from the slave, and

responds after each byte with an ACK bit. In this exam-

ple, the master device is in Master Receive mode and

the slave is Slave Transmit mode.

(master is receiving data from a slave)

• Slave Transmit mode

(slave is transmitting data to a master)

• Slave Receive mode

(slave is receiving data from the master)

On the last byte of data communicated, the master

device may end the transmission by sending a Stop bit.

If the master device is in Receive mode, it sends the

Stop bit in place of the last ACK bit. A Stop bit is indi-

cated by a low-to-high transition of the SDA line while

the SCL line is held high.

To begin communication, a master device starts out in

Master Transmit mode. The master device sends out a

Start bit followed by the address byte of the slave it

intends to communicate with. This is followed by a sin-

gle Read/Write bit, which determines whether the mas-

ter intends to transmit to or receive data from the slave

device.

In some cases, the master may want to maintain con-

trol of the bus and re-initiate another transmission. If

so, the master device may send another Start bit in

place of the Stop bit or last ACK bit when it is in receive

mode.

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwise known as an ACK.

The master then continues in either Transmit mode or

Receive mode and the slave continues in the comple-

ment, either in Receive mode or Transmit mode,

respectively.

The I²C bus specifies three message protocols;

• Single message where a master writes data to a

slave.

A Start bit is indicated by a high-to-low transition of the

SDA line while the SCL line is held high. Address and

data bytes are sent out, Most Significant bit (MSb) first.

The Read/Write bit is sent out as a logical one when the

master intends to read data from the slave, and is sent

out as a logical zero when it intends to write data to the

slave.

• Single message where a master reads data from

a slave.

• Combined message where a master initiates a

minimum of two writes, or two reads, or a

combination of writes and reads, to one or more

slaves.

DS41639A-page 214

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

When one device is transmitting a logical one, or letting

the line float, and a second device is transmitting a log-

ical zero, or holding the line low, the first device can

detect that the line is not a logical one. This detection,

when used on the SCL line, is called clock stretching.

Clock stretching gives slave devices a mechanism to

control the flow of data. When this detection is used on

the SDA line, it is called arbitration. Arbitration ensures

that there is only one master device communicating at

any single time.

22.3.2

ARBITRATION

Each master device must monitor the bus for Start and

Stop bits. If the device detects that the bus is busy, it

cannot begin a new message until the bus returns to an

Idle state.

However, two master devices may try to initiate a trans-

mission on or about the same time. When this occurs,

the process of arbitration begins. Each transmitter

checks the level of the SDA data line and compares it

to the level that it expects to find. The first transmitter to

observe that the two levels do not match, loses arbitra-

tion, and must stop transmitting on the SDA line.

22.3.1

CLOCK STRETCHING

When a slave device has not completed processing

data, it can delay the transfer of more data through the

process of Clock Stretching. An addressed slave

device may hold the SCL clock line low after receiving

or sending a bit, indicating that it is not yet ready to con-

tinue. The master that is communicating with the slave

will attempt to raise the SCL line in order to transfer the

next bit, but will detect that the clock line has not yet

been released. Because the SCL connection is

open-drain, the slave has the ability to hold that line low

until it is ready to continue communicating.

For example, if one transmitter holds the SDA line to a

logical one (lets it float) and a second transmitter holds

it to a logical zero (pulls it low), the result is that the

SDA line will be low. The first transmitter then observes

that the level of the line is different than expected and

concludes that another transmitter is communicating.

The first transmitter to notice this difference is the one

that loses arbitration and must stop driving the SDA

line. If this transmitter is also a master device, it also

must stop driving the SCL line. It then can monitor the

lines for a Stop condition before trying to reissue its

transmission. In the meantime, the other device that

has not noticed any difference between the expected

and actual levels on the SDA line continues with its

original transmission. It can do so without any compli-

cations, because so far, the transmission appears

exactly as expected with no other transmitter disturbing

the message.

Clock stretching allows receivers that cannot keep up

with a transmitter to control the flow of incoming data.

Slave Transmit mode can also be arbitrated, when a

master addresses multiple slaves, but this is less com-

mon.

If two master devices are sending a message to two dif-

ferent slave devices at the address stage, the master

sending the lower slave address always wins arbitra-

tion. When two master devices send messages to the

same slave address, and addresses can sometimes

refer to multiple slaves, the arbitration process must

continue into the data stage.

Arbitration usually occurs very rarely, but it is a neces-

sary process for proper multi-master support.

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TABLE 22-2: I C BUS TERMS

22.4 I C MODE OPERATION

TERM

Description

All MSSP I²C communication is byte oriented and

shifted out MSb first. Six SFR registers and two

interrupt flags interface the module with the PIC^®

microcontroller and user software. Two pins, SDA and

SCL, are exercised by the module to communicate

with other external I²C devices.

Transmitter

The device which shifts data out

onto the bus.

Receiver

Master

The device which shifts data in

from the bus.

The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

22.4.1 BYTE FORMAT

All communication in I²C is done in 9-bit segments. A

byte is sent from a master to a slave or vice-versa, fol-

lowed by an Acknowledge bit sent back. After the 8th

falling edge of the SCL line, the device outputting data

on the SDA changes that pin to an input and reads in

an acknowledge value on the next clock pulse.

Slave

The device addressed by the mas-

ter.

Multi-master

Arbitration

A bus with more than one device

that can initiate data transfers.

Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

The clock signal, SCL, is provided by the master. Data

is valid to change while the SCL signal is low, and

sampled on the rising edge of the clock. Changes on

the SDA line while the SCL line is high define special

conditions on the bus, explained below.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

22.4.2 DEFINITION OF I²C TERMINOLOGY

Idle

No master is controlling the bus,

and both SDA and SCL lines are

high.

There is language and terminology in the description

of I²C communication that have definitions specific to

I²C. That word usage is defined below and may be

used in the rest of this document without explanation.

This table was adapted from the Philips I²C

specification.

Active

Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

22.4.3 SDA AND SCL PINS

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSPADD.

Selection of any I²C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain. These

pins should be set by the user to inputs by setting the

appropriate TRIS bits.

Write Request

Read Request

Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Note: Data is tied to output zero when an I²C

Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

mode is enabled.

22.4.4 SDA HOLD TIME

The hold time of the SDA pin is selected by the SDAHT

bit of the SSPCON3 register. Hold time is the time SDA

is held valid after the falling edge of SCL. Setting the

SDAHT bit selects a longer 300 ns minimum hold time

and may help on buses with large capacitance.

Clock Stretching When a device on the bus hold

SCL low to stall communication.

Bus Collision

Any time the SDA line is sampled

low by the module while it is out-

putting and expected high state.

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22.4.5 START CONDITION

22.4.7 RESTART CONDITION

The I²C specification defines a Start condition as a

transition of SDA from a high to a low state while SCL

line is high. A Start condition is always generated by

the master and signifies the transition of the bus from

an Idle to an Active state. Figure 22-12 shows wave

forms for Start and Stop conditions.

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave. Figure 22-13 shows wave forms for a

Restart condition.

A bus collision can occur on a Start condition if the

module samples the SDA line low before asserting it

low. This does not conform to the I²C Specification that

states no bus collision can occur on a Start.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

22.4.6 STOP CONDITION

A Stop condition is a transition of the SDA line from

low-to-high state while the SCL line is high.

Note: At least one SCL low time must appear

before a Stop is valid, therefore, if the SDA

line goes low then high again while the SCL

line stays high, only the Start condition is

detected.

After a full match with R/W clear in 10-bit mode, a prior

match flag is set and maintained. Until a Stop condi-

tion, a high address with R/W clear, or high address

match fails.

22.4.8 START/STOP CONDITION INTERRUPT

MASKING

The SCIE and PCIE bits of the SSPCON3 register can

enable the generation of an interrupt in Slave modes

that do not typically support this function. Slave modes

where interrupt on Start and Stop detect are already

enabled, these bits will have no effect.

2

FIGURE 22-12:

I C START AND STOP CONDITIONS

SDA

SCL

S

P

Change of

Data Allowed

Stop

Start

Condition

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FIGURE 22-13:

I C RESTART CONDITION

Sr

Change of

Data Allowed

Restart

Condition

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22.4.9 ACKNOWLEDGE SEQUENCE

22.5 I C SLAVE MODE OPERATION

The 9th SCL pulse for any transferred byte in I²C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDA line low. The transmitter must release control

of the line during this time to shift in the response. The

Acknowledge (ACK) is an active-low signal, pulling the

SDA line low indicated to the transmitter that the

device has received the transmitted data and is ready

to receive more.

The MSSP Slave mode operates in one of four modes

selected in the SSPM bits of SSPCON1 register. The

modes can be divided into 7-bit and 10-bit Addressing

mode. 10-bit Addressing modes operate the same as

7-bit with some additional overhead for handling the

larger addresses.

Modes with Start and Stop bit interrupts operated the

same as the other modes with SSPIF additionally get-

ting set upon detection of a Start, Restart, or Stop

condition.

The result of an ACK is placed in the ACKSTAT bit of

the SSPCON2 register.

22.5.1 SLAVE MODE ADDRESSES

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSPCON2 regis-

ter is set/cleared to determine the response.

The SSPADD register (Register 22-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSPBUF register and an inter-

rupt is generated. If the value does not match, the

module goes idle and no indication is given to the soft-

ware that anything happened.

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSPCON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSPSTAT register

or the SSPOV bit of the SSPCON1 register are set

when a byte is received.

The SSP Mask register (Register 22-5) affects the

address matching process. See Section 22.5.9 “SSP

Mask Register” for more information.

When the module is addressed, after the 8th falling

edge of SCL on the bus, the ACKTIM bit of the

SSPCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

22.5.1.1 I²C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

22.5.1.2 I²C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSb of the 10-bit address and

stored in bits 2 and 1 of the SSPADD register.

After the acknowledge of the high byte the UA bit is set

and SCL is held low until the user updates SSPADD

with the low address. The low address byte is clocked

in and all eight bits are compared to the low address

value in SSPADD. Even if there is not an address

match; SSPIF and UA are set, and SCL is held low

until SSPADD is updated to receive a high byte again.

When SSPADD is updated the UA bit is cleared. This

ensures the module is ready to receive the high

address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave hard-

ware will then acknowledge the read request and pre-

pare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

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22.5.2 SLAVE RECEPTION

22.5.2.2 7-bit Reception with AHEN and DHEN

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPSTAT register is cleared.

The received address is loaded into the SSPBUF reg-

ister and acknowledged.

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the 8th fall-

ing edge of SCL. These additional interrupts allow the

slave software to decide whether it wants to ACK the

receive address or data byte, rather than the hard-

ware. This functionality adds support for PMBus™ that

was not present on previous versions of this module.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF of the SSPSTAT

register is set, or bit SSPOV of the SSPCON1 register

is set. The BOEN bit of the SSPCON3 register modifies

this operation. For more information see Register 22-4.

This list describes the steps that need to be taken by

slave software to use these options for I²C commun-

cation. Figure 22-16 displays a module using both

address and data holding. Figure 22-17 includes the

operation with the SEN bit of the SSPCON2 register

set.

An MSSP interrupt is generated for each transferred

data byte. Flag bit, SSPIF, must be cleared by software.

When the SEN bit of the SSPCON2 register is set, SCL

will be held low (clock stretch) following each received

byte. The clock must be released by setting the CKP

bit of the SSPCON1 register, except sometimes in

10-bit mode. See Section 22.2.3 “SPI Master Mode”

for more detail.

1. S bit of SSPSTAT is set; SSPIF is set if interrupt

on Start detect is enabled.

2. Matching address with R/W bit clear is clocked

in. SSPIF is set and CKP cleared after the 8th

falling edge of SCL.

22.5.2.1 7-bit Addressing Reception

3. Slave clears the SSPIF.

4. Slave can look at the ACKTIM bit of the

SSPCON3 register to determine if the SSPIF

was after or before the ACK.

This section describes a standard sequence of events

for the MSSP module configured as an I²C Slave in

7-bit Addressing mode. All decisions made by hard-

ware or software and their effect on reception.

Figure 22-14 and Figure 22-15 is used as a visual

reference for this description.

5. Slave reads the address value from SSPBUF,

clearing the BF flag.

6. Slave sets ACK value clocked out to the master

by setting ACKDT.

This is a step by step process of what typically must

be done to accomplish I²C communication.

7. Slave releases the clock by setting CKP.

8. SSPIF is set after an ACK, not after a NACK.

1. Start bit detected.

9. If SEN = 1 the slave hardware will stretch the

2. S bit of SSPSTAT is set; SSPIF is set if interrupt

on Start detect is enabled.

clock after the ACK.

10. Slave clears SSPIF.

3. Matching address with R/W bit clear is received.

4. The slave pulls SDA low sending an ACK to the

master, and sets SSPIF bit.

Note: SSPIF is still set after the 9th falling edge of

SCL even if there is no clock stretching and

BF has been cleared. Only if NACK is sent

to Master is SSPIF not set

5. Software clears the SSPIF bit.

6. Software reads received address from SSPBUF

clearing the BF flag.

11. SSPIF set and CKP cleared after 8th falling

edge of SCL for a received data byte.

7. If SEN = 1; Slave software sets CKP bit to

release the SCL line.

12. Slave looks at ACKTIM bit of SSPCON3 to

determine the source of the interrupt.

8. The master clocks out a data byte.

13. Slave reads the received data from SSPBUF

clearing BF.

9. Slave drives SDA low sending an ACK to the

master, and sets SSPIF bit.

14. Steps 7-14 are the same for each received data

byte.

10. Software clears SSPIF.

11. Software reads the received byte from SSPBUF

clearing BF.

15. Communication is ended by either the slave

sending an ACK = 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSTSTAT register.

12. Steps 8-12 are repeated for all received bytes

from the master.

13. Master sends Stop condition, setting P bit of

SSPSTAT, and the bus goes idle.

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FIGURE 22-14:

I C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

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FIGURE 22-15:

I C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

DS41639A-page 222

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FIGURE 22-16:

I C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)

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FIGURE 22-17:

I C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)

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22.5.3

SLAVE TRANSMISSION

22.5.3.2

7-bit Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register, and an ACK pulse is

sent by the slave on the ninth bit.

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to

do to accomplish

a

standard transmission.

Figure 22-18 can be used as a reference to this list.

Following the ACK, slave hardware clears the CKP bit

and the SCL pin is held low (see Section 22.5.6

“Clock Stretching” for more detail). By stretching the

clock, the master will be unable to assert another clock

pulse until the slave is done preparing the transmit

data.

1. Master sends a Start condition on SDA and

SCL.

2. S bit of SSPSTAT is set; SSPIF is set if interrupt

on Start detect is enabled.

3. Matching address with R/W bit set is received by

the Slave setting SSPIF bit.

The transmit data must be loaded into the SSPBUF

register which also loads the SSPSR register. Then the

SCL pin should be released by setting the CKP bit of

the SSPCON1 register. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time.

4. Slave hardware generates an ACK and sets

SSPIF.

5. SSPIF bit is cleared by user.

6. Software reads the received address from

SSPBUF, clearing BF.

7. R/W is set so CKP was automatically cleared

after the ACK.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. This ACK

value is copied to the ACKSTAT bit of the SSPCON2

register. If ACKSTAT is set (not ACK), then the data

transfer is complete. In this case, when the not ACK is

latched by the slave, the slave goes idle and waits for

another occurrence of the Start bit. If the SDA line was

low (ACK), the next transmit data must be loaded into

the SSPBUF register. Again, the SCL pin must be

released by setting bit CKP.

8. The slave software loads the transmit data into

SSPBUF.

9. CKP bit is set releasing SCL, allowing the mas-

ter to clock the data out of the slave.

10. SSPIF is set after the ACK response from the

master is loaded into the ACKSTAT register.

11. SSPIF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared by software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

Note 1: If the master ACKs the clock will be

stretched.

2: ACKSTAT is the only bit updated on the

rising edge of SCL (9th) rather than the

falling.

22.5.3.1

Slave Mode Bus Collision

13. Steps 9-13 are repeated for each transmitted

byte.

A slave receives a read request and begins shifting

data out on the SDA line. If a bus collision is detected

and the SBCDE bit of the SSPCON3 register is set, the

BCLIF bit of the PIR register is set. Once a bus collision

is detected, the slave goes idle and waits to be

addressed again. User software can use the BCLIF bit

to handle a slave bus collision.

14. If the master sends a not ACK; the clock is not

held, but SSPIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

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FIGURE 22-18:

I C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

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22.5.3.3

7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPCON3 register

enables additional clock stretching and interrupt gen-

eration after the 8th falling edge of a received match-

ing address. Once a matching address has been

clocked in, CKP is cleared and the SSPIF interrupt is

set.

Figure 22-19 displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

1. Bus starts Idle.

2. Master sends Start condition; the S bit of

SSPSTAT is set; SSPIF is set if interrupt on Start

detect is enabled.

3. Master sends matching address with R/W bit

set. After the 8th falling edge of the SCL line the

CKP bit is cleared and SSPIF interrupt is gener-

ated.

4. Slave software clears SSPIF.

5. Slave software reads ACKTIM bit of SSPCON3

register, and R/W and D/A of the SSPSTAT reg-

ister to determine the source of the interrupt.

6. Slave reads the address value from the

SSPBUF register clearing the BF bit.

7. Slave software decides from this information if it

wishes to ACK or not ACK and sets ACKDT bit

of the SSPCON2 register accordingly.

8. Slave sets the CKP bit releasing SCL.

9. Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit

and sets SSPIF after the ACK if the R/W bit is

set.

11. Slave software clears SSPIF.

12. Slave loads value to transmit to the master into

SSPBUF setting the BF bit.

Note: SSPBUF cannot be loaded until after the

ACK.

13. Slave sets CKP bit releasing the clock.

14. Master clocks out the data from the slave and

sends an ACK value on the 9th SCL pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPCON2 register.

16. Steps 10-15 are repeated for each byte transmit-

ted to the master from the slave.

17. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: Master must send a not ACK on the last byte

to ensure that the slave releases the SCL

line to receive a Stop.

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FIGURE 22-19:

I C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

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22.5.4 SLAVE MODE 10-BIT ADDRESS

RECEPTION

22.5.5 10-BIT ADDRESSING WITH ADDRESS OR

DATA HOLD

This section describes a standard sequence of events

for the MSSP module configured as an I²C slave in

10-bit Addressing mode.

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only

difference is the need to update the SSPADD register

using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCL line is held low are the

same. Figure 22-21 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 22-20 is used as a visual reference for this

description.

This is a step by step process of what must be done by

slave software to accomplish I²C communication.

Figure 22-22 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

1. Bus starts Idle.

2. Master sends Start condition; S bit of SSPSTAT

is set; SSPIF is set if interrupt on Start detect is

enabled.

3. Master sends matching high address with R/W

bit clear; UA bit of the SSPSTAT register is set.

4. Slave sends ACK and SSPIF is set.

5. Software clears the SSPIF bit.

6. Software reads received address from SSPBUF

clearing the BF flag.

7. Slave loads low address into SSPADD,

releasing SCL.

8. Master sends matching low address byte to the

slave; UA bit is set.

Note: Updates to the SSPADD register are not

allowed until after the ACK sequence.

9. Slave sends ACK and SSPIF is set.

Note: If the low address does not match, SSPIF

and UA are still set so that the slave soft-

ware can set SSPADD back to the high

address. BF is not set because there is no

match. CKP is unaffected.

10. Slave clears SSPIF.

11. Slave reads the received matching address

from SSPBUF clearing BF.

12. Slave loads high address into SSPADD.

13. Master clocks a data byte to the slave and

clocks out the slaves ACK on the 9th SCL pulse;

SSPIF is set.

14. If SEN bit of SSPCON2 is set, CKP is cleared by

hardware and the clock is stretched.

15. Slave clears SSPIF.

16. Slave reads the received byte from SSPBUF

clearing BF.

17. If SEN is set the slave sets CKP to release the

SCL.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

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FIGURE 22-20:

I C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

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FIGURE 22-21:

I C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)

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FIGURE 22-22:

I C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

DS41639A-page 232

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22.5.6 CLOCK STRETCHING

22.5.6.2 10-bit Addressing Mode

Clock stretching occurs when a device on the bus

holds the SCL line low effectively pausing communica-

tion. The slave may stretch the clock to allow more

time to handle data or prepare a response for the mas-

ter device. A master device is not concerned with

stretching as anytime it is active on the bus and not

transferring data it is stretching. Any stretching done

by a slave is invisible to the master software and han-

dled by the hardware that generates SCL.

In 10-bit Addressing mode, when the UA bit is set the

clock is always stretched. This is the only time, the

SCL is stretched without CKP being cleared. SCL is

released immediately after a write to SSPADD.

Note: Previous versions of the module did not

stretch the clock if the second address byte

did not match.

22.5.6.3 Byte NACKing

The CKP bit of the SSPCON1 register is used to con-

trol stretching in software. Any time the CKP bit is

cleared, the module will wait for the SCL line to go low

and then hold it. Setting CKP will release SCL and

allow more communication.

When AHEN bit of SSPCON3 is set; CKP is cleared by

hardware after the 8th falling edge of SCL for a

received matching address byte. When DHEN bit of

SSPCON3 is set; CKP is cleared after the 8th falling

edge of SCL for received data.

22.5.6.1 Normal Clock Stretching

Stretching after the 8th falling edge of SCL allows the

slave to look at the received address or data and

decide if it wants to ACK the received data.

Following an ACK if the R/W bit of SSPSTAT is set, a

read request, the slave hardware will clear CKP. This

allows the slave time to update SSPBUF with data to

transfer to the master. If the SEN bit of SSPCON2 is

set, the slave hardware will always stretch the clock

after the ACK sequence. Once the slave is ready; CKP

is set by software and communication resumes.

22.5.7 CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait

for the SCL line to go low and then hold it. However,

clearing the CKP bit will not assert the SCL output low

until the SCL output is already sampled low. There-

fore, the CKP bit will not assert the SCL line until an

external I²C master device has already asserted the

SCL line. The SCL output will remain low until the CKP

bit is set and all other devices on the I²C bus have

released SCL. This ensures that a write to the CKP bit

will not violate the minimum high time requirement for

SCL (see Figure 22-23).

Note 1: The BF bit has no effect on if the clock will

be stretched or not. This is different than

previous versions of the module that

would not stretch the clock, clear CKP, if

SSPBUF was read before the 9th falling

edge of SCL.

2: Previous versions of the module did not

stretch the clock for a transmission if SSP-

BUF was loaded before the 9th falling

edge of SCL. It is now always cleared for

read requests.

FIGURE 22-23:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX ‚ – 1

Master device

asserts clock

CKP

Master device

releases clock

WR

SSPCON1

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Preliminary

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22.5.8 GENERAL CALL ADDRESS SUPPORT

In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave

will prepare to receive the second byte as data, just as

it would in 7-bit mode.

The addressing procedure for the I²C bus is such that

the first byte after the Start condition usually deter-

mines which device will be the slave addressed by the

master device. The exception is the general call

address which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

If the AHEN bit of the SSPCON3 register is set, just as

with any other address reception, the slave hardware

will stretch the clock after the 8th falling edge of SCL.

The slave must then set its ACKDT value and release

the clock with communication progressing as it would

normally.

The general call address is a reserved address in the

I²C protocol, defined as address 0x00. When the

GCEN bit of the SSPCON2 register is set, the slave

module will automatically ACK the reception of this

address regardless of the value stored in SSPADD.

After the slave clocks in an address of all zeros with

the R/W bit clear, an interrupt is generated and slave

software can read SSPBUF and respond.

Figure 22-24 shows

sequence.

a

general call reception

FIGURE 22-24:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data

D5 D4 D3 D2 D1

ACK

9

R/W = 0

General Call Address

ACK

SDA

D7 D6

D0

8

SCL

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

S

SSPIF

BF (SSPSTAT<0>)

Cleared by software

SSPBUF is read

GCEN (SSPCON2<7>)

’1’

22.5.9 SSP MASK REGISTER

An SSP Mask (SSPMSK) register (Register 22-5) is

available in I²C Slave mode as a mask for the value

held in the SSPSR register during an address

comparison operation. A zero (‘0’) bit in the SSPMSK

register has the effect of making the corresponding bit

of the received address a “don’t care”.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP operation until written with a mask value.

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

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22.6.1 I²C MASTER MODE OPERATION

2

22.6 I C MASTER MODE

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

Master mode is enabled by setting and clearing the

appropriate SSPM bits in the SSPCON1 register and

by setting the SSPEN bit. In Master mode, the SDA and

SCK pins must be configured as inputs. The MSSP

peripheral hardware will override the output driver TRIS

controls when necessary to drive the pins low.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted eight bits at a time. After each byte is trans-

mitted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions. The Stop (P) and Start (S) bits are cleared from

a Reset or when the MSSP module is disabled. Control

of the I²C bus may be taken when the P bit is set, or the

bus is Idle.

In Firmware Controlled Master mode, user code

conducts all I²C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDA and SCL lines.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received eight bits at a time.

After each byte is received, an Acknowledge bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

A Baud Rate Generator is used to set the clock

frequency output on SCL. See Section 22.7 “Baud

Rate Generator” for more detail.

Note 1: The MSSP module, when configured in

I²C Master mode, does not allow queue-

ing of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission before the Start con-

dition is complete. In this case, the SSP-

BUF will not be written to and the WCOL

bit will be set, indicating that a write to the

SSPBUF did not occur

2: When in Master mode, Start/Stop detec-

tion is masked and an interrupt is gener-

ated when the SEN/PEN bit is cleared and

the generation is complete.

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Preliminary

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22.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the Baud Rate Gen-

erator (BRG) is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is sam-

pled high, the Baud Rate Generator is reloaded with

the contents of SSPADD<7:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count in the event that the clock

is held low by an external device (Figure 22-25).

FIGURE 22-25:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX ‚ – 1

SCL allowed to transition high

SCL deasserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count

BRG

Reload

22.6.3 WCOL STATUS FLAG

If the user writes the SSPBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL is set and the contents of the buffer are

unchanged (the write does not occur). Any time the

WCOL bit is set it indicates that an action on SSPBUF

was attempted while the module was not idle.

Note:

Because queueing of events is not

allowed, writing to the lower five bits of

SSPCON2 is disabled until the Start

condition is complete.

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22.6.4 I C MASTER MODE START

ister will be automatically cleared by hardware; the

Baud Rate Generator is suspended, leaving the SDA

line held low and the Start condition is complete.

CONDITION TIMING

To initiate a Start condition (Figure 22-26), the user

sets the Start Enable bit, SEN bit of the SSPCON2

register. If the SDA and SCL pins are sampled high,

the Baud Rate Generator is reloaded with the contents

of SSPADD<7:0> and starts its count. If SCL and SDA

are both sampled high when the Baud Rate Generator

times out (TBRG), the SDA pin is driven low. The action

of the SDA being driven low while SCL is high is the

Start condition and causes the S bit of the SSPSTAT1

register to be set. Following this, the Baud Rate Gen-

erator is reloaded with the contents of SSPADD<7:0>

and resumes its count. When the Baud Rate Genera-

tor times out (TBRG), the SEN bit of the SSPCON2 reg-

Note 1: If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition,

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLIF, is set, the Start condition is

aborted and the I²C module is reset into

its Idle state.

2: The Philips I²C™ Specification states that

a bus collision cannot occur on a Start.

FIGURE 22-26:

FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here

At completion of Start bit,

hardware clears SEN bit

and sets SSPIF bit

SDA = 1,

SCL = 1

TBRG

Write to SSPBUF occurs here

2nd bit

SDA

1st bit

TBRG

SCL

S

TBRG

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22.6.5 I C MASTER MODE REPEATED

SSPCON2 register will be automatically cleared and

the Baud Rate Generator will not be reloaded, leaving

the SDA pin held low. As soon as a Start condition is

detected on the SDA and SCL pins, the S bit of the

SSPSTAT register will be set. The SSPIF bit will not be

set until the Baud Rate Generator has timed out.

START CONDITION TIMING

A Repeated Start condition (Figure 22-27) occurs when

the RSEN bit of the SSPCON2 register is programmed

high and the Master state machine is no longer active.

When the RSEN bit is set, the SCL pin is asserted low.

When the SCL pin is sampled low, the Baud Rate Gen-

erator is loaded and begins counting. The SDA pin is

released (brought high) for one Baud Rate Generator

count (TBRG). When the Baud Rate Generator times

out, if SDA is sampled high, the SCL pin will be deas-

serted (brought high). When SCL is sampled high, the

Baud Rate Generator is reloaded and begins counting.

SDA and SCL must be sampled high for one TBRG.

This action is then followed by assertion of the SDA pin

(SDA = 0) for one TBRG while SCL is high. SCL is

asserted low. Following this, the RSEN bit of the

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

•

SDA is sampled low when SCL

goes from low-to-high.

•

SCL goes low before SDA is

asserted low. This may indicate

that another master is attempting to

transmit a data ‘1’.

FIGURE 22-27:

REPEAT START CONDITION WAVEFORM

S bit set by hardware

Write to SSPCON2

occurs here

SDA = 1,

At completion of Start bit,

hardware clears RSEN bit

and sets SSPIF

SDA = 1,

SCL = 1

SCL (no change)

TBRG

1st bit

SDA

SCL

Write to SSPBUF occurs here

TBRG

Sr

Repeated Start

TBRG

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22.6.6 I²C MASTER MODE TRANSMISSION

22.6.6.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSPCON2

register is cleared when the slave has sent an Acknowl-

edge (ACK = 0) and is set when the slave does not

Acknowledge (ACK = 1). A slave sends an Acknowl-

edge when it has recognized its address (including a

general call), or when the slave has properly received

its data.

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the Buffer Full flag bit, BF and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDA pin after the falling edge of SCL is

asserted. SCL is held low for one Baud Rate Generator

rollover count (TBRG). Data should be valid before SCL

is released high. When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin

must remain stable for that duration and some hold

time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDA.

This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received prop-

erly. The status of ACK is written into the ACKSTAT bit

on the rising edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSPIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 22-28).

22.6.6.4 Typical transmit sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSPCON2 register.

2. SSPIF is set by hardware on completion of the

Start.

3. SSPIF is cleared by software.

4. The MSSP module will wait the required start

time before any other operation takes place.

5. The user loads the SSPBUF with the slave

address to transmit.

6. Address is shifted out the SDA pin until all eight

bits are transmitted. Transmission begins as

soon as SSPBUF is written to.

7. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

8. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

release the SDA pin, allowing the slave to respond with

an Acknowledge. On the falling edge of the ninth clock,

the master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT Status bit of the SSPCON2

register. Following the falling edge of the ninth clock

transmission of the address, the SSPIF is set, the BF

flag is cleared and the Baud Rate Generator is turned

off until another write to the SSPBUF takes place, hold-

ing SCL low and allowing SDA to float.

9. The user loads the SSPBUF with eight bits of

data.

10. Data is shifted out the SDA pin until all eight bits

are transmitted.

11. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the

SSPCON2 register. Interrupt is generated once

the Stop/Restart condition is complete.

22.6.6.1

BF Status Flag

In Transmit mode, the BF bit of the SSPSTAT register

is set when the CPU writes to SSPBUF and is cleared

when all eight bits are shifted out.

22.6.6.2

WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the buf-

fer are unchanged (the write does not occur).

WCOL must be cleared by software before the next

transmission.

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FIGURE 22-28:

I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

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2

22.6.7.4 Typical Receive Sequence:

22.6.7

I C MASTER MODE RECEPTION

Master mode reception (Figure 22-29) is enabled by

programming the Receive Enable bit, RCEN bit of the

SSPCON2 register.

1. The user generates a Start condition by setting

the SEN bit of the SSPCON2 register.

2. SSPIF is set by hardware on completion of the

Start.

Note:

The MSSP module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

3. SSPIF is cleared by software.

4. User writes SSPBUF with the slave address to

transmit and the R/W bit set.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPSR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the con-

tents of the SSPSR are loaded into the SSPBUF, the

BF flag bit is set, the SSPIF flag bit is set and the Baud

Rate Generator is suspended from counting, holding

SCL low. The MSSP is now in Idle state awaiting the

next command. When the buffer is read by the CPU,

the BF flag bit is automatically cleared. The user can

then send an Acknowledge bit at the end of reception

by setting the Acknowledge Sequence Enable, ACKEN

bit of the SSPCON2 register.

5. Address is shifted out the SDA pin until all eight

bits are transmitted. Transmission begins as

soon as SSPBUF is written to.

6. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

7. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

8. User sets the RCEN bit of the SSPCON2 register

and the master clocks in a byte from the slave.

9. After the 8th falling edge of SCL, SSPIF and BF

are set.

10. Master clears SSPIF and reads the received

byte from SSPUF, clears BF.

22.6.7.1

BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

11. Master sets ACK value sent to slave in ACKDT

bit of the SSPCON2 register and initiates the

ACK by setting the ACKEN bit.

22.6.7.2

SSPOV Status Flag

12. Masters ACK is clocked out to the slave and

SSPIF is set.

In receive operation, the SSPOV bit is set when eight

bits are received into the SSPSR and the BF flag bit is

already set from a previous reception.

13. User clears SSPIF.

14. Steps 8-13 are repeated for each received byte

from the slave.

22.6.7.3

WCOL Status Flag

15. Master sends a not ACK or Stop to end

communication.

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write does not occur).

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FIGURE 22-29:

I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

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22.6.8

ACKNOWLEDGE SEQUENCE

TIMING

22.6.9

STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN bit of the SSPCON2 register. At the end of a

receive/transmit, the SCL line is held low after the

falling edge of the ninth clock. When the PEN bit is set,

the master will assert the SDA line low. When the SDA

line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCL pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDA pin will be deasserted. When the SDA

pin is sampled high while SCL is high, the P bit of the

SSPSTAT register is set. A TBRG later, the PEN bit is

cleared and the SSPIF bit is set (Figure 22-31).

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the

SSPCON2 register. When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for TBRG. The SCL pin is then

pulled low. Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP module then goes into Idle mode (Figure 22-30).

22.6.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write does

not occur).

22.6.8.1

WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write does

not occur).

FIGURE 22-30:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

write to SSPCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDA

SCL

D0

8

9

SSPIF

Cleared in

SSPIF set at

the end of receive

software

Cleared in

software

SSPIF set at the end

of Acknowledge sequence

Note: TBRG = one Baud Rate Generator period.

FIGURE 22-31:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1for TBRG, followed by SDA = 1for TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

Write to SSPCON2,

set PEN

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

Falling edge of

9th clock

TBRG

SCL

SDA

ACK

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

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22.6.10 SLEEP OPERATION

22.6.13 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

While in Sleep mode, the I²C slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCLIF and reset the

I²C port to its Idle state (Figure 22-32).

22.6.11 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

22.6.12 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I²C bus may

be taken when the P bit of the SSPSTAT register is set,

or the bus is Idle, with both the S and P bits clear. When

the bus is busy, enabling the SSP interrupt will gener-

ate the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSPBUF can be written to. When the user services the

bus collision Interrupt Service Routine and if the I²C

bus is free, the user can resume communication by

asserting a Start condition.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCLIF bit.

If a Start, Repeated Start, Stop or Acknowledge condi-

tion was in progress when the bus collision occurred, the

condition is aborted, the SDA and SCL lines are deas-

serted and the respective control bits in the SSPCON2

register are cleared. When the user services the bus col-

lision Interrupt Service Routine and if the I²C bus is free,

the user can resume communication by asserting a Start

condition.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be set.

• A Repeated Start Condition

• An Acknowledge Condition

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I²C bus

can be taken when the P bit is set in the SSPSTAT

register, or the bus is Idle and the S and P bits are

cleared.

FIGURE 22-32:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data does not match what is driven

by the master.

Data changes

while SCL = 0

SDA line pulled low

by another source

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCLIF)

BCLIF

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PIC16(L)F1454/5/9

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 22-35). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to zero; if the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

22.6.13.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 22-33).

b) SCL is sampled low before SDA is asserted low

(Figure 22-34).

During a Start condition, both the SDA and the SCL

pins are monitored.

Note:

The reason that bus collision is not a fac-

tor during a Start condition is that no two

bus masters can assert a Start condition

at the exact same time. Therefore, one

master will always assert SDA before the

other. This condition does not cause a bus

collision because the two masters must be

allowed to arbitrate the first address fol-

lowing the Start condition. If the address is

the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted,

• the BCLIF flag is set and

•

the MSSP module is reset to its Idle state

(Figure 22-33).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded and counts down. If the

SCL pin is sampled low while SDA is high, a bus colli-

sion occurs because it is assumed that another master

is attempting to drive a data ‘1’ during the Start

condition.

FIGURE 22-33:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,

S bit and SSPIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.

SSP module reset into Idle state.

SDA sampled low before

Start condition. Set BCLIF.

S bit and SSPIF set because

SDA = 0, SCL = 1.

BCLIF

SSPIF and BCLIF are

cleared by software

S

SSPIF

SSPIF and BCLIF are

cleared by software

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Preliminary

DS41639A-page 245

PIC16(L)F1454/5/9

FIGURE 22-34:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG

SDA

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

SCL

SEN

SCL = 0before SDA = 0,

bus collision occurs. Set BCLIF.

SCL = 0before BRG time-out,

bus collision occurs. Set BCLIF.

BCLIF

Interrupt cleared

by software

S

’0’

SSPIF

FIGURE 22-35:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

time-out

SEN

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

’0’

BCLIF

S

SSPIF

Interrupts cleared

by software

SDA = 0, SCL = 1,

set SSPIF

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PIC16(L)F1454/5/9

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 22-36).

If SDA is sampled high, the BRG is reloaded and begins

counting. If SDA goes from high-to-low before the BRG

times out, no bus collision occurs because no two

masters can assert SDA at exactly the same time.

22.6.13.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level (Case 1).

If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition,

see Figure 22-37.

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’ (Case 2).

When the user releases SDA and the pin is allowed to

float high, the BRG is loaded with SSPADD and counts

down to zero. The SCL pin is then deasserted and

when sampled high, the SDA pin is sampled.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

FIGURE 22-36:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared by software

’0’

S

’0’

SSPIF

FIGURE 22-37:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

BCLIF

RSEN

set BCLIF. Release SDA and SCL.

Interrupt cleared

by software

’0’

S

SSPIF

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Preliminary

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PIC16(L)F1454/5/9

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPADD and

counts down to zero. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 22-34). If the SCL pin is sampled

low before SDA is allowed to float high, a bus collision

occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 22-34).

22.6.13.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out (Case 1).

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high (Case 2).

FIGURE 22-38:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

low after TBRG,

set BCLIF

TBRG

SDA

SDA asserted low

SCL

PEN

BCLIF

P

’0’

SSPIF

FIGURE 22-39:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high,

set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

’0’

SSPIF

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2

TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH I C™ OPERATION

Reset

Valueson

Page:

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

TMR1GIE

OSFIE

TMR1GIF

OSFIF

—

PEIE

ADIE⁽²⁾

C2IE

TMR0IE

RCIE

INTE

TXIE

—

IOCIE

SSP1IE

BCL1IE

SSP1IF

BCL1IF

TMR0IF

—

INTF

TMR2IE

ACTIE

TMR2IF

ACTIF

IOCIF

TMR1IE

—

96

97

C1IE

PIE2

USBIE

—

98

PIR1

ADIF⁽²⁾

C2IF

RCIF

C1IF

TXIF

—

TMR1IF

99

USBIF

PIR2

—

100

132

256

207*

253

254

255

256

251

(1)

—

TRISA

TRISA5

TRISA4

—

SSP1ADD

SSP1BUF

SSP1CON1

SSP1CON2

SSP1CON3

SSP1MSK

SSP1STAT

ADD<7:0>

MSSP Receive Buffer/Transmit Register

WCOL

GCEN

SSPOV

ACKSTAT

PCIE

SSPEN

ACKDT

SCIE

CKP

ACKEN

BOEN

SSPM<3:0>

RCEN

PEN

RSEN

AHEN

SEN

ACKTIM

SDAHT

SBCDE

DHEN

MSK<7:0>

SMP

CKE

D/A

P

S

R/W

UA

BF

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I²C™ mode.

*

Page provides register information.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1455/9 only.

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Preliminary

DS41639A-page 249

PIC16(L)F1454/5/9

clock line. The logic dictating when the reload signal is

asserted depends on the mode the MSSP is being

operated in.

22.7 BAUD RATE GENERATOR

The MSSP module has a Baud Rate Generator avail-

able for clock generation in both I²C and SPI Master

modes. The Baud Rate Generator (BRG) reload value

is placed in the SSPADD register (Register 22-6).

When a write occurs to SSPBUF, the Baud Rate Gen-

erator will automatically begin counting down.

Table 22-4 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

EQUATION 22-1:

Once the given operation is complete, the internal clock

will automatically stop counting and the clock pin will

remain in its last state.

FOSC

FCLOCK = -------------------------------------------------

SSPxADD + 14

An internal signal “Reload” in Figure 22-40 triggers the

value from SSPADD to be loaded into the BRG counter.

This occurs twice for each oscillation of the module

FIGURE 22-40:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0>

SSPADD<7:0>

SSPM<3:0>

SCL

Reload

Control

Reload

BRG Down Counter

SSPCLK

FOSC/2

Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPADD when used as a Baud Rate

Generator for I²C. This is an implementation

limitation.

TABLE 22-4: MSSP CLOCK RATE W/BRG

FCLOCK

(2 Rollovers of BRG)

FOSC

FCY

BRG Value

16 MHz

4 MHz

1 MHz

09h

0Ch

27h

09h

400 kHz⁽¹⁾

308 kHz

100 kHz

Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

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22.8 Register Definitions: MSSP Control

REGISTER 22-1: SSPSTAT: SSP STATUS REGISTER

R/W-0/0

SMP

R/W-0/0

CKE

R-0/0

D/A

R-0/0

P

R-0/0

S

R-0/0

R/W

R-0/0

UA

R-0/0

BF

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

SMP: SPI Data Input Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

In I²C Master or Slave mode:

1 = Slew rate control disabled for Standard-Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6

CKE: SPI Clock Edge Select bit (SPI mode only)

In SPI Master or Slave mode:

1= Transmit occurs on transition from active to Idle clock state

0= Transmit occurs on transition from Idle to active clock state

In I²C™ mode only:

1= Enable input logic so that thresholds are compliant with SMbus specification

0= Disable SMbus specific inputs

bit 5

bit 4

D/A: Data/Address bit (I²C mode only)

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

P: Stop bit

(I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

bit 3

bit 2

S: Start bit

(I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

R/W: Read/Write bit information (I²C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match

to the next Start bit, Stop bit, or not ACK bit.

In I²C Slave mode:

1= Read

0= Write

In I²C Master mode:

1= Transmit is in progress

0= Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.

bit 1

UA: Update Address bit (10-bit I²C mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

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Preliminary

DS41639A-page 251

PIC16(L)F1454/5/9

REGISTER 22-1: SSPSTAT: SSP STATUS REGISTER (CONTINUED)

bit 0

BF: Buffer Full Status bit

Receive (SPI and I²C modes):

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Transmit (I²C mode only):

1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full

0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

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PIC16(L)F1454/5/9

REGISTER 22-2: SSPCON1: SSP CONTROL REGISTER 1

R/C/HS-0/0

WCOL

R/C/HS-0/0

SSPOV

R/W-0/0

SSPEN

R/W-0/0

CKP

R/W-0/0

SSPM<3:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Bit is set by hardware C = User cleared

bit 7

WCOL: Write Collision Detect bit

Master mode:

1= A write to the SSPBUF register was attempted while the I²C conditions were not valid for a transmission to be started

0= No collision

Slave mode:

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)

0= No collision

bit 6

SSPOV: Receive Overflow Indicator bit⁽¹⁾

In SPI mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.

Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid

setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the

SSPBUF register (must be cleared in software).

0= No overflow

In I²C mode:

1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode

(must be cleared in software).

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output

In SPI mode:

1= Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins⁽²⁾

0= Disables serial port and configures these pins as I/O port pins

In I²C mode:

1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins⁽³⁾

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

1= Idle state for clock is a high level

0= Idle state for clock is a low level

In I²C Slave mode:

SCL release control

1= Enable clock

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

In I²C Master mode:

Unused in this mode

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000= SPI Master mode, clock = FOSC/4

0001= SPI Master mode, clock = FOSC/16

0010= SPI Master mode, clock = FOSC/64

0011= SPI Master mode, clock = TMR2 output/2

0100= SPI Slave mode, clock = SCK pin, SS pin control enabled

0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0110= I²C Slave mode, 7-bit address

0111= I²C Slave mode, 10-bit address

1000= I²C Master mode, clock = FOSC / (4 * (SSPADD+1))⁽⁴⁾

1001= Reserved

1010= SPI Master mode, clock = FOSC/(4 * (SSPADD+1))⁽⁵⁾

1011= I²C firmware controlled Master mode (Slave idle)

1100= Reserved

1101= Reserved

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1:

In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.

When enabled, these pins must be properly configured as input or output.

When enabled, the SDA and SCL pins must be configured as inputs.

2:

3:

4:

5:

SSPADD values of 0, 1 or 2 are not supported for I²C mode.

SSPADD value of ‘0’ is not supported. Use SSPM = 0000instead.

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Preliminary

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PIC16(L)F1454/5/9

REGISTER 22-3: SSPCON2: SSP CONTROL REGISTER 2

R/W-0/0

GCEN

R-0/0

R/W-0/0

ACKDT

R/S/HS-0/0 R/S/HS-0/0

ACKEN RCEN

R/S/HS-0/0

PEN

R/S/HS-0/0 R/W/HS-0/0

RSEN SEN

bit 0

ACKSTAT

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Cleared by hardware S = User set

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (in I²C Slave mode only)

1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (in I²C mode only)

1= Acknowledge was not received

0= Acknowledge was received

ACKDT: Acknowledge Data bit (in I²C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1= Not Acknowledge

0= Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (in I²C Master mode only)

In Master Receive mode:

1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence idle

bit 3

bit 2

RCEN: Receive Enable bit (in I²C Master mode only)

1= Enables Receive mode for I²C

0= Receive idle

PEN: Stop Condition Enable bit (in I²C Master mode only)

SCKMSSP Release Control:

1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0= Stop condition Idle

bit 1

bit 0

RSEN: Repeated Start Condition Enable bit (in I²C Master mode only)

1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Repeated Start condition Idle

SEN: Start Condition Enable/Stretch Enable bit

In Master mode:

1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Start condition Idle

In Slave mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0= Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the Idle mode, this bit may not be

set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

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PIC16(L)F1454/5/9

REGISTER 22-4: SSPCON3: SSP CONTROL REGISTER 3

R-0/0

R/W-0/0

PCIE

R/W-0/0

SCIE

R/W-0/0

BOEN

R/W-0/0

SDAHT

R/W-0/0

SBCDE

R/W-0/0

AHEN

R/W-0/0

DHEN

ACKTIM

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

ACKTIM: Acknowledge Time Status bit (I²C mode only)⁽³⁾

1= Indicates the I²C bus is in an Acknowledge sequence, set on 8^THfalling edge of SCL clock

0= Not an Acknowledge sequence, cleared on 9^THrising edge of SCL clock

PCIE: Stop Condition Interrupt Enable bit (I²C mode only)

1= Enable interrupt on detection of Stop condition

0= Stop detection interrupts are disabled⁽²⁾

SCIE: Start Condition Interrupt Enable bit (I²C mode only)

1= Enable interrupt on detection of Start or Restart conditions

0= Start detection interrupts are disabled⁽²⁾

BOEN: Buffer Overwrite Enable bit

In SPI Slave mode:⁽¹⁾

1= SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit

0= If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the

SSPCON1 register is set, and the buffer is not updated

In I²C Master mode and SPI Master mode:

This bit is ignored.

In I²C Slave mode:

1= SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state

of the SSPOV bit only if the BF bit = 0.

0= SSPBUF is only updated when SSPOV is clear

bit 3

bit 2

SDAHT: SDA Hold Time Selection bit (I²C mode only)

1= Minimum of 300 ns hold time on SDA after the falling edge of SCL

0= Minimum of 100 ns hold time on SDA after the falling edge of SCL

SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)

If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the

BCL1IF bit of the PIR2 register is set, and bus goes idle

1= Enable slave bus collision interrupts

0= Slave bus collision interrupts are disabled

bit 1

bit 0

AHEN: Address Hold Enable bit (I²C Slave mode only)

1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the

SSPCON1 register will be cleared and the SCL will be held low.

0= Address holding is disabled

DHEN: Data Hold Enable bit (I²C Slave mode only)

1= Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit

of the SSPCON1 register and SCL is held low.

0= Data holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set

when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.

2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 255

PIC16(L)F1454/5/9

REGISTER 22-5: SSPMSK: SSP MASK REGISTER

R/W-1/1

MSK<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-1

bit 0

MSK<7:1>: Mask bits

1= The received address bit n is compared to SSPADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK<0>: Mask bit for I²C Slave mode, 10-bit Address

I²C Slave mode, 10-bit address (SSPM<3:0> = 0111or 1111):

1= The received address bit 0 is compared to SSPADD<0> to detect I²C address match

0= The received address bit 0 is not used to detect I²C address match

I²C Slave mode, 7-bit address, the bit is ignored

2

REGISTER 22-6: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I C MODE)

R/W-0/0

ADD<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

Master mode:

bit 7-0

ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC

10-Bit Slave mode — Most Significant Address Byte:

bit 7-3

Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit pat-

tern sent by master is fixed by I²C specification and must be equal to ‘11110’. However, those bits are

compared by hardware and are not affected by the value in this register.

bit 2-1

bit 0

ADD<2:1>: Two Most Significant bits of 10-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

10-Bit Slave mode — Least Significant Address Byte:

bit 7-0

ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1

bit 0

ADD<7:1>: 7-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

DS41639A-page 256

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

The EUSART module includes the following capabilities:

23.0 ENHANCED UNIVERSAL

SYNCHRONOUS

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in Synchronous

modes

• Sleep operation

system.

Full-Duplex

mode

is

useful

for

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 23-1 and Figure 23-2.

FIGURE 23-1:

EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIE

Interrupt

TXIF

TXREG Register

8

TX/CK pin

MSb

(8)

LSb

0

Pin Buffer

and Control

• • •

Transmit Shift Register (TSR)

TXEN

TRMT

SPEN

Baud Rate Generator

BRG16

FOSC

÷ n

TX9

n

+ 1

Multiplier x4

x16 x64

TX9D

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

SPBRGH

SPBRGL

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 257

PIC16(L)F1454/5/9

FIGURE 23-2:

EUSART RECEIVE BLOCK DIAGRAM

SPEN

CREN

OERR

RCIDL

RX/DT pin

RSR Register

MSb

Stop (8)

LSb

0

START

Pin Buffer

and Control

Data

Recovery

7

1

• • •

Baud Rate Generator

FOSC

RX9

÷ n

BRG16

n

+ 1

Multiplier x4

x16 x64

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

FIFO

SPBRGH

SPBRGL

RX9D

FERR

RCREG Register

8

Data Bus

RCIF

RCIE

Interrupt

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These registers are detailed in Register 23-1,

Register 23-2 and Register 23-3, respectively.

When the receiver or transmitter section is not enabled

then the corresponding RX or TX pin may be used for

general purpose input and output.

DS41639A-page 258

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

23.1.1.2

Transmitting Data

23.1 EUSART Asynchronous Mode

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the Mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is eight bits. Each transmitted bit persists for a

period of 1/(Baud Rate). An on-chip dedicated

8-bit/16-bit Baud Rate Generator is used to derive

standard baud rate frequencies from the system

oscillator. See Table 23-5 for examples of baud rate

configurations.

23.1.1.3

Transmit Data Polarity

The polarity of the transmit data can be controlled with

the SCKP bit of the BAUDCON register. The default

state of this bit is ‘0’ which selects high true transmit idle

and data bits. Setting the SCKP bit to ‘1’ will invert the

transmit data resulting in low true Idle and data bits. The

SCKP bit controls transmit data polarity in

Asynchronous mode only. In Synchronous mode, the

SCKP bit has a different function. See Section 23.5.1.2

“Clock Polarity”.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

23.1.1.4

Transmit Interrupt Flag

23.1.1

EUSART ASYNCHRONOUS

TRANSMITTER

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execution. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

The EUSART transmitter block diagram is shown in

Figure 23-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

23.1.1.1

Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

• TXEN = 1

• SYNC = 0

• SPEN = 1

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

All other EUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART and automatically

configures the TX/CK I/O pin as an output. If the TX/CK

pin is shared with an analog peripheral, the analog I/O

function must be disabled by clearing the corresponding

ANSEL bit.

Note:

The TXIF Transmitter Interrupt flag is set

when the TXEN enable bit is set.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 259

PIC16(L)F1454/5/9

23.1.1.5

TSR Status

23.1.1.7

Asynchronous Transmission Set-up:

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

1. Initialize the SPBRGH, SPBRGL register pair and

the BRGH and BRG16 bits to achieve the desired

baud rate (see Section 23.4 “EUSART Baud

Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9 con-

trol bit. A set ninth data bit will indicate that the

eight Least Significant data bits are an address

when the receiver is set for address detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

4. Set SCKP bit if inverted transmit is desired.

23.1.1.6

Transmitting 9-Bit Characters

5. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set, the

EUSART will shift nine bits out for each character trans-

mitted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the eight Least Significant bits into the TXREG. All nine

bits of data will be transferred to the TSR shift register

immediately after the TXREG is written.

6. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

7. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

8. Load 8-bit data into the TXREG register. This

will start the transmission.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 23.1.2.7 “Address

Detection” for more information on the address mode.

FIGURE 23-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 23-4:

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

1 TCY

Word 1

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 2

Transmit Shift Reg.

Note:

This timing diagram shows two consecutive transmissions.

DS41639A-page 260

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

BAUDCON

INTCON

PIE1

ABDOVF

GIE

TMR1GIE ADIE⁽²⁾

TMR1GIF ADIF⁽²⁾

RCIDL

PEIE

—

SCKP

INTE

TXIE

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

269

96

TMR0IE

RCIE

SSP1IE

SSP1IF

ADDEN

TMR2IE TMR1IE

TMR2IF TMR1IF

97

PIR1

RCIF

TXIF

—

99

RCSTA

SPBRGL

SPBRGH

TRISC

SPEN

RX9

SREN

CREN

FERR

OERR

RX9D

268*

270*

140

259

267

BRG<7:0>

BRG<15:8>

TRISC7⁽¹⁾TRISC6⁽¹⁾TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

TXREG

TXSTA

EUSART Transmit Data Register

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.

Page provides register information.

*

Note 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 261

PIC16(L)F1454/5/9

23.1.2

EUSART ASYNCHRONOUS

RECEIVER

23.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position, then a framing error is set for this

character, otherwise, the framing error is cleared for

this character. See Section 23.1.2.4 “Receive

Framing Error” for more information on framing

errors.

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 23-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all eight

or nine bits of the character have been shifted in, they

are immediately transferred to

a two character

First-In-First-Out (FIFO) memory. The FIFO buffering

allows reception of two complete characters and the

start of a third character before software must start

servicing the EUSART receiver. The FIFO and RSR

registers are not directly accessible by software.

Access to the received data is via the RCREG register.

23.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART. The programmer

must set the corresponding TRIS bit to configure the

RX/DT I/O pin as an input.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 23.1.2.5

“Receive Overrun Error” for more

information on overrun errors.

23.1.2.3

Receive Interrupts

Note:

If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE peripheral interrupt enable bit of the

INTCON register

• GIE Global Interrupt Enable bit of the INTCON

register

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

DS41639A-page 262

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

23.1.2.4

Receive Framing Error

23.1.2.7

Address Detection

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

register.

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit. All other characters will be ignored.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the EUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

23.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTA register.

23.1.2.6

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 263

PIC16(L)F1454/5/9

23.1.2.8

Asynchronous Reception Set-up:

23.1.2.9

9-bit Address Detection Mode Set-up

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 23.4 “EUSART

Baud Rate Generator (BRG)”).

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 23.4 “EUSART

Baud Rate Generator (BRG)”).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

2. Clear the ANSEL bit for the RX pin (if applicable).

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

5. If 9-bit reception is desired, set the RX9 bit.

6. Enable reception by setting the CREN bit.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

5. Enable 9-bit reception by setting the RX9 bit.

6. Enable address detection by setting the ADDEN

bit.

8. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

7. Enable reception by setting the CREN bit.

8. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

9. Get the received eight Least Significant data bits

from the receive buffer by reading the RCREG

register.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

9. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received eight Least Significant data bits

from the receive buffer by reading the RCREG

register. Software determines if this is the

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 23-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg.

Word 2

RCREG

Word 1

RCREG

RCIDL

Read Rcv

Buffer Reg.

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

DS41639A-page 264

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

BAUDCON

INTCON

PIE1

ABDOVF

GIE

TMR1GIE ADIE⁽²⁾

TMR1GIF ADIF⁽²⁾

RCIDL

PEIE

—

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

269

96

TMR0IE

RCIE

SSP1IE

SSP1IF

TMR2IE TMR1IE

TMR2IF TMR1IF

97

PIR1

RCIF

—

99

RCREG

RCSTA

SPBRGL

SPBRGH

TRISC

EUSART Receive Data Register

SREN CREN ADDEN FERR

BRG<7:0>

BRG<15:8>

TRISC7⁽¹⁾TRISC6⁽¹⁾TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

262*

268*

270*

140

267

SPEN

RX9

OERR

RX9D

TXSTA

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.

Page provides register information.

*

Note 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 265

PIC16(L)F1454/5/9

23.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block out-

put (INTOSC). However, the INTOSC frequency may

drift as VDD or temperature changes, and this directly

affects the asynchronous baud rate. Two methods may

be used to adjust the baud rate clock, but both require

a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE

register to adjust the INTOSC output. Adjusting the

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See Section 5.2.2

“Internal Clock Sources” for more information.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 23.4.1

“Auto-Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

DS41639A-page 266

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

23.3 Register Definitions: EUSART Control

REGISTER 23-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-/0

CSRC

R/W-0/0

TX9

R/W-0/0

TXEN⁽¹⁾

R/W-0/0

SYNC

R/W-0/0

SENDB

R/W-0/0

BRGH

R-1/1

R/W-0/0

TX9D

TRMT

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

bit 3

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit⁽¹⁾

1= Transmit enabled

0= Transmit disabled

SYNC: EUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send Sync Break on next transmission (cleared by hardware upon completion)

0= Sync Break transmission completed

Synchronous mode:

Don’t care

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 267

PIC16(L)F1454/5/9

(1)

REGISTER 23-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0/0

SPEN

R/W-0/0

RX9

R/W-0/0

SREN

R/W-0/0

CREN

R/W-0/0

ADDEN

R-0/0

RX9D

FERR

OERR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

DS41639A-page 268

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

REGISTER 23-3: BAUDCON: BAUD RATE CONTROL REGISTER

R-0/0

R-1/1

U-0

—

R/W-0/0

SCKP

R/W-0/0

BRG16

U-0

—

R/W-0/0

WUE

R/W-0/0

ABDEN

ABDOVF

RCIDL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1= Auto-baud timer overflowed

0= Auto-baud timer did not overflow

Synchronous mode:

Don’t care

RCIDL: Receive Idle Flag bit

Asynchronous mode:

1= Receiver is idle

0= Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5

bit 4

Unimplemented: Read as ‘0’

SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:

1= Transmit inverted data to the TX/CK pin

0= Transmit non-inverted data to the TX/CK pin

Synchronous mode:

1= Data is clocked on rising edge of the clock

0= Data is clocked on falling edge of the clock

bit 3

BRG16: 16-bit Baud Rate Generator bit

1= 16-bit Baud Rate Generator is used

0= 8-bit Baud Rate Generator is used

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE

will automatically clear after RCIF is set.

0= Receiver is operating normally

Synchronous mode:

Don’t care

bit 0

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0= Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 269

PIC16(L)F1454/5/9

EXAMPLE 23-1:

CALCULATING BAUD

RATE ERROR

23.4 EUSART Baud Rate Generator

(BRG)

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDCON register selects 16-bit

mode.

FOSC

Desired Baud Rate = -----------------------------------------------------------------------

64[SPBRGH:SPBRGL] + 1

Solving for SPBRGH:SPBRGL:

FOSC

---------------------------------------------

Desired Baud Rate

X = --------------------------------------------- – 1

64

The SPBRGH, SPBRGL register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXSTA

register and the BRG16 bit of the BAUDCON register. In

Synchronous mode, the BRGH bit is ignored.

16000000

-----------------------

9600

= ----------------------- – 1

64

= 25.042 = 25

Table 23-3 contains the formulas for determining the

baud rate. Example 23-1 provides a sample calculation

for determining the baud rate and baud rate error.

16000000

Calculated Baud Rate = --------------------------

6425 + 1

Typical baud rates and error values for various

Asynchronous modes have been computed for your

convenience and are shown in Table 23-3. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

= 9615

Calc. Baud Rate – Desired Baud Rate

Error = --------------------------------------------------------------------------------------------

Desired Baud Rate

9615 – 9600

= ---------------------------------- = 0 . 1 6 %

9600

Writing a new value to the SPBRGH, SPBRGL register

pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow

before outputting the new baud rate.

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is idle before

changing the system clock.

DS41639A-page 270

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 23-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

BRG/EUSART Mode

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend:

x= Don’t care, n = value of SPBRGH, SPBRGL register pair.

TABLE 23-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

RCSTA

ABDOVF RCIDL

—

SCKP

CREN

BRG16

ADDEN

—

WUE

ABDEN

RX9D

269

268

SPEN

CSRC

RX9

SREN

FERR

OERR

SPBRGL

SPBRGH

TXSTA

BRG<7:0>

BRG<15:8>

SYNC SENDB

270*

267

TX9

TXEN

BRGH

TRMT

TX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

Page provides register information.

*

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 271

PIC16(L)F1454/5/9

TABLE 23-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 16.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

—

255

129

32

—

239

119

29

—

207

103

25

—

143

71

17

16

8

1221

2404

9470

10417

19.53k

1.73

0.16

-1.36

0.00

1.73

1200

2400

9600

10286

19.20k

0.00

-1.26

0.00

—

1202

2404

9615

10417

19.23k

0.16

0.00

0.16

—

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

9600

10417

19.2k

57.6k

115.2k

29

27

23

15

14

12

2

—

57.60k

—

7

—

57.60k

—

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

0.00

—

300

1200

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

300

1200

2400

9600

—

191

47

23

5

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

10417

—

0.00

—

2

—

19.20k

0.00

—

0

—

57.60k

—

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 18.432 MHz FOSC = 16.000 MHz

FOSC = 20.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

2400

9600

10417

19.2k

57.6k

—

71

65

35

11

5

9615

10417

19.23k

56.82k

0.16

0.00

0.16

-1.36

129

119

64

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

119

110

59

19

9

9615

10417

19.23k

58.82k

111.1k

0.16

0.00

0.16

2.12

-3.55

103

95

51

16

8

9600

0.00

0.53

0.00

10473

19.20k

57.60k

115.2k

21

115.2k 113.64k -1.36

10

DS41639A-page 272

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 23-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

191

95

23

21

11

3

300

1202

2404

—

0.16

—

207

51

25

—

5

0.16

0.00

0.16

—

1200

0.00

0.53

0.00

2400

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 18.432 MHz FOSC = 16.000 MHz

FOSC = 20.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

2400

9600

10417

19.2k

57.6k

300.0

1200

-0.01

-0.03

0.16

0.00

0.16

-1.36

4166

1041

520

129

119

64

300.0

1200

0.00

-0.37

0.00

3839

959

479

119

110

59

300.03

1200.5

2398

0.01

0.04

-0.08

0.16

0.00

0.16

2.12

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

2303

575

287

71

2399

2400

9615

9600

9615

9600

10417

19.23k

56.818

10378

19.20k

57.60k

115.2k

10417

19.23k

58.82k

10473

19.20k

57.60k

115.2k

65

51

35

21

19

16

11

115.2k 113.636 -1.36

10

9

111.11k -3.55

8

5

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

Error

(decimal)

300

1200

299.9

1199

-0.02

-0.08

0.16

0.00

0.16

-3.55

—

1666

416

207

51

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

300.0

1200

0.00

0.53

0.00

767

191

95

23

21

11

3

300.5

1202

2404

—

0.16

—

207

51

25

—

5

2400

2404

9615

10417

19.23k

55556

—

2400

9600

10417

19.2k

57.6k

115.2k

47

23

10473

19.20k

57.60k

115.2k

10417

—

0.00

—

25

12

—

8

—

1

—

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 273

PIC16(L)F1454/5/9

TABLE 23-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 16.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.01

0.02

-0.03

0.00

0.16

-0.22

0.94

16665

4166

2082

520

479

259

86

300.0

1200

0.00

0.08

0.00

15359

3839

1919

479

441

239

79

300.0

1200.1

2399.5

9592

0.00

0.01

-0.02

-0.08

0.00

0.16

0.64

13332

3332

1666

416

383

207

68

300.0

1200

0.00

0.16

0.00

9215

2303

1151

287

264

143

47

2400

9600

9597

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.47k

116.3k

10425

19.20k

57.60k

115.2k

10417

19.23k

57.97k

10433

19.20k

57.60k

115.2k

42

39

114.29k -0.79

34

23

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.02

0.04

0.16

0

6666

1666

832

207

191

103

34

300.0

1200

0.01

0.04

0.08

0.16

0.00

0.16

2.12

-3.55

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

3071

767

383

95

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

2400

2401

2398

2400

9600

9615

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.14k

117.6k

10417

19.23k

58.82k

111.1k

10473

19.20k

57.60k

115.2k

87

23

0.16

-0.79

2.12

51

47

12

16

15

—

16

8

7

—

DS41639A-page 274

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

and SPBRGL registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the

average bit time when clocked at full speed.

23.4.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

Section 23.4.3 “Auto-Wake-up on

Break”).

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

Setting the ABDEN bit of the BAUDCON register starts

the auto-baud calibration sequence (Figure 23-6).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Table 23-6. The fifth rising edge will occur on the RX pin

at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPBRGH, SPBRGL register pair, the ABDEN

bit is automatically cleared and the RCIF interrupt flag

is set. The value in the RCREG needs to be read to

clear the RCIF interrupt. RCREG content should be

discarded. When calibrating for modes that do not use

the SPBRGH register the user can verify that the

SPBRGL register did not overflow by checking for 00h

in the SPBRGH register.

3: During the auto-baud process, the

auto-baud counter starts counting at one.

Upon completion of the auto-baud

sequence, to achieve maximum accuracy,

subtract one from the SPBRGH:SPBRGL

register pair.

TABLE 23-6:

BRG COUNTER CLOCK RATES

BRG Base

Clock

BRG ABD

Clock

BRG16 BRGH

0

1

FOSC/64

FOSC/16

FOSC/512

FOSC/128

1

0

1

FOSC/16

FOSC/4

FOSC/128

FOSC/32

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 23-6. During ABD,

both the SPBRGH and SPBRGL registers are used as

a 16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

Note:

During the ABD sequence, SPBRGL and

SPBRGH registers are both used as a 16-bit

counter, independent of BRG16 setting.

FIGURE 23-6:

AUTOMATIC BAUD RATE CALIBRATION

XXXXh

0000h

001Ch

BRG Value

Edge #1

bit 1

Edge #2

bit 3

Edge #3

bit 5

Edge #4

bit 7

bit 6

Edge #5

Stop bit

RX pin

Start

bit 0

bit 2

bit 4

BRG Clock

Auto Cleared

Set by User

ABDEN bit

RCIDL

RCIF bit

(Interrupt)

Read

RCREG

XXh

1Ch

00h

SPBRGL

SPBRGH

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 275

PIC16(L)F1454/5/9

23.4.2

AUTO-BAUD OVERFLOW

23.4.3.1

Special Considerations

During the course of automatic baud detection, the

ABDOVF bit of the BAUDCON register will be set if the

baud rate counter overflows before the fifth rising edge

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in the 16 bits of the SPBRGH:SPBRGL register

pair. After the ABDOVF bit has been set, the counter

continues to count until the fifth rising edge is detected

on the RX pin. Upon detecting the fifth RX edge, the

hardware will set the RCIF interrupt flag and clear the

ABDEN bit of the BAUDCON register. The RCIF flag

can be subsequently cleared by reading the RCREG

register. The ABDOVF flag of the BAUDCON register

can be cleared by software directly.

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be ten or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

To terminate the auto-baud process before the RCIF

flag is set, clear the ABDEN bit then clear the ABDOVF

bit of the BAUDCON register. The ABDOVF bit will

remain set if the ABDEN bit is not cleared first.

Oscillator Start-up Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the EUSART.

23.4.3

AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

WUE Bit

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCON register. Once set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a

wake-up event independent of the CPU mode. A

wake-up event consists of a high-to-low transition on the

RX/DT line. (This coincides with the start of a Sync Break

or a wake-up signal character for the LIN protocol.)

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared in software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 23-7), and asynchronously if

the device is in Sleep mode (Figure 23-8). The interrupt

condition is cleared by reading the RCREG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

DS41639A-page 276

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 23-7:

AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4

OSC1

Auto Cleared

Bit set by user

WUE bit

RX/DT Line

RCIF

Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 23-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q4

Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3

Q1

Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4

Auto Cleared

OSC1

Bit Set by User

WUE bit

RX/DT Line

Note 1

RCIF

Cleared due to User Read of RCREG

Sleep Command Executed

Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 277

PIC16(L)F1454/5/9

23.4.4

BREAK CHARACTER SEQUENCE

23.4.5

RECEIVING A BREAK CHARACTER

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘0’ bits and a Stop bit.

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCSTA register and the Received data

as indicated by RCREG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

To send a Break character, set the SENDB and TXEN

bits of the TXSTA register. The Break character trans-

mission is then initiated by a write to the TXREG. The

value of data written to TXREG will be ignored and all

‘0’s will be transmitted.

A Break character has been received when;

• RCIF bit is set

• FERR bit is set

• RCREG = 00h

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

The second method uses the Auto-Wake-up feature

described in Section 23.4.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RCIF interrupt, and receive the next data byte followed

by another interrupt.

The TRMT bit of the TXSTA register indicates when the

transmit operation is active or idle, just as it does during

normal transmission. See Figure 23-9 for the timing of

the Break character sequence.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCON register before placing the EUSART in

Sleep mode.

23.4.4.1

Break and Sync Transmit Sequence

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

FIGURE 23-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

Dummy Write

BRG Output

(Shift Clock)

TX (pin)

Start bit

bit 0

bit 1

Break

bit 11

Stop bit

TXIF bit

(Transmit

Interrupt Flag)

TRMT bit

(Transmit Shift

Empty Flag)

SENDB Sampled Here

Auto Cleared

SENDB

(send Break

control bit)

DS41639A-page 278

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Clearing the SCKP bit sets the Idle state as low. When

the SCKP bit is cleared, the data changes on the rising

edge of each clock.

23.5 EUSART Synchronous Mode

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary cir-

cuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

23.5.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are

automatically enabled when the EUSART is configured

for synchronous master transmit operation.

There are two signal lines in Synchronous mode: a bidi-

rectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The EUSART can operate as either a master or slave

device.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character, the new character data is held in

the TXREG until the last bit of the previous character

has been transmitted. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately trans-

ferred to the TSR. The transmission of the character

commences immediately following the transfer of the

data to the TSR from the TXREG.

Start and Stop bits are not used in synchronous

transmissions.

Each data bit changes on the leading edge of the mas-

ter clock and remains valid until the subsequent leading

clock edge.

23.5.1

SYNCHRONOUS MASTER MODE

Note:

The TSR register is not mapped in data

memory so it is not available to the user.

The following bits are used to configure the EUSART

for synchronous master operation:

• SYNC = 1

23.5.1.4

Synchronous Master Transmission

Set-up:

• CSRC = 1

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 23.4 “EUSART

Baud Rate Generator (BRG)”).

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode;

otherwise, the device will be configured to receive.

Setting the SPEN bit of the RCSTA register enables the

EUSART.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

23.5.1.1

Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin output driver is automatically enabled

when the EUSART is configured for synchronous

transmit or receive operation. Serial data bits change

on the leading edge to ensure they are valid at the trail-

ing edge of each clock. One clock cycle is generated

for each data bit. Only as many clock cycles are

generated as there are data bits.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. Start transmission by loading data to the TXREG

register.

23.5.1.2

Clock Polarity

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP

bit of the BAUDCON register. Setting the SCKP bit sets

the clock Idle state as high. When the SCKP bit is set,

the data changes on the falling edge of each clock.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 279

PIC16(L)F1454/5/9

FIGURE 23-10:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.

FIGURE 23-11:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 23-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

TRANSMISSION

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

—

SCKP

INTE

TXIE

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

269

96

TMR0IE

RCIE

(2)

TMR1GIE

TMR1GIF

SPEN

ADIE

SSP1IE

SSP1IF

ADDEN

TMR2IE

TMR2IF

OERR

TMR1IE

TMR1IF

RX9D

97

(2)

PIR1

ADIF

RCIF

TXIF

—

99

RCSTA

RX9

SREN

CREN

FERR

268

270*

140

259*

267

SPBRGL

SPBRGH

BRG<7:0>

BRG<15:8>

TRISC4 TRISC3

EUSART Transmit Data Register

SYNC SENDB

(1)

TRISC

TXREG

TXSTA

TRISC7

TRISC6

TRISC5

TXEN

TRISC2

BRGH

TRISC1

TRMT

TRISC0

TX9D

CSRC

TX9

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.

*

Page provides register information.

Note 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only.

DS41639A-page 280

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

buffer can be read; however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear, then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set, then the error condition is cleared by either clearing

the CREN bit of the RCSTA register, or by clearing the

SPEN bit which resets the EUSART.

23.5.1.5

Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

EUSART is configured for synchronous master receive

operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

23.5.1.8

Receiving 9-bit Characters

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character,

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set, the EUSART

will shift 9 bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

23.5.1.9

Synchronous Master Reception

Set-up:

Register (RSR). When

a complete character is

1. Initialize the SPBRGH, SPBRGL register pair for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

received into the RSR, the RCIF bit is set and the char-

acter is automatically transferred to the two character

receive FIFO. The Least Significant eight bits of the top

character in the receive FIFO are available in RCREG.

The RCIF bit remains set as long as there are unread

characters in the receive FIFO.

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

Note:

If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

4. Ensure bits CREN and SREN are clear.

5. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

23.5.1.6

Slave Clock

6. If 9-bit reception is desired, set bit RX9.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The

TX/CK pin output driver is automatically disabled when

the device is configured for synchronous slave transmit

or receive operation. Serial data bits change on the

leading edge to ensure they are valid at the trailing edge

of each clock. One data bit is transferred for each clock

cycle. Only as many clock cycles should be received as

there are data bits.

7. Start reception by setting the SREN bit or, for

continuous reception, set the CREN bit.

8. Interrupt flag bit RCIF will be set when reception

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

Note:

If the device is configured as a slave and

the TX/CK function is on an analog pin, the

corresponding ANSEL bit must be

cleared.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

23.5.1.7

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens, the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 281

PIC16(L)F1454/5/9

FIGURE 23-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 23-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON ABDOVF

RCIDL

PEIE

ADIE⁽²⁾

ADIF⁽²⁾

—

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

269

96

INTCON

PIE1

GIE

TMR0IE

RCIE

TMR1GIE

TMR1GIF

SSP1IE

SSP1IF

TMR2IE TMR1IE

TMR2IF TMR1IF

97

PIR1

RCIF

—

99

RCREG

RCSTA

SPBRGL

SPBRGH

TRISC

TXSTA

EUSART Receive Data Register

SREN CREN ADDEN FERR

BRG<7:0>

BRG<15:8>

TRISC7⁽¹⁾TRISC6⁽¹⁾TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

262*

268

270*

140

267

SPEN

RX9

OERR

RX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.

Page provides register information.

*

Note 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only.

DS41639A-page 282

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

23.5.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for synchronous slave operation:

1. The first character will immediately transfer to

the TSR register and transmit.

• SYNC = 1

2. The second word will remain in the TXREG

register.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

3. The TXIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode;

otherwise, the device will be configured to receive.

Setting the SPEN bit of the RCSTA register enables the

EUSART.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

23.5.2.2

Synchronous Slave Transmission

Set-up:

23.5.2.1

EUSART Synchronous Slave

Transmit

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

The operation of the Synchronous Master and Slave

modes are identical (see Section 23.5.1.3

“Synchronous Master Transmission”), except in the

2. Clear the ANSEL bit for the CK pin (if applicable).

3. Clear the CREN and SREN bits.

4. If interrupts are desired, set the TXIE bit of the

PIE1 register, and the GIE and PEIE bits of the

INTCON register.

case of the Sleep mode.

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant 8 bits to the TXREG register.

TABLE 23-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

INTCON

PIE1

ABDOVF

GIE

TMR1GIE ADIE⁽²⁾

TMR1GIF ADIF⁽²⁾

RCIDL

PEIE

—

SCKP

INTE

TXIE

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

269

96

TMR0IE

RCIE

SSP1IE

SSP1IF

ADDEN

TMR2IE TMR1IE

TMR2IF TMR1IF

97

PIR1

RCIF

TXIF

—

99

RX9

TRISC7⁽¹⁾TRISC6⁽¹⁾

SREN

CREN

FERR

OERR

RX9D

RCSTA

TRISC

TXREG

SPEN

268

140

259*

267

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

EUSART Transmit Data Register

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

Page provides register information.

*

Note 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 283

PIC16(L)F1454/5/9

23.5.2.3

EUSART Synchronous Slave

Reception

23.5.2.4

Synchronous Slave Reception

Set-up:

The operation of the Synchronous Master and Slave

modes is identical (Section 23.5.1.5 “Synchronous

Master Reception”), with the following exceptions:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for both the CK and DT pins

(if applicable).

• Sleep

3. If interrupts are desired, set the RCIE bit of the

PIE1 register, and the GIE and PEIE bits of the

INTCON register.

• CREN bit is always set, therefore the receiver is

never idle

• SREN bit, which is a “don’t care” in Slave mode

4. If 9-bit reception is desired, set the RX9 bit.

5. Set the CREN bit to enable reception.

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

6. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

8. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

TABLE 23-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

INTCON

PIE1

ABDOVF

GIE

TMR1GIE ADIE⁽²⁾

TMR1GIF ADIF⁽²⁾

RCIDL

PEIE

—

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

269

96

TMR0IE

RCIE

SSP1IE

SSP1IF

TMR2IE TMR1IE

TMR2IF TMR1IF

97

PIR1

RCIF

—

99

RCREG

RCSTA

TRISC

TXSTA

EUSART Receive Data Register

SREN CREN ADDEN FERR

TRISC7⁽¹⁾TRISC6⁽¹⁾TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

262*

268

140

267

RX9

OERR

RX9D

SPEN

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.

Page provides register information.

*

Note 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only.

DS41639A-page 284

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

23.6.2

SYNCHRONOUS TRANSMIT

DURING SLEEP

23.6 EUSART Operation During Sleep

The EUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the

necessary signals to run the Transmit or Receive Shift

registers during Sleep.

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for synchronous slave transmission

(see Section 23.5.2.2 “Synchronous Slave

Transmission Set-up:”).

Synchronous Slave mode uses an externally generated

clock to run the Transmit and Receive Shift registers.

•

The TXIF interrupt flag must be cleared by writing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

23.6.1

SYNCHRONOUS RECEIVE DURING

SLEEP

• If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON

register.

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Reception (see

Section 23.5.2.4 “Synchronous Slave

Reception Set-up:”).

• Interrupt enable bits TXIE of the PIE1 register and

PEIE of the INTCON register must set.

Upon entering Sleep mode, the device will be ready to

accept clocks on the TX/CK pin and transmit data on

the RX/DT pin. When the data word in the TSR has

been completely clocked out by the external device, the

pending byte in the TXREG will transfer to the TSR and

the TXIF flag will be set, which wakes the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

• If interrupts are desired, set the RCIE bit of the

PIE1 register, and the GIE and PEIE bits of the

INTCON register.

• The RCIF interrupt flag must be cleared by read-

ing RCREG to unload any pending characters in

the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RCIF interrupt

flag bit of the PIR1 register will be set. Thereby, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set, then the Interrupt

Service Routine at address 0004h will be called.

Upon waking from Sleep, the instruction following the

SLEEPinstruction will be executed. If the Global Inter-

rupt Enable (GIE) bit of the INTCON register is also set,

then the Interrupt Service Routine at address 004h will

be called.

23.6.3

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

register, APFCON. To determine which pins can be

moved and what their default locations are upon a

Reset, see Section 12.1 “Alternate Pin Function” for

more information.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 285

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 286

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

For a step-by-step procedure on how to set up this

module for PWM operation, refer to Section 24.1.9

“Setup for PWM Operation using PWMx Pins”.

24.0 PULSE WIDTH MODULATION

(PWM) MODULE

The PWM module generates a Pulse-Width Modulated

signal determined by the duty cycle, period, and

resolution that are configured by the following registers:

FIGURE 24-1:

PWM OUTPUT

Period

• PR2

• T2CON

Pulse Width

TMR2 = PR2

• PWMxDCH

• PWMxDCL

• PWMxCON

TMR2 =

PWMxDCH<7:0>:PWMxDCL<7:6>

TMR2 = 0

Figure 24-1 shows a typical waveform of the PWM

signal. Figure 24-2 shows a simplified block diagram of

PWM operation.

FIGURE 24-2:

SIMPLIFIED PWM BLOCK DIAGRAM

PWMxDCL<7:6>

Duty Cycle registers

PWMxDCH

PWMxOUT

to other peripherals: CWG

Latched

(Not visible to user)

Output Enable (PWMxOE)

TRIS Control

0

1

Q

Comparator

R

S

PWMx

TMR2 Module

(1)

Output Polarity (PWMxPOL)

TMR2

Comparator

PR2

Clear Timer,

PWMx pin and

latch Duty Cycle

Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by

the Timer2 prescaler to create a 10-bit time base.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 287

PIC16(L)F1454/5/9

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

24.1 PWMx Pin Configuration

All PWM outputs are multiplexed with the PORT data

latch. The user must configure the pins as outputs by

clearing the associated TRIS bits.

• TMR2 is cleared

• The PWM output is active. (Exception: When the

PWM duty cycle = 0%, the PWM output will

remain inactive.)

Note:

Clearing the PWMxOE bit will relinquish

control of the PWMx pin.

• The PWMxDCH and PWMxDCL register values

are latched into the buffers.

24.1.1

FUNDAMENTAL OPERATION

The PWM module produces a 10-bit resolution output.

Timer2 and PR2 set the period of the PWM. The

PWMxDCL and PWMxDCH registers configure the

duty cycle. The period is common to all PWM modules,

whereas the duty cycle is independently controlled.

Note:

The Timer2 postscaler has no effect on

the PWM operation.

24.1.4

PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to the PWMxDCH and PWMxDCL register pair.

The PWMxDCH register contains the eight MSbs and

the PWMxDCL<7:6>, the two LSbs. The PWMxDCH

and PWMxDCL registers can be written to at any time.

Note:

The Timer2 postscaler is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

Equation 24-2 is used to calculate the PWM pulse

width. Equation 24-3 is used to calculate the PWM duty

cycle ratio.

All PWM outputs associated with Timer2 are set when

TMR2 is cleared. Each PWMx is cleared when TMR2

is equal to the value specified in the corresponding

PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) reg-

isters. When the value is greater than or equal to PR2,

the PWM output is never cleared (100% duty cycle).

EQUATION 24-2: PULSE WIDTH

Pulse Width = PWMxDCH:PWMxDCL<7:6> 

Note:

The PWMxDCH and PWMxDCL registers

are double buffered. The buffers are

updated when Timer2 matches PR2. Care

should be taken to update both registers

before the timer match occurs.

TOSC

 (TMR2 Prescale Value)

Note: TOSC = 1/FOSC

EQUATION 24-3: DUTY CYCLE RATIO

24.1.2

PWM OUTPUT POLARITY

PWMxDCH:PWMxDCL<7:6>

Duty Cycle Ratio = -----------------------------------------------------------------------------------

4PR2 + 1

The output polarity is inverted by setting the PWMxPOL

bit of the PWMxCON register.

24.1.3

PWM PERIOD

The 8-bit timer TMR2 register is concatenated with the

two Least Significant bits of 1/FOSC, adjusted by the

Timer2 prescaler to create the 10-bit time base. The

system clock is used if the Timer2 prescaler is set to

1:1.

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 24-1.

EQUATION 24-1: PWM PERIOD

PWM Period = PR2 + 1  4  TOSC 

(TMR2 Prescale Value)

Note:

TOSC = 1/FOSC

DS41639A-page 288

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

24.1.5

PWM RESOLUTION

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolu-

tion will result in 1024 discrete duty cycles, whereas an

8-bit resolution will result in 256 discrete duty cycles.

The maximum PWM resolution is 10 bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 24-4.

EQUATION 24-4: PWM RESOLUTION

log4PR2 + 1

Resolution = ----------------------------------------- bits

log2

Note:

If the pulse width value is greater than the

period, the assigned PWM pin(s) will

remain unchanged.

TABLE 24-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

0.31 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

Timer Prescale (1, 4, 64)

PR2 Value

64

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 24-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

0.31 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 64)

PR2 Value

64

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

Maximum Resolution (bits)

24.1.6

OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the

PWMx pin is driving a value, it will continue to drive that

value. When the device wakes up, TMR2 will continue

from its previous state.

24.1.7

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency (FOSC). Any changes in the system clock fre-

quency will result in changes to the PWM frequency.

Refer to Section 6.0 “Active Clock Tuning (ACT)

Module” for additional details.

24.1.8

EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

PWM registers to their Reset states.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 289

PIC16(L)F1454/5/9

24.1.9

SETUP FOR PWM OPERATION

USING PWMx PINS

The following steps should be taken when configuring

the module for PWM operation using the PWMx pins:

1. Disable the PWMx pin output driver(s) by setting

the associated TRIS bit(s).

2. Clear the PWMxCON register.

3. Load the PR2 register with the PWM period

value.

4. Clear the PWMxDCH register and bits <7:6> of

the PWMxDCL register.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the

PIR1 register. See note below.

• Configure the T2CKPS bits of the T2CON

register with the Timer2 prescale value.

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Enable PWM output pin and wait until Timer2

overflows; TMR2IF bit of the PIR1 register is set.

See note below.

7. Enable the PWMx pin output driver(s) by clear-

ing the associated TRIS bit(s) and setting the

PWMxOE bit of the PWMxCON register.

8. Configure the PWM module by loading the

PWMxCON register with the appropriate values.

Note 1: In order to send a complete duty cycle

and period on the first PWM output, the

above steps must be followed in the order

given. If it is not critical to start with a

complete PWM signal, then replace Step

4 with Step 8.

2: For operation with other peripherals only,

disable PWMx pin outputs.

DS41639A-page 290

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

24.2 Register Definitions: PWM Control

REGISTER 24-1: PWMxCON: PWM CONTROL REGISTER

R/W-0/0

R-0/0

R/W-0/0

U-0

—

U-0

—

U-0

—

U-0

—

PWMxEN

PWMxOE

PWMxOUT PWMxPOL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

PWMxEN: PWM Module Enable bit

1= PWM module is enabled

0= PWM module is disabled

PWMxOE: PWM Module Output Enable bit

1= Output to PWMx pin is enabled

0= Output to PWMx pin is disabled

bit 5

bit 4

PWMxOUT: PWM Module Output Value bit

PWMxPOL: PWMx Output Polarity Select bit

1= PWM output is active low

0= PWM output is active high

bit 3-0

Unimplemented: Read as ‘0’

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 291

PIC16(L)F1454/5/9

REGISTER 24-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS

R/W-x/u

bit 0

PWMxDCH<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.

REGISTER 24-3: PWMxDCL: PWM DUTY CYCLE LOW BITS

R/W-x/u

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

PWMxDCL<7:6>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-6

bit 5-0

PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.

Unimplemented: Read as ‘0’

TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PR2

Timer2 module Period Register

199*

291

292

201

199*

PWM1CON

PWM1DCH

PWM1DCL

PWM2CON

PWM2DCH

PWM2DCL

T2CON

PWM1EN

PWM1OE

PWM1OUT

PWM1POL

—

PWM1DCH<7:0>

PWM1DCL<7:6>

—

PWM2EN

PWM2OE

PWM2OUT

PWM2POL

PWM2DCH<7:0>

PWM2DCL<7:6>

—

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

TMR2

Timer2 module Register

—(1)

TRISA

—

TRISA5

TRISC5

TRISA4

—

132

140

TRISC

TRISC7⁽²⁾

TRISC6⁽²⁾

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

Legend:

-= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.

*

Page provides register information.

Note 1:

2:

Unimplemented, read as ‘1’.

PIC16(L)F1459 only.

DS41639A-page 292

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

25.0 COMPLEMENTARY WAVEFORM

GENERATOR (CWG) MODULE

(PIC16(L)F1455/9 ONLY)

The Complementary Waveform Generator (CWG) pro-

duces a complementary waveform with dead-band

delay from a selection of input sources.

The CWG module has the following features:

• Selectable dead-band clock source control

• Selectable input sources

• Output enable control

• Output polarity control

• Dead-band control with independent 6-bit rising

and falling edge dead-band counters

• Auto-shutdown control with:

- Selectable shutdown sources

- Auto-restart enable

- Auto-shutdown pin override control

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 293

PIC16(L)F1454/5/9

FIGURE 25-2:

TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)

cwg_clock

PWM1

CWGxA

Rising Edge

Deadband

Rising Edge Deadband

Rising Edge D

Falling Edge Deadband

CWGxB

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 295

PIC16(L)F1454/5/9

25.4.2

POLARITY CONTROL

25.1 Fundamental Operation

The polarity of each CWG output can be selected

independently. When the output polarity bit is set, the

corresponding output is active high. Clearing the output

polarity bit configures the corresponding output as

active low. However, polarity does not affect the

override levels. Output polarity is selected with the

GxPOLA and GxPOLB bits of the CWGxCON0 register.

The CWG generates a two output complementary

waveform from one of four selectable input sources.

The off-to-on transition of each output can be delayed

from the on-to-off transition of the other output thereby

creating an immediate time delay where neither output

is driven. This is referred to as dead time and is covered

in Section 25.5 “Dead-Band Control”. A typical

operating waveform, with dead band, generated from a

single input signal is shown in Figure 25-2.

25.5 Dead-Band Control

Dead-band control provides for non-overlapping output

signals to prevent shoot-through current in power

switches. The CWG contains two 6-bit dead-band

counters. One dead-band counter is used for the rising

edge of the input source control. The other is used for

the falling edge of the input source control.

It may be necessary to guard against the possibility of

circuit faults or a feedback event arriving too late or not

at all. In this case, the active drive must be terminated

before the Fault condition causes damage. This is

referred to as auto-shutdown and is covered in

Section 25.9 “Auto-Shutdown Control”.

Dead band is timed by counting CWG clock periods

from zero up to the value in the rising or falling dead-

band counter registers. See CWGxDBR and

CWGxDBF registers (Register 25-4 and Register 25-5,

respectively).

25.2 Clock Source

The CWG module allows the following clock sources

to be selected:

• Fosc (system clock)

• HFINTOSC (16 MHz only)

25.6 Rising Edge Dead Band

The clock sources are selected using the G1CS0 bit of

the CWGxCON0 register (Register 25-1).

The rising edge dead-band delays the turn-on of the

CWGxA output from when the CWGxB output is turned

off. The rising edge dead-band time starts when the

rising edge of the input source signal goes true. When

this happens, the CWGxB output is immediately turned

off and the rising edge dead-band delay time starts.

When the rising edge dead-band delay time is reached,

the CWGxA output is turned on.

25.3 Selectable Input Sources

The CWG can generate the complementary waveform

for the following input sources:

• async_C1OUT

• async_C2OUT

• PWM1OUT

The CWGxDBR register sets the duration of the dead-

band interval on the rising edge of the input source

signal. This duration is from 0 to 64 counts of dead band.

• PWM2OUT

The input sources are selected using the GxIS<1:0>

bits in the CWGxCON1 register (Register 25-2).

Dead band is always counted off the edge on the input

source signal. A count of 0 (zero), indicates that no

dead band is present.

25.4 Output Control

If the input source signal is not present long enough for

the count to complete, no output will be seen on the

respective output.

Immediately after the CWG module is enabled, the

complementary drive is configured with both CWGxA

and CWGxB drives cleared.

25.4.1

OUTPUT ENABLES

Each CWG output pin has individual output enable

control. Output enables are selected with the GxOEA

and GxOEB bits of the CWGxCON0 register. When an

output enable control is cleared, the module asserts no

control over the pin. When an output enable is set, the

override value or active PWM waveform is applied to

the pin per the port priority selection. The output pin

enables are dependent on the module enable bit,

GxEN. When GxEN is cleared, CWG output enables

and CWG drive levels have no effect.

DS41639A-page 296

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

25.7 Falling Edge Dead Band

The falling edge dead band delays the turn-on of the

CWGxB output from when the CWGxA output is turned

off. The falling edge dead-band time starts when the

falling edge of the input source goes true. When this

happens, the CWGxA output is immediately turned off

and the falling edge dead-band delay time starts. When

the falling edge dead-band delay time is reached, the

CWGxB output is turned on.

The CWGxDBF register sets the duration of the dead-

band interval on the falling edge of the input source sig-

nal. This duration is from 0 to 64 counts of dead band.

Dead band is always counted off the edge on the input

source signal. A count of 0 (zero), indicates that no

dead band is present.

If the input source signal is not present long enough for

the count to complete, no output will be seen on the

respective output.

Refer to Figure 25-5 and Figure 25-6 for examples.

25.8 Dead-Band Uncertainty

When the rising and falling edges of the input source

trigger the dead-band counters, the input may be asyn-

chronous. This will create some uncertainty in the dead-

band time delay. The maximum uncertainty is equal to

one CWG clock period. Refer to Equation 25-1 for more

detail.

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EQUATION 25-1: DEAD-BAND

UNCERTAINTY

1

TDEADBAND_UNCERTAINTY = ----------------------------

Fcwg_clock

Example:

Fcwg_clock = 16 MHz

Therefore:

1

TDEADBAND_UNCERTAINTY = ----------------------------

Fcwg_clock

1

= ------------------

16 MHz

= 625ns

 2012 Microchip Technology Inc.

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25.9 Auto-Shutdown Control

25.10 Operation During Sleep

Auto-shutdown is a method to immediately override the

CWG output levels with specific overrides that allow for

the safe shutdown of the circuit. The shutdown state

can be either cleared automatically or held until cleared

by software.

The CWG module operates independently from the

system clock and will continue to run during Sleep,

provided that the clock and input sources selected

remain active.

The HFINTOSC remains active during Sleep, provided

that the CWG module is enabled, the input source is

active, and the HFINTOSC is selected as the clock

source, regardless of the system clock source selected.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and the CWG clock

source, when the CWG is enabled and the input source

is active, the CPU will go idle during Sleep, but the CWG

will continue to operate and the HFINTOSC will remain

active. This will have a direct effect on the Sleep mode

current.

25.9.1

SHUTDOWN

The shutdown state can be entered by either of the

following two methods:

• Software generated

• External Input

25.9.1.1

Software Generated Shutdown

Setting the GxASE bit of the CWGxCON2 register will

force the CWG into the shutdown state.

When auto-restart is disabled, the shutdown state will

persist as long as the GxASE bit is set.

When auto-restart is enabled, the GxASE bit will clear

automatically and resume operation on the next rising

edge event. See Figure 25-6.

25.9.1.2

External Input Source

External shutdown inputs provide the fastest way to

safely suspend CWG operation in the event of a Fault

condition. When any of the selected shutdown inputs

go active, the CWG outputs will immediately go to the

selected override levels without a software delay. Any

combination of two input sources can be selected to

cause a shutdown condition. The sources are:

• async_C1OUT

• async_C2OUT

• CWG1FLT

Shutdown inputs are selected using the GxASDS0 and

GxASDS1 bits of the CWGxCON2 register

(Register 25-3).

Note:

Shutdown inputs are level sensitive, not

edge sensitive. The shutdown state can-

not be cleared, except by disabling

auto-shutdown, as long as the shutdown

input level persists.

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25.11.1 PIN OVERRIDE LEVELS

25.11 Configuring the CWG

The levels driven to the output pins, while the shutdown

input is true, are controlled by the GxASDLA and

GxASDLB bits of the CWGxCON1 register

(Register 25-2). GxASDLA controls the CWG1A

override level and GxASDLB controls the CWG1B

override level. The control bit logic level corresponds to

the output logic drive level while in the shutdown state.

The polarity control does not apply to the override level.

The following steps illustrate how to properly configure

the CWG to ensure a synchronous start:

1. Ensure that the TRIS control bits corresponding

to CWGxA and CWGxB are set so that both are

configured as inputs.

2. Clear the GxEN bit, if not already cleared.

3. Set desired dead-band times with the CWGxDBR

and CWGxDBF registers.

25.11.2 AUTO-SHUTDOWN RESTART

4. Setup the following controls in the CWGxCON2

auto-shutdown register:

After an auto-shutdown event has occurred, there are

two ways to have resume operation:

• Select desired shutdown source.

• Select both output overrides to the desired

levels (this is necessary even if not using

auto-shutdown because start-up will be from

a shutdown state).

• Software controlled

• Auto-restart

The restart method is selected with the GxARSEN bit

of the CWGxCON2 register. Waveforms of software

controlled and automatic restarts are shown in

Figure 25-5 and Figure 25-6.

• Set the GxASE bit and clear the GxARSEN

bit.

5. Select the desired input source using the

CWGxCON1 register.

25.11.2.1 Software Controlled Restart

6. Configure the following controls in the

CWGxCON0 register:

When the GxARSEN bit of the CWGxCON2 register is

cleared, the CWG must be restarted after an auto-shut-

down event by software.

• Select desired clock source.

• Select the desired output polarities.

Clearing the shutdown state requires all selected shut-

down inputs to be low; otherwise, the GxASE bit will

remain set. The overrides will remain in effect until the

first rising edge event after the GxASE bit is cleared.

The CWG will then resume operation.

• Set the output enables for the outputs to be

used.

7. Set the GxEN bit.

8. Clear TRIS control bits corresponding to

CWGxA and CWGxB to be used to configure

those pins as outputs.

25.11.2.2 Auto-Restart

When the GxARSEN bit of the CWGxCON2 register is

set, the CWG will restart from the auto-shutdown state

automatically.

9. If auto-restart is to be used, set the GxARSEN

bit and the GxASE bit will be cleared automati-

cally. Otherwise, clear the GxASE bit to start the

CWG.

The GxASE bit will clear automatically when all shut-

down sources go low. The overrides will remain in

effect until the first rising edge event after the GxASE

bit is cleared. The CWG will then resume operation.

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25.12 Register Definitions: CWG Control

REGISTER 25-1: CWGxCON0: CWG CONTROL REGISTER 0

R/W-0/0

GxEN

R/W-0/0

GxOEB

R/W-0/0

GxOEA

R/W-0/0

GxPOLB

R/W-0/0

GxPOLA

U-0

—

U-0

—

R/W-0/0

GxCS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

bit 4

bit 3

GxEN: CWGx Enable bit

1= Module is enabled

0= Module is disabled

GxOEB: CWGxB Output Enable bit

1= CWGxB is available on appropriate I/O pin

0= CWGxB is not available on appropriate I/O pin

GxOEA: CWGxA Output Enable bit

1= CWGxA is available on appropriate I/O pin

0= CWGxA is not available on appropriate I/O pin

GxPOLB: CWGxB Output Polarity bit

1= Output is inverted polarity

0= Output is normal polarity

GxPOLA: CWGxA Output Polarity bit

1= Output is inverted polarity

0= Output is normal polarity

bit 2-1

bit 0

Unimplemented: Read as ‘0’

GxCS0: CWGx Clock Source Select bit

1= HFINTOSC

0= FOSC

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REGISTER 25-2: CWGxCON1: CWG CONTROL REGISTER 1

R/W-x/u

U-0

—

U-0

—

R/W-0/0

GxASDLB<1:0>

GxASDLA<1:0>

GxIS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

GxASDLB<1:0>: CWGx Shutdown State for CWGxB

When an auto-shutdown event is present (GxASE = 1):

11= CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit

10= CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit

01= CWGxB pin is tri-stated

00= CWGxB pin is driven to its inactive state after the selected dead-band interval. GxPOLB still will

control the polarity of the output

bit 5-4

GxASDLA<1:0>: CWGx Shutdown State for CWGxA

When an auto shutdown event is present (GxASE = 1):

11= CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit

10= CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit

01= CWGxA pin is tri-stated

00= CWGxA pin is driven to its inactive state after the selected dead-band interval. GxPOLA still will

control the polarity of the output

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

GxIS<2:0>: CWGx Input Source Select bits

11= PWM2OUT

10= PWM1OUT

01= async_C1OUT

00= async_C2OUT

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REGISTER 25-3: CWGxCON2: CWG CONTROL REGISTER 2

R/W-0/0

GxASE

R/W-0/0

U-0

—

U-0

—

R/W-0/0

—

GxARSEN

GxASDC2

GxASDC1

GxASDFLT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

GxASE: Auto-Shutdown Event Status bit

1= An auto-shutdown event has occurred

0= No auto-shutdown event has occurred

GxARSEN: Auto-Restart Enable bit

1= Auto-restart is enabled

0= Auto-restart is disabled

bit 5-4

bit 3

Unimplemented: Read as ‘0’

GxASDC2: CWG Auto-Shutdown on Comparator 2 Enable

1= Shutdown when Comparator 2 output is high

0= Comparator 2 output has no effect on shutdown

bit 2

bit 1

bit 0

GxASDC1: CWG Auto-Shutdown on Comparator 1 Enable

1= Shutdown when Comparator 1 output is high

0= Comparator 1 output has no effect on shutdown

GxASDFLT: CWG Auto-Shutdown on FLT Enable bit

1= Shutdown when CWG1FLT input is low

0= CWG1FLT input has no effect on shutdown

Unimplemented: Read as ‘0’

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PIC16(L)F1454/5/9

REGISTER 25-4: CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING

DEAD-BAND COUNT REGISTER

U-0

—

U-0

—

R/W-x/u

CWGxDBR<5:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising Counts bits

11 1111= 63-64 counts of dead band

11 1110= 62-63 counts of dead band





00 0010= 2-3 counts of dead band

00 0001= 1-2 counts of dead band

00 0000= 0 counts of dead band

REGISTER 25-5: CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING

DEAD-BAND COUNT REGISTER

U-0

—

U-0

—

R/W-x/u

CWGxDBF<5:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling Counts bits

11 1111= 63-64 counts of dead band

11 1110= 62-63 counts of dead band





00 0010= 2-3 counts of dead band

00 0001= 1-2 counts of dead band

00 0000= 0 counts of dead band. Dead-band generation is bypassed

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PIC16(L)F1454/5/9

(2)

TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH CWG

Registe

r on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

ANSELA

—

ANSA4

—

GxPOLA

—

133

303

304

305

306

CWGxCON0

CWGxCON1

CWGxCON2

CWGxDBF

CWGxDBR

GxEN

GxOEB

GxOEA

GxPOLB

G1CS0

GxASDLB<1:0>

GxASDLA<1:0>

GxIS<1:0>

GxASE

GxARSEN

GxASDC2 GxASDC1

CWGxDBF<5:0>

GxASDFLT

—

CWGxDBR<5:0>

LATA

LATA5

TRISA5

TRISC5

LATA4

TRISA4

TRISC4

—

133

132

140

(1)

TRISA

TRISC

Legend:

—

TRISC7⁽¹⁾TRISC6⁽¹⁾

TRISC3

TRISC2

TRISC1

TRISC0

x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by CWG.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F1455/9 only.

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Preliminary

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NOTES:

DS41639A-page 308

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26.1 Overview

26.0 UNIVERSAL SERIAL BUS

(USB)

This device contains a full-speed and low-speed

compatible USB Serial Interface Engine (SIE) that

allows fast communication between any USB host and

the microcontroller. The SIE can be interfaced directly

to the USB by utilizing the internal transceiver. Some

special hardware features have been included to

improve performance. Dual access port memory in the

device's data memory space (USB RAM) has been

supplied to share direct memory access between the

microcontroller core and the SIE. Buffer descriptors are

also provided, allowing users to freely program

endpoint memory usage within the USB RAM space.

Figure 26-1 presents a general overview of the USB

peripheral and its features.

This section describes the details of the USB

peripheral. Because of the very specific nature of the

module, knowledge of USB is expected. Some high-

level USB information is provided in Section 26.1

“Overview” only for application design reference.

Designers are encouraged to refer to the official

specification published by the USB Implementers

Forum (USB-IF) for the latest information. USB

Specification Revision 2.0 is the most current

specification at the time of publication of this document.

FIGURE 26-1:

USB PERIPHERAL AND OPTIONS

USB PIC^®Microcontroller

(1)

VDD

V^USB3V3

3.3V LDO Regulator⁽²⁾

External 3.3V

Supply

Vcap

P

Internal Pull-ups

FSEN

UPUEN

P

Transceiver

FS

USB

D+

D-

USB Clock from the

Oscillator Module

EN

USB Control and

Configuration

USB

SIE

(3)

512 byte

USB RAM

1: Possible optional setup for LF parts only. F parts should use internal LDO to power V^USB3V3.

Note

2: On F devices the regulator is powered by Vdd. On LF devices the regulator is internally bypassed to Vdd.

3: 496 bytes accessible in both linear and banked data space. 16 bytes accessible in access data space only.

 2012 Microchip Technology Inc.

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The PKTDIS bit of the UCON register is a flag indicating

that the SIE has disabled packet transmission and

reception. This bit is set by the SIE when a SETUP token

is received to allow setup processing. This bit cannot be

set by the microcontroller, only cleared. Clearing the bit

to ‘0’ allows the SIE to continue transmission and/or

reception. Any pending events within the Buffer

Descriptor Table will still be available, indicated within

the USTAT register's FIFO buffer ENDP bits.

26.2 USB Status and Control

The operation of the USB module is configured and

managed through three control registers. In addition, a

total of 14 registers are used to manage the actual USB

transactions. The registers are:

• USB Control register (UCON)

• USB Configuration register (UCFG)

• USB Transfer Status register (USTAT)

• USB Device Address register (UADDR)

• Frame Number registers (UFRMH:UFRML)

• Endpoint Enable registers 0 through 7 (UEPn)

The RESUME bit of the UCON register configures the

peripheral to perform a remote wake-up by executing

Resume signaling. To generate a valid remote wake-up,

firmware must set the RESUME bit for 10 ms and then

automatically clear the bit. For more information on

“resume signaling”, see the USB 2.0 specification.

26.2.1

USB CONTROL (UCON) REGISTER

The USB Control register (Register 26-1) contains bits

needed to control the module behavior during

transfers. The register contains bits that control the

following:

The SUSPND bit of the UCON register places the

module and supporting circuitry in a Low-Power mode.

The input clock to the SIE is also disabled. This bit must

be set by the firmware in response to an IDLEIF

interrupt. It should be reset by the microcontroller

firmware after an ACTVIF interrupt is observed. When

this bit is active, the device remains attached to the bus

but the transceiver outputs remain Idle. The voltage on

the VUSB3V3 pin may vary depending on the value of

this bit. Setting this bit before a IDLEIF request will

result in unpredictable bus behavior.

• Main USB Peripheral Enable

• Ping-Pong Buffer Pointer Reset

• Control of the Suspend mode

• Packet Transfer Disable

The SE0 bit of the UCON register is used to indicate the

occurrence of a single-ended zero on the bus. When

the USB module is enabled, this bit should be

monitored to determine whether the differential data

lines have come out of a single-ended zero condition.

This helps to differentiate the initial power-up state from

the USB Reset signal.

Note:

While in Suspend mode, a typical bus-

powered USB device is limited to the

suspend current discussed in the USB 2.0

specification Chapter 7.2.3. This is the

complete current, which may be drawn by

the microcontroller and its supporting

circuitry. Care should be taken to assure

minimum current draw when the device

enters Suspend mode.

The USBEN bit of the UCON register is used to enable

and disable the module. Setting this bit activates the

module and resets all of the PPBI bits in the Buffer

Descriptor Table to ‘0’. If enabled, this bit will also

activate the USB internal pull-up resistors. Thus, this bit

can be used as a soft attach/detach to the USB. The

USB module needs to be supplied with an active clock

source before the USBEN bit can be set. Also, the USB

module needs to be fully preconfigured prior to

enabling the USB module.

26.2.2

USB CONFIGURATION (UCFG)

REGISTER

The UCFG register (Register 26-2) is used in

configuring system level behavior of the USB module.

All internal and external hardware should be configured

prior to attempting communications. The UCFG

register is used for the following USB functions:

Note:

If the PLL is being used, wait until the

PLLRDY bit is set in the OSCSTAT register

before attempting to set the USBEN bit.

• Bus Speed (Full/Low Speed)

• On-Chip Pull-up Resistor Enable

• Ping-Pong Buffer Usage

The PPBRST bit of the UCON register controls the

Reset status when Double-Buffering mode (ping-pong

buffering) is used. When the PPBRST bit is set, all

Ping-Pong Buffer Pointers are set to the Even buffers.

The PPBRST bit must be cleared by firmware. This bit

is ignored in buffering modes not using ping-pong

buffering.

The UTEYE bit of the UCFG register enables the eye

pattern generation. This bit aids in module testing,

debugging and USB certification processes. Refer to

26.2.2.4 “Eye Pattern Test Enable” for more detail.

Note:

The USB speed, transceiver and pull-up

should only be configured during the mod-

ule setup phase. It is not recommended to

switch these settings while the module is

enabled.

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26.2.2.1

Internal Transceiver

26.2.2.3

Ping-Pong Buffer Configuration

The USB peripheral has a full-speed and low-speed

USB 2.0 capable transceiver internally built-in and

connected to the SIE. The internal transceiver is

enabled when the USBEN bit of the USBCON register

is set. Full-speed operation is selected by setting the

FSEN bit of the UCFG register.

The usage of ping-pong buffers is configured using the

PPB bits of the UCFG register. Refer to Section 26.4.4

“Ping-Pong Buffering” for a complete explanation of

the ping-pong buffers.

26.2.2.4

Eye Pattern Test Enable

An automatic eye pattern test can be generated by setting

the UTEYE bit of the USFG register. The eye pattern

output is dependent upon the USB modules settings,

which must be configured prior to use. The module must

be enabled for eye pattern output to function.

The on-chip USB pull-up resistors are controlled by the

UPUEN bit of the USFG register. The pull-up resistors

can only be active when the USBEN bit of the USBCON

register is set and the module is configured for use.

The internal USB transceiver is powered from the

VUSB3V3 pin. In order to meet USB signaling level

specifications, VUSB3V3 must be supplied with a voltage

source between 3.0V and 3.6V. The best electrical

signal quality is obtained when a 3.3V supply is used

and locally bypassed with a high quality ceramic

capacitor. The capacitor should be placed as close as

possible to the VUSB3V3 and VSS pins.

Once UTEYE is set, the module emulates a switch from

a receive to transmit state and will start transmitting a

J-K-J-K bit sequence (K-J-K-J for full speed). The

sequence will be repeated indefinitely while the Eye

Pattern Test mode is enabled.

Note:

The UTEYE bit should never be set while

the module is connected to an actual USB

system.

Note:

The VUSB3V3 voltage is supplied.

This test mode is intended for board verification to aid

with USB certification tests. It is intended to show a

system developer the noise integrity of the USB signals

which can be affected by board traces, impedance

mismatches and proximity to other system components.

It does not properly test the transition from a receive to

a transmit state. Although the eye pattern is not meant

to replace the more complex USB certification test, it

should aid during first order system debugging.

The D+ and D- signal lines can be routed directly to

their respective pins on the USB connector or cable (for

hard-wired applications). No additional resistors,

capacitors, or magnetic components are required as

the D+ and D- drivers have controlled slew rate and

output impedance intended to match with the

characteristic impedance of the USB cable. See the

USB specifications for the impedance matching

requirements.

26.2.2.2

Internal Pull-Up Resistors

The PIC^®devices have built-in pull-up resistors

designed to meet the requirements for low-speed and

full-speed USB. The UPUEN bit of the UCFG register

enables the internal pull-ups.

Note:

The official USB specifications require the

that USB devices must never source any

current onto the VBUS line of the USB

cable. Additionally, USB devices must

never source any current on the D+/D-

data lines when the VBUS is below the

required voltage. In order to meet this

requirement, applications which are not

purely bus powered should monitor the

VBUS line and avoid turning on the USB

module and D+/D- internal pull-up resis-

tors until the VBUS meets requirements.

VBUS can be connected to and monitored

by any 5V tolerant I/O pin for this purpose.

Refer to USB Specification 2.0, 7.2.1 for

information.

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26.2.3

USB STATUS (USTAT) REGISTER

26.2.4

USB ENDPOINT CONTROL (UEPN)

REGISTER

The USB Status register (Register 26-3) reports the

transaction status within the SIE. When the SIE issues

a USB transaction complete interrupt (TRNIF bit),

USTAT should be read to determine the status of the

transfer. USTAT contains the transfer endpoint number,

direction and Ping-Pong Buffer Pointer value (if used).

Each bidirectional endpoint pair has its own

independent control register, UEPn (where 'n'

represents the endpoint number). Each register has an

identical complement of control bits (see Register 26-4).

The EPHSHK bit configures the USB handshaking for

the endpoint. Typically, this bit is always set except

when using isochronous endpoints.

Note:

The data in the USB Status register is

valid two SIE clocks after the TRNIF bit is

asserted.

The EPCONDIS bit configures the USB control

operations through the endpoint. Clearing this bit

enables SETUP transactions. The corresponding

EPINEN and EPOUTEN bits must be set to enable IN

and OUT transactions.

In low-speed operation with the system

clock operating at 48 MHz, a delay may

be required between receiving the trans-

action complete interrupt and processing

the data in the USTAT register.

Note:

For Endpoint 0, the EPCONDIS bit should

always be cleared since the USB

specifications identify Endpoint 0 as the

default control endpoint.

The USTAT register is actually a read window into a

four-byte status FIFO, maintained by the SIE. It allows

the microcontroller to process one transfer while the

SIE processes additional endpoints (Figure 26-2).

When the SIE completes using a buffer for reading or

writing data, it updates the USTAT register. If another

USB transfer is performed before the TRNIF bit is

serviced, the SIE will store the status of the next

transaction into the status FIFO.

The EPOUTEN bit configures USB OUT transactions

from the host. Setting this bit enables OUT

transactions. Similarly, the EPINEN bit is used to

configure the USB IN transactions from the host.

The EPSTALL bit indicates a STALL condition for the

endpoint. If a STALL is issued on a particular endpoint,

the EPSTALL bit for that endpoint pair will be set by the

SIE. This bit remains set until it is cleared through

firmware, or until the SIE is reset.

Clearing the TRNIF bit advances the FIFO. If the next

data in the FIFO holding register is valid, the SIE will

reassert the interrupt within 6 TCY of clearing the

TRNIF bit. If no additional data is present, the TRNIF bit

will remain clear; USTAT data will no longer be reliable.

26.2.5

USB ADDRESS (UADDR) REGISTER

Note:

If an endpoint request is received while

the USTAT FIFO is full, the SIE will

automatically issue a NAK back to the

host.

The USB Address register contains the unique USB

address that the peripheral will decode when active.

The UADDR register is reset to 00h when a USB Reset

is received, indicated by the USB Reset Interrupt bit

(URSTIF), or when a Reset is received from the micro-

controller. The USB address must be written in

response to the USB SET_ADDRESS request.

FIGURE 26-2:

USTAT FIFO

USTAT from SIE

26.2.6

USB FRAME NUMBER REGISTERS

(UFRMH:UFRML)

The Frame Number registers contain the 11-bit frame

number. The low-order byte is contained in UFRML,

while the three high-order bits are contained in

UFRMH. The register pair is updated with the current

frame number whenever a SOF token is received. For

the microcontroller, these registers are read-only. The

Frame Number registers are primarily used for

isochronous transfers. The contents of the UFRMH and

UFRML registers are only valid when the 48 MHz SIE

clock is active (i.e., contents are inaccurate when

SUSPND bit of the UCON register is set).

Clearing TRNIF

Advances FIFO

4-Byte FIFO

for USTAT

Data Bus

DS41639A-page 312

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26.3 USB RAM

26.4 Buffer Descriptors and the Buffer

Descriptor Table

USB data moves between the microcontroller core and

the SIE through the dual-port USB RAM. This is a

special dual access memory that is mapped into a

normal data memory space (Figure 26-3).

The dual-port general purpose memory space is used

specifically for endpoint buffer control in a structure

known as the Buffer Descriptor Table (BDT). This

provides a flexible method for users to construct and

control endpoint buffers of various lengths and

configuration.

The dual-port general purpose memory space is used

specifically for endpoint buffer control. Depending on

the type of buffering being used, all but 8 bytes of Bank

0 may also be available for use as USB buffer space.

The BDT is composed of Buffer Descriptors (BDs)

which are used to define and control the actual buffers

in the USB RAM space. Each BD, in turn, consists of

four registers:

Although USB RAM is available to the microcontroller as

data memory, the sections that are being accessed by

the SIE should not be accessed by the microcontroller.

A semaphore mechanism is used to determine the

access to a particular buffer at any given time. This is

discussed in Section 26.4.1.1 “Buffer Ownership”.

• BDnSTAT: BD Status register

• BDnCNT: BD Byte Count register

• BDnADRL: BD Address Low register

• BDnADRH: BD Address High register

FIGURE 26-3:

IMPLEMENTATION OF

USB RAM IN DATA

MEMORY SPACE

Note:

Wherever BDn is identified within this

document, the n represents one of the

possible BDs.

BDs always occur as a four-byte block in the sequence,

BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address

of BDnSTAT is accessible in linear data space at 2000h

+ (4n – 1) with n being the buffer descriptor number.

2000h

512 Byte

CPU Dual-Port RAM

Depending on the buffering configuration used

(Section 26.4.4 “Ping-Pong Buffering”), there are

multiple sets of buffer descriptors. The USB

specification mandates that every device must have

Endpoint 0 with both input and output for initial setup.

21FFh

2200h

Although they can be thought of as Special Function

Registers, the Buffer Descriptor Status and Address

registers are not hardware mapped, as conventional

microcontroller SFRs are. When the endpoint

corresponding to a particular BD is not enabled, then its

registers are not used. Instead of appearing as

unimplemented addresses, however, they appear as

available RAM. Only when an endpoint is enabled by

setting the EPINEN bit of the UEPn register does the

memory at those addresses become functional as BD

registers. As with any address in the data memory

space, the BD registers have an indeterminate value on

any device Reset.

512 Byte

CPU Single-Port RAM

23FFh

2400h

USB RAM Port Remap

(TSTDPEN = 1)

25FFh

2600h

An example of a BD for a 64-byte buffer is shown in

Figure 26-4. A particular set of BD registers is only

valid if the corresponding endpoint has been enabled

using the EPINEN bit. All BD registers are available in

USB RAM. The BD for each endpoint should be set up

prior to enabling the endpoint.

Unimplemented

Read ‘0’

29AFh

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Preliminary

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When the UOWN bit is set, giving ownership to the

USB peripheral, the SIE updates the BDs as

necessary, overwriting the original BD values. Thus,

values written by the user to BD are no longer

dependable. Instead, the BDnSTAT register is updated

automatically by the SIE with the token PID and

transfer count (BDnCNT).

FIGURE 26-4:

EXAMPLE OF A BUFFER

DESCRIPTOR

2000h

2001h

2002h

2003h

BD0STAT

(xxh)

(40h)

(80h)

Size of Block

Starting

BD0CNT

BD0ADRL

BD0ADRH

(20h)

Address

2080h

The BDnSTAT byte of the BDT should always be the

last byte updated when preparing to arm an endpoint.

The SIE will clear the UOWN bit when a transaction

has completed.

Buffer

USB Data

Because no hardware mechanism exists to block

access to the memory, unexpected behavior can occur

if the microcontroller attempts to modify memory while

the SIE owns it. Also, reading the memory may

produce inaccurate data until the USB peripheral

returns ownership to the microcontroller.

20BFh

Note:

Memory regions not to scale.

26.4.1

BD STATUS AND CONFIGURATION

The USB Data memory ownership and the BDnSTAT

bits change functionality depending on the UOWN bit

level.

26.4.1.2

BDnSTAT Register (CPU Mode)

When UOWN = 0, the microcontroller core owns the

BD and the other bits of the register become control

functions.

Unlike other control registers, the bit configuration for

the BDnSTAT register is context sensitive determined

by the UOWN bit. If the UOWN bit is clear, the

microcontroller has the ability to modify the BD and its

corresponding buffer. If the UOWN bit is set, the USB

SIE has the ability to modify the BD and its

corresponding buffer. The UOWN, BC9 and BC8 bit

definitions are contained within the BDnSTAT register,

regardless of the UOWN bit value.

The Data Toggle Sync Enable (DTSEN) bit of the

BDnSTAT register controls data toggle parity checking

and, when set, enables data toggle synchronization by

the SIE. When enabled, the DTSEN checks the data

packet's parity against the value of the Data Toggle

Synchronization (DTS) bit. Packets incorrectly

synchronized are ignored and will not be written to the

USB RAM. The USB TRNIF bit will not be set.

However, the SIE will send an ACK token to the host to

acknowledge receipt. Refer to Table 26-1 for the effects

of the DTSEN bit on the SIE.

26.4.1.1

Buffer Ownership

A simple semaphore mechanism is used to distinguish

if the CPU or USB module is allowed to update the BD

and associated buffers in memory, which is shared by

both.

The Buffer Stall bit, BSTALL of the BDnSTAT register,

provides support for control transfers, usually one-time

stalls on Endpoint 0. It also provides support for the

The UOWN bit of the BDnSTAT register is used as a

semaphore to distinguish if the USB or CPU is allowed

to update the BD and associated buffers in memory.

Only the UOWN bit shares functionality between the

two configurations of the BDnSTAT register.

SET_FEATURE/CLEAR_FEATURE

commands

specified in Chapter 9 of the USB specification.

Typically, these commands are executed by continuous

STALLs to any endpoint other than the default control

endpoint.

When the UOWN bit is clear, the BD entry and buffer

memory are “owned” by the microcontroller core. When

the UOWN bit is set, these are “owned” by the USB

peripheral. The BD and corresponding buffers should

only be modified by the “owner”. However, the

BDnSTAT register can be read by either the

microcontroller or the USB, even if they are not the

“owner”.

The BSTALL bit enables buffer stalls. Setting BSTALL

causes the SIE to return a STALL token to the host if a

received token would use the BD in that location. The

EPSTALL bit in the corresponding UEPn control

register is set and a STALL interrupt is generated when

a STALL is issued to the host. The UOWN bit remains

set and the BDs are not changed unless a SETUP

token is received. In this case, the STALL condition is

cleared and the ownership of the BD is returned to the

microcontroller core.

Because the buffer descriptor meanings are based

upon the source of the register update, the user must

configure the basic operation of the USB peripheral

through the BDnSTAT register prior to placing

ownership with the USB peripheral. While still owned

by the microcontroller, the byte count and buffer

location registers must also be set.

The BD bits of the BDnSTAT register store the two Most

Significant digits of the SIE byte count; the lower 8 digits

are stored in the corresponding BDnCNT register. See

Section 26.4.2 “BD Byte Count” for more information.

DS41639A-page 314

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TABLE 26-1: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION

BDnSTAT Settings

Device Response after Receiving Packet

Handshake UOWN TRNIF BDnSTAT and USTAT Status

Updated

OUT Packet

from Host

DTSEN

DTS

DATA0

1

0

x

0

1

x

ACK

NAK

0

1

0

1

0

1

0

DATA1

Not Updated

Updated

DATA0

DATA1

Either

Updated

Either, with error

Not Updated

Legend: x= don’t care

(OUT endpoint) with a BD location in use can yield

unexpected results. When developing USB applications,

the user may want to consider the inclusion of software-

based address validation in their code.

26.4.1.3 BDnSTAT Register (SIE Mode)

When the BD and its buffer are owned by the SIE, most

of the bits in BDnSTAT take on a different meaning. The

configuration is shown in Register 26-6. Once the

UOWN bit is set, any data or control settings previously

written there by the user will be overwritten with data

from the SIE.

26.4.4

PING-PONG BUFFERING

An endpoint is defined to have a ping-pong buffer when

it has two sets of BD entries: one set for an Even

transfer and one set for an Odd transfer. This allows the

CPU to process one BD while the SIE is processing the

other BD. Double-buffering BDs in this way allows for

maximum throughput to/from the USB.

The BDnSTAT register is updated by the SIE with the

token Packet Identifier (PID), which is stored in the PID

bits of the BDnSTAT register. The transfer count in the

corresponding BDnCNT register is updated. Values

that overflow the 8-bit register carry over to the two

Most Significant digits of the count, BD bits of the

BDnSTAT register.

The USB module supports four modes of operation:

• No ping-pong support

• Ping-pong buffer support for OUT Endpoint 0 only

• Ping-pong buffer support for all endpoints

26.4.2

BD BYTE COUNT

The byte count represents the total number of bytes

that will be transmitted during an IN transfer. After an IN

transfer, the SIE will return the number of bytes sent to

the host.

• Ping-pong buffer support for all other Endpoints

except Endpoint 0

The ping-pong buffer settings are configured using the

PPB bits in the UCFG register.

For an OUT transfer, the byte count represents the

maximum number of bytes that can be received and

stored in USB RAM. After an OUT transfer, the SIE will

return the actual number of bytes received. If the

number of bytes received exceeds the corresponding

byte count, the data packet will be rejected and a NAK

handshake will be generated. When this happens, the

byte count will not be updated.

The USB module keeps track of the Ping-Pong Pointer

individually for each endpoint. All pointers are initially

reset to the Even BD when the module is enabled. After

the completion of a transaction (UOWN cleared by the

SIE), the pointer is toggled to the Odd BD. After the

completion of the next transaction, the pointer is

toggled back to the Even BD and so on.

The Even/Odd status of the last transaction is stored in

the PPBI bit of the USTAT register. The user can reset

all Ping-Pong Pointers to Even using the PPBRST bit.

Figure 26-5 shows the four different modes of opera-

tion and how USB RAM is filled with the BDs. BDs have

a fixed relationship to a particular endpoint depending

on the buffering configuration. The mapping of BDs to

endpoints is detailed in Table 26-2. This relationship

also means that gaps may occur in the BDT if end-

points are not enabled contiguously. This theoretically

means that the BDs for disabled endpoints could be

used as buffer space. In practice, users should avoid

using such spaces in the BDT unless a method of vali-

dating BD addresses is implemented.

The 10-bit byte count is distributed over two registers.

The lower 8 bits of the count reside in the BDnCNT reg-

ister. The upper two bits reside in the BC bits of the

BDnSTAT register. This represents a valid byte range

of 0 to 1023.

26.4.3

BD ADDRESS VALIDATION

The BD Address register pair contains the starting RAM

address location for the corresponding endpoint buffer.

No mechanism is available in hardware to validate the

BD address.

If the value of the BD address does not point to an

address in the USB RAM, or if it points to an address

within another endpoint's buffer, data is likely to be lost

or overwritten. Similarly, overlapping a receive buffer

 2012 Microchip Technology Inc.

Preliminary

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PIC16(L)F1454/5/9

FIGURE 26-5:

BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES

PPB<1:0> = 00

No Ping-Pong

Buffers

PPB<1:0> = 01

Ping-Pong Buffer

on EP0 OUT

PPB<1:0> = 10

Ping-Pong

Buffers on all EPs

PPB<1:0> = 11

Ping-Pong Buffers on all

other EPs except EP0

2000h

EP0 OUT

Descriptor

EP0 OUT

Even Descriptor

2000h

EP0 OUT

Even Descriptor

EP0 OUT

Descriptor

EP0 IN

Descriptor

EP0 OUT

Odd Descriptor

EP0 OUT

Odd Descriptor

EP0 IN

Descriptor

EP1 OUT

Descriptor

EP0 IN

Descriptor

EP0 IN

Even Descriptor

EP1 OUT

Even Descriptor

EP1 IN

Descriptor

EP1 OUT

Descriptor

EP0 IN

Odd Descriptor

EP1 OUT

Odd Descriptor

EP1 IN

Descriptor

EP1 OUT

Even Descriptor

EP1 IN

Even Descriptor

EP1 OUT

Odd Descriptor

EP1 IN

Odd Descriptor

EP7 IN

Descriptor

EP1 IN

Even Descriptor

203Fh

EP7 IN

Descriptor

EP1 IN

Odd Descriptor

2043h

EP7 IN

Odd Descriptor

Available

as

Data RAM

2077h

2200h

Available

as

Data RAM

EP7 IN

Odd Descriptor

Available

as

Data RAM

207Fh

2200h

Available

as

Data RAM

2200h

Maximum Memory

Used: 64 bytes

Maximum BDs:

16 (BD0 to BD15)

Maximum Memory

Used: 68 bytes

Maximum BDs:

17 (BD0 to BD15)

Maximum Memory

Used: 128 bytes

Maximum BDs:

Maximum Memory

Used: 120 bytes

Maximum BDs:

32 (BD0 to BD31)

30 (BD0 to BD14

Note: Memory area not shown to scale.

TABLE 26-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT

BUFFERING MODES

BDs Assigned to Endpoint

Mode 3

(Ping-Pong on all other EPs,

except EP0)

Mode 0

(No Ping-Pong)

Mode 1

(Ping-Pong on EP0 OUT)

Mode 2

(Ping-Pong on all EPs)

Endpoint

Out

In

Out

In

Out

In

Out

In

0

2

1

3

0 (E), 1 (O)

2

4

0 (E), 1 (O)

4 (E), 5 (O)

8 (E), 9 (O)

2 (E), 3 (O)

6 (E), 7 (O)

0

1

3

5

2 (E), 3 (O)

6 (E), 7 (O)

4 (E), 5 (O)

8 (E), 9 (O)

2

4

5

6

10 (E), 11 (O)

3

6

7

8

12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)

16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)

20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)

24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)

4

8

9

10

12

14

16

5

10

12

14

11

13

15

11

13

15

6

7

28 (E), 29 (O)

30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)

Legend:

(E) = Even transaction buffer, (O) = Odd transaction buffer

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TABLE 26-3: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BDnSTAT⁽¹⁾

UOWN

DTS⁽⁴⁾

PID3⁽²⁾

PID2⁽²⁾

PID1⁽²⁾

PID0⁽²⁾

BC9

BC8

DTSEN⁽³⁾

BSTALL⁽³⁾

BDnCNT⁽¹⁾

Byte Count

BDnADRL⁽¹⁾Buffer Address Low

BDnADRH⁽¹⁾Buffer Address High

Note 1: For buffer descriptor registers, n may have a value of 0 to 31. For the sake of brevity, all 32 registers are

shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).

2: Bits <5:2> of the BDnSTAT register are used by the SIE to return PID<3:0> values once the register is

turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values

written for DTSEN and BSTALL are no longer valid.

3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the

BDnSTAT register are used to configure the DTSEN and BSTALL settings.

4: This bit is ignored unless DTSEN = 1.

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PIC16(L)F1454/5/9

level and interrupts are enabled through the UIE

register, while flags are maintained through the UIF

register. USB error conditions are considered the

second level and interrupts are enabled through the

UEIE register, while flags are maintained through the

UEIF register. Any USB interrupt condition will trigger

the USB Error Interrupt Flag, the UERRIF bit of the UIF

register.

26.5 USB Interrupts

The USB module can generate multiple interrupt

conditions. To accommodate all of these interrupt

sources, the module is provided with its own interrupt

logic structure, similar to that of the microcontroller.

USB interrupts are enabled with one set of control

registers and trapped with a separate set of flag

registers. All sources are funneled into a single USB

interrupt request, USBIF bit of the PIR2 for use with the

microcontroller's interrupt logic.

Interrupts may be used to trap routine events in a USB

transaction. Figure 26-7 shows some common events

within a USB frame and their corresponding interrupts.

Figure 26-6 shows the interrupt logic for the USB

module, which is divided into two registers in the USB

module. USB status interrupts are considered the top

FIGURE 26-6:

USB INTERRUPT LOGIC FUNNEL

Top Level USB Interrupts

Second Level USB Interrupts

(USB Status Interrupts)

(USB Error Conditions)

UIR (Flag) and UIE (Enable) Registers

UEIR (Flag) and UEIE (Enable) Registers

SOFIF

SOFIE

BTSEF

BTSEE

TRNIF

TRNIE

USBIF

BTOEF

BTOEE

IDLEIF

IDLEIE

DFN8EF

DFN8EE

UERRIF

UERRIE

CRC16EF

CRC16EE

STALLIF

STALLIE

CRC5EF

CRC5EE

PIDEF

PIDEE

ACTVIF

ACTVIE

URSTIF

URSTIE

FIGURE 26-7:

EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS

To Host

ACK

From Host

Data

Set TRNIF

SETUPToken

From Host

IN Token

To Host

Data

From Host

ACK

USB Reset

URSTIF

From Host

To Host

ACK

Start-of-Frame (SOF)

OUT Token Empty Data

Transaction

SOFIF

Transaction

Complete

SOF

RESET

Differential Data

SOF

SETUP

DATA

STATUS

Control Transfer⁽¹⁾

1 ms Frame

Note 1:

The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers

will spread across multiple frames.

DS41639A-page 318

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26.5.1

USB INTERRUPT STATUS (UIR)

REGISTER

26.5.2

USB INTERRUPT ENABLE

REGISTER (UIE)

The USB Interrupt Status register (Register 26-7) con-

tains the flag bits for each of the USB Status interrupt

sources. Each of these sources has a corresponding

interrupt enable bit in the UIE register. All of the USB

status flags are ORed together to generate the USBIF

interrupt flag for the microcontroller's interrupt funnel.

The USB Interrupt Enable register (Register 26-8) con-

tains the enable bits for the USB Status interrupt

sources. Setting any of these bits will enable the

respective interrupt source in the UIR register.

The values in this register only affect the propagation of

an interrupt condition to the microcontroller's interrupt

logic. The flag bits are set by their interrupt conditions,

allowing them to be polled and serviced without actu-

ally generating an interrupt.

Once an interrupt bit has been set by the SIE, it must

be cleared by software. The flag bits can also be set in

software which can aid in firmware debugging.

Note:

All status flags in the UIR register should

be resolved and cleared before the USBIF

bit is cleared.

26.5.3

USB ERROR INTERRUPT STATUS

REGISTER (UEIR)

The USB Error Interrupt Status register (Register 26-9)

contains the flag bits for each of the error sources

within the USB peripheral. Each of these sources is

enabled by a corresponding bit in the UEIE register. All

of the USB error flags are ORed together to generate

the USB Error Interrupt Flag (UERRIF) at the top level

of the interrupt logic.

26.5.1.1

Bus Activity Detect Interrupt Bit

(ACTVIF)

The ACTVIF bit cannot be cleared immediately after the

USB module wakes up from Suspend or while the USB

module is suspended. A few clock cycles are required to

synchronize the internal hardware state machine before

the ACTVIF bit can be cleared by firmware. Clearing the

ACTVIF bit in firmware before the internal hardware is

synchronized may not have an effect on the value of

ACTVIF. The USB module may not be immediately oper-

ational after clearing the SUSPND bit if using the 48 MHz

PLL source because the PLL will require time to lock.

The application code should clear the ACTVIF flag as

shown in Example 26-1.

Each error bit is set as soon as the error condition is

detected. Thus, the interrupt will typically not corre-

spond with the end of a token being processed.

Once an interrupt bit has been set by the SIE, it must

be cleared by software.

Note:

All status flags in the UEIR register should

be resolved and cleared before the

UERRIF bit is cleared.

Only one ACTVIF interrupt is generated when resum-

ing from the USB bus Idle condition. If user firmware

clears the ACTVIF bit, even when there is continuous

bus traffic, the bit will not become set again until after a

IDLEIF condition occurs. Bus traffic must cease long

enough to generate another IDLEIF condition before

another ACTVIF interrupt can be generated.

26.5.4

USB INTERRUPT (UEIE) ENABLE

REGISTER

The USB Error Interrupt Enable register (Register 26-10)

contains the enable bits for each of the USB error inter-

rupt sources. Setting any of these bits will enable the

respective error interrupt source in the UEIR register. If

enabled, the UERRIF bit of the UIR register will be set

when any USB error interrupt is set.

EXAMPLE 26-1:

CLEARING ACTVIF BIT

(UIR<2>)

As with the UIE register, the enable bits only affect the

propagation of an interrupt condition to the

microcontroller's interrupt logic. The flag bits are set by

their interrupt conditions, allowing them to be polled

and serviced without actually generating an interrupt.

Assembly:

BCF

LOOP:

UCON, SUSPND

UIR, ACTVIF

BTFSS

BRA

DONE

BCF

BRA

UIR, ACTVIF

LOOP

DONE:

C:

UCONbits.SUSPND = 0;

while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }

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Preliminary

DS41639A-page 319

PIC16(L)F1454/5/9

In order to meet compliance specifications, the USB

module (and the D+ or D- internal pull-ups) should not

be enabled until the host actively drives VBUS high.

26.6 USB Power Modes

The USB peripheral often has different power

requirements and configurations depending on the

application.

The application should never source any current onto

the 5V VBUS pin of the USB cable.

The most common cases are presented here:

• Bus Power Only

FIGURE 26-9:

SELF-POWER ONLY

• Self-Power Only

• Dual Power with Self-Power Dominance

VSELF

VDD

Means of estimating the current consumption of the

USB transceiver are also provided.

VUSB3V3

VSS

26.6.1

BUS POWER ONLY

In Bus Power Only mode, all power for the application

is drawn from the USB (Figure 26-8). This is effectively

the simplest power method for the device.

In order to meet the inrush current requirements of the

USB 2.0 specifications, the total effective capacitance

appearing across VBUS and ground must be no more

than 10 F. Circuitry is required to limit inrush current,

see section 7.2.4 of the USB specification for more

detail.

26.6.3

DUAL POWER WITH SELF-POWER

DOMINANCE

In Dual Power with Self-Power Dominance mode, the

application uses internal power as the primary source,

but can switch power from the USB when no internal

power is available. Figure 26-10 shows a simple Dual

Power with Self-Power Dominance mode example,

which automatically switches between Self-Power Only

and USB Bus Power Only modes.

All USB devices must support a Low-Power Suspend

mode which meets the current limits from the 5V VBUS

line of the USB cable according to the USB 2.0 specifi-

cation. For high-powered devices that are remote

wake-up capable, a higher limit is allocated. Refer to

USB Specification 2.0, 7.2.3 for information.

Dual power devices must also meet all of the special

requirements for inrush current and Suspend mode

current and must not enable the USB module (or the

D+/D- internal pull-ups) until VBUS is driven high. See

The host signals the USB device to enter the Suspend

mode by stopping all USB traffic to that device for more

than 3 ms. This condition will cause the IDLEIF bit in

the UIR register to become set.

Section 26.6.1

“Bus

Power

Only”

and

Section 26.6.2 “Self-Power Only” for descriptions of

those requirements. Additionally, dual power devices

must never source current onto the 5V VBUS pin of the

USB cable.

During the USB Suspend mode, the D+ or D- pull-up

resistor must remain active, which will consume some

of the allowed suspend current budget.

FIGURE 26-8:

BUS POWER ONLY

FIGURE 26-10:

DUAL POWER EXAMPLE

VBUS

VDD

VBUS

~5V

VDD

VUSB3V3

VSS

100 k

VUSB3V3

VSS

VSELF

~5V

26.6.2

SELF-POWER ONLY

In Self-Power Only mode, the USB application provides

its own power, with very little power being pulled from

the USB. Figure 26-9 shows an example.

Note:

Users should keep in mind the limits for

devices drawing power from the USB.

Refer to USB Specification 2.0, 7.2.3 for

more information.

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26.6.4

USB TRANSCEIVER CURRENT

CONSUMPTION

The USB transceiver consumes a variable amount of

current, depending on following factors:

• Impedance of USB cable

• Length of cable

• VUSB3V3 supply voltage

• Data patterns across cable

Note:

Longer cables have larger capacitance

and consume more total energy when

switching output states.

Data patterns consist of “IN” and “OUT” traffic. “IN”

traffic consumes more current and requires the

microcontroller to drive the USB cable, while “OUT”

traffic requires the host to drive the USB cable.

The data sent across the USB cable is NRZI encoded.

A ‘0’ in the NRZI encoding scheme toggles the output

state of the transceiver (from “J” state to a “K” state, or

vice versa). A ‘1’ in the NRZI does not change the

output state of the transceiver, with the exception of the

effects of bit-stuffing. Because “IN” traffic consists of

data bits of value ‘0’, the transceiver must charge/

discharge the USB cable to change states resulting in

the most current consumption.

More details about NRZI encoding and bit-stuffing can be

found in the USB 2.0 specification's section 7.1, although

knowledge of such details is not required to make USB

applications using PIC^®microcontrollers. Among other

things, the SIE handles bit-stuffing/unstuffing, NRZI

encoding/decoding and CRC generation/checking in

hardware.

The total transceiver current consumption will be

application-specific. However, to help estimate how

much current actually may be required in full-speed

applications, Equation 26-1 can be used.

Example 26-2 shows how this equation can be used for

a theoretical application.

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EQUATION 26-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION

(60 mA • VUSB3V3 • PZERO • PIN • LCABLE)

IXCVR =

+ IPULLUP

(3.3V • 5m)

Legend:

VUSB3V3: Voltage on the VUSB3V3 pin in volts.

For F devices, VUSB3V3 = 3.3V supplied from the internal regulator, VDD  3.6V.

For LF devices, VUSB3V3 is supplied by VDD 3.0  VDD 3.6.

PZERO:

PIN:

Percentage of the IN traffic bits sent by the PIC^®device that are a value of ‘0’.

Percentage of total bus bandwidth that is used for IN traffic.

LCABLE:

Length (in meters) of the USB cable. The USB 2.0 specification requires that full-speed applications

use cables no longer than 5m.

IPULLUP:

Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB cable. On

the host or hub end of the USB cable, 15 k nominal resistors (14.25 k to 24.8 k) are present which

pull both the D+ and D- lines to ground. During bus Idle conditions (such as between packets or during

USB Suspend mode), this results in up to 218 A of quiescent current drawn at 3.3V.

IPULLUP is also dependant on bus traffic conditions and can be as high as 2.2 mA when the USB bandwidth

is fully utilized (either IN or OUT traffic) for data that drives the lines to the “K” state most of the time.

†

EXAMPLE 26-2:

CALCULATING USB TRANSCEIVER CURRENT

For this example, the following assumptions are made about the application:

• 3.3V will be applied to VUSB3V3 and VDD, with the core voltage regulator enabled.

• This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64 bytes every

1 ms, with no restrictions on the values of the bytes being sent. The application may or may not have

additional traffic on OUT endpoints.

• A regular USB “B” or “mini-B” connector will be used on the application circuit board.

In this case, PZERO = 100% = 1, because there should be no restriction on the value of the data moving through

the IN endpoint. All 64 kBps of data could potentially be bytes of value, 00h. Since ‘0’ bits cause toggling of the

output state of the transceiver, they cause the USB transceiver to consume extra current charging/discharging the

cable. In this case, 100% of the data bits sent can be of value ‘0’. This should be considered the “max” value, as

normal data will consist of a fair mix of ones and zeros.

This application uses 64 kBps for IN traffic out of the total bus bandwidth of 1.5 MBps (12 Mbps), therefore:

64 kBps

1.5 MBps

Pin =

= 4.3% = 0.043

Since a regular “B” or “mini-B” connector is used in this application, the end user may plug in any type of cable up

to the maximum allowed 5 m length. Therefore, we use the worst-case length:

LCABLE = 5 meters

Assume IPULLUP = 2.2 mA. The actual value of IPULLUP will likely be closer to 218 A, but allow for the worst-case.

USB bandwidth is shared between all the devices which are plugged into the root port (via hubs). If the application

is plugged into a USB 1.1 hub that has other devices plugged into it, your device may see host to device traffic on

the bus, even if it is not addressed to your device. Since any traffic, regardless of source, can increase the IPULLUP

current above the base 218 A, it is safest to allow for the worst-case of 2.2 mA.

Therefore:

(60 mA • 3.3V • 1 • 0.043 • 5m)

IXCVR =

+ 2.2 mA = 4.8 mA

(3.3V • 5m)

The calculated value should be considered an approximation and additional guardband or application-specific prod-

uct testing is recommended. The transceiver current is “in addition to” the rest of the current consumed by the

microcontroller.

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26.7 Oscillator

The USB module has specific clock requirements. For

full-speed operation, the clock source must be 48 MHz.

Even so, the microcontroller core and other peripherals

are not required to run at that clock speed. Available

clocking options are described in detail in Section 5.4

“USB Operation”.

26.8 Interrupt-On-Change for D+/D-

Pins

The microcontroller has interrupt-on-change function-

ality on both D+ and D- data pins, which allows the

device to detect voltage level changes when first con-

nected to a USB host/hub. This feature is not available

when the USB module is enabled.

The USB host/hub has 15K pull-down resistors on the

D+ and D- pins. When the microcontroller attaches to

the bus, the D+ and D- pins can detect voltage

changes. External resistors are needed for each pin to

maintain

a high state on the pins when the

microcontroller is detached.

The USB module must be disabled (USBEN = 0) for the

interrupt-on-change to function. Enabling the USB

module (USBEN = 1) will automatically disable the

interrupt-on-change for D+ and D- pins. Refer to

Section 13.0 “Interrupt-On-Change” for more detail.

26.9 USB Firmware and Drivers

Microchip provides a number of application-specific

resources, such as USB firmware and driver support.

Refer to www.microchip.com for the latest firmware and

driver support.

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26.10.2 FRAMES

26.10 USB Operation Overview

Information communicated on the bus is grouped into

1 ms time slots, referred to as frames. Each frame can

contain many transactions to various devices and

This section presents some of the basic USB concepts

and useful information necessary to design a USB

device. Although a lot of information is provided in this

section, refer to the USB 2.0 specification for more

details, as needed.

endpoints. Figure 26-7 shows an example of

transaction within a frame.

a

26.10.3 TRANSFERS

26.10.1 LAYERED FRAMEWORK

There are four transfer types defined in the USB

specification:

USB device functionality is structured into a layered

framework, graphically shown in Figure 26-11. Each level

is associated with a functional level within the device. The

highest layer, other than the device, is the configuration. A

device may have multiple configurations. For example, a

particular device may have multiple power requirements

based on Self-Power Only or Bus Power Only modes.

Isochronous: This type provides a transfer method for

large amounts of data (up to 1023 bytes) with timely

delivery ensured; however, the data integrity is not

ensured. This is good for streaming applications where

small data loss is not critical, such as audio.

For each configuration, there may be multiple

interfaces. Each interface could support a particular

mode of that configuration.

Bulk: This type of transfer method allows for large

amounts of data to be transferred with ensured data

integrity; however, the delivery timeliness is not

ensured.

Below the interface is the endpoint(s). Data is directly

moved at this level. Endpoint 0 is always a control

endpoint and, by default, when the device is on the bus,

Endpoint 0 must be available to configure the device.

Interrupt: This type of transfer provides for ensured

timely delivery for small blocks of data, plus data

integrity is ensured.

Control: This type provides device setup control.

While full-speed devices support all transfer types, low-

speed devices are limited to interrupt and control

transfers only.

FIGURE 26-11:

USB LAYERS

Device

To other Configurations (if any)

Configuration

To other Interfaces (if any)

Interface

Endpoint

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26.10.4 POWER

26.10.6 DESCRIPTORS

Power is available from the USB. The USB specifica-

tion defines the bus power requirements. Devices may

either be self-powered or bus powered. Self-powered

devices draw power from an external source, while bus

powered devices use power supplied from the bus.

There are eight different standard descriptor types, of

which five are most important for this device.

26.10.6.1 Device Descriptors

The device descriptor provides general information,

such as manufacturer, product number, serial number,

the class of the device and the number of configurations.

There is only one device descriptor.

The USB specification limits the power taken from the

bus. Refer to USB Specification 2.0, 7.2.3 for power

limits information. Note that power above one unit load

is a request and the host or hub is not obligated to

provide the extra current. Thus, a device capable of

consuming more than one unit load must be able to

maintain a low-power configuration of a one unit load or

less, if necessary.

26.10.6.2 Configuration Descriptors

The configuration descriptor provides information on the

power requirements of the device and how many different

interfaces are supported when in this configuration. There

may be more than one configuration for a device (i.e., low-

power and high-power configurations).

The USB specification also defines a Suspend mode.

In this situation, current must be limited. A device must

enter a Suspend state after 3 ms of inactivity (i.e., no

SOF tokens for 3 ms). A device entering Suspend

mode must drop current consumption within 10 ms

after Suspend. Likewise, when signaling a wake-up,

the device must signal a wake-up within 10 ms of

drawing current above the suspend limit. Refer to USB

Specification 2.0, 7.2.3 for current limit information.

26.10.6.3 Interface Descriptors

The interface descriptor details the number of endpoints

used in this interface, as well as the class of the interface.

There may be more than one interface for a configuration.

26.10.6.4 Endpoint Descriptors

The interface descriptor details the number of endpoints

used in this interface, as well as the class of the interface.

There may be more than one interface for a configuration.

26.10.5 ENUMERATION

When the device is initially attached to the bus, the host

enters an enumeration process in an attempt to identify

the device. Essentially, the host interrogates the device,

gathering information such as power consumption, data

rates and sizes, protocol and other descriptive

information; descriptors contain this information. A

typical enumeration process could be as follows:

26.10.6.5 String Descriptors

Many of the previous descriptors reference one or more

string descriptors. String descriptors provide human

readable information about the layer (Section 26.10.1

“Layered Framework”) they describe. Often these

strings show up in the host to help the user identify the

device. String descriptors are generally optional to save

memory and are encoded in a unicode format.

1. USB Reset: Reset the device, which means the

device is not configured and does not have an address

(address 0).

2. Get Device Descriptor: The host requests a small

portion of the device descriptor.

26.10.7 BUS SPEED

Each USB device must indicate its bus presence and

speed to the host. This is accomplished through a pull-

up, which is connected to the bus at the time of the

attachment event. Depending on the speed of the

device, the pull-up connects either the D+ or D- line to

3.3V. For a low-speed device, the pull-up is connected

to the D- line. For a full-speed device, the pull-up is

connected to the D+ line.

3. USB Reset: Reset the device again.

4. Set Address: The host assigns an address to the

device.

5. Get Device Descriptor: The host retrieves the device

descriptor, gathering info such as manufacturer, type of

device, maximum control packet size.

6. Get configuration descriptors.

7. Get any other descriptors.

26.10.8 CLASS SPECIFICATION AND

DRIVERS SPEED

8. Set a configuration.

USB specifications include class specifications, which

operating system vendors optionally support. Examples

of classes include Audio, Mass Storage, Communications

and Human Interface (HID). In most cases, a driver is

required at the host side to ‘talk’ to the USB device. In

custom applications, a driver may need to be developed.

Fortunately, drivers are available for most common host

systems for the most common classes of devices. Thus,

these drivers can be reused.

The exact enumeration process depends on the host.

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26.11 Register Definitions: USB

REGISTER 26-1: UCON: USB CONTROL REGISTER

U-0

—

R/W-0

R-x

R/C-0

R/W-0

USBEN⁽¹⁾

R/W-0

U-0

—

PPBRST

SE0

PKTDIS

RESUME

SUSPND

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

PPBRST: Ping-Pong Buffers Reset bit

1= Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks

0= Ping-Pong Buffer Pointers not being reset

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SE0: Live Single-Ended Zero Flag bit

1= Single-ended zero active on the USB bus

0= No single-ended zero detected

PKTDIS: Packet Transfer Disable bit

1= SIE token and packet processing disabled, automatically set when a SETUP token is received

0= SIE token and packet processing enabled

USBEN: USB Module Enable bit⁽¹⁾

1= USB module and supporting circuitry enabled (device attached)

0= USB module and supporting circuitry disabled (device detached)

RESUME: Resume Signaling Enable bit

1= Resume signaling activated

0= Resume signaling disabled

SUSPND: Suspend USB bit

1= USB module and supporting circuitry in Power Conserve mode, SIE clock inactive

0= USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate

Unimplemented: Read as ‘0’

Note 1: This bit cannot be set if the USB module does not have an appropriate clock source.

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REGISTER 26-2: UCFG: USB CONFIGURATION REGISTER

R/W-0

U-0

—

R/W-0

UPUEN⁽¹⁾

R/W-0

FSEN⁽¹⁾

R/W-0

UTEYE

Reserved

PPB<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

UTEYE: USB Eye Pattern Test Enable bit

1= Eye pattern test enabled

0= Eye pattern test disabled

bit 5

bit 4

Reserved: Read as ‘0’. Maintain this bit clear

UPUEN: USB On-Chip Pull-up Enable bit⁽¹⁾

1= On-chip pull-up enabled (pull-up on D+ with FSEN = 1or D- with FSEN = 0)

0= On-chip pull-up disabled

bit 3

bit 2

Reserved: Read as ‘0’. Maintain this bit clear

FSEN: Full-Speed Enable bit⁽¹⁾

1= Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz

0= Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz

bit 1-0

PPB<1:0>: Ping-Pong Buffers Configuration bits

11= Even/Odd ping-pong buffers enabled for Endpoints 1 to 15

10= Even/Odd ping-pong buffers enabled for all endpoints

01= Even/Odd ping-pong buffer enabled for OUT Endpoint 0

00= Even/Odd ping-pong buffers disabled

Note 1: The UPUEN, and FSEN bits should never be changed while the USB module is enabled. These values

must be preconfigured prior to enabling the module.

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REGISTER 26-3: USTAT: USB STATUS REGISTER

U-0

—

R-x

PPBI⁽¹⁾

U-0

—

ENDP<3:0>

DIR

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-3

ENDP<2:0>: Encoded Number of Last Endpoint Activity bits

(represents the number of the BDT updated by the last USB transfer)

1111 = Endpoint 15

1110 = Endpoint 14

•

0001 = Endpoint 1

0000 = Endpoint 0

bit 2

bit 1

bit 0

DIR: Last BD Direction Indicator bit

1= The last transaction was an IN token

0= The last transaction was an OUT or SETUP token

PPBI: Ping-Pong BD Pointer Indicator bit⁽¹⁾

1= The last transaction was to the Odd BD bank

0= The last transaction was to the Even BD bank

Unimplemented: Read as ‘0’

Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.

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REGISTER 26-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP7)

U-0

—

U-0

—

U-0

—

R/W-0

EPSTALL⁽¹⁾

bit 0

EPHSHK EPCONDIS

EPOUTEN

EPINEN

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4

Unimplemented: Read as ‘0’

EPHSHK: Endpoint Handshake Enable bit

1= Endpoint handshake enabled

0= Endpoint handshake disabled (typically used for isochronous endpoints)

bit 3

EPCONDIS: Bidirectional Endpoint Control bit

If EPOUTEN = 1 and EPINEN = 1:

1= Disable Endpoint n from control transfers; only IN and OUT transfers allowed

0= Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed

bit 2

bit 1

bit 0

EPOUTEN: Endpoint Output Enable bit

1= Endpoint n output enabled

0= Endpoint n output disabled

EPINEN: Endpoint Input Enable bit

1= Endpoint n input enabled

0= Endpoint n input disabled

EPSTALL: Endpoint STALL Enable bit⁽¹⁾

1= Endpoint n is stalled

0= Endpoint n is not stalled

Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored.

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REGISTER 26-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH

BD31STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)

R/W-x

UOWN⁽¹⁾

R/W-x

DTS⁽²⁾

U-0

R/W-x

BC9

R/W-x

BC8

(3)

—

DTSEN

BSTALL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

UOWN: USB Own bit⁽¹⁾

1= Refer to Register 26-6.

0= The microcontroller core owns the BD and its corresponding buffer

DTS: Data Toggle Synchronization bit⁽²⁾

1= Data 1 packet

0= Data 0 packet

bit 5-4

bit 3

Unimplemented: Read as ‘0’

DTSEN: Data Toggle Synchronization Enable bit

1= Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored

except for a SETUP transaction, which is accepted even if the data toggle bits do not match

0= No data toggle synchronization is performed

bit 2

BSTALL: Buffer Stall Enable bit

1= Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the

given location (UOWN bit remains set, BD value is unchanged)

0= Buffer stall disabled

bit 1-0

BC<9:8>: Byte Count 9 and 8 bits

The byte count bits represent the number of bytes that will be transmitted for an IN token or received

during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.

Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.

2: This bit is ignored unless DTSEN = 1.

3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained as ‘0’.

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REGISTER 26-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH

BD31STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MCU)

R/W-x

U-x

—

R/W-x

PID3

R/W-x

PID2

R/W-x

PID1

R/W-x

PID0

R/W-x

BC9

R/W-x

BC8

UOWN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

UOWN: USB Own bit

1= The SIE owns the BD and its corresponding buffer

0= Refer to Register 26-5.

bit 6

Reserved: Not written by the SIE

bit 5-2

PID<3:0>: Packet Identifier bits

The received token PID value of the last transfer (IN, OUT or SETUP transactions only).

BC<9:8>: Byte Count 9 and 8 bits

bit 1-0

These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer

and the actual number of bytes transmitted on an IN transfer.

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PIC16(L)F1454/5/9

REGISTER 26-7: UIR: USB INTERRUPT STATUS REGISTER

U-0

—

R/W-0

SOFIF

R/W-0

IDLEIF⁽¹⁾

R/W-0

TRNIF⁽²⁾

R/W-0

ACTVIF⁽³⁾

R-0

UERRIF⁽⁴⁾

R/W-0

STALLIF

URSTIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

SOFIF: Start-of-Frame Token Interrupt bit

1= A Start-of-Frame token received by the SIE

0= No Start-of-Frame token received by the SIE

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

STALLIF: A STALL Handshake Interrupt bit

1= A STALL handshake was sent by the SIE

0= A STALL handshake has not been sent

IDLEIF: Idle Detect Interrupt bit⁽¹⁾

1= Idle condition detected (constant Idle state of 3 ms or more)

0= No Idle condition detected

TRNIF: Transaction Complete Interrupt bit⁽²⁾

1= Processing of pending transaction is complete; read USTAT register for endpoint information

0= Processing of pending transaction is not complete or no transaction is pending

ACTVIF: Bus Activity Detect Interrupt bit⁽³⁾

1= Activity on the D+/D- lines was detected

0= No activity detected on the D+/D- lines

UERRIF: USB Error Condition Interrupt bit⁽⁴⁾

1= An unmasked error condition has occurred

0= No unmasked error condition has occurred

URSTIF: USB Reset Interrupt bit

1= Valid USB Reset occurred; UADDR register is cleared

0= No USB Reset has occurred

Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.

2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).

3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.

4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and

cannot be set or cleared by the user.

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REGISTER 26-8: UIE: USB INTERRUPT ENABLE REGISTER

U-0

—

R/W-0

SOFIE

R/W-0

TRNIE

R/W-0

STALLIE

IDLEIE

ACTVIE

UERRIE

URSTIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

SOFIE: Start-of-Frame Token Interrupt Enable bit

1= Start-of-Frame token interrupt enabled

0= Start-of-Frame token interrupt disabled

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

STALLIE: STALL Handshake Interrupt Enable bit

1= STALL interrupt enabled

0= STALL interrupt disabled

IDLEIE: Idle Detect Interrupt Enable bit

1= Idle detect interrupt enabled

0= Idle detect interrupt disabled

TRNIE: Transaction Complete Interrupt Enable bit

1= Transaction interrupt enabled

0= Transaction interrupt disabled

ACTVIE: Bus Activity Detect Interrupt Enable bit

1= Bus activity detect interrupt enabled

0= Bus activity detect interrupt disabled

UERRIE: USB Error Interrupt Enable bit

1= USB error interrupt enabled

0= USB error interrupt disabled

URSTIE: USB Reset Interrupt Enable bit

1= USB Reset interrupt enabled

0= USB Reset interrupt disabled

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PIC16(L)F1454/5/9

REGISTER 26-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER

R/C-0

U-0

—

U-0

—

R/C-0

BTSEF

BTOEF

DFN8EF

CRC16EF

CRC5EF

PIDEF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

C = Clearable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

BTSEF: Bit Stuff Error Flag bit

1= A bit stuff error has been detected

0= No bit stuff error

bit 6-5

bit 4

Unimplemented: Read as ‘0’

BTOEF: Bus Turnaround Time-out Error Flag bit

1= Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)

0= No bus turnaround time-out

bit 3

bit 2

bit 1

bit 0

DFN8EF: Data Field Size Error Flag bit

1= The data field was not an integral number of bytes

0= The data field was an integral number of bytes

CRC16EF: CRC16 Failure Flag bit

1= The CRC16 failed

0= The CRC16 passed

CRC5EF: CRC5 Host Error Flag bit

1= The token packet was rejected due to a CRC5 error

0= The token packet was accepted

PIDEF: PID Check Failure Flag bit

1= PID check failed

0= PID check passed

DS41639A-page 334

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PIC16(L)F1454/5/9

REGISTER 26-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER

R/W-0

U-0

—

U-0

—

R/W-0

PIDEE

BTSEE

BTOEE

DFN8EE

CRC16EE

CRC5EE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

BTSEE: Bit Stuff Error Interrupt Enable bit

1= Bit stuff error interrupt enabled

0= Bit stuff error interrupt disabled

bit 6-5

bit 4

Unimplemented: Read as ‘0’

BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit

1= Bus turnaround time-out error interrupt enabled

0= Bus turnaround time-out error interrupt disabled

bit 3

bit 2

bit 1

bit 0

DFN8EE: Data Field Size Error Interrupt Enable bit

1= Data field size error interrupt enabled

0= Data field size error interrupt disabled

CRC16EE: CRC16 Failure Interrupt Enable bit

1= CRC16 failure interrupt enabled

0= CRC16 failure interrupt disabled

CRC5EE: CRC5 Host Error Interrupt Enable bit

1= CRC5 host error interrupt enabled

0= CRC5 host error interrupt disabled

PIDEE: PID Check Failure Interrupt Enable bit

1= PID check failure interrupt enabled

0= PID check failure interrupt disabled

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 335

PIC16(L)F1454/5/9

(1)

TABLE 26-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION

Details on

Page:

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR2

GIE

OSFIF

OSFIE

—

PEIE

C2IF

TMR0IE

C1IF

C1IE

SE0

INTE

—

IOCIE

BCL1IF

BCL1IE

USBEN

TMR0IF

USBIF

INTF

ACTIF

IOCIF

—

96

100

98

PIE2

C2IE

—

USBIE

ACTIE

—

UCON

UCFG

PPBRST

PKTDIS

RESUME

SUSPND

—

326

327

—

UTEYE

—

Reserved

UPUEN

Reserved

FSEN

DIR

PPB<1:0>

USTAT

UADDR

UFRML

UFRMH

UIR

ENDP<3:0>

PPBI

—

328

312

312*

332

333

334

335

329

—

ADDR6

FRM6

—

ADDR5

ADDR4

FRM4

—

ADDR3

FRM3

ADDR2

FRM2

ADDR1

FRM1

ADDR0

FRM0

FRM7

—

FRM5

—

FRM10

ACTVIF

ACTVIE

CRC16EF

CRC16EE

FRM9

FRM8

—

SOFIF

SOFIE

—

STALLIF

IDLEIF

IDLEIE

BTOEF

BTOEE

TRNIF

TRNIE

DFN8EF

DFN8EE

UERRIF

UERRIE

CRC5EF

CRC5EE

EPINEN

URSTIF

URSTIE

PIDEF

UIE

—

STALLIE

UEIR

BTSEF

BTSEE

—

UEIE

—

PIDEE

UEP0

UEP1

UEP2

UEP3

UEP4

UEP5

UEP6

UEP7

Legend:

—

EPHSHK EPCONDIS EPOUTEN

EPSTALL

—

— = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.

*

Page provides register information.

Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer

Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 26-3.

DS41639A-page 336

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

27.3 Common Programming Interfaces

27.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

Connection to a target device is typically done through

an ICSP header. A commonly found connector on

development tools is the RJ-11 in the 6P6C (6-pin, 6

connector) configuration. See Figure 27-1.

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP

programming:

FIGURE 27-1:

ICD RJ-11 STYLE

CONNECTOR INTERFACE

• ICSPCLK

• ICSPDAT

• MCLR/VPP

• VDD

ICSPDAT

• VSS

NC

2 4 6

VDD

In Program/Verify mode the program memory, user IDs

and the Configuration Words are programmed through

serial communications. The ICSPDAT pin is a bidirec-

tional I/O used for transferring the serial data and the

ICSPCLK pin is the clock input. For more information on

ICSP refer to the “PIC16(L)F145X Memory Programming

Specification” (DS41620).

ICSPCLK

1 3

5

Target

PC Board

Bottom Side

VPP/MCLR

VSS

Pin Description

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

27.1 High-Voltage Programming Entry

Mode

The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT

pins low then raising the voltage on MCLR/VPP to VIHH.

5 = ICSPCLK

6 = No Connect

27.2 Low-Voltage Programming Entry

Mode

Another connector often found in use with the PICkit™

programmers is a standard 6-pin header with 0.1 inch

spacing. Refer to Figure 27-2.

The Low-Voltage Programming Entry mode allows the

PIC^®Flash MCUs to be programmed using VDD only,

without high voltage. When the LVP bit of Configuration

Words is set to ‘1’, the low-voltage ICSP programming

entry is enabled. To disable the Low-Voltage ICSP

mode, the LVP bit must be programmed to ‘0’.

Entry into the Low-Voltage Programming Entry mode

requires the following steps:

1. MCLR is brought to VIL.

2.

A

32-bit key sequence is presented on

ICSPDAT, while clocking ICSPCLK.

Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mode is to be

maintained.

If low-voltage programming is enabled (LVP = 1), the

MCLR Reset function is automatically enabled and

cannot be disabled. See Section 6.5 “MCLR” for more

information.

The LVP bit can only be reprogrammed to ‘0’ by using

the High-Voltage Programming mode.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 337

PIC16(L)F1454/5/9

FIGURE 27-2:

PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE

Pin 1 Indicator

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

1

2

3

4

5

6

5 = ICSPCLK

6 = No Connect

*

The 6-pin header (0.100" spacing) accepts 0.025" square pins.

For additional interface recommendations, refer to your

specific device programmer manual prior to PCB

design.

It is recommended that isolation devices be used to

separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific

application and may include devices such as resistors,

diodes, or even jumpers. See Figure 27-3 for more

information.

FIGURE 27-3:

TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

External

Programming

Signals

Device to be

Programmed

VDD

VPP

VSS

MCLR/VPP

VSS

Data

ICSPDAT

ICSPCLK

Clock

*

To Normal Connections

Isolation devices (as required).

*

DS41639A-page 338

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

28.1 Read-Modify-Write Operations

28.0 INSTRUCTION SET SUMMARY

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

Each PIC16 instruction is a 14-bit word containing the

operation code (opcode) and all required operands.

The op codes are broken into three broad categories.

• Byte Oriented

• Bit Oriented

• Literal and Control

The literal and control category contains the most var-

ied instruction word format.

TABLE 28-1: OPCODE FIELD

DESCRIPTIONS

Table 28-3 lists the instructions recognized by the

MPASM^TMassembler.

Field

Description

All instructions are executed within a single instruction

cycle, with the following exceptions, which may take

two or three cycles:

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

• Subroutine takes two cycles (CALL, CALLW)

• Returns from interrupts or subroutines take two

cycles (RETURN, RETLW, RETFIE)

k

x

Don’t care location (= 0or 1).

• Program branching takes two cycles (GOTO, BRA,

BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)

• One additional instruction cycle will be used when

any instruction references an indirect file register

and the file select register is pointing to program

memory.

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

One instruction cycle consists of 4 oscillator cycles; for

an oscillator frequency of 4 MHz, this gives a nominal

instruction execution rate of 1 MHz.

n

FSR or INDF number. (0-1)

mm

Pre-post increment-decrement mode

selection

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

TABLE 28-2: ABBREVIATION

DESCRIPTIONS

Field

Description

PC

TO

C

Program Counter

Time-out bit

Carry bit

DC

Z

Digit carry bit

Zero bit

PD

Power-down bit

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 339

PIC16(L)F1454/5/9

FIGURE 28-1:

GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13

8

7

6

0

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9

7 6

0

OPCODE

b (BIT #)

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

General

13

8

7

0

OPCODE

k (literal)

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

0

k (literal)

k = 11-bit immediate value

MOVLPinstruction only

13

7

6

0

OPCODE

k (literal)

k = 7-bit immediate value

MOVLBinstruction only

13

5 4

OPCODE

k (literal)

k = 5-bit immediate value

BRAinstruction only

13

9

8

0

OPCODE

k (literal)

k = 9-bit immediate value

FSR Offset instructions

13

7

6

5

0

OPCODE

n

k (literal)

n = appropriate FSR

k = 6-bit immediate value

FSRIncrement instructions

13

3

2

n

1

OPCODE

m (mode)

n = appropriate FSR

m = 2-bit mode value

OPCODE only

13

0

OPCODE

DS41639A-page 340

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PIC16(L)F1454/5/9

TABLE 28-3: PIC16(L)F1454/5/9 ENHANCED INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC f, d

ANDWF

ASRF

LSLF

f, d

Add W and f

Add with Carry W and f

AND W with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

Clear W

Complement f

Decrement f

Increment f

Inclusive OR W with f

Move f

Move W to f

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Subtract with Borrow W from f

Swap nibbles in f

Exclusive OR W with f

1

00 0111 dfff ffff C, DC, Z

11 1101 dfff ffff C, DC, Z

00 0101 dfff ffff Z

11 0111 dfff ffff C, Z

11 0101 dfff ffff C, Z

11 0110 dfff ffff C, Z

2

f, d

f

LSRF

CLRF

CLRW

COMF

DECF

INCF

IORWF

MOVF

MOVWF

RLF

RRF

SUBWF

SUBWFB f, d

SWAPF

XORWF

00 0001 lfff ffff

00 0001 0000 00xx

00 1001 dfff ffff

00 0011 dfff ffff

00 1010 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 1fff ffff

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

f, d

2

C

00 0010 dfff ffff C, DC, Z

11 1011 dfff ffff C, DC, Z

00 1110 dfff ffff

f, d

00 0110 dfff ffff

Z

BYTE ORIENTED SKIP OPERATIONS

f, d

Decrement f, Skip if 0

Increment f, Skip if 0

1(2)

00

1011 dfff ffff

1111 dfff ffff

1, 2

DECFSZ

INCFSZ

BIT-ORIENTED FILE REGISTER OPERATIONS

f, b

Bit Clear f

Bit Set f

1

01

00bb bfff ffff

01bb bfff ffff

2

BCF

BSF

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS

f, b

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

01

10bb bfff ffff

11bb bfff ffff

1, 2

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

k

Add literal and W

AND literal with W

Inclusive OR literal with W

Move literal to BSR

Move literal to PCLATH

Move literal to W

1

11

00

11

1110 kkkk kkkk C, DC, Z

1001 kkkk kkkk

1000 kkkk kkkk

0000 001k kkkk

0001 1kkk kkkk

0000 kkkk kkkk

Z

Subtract W from literal

Exclusive OR literal with W

1100 kkkk kkkk C, DC, Z

1010 kkkk kkkk

Z

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one

additional instruction cycle.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 341

PIC16(L)F1454/5/9

TABLE 28-3: PIC16(L)F1454/5/9 ENHANCED INSTRUCTION SET (CONTINUED)

14-Bit Opcode

Mnemonic,

Status

Affected

Description

Cycles

Notes

Operands

MSb

LSb

CONTROL OPERATIONS

BRA

BRW

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN

k

–

k

–

k

–

Relative Branch

Relative Branch with W

Call Subroutine

Call Subroutine with W

Go to address

Return from interrupt

Return with literal in W

Return from Subroutine

2

11

00

10

00

10

00

11

00

001k kkkk kkkk

0000 0000 1011

0kkk kkkk kkkk

0000 0000 1010

1kkk kkkk kkkk

0000 0000 1001

0100 kkkk kkkk

0000 0000 1000

INHERENT OPERATIONS

CLRWDT

NOP

OPTION

RESET

SLEEP

TRIS

–

f

Clear Watchdog Timer

No Operation

Load OPTION_REG register with W

Software device Reset

Go into Standby mode

Load TRIS register with W

1

00

0000 0110 0100 TO, PD

0000 0000 0000

0000 0110 0010

0000 0000 0001

0000 0110 0011 TO, PD

0000 0110 0fff

C-COMPILER OPTIMIZED

ADDFSR n, k

Add Literal k to FSRn

Move Indirect FSRn to W with pre/post inc/dec

modifier, mm

1

11 0001 0nkk kkkk

00 0000 0001 0nmm

kkkk

MOVIW

n mm

Z

2, 3

k[n]

n mm

Move INDFn to W, Indexed Indirect.

Move W to Indirect FSRn with pre/post inc/dec

modifier, mm

1

11 1111 0nkk 1nmm

00 0000 0001 kkkk

2

2, 3

MOVWI

k[n]

Move W to INDFn, Indexed Indirect.

1

11 1111 1nkk

2

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

3: See Table in the MOVIW and MOVWI instruction descriptions.

DS41639A-page 342

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PIC16(L)F1454/5/9

28.2 Instruction Descriptions

ADDFSR

Add Literal to FSRn

ANDLW

AND literal with W

Syntax:

[ label ] ADDFSR FSRn, k

Syntax:

[ label ] ANDLW

0  k  255

k

Operands:

-32  k  31

n  [ 0, 1]

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k)  (W)

Operation:

FSR(n) + k  FSR(n)

Z

Status Affected:

Description:

None

The contents of W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W register.

The signed 6-bit literal ‘k’ is added to

the contents of the FSRnH:FSRnL

register pair.

FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds

will cause the FSR to wrap around.

ANDWF

AND W with f

ADDLW

Add literal and W

Syntax:

[ label ] ANDWF f,d

Syntax:

[ label ] ADDLW

0  k  255

k

Operands:

0  f  127

d 0,1

Operands:

Operation:

Status Affected:

Description:

(W) + k  (W)

C, DC, Z

Operation:

(W) .AND. (f)  (destination)

Status Affected:

Description:

Z

The contents of the W register are

added to the eight-bit literal ‘k’ and the

result is placed in the W register.

AND the W register with register ‘f’. If

‘d’ is ‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

ASRF

Arithmetic Right Shift

ADDWF

Add W and f

Syntax:

[ label ] ASRF f {,d}

Syntax:

[ label ] ADDWF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d 0,1

Operation:

(f<7>) dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Operation:

(W) + (f)  (destination)

Status Affected:

Description:

C, DC, Z

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the result is

stored in the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. The MSb remains unchanged. If

‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in reg-

ister ‘f’.

ADDWFC

ADD W and CARRY bit to f

C

register f

Syntax:

[ label ] ADDWFC

f {,d}

Operands:

0  f  127

d [0,1]

Operation:

(W) + (f) + (C)  dest

Status Affected:

Description:

C, DC, Z

Add W, the Carry flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 343

PIC16(L)F1454/5/9

BTFSC

Bit Test f, Skip if Clear

BCF

Bit Clear f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] BCF f,b

Operands:

0  f  127

0  b  7

Operands:

0  f  127

0  b  7

Operation:

skip if (f<b>) = 0

Operation:

0 (f<b>)

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

Bit ‘b’ in register ‘f’ is cleared.

If bit ‘b’, in register ‘f’, is ‘0’, the next

instruction is discarded, and a NOPis

executed instead, making this a

2-cycle instruction.

BTFSS

Bit Test f, Skip if Set

BRA

Relative Branch

Syntax:

[ label ] BTFSS f,b

Syntax:

[ label ] BRA label

[ label ] BRA $+k

Operands:

0  f  127

0  b < 7

Operands:

-256  label - PC + 1  255

-256  k  255

Operation:

skip if (f<b>) = 1

Operation:

(PC) + 1 + k  PC

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOPis

executed instead, making this a

2-cycle instruction.

Add the signed 9-bit literal ‘k’ to the

PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + k.

This instruction is a two-cycle instruc-

tion. This branch has a limited range.

BRW

Relative Branch with W

Syntax:

[ label ] BRW

None

Operands:

Operation:

Status Affected:

Description:

(PC) + (W)  PC

None

Add the contents of W (unsigned) to

the PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + (W).

This instruction is a two-cycle instruc-

tion.

BSF

Bit Set f

Syntax:

[ label ] BSF f,b

Operands:

0  f  127

0  b  7

Operation:

1 (f<b>)

Status Affected:

Description:

None

Bit ‘b’ in register ‘f’ is set.

DS41639A-page 344

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

CALL

Call Subroutine

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CALL

0  k  2047

k

Syntax:

[ label ] CLRWDT

Operands:

Operation:

Operands:

Operation:

None

(PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

00h  WDT

0 WDT prescaler,

1 TO

1 PD

Status Affected:

Description:

None

Status Affected:

Description:

TO, PD

Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.

The eleven-bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALLis a two-cycle instruc-

tion.

CLRWDTinstruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT.

Status bits TO and PD are set.

COMF

Complement f

CALLW

Subroutine Call With W

Syntax:

[ label ] COMF f,d

Syntax:

[ label ] CALLW

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

None

(PC) +1  TOS,

(W)  PC<7:0>,

Operation:

(f)  (destination)

(PCLATH<6:0>) PC<14:8>

Status Affected:

Description:

Z

The contents of register ‘f’ are com-

plemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Status Affected:

Description:

None

Subroutine call with W. First, the

return address (PC + 1) is pushed

onto the return stack. Then, the con-

tents of W is loaded into PC<7:0>,

and the contents of PCLATH into

PC<14:8>. CALLWis a two-cycle

instruction.

DECF

Decrement f

CLRF

Clear f

Syntax:

[ label ] DECF f,d

Syntax:

[ label ] CLRF

0  f  127

f

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

00h  (f)

1 Z

Operation:

(f) - 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

The contents of register ‘f’ are cleared

and the Z bit is set.

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h  (W)

1 Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z) is

set.

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Preliminary

DS41639A-page 345

PIC16(L)F1454/5/9

DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - 1  (destination);

skip if result = 0

Operation:

(f) + 1  (destination),

skip if result = 0

Status Affected:

Description:

None

Status Affected:

Description:

None

The contents of register ‘f’ are decre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, then a

NOPis executed instead, making it a

2-cycle instruction.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, a NOPis

executed instead, making it a 2-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO

0  k  2047

k

Syntax:

[ label ] IORLW

0  k  255

(W) .OR. k  (W)

Z

k

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k  PC<10:0>

PCLATH<4:3>  PC<12:11>

Status Affected:

Description:

None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’. The

result is placed in the W register.

GOTOis an unconditional branch. The

eleven-bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTOis a two-cycle instruction.

INCF

Increment f

IORWF

Inclusive OR W with f

Syntax:

[ label ] INCF f,d

Syntax:

[ label ] IORWF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) + 1  (destination)

Operation:

(W) .OR. (f)  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

Inclusive OR the W register with regis-

ter ‘f’. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

DS41639A-page 346

Preliminary

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PIC16(L)F1454/5/9

LSLF

Logical Left Shift

MOVF

Move f

Syntax:

[ label ] LSLF f {,d}

Syntax:

[ label ] MOVF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f<7>)  C

Operation:

(f)  (dest)

(f<6:0>)  dest<7:1>

0  dest<0>

Status Affected:

Description:

Z

The contents of register f is moved to

a destination dependent upon the

status of d. If d = 0,

destination is W register. If d = 1, the

destination is file register f itself. d = 1

is useful to test a file register since

status flag Z is affected.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the left through the Carry flag.

A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,

the result is placed in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Words:

1

C

register f

0

Cycles:

Example:

MOVF

FSR, 0

After Instruction

LSRF

Logical Right Shift

W

Z

=

value in FSR register

1

Syntax:

[ label ] LSRF f {,d}

Operands:

0  f  127

d [0,1]

Operation:

0  dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. A ‘0’ is shifted into the MSb. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is stored back in register ‘f’.

0

C

register f

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 347

PIC16(L)F1454/5/9

MOVIW

Move INDFn to W

MOVLP

Move literal to PCLATH

Syntax:

[ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

Syntax:

[ label ] MOVLP

0  k  127

k  PCLATH

None

k

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

The seven-bit literal ‘k’ is loaded into the

PCLATH register.

INDFn  W

Effective address is determined by

• FSR + 1 (preincrement)

• FSR - 1 (predecrement)

• FSR + k (relative offset)

After the Move, the FSR value will be

either:

• FSR + 1 (all increments)

• FSR - 1 (all decrements)

• Unchanged

MOVLW

Move literal to W

Syntax:

[ label ] MOVLW

0  k  255

k  (W)

k

Operands:

Operation:

Status Affected:

Description:

None

The eight-bit literal ‘k’ is loaded into W

register. The “don’t cares” will assem-

ble as ‘0’s.

Status Affected:

Z

Words:

1

Cycles:

Example:

Mode

Syntax

mm

00

01

10

11

MOVLW

0x5A

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

After Instruction

W

=

0x5A

MOVWF

Move W to f

[ label ] MOVWF

0  f  127

(W)  (f)

Syntax:

f

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Operands:

Operation:

Status Affected:

Description:

None

Move data from W register to register

‘f’.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

Words:

1

Cycles:

Example:

MOVWF

Before Instruction

OPTION_REG = 0xFF

OPTION_REG

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

W

= 0x4F

After Instruction

OPTION_REG = 0x4F

= 0x4F

W

MOVLB

Move literal to BSR

Syntax:

[ label ] MOVLB

0  k  15

k  BSR

None

k

Operands:

Operation:

Status Affected:

Description:

The five-bit literal ‘k’ is loaded into the

Bank Select Register (BSR).

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Preliminary

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PIC16(L)F1454/5/9

NOP

No Operation

MOVWI

Move W to INDFn

Syntax:

[ label ] NOP

Syntax:

[ label ] MOVWI ++FSRn

[ label ] MOVWI --FSRn

[ label ] MOVWI FSRn++

[ label ] MOVWI FSRn--

[ label ] MOVWI k[FSRn]

Operands:

Operation:

Status Affected:

Description:

Words:

None

No operation

None

No operation.

Operands:

Operation:

n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

1

Cycles:

1

W  INDFn

Example:

NOP

Effective address is determined by

• FSR + 1 (preincrement)

• FSR - 1 (predecrement)

• FSR + k (relative offset)

After the Move, the FSR value will be

either:

• FSR + 1 (all increments)

• FSR - 1 (all decrements)

Unchanged

Load OPTION_REG Register

with W

OPTION

Syntax:

[ label ] OPTION

None

Operands:

Operation:

Status Affected:

Description:

Status Affected:

None

(W)  OPTION_REG

None

Mode

Syntax

mm

00

01

10

11

Move data from W register to

OPTION_REG register.

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

RESET

Software Reset

Syntax:

[ label ] RESET

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Operands:

Operation:

None

Execute a device Reset. Resets the

nRI flag of the PCON register.

Status Affected:

Description:

None

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

This instruction provides a way to

execute a hardware Reset by soft-

ware.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

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Preliminary

DS41639A-page 349

PIC16(L)F1454/5/9

RETURN

Return from Subroutine

RETFIE

Syntax:

Return from Interrupt

[ label ] RETFIE

None

Syntax:

[ label ] RETURN

None

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

TOS  PC

None

TOS  PC,

1 GIE

Status Affected:

Description:

None

Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two-cycle instruction.

Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global Interrupt Enable bit,

GIE (INTCON<7>). This is a two-cycle

instruction.

Words:

1

Cycles:

Example:

2

RETFIE

After Interrupt

PC

=

TOS

GIE =

1

RETLW

Syntax:

Return with literal in W

RLF

Rotate Left f through Carry

[ label ] RETLW

0  k  255

k

Syntax:

Operands:

[ label ]

RLF f,d

Operands:

Operation:

0  f  127

d  [0,1]

k  (W);

TOS  PC

Operation:

See description below

C

Status Affected:

Description:

None

Status Affected:

Description:

The W register is loaded with the eight

bit literal ‘k’. The program counter is

loaded from the top of the stack (the

return address). This is a two-cycle

instruction.

The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Words:

1

2

C

Register f

Cycles:

Example:

CALL TABLE;W contains table

;offset value

Words:

1

Cycles:

Example:

•

;W now has table value

TABLE

RLF

REG1,0

Before Instruction

ADDWF PC ;W = offset

RETLW k1 ;Begin table

REG1

C

=

1110 0110

0

RETLW k2

;

After Instruction

•

REG1

W

C

=

1110 0110

1100 1100

1

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

DS41639A-page 350

Preliminary

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PIC16(L)F1454/5/9

SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW

0 k 255

k

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Status Affected:

Description:

Operands:

0  f  127

d  [0,1]

k - (W) W)

C, DC, Z

Operation:

See description below

C

The W register is subtracted (2’s com-

plement method) from the eight-bit

literal ‘k’. The result is placed in the W

register.

Status Affected:

Description:

The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

C = 0

W  k

C = 1

W  k

C

Register f

DC = 0

DC = 1

W<3:0>  k<3:0>

W<3:0>  k<3:0>

SUBWF

Subtract W from f

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

[ label ] SUBWF f,d

Syntax:

Operands:

0 f 127

d  [0,1]

Operands:

Operation:

00h  WDT,

0 WDT prescaler,

1 TO,

Operation:

(f) - (W) destination)

Status Affected:

Description:

C, DC, Z

0 PD

Subtract (2’s complement method) W

register from register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO is

set. Watchdog Timer and its

prescaler are cleared.

C = 0

W  f

The processor is put into Sleep mode

with the oscillator stopped.

C = 1

W  f

DC = 0

DC = 1

W<3:0>  f<3:0>

W<3:0>  f<3:0>

SUBWFB

Subtract W from f with Borrow

Syntax:

SUBWFB f {,d}

Operands:

0  f  127

d  [0,1]

Operation:

(f) – (W) – (B) dest

Status Affected:

Description:

C, DC, Z

Subtract W and the BORROW flag

(CARRY) from register ‘f’ (2’s comple-

ment method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 351

PIC16(L)F1454/5/9

SWAPF

Swap Nibbles in f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORLW

0 k 255

k

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k W)

Z

Operation:

(f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

The contents of the W register are

XOR’ed with the eight-bit

literal ‘k’. The result is placed in the

W register.

Status Affected:

Description:

None

The upper and lower nibbles of regis-

ter ‘f’ are exchanged. If ‘d’ is ‘0’, the

result is placed in the W register. If ‘d’

is ‘1’, the result is placed in register ‘f’.

XORWF

Exclusive OR W with f

TRIS

Load TRIS Register with W

Syntax:

[ label ] XORWF f,d

Syntax:

[ label ] TRIS f

5  f  7

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

(W)  TRIS register ‘f’

None

Operation:

(W) .XOR. (f) destination)

Status Affected:

Description:

Z

Move data from W register to TRIS

register.

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

When ‘f’ = 7, TRISC is loaded.

Exclusive OR the contents of the W

register with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in regis-

ter ‘f’.

DS41639A-page 352

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

29.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS, PIC16LF1454/5/9 ..................................................................... -0.3V to +6.5V

Voltage on VDD with respect to VSS, PIC16LF1454/5/9 ..................................................................... -0.3V to +4.0V

Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾...............................................................................................................................800 mW

Maximum current out of VSS pin, -40°C  TA  +85°C for industrial............................................................... 396 mA

Maximum current out of VSS pin, -40°C  TA  +125°C for extended ............................................................ 114 mA

Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 292 mA

Maximum current into VDD pin, -40°C  TA  +125°C for extended............................................................... 107 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x

IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 353

PIC16(L)F1454/5/9

FIGURE 29-1:

PIC16F1454/5/9 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

5.5

2.7

2.3

0

10

20

40

48

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 29-1 for each Oscillator mode’s supported frequencies.

FIGURE 29-2:

PIC16LF1454/5/9 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

3.6

2.7

1.8

0

10

20

40

48

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 29-1 for each Oscillator mode’s supported frequencies.

DS41639A-page 354

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

29.1 DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1454/5/9

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1454/5/9

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param.

No.

Sym.

Characteristic

Min. Typ† Max.

Units

Conditions

D001

VDD

Supply Voltage (VDDMIN, VDDMAX)

PIC16LF1454/5/9 1.8

—

3.6

V

FOSC  20 MHz

FOSC  48 MHz

2.5

D001

PIC16F1454/5/9 2.3

2.5

—

5.5

V

FOSC  20 MHz

FOSC  48 MHz

D002*

VDR

RAM Data Retention Voltage⁽¹⁾

PIC16LF1454/5/9 1.5

PIC16F1454/5/9 1.7

—

V

Device in Sleep mode

D002*

D002A VPOR*

Power-on Reset Release Voltage

PIC16LF1454/5/9

PIC16F1454/5/9

Power-on Reset Rearm Voltage

—

1.6

1.7

—

V

D002A

D002B VPORR*

PIC16LF1454/5/9

PIC16F1454/5/9

—

0.8

—

V

D002B

1.65

D003

VADFVR

Fixed Voltage Reference Voltage for

ADC, Initial Accuracy

—

1

—

%

1.024V, VDD  2.5V, 85°C (NOTE 2)

1.024V, VDD  2.5V, 125°C (NOTE 2)

2.048V, VDD  2.5V, 85°C

2.048V, VDD  2.5V, 125°C

4.096V, VDD  4.75V, 85°C

4.096V, VDD  4.75V, 125°C

D003C* TCVFVR

Temperature Coefficient, Fixed

Voltage Reference

—

-130

0.270

—

ppm/°C

%/V

D003D* VFVR/

VIN

Line Regulation, Fixed Voltage

Reference

—

D004*

SVDD

VDD Rise Rate to ensure internal

Power-on Reset signal

0.05

V/ms See Section 6.1 “Power-On Reset

(POR)” for details.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

2: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting

the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or

greater.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 355

PIC16(L)F1454/5/9

FIGURE 29-3:

POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR

POR REARM

VSS

(3)

(2)

TPOR

TVLOW

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

DS41639A-page 356

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

29.2 DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1454/5/9

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1454/5/9

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Device

Min.

Typ†

Max.

Units

No.

Characteristics

VDD

Note

Supply Current (IDD)^{(1, 2)}

D010

—

2

—

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

FOSC = 32 kHz LP Oscillator mode

4

16

19

D011

40

FOSC = 1 MHz XT Oscillator mode

80

110

130

160

120

220

230

300

350

30

D012

FOSC = 4 MHz XT Oscillator mode

D013

FOSC = 1 MHz

EC Oscillator mode, Medium-power mode

50

75

FOSC = 1 MHz

EC Oscillator mode

Medium-power mode

100

115

100

180

D014

FOSC = 4 MHz

EC Oscillator mode,

Medium-power mode

—

225

300

350

2.3

4.0

23

—

A

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

FOSC = 4 MHz

EC Oscillator mode

Medium-power mode

D015

FOSC = 31 kHz

LFINTOSC mode

FOSC = 31 kHz

LFINTOSC mode

46

145

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 357

PIC16(L)F1454/5/9

29.2 DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1454/5/9

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1454/5/9

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Device

Characteristics

Min.

Typ†

Max.

Units

No.

VDD

Note

D016

—

220

280

340

410

535

380

560

720

920

1017

520

810

1000

1300

1600

750

—

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

3.0

FOSC = 500 kHz HFINTOSC mode

D016

FOSC = 500 kHz HFINTOSC mode

D017*

FOSC = 8 MHz

HFINTOSC mode

FOSC = 8 MHz

HFINTOSC mode

D018

FOSC = 16 MHz

HFINTOSC mode

FOSC = 16 MHz

HFINTOSC mode

D019A

FOSC = 20 MHz

ECH mode

—

1400

1600

6

—

A

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

FOSC = 20 MHz

ECH mode

D019B

FOSC = 32 kHz ECL mode

8

11

FOSC = 32 kHz ECL mode

15

18

D019C

15

FOSC = 500 kHz ECL mode

20

35

45

55

D020

150

280

230

310

370

FOSC = 4 MHz EXTRC mode (Note 3)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

DS41639A-page 358

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

29.2 DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1454/5/9

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1454/5/9

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Device

Characteristics

Min.

Typ†

Max.

Units

No.

VDD

Note

D021

—

1000

1350

1700

—

A

3.0

5.0

FOSC = 20 MHz HS Oscillator mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 359

PIC16(L)F1454/5/9

29.3 DC Characteristics: PIC16(L)F1454/5/9-I/E (Power-Down)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1454/5/9

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1454/5/9

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Max.

Device Characteristics

Min.

Typ†

Units

No.

+85°C +125°C

VDD

Note

Power-down Current (IPD)⁽²⁾

D022

—

0.025

0.035

—

A

1.8

3.0

Base Current: WDT, BOR, FVR,

and SOSC disabled, all Peripher-

als inactive

D022

—

0.20

0.25

0.30

10

—

A

2.3

3.0

5.0

2.3

3.0

5.0

WDT, BOR, FVR, and SOSC dis-

abled, all Peripherals inactive

(VREGPM = 1; Low-Power mode)

D022A

Base Current: WDT, BOR, FVR

and SOSC disabled, all peripheral

inactive (VREGPM = 0; Normal

Power mode)

11

12

D023

—

0.29

0.39

10.5

11.3

12.5

14

—

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

3.0

5.0

3.0

5.0

LPWDT Current (Note 1)

D023A

FVR current (Note 1)

23

30

34

D024

7

BOR Current (Note 1)

15

17

D24A

0.1

11

LPBOR Current (Note 1)

12

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: A/D oscillator source is FRC.

DS41639A-page 360

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

29.3 DC Characteristics: PIC16(L)F1454/5/9-I/E (Power-Down) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1454/5/9

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1454/5/9

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Max.

Device Characteristics

Min.

Typ†

Units

No.

+85°C +125°C

VDD

Note

D025

—

0.6

1.8

11

—

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

SOSC Current (Note 1)

D025

SOSC Current (Note 1)

13

19

D026

.025

.035

10

A/D Current (Note 1, Note 3), no

conversion in progress

A/D Current (Note 1, Note 3), no

conversion in progress

11

12

D026A*

250

280

7

A/D Current (Note 1, Note 3),

conversion in progress

A/D Current (Note 1, Note 3),

conversion in progress

D027

Comparator, Low-Power mode

(Note 1)

8

17

Comparator, Low-Power mode

(Note 1)

18

19

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: A/D oscillator source is FRC.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 361

PIC16(L)F1454/5/9

29.4 DC Characteristics: PIC16(L)F1454/5/9-I/E

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O PORT:

D030

D030A

D031

with TTL buffer

—

0.8

V

4.5V  VDD  5.5V

0.15 VDD

0.2 VDD

0.8

1.8V  VDD  4.5V

2.0V  VDD  5.5V

3.0 VDD

with Schmitt Trigger buffer

with SMBus

D032

MCLR

0.2 VDD

VIH

Input High Voltage

I/O ports:

D040

with TTL buffer

2.0

—

V

4.5V  VDD 5.5V

1.8V  VDD  4.5V

D040A

0.25 VDD +

0.8

D041

D042

D060

with Schmitt Trigger buffer

with SMBus

0.8 VDD

2.1

—

VDD

—

V

2.0V  VDD  5.5V

3.0 VDD

MCLR

0.8 VDD

IIL

Input Leakage Current⁽¹⁾

I/O ports

—

± 5

± 125

nA

VSS  VPIN  VDD, Pin at high-

impedance at 85°C

± 5

± 1000

± 200

nA 125°C

D061

MCLR⁽²⁾

± 50

nA

A

V

VSS  VPIN  VDD at 85°C

IPUR

VOL

Weak Pull-up Current

D070*

25

100

140

200

300

VDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS

Output Low Voltage⁽³⁾

D080

D090

I/O ports

IOL = 8mA, VDD = 5V

IOL = 6mA, VDD = 3.3V

IOL = 1.8mA, VDD = 1.8V

—

0.6

VOH

Output High Voltage⁽³⁾

I/O ports

IOH = 3.5mA, VDD = 5V

IOH = 3mA, VDD = 3.3V

IOH = 1mA, VDD = 1.8V

VDD - 0.7

—

V

Capacitive Loading Specs on Output Pins

All I/O pins

These parameters are characterized but not tested.

D101A* CIO

—

50

pF

*

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Negative current is defined as current sourced by the pin.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Including OSC2 in CLKOUT mode.

DS41639A-page 362

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

29.5 Memory Programming Requirements

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

DC CHARACTERISTICS

Param

Sym.

No.

Characteristic

Program Memory

Min.

Typ†

Max.

Units

Conditions

Programming Specifications

D110

D111

VIHH

IDDP

Voltage on MCLR/VPP pin

8.0

—

9.0

10

V

(Note 2)

Supply Current during

Programming

mA

D112

D113

VBE

VDD for Bulk Erase

2.7

—

VDDMAX

V

VPEW

VDD for Write or Row Erase

VDDMIN

D114

IPPPGM Current on MCLR/VPP during

Erase/Write

—

1.0

—

mA

D115

IDDPGM Current on VDD during Erase/

Write

—

5.0

—

mA

Program Flash Memory

—

2

D121

D122

D123

D124

EP

Cell Endurance

10K

VDDMIN

—

VDDMAX

2.5

E/W -40C to +85C (Note 1)

VPRW

TIW

VDD for Read/Write

Self-timed Write Cycle Time

V

ms

TRETD Characteristic Retention

—

40

—

Year Provided no other

specifications are violated

D125

EHEFC High-Endurance Flash Cell

100K

—

E/W 0°C to +60°C lower byte,

last 128 addresses

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Self-write and Block Erase.

2: Required only if single-supply programming is disabled.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 363

PIC16(L)F1454/5/9

29.6 USB Module Specifications

Operating Conditions-40°C  TA  +85°C (unless otherwise state)

Param

Sym

Characteristic

Min

Typ

Max Units

Conditions

No.

D313

VUSB

USB Voltage

3.0

—

3.6

V

Voltage on VUSB3V3 pin must be

in this range for proper USB

operation

D314

D315

D316

D318

IIL

Input Leakage on pin

—

± 1

0.8

—

A VSS VPIN VDD pin athigh

impedance

VILUSB Input Low Voltage for USB

Buffer

V

For VUSB3V3 range

VIHUSB Input High Voltage for USB

Buffer

2.0

—

VDIFS Differential Input Sensitivity

0.2

The difference between D+ and

D- must exceed this value while

VCM is met

D319

VCM

Differential Common Mode

Range

0.8

—

2.5

V

D320

D321

D322

ZOUT

VOL

Driver Output Impedance⁽¹⁾

28

0.0

2.8

—

44

0.3

3.6



V

Voltage Output Low

1.5 kload connected to 3.6V

1.5 kload connected to ground

VOH

Voltage Output High

Note 1: The D+ and D- signal lines have been built-in impedance matching resistors. No external resistors,

capacitors or magnetic components are necessary on the D+/D- signal paths between the

PIC16(L)F1454/5/9 family device and USB cable.

DS41639A-page 364

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

29.7 Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No.

Sym.

Characteristic

Typ.

Units

Conditions

14-Pin PDIP package

TH01

JA

Thermal Resistance Junction to Ambient

70

C/W

95.3

100

45.7

14-Pin SOIC package

14-Pin TSSOP package

16-Pin QFN 4x4mm package

62.2

77.7

87.3

43.0

32

C/W

20-pin PDIP package

20-pin SOIC package

20-pin SSOP package

20-pin QFN 4x4mm package

TH02

JC

Thermal Resistance Junction to Case

14-Pin PDIP package

31

C/W

14-Pin SOIC package

24.4

6.3

14-Pin TSSOP package

16-Pin QFN 4x4mm package

27.5

20-pin PDIP package

23.1

31.1

5.3

150

—

C/W

C

20-pin SOIC package

20-pin SSOP package

20-pin QFN 4x4mm package

TH03

TH04

TH05

TH06

TH07

TJMAX

PD

Maximum Junction Temperature

Power Dissipation

W

PD = PINTERNAL + PI/O

(1)

PINTERNAL Internal Power Dissipation

—

W

PINTERNAL = IDD x VDD

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

(2)

PDER

—

W

PDER = PDMAX (TJ - TA)/JA

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature

3: TJ = Junction Temperature

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 365

PIC16(L)F1454/5/9

29.8

Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

CLKIN

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCKx

SS

SDIx

do

dt

SDO

Data in

I/O PORT

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 29-4:

LOAD CONDITIONS

Load Condition

CL

VSS

Legend: CL = 50 pF for all pins

DS41639A-page 366

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

29.9 AC Characteristics: PIC16(L)F1454/5/9-I/E

FIGURE 29-5:

CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

CLKIN

OS12

OS03

OS11

OS02

CLKOUT

(CLKOUT Mode)

Note 1:

See Table 29-3 for timing information.

TABLE 29-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param

Sym.

No.

Characteristic

Min.

Typ†

Max.

Units

Conditions

OS01

FOSC

External CLKIN Frequency⁽¹⁾

DC

—

0.5

4

MHz EC Oscillator mode (low)

MHz EC Oscillator mode (medium)

MHz EC Oscillator mode (high)

DC

20



OS02

OS03

TOSC

TCY

External CLKIN Period⁽¹⁾

Instruction Cycle Time⁽¹⁾

31.25

125

ns

EC mode

DC

TCY = FOSC/4

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-

sumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external

clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

TABLE 29-2: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param

Sym.

No.

Characteristic

Min. Typ† Max. Units

Conditions

OS08

HFOSC

Internal Calibrated HFINTOSC Frequency⁽¹⁾

Frequency Tolerance

—

16.0

± 3

± 6

31

—

8

MHz 0°C  TA  +85°C

OS08A HFTOL

%

+25°C, 16 MHz

0°C  TA  +85°C, 16 MHz

OS09

LFOSC

Internal LFINTOSC Frequency

kHz -40°C  TA  +125°C

s

OS10* TIOSC ST

HFINTOSC

5

Wake-up from Sleep Start-up Time

OS11* TUNELOCK HFINTOSC

Self-tune Lock Time

These parameters are characterized but not tested.

—

<5

8

mS NOTE 2

*

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

2: Time for reference clock stable and in range to HFINTOSC tuned within range specified by OS08A (with Self-Tune).

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 367

PIC16(L)F1454/5/9

FIGURE 29-6:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

FOSC

OS12

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS18

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

TABLE 29-3: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

OS11 TosH2ckL FOSC to CLKOUT ⁽¹⁾

OS12 TosH2ckH FOSC to CLKOUT ⁽¹⁾

OS13 TckL2ioV CLKOUT to Port out valid⁽¹⁾

—

70

72

20

ns VDD = 3.3-5.0V

ns

—

OS14 TioV2ckH Port input valid before CLKOUT⁽¹⁾

OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid

TOSC + 200 ns

—

50

—

70*

—

ns

—

ns VDD = 3.3-5.0V

OS16 TosH2ioI

Fosc (Q2 cycle) to Port input invalid

50

(I/O in hold time)

OS17 TioV2osH Port input valid to Fosc(Q2 cycle)

20

—

ns

(I/O in setup time)

OS18* TioR

OS19* TioF

Port output rise time⁽²⁾

—

15

40

32

72

ns

VDD = 2.0V

VDD = 5.0V

Port output fall time⁽²⁾

—

28

15

55

30

VDD = 2.0V

VDD = 5.0V

OS20* Tinp

OS21* Tioc

INT pin input high or low time

25

—

ns

Interrupt-on-change new input level

time

*

†

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC.

DS41639A-page 368

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 29-7:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

Internal Reset⁽¹⁾

Watchdog Timer

Reset⁽¹⁾

31

34

I/O pins

Note 1: Asserted low.

FIGURE 29-8:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR and VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

37

Reset

33⁽¹⁾

(due to BOR)

Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.

2 ms delay if PWRTE = 0and VREGEN = 1.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 369

PIC16(L)F1454/5/9

TABLE 29-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

TMCL

Characteristic

Min. Typ† Max. Units

Conditions

30

MCLR Pulse Width (low)

2

5

—

s VDD = 3.3-5V, -40°C to +85°C

s VDD = 3.3-5V

31

TWDTLP Low-Power Watchdog Timer

Time-out Period

10

16

27

ms VDD = 3.3V-5V,

1:16 Prescaler used

33*

34*

TPWRT Power-up Timer Period, PWRTE = 0 40

65

—

140

2.0

ms

TIOZ

I/O high-impedance from MCLR Low

or Watchdog Timer Reset

—

s

35

VBOR

Brown-out Reset Voltage⁽²⁾

2.55 2.70 2.85

1.80 1.90 2.11

V

BORV = 0

BORV = 1

36*

37*

VHYST

Brown-out Reset Hysteresis

0

1

25

3

50

5

mV -40°C to +85°C

TBORDC Brown-out Reset DC Response

Time

s VDD  VBOR

38*

VLPOR

Low-Power Brown-out

1.8

2.1

2.5

V

LPBOR = 1

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

FIGURE 29-9:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

DS41639A-page 370

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

TABLE 29-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

TT0H

Characteristic

T0CKI High Pulse Width

Min.

Typ†

Max.

Units

Conditions

40*

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

41*

42*

TT0L

TT0P

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

ns N = prescale value

(2, 4, ..., 256)

45*

TT1H

T1CKI High Synchronous, No Prescaler

0.5 TCY + 20

15

—

ns

Time

Synchronous,

with Prescaler

Asynchronous

30

—

ns

46*

47*

TT1L

TT1P

T1CKI Low Synchronous, No Prescaler

0.5 TCY + 20

Time

Synchronous, with Prescaler

Asynchronous

15

30

T1CKI Input Synchronous

Period

Greater of:

30 or TCY + 40

N

ns N = prescale value

(1, 2, 4, 8)

Asynchronous

60

—

ns

49*

TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC

7 TOSC

—

Timers in Sync

mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater.

TABLE 29-6: PIC16(L)F1454/5/9 A/D CONVERTER (ADC) CHARACTERISTICS:

Standard Operating Conditions (unless otherwise stated)

Operating temperature Tested at 25°C

Param

No.

Sym.

Characteristic

Resolution

Min.

Typ†

Max. Units

Conditions

AD01 NR

AD02 EIL

AD03 EDL

—

10

±1.7

±1

bit

Integral Error

LSb VREF = 3.0V

Differential Error

LSb No missing codes

VREF = 3.0V

AD04 EOFF Offset Error

—

±2.5

±2.0

VDD

VREF

10

LSb VREF = 3.0V

AD05 EGN Gain Error

AD06 VREF Reference Voltage⁽³⁾

1.8

VSS

—

V

VREF = (VREF+ minus VREF-)

AD07 VAIN Full-Scale Range

AD08 ZAIN Recommended Impedance of

Analog Voltage Source

k Can go higher if external 0.01F capacitor is

present on input pin.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

3: ADC VREF is from external VREF+ pin, VDD pin, whichever is selected as reference input.

4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification

includes any such leakage from the ADC module.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 371

PIC16(L)F1454/5/9

TABLE 29-7: PIC16(L)F1454/5/9 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param

Sym.

No.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD130* TAD

A/D Clock Period

1.0

—

9.0

6.0

s

TOSC-based

ADCS<1:0> = 11(ADFRC mode)

A/D Internal FRC Oscillator

Period

1.6

AD131 TCNV Conversion Time (not including

Acquisition Time)⁽¹⁾

—

11

—

TAD Set GO/DONE bit to conversion

complete

AD132* TACQ Acquisition Time

5.0

s

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The ADRES register may be read on the following TCY cycle.

FIGURE 29-10:

PIC16(L)F1454/5/9 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

1 TCY

AD134

Q4

(TOSC/2⁽¹⁾

)

AD131

AD130

A/D CLK

9

8

7

6

3

2

1

0

A/D Data

ADRES

NEW_DATA

1 TCY

OLD_DATA

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

DS41639A-page 372

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 29-11:

PIC16(L)F1454/5/9 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

AD134

(1)

(TOSC/2 + TCY

1 TCY

)

AD131

Q4

AD130

A/D CLK

A/D Data

9

8

7

3

2

1

0

6

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 373

PIC16(L)F1454/5/9

TABLE 29-8: COMPARATOR SPECIFICATIONS

Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).

Param

No.

Sym.

Characteristics

Input Offset Voltage

Min.

Typ.

Max.

Units

Comments

CM01

VIOFF

—

±7.5

±60

mV High Power mode

VICM = VDD/2

CM02

VICM

Input Common Mode Voltage

Response Time Rising Edge

0

—

VDD

800

V

CM04A

—

400

ns

s

High-Power mode

(Note 1)

CM04B

CM04C

CM04D

CM05

Response Time Falling Edge

Response Time Rising Edge

Response Time Falling Edge

—

200

1200

550

—

400

—

High-Power mode

(Note 1)

TRESP

Low-Power mode

(Note 1)

—

Low-Power mode

(Note 1)

TMC2OV Comparator Mode Change to

Output Valid*

10

—

CM06

CHYSTER Comparator Hysteresis

65

mV Note 2

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions

from VSS to VDD.

2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.

TABLE 29-9: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS

Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).

Param

No.

Sym.

Characteristics

Step Size

Min.

Typ.

Max.

Units

Comments

DAC01*

DAC02*

DAC03*

DAC04*

*

CLSB

—

VDD/32

—

 1/2

—

V

LSb



CACC

CR

Absolute Accuracy

Unit Resistor Value (R)

Settling Time⁽¹⁾

5K

CST

—

10

s

These parameters are characterized but not tested.

Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.

DS41639A-page 374

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 29-12:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK

DT

US121

US122

US120

Refer to Figure 29-4 for load conditions.

Note:

TABLE 29-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param.

Symbol

No.

Characteristic

Min.

Max.

Units Conditions

US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

—

80

100

45

ns

US121 TCKRF

Clock out rise time and fall time

(Master mode)

50

US122 TDTRF

Data-out rise time and fall time

45

50

FIGURE 29-13:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK

DT

US125

US126

Note: Refer to Figure 29-4 for load conditions.

TABLE 29-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param.

Symbol

No.

Characteristic

Min.

Max. Units

Conditions

US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK  (DT hold time)

10

15

—

ns

US126 TCKL2DTL Data-hold after CK  (DT hold time)

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 375

PIC16(L)F1454/5/9

FIGURE 29-14:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

SP70

SCK

(CKP = 0)

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

LSb In

SP74

SP73

Note: Refer to Figure 29-4 for load conditions.

FIGURE 29-15:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81

SCK

(CKP = 0)

SP71

SP73

SP72

SP79

SCK

(CKP = 1)

SP80

SP78

LSb

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

SP74

Note: Refer to Figure 29-4 for load conditions.

LSb In

DS41639A-page 376

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

FIGURE 29-16:

SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK

(CKP = 0)

SP83

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP79

SP80

MSb

SDO

SDI

bit 6 - - - - - -1

SP75, SP76

bit 6 - - - -1

SP77

MSb In

SP74

SP73

LSb In

Note: Refer to Figure 29-4 for load conditions.

FIGURE 29-17:

SPI SLAVE MODE TIMING (CKE = 1)

SP82

SP70

SS

SP83

SCK

(CKP = 0)

SP72

SP71

SCK

(CKP = 1)

SP80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note: Refer to Figure 29-4 for load conditions.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 377

PIC16(L)F1454/5/9

TABLE 29-12: SPI MODE REQUIREMENTS

Param

No.

Symbol

Characteristic

Min.

Typ† Max. Units Conditions

SP70* TSSL2SCH, SS to SCK or SCK input

TCY

—

ns

TSSL2SCL

SP71* TSCH

SP72* TSCL

SCK input high time (Slave mode)

SCK input low time (Slave mode)

TCY + 20

100

—

ns

SP73* TDIV2SCH, Setup time of SDI data input to SCK edge

TDIV2SCL

SP74* TSCH2DIL, Hold time of SDI data input to SCK edge

TSCL2DIL

100

—

ns

SP75* TDOR

SDO data output rise time

3.0-5.5V

1.8-5.5V

—

10

—

Tcy

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns

SP76* TDOF

SDO data output fall time

SP77* TSSH2DOZ SS to SDO output high-impedance

SP78* TSCR

SCK output rise time

(Master mode)

3.0-5.5V

1.8-5.5V

SP79* TSCF

SCK output fall time (Master mode)

SP80* TSCH2DOV, SDO data output valid after

TSCL2DOV SCK edge

3.0-5.5V

1.8-5.5V

SP81* TDOV2SCH, SDO data output setup to SCK edge

TDOV2SCL

SP82* TSSL2DOV SDO data output valid after SS edge

—

50

—

ns

SP83* TSCH2SSH, SS after SCK edge

1.5TCY + 40

TSCL2SSH

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS41639A-page 378

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

2

FIGURE 29-18:

I C™ BUS START/STOP BITS TIMING

SCL

SP93

SP91

SP90

SP92

SDA

Stop

Condition

Start

Condition

Note: Refer to Figure 29-4 for load conditions.

2

TABLE 29-13: I C™ BUS START/STOP BITS REQUIREMENTS

Param

No.

Symbol

Characteristic

Min. Typ Max. Units

Conditions

SP90* TSU:STA Start condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns Only relevant for Repeated

Start condition

SP91* THD:STA Start condition

Hold time

4000

600

ns After this period, the first

clock pulse is generated

SP92* TSU:STO Stop condition

Setup time

4700

600

ns

SP93 THD:STO Stop condition

Hold time

4000

600

ns

*

These parameters are characterized but not tested.

2

FIGURE 29-19:

I C™ BUS DATA TIMING

SP100

SP103

SP102

SP101

SCL

SP90

SP106

SP107

SP92

SP91

SDA

In

SP110

SP109

SDA

Out

Note: Refer to Figure 29-4 for load conditions.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 379

PIC16(L)F1454/5/9

2

TABLE 29-14: I C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

100 kHz mode

Min.

Max. Units

Conditions

SP100* THIGH

Clock high time

4.0

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY

4.7

—

SP101* TLOW

Clock low time

100 kHz mode

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

SSP module

1.3

—

Device must operate at a

minimum of 10 MHz

1.5TCY

—

SP102* TR

SP103* TF

SDA and SCL rise 100 kHz mode

time

1000

ns

400 kHz mode

20 + 0.1CB 300

CB is specified to be from

10-400 pF

SDA and SCL fall

time

100 kHz mode

400 kHz mode

—

250

ns

20 + 0.1CB 250

CB is specified to be from

10-400 pF

SP106* THD:DAT Data input hold time 100 kHz mode

400 kHz mode

0

—

0.9

—

ns

s

ns

s

0

SP107* TSU:DAT Data input setup

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

250

100

—

(Note 2)

(Note 1)

—

SP109* TAA

Output valid from

clock

3500

—

SP110* TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

SP111 CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I²C™ bus device can be used in a Standard mode (100 kHz) I²C bus system, but

the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does

not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,

it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to

the Standard mode I²C bus specification), before the SCL line is released.

DS41639A-page 380

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

NOTES:

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 381

PIC16(L)F1454/5/9

DS41639A-page 382

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

30.0 DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

Graphs and charts are not available at this time.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 383

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 384

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

31.1 MPLAB Integrated Development

Environment Software

31.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers and dsPIC^®digital signal

controllers are supported with a full range of software

and hardware development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• A single graphical interface to all debugging tools

- Simulator

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- Programmer (sold separately)

- HI-TECH C^®for Various Device Families

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Customizable data windows with direct edit of

contents

• Simulators

• High-level source code debugging

• Mouse over variable inspection

- MPLAB SIM Software Simulator

• Emulators

• Drag and drop variables from source to watch

windows

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 385

PIC16(L)F1454/5/9

31.2 MPLAB C Compilers for Various

Device Families

31.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

31.3 HI-TECH C for Various Device

Families

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

31.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

31.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• MPLAB IDE compatibility

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

DS41639A-page 386

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

31.7 MPLAB SIM Software Simulator

31.9 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC^®Flash microcon-

trollers and dsPIC^®DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

31.10 PICkit 3 In-Circuit Debugger/

Programmer and

31.8 MPLAB REAL ICE In-Circuit

Emulator System

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC^®and dsPIC^®Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 387

PIC16(L)F1454/5/9

31.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

31.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows^®programming interface supports baseline

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

(PIC10F,

PIC12F5xx,

PIC16F5xx),

midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Development Environment (IDE) the PICkit™

2

enables in-circuit debugging on most PIC^®microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

31.12 MPLAB PM3 Device Programmer

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS41639A-page 388

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

32.0 PACKAGING INFORMATION

32.1 Package Marking Information

14-Lead PDIP (300 mil)

Example

PIC16F1454

-E/P

e3

1220123

14-Lead SOIC (3.90 mm)

Example

PIC16F1455

e

3

-E/SL

1220123

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro^®device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 389

PIC16(L)F1454/5/9

14-Lead TSSOP (4.4 mm)

Example

XXXXXXXX

YYWW

F1454EST

1220

NNN

123

16-Lead QFN (4x4x0.9 mm)

Example

PIC16

F1455

PIN 1

e

3

E/ML

220123

20-Lead PDIP (300 mil)

Example

PIC16F1459

XXXXXXXXXXXXXXXXX

e

3

-E/P

YYWWNNN

1220123

DS41639A-page 390

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

20-Lead SOIC (7.50 mm)

Example

PIC16F1459

e

3

-E/SO

1220123

20-Lead SSOP (5.30 mm)

Example

PIC16F1459

e

3

-E/SS

1220123

Example

20-Lead QFN (4x4x0.9 mm)

PIC16

F1459

PIN 1

e

3

E/ML

220123

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 391

PIC16(L)F1454/5/9

32.2 Package Details

The following sections give the technical details of the packages.

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DS41639A-page 392

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 393

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS41639A-page 394

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 395

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS41639A-page 396

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 397

PIC16(L)F1454/5/9

ꢀꢟꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢠꢏꢅꢆꢇꢡꢉꢅꢋꢢꢇꢝꢙꢇꢃꢄꢅꢆꢇꢈꢅꢍꢣꢅꢤꢄꢇꢒꢥꢃꢓꢇꢔꢇꢁꢦꢁꢦꢖꢧꢨꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢠꢡꢝꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

D

D2

EXPOSED

PAD

e

E

E2

2

1

2

b

1

K

N

NOTE 1

L

TOP VIEW

BOTTOM VIEW

A3

A

A1

ꢯꢄꢃꢏꢇꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅ

ꢝꢕꢄꢏꢉꢖꢏꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢴꢆꢌꢐꢉꢊꢊꢅꢸꢃꢋꢏꢘ

ꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋꢅꢳꢌꢄꢜꢏꢘ

ꢝꢕꢄꢏꢉꢖꢏꢅꢸꢃꢋꢏꢘ

ꢝꢕꢄꢏꢉꢖꢏꢅꢳꢌꢄꢜꢏꢘ

ꢀꢻ

ꢌ

ꢣꢁꢻꢨꢅꢩꢛꢝ

ꢣꢁꢷꢣ

ꢣꢁꢣꢙ

ꢣꢁꢙꢣꢅꢼꢠꢬ

ꢥꢁꢣꢣꢅꢩꢛꢝ

ꢙꢁꢻꢨ

ꢥꢁꢣꢣꢅꢩꢛꢝ

ꢙꢁꢻꢨ

ꢦ

ꢣꢁꢹꢣ

ꢣꢁꢣꢣ

ꢀꢁꢣꢣ

ꢣꢁꢣꢨ

ꢦꢀ

ꢦꢞ

ꢠ

ꢠꢙ

ꢟ

ꢟꢙ

ꢔ

ꢳ

ꢙꢁꢨꢣ

ꢙꢁꢹꢣ

ꢙꢁꢨꢣ

ꢣꢁꢙꢨ

ꢣꢁꢞꢣ

ꢣꢁꢙꢣ

ꢙꢁꢹꢣ

ꢣꢁꢞꢨ

ꢣꢁꢨꢣ

ꢶ

ꢣꢁꢞꢣ

ꢣꢁꢥꢣ

ꢶ

ꢝꢕꢄꢏꢉꢖꢏꢽꢏꢕꢽꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋ

V

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢂꢉꢖꢭꢉꢜꢌꢅꢃꢇꢅꢇꢉꢗꢅꢇꢃꢄꢜꢈꢊꢉꢏꢌꢋꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢀꢙꢺꢩ

DS41639A-page 398

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 399

PIC16(L)F1454/5/9

ꢩꢖꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢉꢇꢐꢑꢂꢃꢌꢑꢄꢇꢒꢈꢓꢇꢔꢇꢕꢖꢖꢇꢗꢌꢉꢇꢘꢙꢆꢚꢇꢛꢈꢎꢐꢈꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

ꢅ

N

E1

NOTE 1

1

2

3

D

E

A2

A

L

c

A1

b1

eB

e

b

ꢯꢄꢃꢏꢇꢰꢱꢝꢲꢠꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢙꢣ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢫꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ

ꢌ

ꢦ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢁꢀꢣꢣꢅꢩꢛꢝ

ꢶ

ꢁꢀꢞꢣ

ꢶ

ꢁꢞꢀꢣ

ꢁꢙꢨꢣ

ꢀꢁꢣꢞꢣ

ꢁꢀꢞꢣ

ꢁꢣꢀꢣ

ꢁꢣꢻꢣ

ꢁꢣꢀꢹ

ꢶ

ꢁꢙꢀꢣ

ꢁꢀꢷꢨ

ꢶ

ꢁꢀꢀꢨ

ꢁꢣꢀꢨ

ꢁꢞꢣꢣ

ꢁꢙꢥꢣ

ꢁꢷꢹꢣ

ꢁꢀꢀꢨ

ꢁꢣꢣꢹ

ꢁꢣꢥꢨ

ꢁꢣꢀꢥ

ꢶ

ꢁꢞꢙꢨ

ꢁꢙꢹꢣ

ꢀꢁꢣꢻꢣ

ꢁꢀꢨꢣ

ꢁꢣꢀꢨ

ꢁꢣꢺꢣ

ꢁꢣꢙꢙ

ꢁꢥꢞꢣ

ꢖ

ꢔꢀ

ꢔ

ꢌꢩ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢀꢷꢩ

DS41639A-page 400

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 401

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS41639A-page 402

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

ꢩꢖꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢪꢫꢬꢌꢑꢣꢇꢪꢗꢅꢉꢉꢇꢭꢏꢋꢉꢌꢑꢄꢇꢒꢪꢪꢓꢇꢔꢇꢮꢧꢕꢖꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢪꢪꢭꢈꢜꢇ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

D

N

E

E1

NOTE 1

1

2

e

b

c

A2

A

φ

A1

L1

ꢯꢄꢃꢏꢇꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

L

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢣ

ꢌ

ꢣꢁꢻꢨꢅꢩꢛꢝ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅ

ꢴꢆꢌꢐꢉꢊꢊꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ

ꢬꢕꢕꢏꢡꢐꢃꢄꢏ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ

ꢦ

ꢶ

ꢀꢁꢺꢨ

ꢶ

ꢺꢁꢹꢣ

ꢨꢁꢞꢣ

ꢺꢁꢙꢣ

ꢣꢁꢺꢨ

ꢀꢁꢙꢨꢅꢼꢠꢬ

ꢶ

ꢙꢁꢣꢣ

ꢀꢁꢹꢨ

ꢶ

ꢹꢁꢙꢣ

ꢨꢁꢻꢣ

ꢺꢁꢨꢣ

ꢣꢁꢷꢨ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢳꢀ

ꢖ

ꢀꢁꢻꢨ

ꢣꢁꢣꢨ

ꢺꢁꢥꢣ

ꢨꢁꢣꢣ

ꢻꢁꢷꢣ

ꢣꢁꢨꢨ

ꢣꢁꢣꢷ

ꢣꢾ

ꢣꢁꢙꢨ

ꢹꢾ

ꢀ

ꢥꢾ

ꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢔ

ꢣꢁꢙꢙ

ꢶ

ꢣꢁꢞꢹ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢙꢣꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢺꢙꢩ

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 403

PIC16(L)F1454/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS41639A-page 404

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

ꢩꢖꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢠꢏꢅꢆꢇꢡꢉꢅꢋꢢꢇꢝꢙꢇꢃꢄꢅꢆꢇꢈꢅꢍꢣꢅꢤꢄꢇꢒꢥꢃꢓꢇꢔꢇꢁꢦꢁꢦꢖꢧꢨꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢠꢡꢝꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

ꢅ

D

D2

EXPOSED

PAD

e

E2

E

2

1

b

2

1

K

N

NOTE 1

L

BOTTOM VIEW

TOP VIEW

A

A1

A3

ꢯꢄꢃꢏꢇꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢣ

ꢌ

ꢣꢁꢨꢣꢅꢩꢛꢝ

ꢣꢁꢷꢣ

ꢣꢁꢣꢙ

ꢣꢁꢙꢣꢅꢼꢠꢬ

ꢥꢁꢣꢣꢅꢩꢛꢝ

ꢙꢁꢺꢣ

ꢥꢁꢣꢣꢅꢩꢛꢝ

ꢙꢁꢺꢣ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅ

ꢝꢕꢄꢏꢉꢖꢏꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢴꢆꢌꢐꢉꢊꢊꢅꢸꢃꢋꢏꢘ

ꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋꢅꢳꢌꢄꢜꢏꢘ

ꢝꢕꢄꢏꢉꢖꢏꢅꢸꢃꢋꢏꢘ

ꢝꢕꢄꢏꢉꢖꢏꢅꢳꢌꢄꢜꢏꢘ

ꢝꢕꢄꢏꢉꢖꢏꢽꢏꢕꢽꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋ

ꢦ

ꢣꢁꢹꢣ

ꢣꢁꢣꢣ

ꢀꢁꢣꢣ

ꢣꢁꢣꢨ

ꢦꢀ

ꢦꢞ

ꢠ

ꢠꢙ

ꢟ

ꢟꢙ

ꢔ

ꢳ

ꢙꢁꢻꢣ

ꢙꢁꢹꢣ

ꢙꢁꢻꢣ

ꢣꢁꢀꢹ

ꢣꢁꢞꢣ

ꢣꢁꢙꢣ

ꢙꢁꢹꢣ

ꢣꢁꢞꢣ

ꢣꢁꢨꢣ

ꢶ

ꢣꢁꢙꢨ

ꢣꢁꢥꢣ

ꢶ

V

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢂꢉꢖꢭꢉꢜꢌꢅꢃꢇꢅꢇꢉꢗꢅꢇꢃꢄꢜꢈꢊꢉꢏꢌꢋꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢀꢙꢻꢩ

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 405

PIC16(L)F1454/5/9

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

DS41639A-page 406

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A (06/2012)

Initial release.

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 407

PIC16(L)F1454/5/9

NOTES:

DS41639A-page 408

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

INDEX

BAUDCON Register ......................................................... 269

BF ............................................................................. 238, 240

BF Status Flag.......................................................... 238, 240

Block Diagrams

A

A/D

Specifications.................................................... 371, 372

Absolute Maximum Ratings .............................................. 353

AC Characteristics

ADC.......................................................................... 154

ADC Transfer Function............................................. 166

Analog Input Model........................................... 166, 178

Clock Source .............................................................. 58

Comparator............................................................... 174

Crystal Operation.................................................. 60, 61

Digital-to-Analog Converter (DAC) ........................... 170

EUSART Receive..................................................... 258

EUSART Transmit.................................................... 257

External RC Mode ...................................................... 62

Fail-Safe Clock Monitor (FSCM)................................. 71

Generic I/O Port........................................................ 129

Interrupt Logic............................................................. 91

On-Chip Reset Circuit................................................. 79

PIC16(L)F1454/5/9..................................................... 14

PIC16C74................................................................. 5, 6

PIC16C74A............................................................... 5, 6

PWM......................................................................... 287

Resonator Operation .................................................. 60

Self Tuning ................................................................. 73

Timer0 ...................................................................... 183

Timer1 ...................................................................... 187

Timer1 Gate.............................................. 192, 193, 194

Timer2 ...................................................................... 199

USB Interrupt Logic .................................................. 318

USB Peripheral and Options .................................... 309

Voltage Reference.................................................... 149

Voltage Reference Output Buffer Example .............. 170

BORCON Register.............................................................. 81

BRA .................................................................................. 344

Break Character (12-bit) Transmit and Receive ............... 278

Brown-out Reset (BOR)...................................................... 81

Specifications ........................................................... 370

Timing and Characteristics....................................... 369

Industrial and Extended ............................................ 367

Load Conditions........................................................ 366

ACKSTAT ......................................................................... 238

ACKSTAT Status Flag ...................................................... 238

ADC .................................................................................. 153

Acquisition Requirements ......................................... 165

Associated registers.................................................. 167

Block Diagram........................................................... 154

Calculating Acquisition Time..................................... 165

Channel Selection..................................................... 155

Configuration............................................................. 155

Configuring Interrupt ................................................. 159

Conversion Clock...................................................... 155

Conversion Procedure .............................................. 159

Internal Sampling Switch (RSS) Impedance.............. 165

Interrupts................................................................... 157

Operation .................................................................. 158

Operation During Sleep ............................................ 158

Port Configuration..................................................... 155

Reference Voltage (VREF)......................................... 155

Source Impedance.................................................... 165

Starting an A/D Conversion ...................................... 157

ADCON0 Register....................................................... 38, 160

ADCON1 Register....................................................... 38, 161

ADCON2 Register............................................................. 162

ADDFSR ........................................................................... 343

ADDWFC .......................................................................... 343

ADRESH Register............................................................... 38

ADRESH Register (ADFM = 0)......................................... 163

ADRESH Register (ADFM = 1)......................................... 164

ADRESL Register (ADFM = 0).......................................... 163

ADRESL Register (ADFM = 1).......................................... 164

Alternate Pin Function....................................................... 130

Analog-to-Digital Converter. See ADC

C

ANSELA Register ............................................................. 133

ANSELB Register ............................................................. 137

ANSELC Register ............................................................. 141

APFCON Register............................................................. 130

Assembler

C Compilers

MPLAB C18.............................................................. 386

CALL................................................................................. 345

CALLW ............................................................................. 345

CLKRCON Register............................................................ 88

Clock Accuracy with Asynchronous Operation................. 266

Clock Sources

MPASM Assembler................................................... 386

Automatic Context Saving................................................... 95

External Modes........................................................... 59

EC ...................................................................... 59

HS ...................................................................... 59

LP....................................................................... 59

OST .................................................................... 60

RC ...................................................................... 62

XT....................................................................... 59

Internal Modes............................................................ 62

HFINTOSC ......................................................... 62

Internal Oscillator Clock Switch Timing.............. 64

LFINTOSC.......................................................... 63

Clock Switching ............................................................ 66, 67

CMOUT Register.............................................................. 180

CMxCON0 Register.......................................................... 179

CMxCON1 Register.......................................................... 180

B

Bank 10............................................................................... 41

Bank 11............................................................................... 41

Bank 12............................................................................... 41

Bank 13............................................................................... 41

Bank 14-28.......................................................................... 41

Bank 2................................................................................. 39

Bank 3................................................................................. 39

Bank 30............................................................................... 42

Bank 31............................................................................... 43

Bank 4................................................................................. 40

Bank 5................................................................................. 40

Bank 6................................................................................. 40

Bank 7................................................................................. 40

Bank 8................................................................................. 40

Bank 9................................................................................. 40

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 409

PIC16(L)F1454/5/9

Code Examples

EUSART ........................................................................... 257

Associated Registers

A/D Conversion.........................................................159

Initializing PORTA............................................. 129, 131

Writing to Flash Program Memory ............................121

Comparator

Associated Registers ................................................181

Operation ..................................................................173

Comparator Module ..........................................................173

Cx Output State Versus Input Conditions .................175

Comparator Specifications................................................374

Comparators

C2OUT as T1 Gate...................................................189

Complementary Waveform Generator (CWG).......... 293, 294

CONFIG1 Register..............................................................52

CONFIG2 Register..............................................................54

Core Function Register .......................................................37

CPU Clock Divider ..............................................................66

Customer Change Notification Service .............................415

Customer Notification Service...........................................415

Customer Support.............................................................415

CWG

Auto-shutdown Control .............................................300

Clock Source.............................................................296

Output Control...........................................................296

Selectable Input Sources..........................................296

CWGxCON0 Register .......................................................303

CWGxCON1 Register .......................................................304

CWGxCON2 Register .......................................................305

CWGxDBF Register..........................................................306

CWGxDBR Register..........................................................306

Baud Rate Generator ....................................... 271

Asynchronous Mode................................................. 259

12-bit Break Transmit and Receive .................. 278

Associated Registers

Receive .................................................... 265

Transmit.................................................... 261

Auto-Wake-up on Break ................................... 276

Baud Rate Generator (BRG) ............................ 270

Clock Accuracy................................................. 266

Receiver ........................................................... 262

Setting up 9-bit Mode with Address Detect ...... 264

Transmitter ....................................................... 259

Baud Rate Generator (BRG)

Auto Baud Rate Detect..................................... 275

Baud Rate Error, Calculating............................ 270

Baud Rates, Asynchronous Modes .................. 272

Formulas........................................................... 271

High Baud Rate Select (BRGH Bit) .................. 270

Synchronous Master Mode............................... 279, 283

Associated Registers

Receive .................................................... 282

Transmit.................................................... 280

Reception ......................................................... 281

Transmission .................................................... 279

Synchronous Slave Mode

Associated Registers

Receive .................................................... 284

Transmit.................................................... 283

Reception ......................................................... 284

Transmission .................................................... 283

Extended Instruction Set

D

DACCON0 (Digital-to-Analog Converter

Control 0) Register....................................................172

DACCON1 (Digital-to-Analog Converter

Control 1) Register....................................................172

Data Memory.......................................................................26

DC and AC Characteristics ...............................................383

DC Characteristics

Extended and Industrial ............................................362

Industrial and Extended ............................................355

Development Support .......................................................385

Device Configuration...........................................................51

Code Protection ..........................................................55

Configuration Word.....................................................51

Device ID and Revision ID..........................................56

User ID........................................................................55

Device ID Register ..............................................................56

Device Overview ......................................................... 13, 107

Digital-to-Analog Converter (DAC)....................................169

Associated Registers ................................................172

Effects of a Reset......................................................170

Specifications............................................................374

ADDFSR................................................................... 343

F

Fail-Safe Clock Monitor ...................................................... 71

Fail-Safe Condition Clearing....................................... 71

Fail-Safe Detection ..................................................... 71

Fail-Safe Operation..................................................... 71

Reset or Wake-up from Sleep .................................... 71

Firmware Instructions ....................................................... 339

Fixed Voltage Reference (FVR)........................................ 149

Associated Registers................................................ 150

Flash Program Memory .................................................... 112

Associated Registers................................................ 128

Configuration Word w/ Flash

Program Memory.............................................. 128

Erasing ..................................................................... 116

Modifying .................................................................. 122

Write Verify............................................................... 124

Writing ...................................................................... 118

FSR Register ...................................................................... 37

FVRCON (Fixed Voltage Reference Control) Register..... 150

E

I

Effects of Reset

PWM mode ...............................................................289

Electrical Specifications ....................................................353

Enhanced Mid-Range CPU.................................................21

Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART)...............................257

Equations

Estimating USB Transceiver Current

Consumption.....................................................322

Errata ..................................................................................11

I²C Mode (MSSP)

Acknowledge Sequence Timing ............................... 242

Bus Collision

During a Repeated Start Condition................... 246

During a Stop Condition ................................... 247

Effects of a Reset ..................................................... 243

I²C Clock Rate w/BRG.............................................. 249

Master Mode

Operation.......................................................... 234

Reception ......................................................... 240

DS41639A-page 410

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

Start Condition Timing .............................. 236, 237

Transmission .................................................... 238

Multi-Master Communication, Bus Collision

Internal Oscillator Block

INTOSC

Specifications ................................................... 367

and Arbitration .................................................. 243

Multi-Master Mode .................................................... 243

Read/Write Bit Information (R/W Bit) ........................ 219

Slave Mode

Internal Sampling Switch (RSS) Impedance ..................... 165

Internet Address ............................................................... 415

Interrupt-On-Change......................................................... 143

Associated Registers................................................ 148

Interrupts ............................................................................ 91

ADC.......................................................................... 159

Associated registers w/ Interrupts ............................ 101

Configuration Word w/ Clock Sources........................ 78

Configuration Word w/ Reference Clock Sources ...... 89

TMR1........................................................................ 191

INTOSC Specifications..................................................... 367

IOCAF Register ................................................................ 146

IOCAN Register................................................................ 145

IOCAP Register................................................................ 145

IOCBF Register ................................................................ 147

IOCBN Register................................................................ 147

IOCBP Register................................................................ 146

Transmission .................................................... 224

Sleep Operation........................................................ 243

Stop Condition Timing............................................... 242

INDF Register ..................................................................... 37

Indirect Addressing ............................................................. 47

Instruction Format............................................................. 340

Instruction Set................................................................... 339

ADDLW..................................................................... 343

ADDWF..................................................................... 343

ADDWFC .................................................................. 343

ANDLW..................................................................... 343

ANDWF..................................................................... 343

BRA........................................................................... 344

CALL......................................................................... 345

CALLW...................................................................... 345

LSLF ......................................................................... 347

LSRF......................................................................... 347

MOVF........................................................................ 347

MOVIW ..................................................................... 348

MOVLB ..................................................................... 348

MOVWI ..................................................................... 349

OPTION .................................................................... 349

RESET...................................................................... 349

SUBWFB................................................................... 351

TRIS.......................................................................... 352

BCF........................................................................... 344

BSF........................................................................... 344

BTFSC ...................................................................... 344

BTFSS ...................................................................... 344

CALL......................................................................... 345

CLRF......................................................................... 345

CLRW ....................................................................... 345

CLRWDT................................................................... 345

COMF ....................................................................... 345

DECF ........................................................................ 345

DECFSZ.................................................................... 346

GOTO ....................................................................... 346

INCF.......................................................................... 346

INCFSZ..................................................................... 346

IORLW ...................................................................... 346

IORWF...................................................................... 346

MOVLW .................................................................... 348

MOVWF .................................................................... 348

NOP .......................................................................... 349

RETFIE ..................................................................... 350

RETLW ..................................................................... 350

RETURN................................................................... 350

RLF ........................................................................... 350

RRF........................................................................... 351

SLEEP ...................................................................... 351

SUBLW ..................................................................... 351

SUBWF..................................................................... 351

SWAPF ..................................................................... 352

XORLW..................................................................... 352

XORWF..................................................................... 352

INTCON Register................................................................ 96

L

LATA Register .......................................................... 133, 141

LATB Register .................................................................. 137

Load Conditions................................................................ 366

LSLF ................................................................................. 347

LSRF ................................................................................ 347

M

Master Synchronous Serial Port. See MSSP

MCLR ................................................................................. 82

Internal........................................................................ 82

Memory Organization ......................................................... 23

Data............................................................................ 26

Program...................................................................... 23

Microchip Internet Web Site.............................................. 415

MOVIW............................................................................. 348

MOVLB............................................................................. 348

MOVWI............................................................................. 349

MPLAB ASM30 Assembler, Linker, Librarian................... 386

MPLAB Integrated Development

Environment Software .............................................. 385

MPLAB PM3 Device Programmer .................................... 388

MPLAB REAL ICE In-Circuit Emulator System ................ 387

MPLINK Object Linker/MPLIB Object Librarian................ 386

MSSP ............................................................................... 203

SPI Mode.................................................................. 206

SSPBUF Register..................................................... 209

SSPSR Register....................................................... 209

MSSPx

I²C Mode .................................................................. 214

I²C Mode Operation.................................................. 216

O

OPCODE Field Descriptions............................................. 339

OPTION............................................................................ 349

OPTION_REG Register.................................................... 185

OSCCON Register.............................................................. 75

Oscillator

Associated Registers.................................................. 78

Associated registers ................................................. 307

Oscillator Module........................................................ 57, 309

ECH............................................................................ 57

ECL............................................................................. 57

ECM............................................................................ 57

HS............................................................................... 57

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 411

PIC16(L)F1454/5/9

INTOSC ......................................................................57

LP................................................................................57

RC...............................................................................57

XT ...............................................................................57

Oscillator Parameters........................................................367

Oscillator Specifications....................................................367

Oscillator Start-up Timer (OST)

Specifications............................................................370

Oscillator Switching

Fail-Safe Clock Monitor...............................................71

Two-Speed Clock Start-up..........................................69

OSCSTAT Register.............................................................76

OSCTUNE Register ............................................................77

Pulse Width Modulation (PWM)........................................ 287

Associated registers w/ PWM................................... 292

PWM Mode

Duty Cycle ........................................................ 288

Effects of Reset ................................................ 289

Example PWM Frequencies and

Resolutions, 20 MHZ................................ 289

Example PWM Frequencies and

Resolutions, 8 MHz .................................. 289

Operation in Sleep Mode.................................. 289

Setup for Operation using PWMx pins ............. 290

System Clock Frequency Changes .................. 289

PWM Period.............................................................. 288

Setup for PWM Operation using PWMx Pins ........... 290

PWMxCON Register......................................................... 291

PWMxDCH Register......................................................... 292

PWMxDCL Register.......................................................... 292

P

Packaging .........................................................................389

Marking .....................................................................389

PDIP Details..............................................................392

PCL and PCLATH...............................................................21

PCL Register.......................................................................37

PCLATH Register................................................................37

PCON Register ............................................................. 38, 85

PIE1 Register................................................................38, 97

PIE2 Register................................................................38, 98

Pinout Descriptions

R

RCREG............................................................................. 264

RCREG Register ................................................................ 39

RCSTA Register ......................................................... 39, 268

Reader Response............................................................. 416

Read-Modify-Write Operations ......................................... 339

Reference Clock ................................................................. 87

Associated Registers.................................................. 89

Registers

PIC16(L)F1454 ...........................................................15

PIC16(L)F1455 ...........................................................17

PIC16(L)F1459 ...........................................................19

PIR1 Register................................................................38, 99

PIR2 Register..............................................................38, 100

PMADR Registers.............................................................112

PMADRH Registers ..........................................................112

PMADRL Register.............................................................126

PMADRL Registers...........................................................112

PMCON1 Register .................................................... 112, 127

PMCON2 Register .................................................... 112, 128

PMDATH Register.............................................................125

PMDATL Register .............................................................125

PMDRH Register...............................................................126

PORTA..............................................................................131

Associated Registers ................................................134

LATA Register.............................................................39

PORTA Register .........................................................38

Specifications............................................................368

PORTA Register ...............................................................132

PORTB..............................................................................135

Associated Registers ................................................138

LATB Register.............................................................39

PORTB Register .........................................................38

PORTB Register ...............................................................136

PORTC

Associated Registers ................................................141

LATC Register ............................................................39

Pin Descriptions and Diagrams.................................139

PORTC Register.........................................................38

PORTC Register ...............................................................140

Power-Down Mode (Sleep)...............................................103

Associated Registers ................................................106

Power-on Reset ..................................................................80

Power-up Time-out Sequence ............................................82

Power-up Timer (PWRT).....................................................80

Specifications............................................................370

PR2 Register.......................................................................38

Program Memory ................................................................23

Map and Stack (PIC16(L)F1509 .................................24

Programming, Device Instructions ....................................339

ADCON0 (ADC Control 0)........................................ 160

ADCON1 (ADC Control 1)........................................ 161

ADCON2 (ADC Control 2)........................................ 162

ADRESH (ADC Result High) with ADFM = 0) .......... 163

ADRESH (ADC Result High) with ADFM = 1) .......... 164

ADRESL (ADC Result Low) with ADFM = 0)............ 163

ADRESL (ADC Result Low) with ADFM = 1)............ 164

ANSELA (PORTA Analog Select)............................. 133

ANSELB (PORTB Analog Select)............................. 137

ANSELC (PORTC Analog Select) ............................ 141

APFCON (Alternate Pin Function Control) ............... 130

BAUDCON (Baud Rate Control)............................... 269

BDnSTAT (Buffer Descriptor n Status,

CPU Mode)............................................... 314, 330

BDnSTAT (Buffer Descriptor n Status,

SIE Mode)................................................. 315, 331

BORCON Brown-out Reset Control) .......................... 81

CLKRCON (Reference Clock Control)........................ 88

CMOUT (Comparator Output) .................................. 180

CMxCON0 (Cx Control)............................................ 179

CMxCON1 (Cx Control 1)......................................... 180

Configuration Word 1.................................................. 52

Configuration Word 2.................................................. 54

Core Function, Summary............................................ 37

CWGxCON0 (CWG Control 0) ................................. 303

CWGxCON1 (CWG Control 1) ................................. 304

CWGxCON2 (CWG Control 1) ................................. 305

CWGxDBF (CWGx Dead Band Falling Count)......... 306

CWGxDBR (CWGx Dead Band Rising Count)......... 306

DACCON0................................................................ 172

DACCON1................................................................ 172

Device ID.................................................................... 56

FVRCON................................................................... 150

INTCON (Interrupt Control)......................................... 96

IOCAF (Interrupt-on-Change PORTA Flag).............. 146

IOCAN (Interrupt-on-Change PORTA

Negative Edge)................................................. 145

IOCAP (Interrupt-on-Change PORTA

Positive Edge) .................................................. 145

DS41639A-page 412

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

IOCBF (Interrupt-on-Change PORTB Flag).............. 147

IOCBN (Interrupt-on-Change PORTB

Negative Edge)................................................. 147

IOCBP (Interrupt-on-Change PORTB

Reset .................................................................................. 79

Reset Instruction................................................................. 82

Resets ................................................................................ 79

Associated Registers.................................................. 86

Revision History................................................................ 407

Positive Edge)................................................... 146

LATA (Data Latch PORTA)....................................... 133

LATB (Data Latch PORTB)....................................... 137

LATC (Data Latch PORTC) ...................................... 141

OPTION_REG (OPTION) ......................................... 185

OSCCON (Oscillator Control) ..................................... 75

OSCSTAT (Oscillator Status) ..................................... 76

OSCTUNE (Oscillator Tuning).................................... 77

PCON (Power Control Register)................................. 85

PCON (Power Control) ............................................... 85

PIE1 (Peripheral Interrupt Enable 1)........................... 97

PIE2 (Peripheral Interrupt Enable 2)........................... 98

PIR1 (Peripheral Interrupt Register 1) ........................ 99

PIR2 (Peripheral Interrupt Request 2) ...................... 100

PMADRL (Program Memory Address)...................... 126

PMCON1 (Program Memory Control 1).................... 127

PMCON2 (Program Memory Control 2).................... 128

PMDATH (Program Memory Data)........................... 125

PMDATL (Program Memory Data)............................ 125

PMDRH (Program Memory Address) ....................... 126

PORTA...................................................................... 132

PORTB...................................................................... 136

PORTC ..................................................................... 140

PWMxCON (PWM Control)....................................... 291

PWMxDCH (PWM Control)....................................... 292

PWMxDCL (PWM Control) ....................................... 292

RCREG..................................................................... 275

RCSTA (Receive Status and Control)....................... 268

SPBRGH................................................................... 270

SPBRGL ................................................................... 270

Special Function, Summary........................................ 38

SSPADD (MSSP Address and Baud Rate,

S

Software Simulator (MPLAB SIM) .................................... 387

SPBRG Register................................................................. 39

SPBRGH Register............................................................ 270

SPBRGL Register............................................................. 270

Special Function Registers (SFRs)..................................... 38

SPI Mode (MSSP)

SPI Clock.................................................................. 209

SPI Mode (MSSPx)

Associated Registers................................................ 213

SSPADD Register............................................................. 255

SSPCON1 Register.......................................................... 252

SSPCON2 Register.......................................................... 253

SSPCON3 Register.......................................................... 254

SSPMSK Register ............................................................ 255

SSPOV ............................................................................. 240

SSPOV Status Flag.......................................................... 240

SSPSTAT Register........................................................... 250

R/W Bit ..................................................................... 219

ST

Block Diagram ............................................................ 73

Stack................................................................................... 45

Accessing ................................................................... 45

Reset .......................................................................... 47

Stack Overflow/Underflow .................................................. 82

STATUS Register ............................................................... 27

SUBWFB .......................................................................... 351

T

T1CON Register ......................................................... 38, 195

T1GCON Register ............................................................ 196

T2CON (Timer2) Register................................................. 201

T2CON Register ................................................................. 38

Temperature Indicator

I²C Mode) ......................................................... 255

SSPCON1 (MSSP Control 1).................................... 252

SSPCON2 (SSP Control 2)....................................... 253

SSPCON3 (SSP Control 3)....................................... 254

SSPMSK (SSP Mask)............................................... 255

SSPSTAT (SSP Status)............................................ 250

STATUS...................................................................... 27

T1CON (Timer1 Control)........................................... 195

T1GCON (Timer1 Gate Control)............................... 196

T2CON...................................................................... 201

TRISA (Tri-State PORTA)......................................... 132

TRISB (Tri-State PORTB)......................................... 136

TRISC (Tri-State PORTC) ........................................ 140

TXSTA (Transmit Status and Control) ...................... 267

UCFG (USB Configuration)............................... 310, 327

UCON (USB Control)........................................ 310, 326

UEIE (USB Error Interrupt Enable) ........................... 335

UEIE (USB Interrupt Enable) .................................... 319

UEIR (USB Error Interrupt Status).................... 319, 334

UEPN (USB Endpoint Control) ................................. 312

UEPn (USB Endpoint n Control)............................... 329

UIE (USB Interrupt Enable)............................... 319, 333

UIR (USB Interrupt Status) ............................... 319, 332

USTAT (USB Status) ........................................ 312, 328

VREGCON (Voltage Regulator Control)................... 106

WDTCON (Watchdog Timer Control) ....................... 110

WPUA (Weak Pull-up PORTA)................................. 134

WPUB (Weak Pull-up PORTB)................................. 138

RESET .............................................................................. 349

Associated Registers................................................ 152

Temperature Indicator Module.......................................... 151

Thermal Considerations.................................................... 365

Timer0 .............................................................................. 183

Associated Registers................................................ 185

Operation.................................................................. 183

Specifications ........................................................... 371

Timer1 .............................................................................. 187

Associated registers ................................................. 197

Asynchronous Counter Mode................................... 189

Reading and Writing......................................... 189

Clock Source Selection ............................................ 188

Interrupt .................................................................... 191

Operation.................................................................. 188

Operation During Sleep............................................ 191

Oscillator................................................................... 189

Prescaler .................................................................. 189

Specifications ........................................................... 371

Timer1 Gate

Selecting Source .............................................. 189

TMR1H Register....................................................... 187

TMR1L Register ....................................................... 187

Timer2 .............................................................................. 199

Associated registers ................................................. 202

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 413

PIC16(L)F1454/5/9

Timers

SPI Mode.................................................................. 378

TMR0 Register.................................................................... 38

TMR1H Register................................................................. 38

TMR1L Register.................................................................. 38

TMR2 Register.................................................................... 38

TRIS.................................................................................. 352

TRISA Register........................................................... 38, 132

TRISB Register........................................................... 38, 136

TRISC............................................................................... 139

TRISC Register........................................................... 38, 140

Two-Speed Clock Start-up Mode........................................ 69

TXREG ............................................................................. 259

TXREG Register................................................................. 39

TXSTA Register.......................................................... 39, 267

BRGH Bit .................................................................. 270

Timer1

T1CON..............................................................195

T1GCON...........................................................196

Timer2

T2CON..............................................................201

Timing Diagrams

A/D Conversion.........................................................372

A/D Conversion (Sleep Mode) ..................................373

Acknowledge Sequence ...........................................242

Asynchronous Reception..........................................264

Asynchronous Transmission.....................................260

Asynchronous Transmission (Back to Back) ............260

Auto Wake-up Bit (WUE) During

Normal Operation..............................................277

Auto Wake-up Bit (WUE) During Sleep ....................277

Automatic Baud Rate Calibration..............................275

Baud Rate Generator with Clock Arbitration.............235

BRG Reset Due to SDA Arbitration

U

Universal Serial Bus

Associated Registers................................................ 336

BD Address Validation.............................................. 315

BD Byte Count.......................................................... 315

Buffer Descriptor Table (BDT) .................................. 313

Buffer Descriptors

During Start Condition.......................................245

Brown-out Reset (BOR)............................................369

Brown-out Reset Situations ........................................81

Bus Collision During a Repeated

Assignment in Different Buffering Modes ......... 316

Example............................................................ 314

Memory Map..................................................... 316

Register Summary............................................ 317

Buffer Descriptors (BDn)........................................... 313

Interrupt-on-change.................................................. 323

Interrupts .................................................................. 318

and USB Transactions...................................... 318

Oscillator................................................................... 323

Ping-Pong Buffering ................................................. 315

Power Modes............................................................ 320

RAM.......................................................................... 313

Memory Map..................................................... 313

Status and Control.................................................... 310

Universal Serial Bus (USB)............................................... 309

USART

Start Condition (Case 1) ...................................246

Bus Collision During a Repeated

Start Condition (Case 2) ...................................246

Bus Collision During a Start Condition (SCL = 0) .....245

Bus Collision During a Stop Condition (Case 1) .......247

Bus Collision During a Stop Condition (Case 2) .......247

Bus Collision During Start Condition (SDA only) ......244

Bus Collision for Transmit and Acknowledge............243

CLKOUT and I/O.......................................................368

Clock Synchronization ..............................................232

Clock Timing .............................................................367

Comparator Output ...................................................173

Fail-Safe Clock Monitor (FSCM).................................72

First Start Bit Timing .................................................236

I²C Bus Data.............................................................379

I²C Bus Start/Stop Bits..............................................379

I²C Master Mode (7 or 10-Bit Transmission) ............239

I²C Master Mode (7-Bit Reception)...........................241

I²C Stop Condition Receive or Transmit Mode .........242

INT Pin Interrupt..........................................................94

Internal Oscillator Switch Timing.................................65

Repeat Start Condition..............................................237

Reset Start-up Sequence............................................83

Reset, WDT, OST and Power-up Timer ...................369

Send Break Character Sequence .............................278

SPI Master Mode (CKE = 1, SMP = 1) .....................376

SPI Mode (Master Mode)..........................................209

SPI Slave Mode (CKE = 0) .......................................377

SPI Slave Mode (CKE = 1) .......................................377

Synchronous Reception (Master Mode, SREN) .......282

Synchronous Transmission.......................................280

Synchronous Transmission (Through TXEN) ...........280

Timer0 and Timer1 External Clock ...........................370

Timer1 Incrementing Edge........................................191

Two Speed Start-up....................................................70

USART Synchronous Receive (Master/Slave) .........375

USART Synchronous Transmission (Master/Slave) .375

Wake-up from Interrupt .............................................104

Timing Parameter Symbology...........................................366

Timing Requirements

Synchronous Master Mode

Requirements, Synchronous Receive .............. 375

Requirements, Synchronous Transmission...... 375

Timing Diagram, Synchronous Receive ........... 375

Timing Diagram, Synchronous Transmission... 375

USB .................................................................................. 309

USB Operation.................................................................... 66

V

VREF. SEE ADC Reference Voltage

VREGCON Register ......................................................... 106

W

Wake-up on Break............................................................ 276

Wake-up Using Interrupts................................................. 104

Watchdog Timer (WDT)...................................................... 82

Associated Registers................................................ 111

Modes....................................................................... 108

Specifications ........................................................... 370

WCOL....................................................... 235, 238, 240, 242

WCOL Status Flag.................................... 235, 238, 240, 242

WDTCON Register ........................................................... 110

WPUA Register................................................................. 134

WPUB Register................................................................. 138

Write Protection .................................................................. 55

WWW Address ................................................................. 415

WWW, On-Line Support ..................................................... 11

I²C Bus Data.............................................................380

I2C Bus Start/Stop Bits .............................................379

DS41639A-page 414

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

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To register, access the Microchip web site at

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 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 415

PIC16(L)F1454/5/9

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

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DS41639A-page 416

Preliminary

 2012 Microchip Technology Inc.

PIC16(L)F1454/5/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

[X]⁽¹⁾

PART NO.

X

/XX

XXX

-

Examples:

Device Tape and Reel

Option

Temperature

Range

Package

Pattern

a)

PIC16F1454T - E/SL

Tape and Reel,

Industrial temperature,

SOIC package

b)

c)

PIC16F1459 - I/P

Industrial temperature

PDIP package

Device:

PIC16F1454, PIC16LF1454,

PIC16F1455, PIC16LF1455,

PIC16F1459, PIC16LF1459

PIC16F1459 - E/ML

Extended temperature,

QFN package

Tape and Reel

Option:

Blank = Standard packaging (tube or tray)

T

= Tape and Reel⁽¹⁾

Temperature

Range:

I

E

=

-40C to +85C (Industrial)

-40C to +125C (Extended)

Package:⁽²⁾

ML

P

SS

ST

SO

SL

=

QFN 4x4

Plastic DIP

SSOP

TSSOP

SOIC 20-Lead

SOIC 14-Lead

Note 1:

Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes and

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Check with your Microchip Sales Office

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form-factor package availability, or contact

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Pattern:

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(blank otherwise)

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 417

Worldwide Sales and Service

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Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

China - Xiamen

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

11/29/11

DS41639A-page 418

Preliminary

 2012 Microchip Technology Inc.


型号：	PIC16LF1454T-ESSQTP
厂家：	MICROCHIP
描述：	14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology 二十零分之一十四引脚闪存8位USB单片机与XLP技术闪存微控制器
文件：	总418页 (文件大小：7681K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16LF1454T-ESSQTP [MICROCHIP]

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