PIC16LF1508T-I/SS_技术文档

PIC16(L)F1508/9

20-Pin Flash, 8-Bit Microcontrollers with XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• Only 49 Instructions

• Operating Speed:

- DC – 20 MHz clock input

- DC – 200 ns instruction cycle

• Interrupt Capability with Automatic Context

Saving

• 16-Level Deep Hardware Stack with Optional

Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

eXtreme Low-Power (XLP)

Features(PIC16LF1508/9):

• Sleep Current:

- 20 nA @ 1.8V, typical

• Watchdog Timer Current:

- 260 nA @ 1.8V, typical

• Operating Current:

- 30 A/MHz @ 1.8V, typical

• Secondary Oscillator Current:

- 700 nA @ 32 kHz, 1.8V, typical

Peripheral Features:

•

Analog-to-Digital Converter (ADC):

- 10-bit resolution

- 12 external channels

- Three internal channels:

- Fixed Voltage Reference

- Digital-to-Analog Converter (DAC)

- Temperature Indicator channel

- Auto acquisition capability

- Conversion available during Sleep

Flexible Oscillator Structure:

• 16 MHz Internal Oscillator Block:

- Factory calibrated to ±1%, typical

- Software selectable frequency range from

16 MHz to 31 kHz

• 31 kHz Low-Power Internal Oscillator

• Three External Clock modes up to 20 MHz

Special Microcontroller Features:

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1508/9)

- 2.3V to 5.5V (PIC16F1508/9)

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Programmable Low-Power Brown-out Reset

(LPBOR)

• Extended Watchdog Timer (WDT):

- Programmable period from 1 ms to 256s

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via Two

Pins

• Enhanced Low-Voltage Programming (LVP)

• In-Circuit Debug (ICD) via Two Pins

• Power-Saving Sleep mode:

- Low-Power Sleep mode

- Low-Power BOR (LPBOR)

• Integrated Temperature Indicator

• 128 Bytes High-Endurance Flash

- 100,000 write Flash endurance (minimum)

• 5-Bit Digital-to-Analog Converter (DAC):

- Output available externally

- Positive reference selection

- Internal connections to comparators and ADC

• Two Comparators:

- Rail-to-rail inputs

- Power mode control

- Software controllable hysteresis

• Voltage Reference:

- 1.024V Fixed Voltage Reference (FVR) with

1x, 2x and 4x Gain output levels

• 18 I/O Pins (1 Input-only Pin):

- High current sink/source 25 mA/25 mA

- Individually programmable weak pull-ups

- Individually programmable

Interrupt-on-Change (IOC) pins

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

• Timer2: 8-Bit Timer/Counter with 8-Bit Period

Register, Prescaler and Postscaler

• Four 10-bit PWM modules

Memory:

• Up to 8 Kwords Linear Program Memory

Addressing

• Up to 512 bytes Linear Data Memory Addressing

• High-Endurance Flash Data Memory (HEF)

- 128 bytes if nonvolatile data storage

- 100k erase/write cycles

• Master Synchronous Serial Port (MSSP) with SPI

and I²C with:

- 7-bit address masking

- SMBus/PMBus™ compatibility

 2011-2015 Microchip Technology Inc.

DS40001609E-page 1

PIC16(L)F1508/9

• Numerically Controlled Oscillator (NCO):

- 20-bit accumulator

- 16-bit increment

- True linear frequency control

- High-speed clock input

- Selectable Output modes

- Fixed Duty Cycle (FDC) mode

- Pulse Frequency (PF) mode

• Complementary Waveform Generator (CWG):

- Eight selectable signal sources

- Selectable falling and rising edge dead-band

control

Peripheral Features (Continued):

• Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART)

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

- Auto-wake-up on Start

• Four Configurable Logic Cell (CLC) modules:

- 16 selectable input source signals

- Four inputs per module

- Software control of combinational/sequential

logic/state/clock functions

- AND/OR/XOR/D Flop/D Latch/SR/JK

- Inputs from external and internal sources

- Output available to pins and peripherals

- Operation while in Sleep

- Polarity control

- Four auto-shutdown sources

- Multiple input sources: PWM, CLC, NCO

PIC12(L)F1501/PIC16(L)F150X FAMILY TYPES

Device

PIC12(L)F1501 (1) 1024 64

6

4

8

1

2

1

2/1

4

—

1

—

1

2

4

1

H

—

Y

PIC16(L)F1503 (2) 2048 128 12

PIC16(L)F1507 (3) 2048 128 18 12

PIC16(L)F1508 (4) 4096 256 18 12

PIC16(L)F1509 (4) 8192 512 18 12

—

2

—

1

—

1

H

I/H

2

1

Y

Note 1: Debugging Methods: (I) - Integrated on Chip; (H) - using Debug Header; (E) - using Emulation Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS40001615

2: DS40001607

3: DS40001586

4: DS40001609

PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.

PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers.

PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.

PIC16(L)F1508/9 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.

Note:

For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

DS40001609E-page 2

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

PIN DIAGRAMS

20-pin PDIP, SOIC, SSOP

VDD

1

VSS

20

19

18

RA0/ICSPDAT

RA1/ICSPCLK

RA5

2

3

4

RA4

MCLR/VPP/RA3

17 RA2

RC5

RC4

RC3

RC6

RC7

RB7

16

15

14

RC0

RC1

RC2

5

6

7

8

13 RB4

12

11 RB6

9

RB5

10

Note: See Table 1 for location of all peripheral functions.

20-pin QFN, UQFN

20 19 18

17 16

RA1/ICSPCLK

RA2

15

14

13

12

11

MCLR/VPP/RA3

1

2

3

4

5

RC5

RC4

RC3

PIC16(L)F1508

PIC16(L)F1509

RC0

RC1

RC2

RC6

9

10

7

8

6

Note 1: See Table 1 for location of all peripheral functions.

2: It is recommended that the exposed bottom pad be connected to VSS.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 3

PIC16(L)F1508/9

PIN ALLOCATION TABLE

TABLE 1:

20-PIN ALLOCATION TABLE (PIC16(L)F1508/9)

RA0

RA1

19 16

AN0 DAC1OUT1 C1IN+

—

IOC

Y

ICSPDAT

ICDDAT

—

18 15

17 14

AN1

VREF+

C1IN0-

C2IN0-

CLC4IN1

ICSPCLK

ICDCLK

—

RA2

RA3

RA4

RA5

AN2 DAC1OUT2 C1OUT

T0CKI

T1G⁽¹⁾

CWG1FLT

—

CLC1

CLC1IN0

—

PWM3

—

INT/

IOC

Y

—

4

3

2

1

—

AN3

—

SS⁽¹⁾

—

IOC

MCLR

VPP

20

19

SOSCO

T1G

—

CLKOUT

OSC2

SOSCI

T1CKI

—

NCO1CLK

—

CLKIN

OSC1

RB4

RB5

RB6

RB7

13 10 AN10

—

RX/DT

—

SDA/SDI

—

CLC3IN0

CLC4IN0

—

IOC

—

Y

—

12

11

10

9

8

7

AN11

—

SCL/SCK

—

Y

—

TX/CK

—

CLC3

CLC2

—

Y

RC0 16 13

RC1 15 12

AN4

AN5

C2IN+

—

C1IN1-

C2IN1-

—

NCO1

PWM4

—

RC2 14 11

AN6

AN7

—

C1IN2-

C2IN2-

—

RC3

RC4

7

6

4

3

C1IN3-

C2IN3-

CLC2IN0 PWM2

C2OUT

CWG1B

CLC4

CLC2IN1

CLC1⁽¹⁾PWM1

—

RC5

RC6

RC7

VDD

VSS

5

8

9

1

2

5

—

AN8

AN9

—

SS

SDO

—

CWG1A

—

NCO1⁽¹⁾CLC3IN1

—

6

—

CLC1IN1

—

18

—

VDD

VSS

20 17

—

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

DS40001609E-page 4

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE OF CONTENTS

1.0 Device Overview .......................................................................................................................................................................... 8

2.0 Enhanced Mid-Range CPU........................................................................................................................................................ 13

3.0 Memory Organization................................................................................................................................................................. 15

4.0 Device Configuration.................................................................................................................................................................. 40

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 46

6.0 Resets ........................................................................................................................................................................................ 62

7.0 Interrupts .................................................................................................................................................................................... 70

8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 83

9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 86

10.0 Flash Program Memory Control ................................................................................................................................................. 90

11.0 I/O Ports ................................................................................................................................................................................... 106

12.0 Interrupt-On-Change ................................................................................................................................................................ 119

13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 124

14.0 Temperature Indicator Module ................................................................................................................................................. 126

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 128

16.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 142

17.0 Comparator Module.................................................................................................................................................................. 145

18.0 Timer0 Module ......................................................................................................................................................................... 152

19.0 Timer1 Module with Gate Control............................................................................................................................................. 155

20.0 Timer2 Module ......................................................................................................................................................................... 166

21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 169

22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 223

23.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................. 251

24.0 Configurable Logic Cell (CLC).................................................................................................................................................. 257

25.0 Numerically Controlled Oscillator (NCO) Module..................................................................................................................... 273

26.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 280

27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 292

28.0 Instruction Set Summary.......................................................................................................................................................... 294

29.0 Electrical Specifications............................................................................................................................................................ 309

30.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 339

31.0 Development Support............................................................................................................................................................... 380

32.0 Packaging Information.............................................................................................................................................................. 384

Appendix A: Data Sheet Revision History.......................................................................................................................................... 397

The Microchip Website ...................................................................................................................................................................... 398

Customer Change Notification Service .............................................................................................................................................. 398

Customer Support.............................................................................................................................................................................. 398

Product Identification System ............................................................................................................................................................ 399

 2011-2015 Microchip Technology Inc.

DS40001609E-page 5

PIC16(L)F1508/9

TO OUR VALUED CUSTOMERS

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enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Register on our website at www.microchip.com to receive the most current information on all of our products.

DS40001609E-page 6

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

1.0

DEVICE OVERVIEW

The block diagram of these devices are shown in

Figure 1-1, the available peripherals are shown in

Table 1-1, and the pinout descriptions are shown in

Table 1-2.

TABLE 1-1:

DEVICE PERIPHERAL SUMMARY

Peripheral

Analog-to-Digital Converter (ADC)

Complementary Wave Generator (CWG)

Digital-to-Analog Converter (DAC)

●

Enhanced Universal

Synchronous/Asynchronous Receiver/

Transmitter (EUSART)

Fixed Voltage Reference (FVR)

●

Numerically Controlled Oscillator (NCO)

Temperature Indicator

Comparators

C1

●

C2

Configurable Logic Cell (CLC)

CLC1

●

CLC2

CLC3

CLC4

Master Synchronous Serial Ports

MSSP1

●

PWM Modules

PWM1

●

PWM2

PWM3

PWM4

Timers

Timer0

●

Timer1

Timer2

DS40001609E-page 8

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 1-1:

PIC16(L)F1508/9 BLOCK DIAGRAM

Rev. 10-000039A

8/1/2013

Program

Flash Memory

RAM

PORTA

OSC2/CLKOUT

Timing

Generation

PORTB

PORTC

CPU

OSC1/CLKIN

INTRC

Oscillator

(Note 3)

MCLR

Temp

Indicator

ADC

10-bit

MSSP1

TMR2

TMR1

TMR0

C2

C1

DAC

FVR

EUSART

CWG1

NCO1

CLC4

CLC3

CLC2

CLC1

PWM4

PWM3

PWM2

PWM1

Note 1: See applicable chapters for more information on peripherals.

2: See Table 1-1 for peripherals on specific devices.

3: See Figure 2-1.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 9

PIC16(L)F1508/9

TABLE 1-2:

PIC16(L)F1508/9 PINOUT DESCRIPTION

Input Output

Name

Function

Description

Type

RA0/AN0/C1IN+/DAC1OUT1/

ICSPDAT/ICDDAT

RA0

AN0

TTL

AN

—

CMOS General purpose I/O.

—

ADC Channel input.

C1IN+

DAC1OUT1

ICSPDAT

ICDDAT

RA1

Comparator positive input.

AN

Digital-to-Analog Converter output.

ST

CMOS ICSP™ Data I/O.

ST

CMOS In-Circuit Debug data.

CMOS General purpose I/O.

RA1/AN1/CLC4IN1/VREF+/

C1IN0-/C2IN0-/ICSPCLK/

ICDCLK

TTL

AN

ST

AN1

—

ADC Channel input.

CLC4IN1

VREF+

C1IN0-

C2IN0-

ICSPCLK

ICDCLK

RA2

Configurable Logic Cell source input.

ADC Positive Voltage Reference input.

Comparator negative input.

ICSP Programming Clock.

In-Circuit Debug Clock.

AN

ST

RA2/AN2/C1OUT/DAC1OUT2/

T0CKI/INT/PWM3/CLC1/

CWG1FLT

ST

CMOS General purpose I/O.

ADC Channel input.

CMOS Comparator output.

AN2

AN

—

C1OUT

DAC1OUT2

T0CKI

INT

—

AN

—

Digital-to-Analog Converter output.

ST

Timer0 clock input.

External interrupt.

ST

—

PWM3

CLC1

—

CMOS PWM output.

—

CMOS Configurable Logic Cell source output.

CWG1FLT

RA3

ST

—

Complementary Waveform Generator Fault input.

General purpose input with IOC and WPU.

Configurable Logic Cell source input.

Programming voltage.

(1)

RA3/CLC1IN0/VPP/T1G /SS

MCLR

/

TTL

ST

CLC1IN0

VPP

HV

ST

T1G

Timer1 Gate input.

SS

ST

Slave Select input.

MCLR

RA4

ST

Master Clear with internal pull-up.

RA4/AN3/SOSCO/

CLKOUT/T1G

TTL

AN

XTAL

—

CMOS General purpose I/O.

ADC Channel input.

AN3

—

SOSCO

CLKOUT

T1G

XTAL Secondary Oscillator Connection.

CMOS FOSC/4 output.

ST

—

Timer1 Gate input.

RA5/CLKIN/T1CKI/NCO1CLK/

SOSCI

RA5

TTL

CMOS

ST

CMOS General purpose I/O.

CLKIN

T1CKI

NCO1CLK

SOSCI

—

External clock input (EC mode).

Timer1 clock input.

ST

Numerically Controlled Oscillator Clock source input.

XTAL

XTAL Secondary Oscillator Connection.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open-Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

DS40001609E-page 10

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 1-2:

PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

RB4/AN10/CLC3IN0/SDA/SDI

RB4

AN10

CLC3IN0

SDA

TTL

AN

ST

CMOS General purpose I/O.

—

ADC Channel input.

Configurable Logic Cell source input.

2

I C

OD

—

I C data input/output.

SDI

CMOS

TTL

AN

SPI data input.

RB5/AN11/CLC4IN0/RX/DT

RB5

CMOS General purpose I/O.

AN11

CLC4IN0

RX

—

ADC Channel input.

ST

Configurable Logic Cell source input.

USART asynchronous input.

ST

DT

ST

CMOS USART synchronous data.

RB6/SCL/SCK

RB6

TTL

CMOS General purpose I/O.

2

SCL

I C

OD

I C clock.

SCK

ST

TTL

—

CMOS SPI clock.

RB7/CLC3/TX/CK

RB7

CMOS General purpose I/O.

CLC3

TX

CMOS Configurable Logic Cell source output.

CMOS USART asynchronous transmit.

CMOS USART synchronous clock.

CMOS General purpose I/O.

—

CK

ST

TTL

AN

—

RC0/AN4/CLC2/C2IN+

RC0

AN4

—

ADC Channel input.

CMOS Configurable Logic Cell source output.

Comparator positive input.

CMOS General purpose I/O.

CLC2

C2IN+

RC1

AN

TTL

AN

—

RC1/AN5/C1IN1-/C2IN1-/PWM4/

NCO1

AN5

—

ADC Channel input.

C1IN1-

C2IN1-

PWM4

NCO1

RC2

Comparator negative input.

CMOS PWM output.

—

CMOS Numerically Controlled Oscillator is source output.

CMOS General purpose I/O.

RC2/AN6/C1IN2-/C2IN2-

TTL

AN

TTL

AN

—

AN6

—

ADC Channel input.

C1IN2-

C2IN2-

RC3

Comparator negative input.

RC3/AN7/C1IN3-/C2IN3-/PWM2/

CLC2IN0

CMOS General purpose I/O.

AN7

—

ADC Channel input.

C1IN3-

C2IN3-

PWM2

CLC2IN0

RC4

Comparator negative input.

CMOS PWM output.

ST

TTL

—

Configurable Logic Cell source input.

RC4/C2OUT/CLC2IN1/CLC4/

CWG1B

CMOS General purpose I/O.

CMOS Comparator output.

C2OUT

CLC2IN1

CLC4

CWG1B

ST

—

Configurable Logic Cell source input.

CMOS Configurable Logic Cell source output.

CMOS CWG complementary output.

—

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open-Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 11

PIC16(L)F1508/9

TABLE 1-2:

PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

(1)

RC5/PWM1/CLC1

CWG1A

/

RC5

PWM1

CLC1

CWG1A

RC6

TTL

—

CMOS General purpose I/O.

CMOS PWM output.

—

CMOS Configurable Logic Cell source output.

CMOS CWG primary output.

—

(1)

RC6/AN8/NCO1 /CLC3IN1/

SS

TTL

AN

CMOS General purpose I/O.

AN8

—

ADC Channel input.

NCO1

CLC3IN1

SS

—

CMOS Numerically Controlled Oscillator source output.

ST

—

Configurable Logic Cell source input.

Slave Select input.

ST

RC7/AN9/CLC1IN1/SDO

RC7

TTL

AN

CMOS General purpose I/O.

AN9

—

ADC Channel input.

CLC1IN1

SDO

ST

Configurable Logic Cell source input.

—

CMOS SPI data output.

VDD

VSS

VDD

Power

—

Positive supply.

VSS

Ground reference.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open-Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

DS40001609E-page 12

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

2.0

ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

Relative addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read

program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

FIGURE 2-1:

CORE BLOCK DIAGRAM

Rev. 10-000055A

7/30/2013

15

Configuration

15

Data Bus

8

Program Counter

Flash

Program

Memory

16-Level Stack

(15-bit)

RAM

14

Program

Bus

12

Program Memory

Read (PMR)

RAM Addr

Addr MUX

Instruction Reg

Indirect

Addr

Direct Addr

7

12

5

12

BSR Reg

15

FSR0 Reg

STATUS Reg

MUX

15

FSR1 Reg

8

3

Power-up

Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Instruction

Decode and

Control

ALU

8

CLKIN

Timing

Generation

CLKOUT

W Reg

Internal

Oscillator

Block

VDD

VSS

 2011-2015 Microchip Technology Inc.

DS40001609E-page 13

PIC16(L)F1508/9

2.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 7.5 “Automatic Context Saving”,

for more information.

2.2

16-Level Stack with Overflow and

Underflow

These devices have a hardware stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Under-

flow will set the appropriate bit (STKOVF or STKUNF)

in the PCON register, and if enabled, will cause a soft-

ware Reset. See Section 3.5 “Stack” for more details.

2.3

File Select Registers

There are two 16-bit File Select Registers (FSR).

FSRs can access all file registers and program mem-

ory, which allows one Data Pointer for all memory.

When an FSR points to program memory, there is one

additional instruction cycle in instructions using INDF

to allow the data to be fetched. General purpose mem-

ory can now also be addressed linearly, providing the

ability to access contiguous data larger than 80 bytes.

There are also new instructions to support the FSRs.

See Section 3.6 “Indirect Addressing” for more

details.

2.4

Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See Section

28.0 “Instruction Set Summary” for more details.

DS40001609E-page 14

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

The following features are associated with access and

control of program memory and data memory:

3.0

MEMORY ORGANIZATION

These devices contain the following types of memory:

• PCL and PCLATH

• Stack

• Program Memory

- Configuration Words

- Device ID

• Indirect Addressing

- User ID

3.1

Program Memory Organization

- Flash Program Memory

• Data Memory

The enhanced mid-range core has a 15-bit program

counter capable of addressing a 32K x 14 program

memory space. Table 3-1 shows the memory sizes

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

implemented. Accessing

a location above these

boundaries will cause a wrap-around within the

implemented memory space. The Reset vector is at

0000h and the interrupt vector is at 0004h (See

Figure 3-1).

3.2

High-Endurance Flash

This device has a 128 byte section of high-endurance

program Flash memory (PFM) in lieu of data EEPROM.

This area is especially well suited for nonvolatile data

storage that is expected to be updated frequently over

the life of the end product. See Section 10.2 “Flash

Program Memory Overview” for more information on

writing data to PFM. See Section 3.2.1.2 “Indirect

Read with FSR” for more information about using the

FSR registers to read byte data stored in PFM.

TABLE 3-1:

Device

DEVICE SIZES AND ADDRESSES

Program Memory

Space (Words)

Last Program Memory

Address

High-Endurance Flash

Memory Address Range ⁽¹⁾

PIC16LF1508

PIC16F1508

4,096

8,192

0FFFh

1FFFh

0F80h-0FFFh

1F80h-1FFFh

PIC16LF1509

PIC16F1509

Note 1: High-endurance Flash applies to low byte of each address in the range.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 15

PIC16(L)F1508/9

FIGURE 3-1:

PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F1508

PIC16(L)F1509

Rev. 10-000040B

7/30/2013

PC<14:0>

PIC16(L)F1508

Rev. 10-000040A

7/30/2013

CALL, CALLW

15

RETURN, RETLW

Interrupt, RETFIE

PC<14:0>

15

Stack Level 0

Stack Level 1

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

0000h

Stack Level 15

Interrupt Vector

Page 0

0004h

0005h

0000h

Reset Vector

07FFh

0800h

Interrupt Vector

Page 0

0004h

0005h

Page 1

Page 2

On-chip

Program

Memory

0FFFh

1000h

On-chip

Program

Memory

07FFh

0800h

17FFh

1800h

Page 1

0FFFh

1000h

Page 3

Rollover to Page 0

1FFFh

2000h

Rollover to Page 0

Rollover to Page 3

7FFFh

Rollover to Page 1

7FFFh

DS40001609E-page 16

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

3.2.1

READING PROGRAM MEMORY AS

DATA

3.2.1.2

Indirect Read with FSR

The program memory can be accessed as data by set-

ting bit 7 of the FSRxH register and reading the match-

ing INDFx register. The MOVIWinstruction will place the

lower eight bits of the addressed word in the W register.

Writes to the program memory cannot be performed via

the INDF registers. Instructions that access the pro-

gram memory via the FSR require one extra instruction

cycle to complete. Example 3-2 demonstrates access-

ing the program memory via an FSR.

There are two methods of accessing constants in

program memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

3.2.1.1

RETLWInstruction

The RETLWinstruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

The HIGHoperator will set bit<7> if a label points to a

location in program memory.

EXAMPLE 3-1:

constants

BRW

RETLWINSTRUCTION

EXAMPLE 3-2:

ACCESSING PROGRAM

MEMORY VIA FSR

;Add Index in W to

;program counter to

;select data

;Index0 data

;Index1 data

constants

DW DATA0

;First constant

;Second constant

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

DW DATA1

DW DATA2

DW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

ADDLW LOW constants

MOVWF FSR1L

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

MOVLW HIGH constants;MSb sets

automatically

;… THE CONSTANT IS IN W

MOVWF FSR1H

BTFSC STATUS, C

;carry from ADDLW?

;yes

The BRW instruction makes this type of table very

simple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRWinstruction is not available so the older table read

method must be used.

INCF

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

FSR1h, f

 2011-2015 Microchip Technology Inc.

DS40001609E-page 17

PIC16(L)F1508/9

3.3.1

CORE REGISTERS

3.3

Data Memory Organization

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in Table 3-2. For detailed

information, see Table 3-8.

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

TABLE 3-2:

CORE REGISTERS

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.6 “Indirect

Addressing” for more information.

Addresses

BANKx

x00h or x80h

x01h or x81h

x02h or x82h

x03h or x83h

x04h or x84h

x05h or x85h

x06h or x86h

x07h or x87h

x08h or x88h

x09h or x89h

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

Data memory uses a 12-bit address. The upper five bits

of the address define the Bank address and the lower

seven bits select the registers/RAM in that bank.

WREG

PCLATH

INTCON

x0Ah or x8Ah

x0Bh or x8Bh

DS40001609E-page 18

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u= unchanged).

3.3.1.1

STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section

28.0 “Instruction Set Summary”).

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

REGISTER 3-1:

STATUS: STATUS REGISTER

U-0

—

U-0

—

U-0

—

R-1/q

TO

R-1/q

PD

R/W-0/u

Z

R/W-0/u

DC⁽¹⁾

R/W-0/u

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-5

bit 4

Unimplemented: Read as ‘0’

TO: Time-Out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

bit 3

bit 2

bit 1

bit 0

PD: Power-Down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 19

PIC16(L)F1508/9

3.3.2

SPECIAL FUNCTION REGISTER

FIGURE 3-2:

BANKED MEMORY

PARTITIONING

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch

through x1Fh/x9Fh). The registers associated with the

operation of the peripherals are described in the appro-

priate peripheral chapter of this data sheet.

Rev. 10-000041A

7/30/2013

7-bit Bank Offset

00h

Memory Region

Core Registers

(12 bytes)

0Bh

0Ch

3.3.3

GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank. The Special Function Registers occupy the 20

bytes after the core registers of every data memory

bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

Special Function Registers

(20 bytes maximum)

1Fh

20h

3.3.3.1

Linear Access to GPR

The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section

3.6.2 “Linear Data Memory” for more information.

General Purpose RAM

(80 bytes maximum)

3.3.4

COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

6Fh

70h

Common RAM

(16 bytes)

7Fh

DS40001609E-page 20

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PIC16(L)F1508/9

TABLE 3-7:

PIC16(L)F1508/9 MEMORY MAP, BANK 30-31

Bank 30

Bank 31

—

F0Ch

F8Ch

—

F0Dh

F0Eh

F0Fh

F10h

F11h

F12h

F13h

F14h

F15h

F16h

F17h

F18h

F19h

F1Ah

F1Bh

F1Ch

F1Dh

F1Eh

F1Fh

F20h

F21h

F22h

F23h

F24h

F25h

F26h

F27h

F28h

F29h

F2Ah

F2Bh

F2Ch

F2Dh

F2Eh

F2Fh

F30h

—

Unimplemented

Read as ‘0’

CLCDATA

CLC1CON

CLC1POL

CLC1SEL0

CLC1SEL1

CLC1GLS0

CLC1GLS1

CLC1GLS2

CLC1GLS3

CLC2CON

CLC2POL

CLC2SEL0

CLC2SEL1

CLC2GLS0

CLC2GLS1

CLC2GLS2

CLC2GLS3

CLC3CON

CLC3POL

CLC3SEL0

CLC3SEL1

CLC3GLS0

CLC3GLS1

CLC3GLS2

CLC3GLS3

CLC4CON

CLC4POL

CLC4SEL0

CLC4SEL1

CLC4GLS0

CLC4GLS1

CLC4GLS2

CLC4GLS3

FE3h

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

FECh

FEDh

FEEh

FEFh

STATUS_SHAD

WREG_SHAD

BSR_SHAD

PCLATH_SHAD

FSR0L_SHAD

FSR0H_SHAD

FSR1L_SHAD

FSR1H_SHAD

—

STKPTR

TOSL

TOSH

Unimplemented

Read as ‘0’

F6Fh

Legend:

= Unimplemented data memory locations, read as ‘0’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 25

PIC16(L)F1508/9

3.3.6

CORE FUNCTION REGISTERS

SUMMARY

The Core Function registers listed in Table 3-8 can be

addressed from any Bank.

TABLE 3-8:

CORE FUNCTION REGISTERS SUMMARY

Value on

POR, BOR other Resets

Value on all

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0-31

x00h or

x80h

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

INDF0

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 0000 0000 0000

x01h or

x81h

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

INDF1

PCL

x02h or

x82h

Program Counter (PC) Least Significant Byte

x03h or

x83h

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

x04h or

x84h

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

x05h or

x85h

x06h or

x86h

x07h or

x87h

x08h or

x88h

—

BSR<4:0>

x09h or

x89h

WREG

PCLATH

INTCON

Working Register

x0Ahor

x8Ah

—

Write Buffer for the upper 7 bits of the Program Counter

PEIE TMR0IE INTE IOCIE TMR0IF

x0Bhor

x8Bh

GIE

INTF

IOCIF

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

DS40001609E-page 26

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 3-9:

SPECIAL FUNCTION REGISTER SUMMARY

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0

00Ch

00Dh

00Eh

010h

011h

PORTA

PORTB

PORTC

—

RA5

RB5

RC5

RA4

RB4

RC4

RA3

—

RA2

—

RA1

—

RA0

—

--xx xxxx --xx xxxx

xxxx ---- xxxx ----

xxxx xxxx xxxx xxxx

RB7

RB6

RC6

RC7

RC3

RC2

RC1

RC0

Unimplemented

TMR1GIF

OSFIF

—

PIR1

ADIF

C2IF

—

RCIF

C1IF

—

TXIF

—

SSP1IF

BCL1IF

CLC4IF

—

TMR2IF

—

TMR1IF

—

0000 0-00 0000 0-00

000- -00- 000- -00-

---- 0000 ---- 0000

012h

013h

014h

015h

016h

017h

018h

019h

PIR2

NCO1IF

CLC3IF

PIR3

—

CLC2IF

CLC1IF

—

Unimplemented

—

TMR0

TMR1L

TMR1H

T1CON

T1GCON

Holding Register for the 8-bit Timer0 Count

xxxx xxxx uuuu uuuu

0000 00-0 uuuu uu-u

0000 0x00 uuuu uxuu

Holding Register for the Least Significant Byte of the 16-bit TMR1 Count

Holding Register for the Most Significant Byte of the 16-bit TMR1 Count

TMR1CS<1:0>

TMR1GE T1GPOL

T1CKPS<1:0>

T1GTM T1GSPM

T1OSCEN T1SYNC

—

TMR1ON

T1GGO/

DONE

T1GVAL

T1GSS<1:0>

01Ah

01Bh

01Ch

TMR2

PR2

Timer2 Module Register

Timer2 Period Register

—

0000 0000 0000 0000

1111 1111 1111 1111

-000 0000 -000 0000

T2CON

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

01Dh

to

—

Unimplemented

—

01Fh

Bank 1

08Ch

08Dh

08Eh

08Fh

090h

091h

092h

093h

094h

095h

096h

097h

098h

099h

09Ah

09Bh

09Ch

09Dh

09Eh

09Fh

(2)

TRISA

TRISB

TRISC

—

TRISA5

TRISB5

TRISC5

TRISA4

—

TRISA2

—

TRISA1

TRISA0

—

--11 1111 --11 1111

1111 ---- 1111 ----

1111 1111 1111 1111

TRISB7

TRISB6

TRISC6

TRISB4

TRISC4

—

TRISC7

TRISC3

TRISC2

TRISC1

TRISC0

Unimplemented

TMR1GIE

OSFIE

—

PIE1

ADIE

C2IE

—

RCIE

C1IE

—

TXIE

—

SSP1IE

BCL1IE

CLC4IE

—

TMR2IE

—

TMR1IE

—

0000 0-00 0000 0-00

000- 00-- 000- 00--

---- 0000 ---- 0000

PIE2

NCO1IE

CLC3IE

PIE3

—

CLC2IE

CLC1IE

—

Unimplemented

—

OPTION_REG

PCON

WDTCON

—

WPUEN

STKOVF

—

INTEDG

STKUNF

—

TMR0CS

—

TMR0SE

RWDT

PSA

PS<2:0>

POR

1111 1111 1111 1111

00-1 11qq qq-q qquu

--01 0110 --01 0110

RMCLR

RI

BOR

WDTPS<4:0>

SWDTEN

Unimplemented

—

OSCCON

OSCSTAT

ADRESL

ADRESH

ADCON0

ADCON1

ADCON2

IRCF<3:0>

—

SCS<1:0>

-011 1-00 -011 1-00

0-q0 --00 q-qq --qq

xxxx xxxx uuuu uuuu

-000 0000 -000 0000

0000 --00 0000 --00

0000 ---- 0000 ----

SOSCR

—

OSTS

HFIOFR

—

LFIOFR

HFIOFS

ADC Result Register Low

ADC Result Register High

—

CHS<4:0>

GO/DONE

ADON

—

ADFM

ADCS<2:0>

—

ADPREF<1:0>

TRIGSEL<3:0>

—

Legend:

Note 1:

2:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

PIC16F1508/9 only.

Unimplemented, read as ‘1’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 27

PIC16(L)F1508/9

TABLE 3-9:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 2

10Ch

10Dh

10Eh

LATA

LATB

LATC

—

LATA5

LATB5

LATC5

LATA4

LATB4

LATC4

—

LATA2

—

LATA1

—

LATA0

—

--xx -xxx --uu -uuu

xxxx ---- uuuu ----

xxxx xxxx uuuu uuuu

LATB7

LATB6

LATC6

LATC7

LATC3

LATC2

LATC1

LATC0

10Fh

Unimplemented

C1ON

—

110h

—

111h

CM1CON0

C1OUT

C1OE

C1POL

—

C1SP

C1HYS

C1SYNC

0000 -100 0000 -100

112h

to

—

Unimplemented

—

114h

115h

116h

117h

118h

119h

CMOUT

—

MC2OUT

—

MC1OUT

BORRDY

---- --00 ---- --00

10-- ---q uu-- ---u

0q00 0000 0q00 0000

0-00 -0-- 0-00 -0--

---0 0000 ---0 0000

BORCON

FVRCON

DAC1CON0

DAC1CON1

SBOREN

BORFS

FVREN

DACEN

—

FVRRDY

TSEN

DACOE1

—

TSRNG

DACOE2

CDAFVR<1:0>

ADFVR<1:0>

—

DACPSS

—

DACR<4:0>

11Ah

to

—

Unimplemented

—

11Ch

11Dh

11Eh

11Fh

Bank 3

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

APFCON

—

SSSEL

T1GSEL

—

CLC1SEL

NCO1SEL

---0 0-00 ---0 0-00

—

Unimplemented

—

ANSELA

ANSELB

ANSELC

—

ANSB5

—

ANSA4

ANSB4

—

ANSA2

—

ANSA1

—

ANSA0

—

---1 -111 ---1 -111

--11 ---- --11 ----

11-- 1111 11-- 1111

—

ANSC7

ANSC6

ANSC3

ANSC2

ANSC1

ANSC0

Unimplemented

—

PMADRL

PMADRH

PMDATL

PMDATH

PMCON1

PMCON2

VREGCON⁽¹⁾

—

Flash Program Memory Address Register Low Byte

0000 0000 0000 0000

1000 0000 1000 0000

xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

1000 x000 1000 q000

0000 0000 0000 0000

---- --01 ---- --01

(2)

—

Flash Program Memory Address Register High Byte

Flash Program Memory Read Data Register Low Byte

—

Flash Program Memory Read Data Register High Byte

(2)

—

CFGS

LWLO

FREE

WRERR

WREN

WR

RD

Flash Program Memory Control Register 2

—

VREGPM

Reserved

Unimplemented

—

RCREG

TXREG

SPBRGL

SPBRGH

RCSTA

TXSTA

USART Receive Data Register

USART Transmit Data Register

0000 0000 0000 0000

0000 000x 0000 000x

0000 0010 0000 0010

01-0 0-00 01-0 0-00

Baud Rate Generator Data Register Low

Baud Rate Generator Data Register High

SPEN

CSRC

RX9

TX9

SREN

TXEN

—

CREN

SYNC

SCKP

ADDEN

SENDB

BRG16

FERR

BRGH

—

OERR

TRMT

WUE

RX9D

TX9D

BAUDCON

ABDOVF

RCIDL

ABDEN

Legend:

Note 1:

2:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

PIC16F1508/9 only.

Unimplemented, read as ‘1’.

DS40001609E-page 28

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 3-9:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 4

20Ch

WPUA

WPUB

—

WPUA5

WPUB5

WPUA4

WPUB4

WPUA3

—

WPUA2

—

WPUA1

—

WPUA0

—

--11 1111 --11 1111

1111 ---- 1111 ----

20Dh

WPUB7

WPUB6

E20Eh

to

—

Unimplemented

—

212h

213h

214h

215h

216h

217h

SSP1MSK

SSP1STAT

SSP1CON1

SSP1CON2

SSP1CON3

MSK<7:0>

1111 1111 1111 1111

0000 0000 0000 0000

SMP

CKE

D/A

P

S

R/W

UA

BF

WCOL

SSPOV

SSPEN

ACKDT

SCIE

CKP

SSPM<3:0>

GCEN

ACKSTAT

PCIE

ACKEN

BOEN

RCEN

PEN

RSEN

AHEN

SEN

ACKTIM

SDAHT

SBCDE

DHEN

218h

to

21Fh

—

Unimplemented

—

Bank 5

28Ch

to

29Fh

Bank 6

30Ch

to

31Fh

Bank 7

38Ch

to

390h

391h

392h

393h

394h

395h

396h

IOCAP

IOCAN

IOCAF

IOCBP

IOCBN

IOCBF

—

IOCAP5

IOCAN5

IOCAF5

IOCBP5

IOCBN5

IOCBF5

IOCAP4

IOCAN4

IOCAF4

IOCBP4

IOCBN4

IOCBF4

IOCAP3

IOCAN3

IOCAF3

—

IOCAP2

IOCAN2

IOCAF2

—

IOCAP1

IOCAN1

IOCAF1

—

IOCAP0

IOCAN0

IOCAF0

—

--00 0000 --00 0000

0000 ---- 0000 ----

—

IOCBP7

IOCBP6

IOCBN7

IOCBF7

IOCBN6

IOCBF6

—

397h

to

39Fh

—

Unimplemented

—

Bank 8

40Ch

to

41Fh

Bank 9

48Ch

to

497h

498h

499h

49Ah

49Bh

49Ch

49Dh

49Eh

49Fh

NCO1ACCL

NCO1ACCH

NCO1ACCU

NCO1INCL

NCO1INCH

—

NCO1ACC<7:0>

NCO1ACC<15:8>

NCO1ACC<19:16>

NCO1INC<7:0>

0000 0000 0000 0000

0000 0001 0000 0001

0000 0000 0000 0000

NCO1INC<15:8>

Unimplemented

N1EN

—

NCO1CON

NCO1CLK

N1OE

N1OUT

N1POL

—

N1PFM

0000 ---0 0000 ---0

0000 --00 0000 --00

N1PWS<2:0>

N1CKS<1:0>

Legend:

Note 1:

2:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

PIC16F1508/9 only.

Unimplemented, read as ‘1’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 29

PIC16(L)F1508/9

TABLE 3-9:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 10

50Ch

to

51Fh

—

Unimplemented

—

Bank 11

58Ch

to

59Fh

—

Bank 12

60Ch

to

—

610h

611h

PWM1DCL

PWM1DCH

PWM1CON0

PWM2DCL

PWM2DCH

PWM2CON0

PWM3DCL

PWM3DCH

PWM3CON0

PWM4DCL

PWM4DCH

PWM4CON0

PWM1DCL<7:6>

—

00-- ---- 00-- ----

xxxx xxxx uuuu uuuu

0000 ---- 0000 ----

00-- ---- 00-- ----

xxxx xxxx uuuu uuuu

0000 ---- 0000 ----

00-- ---- 00-- ----

xxxx xxxx uuuu uuuu

0000 ---- 0000 ----

00-- ---- 00-- ----

xxxx xxxx uuuu uuuu

0000 ---- 0000 ----

612h

613h

614h

615h

616h

617h

618h

619h

61Ah

61Bh

61Ch

PWM1DCH<7:0>

PWM1EN

PWM1OE PWM1OUT PWM1POL

—

PWM2DCL<7:6>

—

PWM2DCH<7:0>

PWM2EN

PWM2OE PWM2OUT PWM2POL

—

PWM3DCL<7:6>

—

PWM3DCH<7:0>

PWM3EN

PWM3OE PWM3OUT PWM3POL

—

PWM4DCL<7:6>

—

PWM4DCH<7:0>

PWM4OE PWM4OUT PWM4POL

PWM4EN

—

61Dh

to

—

Unimplemented

—

61Fh

Bank 13

68Ch

to

—

Unimplemented

—

690h

691h

CWG1DBR

CWG1DBF

CWG1CON0

CWG1CON1

CWG1CON2

—

CWG1DBR<5:0>

CWG1DBF<5:0>

--00 0000 --00 0000

--xx xxxx --xx xxxx

0000 0--0 0000 0--0

0000 -000 0000 -000

692h

693h

694h

695h

G1EN

G1OEB

G1OEA

G1POLB

—

G1POLA

—

G1CS0

G1ASDLB<1:0>

G1ASDLA<1:0>

—

G1IS<2:0>

G1ASE

G1ARSEN

—

G1ASDSC2 G1ASDSC1 G1ASDSFLT G1ASDSCLC2 00-- 0000 00-- 0000

696h

to

—

Unimplemented

—

69Fh

Legend:

Note 1:

2:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

PIC16F1508/9 only.

Unimplemented, read as ‘1’.

DS40001609E-page 30

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 3-9:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Banks 14-29

x0Ch/

x8Ch

—

x1Fh/

x9Fh

—

Unimplemented

—

Bank 30

F0Ch

to

—

Unimplemented

—

F0Eh

F0Fh

CLCDATA

CLC1CON

CLC1POL

CLC1SEL0

CLC1SEL1

CLC1GLS0

CLC1GLS1

CLC1GLS2

CLC1GLS3

CLC2CON

CLC2POL

CLC2SEL0

CLC2SEL1

CLC2GLS0

CLC2GLS1

CLC2GLS2

CLC2GLS3

CLC3CON

CLC3POL

CLC3SEL0

CLC3SEL1

CLC3GLS0

CLC3GLS1

CLC3GLS2

CLC3GLS3

CLC4CON

CLC4POL

CLC4SEL0

CLC4SEL1

CLC4GLS0

CLC4GLS1

CLC4GLS2

CLC4GLS3

CLC3CON

CLC3POL

CLC4GLS3

—

LC1EN

LC1POL

—

LC1OE

—

LC1INTP

—

MLC4OUT MLC3OUT MLC2OUT

MLC1OUT ---- 0000 ---- 0000

F10h

F11h

F12h

F13h

F14h

F15h

F16h

F17h

F18h

F19h

F1Ah

F1Bh

F1Ch

F1Dh

F1Eh

F1Fh

F20h

F21h

F22h

F23h

F24h

F25h

F26h

F27h

F28h

F29h

F2Ah

F2Bh

F2Ch

F2Dh

F2Eh

F2Fh

F20h

F21h

F2Fh

LC1OUT

—

LC1INTN LC1MODE<2:0>

0000 0000 0000 0000

LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu

LC1D2S<2:0>

LC1D4S<2:0>

—

LC1D1S<2:0>

LC1D3S<2:0>

-xxx -xxx -uuu -uuu

—

LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T

LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T

LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T

LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T

LC1G1D1N xxxx xxxx uuuu uuuu

LC1G2D1N xxxx xxxx uuuu uuuu

LC1G3D1N xxxx xxxx uuuu uuuu

LC1G4D1N xxxx xxxx uuuu uuuu

LC2MODE<2:0> 0000 0000 0000 0000

LC2EN

LC2POL

—

LC2OE

—

LC2OUT

—

LC2INTP

—

LC2INTN

LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu

LC2D2S<2:0>

LC2D4S<2:0>

—

LC2D1S<2:0>

LC2D3S<2:0>

-xxx -xxx -uuu -uuu

—

LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T

LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T

LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T

LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T

LC2G1D1N xxxx xxxx uuuu uuuu

LC2G2D1N xxxx xxxx uuuu uuuu

LC2G3D1N xxxx xxxx uuuu uuuu

LC2G4D1N xxxx xxxx uuuu uuuu

LC3MODE<2:0> 0000 0000 0000 0000

LC3EN

LC3POL

—

LC3OE

—

LC3OUT

—

LC3INTP

—

LC3INTN

LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu

LC3D2S<2:0>

LC3D4S<2:0>

—

LC3D1S<2:0>

LC3D3S<2:0>

-xxx -xxx -uuu -uuu

—

LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T

LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T

LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T

LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T

LC3G1D1N xxxx xxxx uuuu uuuu

LC3G2D1N xxxx xxxx uuuu uuuu

LC3G3D1N xxxx xxxx uuuu uuuu

LC3G4D1N xxxx xxxx uuuu uuuu

LC4MODE<2:0> 0000 0000 0000 0000

LC4EN

LC4POL

—

LC4OE

—

LC4OUT

—

LC4INTP

—

LC4INTN

LC4G4POL LC4G3POL LC4G2POL LC4G1POL 0--- xxxx 0--- uuuu

LC4D2S<2:0>

LC4D4S<2:0>

—

LC4D1S<2:0>

LC4D3S<2:0>

-xxx -xxx -uuu -uuu

—

LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T

LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T

LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T

LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T

LC4G1D1N xxxx xxxx uuuu uuuu

LC4G2D1N xxxx xxxx uuuu uuuu

LC4G3D1N xxxx xxxx uuuu uuuu

LC4G4D1N xxxx xxxx uuuu uuuu

LC3MODE<2:0> 0000 0000 0000 0000

LC3EN

LC3OE

—

LC3OUT

—

LC3INTP

—

LC3INTN

LC3POL

LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu

LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T

LC4G4D1N xxxx xxxx uuuu uuuu

F30h

to

—

Unimplemented

—

F6Fh

Legend:

Note 1:

2:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

PIC16F1508/9 only.

Unimplemented, read as ‘1’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 31

PIC16(L)F1508/9

TABLE 3-9:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 31

F8Ch

—

FE3h

—

Unimplemented

—

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

STATUS_

SHAD

—

Z_SHAD

DC_SHAD

C_SHAD

---- -xxx ---- -uuu

xxxx xxxx uuuu uuuu

---x xxxx ---u uuuu

-xxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

WREG_

SHAD

Working Register Shadow

BSR_

—

Bank Select Register Shadow

SHAD

PCLATH_

SHAD

Program Counter Latch High Register Shadow

FSR0L_

SHAD

Indirect Data Memory Address 0 Low Pointer Shadow

Indirect Data Memory Address 0 High Pointer Shadow

Indirect Data Memory Address 1 Low Pointer Shadow

Indirect Data Memory Address 1 High Pointer Shadow

Unimplemented

FSR0H_

SHAD

FSR1L_

SHAD

FSR1H_

SHAD

FECh

FEDh

FEEh

FEFh

—

Current Stack Pointer

---1 1111 ---1 1111

xxxx xxxx uuuu uuuu

-xxx xxxx -uuu uuuu

STKPTR

TOSL

TOSH

Top-of-Stack Low byte

Top-of-Stack High byte

—

Legend:

Note 1:

2:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.

PIC16F1508/9 only.

Unimplemented, read as ‘1’.

DS40001609E-page 32

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

3.4.2

COMPUTED GOTO

3.4

PCL and PCLATH

A computed GOTOis accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTOmethod, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application

Note AN556, “Implementing a Table Read” (DS00556).

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 3-3 shows the five

situations for the loading of the PC.

3.4.3

COMPUTED FUNCTION CALLS

FIGURE 3-3:

LOADING OF PC IN

A computed function CALLallows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

DIFFERENT SITUATIONS

Rev. 10-000042A

7/30/2013

PCH

7

14

PCL

0

Instruction

with PCL as

Destination

PC

8

6

0

If using the CALLinstruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

PCLATH

ALU result

PCH

14

6

PCL

0

The CALLWinstruction enables computed calls by com-

bining PCLATH and W to form the destination address.

A computed CALLWis accomplished by loading the W

register with the desired address and executing CALLW.

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

GOTO,

CALL

PC

4

11

OPCODE <10:0>

PCLATH

PCH

7

14

6

PCL

0

CALLW

PC

3.4.4

BRANCHING

8

W

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

PCLATH

14

PCL

0

PCH

BRW

BRA

PC

15

PC + W

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

15

If using BRA, the entire PC will be loaded with PC + 1 +,

the signed value of the operand of the BRAinstruction.

PC + OPCODE <8:0>

3.4.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<14:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper seven bits to the PCLATH

register. When the lower eight bits are written to the

PCL register, all 15 bits of the program counter will

change to the values contained in the PCLATH register

and those being written to the PCL register.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 33

PIC16(L)F1508/9

3.5.1

ACCESSING THE STACK

3.5

Stack

The stack is available through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS

is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR,

which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is 5 bits to allow detection of

overflow and underflow.

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figures 3-4 through 3-7). The stack

space is not part of either program or data space. The

PC is PUSHed onto the stack when CALL or CALLW

instructions are executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN,

RETLWor a RETFIEinstruction execution. PCLATH is

not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN

bit is programmed to ‘0‘ (Configuration Words). This

means that after the stack has been PUSHed sixteen

times, the seventeenth PUSH overwrites the value that

was stored from the first PUSH. The eighteenth PUSH

overwrites the second PUSH (and so on). The

STKOVF and STKUNF flag bits will be set on an Over-

flow/Underflow, regardless of whether the Reset is

enabled.

Note:

Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLWand

Interrupts will increment STKPTR while RETLW,

RETURN, and RETFIEwill decrement STKPTR. At any

time STKPTR can be inspected to see how much stack

is left. The STKPTR always points at the currently used

place on the stack. Therefore, a CALL or CALLW will

increment the STKPTR and then write the PC, and a

return will unload the PC and then decrement the

STKPTR.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, CALLW, RETURN, RETLW and

RETFIE instructions or the vectoring to

an interrupt address.

Reference Figure 3-4 through Figure 3-7 for examples

of accessing the stack.

FIGURE 3-4:

ACCESSING THE STACK EXAMPLE 1

Rev. 10-000043A

7/30/2013

Stack Reset Disabled

STKPTR = 0x1F

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x1F

(STVREN = 0)

Initial Stack Configuration:

After Reset, the stack is empty. The

empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL register will return ‘0’. If the

Stack Overflow/Underflow Reset is

disabled, the TOSH/TOSL register will

return the contents of stack address

0x0F.

Stack Reset Enabled

STKPTR = 0x1F

TOSH:TOSL

0x0000

(STVREN = 1)

DS40001609E-page 34

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 3-5:

ACCESSING THE STACK EXAMPLE 2

Rev. 10-000043B

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

This figure shows the stack configuration

after the first CALL or a single interrupt.

If a RETURNinstruction is executed, the

return address will be placed in the

Program Counter and the Stack Pointer

decremented to the empty state (0x1F).

STKPTR = 0x00

TOSH:TOSL

0x00

Return Address

FIGURE 3-6:

ACCESSING THE STACK EXAMPLE 3

Rev. 10-000043C

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

After seven CALLs or six CALLs and an

interrupt, the stack looks like the figure on

the left. A series of RETURNinstructions will

repeatedly place the return addresses into

the Program Counter and pop the stack.

STKPTR = 0x06

TOSH:TOSL

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

 2011-2015 Microchip Technology Inc.

DS40001609E-page 35

PIC16(L)F1508/9

FIGURE 3-7:

ACCESSING THE STACK EXAMPLE 4

Rev. 10-000043D

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

When the stack is full, the next CALLor

an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00 so

the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

STKPTR = 0x10

TOSH:TOSL

3.5.2

OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is

programmed to ‘1’, the device will be reset if the stack

is PUSHed beyond the sixteenth level or POPed

beyond the first level, setting the appropriate bits

(STKOVF or STKUNF, respectively) in the PCON

register.

3.6

Indirect Addressing

The INDFn registers are not physical registers. Any

instruction that accesses an INDFn register actually

accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address

specifies one of the two INDFn registers, the read will

return ‘0’ and the write will not occur (though Status bits

may be affected). The FSRn register value is created

by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an

addressing space with 65536 locations. These locations

are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

DS40001609E-page 36

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 3-8:

INDIRECT ADDRESSING

Rev. 10-000044A

7/30/2013

0x0000

Traditional

Data Memory

0x0FFF

0x1000

0x0FFF

Reserved

0x1FFF

0x2000

Linear

Data Memory

0x29AF

0x29B0

Reserved

0x0000

0x7FFF

0x8000

FSR

Address

Range

Program

Flash Memory

0xFFFF

0x7FFF

Note:

Not all memory regions are completely implemented. Consult device memory tables for memory limits.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 37

PIC16(L)F1508/9

3.6.1

TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR

address 0x000 to FSR address 0xFFF. The addresses

correspond to the absolute addresses of all SFR, GPR

and common registers.

FIGURE 3-9:

TRADITIONAL DATA MEMORY MAP

Rev. 10-000056A

7/31/2013

Direct Addressing

From Opcode

Indirect Addressing

4

BSR

0

6

0

7

FSRxH

0

7

FSRxL

0

0 0 0 0

Bank Select

11111

Bank Select Location Select

00000 00001 00010

Location Select

0x00

0x7F

Bank 31

Bank 0 Bank 1 Bank 2

DS40001609E-page 38

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

3.6.2

LINEAR DATA MEMORY

3.6.3

PROGRAM FLASH MEMORY

The linear data memory is the region from FSR

address 0x2000 to FSR address 0x29AF. This region is

a virtual region that points back to the 80-byte blocks of

GPR memory in all the banks.

To make constant data access easier, the entire

program Flash memory is mapped to the upper half of

the FSR address space. When the MSb of FSRnH is

set, the lower 15 bits are the address in program

memory which will be accessed through INDF. Only the

lower eight bits of each memory location is accessible

via INDF. Writing to the program Flash memory cannot

be accomplished via the FSR/INDF interface. All

instructions that access program Flash memory via the

FSR/INDF interface will require one additional

instruction cycle to complete.

Unimplemented memory reads as 0x00. Use of the

linear data memory region allows buffers to be larger

than 80 bytes because incrementing the FSR beyond

one bank will go directly to the GPR memory of the next

bank.

The 16 bytes of common memory are not included in

the linear data memory region.

FIGURE 3-11:

PROGRAM FLASH

MEMORY MAP

FIGURE 3-10:

LINEAR DATA MEMORY

MAP

Rev. 10-000057A

7/31/2013

Rev. 10-000058A

7/31/2013

7

FSRnH

0

7

FSRnL

0

7

FSRnH

0

7

FSRnL

0

1

0 0 1

Location Select

0x8000

Location Select

0x0000

0x2000

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

Program

Flash

Memory

(low 8 bits)

0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x7FFF

0xFFFF

0x29AF

 2011-2015 Microchip Technology Inc.

DS40001609E-page 39

PIC16(L)F1508/9

4.0

DEVICE CONFIGURATION

Device configuration consists of Configuration Words,

Code Protection and Device ID.

4.1

Configuration Words

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1 at

8007h and Configuration Word 2 at 8008h.

Note:

The DEBUG bit in Configuration Words is

managed automatically by device

development tools including debuggers

and programmers. For normal device

operation, this bit should be maintained as

a ‘1’.

DS40001609E-page 40

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

4.2

Register Definitions: Configuration Words

REGISTER 4-1:

CONFIG1: CONFIGURATION WORD 1

R/P-1

FCMEN⁽¹⁾

R/P-1

IESO⁽¹⁾

R/P-1

BOREN<1:0>⁽²⁾

R/P-1

U-1

—

CLKOUTEN

bit 13

bit 8

R/P-1

CP⁽³⁾

R/P-1

MCLRE

PWRTE

WDTE<1:0>

FOSC<2:0>

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared

-n = Value when blank or after Bulk Erase

bit 13

bit 12

bit 11

FCMEN: Fail-Safe Clock Monitor Enable bit

1= Fail-Safe Clock Monitor is enabled⁽¹⁾

0= Fail-Safe Clock Monitor is disabled

IESO: Internal External Switchover bit⁽¹⁾

1= Internal/External Switchover (Two-Speed Start-up) mode is enabled

0= Internal/External Switchover mode is disabled

CLKOUTEN: Clock Out Enable bit

1= CLKOUT function is disabled. I/O function on the CLKOUT pin

0= CLKOUT function is enabled on the CLKOUT pin

bit 10-9

BOREN<1:0>: Brown-Out Reset Enable bits⁽²⁾

11= BOR enabled

10= BOR enabled during operation and disabled in Sleep

01= BOR controlled by SBOREN bit of the BORCON register

00= BOR disabled

bit 8

bit 7

Unimplemented: Read as ‘1’

CP: Code Protection bit⁽³⁾

1= Program memory code protection is disabled

0= Program memory code protection is enabled

bit 6

MCLRE: MCLR/VPP Pin Function Select bit

If LVP bit = 1:

This bit is ignored.

If LVP bit = 0:

1= MCLR/VPP pin function is MCLR; Weak pull-up enabled.

0= MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUA3 bit.

bit 5

PWRTE: Power-Up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

bit 4-3

WDTE<1:0>: Watchdog Timer Enable bits

11= WDT enabled

10= WDT enabled while running and disabled in Sleep

01= WDT controlled by the SWDTEN bit in the WDTCON register

00= WDT disabled

 2011-2015 Microchip Technology Inc.

DS40001609E-page 41

PIC16(L)F1508/9

REGISTER 4-1:

CONFIG1: CONFIGURATION WORD 1 (CONTINUED)

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111= ECH:External clock, High-Power mode: on CLKIN pin

110= ECM: External clock, Medium Power mode: on CLKIN pin

101= ECL: External clock, Low-Power mode: on CLKIN pin

100= INTOSC oscillator: I/O function on CLKIN pin

011= EXTRC oscillator: External RC circuit connected to CLKIN pin

010= HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins

001= XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins

000= LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: When FSCM is enabled, Two-Speed Start-up will be automatically enabled, regardless of the IESO bit value.

2: Enabling Brown-out Reset does not automatically enable Power-up Timer.

3: Once enabled, code-protect can only be disabled by bulk erasing the device.

DS40001609E-page 42

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

REGISTER 4-2:

CONFIG2: CONFIGURATION WORD 2

R/P-1

LVP⁽¹⁾

R/P-1

DEBUG⁽³⁾

R/P-1

BORV⁽²⁾

R/P-1

U-1

—

LPBOR

STVREN

bit 13

bit 8

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

R/P-1

WRT<1:0>

bit 7

bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

-n = Value when blank or after Bulk Erase

bit 13

bit 12

bit 11

bit 10

bit 9

LVP: Low-Voltage Programming Enable bit⁽¹⁾

1= Low-voltage programming enabled

0= High-voltage on MCLR must be used for programming

DEBUG: In-Circuit Debugger Mode bit⁽³⁾

1= In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins

0= In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

LPBOR: Low-Power BOR Enable bit

1= Low-Power Brown-out Reset is disabled

0= Low-Power Brown-out Reset is enabled

BORV: Brown-Out Reset Voltage Selection bit⁽²⁾

1= Brown-out Reset voltage (VBOR), low trip point selected

0= Brown-out Reset voltage (VBOR), high trip point selected

STVREN: Stack Overflow/Underflow Reset Enable bit

1= Stack Overflow or Underflow will cause a Reset

0= Stack Overflow or Underflow will not cause a Reset

bit 8-2

bit 1-0

Unimplemented: Read as ‘1’

WRT<1:0>: Flash Memory Self-Write Protection bits

4 kW Flash memory (PIC16(L)F1508/9 only)

11= Write protection off

10= 000h to 1FFh write protected, 200h to FFFh may be modified

01= 000h to 7FFh write protected, 800h to FFFh may be modified

00= 000h to FFFh write protected, no addresses may be modified

8 kW Flash memory (PIC16(L)F1509 only)

11= Write protection off

10= 0000h to 01FFh write protected, 0200h to 1FFFh may be modified

01= 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified

00= 0000h to 1FFFh write protected, no addresses may be modified

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: See VBOR parameter for specific trip point voltages.

3: The DEBUG bit in Configuration Words is managed automatically by device development tools including

debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 43

PIC16(L)F1508/9

4.3

Code Protection

Code protection allows the device to be protected from

unauthorized access. Internal access to the program

memory is unaffected by any code protection setting.

4.3.1

PROGRAM MEMORY PROTECTION

The entire program memory space is protected from

external reads and writes by the CP bit in Configuration

Words. When CP = 0, external reads and writes of

program memory are inhibited and a read will return all

‘0’s. The CPU can continue to read program memory,

regardless of the protection bit settings. Writing the

program memory is dependent upon the write

protection

setting.

See

Section

4.4 “Write

Protection” for more information.

4.4

Write Protection

Write protection allows the device to be protected from

unintended self-writes. Applications, such as

bootloader software, can be protected while allowing

other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the

size of the program memory block that is protected.

4.5

User ID

Four memory locations (8000h-8003h) are designated as

ID locations where the user can store checksum or other

code identification numbers. These locations are

readable and writable during normal execution. See

Section 10.4 “User ID, Device ID and Configuration

Word Access” for more information on accessing these

memory locations. For more information on checksum

calculation, see the “PIC12(L)F1501/PIC16(L)F150X

Memory Programming Specification” (DS41573).

DS40001609E-page 44

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

4.6

Device ID and Revision ID

The memory location 8006h is where the Device ID and

Revision ID are stored. The upper nine bits hold the

Device ID. The lower five bits hold the Revision ID. See

Section 10.4 “User ID, Device ID and Configuration

Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and

debuggers, may be used to read the Device ID and

Revision ID.

4.7

Register Definitions: Device ID

REGISTER 4-3:

DEVID: DEVICE ID REGISTER

R

DEV<8:3>

bit 13

bit 8

bit 0

R

DEV<2:0>

REV<4:0>

bit 7

Legend:

R = Readable bit

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 13-5

DEV<8:0>: Device ID bits

DEVID<13:0> Values

Device

DEV<8:0>

REV<4:0>

PIC16LF1508

PIC16F1508

PIC16LF1509

PIC16F1509

10 1101 111

10 1101 001

10 1110 000

10 1101 010

x xxxx

bit 4-0

REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

 2011-2015 Microchip Technology Inc.

DS40001609E-page 45

PIC16(L)F1508/9

The oscillator module can be configured in one of the

following clock modes.

5.0

OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

1. ECL – External Clock Low-Power mode

(0 MHz to 0.5 MHz)

5.1

Overview

2. ECM – External Clock Medium Power mode

(0.5 MHz to 4 MHz)

The oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 5-1

illustrates a block diagram of the oscillator module.

3. ECH – External Clock High-Power mode

(4 MHz to 20 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode (up to 4 MHz)

Clock sources can be supplied from external oscillators,

quartz crystal resonators, ceramic resonators and

Resistor-Capacitor (RC) circuits. In addition, the system

clock source can be supplied from one of two internal

oscillators, with a choice of speeds selectable via

software. Additional clock features include:

6. HS – High Gain Crystal or Ceramic Resonator

mode (4 MHz to 20 MHz)

7. EXTRC – External Resistor-Capacitor

8. INTOSC – Internal oscillator (31 kHz to 16 MHz)

Clock Source modes are selected by the FOSC<2:0>

bits in the Configuration Words. The FOSC bits

determine the type of oscillator that will be used when

the device is first powered.

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

The ECH, ECM, and ECL clock modes rely on an

external logic level signal as the device clock source.

The LP, XT, and HS clock modes require an external

crystal or resonator to be connected to the device.

Each mode is optimized for a different frequency range.

The EXTRC clock mode requires an external resistor

and capacitor to set the oscillator frequency.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, ECH, ECM, ECL or EXTRC modes) and

switch automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

The INTOSC internal oscillator block produces a low

and high-frequency clock source, designated

LFINTOSC and HFINTOSC. (See Internal Oscillator

Block, Figure 5-1). A wide selection of device clock

frequencies may be derived from these two clock

sources.

• Fast start-up oscillator allows internal circuits to

power-up and stabilize before switching to the 16

MHz HFINTOSC

DS40001609E-page 46

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 5-1:

SIMPLIFIED PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

Rev. 10-000030A

7/30/2013

CLKIN/ OSC1/

SOSCI/ T1CKI

Sleep

Primary

Oscillator

(OSC)

Primary Clock

Secondary Clock⁽¹⁾

INTOSC

(1)

FOSC

CLKOUT/ OSC2/

SOSCO/ T1G

Secondary

Oscillator

(SOSC)

to CPU and

Peripherals

IRCF<3:0>

HFINTOSC

4

16 MHz

8 MHz

Start-up

Control Logic

Clock

4 MHz

Control

2 MHz

16 MHz

1 MHz

Oscillator

HFINTOSC⁽¹⁾

*500 kHz

*250 kHz

*125 kHz

62.5 kHz

*31.25 kHz

*31 kHz

3

2

SCS<1:0>

Fast Start-up

Oscillator

FOSC<2:0>

LFINTOSC

LFINTOSC⁽¹⁾

31 kHz

Oscillator

to WDT, PWRT, and

other Peripherals

FRC

FRC⁽¹⁾

600 kHz

Oscillator

to ADC and

other Peripherals

* Available with more than one IRCF selection

Note 1: See Section 5.2.2.4 “Peripheral Clock Sources”.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 47

PIC16(L)F1508/9

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

5.2

Clock Source Types

Clock sources can be classified as external, internal or

peripheral.

External clock sources rely on external circuitry for the

clock source to function. Examples are: oscillator mod-

ules (ECH, ECM, ECL modes), quartz crystal resona-

tors or ceramic resonators (LP, XT and HS modes) and

Resistor-Capacitor (EXTRC) mode circuits.

FIGURE 5-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

Internal clock sources are contained within the oscillator

module. The internal oscillator block has two internal

oscillators that are used to generate the internal system

clock sources: the 16 MHz High-Frequency Internal

Oscillator (HFINTOSC) and the 31 kHz Low-Frequency

Internal Oscillator (LFINTOSC).

Rev. 10-000045A

7/30/2013

Clock from

Ext. system

OSC1/CLKIN

PIC^®MCU

The peripheral clock source is a nominal 600 kHz

internal RC oscillator, FRC. The FRC is traditionally

used with the ADC module, but is sometimes available

to other peripherals. See Section 5.2.2.4 “Peripheral

Clock Sources”.

FOSC/4 or I/O⁽¹⁾

OSC2/CLKOUT

Note 1: Output depends upon the CLKOUTEN bit

of the Configuration Words.

The system clock can be selected between external or

internal clock sources via the System Clock Select

(SCS) bits in the OSCCON register. See Section

5.3 “Clock Switching” for additional information.

5.2.1.2

LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 5-3). The three modes select

a low, medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

5.2.1

EXTERNAL CLOCK SOURCES

An external clock source can be used as the device

system clock by performing one of the following

actions:

• Program the FOSC<2:0> bits in the Configuration

Words to select an external clock source that will

be used as the default system clock upon a

device Reset.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is designed to

drive only 32.768 kHz tuning-fork type crystals (watch

crystals).

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to:

- Secondary oscillator during run-time, or

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

- An external clock source determined by the

value of the FOSC bits.

See Section 5.3 “Clock Switching” for more informa-

tion.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require a high drive setting.

5.2.1.1

EC Mode

The External Clock (EC) mode allows an externally

generated logic level signal to be the system clock

source. When operating in this mode, an external clock

source is connected to the OSC1 input.

OSC2/CLKOUT is available for general purpose I/O or

CLKOUT. Figure 5-2 shows the pin connections for EC

mode.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

EC mode has three power modes to select from through

the FOSC bits in the Configuration Words:

• ECH – High-power, 4-20 MHz

• ECM – Medium-power, 0.5-4 MHz

• ECL – Low-power, 0-0.5 MHz

DS40001609E-page 48

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 5-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 5-4:

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

Rev. 10-000060A

7/30/2013

Rev. 10-000059A

7/30/2013

PIC^®MCU

Ceramic

Resonator

PIC^®MCU

OSC1/CLKIN

C1

To Internal

Logic

C1

C2

To Internal

Logic

(3)

(2)

RP

Sleep

Quartz

Crystal

RF

(2)

Sleep

RF

OSC2/CLKOUT

(1)

C2

Note 1:

2:

RS

OSC2/CLKOUT

(1)

RS

A series resistor (Rs) may be required for

ceramic resonators with low drive level.

Note 1:

2:

A series resistor (Rs) may be required for

quartz crystals with low drive level.

The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ and 10 MΩ).

The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ and 10 MΩ).

3.

An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

Note 1: Quartz

crystal

characteristics

vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

5.2.1.3

Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended,

unless either FSCM or Two-Speed Start-Up are

enabled. In this case, code will continue to execute at

the selected INTOSC frequency while the OST is

counting. The OST ensures that the oscillator circuit,

using a quartz crystal resonator or ceramic resonator,

has started and is providing a stable system clock to

the oscillator module.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section

5.4 “Two-Speed Clock Start-up Mode”).

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 49

PIC16(L)F1508/9

5.2.1.4

Secondary Oscillator

5.2.1.5

External RC Mode

The secondary oscillator is a separate crystal oscillator

that is associated with the Timer1 peripheral. It is opti-

mized for timekeeping operations with a 32.768 kHz

crystal connected between the SOSCO and SOSCI

device pins.

The External Resistor-Capacitor (EXTRC) mode

supports the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required.

The secondary oscillator can be used as an alternate

system clock source and can be selected during

run-time using clock switching. Refer to Section

5.3 “Clock Switching” for more information.

The RC circuit connects to OSC1. OSC2/CLKOUT is

available for general purpose I/O or CLKOUT. The

function of the OSC2/CLKOUT pin is determined by the

CLKOUTEN bit in Configuration Words.

Figure 5-6 shows the External RC mode connections.

FIGURE 5-5:

QUARTZ CRYSTAL

OPERATION

FIGURE 5-6:

EXTERNAL RC MODES

(SECONDARY

OSCILLATOR)

Rev. 10-000062A

7/31/2013

Rev. 10-000061A

7/30/2013

V

DD

PIC^®MCU

REXT

OSC1/CLKIN

Internal

SOSCI

Clock

CEXT

VSS

C1

To Internal

Logic

32.768 kHz

Quartz

Crystal

F

OSC/4

OSC2/CLKOUT

or I/O⁽¹⁾

Recommended values:10 k REXT 100 k, <3V

3 k REXT 100 k, 3-5V

SOSCO

C2

CEXT > 20 pF, 2-5V

Note 1:

Output depends upon the CLKOUTEN bit of the

Configuration Words.

Note 1: Quartz

crystal

characteristics

vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

3: For oscillator design assistance, reference

The user also needs to take into account variation due

to tolerance of the external RC components used.

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for

Low-Power External Oscillators”

(DS01288)

DS40001609E-page 50

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

5.2.2

INTERNAL CLOCK SOURCES

5.2.2.2

LFINTOSC

The device may be configured to use the internal oscil-

lator block as the system clock by performing one of the

following actions:

The Low-Frequency Internal Oscillator (LFINTOSC) is

a 31 kHz internal clock source.

The output of the LFINTOSC connects to a multiplexer

(see Figure 5-1). Select 31 kHz, via software, using the

IRCF<3:0> bits of the OSCCON register. See Section

5.2.2.6 “Internal Oscillator Clock Switch Timing” for

more information. The LFINTOSC is also the frequency

for the Power-up Timer (PWRT), Watchdog Timer

(WDT) and Fail-Safe Clock Monitor (FSCM).

• Program the FOSC<2:0> bits in Configuration

Words to select the INTOSC clock source, which

will be used as the default system clock upon a

device Reset.

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to the internal

oscillator during run-time. See Section

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register = 000) as the

system clock source (SCS bits of the OSCCON

register = 1x), or when any of the following are

enabled:

5.3 “Clock Switching”for more information.

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT is available for general

purpose I/O or CLKOUT.

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired LF frequency, and

The function of the OSC2/CLKOUT pin is determined

by the CLKOUTEN bit in Configuration Words.

• FOSC<2:0> = 100, or

The internal oscillator block has two independent

oscillators that provides the internal system clock

source.

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’.

Peripherals that use the LFINTOSC are:

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

16 MHz.

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

2. The LFINTOSC (Low-Frequency Internal

• Fail-Safe Clock Monitor (FSCM)

Oscillator) operates at 31 kHz.

The Low-Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running.

5.2.2.1

HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 16 MHz internal clock source.

5.2.2.3

FRC

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). The frequency derived

from the HFINTOSC can be selected via software using

the IRCF<3:0> bits of the OSCCON register. See

Section 5.2.2.6 “Internal Oscillator Clock Switch

Timing” for more information.

The FRC clock is an uncalibrated, nominal 600 kHz

peripheral clock source.

The FRC is automatically turned on by the peripherals

requesting the FRC clock.

The FRC clock continues to run during Sleep.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired HF frequency, and

• FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’.

A fast start-up oscillator allows internal circuits to

power-up and stabilize before switching to HFINTOSC.

The High-Frequency Internal Oscillator Ready bit

(HFIOFR) of the OSCSTAT register indicates when the

HFINTOSC is running.

The High-Frequency Internal Oscillator Stable bit

(HFIOFS) of the OSCSTAT register indicates when the

HFINTOSC is running within 0.5% of its final value.

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5.2.2.4

Peripheral Clock Sources

5.2.2.5

Internal Oscillator Frequency

Selection

The clock sources described in this chapter and the

Timer’s are available to different peripherals. Table 5-1

lists the clocks and timers available for each peripheral.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The postscaled output of the 16 MHz HFINTOSC and

31 kHz LFINTOSC connect to a multiplexer (see

Figure 5-1). The Internal Oscillator Frequency Select

bits IRCF<3:0> of the OSCCON register (Register 5-1)

select the frequency output of the internal oscillators.

TABLE 5-1:

PERIPHERAL CLOCK

SOURCES

Note:

Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’

and the frequency selection is set to

500 kHz. The user can modify the IRCF

bits to select a different frequency.

ADC

●

CLC

●

COMP

CWG

EUSART

MSSP

NCO

●

The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These dupli-

cate choices can offer system design trade-offs. Lower

power consumption can be obtained when changing

oscillator sources for a given frequency. Faster transi-

tion times can be obtained between frequency changes

that use the same oscillator source.

●

PWM

PWRT

TMR0

TMR1

TMR2

WDT

●

5.2.2.6

Internal Oscillator Clock Switch

Timing

●

When switching between the HFINTOSC and the

LFINTOSC, the new oscillator may already be shut

down to save power (see Figure 5-7). If this is the case,

there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC and

LFINTOSC oscillators. The sequence of a frequency

selection is as follows:

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

5. The new clock is now active.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 5-3.

Start-up delay specifications are located in Table 29-8,

“Oscillator Parameters”.

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FIGURE 5-7:

HFINTOSC

INTERNAL OSCILLATOR SWITCH TIMING

LFINTOSC (FSCM and WDT disabled)

HFINTOSC

(1)

Oscillator Delay

2-cycle Sync

Running

LFINTOSC

0

0

IRCF <3:0>

System Clock

HFINTOSC

LFINTOSC (Either FSCM or WDT enabled)

HFINTOSC

2-cycle Sync

Running

LFINTOSC

0

0

IRCF <3:0>

System Clock

LFINTOSC

HFINTOSC

(2)

LFINTOSC turns off unless WDT or FSCM is enabled

Running

LFINTOSC

(1)

2-cycle Sync

Oscillator Delay

HFINTOSC

IRCF <3:0>

= 0

 0

System Clock

Note 1: See Table 5-3, “Oscillator Switching Delays” for more information.

2: LFINTOSC will continue to run if a peripheral has selected it as the clock source. See

Section 5.2.2.4 “Peripheral Clock Sources”.

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When Fail-Safe Clock Monitor and/or Two-Speed

Start-up are enabled, (FCMEN = 1 and/or IESO = 1),

the device will operate using the internal oscillator

(INTOSC) selected by the IRCF<3:0> bits, whenever

OSTS = 0. When the OST period expires,

(OSTS = 1), the system clock will switch to the external

oscillator selected.

5.3

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bits of the OSCCON

register. The following clock sources can be selected

using the SCS bits:

• Default system oscillator determined by FOSC

bits in Configuration Words

When Fail-Safe Clock Monitor and Two-Speed Start-up

are disabled, (FCMEN = 0 and IESO = 0), the device

will be held in Reset while OSTS = 0. When OST

period expires, (OSTS = 1), Reset will be released and

execution will begin 10 FOSC cycles later using the

external oscillator selected.

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

5.3.1

SYSTEM CLOCK SELECT (SCS)

BITS

For definition of the OSTS bit with clock sources other

than external oscillator modes (HS, XT or LP), see

Table 5-2.

The System Clock Select (SCS) bits of the OSCCON

register selects the system clock source that is used for

the CPU and peripherals.

The OSTS bit does not reflect the status of the

secondary oscillator.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of

the FOSC<2:0> bits in the Configuration Words.

TABLE 5-2:

OSTS BIT DEFINITION

SCS<1:0> bits

• When the SCS bits of the OSCCON register = 01,

the system clock source is the secondary

oscillator.

FOSC<2:0>

selection

00

01

1x

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<3:0>

bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always

cleared.

OSTS value

INTOSC

0

1

0

ECH, ECM, ECL,

EXTRC

0

HS, XT, LP

normal*

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or

Fail-Safe Clock Monitor, does not update

the SCS bits of the OSCCON register. The

user can monitor the OSTS bit of the

OSCSTAT register to determine the current

system clock source. See Table 5-2.

* Normal function for oscillator modes (OSTS = 0),

while OST counting (OSTS = 1), after OST count

has expired.

5.3.3

SECONDARY OSCILLATOR

The secondary oscillator is a separate crystal oscillator

associated with the Timer1 peripheral. It is optimized

for timekeeping operations with a 32.768 kHz crystal

connected between the SOSCO and SOSCI device

pins.

When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 5-3.

5.3.2

OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT

The secondary oscillator is enabled using the

T1OSCEN control bit in the T1CON register. See

Section 19.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

The Oscillator Start-up Timer Status (OSTS) bit in the

OSCSTAT register has different definitions that are

dependent on the FOSC bit selection in the

Configuration Word. Table 5-2 defines the OSTS bit

value for the FOSC selections.

5.3.4

SECONDARY OSCILLATOR READY

(SOSCR) BIT

The user must ensure that the secondary oscillator is

ready to be used before it is selected as a system clock

source. The Secondary Oscillator Ready (SOSCR) bit

of the OSCSTAT register indicates whether the

secondary oscillator is ready to be used. After the

SOSCR bit is set, the SCS bits can be configured to

select the secondary oscillator.

The normal function of the OSTS bit is when

FOSC<2:0> selects one of the external oscillator

modes, HS, XT or LP, while the OST is counting pulses

on the OSC1 pin from the external oscillator,

OSTS = 0. When the OST has counted 1024 pulses,

the OSTS bit should be set, OSTS = 1, indicating the

oscillator is stable and ready to be used.

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5.3.5

CLOCK SWITCHING BEFORE

SLEEP

5.4

Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external oscil-

lator start-up and code execution. In applications that

make heavy use of the Sleep mode, Two-Speed Start-up

will remove the external oscillator start-up time from the

time spent awake and can reduce the overall power con-

sumption of the device. This mode allows the application

to wake-up from Sleep, perform a few instructions using

the INTOSC internal oscillator block as the clock source

and go back to Sleep without waiting for the external

oscillator to become stable.

When clock switching from an old clock to a new clock

is requested just prior to entering Sleep mode, it is

necessary to confirm that the switch is complete before

the SLEEPinstruction is executed. Failure to do so may

result in an incomplete switch and consequential loss

of the system clock altogether. Clock switching is

confirmed by monitoring the clock status bits in the

OSCSTAT register. Switch confirmation can be

accomplished by sensing that the ready bit for the new

clock is set or the ready bit for the old clock is cleared.

For example, when switching between the internal

oscillator with the PLL and the internal oscillator without

the PLL, monitor the PLLR bit. When PLLR is set, the

switch to 32 MHz operation is complete. Conversely,

when PPLR is cleared, the switch from 32 MHz

operation to the selected internal clock is complete.

Two-Speed Start-up provides benefits when the oscillator

module is configured for LP, XT, or HS modes. The Oscil-

lator Start-up Timer (OST) is enabled for these modes

and must count 1024 oscillations before the oscillator

can be used as the system clock source.

If the oscillator module is configured for any mode

other than LP, XT or HS mode, then Two-Speed

Start-up is disabled. This is because the external clock

oscillator does not require any stabilization time after

POR or an exit from Sleep.

If the OST count reaches 1024 before the device enters

Sleep mode, the OSTS bit of the OSCSTAT register is

set and program execution switches to the external oscil-

lator. However, the system may never operate from the

external oscillator if the time spent awake is very short.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCSTAT register to

remain clear.

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5.4.1

TWO-SPEED START-UP MODE

CONFIGURATION

5.4.2

TWO-SPEED START-UP

SEQUENCE

Two-Speed Start-up mode is configured by the following

settings:

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0>

bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

• IESO (of the Configuration Words) = 1;

Internal/External Switchover bit (Two-Speed

Start-up mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Words

configured for LP, XT or HS mode.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

5.4.3

CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCSTAT

register will confirm if the CPU is running from the

external clock source, as defined by the FOSC<2:0>

bits in the Configuration Words, or the internal oscilla-

tor. See Table 5-2.

Note:

When FSCM is enabled, Two-Speed

Start-up will automatically be enabled.

TABLE 5-3:

Switch From

OSCILLATOR SWITCHING DELAYS

Switch To

Oscillator Delay

LFINTOSC

1 cycle of each clock source

2 s (approx.)

HFINTOSC

Any clock source

ECH, ECM, ECL, EXTRC

LP, XT, HS

2 cycles

1024 Clock Cycles (OST)

1024 Secondary Oscillator Cycles

Secondary Oscillator

FIGURE 5-8:

TWO-SPEED START-UP

INTOSC

TOST

OSC1

0

1

1022 1023

OSC2

PC - N

PC + 1

Program Counter

PC

System Clock

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5.5.3

FAIL-SAFE CONDITION CLEARING

5.5

Fail-Safe Clock Monitor

When a Fail-Safe condition exists, the user must take

the following actions to clear the condition before

returning to normal operation with the external source.

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator or

external clock fail. If an oscillator mode is selected, the

FSCM can detect oscillator failure any time after the

Oscillator Start-up Timer (OST) has expired. When an

external clock mode is selected, the FSCM can detect

failure as soon as the device is released from Reset.

The next sections describe how to clear the Fail-Safe

condition for specific clock selections (FOSC bits) and

clock switching modes (SCS bit settings).

5.5.3.1

External Oscillator with

SCS<1:0> = 00

FSCM is enabled by setting the FCMEN bit in the

Configuration Words. The FSCM is applicable to external

oscillator modes (LP, XT, HS) and external clock modes

(ECH, ECM, ECL, EXTRC) and the Secondary Oscillator

(SOSC).

When a Fail-Safe condition occurs with the FOSC bits

selecting external oscillator (FOSC<2:0> = HS, XT, LP)

and the clock switch has been selected to run from the

FOSC selection (SCS<1:0> = 00), the condition is

cleared by performing the following procedure.

FIGURE 5-9:

FSCM BLOCK DIAGRAM

When SCS<1:0> = 00 (Running from FOSC selection)

SCS<1:0> = 1x:

Clock Monitor

Latch

External

Clock

S

Q

Change the SCS bits in the OSCCON register

to select the internal oscillator block. This resets

the OST timer and allows it to operate again.

LFINTOSC

Oscillator

÷ 64

R

Q

OSFIF = 0:

Clear the OSFIF bit in the PIR2 register.

SCS<1:0> = 00:

31 kHz

(~32 s)

488 Hz

(~2 ms)

Change the SCS bits in the OSCCON register

to select the FOSC Configuration Word clock

selection. This will start the OST. The CPU will

continue to operate from the internal oscillator

until the OST count is reached. When OST

expires, the clock module will switch to the

external oscillator and the Fail-Safe condition

will be cleared.

Sample Clock

Clock

Failure

Detected

5.5.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

monitoring falling clock edges and using LFINTOSC as a

time base. See Figure 5-9. Detection of a failed oscillator

will take 32 to 96 cycles of the LFINTOSC. Figure 5-10

shows a timing diagram of the FSCM module.

If the Fail-Safe condition still exists, the OSFIF bit will

again be set by hardware.

5.5.3.2

External Clock with SCS<1:0> = 00

When a Fail-Safe condition occurs with the FOSC bits

selecting external clock (FOSC<2:0> = ECH, ECM,

ECL, EXTRC) and the clock switch has selected to run

from the FOSC selection (SCS<1:0> = 00), the condi-

tion is cleared by performing the following procedure.

5.5.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

CPU clock to an internal clock source and sets the OSFIF

bit of the PIR2 register. The internal clock source is

determined by the IRCF<3:0> bits in the OSCCON

register.

When SCS<1:0> = 00 (Running from FOSC selection)

SCS<1:0> = 1x:

When the OSFIF bit is set, an interrupt will be generated,

if the OSFIE bit in the PIE2 register is enabled. The user’s

firmware in the Interrupt Service Routine (ISR) can then

take steps to mitigate the problems that may arise from

the failed clock.

Change the SCS bits in the OSCCON register

to select the internal oscillator block. This resets

the OST timer and allows it to operate again.

OSFIF = 0:

The system clock will continue to be sourced from the

internal clock source until the fail-safe condition has

been cleared, see Section 5.5.3 “Fail-Safe Condition

Clearing”.

Clear the OSFIF bit in the PIR2 register.

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SCS<1:0> = 00:

SCS<1:0> = 01:

Change the SCS bits in the OSCCON register

to select the FOSC Configuration Word clock

selection. Since the OST is not applicable with

external clocks, the clock module will

immediately switch to the external clock, and

the fail-safe condition will be cleared.

to select the secondary oscillator. The clock

module will immediately switch to the

secondary oscillator and the fail-safe condition

will be cleared.

If the Fail-Safe condition still exists, the OSFIF bit will

again be set by hardware.

If the Fail-Safe condition still exists, the OSFIF bit will

again be set by hardware.

5.5.4

RESET OR WAKE-UP FROM SLEEP

5.5.3.3

Secondary Oscillator with

SCS<1:0> = 01

The FSCM is designed to detect external oscillator or

external clock failures.

When a Fail-Safe condition occurs with the clock switch

selected to run from the Secondary Oscillator selection

(SCS<1:0> = 01), regardless of the FOSC selection,

the condition is cleared by performing the following pro-

cedure.

When FSCM is used with an external oscillator, the

Oscillator Start-up Timer (OST) count must expire

before the FSCM becomes active. The OST is used

after waking up from Sleep and after any type of Reset.

When the FSCM is used with external clocks, the OST

is not used and the FSCM will be active as soon as the

Reset or wake-up has completed.

SCS<1:0> = 01 (Secondary Oscillator)

SCS<1:0> = 1x:

When the FSCM is enabled, the Two-Speed Start-up is

also enabled. Therefore, the device will always be exe-

cuting code while the OST is operating.

Change the SCS bits in the OSCCON register

to select the internal oscillator block.

OSFIF = 0:

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep).

Clear the OSFIF bit in the PIR2 register.

Read SOSCR:

The OST is not used with the secondary

oscillator, therefore, the user must determine if

the secondary oscillator is ready by monitoring

the SOSCR bit in the OSCSTAT register.

When the SOSCR bit is set, the secondary

oscillator is ready.

FIGURE 5-10:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSFIF

Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

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5.6

Register Definitions: Oscillator Control

REGISTER 5-1:

OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1

IRCF<3:0>

U-0

—

U-0

—

R/W-0/0

SCS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-3

IRCF<3:0>: Internal Oscillator Frequency Select bits

1111= 16 MHz

1110= 8 MHz

1101= 4 MHz

1100= 2 MHz

1011= 1 MHz

1010= 500 kHz⁽¹⁾

1001= 250 kHz⁽¹⁾

1000= 125 kHz⁽¹⁾

0111= 500 kHz (default upon Reset)

0110= 250 kHz

0101= 125 kHz

0100= 62.5 kHz

001x= 31.25 kHz

000x= 31 kHz LF

bit 2

Unimplemented: Read as ‘0’

bit 1-0

SCS<1:0>: System Clock Select bits

1x= Internal oscillator block

01= Secondary oscillator

00= Clock determined by FOSC<2:0> in Configuration Words.

Note 1: Duplicate frequency derived from HFINTOSC.

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REGISTER 5-2:

OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q

SOSCR

bit 7

U-0

—

R-q/q

R-0/q

U-0

—

U-0

—

R-0/q

OSTS

HFIOFR

LFIOFR

HFIOFS

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Conditional

bit 7

SOSCR: Secondary Oscillator Ready bit

If T1OSCEN = 1:

1= Secondary oscillator is ready

0= Secondary oscillator is not ready

If T1OSCEN = 0:

1= Timer1 clock source is always ready

bit 6

bit 5

Unimplemented: Read as ‘0’

OSTS: Oscillator Start-up Timer Status bit

When the FOSC<2:0> bits select HS, XT or LP oscillator:

1= OST has counted 1024 clocks, device is clocked by the FOSC<2:0> bit selection

0= OST is counting, device is clocked from the internal oscillator (INTOSC) selected by the IRCF<3:0>

bits.

For all other FOSC<2:0> bit selections:

See Table 5-2, “OSTS Bit Definition”.

bit 4

HFIOFR: High-Frequency Internal Oscillator Ready bit

1= HFINTOSC is ready

0= HFINTOSC is not ready

bit 3-2

bit 1

Unimplemented: Read as ‘0’

LFIOFR: Low-Frequency Internal Oscillator Ready bit

1= LFINTOSC is ready

0= LFINTOSC is not ready

bit 0

HFIOFS: High-Frequency Internal Oscillator Stable bit

1= HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC

0= HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC

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TABLE 5-4:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON

OSCSTAT

PIE2

—

IRCF<3:0>

—

SCS<1:0>

LFIOFR HFIOFS

59

60

SOSCR

OSFIE

OSFIF

—

OSTS

C1IE

C1IF

HFIOFR

—

C2IE

C2IF

—

BCL1IE

BCL1IF

NCO1IE

NCO1IF

—

77

PIR2

80

T1CON

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN T1SYNC

TMR1ON

163

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

TABLE 5-5: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

—

CONFIG1

41

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 61

PIC16(L)F1508/9

6.0

RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

• MCLR Reset

• WDT Reset

• RESETinstruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional power-up timer

can be enabled to extend the Reset time after a BOR

or POR event.

A simplified block diagram of the On-chip Reset Circuit

is shown in Figure 6-1.

FIGURE 6-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Rev. 10-000006A

8/14/2013

ICSP™ Programming Mode Exit

RESET Instruction

Stack Underflow

Stack Overlfow

MCLRE

Sleep

VPP/MCLR

WDT

Time-out

Device

Reset

Power-on

Reset

VDD

BOR

Active⁽¹⁾

Brown-out

Reset

R

Power-up

Timer

LFINTOSC

PWRTE

LPBOR

Reset

Note 1: See Table 6-1 for BOR active conditions.

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6.1

Power-On Reset (POR)

6.2

Brown-Out Reset (BOR)

The POR circuit holds the device in Reset until VDD has

reached an acceptable level for minimum operation.

Slow rising VDD, fast operating speeds or analog

performance may require greater than minimum VDD.

The PWRT, BOR or MCLR features can be used to

extend the start-up period until all device operation

conditions have been met.

The BOR circuit holds the device in Reset when VDD

reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for

execution protection can be implemented.

The Brown-out Reset module has four operating

modes controlled by the BOREN<1:0> bits in Configu-

ration Words. The four operating modes are:

• BOR is always on

6.1.1

POWER-UP TIMER (PWRT)

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

The Power-up Timer provides a nominal 64 ms

time-out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the VDD to

rise to an acceptable level. The Power-up Timer is

enabled by clearing the PWRTE bit in Configuration

Words.

Refer to Table 6-1 for more information.

The Brown-out Reset voltage level is selectable by

configuring the BORV bit in Configuration Words.

A VDD noise rejection filter prevents the BOR from

triggering on small events. If VDD falls below Vpor for a

duration greater than parameter TBORDC, the device

will reset. See Figure 6-2 for more information.

The Power-up Timer starts after the release of the POR

and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 6-1:

BOREN<1:0>

11

BOR OPERATING MODES

Instruction Execution upon:

Release of POR or Wake-up from Sleep

SBOREN

Device Mode

BOR Mode

X

Active

Waits for BOR ready⁽¹⁾

(BORRDY = 1)

Awake

Sleep

Active

Disabled

Active

Waits for BOR ready

10

X

1

(BORRDY = 1)

Waits for BOR ready⁽¹⁾

X

(BORRDY = 1)

01

00

0

X

Disabled

Begins immediately

(BORRDY = x)

Note 1: In these specific cases, “release of POR” and “wake-up from Sleep,” there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR

circuit is forced on by the BOREN<1:0> bits.

BOR protection is not active during Sleep. The device

wake-up will be delayed until the BOR is ready.

6.2.1

BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are pro-

grammed to ‘11’, the BOR is always on. The device

start-up will be delayed until the BOR is ready and VDD

is higher than the BOR threshold.

6.2.3

BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are

programmed to ‘01’, the BOR is controlled by the

SBOREN bit of the BORCON register. The device

start-up is not delayed by the BOR ready condition or

the VDD level.

BOR protection is active during Sleep. The BOR does

not delay wake-up from Sleep.

6.2.2

BOR IS OFF IN SLEEP

BOR protection begins as soon as the BOR circuit is

ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

When the BOREN bits of Configuration Words are pro-

grammed to ‘10’, the BOR is on, except in Sleep. The

device start-up will be delayed until the BOR is ready

and VDD is higher than the BOR threshold.

BOR protection is unchanged by Sleep.

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PIC16(L)F1508/9

FIGURE 6-2:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

TPWRT

VDD

VBOR

Internal

Reset

< TPWRT

(1)

TPWRT

VDD

VBOR

Internal

Reset

(1)

TPWRT

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

6.3

Register Definitions: BOR Control

REGISTER 6-1:

BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u

SBOREN

bit 7

R/W-0/u

BORFS

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R-q/u

—

BORRDY

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

SBOREN: Software Brown-Out Reset Enable bit

If BOREN <1:0> in Configuration Words = 01:

1= BOR Enabled

0= BOR Disabled

If BOREN <1:0> in Configuration Words  01:

SBOREN is read/write, but has no effect on the BOR

(1)

BORFS: Brown-Out Reset Fast Start bit

If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):

1= Band gap is forced on always (covers sleep/wake-up/operating cases)

0= Band gap operates normally, and may turn off

If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)

BORFS is Read/Write, but has no effect.

bit 5-1

bit 0

Unimplemented: Read as ‘0’

BORRDY: Brown-Out Reset Circuit Ready Status bit

1= The Brown-out Reset circuit is active

0= The Brown-out Reset circuit is inactive

Note 1: BOREN<1:0> bits are located in Configuration Words.

DS40001609E-page 64

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6.4

Low-Power Brown-Out Reset

(LPBOR)

6.6

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDTinstruction within the time-out

period. The TO and PD bits in the STATUS register are

changed to indicate the WDT Reset. See Section

9.0 “Watchdog Timer (WDT)” for more information.

The Low-Power Brown-out Reset (LPBOR) operates

like the BOR to detect low voltage conditions on the

VDD pin. When too low of a voltage is detected, the

device is held in Reset. When this occurs, a register bit

(BOR) is changed to indicate that a BOR Reset has

occurred. The BOR bit in PCON is used for both BOR

and the LPBOR. Refer to Register 6-2.

6.7

RESETInstruction

A RESETinstruction will cause a device Reset. The RI

bit in the PCON register will be set to ‘0’. See Table 6-4

for default conditions after a RESET instruction has

occurred.

The LPBOR voltage threshold (Lapboard) has a wider

tolerance than the BOR (Vpor), but requires much less

current (LPBOR current) to operate. The LPBOR is

intended for use when the BOR is configured as dis-

abled (BOREN = 00) or disabled in Sleep mode

(BOREN = 10).

6.8

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON

register indicate the Reset condition. These Resets are

enabled by setting the STVREN bit in Configuration

Words. See Section 3.5.2 “Overflow/Underflow

Reset” for more information.

Refer to Figure 6-1 to see how the LPBOR interacts

with other modules.

6.4.1

ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of

Configuration Words. When the device is erased, the

LPBOR module defaults to disabled.

6.9

Programming Mode Exit

6.5

MCLR

Upon exit of Programming mode, the device will

behave as if a POR had just occurred.

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Words and the LVP bit of

Configuration Words (Table 6-2).

6.10 Power-Up Timer

The Power-up Timer optionally delays device execution

after a BOR or POR event. This timer is typically used to

allow VDD to stabilize before allowing the device to start

running.

TABLE 6-2:

MCLRE

MCLR CONFIGURATION

LVP

MCLR

The Power-up Timer is controlled by the PWRTE bit of

Configuration Words.

0

1

x

0

1

Disabled

Enabled

6.11 Start-up Sequence

Upon the release of a POR or BOR, the following must

occur before the device will begin executing:

6.5.1

MCLR ENABLED

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

1. Power-up Timer runs to completion (if enabled).

2. MCLR must be released (if enabled).

The total time-out will vary based on oscillator configu-

ration and Power-up Timer configuration. See Section

5.0 “Oscillator Module (With Fail-Safe Clock Moni-

tor)” for more information.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

Note:

A Reset does not drive the MCLR pin low.

The Power-up Timer runs independently of MCLR

Reset. If MCLR is kept low long enough, the Power-up

Timer will expire. Upon bringing MCLR high, the device

will begin execution after 10 FOSS cycles (see

Figure 6-3). This is useful for testing purposes or to

synchronize more than one device operating in parallel.

6.5.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 11.3 “PORTA Regis-

ters” for more information.

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FIGURE 6-3:

RESET START-UP SEQUENCE

Rev. 10-000032A

7/30/2013

VDD

Internal POR

Power-up Timer

MCLR

TPWRT

Internal RESET

Int. Oscillator

FOSC

Begin Execution

code execution ⁽¹⁾

Internal Oscillator, PWRTEN = 0

Internal Oscillator, PWRTEN = 1

VDD

Internal POR

Power-up Timer

MCLR

TPWRT

Internal RESET

Ext. Clock (EC)

FOSC

Begin Execution

code execution ⁽¹⁾

External Clock (EC modes), PWRTEN = 0

External Clock (EC modes), PWRTEN = 1

VDD

Internal POR

Power-up Timer

MCLR

TPWRT

Internal RESET

Osc Start-Up Timer

Ext. Oscillator

FOSC

TOST

Begin Execution

code

execution ⁽¹⁾

External Oscillators , PWRTEN = 0, IESO = 0

External Oscillators , PWRTEN = 1, IESO = 0

VDD

Internal POR

Power-up Timer

MCLR

TPWRT

Internal RESET

Osc Start-Up Timer

Ext. Oscillator

Int. Oscillator

TOST

FOSC

code execution ⁽¹⁾

Begin Execution

External Oscillators , PWRTEN = 0, IESO = 1

External Oscillators , PWRTEN = 1, IESO = 1

Note 1: Code execution begins 10 FOSC cycles after the FOSC clock is released.

DS40001609E-page 66

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6.12 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON registers are updated to indicate the cause of

the Reset. Table 6-3 and Table 6-4 show the Reset

conditions of these registers.

TABLE 6-3:

RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR

RI

POR BOR

TO

PD

Condition

0

u

1

u

0

u

1

u

0

u

1

u

0

u

1

u

0

u

0

u

x

0

u

1

0

x

1

0

1

u

1

u

1

x

0

1

u

0

u

0

u

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

TABLE 6-4:

RESET CONDITION FOR SPECIAL REGISTERS

Program

STATUS

Register

PCON

Register

Condition

Counter

Power-on Reset

0000h

---1 1000

00-- 110x

uu-- 0uuu

MCLR Reset during normal operation

0000h

---u muumuu

MCLR Reset during Sleep

WDT Reset

0000h

---1 0uuu

---0 muumuu

---0 0uuu

---1 1uuu

---1 0uuu

---u uuuu

uu-- 0uuu

uu-- uuuu

00-- 11u0

uu-- uuuu

uu-- u0uu

1u-- uuuu

u1-- uuuu

WDT Wake-up from Sleep

Brown-out Reset

PC + 1

0000h

Interrupt Wake-up from Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

PC + 1⁽¹⁾

0000h

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address

is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

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6.13 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

• MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON register bits are shown in Register 6-2.

6.14 Register Definitions: Power Control

REGISTER 6-2:

PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q

U-0

—

R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

RWDT RMCLR RI POR BOR

bit 0

STKOVF

bit 7

STKUNF

Legend:

HC = Bit is cleared by hardware

HS = Bit is set by hardware

U = Unimplemented bit, read as ‘0’

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

STKOVF: Stack Overflow Flag bit

1= A Stack Overflow occurred

0= A Stack Overflow has not occurred or cleared by firmware

STKUNF: Stack Underflow Flag bit

1= A Stack Underflow occurred

0= A Stack Underflow has not occurred or cleared by firmware

bit 5

bit 4

Unimplemented: Read as ‘0’

RWDT: Watchdog Timer Reset Flag bit

1= A Watchdog Timer Reset has not occurred or set by firmware

0= A Watchdog Timer Reset has occurred (cleared by hardware)

bit 3

bit 2

bit 1

bit 0

RMCLR: MCLR Reset Flag bit

1= A MCLR Reset has not occurred or set by firmware

0= A MCLR Reset has occurred (cleared by hardware)

RI: RESETInstruction Flag bit

1= A RESETinstruction has not been executed or set by firmware

0= A RESETinstruction has been executed (cleared by hardware)

POR: Power-On Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-Out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

DS40001609E-page 68

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TABLE 6-5:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BORCON SBOREN BORFS

—

RWDT

TO

—

RMCLR

PD

—

RI

Z

—

POR

DC

BORRDY

BOR

64

68

19

88

PCON

STKOVF STKUNF

STATUS

WDTCON

—

C

WDTPS<4:0>

SWDTEN

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.

TABLE 6-6: SUMMARY OF CONFIGURATION WORD WITH RESETS

Register

on Page

Name

Bits Bit -/7

Bit -/6 Bit 13/5 Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

CP

—

FCMEN

IESO

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

BORV STVREN

WRT<1:0>

—

CONFIG1

CONFIG2

43

MCLRE PWRTE

WDTE<1:0>

13:8

7:0

—

LVP

—

LPBOR

—

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

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7.0

INTERRUPTS

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

This chapter contains the following information for

Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

• INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the

corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 7-1.

FIGURE 7-1:

INTERRUPT LOGIC

Rev. 10-000010A

1/13/2014

TMR0IF

TMR0IE

Wake-up

(If in Sleep mode)

INTF

INTE

Peripheral Interrupts

(TMR1IF) PIR1<0>

IOCIF

IOCIE

Interrupt

to CPU

(TMR1IE) PIE1<0>

PEIE

GIE

PIRn<7>

PIEn<7>

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7.1

Operation

7.2

Interrupt Latency

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The latency for synchronous

interrupts is three or four instruction cycles. For

asynchronous interrupts, the latency is three to five

instruction cycles, depending on when the interrupt

occurs. See Figure 7-2 and Figure 7-3 for more details.

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIE1, PIE2 and PIE3 registers)

The INTCON, PIR1, PIR2 and PIR3 registers record

individual interrupts via interrupt flag bits. Interrupt flag

bits will be set, regardless of the status of the GIE, PEIE

and individual interrupt enable bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

shadow registers (See “Section 7.5 “Automatic

Context Saving”.”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

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FIGURE 7-2:

INTERRUPT LATENCY

Fosc

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Interrupt Sampled

during Q1

Interrupt

GIE

PC-1

PC

PC+1

0004h

0005h

PC

1-Cycle Instruction at PC

Execute

Inst(PC)

NOP

Inst(0004h)

Interrupt

GIE

PC+1/FSR

ADDR

New PC/

PC+1

PC-1

PC

0004h

0005h

PC

Execute

2-Cycle Instruction at PC

Inst(PC)

NOP

Inst(0004h)

Interrupt

GIE

PC-1

PC

FSR ADDR

INST(PC)

PC+1

PC+2

0004h

0005h

PC

Execute

3-Cycle Instruction at PC

NOP

Inst(0004h)

Inst(0005h)

Interrupt

GIE

PC-1

PC

FSR ADDR

INST(PC)

PC+1

PC+2

0004h

0005h

PC

NOP

Execute

3-Cycle Instruction at PC

NOP

Inst(0004h)

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FIGURE 7-3:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

FOSC

CLKOUT

(3)

INT pin

INTF

(1)

(2)

(4)

Interrupt Latency

GIE

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Forced NOP

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”.

4: INTF is enabled to be set any time during the Q4-Q1 cycles.

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7.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEPinstruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to Section 8.0 “Power-

Down Mode (Sleep)” for more details.

7.4

INT Pin

The INT pin can be used to generate an asynchronous

edge-triggered interrupt. This interrupt is enabled by

setting the INTE bit of the INTCON register. The

INTEDG bit of the OPTION_REG register determines on

which edge the interrupt will occur. When the INTEDG

bit is set, the rising edge will cause the interrupt. When

the INTEDG bit is clear, the falling edge will cause the

interrupt. The INTF bit of the INTCON register will be set

when a valid edge appears on the INT pin. If the GIE and

INTE bits are also set, the processor will redirect

program execution to the interrupt vector.

7.5

Automatic Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these regis-

ters are automatically restored. Any modifications to

these registers during the ISR will be lost. If modifica-

tions to any of these registers are desired, the corre-

sponding shadow register should be modified and the

value will be restored when exiting the ISR. The

shadow registers are available in Bank 31 and are

readable and writable. Depending on the user’s appli-

cation, other registers may also need to be saved.

DS40001609E-page 74

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

7.6

Register Definitions: Interrupt Control

REGISTER 7-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

GIE⁽¹⁾

R/W-0/0

PEIE⁽²⁾

R/W-0/0

TMR0IE

R/W-0/0

INTE

R/W-0/0

IOCIE

R/W-0/0

TMR0IF

R/W-0/0

INTF

R-0/0

IOCIF⁽³⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

GIE: Global Interrupt Enable bit⁽¹⁾

1= Enables all active interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit⁽²⁾

1= Enables all active peripheral interrupts

0= Disables all peripheral interrupts

TMR0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: INT External Interrupt Enable bit

1= Enables the INT external interrupt

0= Disables the INT external interrupt

IOCIE: Interrupt-on-Change Enable bit

1= Enables the interrupt-on-change

0= Disables the interrupt-on-change

TMR0IF: Timer0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed

0= TMR0 register did not overflow

INTF: INT External Interrupt Flag bit

1= The INT external interrupt occurred

0= The INT external interrupt did not occur

IOCIF: Interrupt-on-Change Interrupt Flag bit⁽³⁾

1= When at least one of the interrupt-on-change pins changed state

0= None of the interrupt-on-change pins have changed state

Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the

appropriate interrupt flag bits are clear prior to enabling an interrupt.

2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

3: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers

have been cleared by software.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 75

PIC16(L)F1508/9

REGISTER 7-2:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0

TMR1GIE

bit 7

R/W-0/0

ADIE

R/W-0/0

RCIE

R/W-0/0

TXIE

R/W-0/0

SSP1IE

U-0

—

R/W-0/0

TMR2IE

R/W-0/0

TMR1IE

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

TMR1GIE: Timer1 Gate Interrupt Enable bit

1= Enables the Timer1 gate acquisition interrupt

0= Disables the Timer1 gate acquisition interrupt

ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1= Enables the MSSP interrupt

0= Disables the MSSP interrupt

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

bit 0

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

DS40001609E-page 76

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

REGISTER 7-3:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

OSFIE

bit 7

R/W-0/0

C2IE

R/W-0/0

C1IE

U-0

—

R/W-0/0

BCL1IE

R/W-0/0

NCO1IE

U-0

—

U-0

—

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

bit 5

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enables the Oscillator Fail interrupt

0= Disables the Oscillator Fail interrupt

C2IE: Comparator C2 Interrupt Enable bit

1= Enables the Comparator C2 interrupt

0= Disables the Comparator C2 interrupt

C1IE: Comparator C1 Interrupt Enable bit

1= Enables the Comparator C1 interrupt

0= Disables the Comparator C1 interrupt

bit 4

bit 3

Unimplemented: Read as ‘0’

BCL1IE: MSSP Bus Collision Interrupt Enable bit

1= Enables the MSSP Bus Collision Interrupt

0= Disables the MSSP Bus Collision Interrupt

bit 2

NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit

1= Enables the NCO interrupt

0= Disables the NCO interrupt

bit 1-0

Unimplemented: Read as ‘0’

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 77

PIC16(L)F1508/9

REGISTER 7-4:

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

CLC4IE

R/W-0/0

CLC3IE

R/W-0/0

CLC2IE

R/W-0/0

CLC1IE

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

Unimplemented: Read as ‘0’

CLC4IE: Configurable Logic Block 4 Interrupt Enable bit

1= Enables the CLC 4 interrupt

0= Disables the CLC 4 interrupt

bit 2

bit 1

bit 0

CLC3IE: Configurable Logic Block 3 Interrupt Enable bit

1= Enables the CLC 3 interrupt

0= Disables the CLC 3 interrupt

CLC2IE: Configurable Logic Block 2 Interrupt Enable bit

1= Enables the CLC 2 interrupt

0= Disables the CLC 2 interrupt

CLC1IE: Configurable Logic Block 1 Interrupt Enable bit

1= Enables the CLC 1 interrupt

0= Disables the CLC 1 interrupt

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

DS40001609E-page 78

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

REGISTER 7-5:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0

TMR1GIF

bit 7

R/W-0/0

ADIF

R-0/0

RCIF

R/W-0/0

TXIF

R/W-0/0

SSP1IF

U-0

—

R/W-0/0

TMR2IF

R/W-0/0

TMR1IF

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

TMR1GIF: Timer1 Gate Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

ADIF: ADC Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

RCIF: USART Receive Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

TXIF: USART Transmit Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR2IF: Timer2 to PR2 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 0

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 79

PIC16(L)F1508/9

REGISTER 7-6:

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

OSFIF

R/W-0/0

C2IF

R/W-0/0

C1IF

U-0

—

R/W-0/0

BCL1IF

R/W-0/0

NCO1IF

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

bit 5

OSFIF: Oscillator Fail Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

C2IF: Comparator C2 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

C1IF: Comparator C1 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 4

bit 3

Unimplemented: Read as ‘0’

BCL1IF: MSSP Bus Collision Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 2

NCO1IF: Numerically Controlled Oscillator Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 1-0

Unimplemented: Read as ‘0’

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

DS40001609E-page 80

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

REGISTER 7-7:

PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

CLC4IF

R/W-0/0

CLC3IF

R/W-0/0

CLC2IF

R/W-0/0

CLC1IF

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

Unimplemented: Read as ‘0’

CLC4IF: Configurable Logic Block 4 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 2

bit 1

bit 0

CLC3IF: Configurable Logic Block 3 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

CLC2IF: Configurable Logic Block 2 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

CLC1IF: Configurable Logic Block 1 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 81

PIC16(L)F1508/9

TABLE 7-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

PSA

TMR0IF

INTF

IOCIF

75

154

76

77

78

79

80

81

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE

PS<2:0>

PIE1

PIE2

PIE3

PIR1

PIR2

PIR3

TMR1GIE

OSFIE

—

ADIE

C2IE

—

RCIE

C1IE

—

TXIE

—

SSP1IE

—

TMR2IE TMR1IE

BCL1IE NCO1IE

CLC4IE CLC3IE CLC2IE CLC1IE

SSP1IF TMR2IF TMR1IF

BCL1IF NCO1IF

CLC4IF CLC3IF CLC2IF CLC1IF

—

TMR1GIF

OSFIF

—

ADIF

C2IF

—

RCIF

C1IF

—

TXIF

—

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

DS40001609E-page 82

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

The first three events will cause a device Reset. The

last three events are considered a continuation of pro-

gram execution. To determine whether a device Reset

or wake-up event occurred, refer to Section

6.12 “Determining the Cause of a Reset”.

8.0

POWER-DOWN MODE (SLEEP)

The Power-down mode is entered by executing a

SLEEPinstruction.

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEPinstruction, the device will then call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

2. PD bit of the STATUS register is cleared.

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

5. 31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in

Sleep.

6. Timer1 and peripherals that operate from

Timer1 continue operation in Sleep when the

Timer1 clock source selected is:

•

LFINTOSC

T1CKI

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

Timer1 oscillator

8.1.1

WAKE-UP USING INTERRUPTS

7. ADC is unaffected, if the dedicated FRC oscillator

is selected.

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

8. I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or high-

impedance).

• If the interrupt occurs before the execution of a

SLEEPinstruction

9. Resets other than WDT are not affected by

Sleep mode.

- SLEEPinstruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following

conditions should be considered:

- PD bit of the STATUS register will not be

cleared.

• I/O pins should not be floating

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

- SLEEPinstruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared

• CWG, NCO and CLC modules using HFINTOSC

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching

currents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include the FVR module. See Section

13.0 “Fixed Voltage Reference (FVR)” for more

information on this module.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

8.1

Wake-up from Sleep

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin, if enabled

2. BOR Reset, if enabled

3. POR Reset

4. Watchdog Timer, if enabled

5. Any external interrupt

6. Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 83

PIC16(L)F1508/9

FIGURE 8-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN⁽¹⁾

(3)

CLKOUT⁽²⁾

TOST

Interrupt Latency⁽⁴⁾

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Forced NOP

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

External clock. High, Medium, Low mode assumed.

CLKOUT is shown here for timing reference.

TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes.

GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

2:

3:

4:

8.2.2

PERIPHERAL USAGE IN SLEEP

8.2

Low-Power Sleep Mode

Some peripherals that can operate in Sleep mode will

not operate properly with the Low-Power Sleep mode

selected. The LDO will remain in the Normal Power

mode when those peripherals are enabled. The Low-

Power Sleep mode is intended for use with these

peripherals:

This device contains an internal Low Dropout (LDO)

voltage regulator, which allows the device I/O pins to

operate at voltages up to 5.5V while the internal device

logic operates at a lower voltage. The LDO and its

associated reference circuitry must remain active when

the device is in Sleep mode.

• Brown-out Reset (BOR)

Low-Power Sleep mode allows the user to optimize the

operating current in Sleep. Low-Power Sleep mode can

be selected by setting the VREGPM bit of the

VREGCON register, putting the LDO and reference

circuitry in a low-power state whenever the device is in

Sleep.

• Watchdog Timer (WDT)

• External interrupt pin/Interrupt-on-change pins

• Timer1 (with external clock source)

The Complementary Waveform Generator (CWG), the

Numerically Controlled Oscillator (NCO) and the Con-

figurable Logic Cell (CLC) modules can utilize the

HFINTOSC oscillator as either a clock source or as an

input source. Under certain conditions, when the

HFINTOSC is selected for use with the CWG, NCO or

CLC modules, the HFINTOSC will remain active

during Sleep. This will have a direct effect on the

Sleep mode current.

8.2.1

SLEEP CURRENT VS. WAKE-UP

TIME

In the Default Operating mode, the LDO and reference

circuitry remain in the normal configuration while in

Sleep. The device is able to exit Sleep mode quickly

since all circuits remain active. In Low-Power Sleep

mode, when waking up from Sleep, an extra delay time

is required for these circuits to return to the normal con-

figuration and stabilize.

Please refer to sections Section 24.5 “Operation

During Sleep”, 25.7 “Operation In Sleep” and 26.10

“Operation During Sleep” for more information.

The Low-Power Sleep mode is beneficial for applica-

tions that stay in Sleep mode for long periods of time.

The Normal mode is beneficial for applications that

need to wake from Sleep quickly and frequently.

Note:

The PIC16LF1508/9 does not have a con-

figurable Low-Power Sleep mode.

PIC16LF1508/9 is an unregulated device

and is always in the lowest power state

when in Sleep, with no wake-up time pen-

alty. This device has a lower maximum

VDD and I/O voltage than the

PIC16F1508/9.

See

Section

29.0 “Electrical Specifications” for

more information.

DS40001609E-page 84

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

8.3

Register Definitions: Voltage Regulator Control

REGISTER 8-1:

VREGCON: VOLTAGE REGULATOR CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

R/W-1/1

VREGPM

Reserved

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-2

bit 1

Unimplemented: Read as ‘0’

VREGPM: Voltage Regulator Power Mode Selection bit

1= Low-Power Sleep mode enabled in Sleep⁽²⁾

Draws lowest current in Sleep, slower wake-up

0= Normal Power mode enabled in Sleep⁽²⁾

Draws higher current in Sleep, faster wake-up

bit 0

Reserved: Read as ‘1’. Maintain this bit set.

Note 1: PIC16F1508/9 only.

2: See Section 29.0 “Electrical Specifications”.

TABLE 8-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on

Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

IOCAF

IOCAN

IOCAP

IOCBF

IOCBN

IOCBP

GIE

—

PEIE

—

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

75

IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0

IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0

IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0

121

122

—

IOCBF7 IOCBF6 IOCBF5 IOCBF4

IOCBN7 IOCBN6 IOCBN5 IOCBN4

IOCBP7 IOCBP6 IOCBP5 IOCBP4

—

PIE1

TMR1GIE

ADIE

C2IE

—

RCIE

C1IE

—

TXIE

—

SSP1IE

TMR2IE TMR1IE

76

77

78

81

19

88

PIE2

OSFIE

—

BCL1IE NCO1IE

CLC4IE CLC3IE CLC2IE CLC1IE

SSP1IF TMR2IF TMR1IF

BCL1IF NCO1IF

—

PIE3

—

PIR1

TMR1GIF

OSFIF

—

ADIF

C2IF

—

RCIF

C1IF

—

TXIF

—

PIR2

—

CLC2IF

DC

—

CLC1IF

C

PIR3

—

CLC4IF

PD

CLC3IF

Z

STATUS

WDTCON

—

TO

—

WDTPS<4:0>

SWDTEN

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 85

PIC16(L)F1508/9

9.0

WATCHDOG TIMER (WDT)

The Watchdog Timer is a system timer that generates

a Reset if the firmware does not issue a CLRWDT

instruction within the time-out period. The Watchdog

Timer is typically used to recover the system from

unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (nominal)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 9-1:

WATCHDOG TIMER BLOCK DIAGRAM

Rev. 10-000141A

7/30/2013

WDTE<1:0> = 01

SWDTEN

WDT

Time-out

23-%it Programmable

WDTE<1:0> = 11

LFINTOSC

Prescaler WDT

WDTE<1:0> = 10

Sleep

WDTPS<4:0>

DS40001609E-page 86

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

9.1

Independent Clock Source

9.3

Time-Out Period

The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator. Time intervals in this

chapter are based on a nominal interval of 1 ms. See

Section 29.0 “Electrical Specifications” for the

LFINTOSC tolerances.

The WDTPS bits of the WDTCON register set the

time-out period from 1 ms to 256 seconds (nominal).

After a Reset, the default time-out period is two

seconds.

9.4

Clearing the WDT

9.2

WDT Operating Modes

The WDT is cleared when any of the following condi-

tions occur:

The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration

Words. See Table 9-1.

• Any Reset

• CLRWDTinstruction is executed

• Device enters Sleep

9.2.1

WDT IS ALWAYS ON

• Device wakes up from Sleep

• Oscillator fail

When the WDTE bits of Configuration Words are set to

‘11’, the WDT is always on.

• WDT is disabled

WDT protection is active during Sleep.

• Oscillator Start-up Timer (OST) is running

9.2.2

WDT IS OFF IN SLEEP

See Table 9-2 for more information.

When the WDTE bits of Configuration Words are set to

‘10’, the WDT is on, except in Sleep.

9.5

Operation During Sleep

WDT protection is not active during Sleep.

When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes

counting. When the device exits Sleep, the WDT is

cleared again.

9.2.3

WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to

‘01’, the WDT is controlled by the SWDTEN bit of the

WDTCON register.

The WDT remains clear until the OST, if enabled, com-

pletes. See Section 5.0 “Oscillator Module (With

Fail-Safe Clock Monitor)” for more information on the

OST.

WDT protection is unchanged by Sleep. See Table 9-1

for more details.

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits

in the STATUS register are changed to indicate the

event. The RWDT bit in the PCON register can also be

used. See Section 3.0 “Memory Organization” for

more information.

TABLE 9-1:

WDTE<1:0>

WDT OPERATING MODES

Device

Mode

WDT

Mode

SWDTEN

11

10

X

Active

Awake

Sleep Disabled

1

0

X

Active

01

Disabled

00

TABLE 9-2:

WDT CLEARING CONDITIONS

Conditions

WDT

WDTE<1:0> = 00

WDTE<1:0> = 01 and SWDTEN = 0

WDTE<1:0> = 10 and enter Sleep

CLRWDTCommand

Cleared

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

Unaffected

Change INTOSC divider (IRCF bits)

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9.6

Register Definitions: Watchdog Timer Control

REGISTER 9-1:

WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

R/W-0/0

R/W-1/1

R/W-0/0

R/W-1/1

R/W-0/0

WDTPS<4:0>

SWDTEN

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-1

Unimplemented: Read as ‘0’

WDTPS<4:0>: Watchdog Timer Period Select bits⁽¹⁾

Bit Value = Prescale Rate

11111 = Reserved. Results in minimum interval (1:32)

•

10011 = Reserved. Results in minimum interval (1:32)

10010 = 1:8388608 (2²³) (Interval 256s nominal)

10001 = 1:4194304 (2²²) (Interval 128s nominal)

10000 = 1:2097152 (2²¹) (Interval 64s nominal)

01111 = 1:1048576 (2²⁰) (Interval 32s nominal)

01110 = 1:524288 (2¹⁹) (Interval 16s nominal)

01101 = 1:262144 (2¹⁸) (Interval 8s nominal)

01100 = 1:131072 (2¹⁷) (Interval 4s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value)

01010 = 1:32768 (Interval 1s nominal)

01001 = 1:16384 (Interval 512 ms nominal)

01000 = 1:8192 (Interval 256 ms nominal)

00111 = 1:4096 (Interval 128 ms nominal)

00110 = 1:2048 (Interval 64 ms nominal)

00101 = 1:1024 (Interval 32 ms nominal)

00100 = 1:512 (Interval 16 ms nominal)

00011 = 1:256 (Interval 8 ms nominal)

00010 = 1:128 (Interval 4 ms nominal)

00001 = 1:64 (Interval 2 ms nominal)

00000 = 1:32 (Interval 1 ms nominal)

bit 0

SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = 1x:

This bit is ignored.

If WDTE<1:0> = 01:

1= WDT is turned on

0= WDT is turned off

If WDTE<1:0> = 00:

This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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TABLE 9-3:

SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON

PCON

—

STKOVF

—

IRCF<3:0>

—

RI

Z

SCS<1:0>

59

68

19

88

STKUNF

—

RWDT

TO

RMCLR

PD

POR

DC

BOR

C

STATUS

WDTCON

—

WDTPS<4:0>

SWDTEN

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

TABLE 9-4:

SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

—

CONFIG1

41

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

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Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared by hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

10.0 FLASH PROGRAM MEMORY

CONTROL

The Flash program memory is readable and writable

during normal operation over the full VDD range.

Program memory is indirectly addressed using Special

Function Registers (SFRs). The SFRs used to access

program memory are:

The WREN bit, when set, will allow a write operation to

occur. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted

by a Reset during normal operation. In these situations,

following Reset, the user can check the WRERR bit

and execute the appropriate error handling routine.

• PMCON1

• PMCON2

• PMDATL

• PMDATH

• PMADRL

• PMADRH

The PMCON2 register is a write-only register. Attempting

to read the PMCON2 register will return all ‘0’s.

To enable writes to the program memory, a specific

pattern (the unlock sequence), must be written to the

PMCON2 register. The required unlock sequence

prevents inadvertent writes to the program memory

write latches and Flash program memory.

When accessing the program memory, the

PMDATH:PMDATL register pair forms a 2-byte word

that holds the 14-bit data for read/write, and the

PMADRH:PMADRL register pair forms a 2-byte word

that holds the 15-bit address of the program memory

location being read.

10.2 Flash Program Memory Overview

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip charge

pump rated to operate over the operating voltage range

of the device.

It is important to understand the Flash program memory

structure for erase and programming operations. Flash

program memory is arranged in rows. A row consists of

a fixed number of 14-bit program memory words. A row

is the minimum size that can be erased by user software.

The Flash program memory can be protected in two

ways; by code protection (CP bit in Configuration Words)

and write protection (WRT<1:0> bits in Configuration

Words).

Code protection (CP = 0)⁽¹⁾, disables access, reading

and writing, to the Flash program memory via external

device programmers. Code protection does not affect

the self-write and erase functionality. Code protection

can only be reset by a device programmer performing

a Bulk Erase to the device, clearing all Flash program

memory, Configuration bits and User IDs.

After a row has been erased, the user can reprogram

all or a portion of this row. Data to be written into the

program memory row is written to 14-bit wide data write

latches. These write latches are not directly accessible

to the user, but may be loaded via sequential writes to

the PMDATH:PMDATL register pair.

Note:

If the user wants to modify only a portion

of a previously programmed row, then the

contents of the entire row must be read

and saved in RAM prior to the erase.

Then, new data and retained data can be

written into the write latches to reprogram

the row of Flash program memory. How-

ever, any unprogrammed locations can be

written without first erasing the row. In this

case, it is not necessary to save and

rewrite the other previously programmed

locations.

Write protection prohibits self-write and erase to a

portion or all of the Flash program memory, as defined

by the bits WRT<1:0>. Write protection does not affect

a device programmers ability to read, write or erase the

device.

Note 1: Code protection of the entire Flash

program memory array is enabled by

clearing the CP bit of Configuration Words.

See Table 10-1 for Erase Row size and the number of

write latches for Flash program memory.

10.1 PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up

to a maximum of 32K words of program memory. When

selecting a program address value, the MSB of the

address is written to the PMADRH register and the LSB

is written to the PMADRL register.

TABLE 10-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Write

Latches

(words)

Row Erase

(words)

Device

10.1.1

PMCON1 AND PMCON2

REGISTERS

PIC16(L)F1508

PIC16(L)F1509

32

PMCON1 is the control register for Flash program

memory accesses.

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10.2.1

READING THE FLASH PROGRAM

MEMORY

FIGURE 10-1:

FLASH PROGRAM

MEMORY READ

FLOWCHART

To read a program memory location, the user must:

1. Write the desired address to the

PMADRH:PMADRL register pair.

2. Clear the CFGS bit of the PMCON1 register.

Rev. 10-000046A

7/30/2013

Start

Read Operation

3. Then, set control bit RD of the PMCON1 register.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to

read the data. This causes the second instruction

immediately following the “BSF PMCON1,RD” instruction

to be ignored. The data is available in the very next cycle,

in the PMDATH:PMDATL register pair; therefore, it can

be read as two bytes in the following instructions.

Select

Program or Configuration Memory

(CFGS)

Select

Word Address

PMDATH:PMDATL register pair will hold this value until

another read or until it is written to by the user.

(PMADRH:PMADRL)

Note:

The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

2-cycle instruction on the next instruction

after the RD bit is set.

Initiate Read operation

(RD = 1)

Instruction fetched ignored

NOP execution forced

Instruction fetched ignored

NOPexecution forced

Data read now in

PMDATH:PMDATL

End

Read Operation

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FIGURE 10-2:

FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

PC + 1

PMADRH,PMADRL

PC + 3

PC+3

PC + 4

PC + 5

Flash ADDR

Flash Data

INSTR (PC)

INSTR (PC + 1)

PMDATH,PMDATL

INSTR (PC + 3)

INSTR (PC + 4)

INSTR(PC + 1)

INSTR(PC + 2)

instruction ignored instruction ignored

BSF PMCON1,RD

executed here

INSTR(PC - 1)

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

Forced NOP

executed here

RD bit

PMDATH

PMDATL

Register

EXAMPLE 10-1:

FLASH PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO

*

data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL

; Select Bank for PMCON registers

MOVLW

MOVWF

MOVLW

MOVWF

PROG_ADDR_LO

PMADRL

PROG_ADDR_HI

PMADRH

;

; Store LSB of address

;

; Store MSB of address

BCF

BSF

NOP

PMCON1,CFGS

PMCON1,RD

; Do not select Configuration Space

; Initiate read

; Ignored (Figure 10-2)

MOVF

PMDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

PMDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

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10.2.2

FLASH MEMORY UNLOCK

SEQUENCE

FIGURE 10-3:

FLASH PROGRAM

MEMORY UNLOCK

SEQUENCE FLOWCHART

The unlock sequence is a mechanism that protects the

Flash program memory from unintended self-write pro-

gramming or erasing. The sequence must be executed

and completed without interruption to successfully

complete any of the following operations:

Rev. 10-000047A

7/30/2013

Start

Unlock Sequence

• Row Erase

• Load program memory write latches

• Write of program memory write latches to

program memory

Write 0x55 to

PMCON2

• Write of program memory write latches to User

IDs

The unlock sequence consists of the following steps:

1. Write 55h to PMCON2

Write 0xAA to

PMCON2

2. Write AAh to PMCON2

3. Set the WR bit in PMCON1

4. NOPinstruction

Initiate

Write or Erase operation

(WR = 1)

5. NOPinstruction

Once the WR bit is set, the processor will always force

two NOP instructions. When an Erase Row or Program

Row operation is being performed, the processor will stall

internal operations (typical 2 ms), until the operation is

complete and then resume with the next instruction.

When the operation is loading the program memory write

latches, the processor will always force the two NOP

instructions and continue uninterrupted with the next

instruction.

Instruction fetched ignored

NOPexecution forced

Instruction fetched ignored

NOP execution forced

Since the unlock sequence must not be interrupted,

global interrupts should be disabled prior to the unlock

sequence and re-enabled after the unlock sequence is

completed.

End

Unlock Sequence

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10.2.3

ERASING FLASH PROGRAM

MEMORY

FIGURE 10-4:

FLASH PROGRAM

MEMORY ERASE

FLOWCHART

While executing code, program memory can only be

erased by rows. To erase a row:

Rev. 10-000048A

7/30/2013

1. Load the PMADRH:PMADRL register pair with

any address within the row to be erased.

Start

Erase Operation

2. Clear the CFGS bit of the PMCON1 register.

3. Set the FREE and WREN bits of the PMCON1

register.

4. Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

Disable Interrupts

(GIE = 0)

5. Set control bit WR of the PMCON1 register to

begin the erase operation.

See Example 10-2.

Select

Program or Configuration Memory

(CFGS)

After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The

user must place two NOP instructions immediately

following the WR bit set instruction. The processor will

halt internal operations for the typical 2 ms erase time.

This is not Sleep mode as the clocks and peripherals

will continue to run. After the erase cycle, the processor

will resume operation with the third instruction after the

PMCON1 write instruction.

Select Row Address

(PMADRH:PMADRL)

Select Erase Operation

(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence

(See Note 1)

CPU stalls while

Erase operation completes

(2 ms typical)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

Note 1: See Figure 10-3.

DS40001609E-page 94

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EXAMPLE 10-2:

ERASING ONE ROW OF PROGRAM MEMORY

; This row erase routine assumes the following:

; 1. A valid address within the erase row is loaded in ADDRH:ADDRL

; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF

INTCON,GIE

PMADRL

ADDRL,W

PMADRL

ADDRH,W

; Disable ints so required sequences will execute properly

; Load lower 8 bits of erase address boundary

; Load upper 6 bits of erase address boundary

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

BCF

PMADRH

PMCON1,CFGS

PMCON1,FREE

PMCON1,WREN

; Not configuration space

; Specify an erase operation

; Enable writes

BSF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required sequence to initiate erase

; Write 55h

;

; Write AAh

; Set WR bit to begin erase

NOP

; NOP instructions are forced as processor starts

; row erase of program memory.

;

; The processor stalls until the erase process is complete

; after erase processor continues with 3rd instruction

BCF

BSF

PMCON1,WREN

INTCON,GIE

; Disable writes

; Enable interrupts

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The following steps should be completed to load the

write latches and program a row of program memory.

These steps are divided into two parts. First, each write

latch is loaded with data from the PMDATH:PMDATL

using the unlock sequence with LWLO = 1. When the

last word to be loaded into the write latch is ready, the

LWLO bit is cleared and the unlock sequence

executed. This initiates the programming operation,

writing all the latches into Flash program memory.

10.2.4

WRITING TO FLASH PROGRAM

MEMORY

Program memory is programmed using the following

steps:

1. Load the address in PMADRH:PMADRL of the

row to be programmed.

2. Load each write latch with data.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

Note:

The special unlock sequence is required

to load a write latch with data or initiate a

Flash programming operation. If the

unlock sequence is interrupted, writing to

the latches or program memory will not be

initiated.

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten. Pro-

gram memory can only be erased one row at a time. No

automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at

a time. The maximum number of words written at one

time is equal to the number of write latches. See

Figure 10-5 (row writes to program memory with 32

write latches) for more details.

1. Set the WREN bit of the PMCON1 register.

2. Clear the CFGS bit of the PMCON1 register.

3. Set the LWLO bit of the PMCON1 register.

When the LWLO bit of the PMCON1 register is

‘1’, the write sequence will only load the write

latches and will not initiate the write to Flash

program memory.

The write latches are aligned to the Flash row address

boundary defined by the upper 10-bits of

PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)

with the lower five bits of PMADRL, (PMADRL<4:0>)

determining the write latch being loaded. Write opera-

tions do not cross these boundaries. At the completion

of a program memory write operation, the data in the

write latches is reset to contain 0x3FFF.

4. Load the PMADRH:PMADRL register pair with

the address of the location to be written.

5. Load the PMDATH:PMDATL register pair with

the program memory data to be written.

6. Execute the unlock sequence (Section

10.2.2 “Flash Memory Unlock Sequence”).

The write latch is now loaded.

7. Increment the PMADRH:PMADRL register pair

to point to the next location.

8. Repeat steps 5 through 7 until all but the last

write latch has been loaded.

9. Clear the LWLO bit of the PMCON1 register.

When the LWLO bit of the PMCON1 register is

‘0’, the write sequence will initiate the write to

Flash program memory.

10. Load the PMDATH:PMDATL register pair with

the program memory data to be written.

11.

Execute the unlock sequence (Section

10.2.2 “Flash Memory Unlock Sequence”).

The entire program memory latch content is now

written to Flash program memory.

Note:

The program memory write latches are

reset to the blank state (0x3FFF) at the

completion of every write or erase

operation. As a result, it is not necessary

to load all the program memory write

latches. Unloaded latches will remain in

the blank state.

An example of the complete write sequence is shown in

Example 10-3. The initial address is loaded into the

PMADRH:PMADRL register pair; the data is loaded

using indirect addressing.

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FIGURE 10-6:

FLASH MEMORY WRITE FLOWCHART

Rev. 10-000049A

7/30/2013

Start

Write Operation

Determine number of

words to be written into

Program or Configuration

Memory. The number of

words cannot exceed the

number of words per row

(word_cnt)

Enable Write/Erase

Operation (WREN = 1)

Load the value to write

(PMDATH:PMDATL)

Disable Interrupts

(GIE = 0)

Update the word counter

(word_cnt--)

Write Latches to Flash

(LWLO = 0)

Select

Program or Config.

Memory (CFGS)

Unlock Sequence

(See Note 1)

Last word to

write ?

Yes

Select Row Address

(PMADRH:PMADRL)

No

CPU stalls while Write

operation completes

(2 ms typical)

Unlock Sequence

(See Note 1)

Select Write Operation

(FREE = 0)

No delay when writing to

Program Memory Latches

Load Write Latches Only

Disable Write/Erase

Operation (WREN = 0)

(LWLO = 1)

Re-enable Interrupts

(GIE = 1)

Increment Address

(PMADRH:PMADRL++)

End

Write Operation

Note 1: See Figure 10-3.

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EXAMPLE 10-3:

WRITING TO FLASH PROGRAM MEMORY (32 WRITE LATCHES)

; This write routine assumes the following:

; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

;

BCF

INTCON,GIE

PMADRH

ADDRH,W

PMADRH

ADDRL,W

PMADRL

; Disable ints so required sequences will execute properly

; Bank 3

; Load initial address

;

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

LOW DATA_ADDR ; Load initial data address

FSR0L

HIGH DATA_ADDR ; Load initial data address

;

FSR0H

;

PMCON1,CFGS

PMCON1,WREN

PMCON1,LWLO

; Not configuration space

; Enable writes

; Only Load Write Latches

BSF

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

FSR0++

PMDATL

FSR0++

PMDATH

; Load first data byte into lower

;

; Load second data byte into upper

;

MOVF

PMADRL,W

0x1F

STATUS,Z

START_WRITE

; Check if lower bits of address are '00000'

; Check if we're on the last of 32 addresses

;

; Exit if last of 32 words,

;

XORLW

ANDLW

BTFSC

GOTO

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required write sequence:

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; NOP instructions are forced as processor

; loads program memory write latches

;

NOP

INCF

GOTO

PMADRL,F

LOOP

; Still loading latches Increment address

; Write next latches

START_WRITE

BCF

PMCON1,LWLO

; No more loading latches - Actually start Flash program

; memory write

MOVLW

55h

PMCON2

0AAh

PMCON2

PMCON1,WR

; Start of required write sequence:

; Write 55h

;

MOVWF

MOVLW

MOVWF

BSF

; Write AAh

; Set WR bit to begin write

; NOP instructions are forced as processor writes

; all the program memory write latches simultaneously

; to program memory.

NOP

; After NOPs, the processor

; stalls until the self-write process in complete

; after write processor continues with 3rd instruction

; Disable writes

BCF

BSF

PMCON1,WREN

INTCON,GIE

; Enable interrupts

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FIGURE 10-7:

FLASH PROGRAM

MEMORY MODIFY

FLOWCHART

10.3 Modifying Flash Program Memory

When modifying existing data in a program memory

row, and data within that row must be preserved, it must

first be read and saved in a RAM image. Program

memory is modified using the following steps:

Rev. 10-000050A

7/30/2013

1. Load the starting address of the row to be

modified.

Start

Modify Operation

2. Read the existing data from the row into a RAM

image.

3. Modify the RAM image to contain the new data

to be written into program memory.

Read Operation

(See Note 1)

4. Load the starting address of the row to be

rewritten.

5. Erase the program memory row.

An image of the entire row

read must be stored in RAM

6. Load the write latches with data from the RAM

image.

7. Initiate a programming operation.

Modify Image

The words to be modified are

changed in the RAM image

Erase Operation

(See Note 2)

Write Operation

Use RAM image

(See Note 3)

End

Modify Operation

Note 1: See Figure 10-2.

2: See Figure 10-4.

3: See Figure 10-5.

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10.4 User ID, Device ID and

Configuration Word Access

Instead of accessing program memory, the User ID’s,

Device ID/Revision ID and Configuration Words can be

accessed when CFGS = 1 in the PMCON1 register.

This is the region that would be pointed to by

PC<15> = 1, but not all addresses are accessible.

Different access may exist for reads and writes. Refer

to Table 10-2.

When read access is initiated on an address outside

the

parameters

listed

in

Table 10-2,

the

PMDATH:PMDATL register pair is cleared, reading

back ‘0’s.

TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)

Address

Function

Read Access

Write Access

8000h-8003h

8006h

User IDs

Yes

No

Device ID/Revision ID

Configuration Words 1 and 2

8007h-8008h

EXAMPLE 10-4:

CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:

*

PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL

; Select correct Bank

;

; Store LSB of address

; Clear MSB of address

MOVLW

MOVWF

CLRF

PROG_ADDR_LO

PMADRL

PMADRH

BSF

BCF

BSF

NOP

BSF

PMCON1,CFGS

INTCON,GIE

PMCON1,RD

; Select Configuration Space

; Disable interrupts

; Initiate read

; Executed (See Figure 10-2)

; Ignored (See Figure 10-2)

; Restore interrupts

INTCON,GIE

MOVF

PMDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

PMDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

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10.5 Write Verify

It is considered good programming practice to verify that

program memory writes agree with the intended value.

Since program memory is stored as a full page then the

stored program memory contents are compared with the

intended data stored in RAM after the last write is

complete.

FIGURE 10-8:

FLASH PROGRAM

MEMORY VERIFY

FLOWCHART

Rev. 10-000051A

7/30/2013

Start

Verify Operation

This routine assumes that the last

row of data written was from an

image saved on RAM. This image

will be used to verify the data

currently stored in Flash Program

Memory

Read Operation

(See Note 1)

PMDAT =

RAM image ?

No

Yes

Fail

Verify Operation

No

Last word ?

Yes

End

Verify Operation

Note 1: See Figure 10-2.

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10.6 Register Definitions: Flash Program Memory Control

REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u

PMDAT<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

PMDAT<7:0>: Read/write value for Least Significant bits of program memory

REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0

—

U-0

—

R/W-x/u

PMDAT<13:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

PMDAT<13:8>: Read/write value for Most Significant bits of program memory

REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0

PMADR<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

PMADR<7:0>: Specifies the Least Significant bits for program memory address

REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1

R/W-0/0

(1)

—

PMADR<14:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

Unimplemented: Read as ‘1’

bit 6-0

PMADR<14:8>: Specifies the Most Significant bits for program memory address

Note 1:

Unimplemented, read as ‘1’.

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REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

(2)

U-1

R/W-0/0

CFGS

R/W-0/0

LWLO

R/W/HC-0/0 R/W/HC-x/q

FREE WRERR

R/W-0/0

WREN

R/S/HC-0/0

WR

R/S/HC-0/0

RD

(1)

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

S = Bit can only be set

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

bit 6

Unimplemented: Read as ‘1’

CFGS: Configuration Select bit

1= Access Configuration, User ID and Device ID Registers

0= Access Flash program memory

(3)

bit 5

LWLO: Load Write Latches Only bit

1= Only the addressed program memory write latch is loaded/updated on the next WR command

0= The addressed program memory write latch is loaded/updated and a write of all program memory write latches

will be initiated on the next WR command

bit 4

bit 3

FREE: Program Flash Erase Enable bit

1= Performs an erase operation on the next WR command (hardware cleared upon completion)

0= Performs a write operation on the next WR command

WRERR: Program/Erase Error Flag bit

1= Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically

on any set attempt (write ‘1’) of the WR bit).

0= The program or erase operation completed normally.

bit 2

bit 1

WREN: Program/Erase Enable bit

1= Allows program/erase cycles

0= Inhibits programming/erasing of program Flash

WR: Write Control bit

1= Initiates a program Flash program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

0= Program/erase operation to the Flash is complete and inactive.

bit 0

RD: Read Control bit

1= Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set

(not cleared) in software.

0= Does not initiate a program Flash read.

Note 1: Unimplemented bit, read as ‘1’.

2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).

3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).

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REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0

Program Memory Control Register 2

W-0/0

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

S = Bit can only be set

‘1’ = Bit is set

bit 7-0

Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

PMCON1 register. The value written to this register is used to unlock the writes. There are specific

timing requirements on these writes.

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PMCON1

PMCON2

PMADRL

GIE

PEIE

TMR0IE

LWLO

INTE

IOCIE

TMR0IF

WREN

INTF

WR

IOCIF

RD

75

(1)

CFGS

FREE

WRERR

—

104

105

103

Program Memory Control Register 2

PMADRL<7:0>

(1)

PMADRH

PMDATL

—

PMADRH<6:0>

PMDATL<7:0>

PMDATH

—

PMDATH<5:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

Note 1: Unimplemented, read as ‘1’.

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH RESETS

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

CP

—

FCMEN

IESO

CLKOUTEN

BOREN<1:0>

—

CONFIG1

41

43

MCLRE PWRTE

WDTE<1:0>

FOSC<2:0>

STVREN

13:8

7:0

—

LVP

—

LPBOR

—

BORV

—

CONFIG2

—

WRT<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

 2011-2015 Microchip Technology Inc.

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FIGURE 11-1:

GENERIC I/O PORT

OPERATION

11.0 I/O PORTS

Each port has three standard registers for its operation.

These registers are:

Rev. 10-000052A

7/30/2013

• TRISx registers (data direction)

Read LATx

• PORTx registers (reads the levels on the pins of

the device)

TRISx

• LATx registers (output latch)

D

Q

Some ports may have one or more of the following

additional registers. These registers are:

Write LATx

Write PORTx

VDD

CK

• ANSELx (analog select)

• WPUx (weak pull-up)

Data Register

In general, when a peripheral is enabled on a port pin,

that pin cannot be used as a general purpose output.

However, the pin can still be read.

Data bus

I/O pin

Read PORTx

To digital peripherals

ANSELx

TABLE 11-1: PORT AVAILABILITY PER

DEVICE

To analog peripherals

VSS

Device

PIC16(L)F1508/9

●

The Data Latch (LATx registers) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

A write operation to the LATx register has the same

effect as a write to the corresponding PORTx register.

A read of the LATx register reads of the values held in

the I/O PORT latches, while a read of the PORTx

register reads the actual I/O pin value.

Ports that support analog inputs have an associated

ANSELx register. When an ANSEL bit is set, the digital

input buffer associated with that bit is disabled.

Disabling the input buffer prevents analog signal levels

on the pin between a logic high and low from causing

excessive current in the logic input circuitry. A

simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 11-1.

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These bits have no effect on the values of any TRIS

register. PORT and TRIS overrides will be routed to the

correct pin. The unselected pin will be unaffected.

11.1 Alternate Pin Function

The Alternate Pin Function Control (APFCON) register

is used to steer specific peripheral input and output

functions between different pins. The APFCON register

is shown in Register 11-1. For this device family, the

following functions can be moved between different

pins.

• SS

• T1G

• CLC1

• NCO1

11.2 Register Definitions: Alternate Pin Function Control

REGISTER 11-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

R/W-0/0

SSSEL

R/W-0/0

T1GSEL

U-0

—

R/W-0/0

CLC1SEL

NCO1SEL

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4

Unimplemented: Read as ‘0’

SSSEL: Pin Selection bit

1= SS function is on RA3

0= SS function is on RC6

bit 3

T1GSEL: Pin Selection bit

1= T1G function is on RA3

0= T1G function is on RA4

bit 2

bit 1

Unimplemented: Read as ‘0’

CLC1SEL: Pin Selection bit

1= CLC1 function is on RC5

0= CLC1 function is on RA2

bit 0

NCO1SEL: Pin Selection bit

1= NCO1 function is on RC6

0= NCO1 function is on RC1

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11.3.4

PORTA FUNCTIONS AND OUTPUT

PRIORITIES

11.3 PORTA Registers

11.3.1

DATA REGISTER

Each PORTA pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 11-2.

PORTA is a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 11-3). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). The exception is RA3, which is

input-only and its TRIS bit will always read as ‘1’.

Example 11-1 shows how to initialize an I/O port.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input functions, such as ADC and comparator

inputs, are not shown in the priority lists. These inputs

are active when the I/O pin is set for Analog mode using

the ANSELx registers. Digital output functions may

control the pin when it is in Analog mode with the

priority shown below in Table 11-2.

Reading the PORTA register (Register 11-2) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATA).

TABLE 11-2: PORTA OUTPUT PRIORITY

(1)

Pin Name

Function Priority

RA0

ICSPDAT

DAC1OUT1

RA0

11.3.2

DIRECTION CONTROL

RA1

RA2

RA1

The TRISA register (Register 11-3) controls the

PORTA pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISA register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

DAC1OUT2

CLC1

(2)

C1OUT

PWM3

RA2

RA3

RA4

None

CLKOUT

SOSCO

RA4

11.3.3

ANALOG CONTROL

The ANSELA register (Register 11-5) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

RA5

SOSCI

RA5

Note 1: Priority listed from highest to lowest.

2: Default pin (see APFCON register).

3: Alternate pin (see APFCON register).

The state of the ANSELA bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

Note:

The ANSELA bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

EXAMPLE 11-1:

INITIALIZING PORTA

BANKSEL PORTA

;

CLRF

BANKSEL LATA

CLRF LATA

BANKSEL ANSELA

CLRF ANSELA

BANKSEL TRISA

PORTA

;Init PORTA

;Data Latch

;

;digital I/O

;

MOVLW

MOVWF

B'00111000' ;Set RA<5:3> as inputs

TRISA

;and set RA<2:0> as

;outputs

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11.4 Register Definitions: PORTA

REGISTER 11-2: PORTA: PORTA REGISTER

U-0

—

U-0

—

R/W-x/x

RA5

R/W-x/x

RA4

R-x/x

RA3

R/W-x/x

RA2

R/W-x/x

RA1

R/W-x/x

RA0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RA<5:0>: PORTA I/O Value bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return

of actual I/O pin values.

REGISTER 11-3: TRISA: PORTA TRI-STATE REGISTER

U-0

—

U-0

—

R/W-1/1

TRISA5

R/W-1/1

TRISA4

U-1

R/W-1/1

TRISA2

R/W-1/1

TRISA1

R/W-1/1

TRISA0

(1)

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

TRISA<5:4>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

bit 3

Unimplemented: Read as ‘1’

bit 2-0

TRISA<2:0>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

Note 1: Unimplemented, read as ‘1’.

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REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER

U-0

—

U-0

—

R/W-x/u

LATA5

R/W-x/u

LATA4

U-0

—

R/W-x/u

LATA2

R/W-x/u

LATA1

R/W-x/u

LATA0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

bit 3

Unimplemented: Read as ‘0’

LATA<5:4>: RA<5:4> Output Latch Value bits⁽¹⁾

Unimplemented: Read as ‘0’

bit 2-0

LATA<2:0>: RA<2:0> Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return

of actual I/O pin values.

REGISTER 11-5: ANSELA: PORTA ANALOG SELECT REGISTER

U-0

—

U-0

—

U-0

—

R/W-1/1

ANSA4

U-0

—

R/W-1/1

ANSA2

R/W-1/1

ANSA1

R/W-1/1

ANSA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4

Unimplemented: Read as ‘0’

ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

bit 3

Unimplemented: Read as ‘0’

bit 2-0

ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

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REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER

U-0

—

U-0

—

R/W-1/1

WPUA5

R/W-1/1

WPUA4

R/W-1/1

WPUA3

R/W-1/1

WPUA2

R/W-1/1

WPUA1

R/W-1/1

WPUA0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

WPUA<5:0>: Weak Pull-up Register bits⁽³⁾

1= Pull-up enabled

0= Pull-up disabled

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is configured as an output.

3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

—

ANSA4

SSSEL

LATA4

—

ANSA2

—

ANSA1

ANSA0

110

107

110

154

109

111

T1GSEL

APFCON

LATA

CLC1SEL NCO1SEL

—

LATA5

TMR0CS

RA5

—

LATA2

LATA1

PS<2:0>

RA1

LATA0

OPTION_REG

PORTA

WPUEN

—

INTEDG

—

TMR0SE

RA4

PSA

RA3

RA2

RA0

(1)

—

TRISA

—

TRISA5

WPUA5

TRISA4

WPUA4

TRISA2

WPUA2

TRISA1

WPUA1

TRISA0

WPUA0

WPUA

—

WPUA3

Legend:

Note 1:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Unimplemented, read as ‘1’.

TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH PORTA

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

—

CONFIG1

41

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

 2011-2015 Microchip Technology Inc.

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11.5.4

PORTB FUNCTIONS AND OUTPUT

PRIORITIES

11.5 PORTB Registers

11.5.1

DATA REGISTER

Each PORTB pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 11-5.

PORTB is a 4-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 11-8). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., disable the

output driver). Clearing a TRISB bit (= 0) will make the

corresponding PORTB pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). Example 11-1 shows how to

initialize an I/O port.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input functions, such as ADC and comparator

inputs, are not shown in the priority lists. These inputs

are active when the I/O pin is set for Analog mode using

the ANSELx registers. Digital output functions may

control the pin when it is in Analog mode with the

priority shown below in Table 11-5.

Reading the PORTB register (Register 11-7) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATB).

TABLE 11-5: PORTB OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

RB4

SDA

RB4

11.5.2

DIRECTION CONTROL

The TRISB register (Register 11-8) controls the

PORTB pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISB register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

RB5

RB6

RB5

SCL

SCK

RB6

RB7

CLC3

TX

RB7

11.5.3

ANALOG CONTROL

Note 1: Priority listed from highest to lowest.

2: Default pin (see APFCON register).

3: Alternate pin (see APFCON register).

The ANSELB register (Register 11-10) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELB bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

Note:

The ANSELB bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

DS40001609E-page 112

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11.6 Register Definitions: PORTB

REGISTER 11-7: PORTB: PORTB REGISTER

R/W-x/x

RB7

R/W-x/x

RB6

R/W-x/x

RB5

R/W-x/x

RB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

RB<7:4>: PORTB I/O Value bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

bit 3-0

Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is

return of actual I/O pin values.

REGISTER 11-8: TRISB: PORTB TRI-STATE REGISTER

R/W-1/1

TRISB7

R/W-1/1

TRISB6

R/W-1/1

TRISB5

R/W-1/1

TRISB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

bit 3-0

RB<7:4>: PORTB Tri-State Control bits

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

Unimplemented: Read as ‘0’

 2011-2015 Microchip Technology Inc.

DS40001609E-page 113

PIC16(L)F1508/9

REGISTER 11-9: LATB: PORTB DATA LATCH REGISTER

R/W-x/u

LATB7

R/W-x/u

LATB6

R/W-x/u

LATB5

R/W-x/u

LATB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

bit 3-0

LATB<7:4>: RB<7:4> Output Latch Value bits⁽¹⁾

Unimplemented: Read as ‘0’

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is

return of actual I/O pin values.

REGISTER 11-10: ANSELB: PORTB ANALOG SELECT REGISTER

U-0

—

U-0

—

R/W-1/1

ANSB5

R/W-1/1

ANSB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

bit 3-0

Unimplemented: Read as ‘0’

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

DS40001609E-page 114

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PIC16(L)F1508/9

REGISTER 11-11: WPUB: WEAK PULL-UP PORTB REGISTER^(1),(2)

R/W-1/1

WPUB7

R/W-1/1

WPUB6

R/W-1/1

WPUB5

R/W-1/1

WPUB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

WPUB<7:4>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is configured as an output.

TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

—

ANSB5

—

ANSB4

SSSEL

LATB4

TMR0SE

RB4

—

T1GSEL

—

114

107

114

154

113

115

APFCON

LATB

—

CLC1SEL NCO1SEL

LATB7

WPUEN

RB7

LATB6

INTEDG

RB6

LATB5

TMR0CS

RB5

—

PS<2:0>

—

OPTION_REG

PORTB

TRISB

PSA

—

TRISB7

WPUB7

TRISB6

WPUB6

TRISB5

WPUB5

TRISB4

WPUB4

—

WPUB

—

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

Note 1: Unimplemented, read as ‘1’.

TABLE 11-7: SUMMARY OF CONFIGURATION WORD WITH PORTB

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN

BOREN<1:0>

FOSC<2:0>

—

CONFIG1

41

CP

MCLRE

WDTE<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTB.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 115

PIC16(L)F1508/9

11.7.4

PORTC FUNCTIONS AND OUTPUT

PRIORITIES

11.7 PORTC Registers

11.7.1

DATA REGISTER

Each PORTC pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 11-8.

PORTC is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC

(Register 11-13). Setting a TRISC bit (= 1) will make

the corresponding PORTC pin an input (i.e., disable

the output driver). Clearing a TRISC bit (= 0) will make

the corresponding PORTC pin an output (i.e., enable

the output driver and put the contents of the output

latch on the selected pin). Example 11-1 shows how to

initialize an I/O port.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not

included in the output priority list. These input functions

can remain active when the pin is configured as an

output. Certain digital input functions override other

port functions and are included in the output priority list.

Reading the PORTC register (Register 11-12) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATC).

TABLE 11-8: PORTC OUTPUT PRIORITY

Pin Name

Function Priority⁽¹⁾

RC0

CLC2

RC0

11.7.2

DIRECTION CONTROL

RC1

NCO1⁽²⁾

PWM4

RC1

The TRISC register (Register 11-13) controls the

PORTC pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISC register are maintained set when using them

as analog inputs. I/O pins configured as analog input

always read ‘0’.

RC2

RC3

RC2

PWM2

RC3

RC4

CWG1B

CLC4

C2OUT

RC4

11.7.3

ANALOG CONTROL

The ANSELC register (Register 11-15) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELC bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

RC5

CWG1A

CLC1⁽³⁾

PWM1

RC5

NCO1⁽³⁾

RC6

The state of the ANSELC bits has no effect on digital out-

put functions. A pin with TRIS clear and ANSELC set will

still operate as a digital output, but the Input mode will be

analog. This can cause unexpected behavior when exe-

cuting read-modify-write instructions on the affected

port.

RC6

RC7

SDO

RC7

Note 1: Priority listed from highest to lowest.

2: Default pin (see APFCON register).

3: Alternate pin (see APFCON register).

Note:

The ANSELC bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

DS40001609E-page 116

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11.8 Register Definitions: PORTC

REGISTER 11-12: PORTC: PORTC REGISTER

R/W-x/u

RC7

R/W-x/u

RC6

R/W-x/u

RC5

R/W-x/u

RC4

R/W-x/u

RC3

R/W-x/u

RC2

R/W-x/u

RC1

R/W-x/u

RC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

RC<7:0>: PORTC General Purpose I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 11-13: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1

TRISC7

R/W-1/1

TRISC6

R/W-1/1

TRISC5

R/W-1/1

TRISC4

R/W-1/1

TRISC3

R/W-1/1

TRISC2

R/W-1/1

TRISC1

R/W-1/1

TRISC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

REGISTER 11-14: LATC: PORTC DATA LATCH REGISTER

R/W-x/u

LATC7

R/W-x/u

LATC6

R/W-x/u

LATC5

R/W-x/u

LATC4

R/W-x/u

LATC3

R/W-x/u

LATC2

R/W-x/u

LATC1

R/W-x/u

LATC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

LATC<7:0>: PORTC Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is

return of actual I/O pin values.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 117

PIC16(L)F1508/9

REGISTER 11-15: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1/1

ANSC7

R/W-1/1

ANSC6

U-0

—

U-0

—

R/W-1/1

ANSC3

R/W-1/1

ANSC2

R/W-1/1

ANSC1

R/W-1/1

ANSC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-6

ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

TABLE 11-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELC

LATC

ANSC7

LATC7

RC7

ANSC6

LATC6

RC6

—

ANSC3

LATC3

RC3

ANSC2

LATC2

RC2

ANSC1

LATC1

RC1

ANSC0

LATC0

RC0

118

117

LATC5

RC5

LATC4

RC4

PORTC

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

Legend:

x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

DS40001609E-page 118

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PIC16(L)F1508/9

12.3 Interrupt Flags

12.0 INTERRUPT-ON-CHANGE

The IOCAFx and IOCBFx bits located in the IOCAF and

IOCBF registers, respectively, are status flags that

correspond to the interrupt-on-change pins of the

associated port. If an expected edge is detected on an

appropriately enabled pin, then the status flag for that pin

will be set, and an interrupt will be generated if the IOCIE

bit is set. The IOCIF bit of the INTCON register reflects

the status of all IOCAFx and IOCBFx bits.

The PORTA and PORTB pins can be configured to

operate as Interrupt-on-Change (IOC) pins. An interrupt

can be generated by detecting a signal that has either a

rising edge or a falling edge. Any individual port pin, or

combination of port pins, can be configured to generate

an interrupt. The interrupt-on-change module has the

following features:

• Interrupt-on-Change enable (Master Switch)

• Individual pin configuration

12.4 Clearing Interrupt Flags

• Rising and falling edge detection

• Individual pin interrupt flags

The individual status flags, (IOCAFx and IOCBFx bits),

can be cleared by resetting them to zero. If another edge

is detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

Figure 12-1 is a block diagram of the IOC module.

12.1 Enabling the Module

To allow individual port pins to generate an interrupt, the

IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will

still occur, but an interrupt will not be generated.

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

EXAMPLE 12-1:

CLEARING INTERRUPT

FLAGS

(PORTA EXAMPLE)

12.2 Individual Pin Configuration

For each port pin, a rising edge detector and a falling

edge detector are present. To enable a pin to detect a

rising edge, the associated bit of the IOCxP register is

set. To enable a pin to detect a falling edge, the

associated bit of the IOCxN register is set.

MOVLW 0xff

XORWF IOCAF, W

ANDWF IOCAF, F

A pin can be configured to detect rising and falling

edges simultaneously by setting both associated bits of

the IOCxP and IOCxN registers, respectively.

12.5 Operation in Sleep

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCxF

register will be updated prior to the first instruction

executed out of Sleep.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 119

PIC16(L)F1508/9

FIGURE 12-1:

INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)

Rev. 10-000 037A

6/2/201 4

D

Q

IOCANx

R

Q4Q1

edge

detect

RAx

to data bus

IOCAFx

S

data bus =

0 or 1

D

Q

D

Q

IOCAPx

write IOCAFx

R

IOCIE

Q2

IOC interrupt

to CPU core

from all other

IOCnFx individual

pin detectors

FOSC

Q1

Q2

Q3

Q4

Q4Q1

DS40001609E-page 120

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PIC16(L)F1508/9

12.6 Register Definitions: Interrupt-on-Change Control

REGISTER 12-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

U-0

—

U-0

—

R/W-0/0

IOCAP5

R/W-0/0

IOCAP4

R/W-0/0

IOCAP3

R/W-0/0

IOCAP2

R/W-0/0

IOCAP1

R/W-0/0

IOCAP0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set

upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

REGISTER 12-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER

U-0

—

U-0

—

R/W-0/0

IOCAN5

R/W-0/0

IOCAN4

R/W-0/0

IOCAN3

R/W-0/0

IOCAN2

R/W-0/0

IOCAN1

R/W-0/0

IOCAN0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set

upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

REGISTER 12-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

U-0

—

U-0

—

R/W/HS-0/0

IOCAF5

R/W/HS-0/0

IOCAF4

R/W/HS-0/0

IOCAF3

R/W/HS-0/0

IOCAF2

R/W/HS-0/0

IOCAF1

R/W/HS-0/0

IOCAF0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCAPx = 1and a rising edge was detected on RAx, or when IOCANx = 1and a falling edge was

detected on RAx.

0= No change was detected, or the user cleared the detected change.

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DS40001609E-page 121

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REGISTER 12-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER

R/W-0/0

IOCBP7

R/W-0/0

IOCBP6

R/W-0/0

IOCBP5

R/W-0/0

IOCBP4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set

upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

bit 3-0

Unimplemented: Read as ‘0’

REGISTER 12-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER

R/W-0/0

IOCBN7

R/W-0/0

IOCBN6

R/W-0/0

IOCBN5

R/W-0/0

IOCBN4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3-0

IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set

upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

Unimplemented: Read as ‘0’

REGISTER 12-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER

R/W/HS-0/0

IOCBF7

R/W/HS-0/0

IOCBF6

R/W/HS-0/0

IOCBF5

R/W/HS-0/0

IOCBF4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-4

bit 3-0

IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling edge was

detected on RBx.

0= No change was detected, or the user cleared the detected change.

Unimplemented: Read as ‘0’

DS40001609E-page 122

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

—

GIE

—

PEIE

—

ANSA4

INTE

—

IOCIE

IOCAF3

IOCAN3

IOCAP3

—

ANSA2

TMR0IF

IOCAF2

IOCAN2

IOCAP2

—

ANSA1

INTF

IOCAF1

IOCAN1

IOCAP1

—

ANSA0

IOCIF

IOCAF0

IOCAN0

IOCAP0

—

110

75

INTCON

IOCAF

IOCAN

IOCAP

IOCBF

IOCBN

IOCBP

TRISA

TRISB

Legend:

TMR0IE

IOCAF5

IOCAN5

IOCAP5

IOCBF5

IOCBN5

IOCBP5

TRISA5

TRISB5

—

IOCAF4

IOCAN4

IOCAP4

IOCBF4

IOCBN4

IOCBP4

TRISA4

TRISB4

121

122

109

113

—

IOCBF7

IOCBN7

IOCBP7

—

IOCBF6

IOCBN6

IOCBP6

—

—(1)

—

TRISA2

—

TRISA1

—

TRISA0

—

TRISB7

TRISB6

—

— = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.

Note 1: Unimplemented, read as ‘1’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 123

PIC16(L)F1508/9

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the ADC module. Refer-

ence Section 15.0 “Analog-to-Digital Converter

(ADC) Module” for additional information.

13.0 FIXED VOLTAGE REFERENCE

(FVR)

The Fixed Voltage Reference (FVR) is a stable voltage

reference, independent of VDD, with a nominal output

level (VFVR) of 1.024V. The output of the FVR can be

configured to supply a reference voltage to the

following:

The CDAFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the comparator modules.

Reference Section 17.0 “Comparator Module” for

additional information.

• ADC input channel

• Comparator positive input

• Comparator negative input

To minimize current consumption when the FVR is

disabled, the FVR buffers should be turned off by

clearing the Buffer Gain Selection bits.

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

13.2 FVR Stabilization Period

13.1 Independent Gain Amplifier

When the Fixed Voltage Reference module is enabled,

it requires time for the reference and amplifier circuits

to stabilize. Once the circuits stabilize and are ready for

use, the FVRRDY bit of the FVRCON register will be

set. See the FVR Stabilization Period characterization

graph, Figure 30-64.

The output of the FVR supplied to the peripherals, (listed

above), is routed through a programmable gain amplifier.

Each amplifier can be programmed for a gain of 1x, 2x or

4x, to produce the three possible voltage levels.

FIGURE 13-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

Rev. 10-000053A

8/6/2013

2

ADFVR<1:0>

1x

2x

4x

FVR_buffer1

(To ADC Module)

CDAFVR<1:0>

1x

2x

4x

FVR_buffer2

(To Comparators)

FVREN

Note 1

+

FVRRDY

_

TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Peripheral

Conditions

Description

HFINTOSC

FOSC<2:0> = 010and

INTOSC is active and device is not in Sleep.

IRCF<3:0> = 000x

BOREN<1:0> = 11

BOR always enabled.

BOR

LDO

BOREN<1:0> = 10and BORFS = 1

BOREN<1:0> = 01and BORFS = 1

BOR disabled in Sleep mode, BOR Fast Start enabled.

BOR under software control, BOR Fast Start enabled.

All PIC16F1508/9 devices, when

VREGPM = 1and not in Sleep

The device runs off of the Low-Power Regulator when in Sleep

mode.

DS40001609E-page 124

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

13.3 Register Definitions: FVR Control

REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0

FVREN⁽¹⁾

R-q/q

FVRRDY⁽²⁾

R/W-0/0

TSEN⁽³⁾

R/W-0/0

TSRNG⁽³⁾

R/W-0/0

CDAFVR<1:0>⁽¹⁾

ADFVR<1:0>⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

bit 4

bit 3-2

FVREN: Fixed Voltage Reference Enable bit⁽¹⁾

1= Fixed Voltage Reference is enabled

0= Fixed Voltage Reference is disabled

FVRRDY: Fixed Voltage Reference Ready Flag bit⁽²⁾

1= Fixed Voltage Reference output is ready for use

0= Fixed Voltage Reference output is not ready or not enabled

TSEN: Temperature Indicator Enable bit⁽³⁾

1= Temperature Indicator is enabled

0= Temperature Indicator is disabled

TSRNG: Temperature Indicator Range Selection bit⁽³⁾

1= VOUT = VDD - 4VT (High Range)

0= VOUT = VDD - 2VT (Low Range)

CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits⁽¹⁾

11= Comparator FVR Buffer Gain is 4x, with output voltage = 4x VFVR (4.096V nominal)⁽⁴⁾

10= Comparator FVR Buffer Gain is 2x, with output voltage = 2x VFVR (2.048V nominal)⁽⁴⁾

01= Comparator FVR Buffer Gain is 1x, with output voltage = 1x VFVR (1.024V nominal)

00= Comparator FVR Buffer is off

bit 1-0

ADFVR<1:0>: ADC FVR Buffer Gain Selection bit⁽¹⁾

11= ADC FVR Buffer Gain is 4x, with output voltage = 4x VFVR (4.096V nominal)⁽⁴⁾

10= ADC FVR Buffer Gain is 2x, with output voltage = 2x VFVR (2.048V nominal)⁽⁴⁾

01= ADC FVR Buffer Gain is 1x, with output voltage = 1x VFVR (1.024V nominal)

00= ADC FVR Buffer is off

Note 1: To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by clear-

ing the Buffer Gain Selection bits.

2: FVRRDY is always ‘1’ for the PIC16F1508/9 devices.

3: See Section 14.0 “Temperature Indicator Module” for additional information.

4: Fixed Voltage Reference output cannot exceed VDD.

TABLE 13-2: SUMMARYOF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

FVREN

FVRRDY

TSEN

TSRNG

CDAFVR>1:0>

ADFVR<1:0>

125

Legend:

Shaded cells are unused by the Fixed Voltage Reference module.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 125

PIC16(L)F1508/9

FIGURE 14-1:

TEMPERATURE CIRCUIT

DIAGRAM

14.0 TEMPERATURE INDICATOR

MODULE

Rev. 10-000069A

7/31/2013

This family of devices is equipped with a temperature

circuit designed to measure the operating temperature

of the silicon die. The circuit’s range of operating

temperature falls between -40°C and +85°C. The

output is a voltage that is proportional to the device

temperature. The output of the temperature indicator is

internally connected to the device ADC.

VDD

TSEN

The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,

depending on the level of calibration performed. A one-

point calibration allows the circuit to indicate a

temperature closely surrounding that point. A two-point

calibration allows the circuit to sense the entire range

of temperature more accurately. Reference Application

Note AN1333, “Use and Calibration of the Internal

Temperature Indicator” (DS01333) for more details

regarding the calibration process.

TSRNG

VOUT

To ADC

Temp. Indicator

14.1 Circuit Operation

Figure 14-1 shows a simplified block diagram of the

temperature circuit. The proportional voltage output is

achieved by measuring the forward voltage drop across

multiple silicon junctions.

14.2 Minimum Operating VDD

When the temperature circuit is operated in low range,

the device may be operated at any operating voltage

that is within specifications.

Equation 14-1 describes the output characteristics of

the temperature indicator.

When the temperature circuit is operated in high range,

the device operating voltage, VDD, must be high

enough to ensure that the temperature circuit is

correctly biased.

EQUATION 14-1: VOUT RANGES

High Range: VOUT = VDD - 4VT

Low Range: VOUT = VDD - 2VT

Table 14-1 shows the recommended minimum VDD vs.

range setting.

TABLE 14-1: RECOMMENDED VDD VS.

RANGE

The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See Section

13.0 “Fixed Voltage Reference (FVR)” for more

information.

Min. VDD, TSRNG = 1

Min. VDD, TSRNG = 0

3.6V

1.8V

The circuit is enabled by setting the TSEN bit of the

FVRCON register. When disabled, the circuit draws no

current.

14.3 Temperature Output

The output of the circuit is measured using the internal

Analog-to-Digital Converter. A channel is reserved for

the temperature circuit output. Refer to Section

15.0 “Analog-to-Digital Converter (ADC) Module” for

detailed information.

The circuit operates in either high or low range. The high

range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This

provides more resolution over the temperature range,

but may be less consistent from part to part. This range

requires a higher bias voltage to operate and thus, a

higher VDD is needed.

14.4 ADC Acquisition Time

To ensure accurate temperature measurements, the

user must wait at least 200 s after the ADC input

multiplexer is connected to the temperature indicator

output before the conversion is performed. In addition,

the user must wait 200 s between sequential

conversions of the temperature indicator output.

The low range is selected by clearing the TSRNG bit of

the FVRCON register. The low range generates a lower

voltage drop and thus, a lower bias voltage is needed to

operate the circuit. The low range is provided for low

voltage operation.

DS40001609E-page 126

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

FVREN

FVRRDY

TSEN

TSRNG

CDAFVR>1:0>

ADFVR<1:0>

125

Legend:

Shaded cells are unused by the temperature indicator module.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 127

PIC16(L)F1508/9

approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 15-1 shows the block diagram of the ADC.

15.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

The ADC voltage reference is software selectable to be

either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

FIGURE 15-1:

ADC BLOCK DIAGRAM

Rev. 10-000033A

V

DD

ADPREF

7/30/2013

Positive

Reference

Select

V

DD

VREF+ pin

ADCS<2:0>

F

V

SS

AN0

ANa

VRNEG VRPOS

External

Channel

Inputs

.

Fosc

OSC/n

F

OSC

Divider

ADC

Clock

Select

ADC_clk

sampled

input

F

RC

ANz

F

RC

Temp Indicator

DACx_output

FVR_buffer1

Internal

Channel

Inputs

ADC CLOCK SOURCE

ADFM

ADC

Sample Circuit

CHS<4:0>

set bit ADIF

10

complete

start

10-bit Result

16

Write to bit

GO/DONE

Q1

Q4

ADRESH

ADRESL

Q2

Enable

Trigger Select

TRIGSEL<3:0>

ADON

. . .

V

SS

Trigger Sources

AUTO CONVERSION

TRIGGER

DS40001609E-page 128

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

15.1.4

CONVERSION CLOCK

15.1 ADC Configuration

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• FOSC/2

• Channel selection

• FOSC/4

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• FOSC/8

• FOSC/16

• FOSC/32

• Result formatting

• FOSC/64

15.1.1

PORT CONFIGURATION

• FRC (internal RC oscillator)

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to Section

11.0 “I/O Ports” for more information.

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11.5 TAD

periods as shown in Figure 15-2.

For correct conversion, the appropriate TAD specifica-

tion must be met. Refer to the ADC conversion require-

ments in Section 29.0 “Electrical Specifications” for

more information. Table 15-1 gives examples of

appropriate ADC clock selections.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

15.1.2

CHANNEL SELECTION

There are 15 channel selections available:

• AN<11:0> pins

• Temperature Indicator

• DAC1_output

• FVR_buffer1

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay (TACQ) is required

before starting the next conversion. Refer to Section

15.2.6 “ADC Conversion Procedure” for more infor-

mation.

15.1.3

ADC VOLTAGE REFERENCE

The ADC module uses a positive and a negative

voltage reference. The positive reference is labeled

ref+ and the negative reference is labeled ref-.

The positive voltage reference (ref+) is selected by the

ADPREF bits in the ADCON1 register. The positive

voltage reference source can be:

• VREF+ pin

• VDD

The negative voltage reference (ref-) source is:

• VSS

 2011-2015 Microchip Technology Inc.

DS40001609E-page 129

PIC16(L)F1508/9

TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC

ADCS<2:0

Clock

>

20 MHz

16 MHz

8 MHz

4 MHz

1 MHz

Source

Fosc/2

Fosc/4

Fosc/8

Fosc/16

Fosc/32

Fosc/64

FRC

000

100

001

101

010

110

x11

100 ns

200 ns

400 ns

800 ns

1.6 s

125 ns

250 ns

500 ns

1.0 s

2.0 s

4.0 s

250 ns

500 ns

1.0 s

2.0 s

4.0 s

8.0 s

500 ns

1.0 s

2.0 s

4.0 s

2.0 s

8.0 s

4.0 s

16.0 s

32.0 s

64.0 s

1.0-6.0 s

8.0 s

3.2 s

16.0 s

1.0-6.0 s

Legend: Shaded cells are outside of recommended range.

Note:

The TAD period when using the FRC clock source can fall within a specified range, (see TAD parameter).

The TAD period when using the FOSC-based clock source can be configured for a more precise TAD period.

However, the FRC clock source must be used when conversions are to be performed with the device in

Sleep mode.

FIGURE 15-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

Rev. 10-000035A

7/30/2013

TAD1

TAD2

b9

TAD3

b8

TAD4

b7

TAD5

b6

TAD6

b5

TAD7

b4

TAD8

b3

TAD9

b2

TAD10

b1

TAD11

b0

THCD

Conversion Starts

TACQ

On the following cycle:

Holding capacitor disconnected

from analog input (THCD).

ADRESH:ADRESL is loaded,

GO bit is cleared,

Set GO bit

ADIF bit is set,

holding capacitor is reconnected to analog input.

Enable ADC (ADON bit)

and

Select channel (ACS bits)

DS40001609E-page 130

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

15.1.5

INTERRUPTS

15.1.6

RESULT FORMATTING

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

The 10-bit ADC conversion result can be supplied in

two formats, left justified or right justified. The ADFM bit

of the ADCON1 register controls the output format.

Figure 15-3 shows the two output formats.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the FRC oscillator is selected.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEPinstruc-

tion is always executed. If the user is attempting to

wake-up from Sleep and resume in-line code execu-

tion, the GIE and PEIE bits of the INTCON register

must be disabled. If the GIE and PEIE bits of the

INTCON register are enabled, execution will switch to

the Interrupt Service Routine.

FIGURE 15-3:

10-BIT ADC CONVERSION RESULT FORMAT

Rev. 10-000054A

7/30/2013

ADRESH

ADRESL

LSB

(ADFM = 0) MSB

bit 7

bit 0

bit 7

bit 0

10-bit ADC Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 0

bit 7

Unimplemented: Read as ‘0’

10-bit ADC Result

 2011-2015 Microchip Technology Inc.

DS40001609E-page 131

PIC16(L)F1508/9

15.2.4

ADC OPERATION DURING SLEEP

15.2 ADC Operation

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. Performing the ADC conversion during Sleep

can reduce system noise. If the ADC interrupt is

enabled, the device will wake-up from Sleep when the

conversion completes. If the ADC interrupt is disabled,

the ADC module is turned off after the conversion com-

pletes, although the ADON bit remains set.

15.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 15.2.6 “ADC Conver-

sion Procedure”.

When the ADC clock source is something other than

FRC, a SLEEPinstruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

15.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

15.2.5

AUTO-CONVERSION TRIGGER

• Clear the GO/DONE bit

The auto-conversion trigger allows periodic ADC mea-

surements without software intervention. When a rising

edge of the selected source occurs, the GO/DONE bit

is set by hardware.

• Set the ADIF Interrupt Flag bit

• Update the ADRESH and ADRESL registers with

new conversion result

The auto-conversion trigger source is selected with the

TRIGSEL<3:0> bits of the ADCON2 register.

15.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH and ADRESL registers will be updated with

the partially complete Analog-to-Digital conversion

sample. Incomplete bits will match the last bit

converted.

Using the auto-conversion trigger does not assure

proper ADC timing. It is the user’s responsibility to

ensure that the ADC timing requirements are met.

See Table 15-2 for auto-conversion sources.

TABLE 15-2: AUTO-CONVERSION

SOURCES

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

Source Peripheral

Timer0

Signal Name

T0_overflow

Timer1

T1_overflow

T2_match

C1OUT_sync

C2OUT_sync

LC1_out

Timer2

Comparator C1

Comparator C2

CLC1

CLC2

LC2_out

CLC3

LC3_out

CLC4

LC4_out

DS40001609E-page 132

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

15.2.6

ADC CONVERSION PROCEDURE

EXAMPLE 15-1:

ADC CONVERSION

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

;This code block configures the ADC

;for polling, Vdd and Vss references, FRC

;oscillator and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

register)

• Configure pin as analog (Refer to the ANSEL

register)

BANKSEL

MOVLW

ADCON1

;

B’11110000’ ;Right justify, FRC

;oscillator

• Disable weak pull-ups either globally (Refer

to the OPTION_REG register) or individually

(Refer to the appropriate WPUx register).

MOVWF

BANKSEL

BSF

BANKSEL

BSF

ADCON1

TRISA

TRISA,0

ANSEL

ANSEL,0

WPUA

WPUA,0

;Vdd and Vss Vref+

;

;Set RA0 to input

;

;Set RA0 to analog

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

BANKSEL

BCF

;Disable weak

pull-up on RA0

;

BANKSEL

MOVLW

MOVWF

CALL

ADCON0

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

B’00000001’ ;Select channel AN0

ADCON0

SampleTime

;Turn ADC On

;Acquisiton delay

• Enable ADC interrupt

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

BANKSEL

MOVF

ADCON0,ADGO ;Start conversion

ADCON0,ADGO ;Is conversion done?

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

$-1

ADRESH

;No, test again

;

.

ADRESH,W

RESULTHI

ADRESL

;Read upper 2 bits

;store in GPR space

;

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

ADRESL,W

RESULTLO

;Read lower 8 bits

;Store in GPR space

• Polling the GO/DONE bit

MOVWF

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 15.4 “ADC Acquisi-

tion Requirements”.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 133

PIC16(L)F1508/9

15.3 Register Definitions: ADC Control

REGISTER 15-1: ADCON0: ADC CONTROL REGISTER 0

U-0

—

R/W-0/0

ADON

CHS<4:0>

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-2

CHS<4:0>: Analog Channel Select bits

00000= AN0

00001= AN1

00010= AN2

00011= AN3

00100= AN4

00101= AN5

00110= AN6

00111= AN7

01000= AN8

01001= AN9

01010= AN10

01011= AN11

01100= Reserved. No channel connected.

•

11100= Reserved. No channel connected.

11101= Temperature Indicator⁽¹⁾

11110= DAC (Digital-to-Analog Converter)⁽³⁾

11111=FVR (Fixed Voltage Reference) Buffer 1 Output⁽²⁾

GO/DONE: ADC Conversion Status bit

bit 1

bit 0

1= ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.

This bit is automatically cleared by hardware when the ADC conversion has completed.

0= ADC conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

Note 1: See Section 14.0 “Temperature Indicator Module” for more information.

2: See Section 13.0 “Fixed Voltage Reference (FVR)” for more information.

3: See Section 16.0 “5-Bit Digital-to-Analog Converter (DAC) Module” for more information.

DS40001609E-page 134

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PIC16(L)F1508/9

REGISTER 15-2: ADCON1: ADC CONTROL REGISTER 1

R/W-0/0

ADFM

R/W-0/0

U-0

—

U-0

—

R/W-0/0

ADCS<2:0>

ADPREF<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

ADFM: ADC Result Format Select bit

1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is

loaded.

0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is

loaded.

bit 6-4

ADCS<2:0>: ADC Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

011= FRC (clock supplied from an internal RC oscillator)

100= FOSC/4

101= FOSC/16

110= FOSC/64

111= FRC (clock supplied from an internal RC oscillator)

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits

00= VRPOS is connected to VDD

01= Reserved

10= VRPOS is connected to external VREF+ pin⁽¹⁾

11= Reserved

Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage

specification exists. See Section 29.0 “Electrical Specifications” for details.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 135

PIC16(L)F1508/9

REGISTER 15-3: ADCON2: ADC CONTROL REGISTER 2

R/W-0/0

TRIGSEL<3:0>⁽¹⁾

R/W-0/0

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-4

TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits⁽¹⁾

0000= No auto-conversion trigger selected

0001= Reserved

0010= Reserved

0011= Timer0 – T0_overflow⁽²⁾

0100= Timer1 – T1_overflow⁽²⁾

0101= Timer2 – T2_match

0110= Comparator C1 – C1OUT_sync

0111= Comparator C2 – C2OUT_sync

1000= CLC1 – LC1_out

1001= CLC2 – LC2_out

1010= CLC3 – LC3_out

1011= CLC4 – LC4_out

1100= Reserved

1101= Reserved

1110= Reserved

1111= Reserved

bit 3-0

Unimplemented: Read as ‘0’

Note 1: This is a rising edge sensitive input for all sources.

2: Signal also sets its corresponding interrupt flag.

DS40001609E-page 136

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PIC16(L)F1508/9

REGISTER 15-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u

bit 0

ADRES<9:2>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

REGISTER 15-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

ADRES<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result

Reserved: Do not use.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 137

PIC16(L)F1508/9

REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

ADRES<9:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-2

bit 1-0

Reserved: Do not use.

ADRES<9:8>: ADC Result Register bits

Upper two bits of 10-bit conversion result

REGISTER 15-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u

ADRES<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

DS40001609E-page 138

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PIC16(L)F1508/9

source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (or changed), an ADC acquisition must be

done before the conversion can be started. To calculate

the minimum acquisition time, Equation 15-1 may be

used. This equation assumes that 1/2 LSb error is used

(1,024 steps for the ADC). The 1/2 LSb error is the

maximum error allowed for the ADC to meet its

specified resolution.

15.4 ADC Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 15-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 15-4. The maximum recommended

impedance for analog sources is 10 k. As the

EQUATION 15-1: ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + Temperature - 25°C0.05µs/°C

The value for TC can be approximated with the following equations:

1





;[1] VCHOLD charged to within 1/2 lsb

^VAPPLIED^{1 – -------------------------- = VCHOLD}



2^{n + 1} – 1

–TC

---------





RC

VAPPLIED 1 – e

= V^CHOLD







;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]



–Tc

--------









RC

1







^{= VAPPLIED}^{1 – --------------------------}

2^{n + 1} – 1

VAPPLIED 1 – e





Note: Where n = number of bits of the ADC.

Solving for TC:

TC = –CHOLDRIC + RSS + RS ln(1/2047)

= –12.5pF1k + 7k + 10k ln(0.0004885)

= 1.72µs

Therefore:

TACQ = 2µs + 1.72µs + 50°C- 25°C0.05µs/°C

= 4.97µs

Note 1: The reference voltage (VRPOS) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 139

PIC16(L)F1508/9

FIGURE 15-4:

ANALOG INPUT MODEL

Rev. 10-000070A

8/2/2013

V

DD

Sampling

Analog

switch

V

T

§ 0.6V

SS

Input pin

RS

R

IC 1

K

RSS

(1)

ILEAKAGE

CHOLD = 10 pF

Ref-

CPIN

5pF

VA

6V

5V

Legend: CHOLD

= Sample/Hold Capacitance

= Input Capacitance

VDD 4V

3V

RSS

CPIN

I

LEAKAGE = Leakage Current at the pin due to varies injunctions

2V

R

IC

= Interconnect Resistance

= Resistance of Sampling switch

= Sampling Switch

R

SS

5 6 7 8 91011

Sampling Switch

(k )

VT

= Threshold Voltage

Note 1: Refer to Section 29.0 “Electrical Specifications”.

FIGURE 15-5:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

03h

02h

01h

00h

Analog Input Voltage

1.5 LSB

0.5 LSB

Zero-Scale

Transition

Ref-

Full-Scale

Transition

Ref+

DS40001609E-page 140

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PIC16(L)F1508/9

TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

ADCON1

ADCON2

ADRESH

ADRESL

ANSELA

ANSELB

ANSELC

INTCON

PIE1

—

CHS<4:0>

GO/DONE

ADON

134

135

ADFM

ADCS<2:0>

—

ADPREF<1:0>

TRIGSEL<3:0>

—

136

ADC Result Register High

ADC Result Register Low

137, 138

110

—

ANSA4

ANSB4

—

ANSA2

—

ANSA1

—

ANSA0

—

ANSB5

—

114

ANSC7

GIE

ANSC6

PEIE

ANSC3

IOCIE

SSP1IE

ANSC2

TMR0IF

—

ANSC1

INTF

ANSC0

IOCIF

TMR1IE

TMR1IF

TRISA0

—

118

TMR0IE

RCIE

INTE

75

TMR1GIE

TMR1GIF

—

ADIE

TXIE

TMR2IE

TMR2IF

TRISA1

—

76

PIR1

ADIF

RCIF

TXIF

SSP1IF

—

79

—(1)

TRISA

—

TRISA5

TRISB5

TRISC5

TSEN

TRISA4

TRISB4

TRISC4

TSRNG

TRISA2

—

109

TRISB

TRISB7

TRISC7

FVREN

TRISB6

TRISC6

FVRRDY

—

113

TRISC

TRISC3

TRISC2

TRISC1

TRISC0

117

FVRCON

Legend:

CDAFVR<1:0>

ADFVR<1:0>

125

x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not

used for ADC module.

Note 1: Unimplemented, read as ‘1’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 141

PIC16(L)F1508/9

The output of the DAC (DACx_output) can be selected

as a reference voltage to the following:

16.0 5-BIT DIGITAL-TO-ANALOG

CONVERTER (DAC) MODULE

• Comparator positive input

• ADC input channel

• DACxOUT1 pin

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,

with 32 selectable output levels.

• DACxOUT2 pin

The positive input source (VSOURCE+) of the DAC can

be connected to:

The Digital-to-Analog Converter (DAC) can be enabled

by setting the DACEN bit of the DACxCON0 register.

• External VREF+ pin

• VDD supply voltage

The negative input source (VSOURCE-) of the DAC can

be connected to:

• Vss

FIGURE 16-1:

DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

Rev. 10-000026A

7/30/2013

VDD

0

1

VSOURCE+

VREF+

DACR<4:0>

5

R

DACPSS

DACEN

DACx_output

To Peripherals

32

Steps

R

DACxOUT1 ⁽¹⁾

DACOE1

DACxOUT2 ⁽¹⁾

DACOE2

VSOURCE-

VSS

Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).

DS40001609E-page 142

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PIC16(L)F1508/9

16.1 Output Voltage Selection

16.4 Operation During Sleep

The DAC has 32 voltage level ranges. The 32 levels

are set with the DACR<4:0> bits of the DACxCON1

register.

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the DACxCON0 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

The DAC output voltage can be determined by using

Equation 16-1.

16.5 Effects of a Reset

16.2 Ratiometric Output Level

A device Reset affects the following:

• DACx is disabled.

The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage

of either input source fluctuates, a similar fluctuation will

result in the DAC output value.

• DACX output voltage is removed from the

DACxOUTn pin(s).

• The DACR<4:0> range select bits are cleared.

The value of the individual resistors within the ladder

can be found in Table 29-14.

16.3 DAC Voltage Reference Output

The unbuffered DAC voltage can be output to the

DACxOUTn pin(s) by setting the respective DACOEn

bit(s) of the DACxCON0 register. Selecting the DAC

reference voltage for output on either DACxOUTn pin

automatically overrides the digital output buffer, the

weak pull-up and digital input threshold detector

functions of that pin.

Reading the DACxOUTn pin when it has been

configured for DAC reference voltage output will

EQUATION 16-1: DAC OUTPUT VOLTAGE

IF DACEN = 1

DACR4:0





DACx_output = VSOURCE+ – VSOURCE-  ----------------------------- + VSOURCE-

2⁵





Note:

See the DACxCON0 register for the available VSOURCE+ and VSOURCE- selections.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 143

PIC16(L)F1508/9

16.6 Register Definitions: DAC Control

REGISTER 16-1: DACxCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0

DACEN

U-0

—

R/W-0/0

U-0

—

R/W-0/0

U-0

—

U-0

—

DACOE1

DACOE2

DACPSS

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

DACEN: DAC Enable bit

1= DACx is enabled

0= DACx is disabled

bit 6

bit 5

Unimplemented: Read as ‘0’

DACOE1: DAC Voltage Output Enable bit

1= DACx voltage level is output on the DACxOUT1 pin

0= DACx voltage level is disconnected from the DACxOUT1 pin

bit 4

DACOE2: DAC Voltage Output Enable bit

1= DACx voltage level is output on the DACxOUT2 pin

0= DACx voltage level is disconnected from the DACxOUT2 pin

bit 3

bit 2

Unimplemented: Read as ‘0’

DACPSS: DAC Positive Source Select bit

1=

0=

VREF+ pin

VDD

bit 1-0

Unimplemented: Read as ‘0’

REGISTER 16-2: DACxCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0/0

DACR<4:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

DACR<4:0>: DAC Voltage Output Select bits

TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DAC1CON0

DAC1CON1

Legend:

DACEN

—

DACOE1

—

DACOE2

—

DACPSS

—

144

DACR<4:0>

— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

DS40001609E-page 144

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

17.1

Comparator Overview

17.0 COMPARATOR MODULE

A single comparator is shown in Figure 17-2 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

Comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of program execution. The analog

comparator module includes the following features:

The comparators available for this device are listed in

Table 17-1.

• Independent comparator control

• Programmable input selection

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

TABLE 17-1: AVAILABLE COMPARATORS

Device

C1

C2

• Wake-up from Sleep

PIC16(L)F1508

PIC16(L)F1509

●

• Programmable Speed/Power optimization

• PWM shutdown

• Programmable and fixed voltage reference

FIGURE 17-1:

COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM

Rev. 10-000027A

8/5/2013

CxINTP

3

Interrupt

CxNCH<2:0>

CxON⁽¹⁾

Rising

Edge

set bit

CxIF

CxIN0-

CxIN1-

000

CxINTN

D

001

010

011

100

Interrupt

Falling

Edge

CxIN2-

CxON⁽¹⁾

Cx

CxIN3-

CxVN

CxVP

CxOUT

MCxOUT

FVR_buffer2

-

Q

CxIN+

DAC_out

00

01

10

+

Q1

CxOUT_async

CxSP CxHYS

CxPOL

to

FVR_buffer2

peripherals

11

CxOUT_sync

CxOE

to

CxPCH<1:0>

CxON⁽¹⁾

2

peripherals

CxSYNC

Q

TRIS bit

0

CxOUT

D

1

(From Timer1 Module) T1CLK

 2011-2015 Microchip Technology Inc.

DS40001609E-page 145

PIC16(L)F1508/9

• CxIN+ analog pin

• DAC1_output

• FVR_buffer2

• VSS

FIGURE 17-2:

SINGLE COMPARATOR

VIN+

VIN-

+

–

Output

See Section 13.0 “Fixed Voltage Reference (FVR)”

for more information on the Fixed Voltage Reference

module.

See Section 16.0 “5-Bit Digital-to-Analog Converter

(DAC) Module” for more information on the DAC input

signal.

VIN-

VIN+

Any time the comparator is disabled (CxON = 0), all

comparator inputs are disabled.

17.2.3

COMPARATOR NEGATIVE INPUT

SELECTION

Output

The CxNCH<2:0> bits of the CMxCON0 register direct

one of the input sources to the comparator inverting

input.

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

Note:

To use CxIN+ and CxINx- pins as analog

input, the appropriate bits must be set in

the ANSEL register and the correspond-

ing TRIS bits must also be set to disable

the output drivers.

17.2 Comparator Control

Each comparator has two control registers: CMxCON0

and CMxCON1.

17.2.4

COMPARATOR OUTPUT

SELECTION

The CMxCON0 registers (see Register 17-1) contain

Control and Status bits for the following:

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CMOUT register. In order to

make the output available for an external connection,

the following conditions must be true:

• Enable

• Output selection

• Output polarity

• Speed/Power selection

• Hysteresis enable

• Output synchronization

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

The CMxCON1 registers (see Register 17-2) contain

Control bits for the following:

The

synchronous

comparator

output

signal

(CxOUT_sync) is available to the following peripheral(s):

• Interrupt enable

• Configurable Logic Cell (CLC)

• Analog-to-Digital Converter (ADC)

• Timer1

• Interrupt edge polarity

• Positive input channel selection

• Negative input channel selection

The

asynchronous

comparator

output

signal

17.2.1

COMPARATOR ENABLE

(CxOUT_async) is available to the following peripheral(s):

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

•

Complementary Waveform Generator (CWG)

Note 1: The CxOE bit of the CMxCON0 register

overrides the PORT data latch. Setting

the CxON bit of the CMxCON0 register

has no impact on the port override.

17.2.2

COMPARATOR POSITIVE INPUT

SELECTION

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

Configuring the CxPCH<1:0> bits of the CMxCON1

register directs an internal voltage reference or an

analog pin to the non-inverting input of the comparator:

DS40001609E-page 146

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PIC16(L)F1508/9

17.2.5

COMPARATOR OUTPUT POLARITY

17.3 Analog Input Connection

Considerations

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

A simplified circuit for an analog input is shown in

Figure 17-3. Since the analog input pins share their

connection with a digital input, they have reverse

biased ESD protection diodes to VDD and VSS. The

analog input, therefore, must be between VSS and VDD.

If the input voltage deviates from this range by more

than 0.6V in either direction, one of the diodes is for-

ward biased and a latch-up may occur.

Table 17-2 shows the output state versus input

conditions, including polarity control.

TABLE 17-2:

COMPARATOR OUTPUT

STATE VS. INPUT CONDITIONS

A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

Input Condition

CxPOL

CxOUT

CxVN > CxVP

CxVN < CxVP

CxVN > CxVP

CxVN < CxVP

0

1

0

1

0

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

17.2.6

COMPARATOR SPEED/POWER

SELECTION

The trade-off between speed or power can be opti-

mized during program execution with the CxSP control

bit. The default state for this bit is ‘1’ which selects the

Normal-Speed mode. Device power consumption can

be optimized at the cost of slower comparator propaga-

tion delay by clearing the CxSP bit to ‘0’.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

FIGURE 17-3:

ANALOG INPUT MODEL

Rev. 10-000071A

8/2/2013

VDD

Analog

VT § 0.6V

Input pin

RS < 10K

RIC

To Comparator

(1)

ILEAKAGE

CPIN

5pF

VA

VSS

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

VT

= Interconnect Resistance

= Source Impedance

= Analog Voltage

= Threshold Voltage

Note 1: See Section 29.0 “Electrical Specifications”.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 147

PIC16(L)F1508/9

The associated interrupt flag bit, CxIF bit of the PIR2

register, must be cleared in software. If another edge is

detected while this flag is being cleared, the flag will still

be set at the end of the sequence.

17.4 Comparator Hysteresis

A selectable amount of separation voltage can be

added to the input pins of each comparator to provide a

hysteresis function to the overall operation. Hysteresis

is enabled by setting the CxHYS bit of the CMxCON0

register.

Note:

Although a comparator is disabled, an

interrupt can be generated by changing

the output polarity with the CxPOL bit of

the CMxCON0 register, or by switching

the comparator on or off with the CxON bit

of the CMxCON0 register.

See Section 29.0 “Electrical Specifications” for

more information.

17.5 Timer1 Gate Operation

The output resulting from a comparator operation can

be used as a source for gate control of Timer1. See

Section 19.6 “Timer1 Gate” for more information.

This feature is useful for timing the duration or interval

of an analog event.

17.7 Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the comparator

differs from the settling time of the voltage reference.

Therefore, both of these times must be considered when

determining the total response time to a comparator

input change. See the Comparator and Voltage Refer-

ence Specifications in Section 29.0 “Electrical Specifi-

cations” for more details.

It is recommended that the comparator output be syn-

chronized to Timer1. This ensures that Timer1 does not

increment while a change in the comparator is occur-

ring.

17.5.1

COMPARATOR OUTPUT

SYNCHRONIZATION

The output from the Cx comparator can be

synchronized with Timer1 by setting the CxSYNC bit of

the CMxCON0 register.

Once enabled, the comparator output is latched on the

falling edge of the Timer1 source clock. If a prescaler is

used with Timer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagram (Figure 17-2) and the Timer1 Block

Diagram (Figure 19-2) for more information.

17.6 Comparator Interrupt

An interrupt can be generated upon a change in the

output value of the comparator for each comparator, a

rising edge detector and a falling edge detector are

present.

When either edge detector is triggered and its associ-

ated enable bit is set (CxINTP and/or CxINTN bits of

the CMxCON1 register), the Corresponding Interrupt

Flag bit (CxIF bit of the PIR2 register) will be set.

To enable the interrupt, you must set the following bits:

• CxON, CxPOL and CxSP bits of the CMxCON0

register

• CxIE bit of the PIE2 register

• CxINTP bit of the CMxCON1 register (for a rising

edge detection)

• CxINTN bit of the CMxCON1 register (for a falling

edge detection)

• PEIE and GIE bits of the INTCON register

DS40001609E-page 148

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PIC16(L)F1508/9

17.8 Register Definitions: Comparator Control

REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0

CxON

R-0/0

R/W-0/0

CxOE

R/W-0/0

CxPOL

U-0

—

R/W-1/1

CxSP

R/W-0/0

CxHYS

R/W-0/0

CxSYNC

CxOUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

CxON: Comparator Enable bit

1= Comparator is enabled

0= Comparator is disabled and consumes no active power

CxOUT: Comparator Output bit

If CxPOL = 1 (inverted polarity):

1= CxVP < CxVN

0= CxVP > CxVN

If CxPOL = 0 (non-inverted polarity):

1= CxVP > CxVN

0= CxVP < CxVN

bit 5

bit 4

CxOE: Comparator Output Enable bit

1= CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually

drive the pin. Not affected by CxON.

0= CxOUT is internal only

CxPOL: Comparator Output Polarity Select bit

1= Comparator output is inverted

0= Comparator output is not inverted

bit 3

bit 2

Unimplemented: Read as ‘0’

CxSP: Comparator Speed/Power Select bit

1= Comparator mode in normal power, higher speed

0= Comparator mode in low-power, low-speed

bit 1

bit 0

CxHYS: Comparator Hysteresis Enable bit

1= Comparator hysteresis enabled

0= Comparator hysteresis disabled

CxSYNC: Comparator Output Synchronous Mode bit

1= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.

Output updated on the falling edge of Timer1 clock source.

0= Comparator output to Timer1 and I/O pin is asynchronous

 2011-2015 Microchip Technology Inc.

DS40001609E-page 149

PIC16(L)F1508/9

REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

R/W-0/0

CxINTP

R/W-0/0

CxINTN

R/W-0/0

U-0

—

R/W-0/0

CxPCH<1:0>

CxNCH<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit

0= No interrupt flag will be set on a positive going edge of the CxOUT bit

bit 6

CxINTN: Comparator Interrupt on Negative Going Edge Enable bits

1= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit

0= No interrupt flag will be set on a negative going edge of the CxOUT bit

bit 5-4

CxPCH<1:0>: Comparator Positive Input Channel Select bits

11= CxVP connects to VSS

10= CxVP connects to FVR Voltage Reference

01= CxVP connects to DAC Voltage Reference

00= CxVP connects to CxIN+ pin

bit 3

Unimplemented: Read as ‘0’

bit 2-0

CxNCH<2:0>: Comparator Negative Input Channel Select bits

111= Reserved

110= Reserved

101= Reserved

100= CxVN connects to FVR Voltage reference

011= CxVN connects to CxIN3- pin

010= CxVN connects to CxIN2- pin

001= CxVN connects to CxIN1- pin

000= CxVN connects to CxIN0- pin

REGISTER 17-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0/0

MC2OUT

MC1OUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-2

bit 1

Unimplemented: Read as ‘0’

MC2OUT: Mirror Copy of C2OUT bit

MC1OUT: Mirror Copy of C1OUT bit

bit 0

DS40001609E-page 150

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PIC16(L)F1508/9

TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

ANSELC

CM1CON0

CM2CON0

CM1CON1

CM2CON1

CMOUT

DAC1CON0

DAC1CON1

FVRCON

INTCON

PIE2

—

ANSC6

C1OUT

C2OUT

C1INTN

C2INTN

—

ANSA4

—

ANSC3

—

ANSA2

ANSC2

C1SP

ANSA1

ANSC1

ANSA0

ANSC0

110

118

149

150

144

125

75

ANSC7

C1ON

C2ON

C1NTP

C2NTP

—

C1OE

C2OE

C1POL

C2POL

C1HYS

C1SYNC

C2SYNC

—

C2SP

C2HYS

C1PCH<1:0>

C2PCH<1:0>

—

C1NCH<2:0>

C2NCH<2:0>

—

MC2OUT MC1OUT

DACEN

—

DACOE1

—

DACOE2

—

DACPSS

DACR<4:0>

—

FVREN

GIE

FVRRDY

PEIE

TSEN

TMR0IE

C1IE

TSRNG

INTE

—

CDAFVR<1:0>

ADFVR<1:0>

IOCIE

BCL1IE

BCL1IF

RA3

TMR0IF

NCO1IE

NCO1IF

RA2

INTF

—

IOCIF

—

OSFIE

OSFIF

C2IE

77

C2IF

C1IF

PIR2

—

80

PORTA

RA5

RA4

RA1

RA0

109

117

110

117

109

117

—

RC7

—

RC6

—

PORTC

LATA

RC5

RC4

RC3

RC2

RC1

RC0

LATA5

LATC5

TRISA5

TRISC5

LATA4

LATC4

TRISA4

TRISC4

—

LATA2

LATC2

TRISA2

TRISC2

LATA1

LATC1

TRISA1

TRISC1

LATA0

LATC0

TRISA0

TRISC0

LATC

LATC7

—

LATC6

—

LATC3

(1)

—

TRISA

TRISC

TRISC7

TRISC6

TRISC3

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

Note 1: Unimplemented, read as ‘1’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 151

PIC16(L)F1508/9

18.1.2

8-BIT COUNTER MODE

18.0 TIMER0 MODULE

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin.

The Timer0 module is an 8-bit timer/counter with the

following features:

8-Bit Counter mode using the T0CKI pin is selected by

setting the TMR0CS bit in the OPTION_REG register to

‘1’.

• 8-bit timer/counter register (TMR0)

• 3-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

The rising or falling transition of the incrementing edge

for either input source is determined by the TMR0SE bit

in the OPTION_REG register.

• TMR0 can be used to gate Timer1

Figure 18-1 is a block diagram of the Timer0 module.

18.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

18.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-bit Timer mode is

selected by clearing the TMR0CS bit of the

OPTION_REG register.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register

can be adjusted, in order to account for

the two instruction cycle delay when

TMR0 is written.

FIGURE 18-1:

TIMER0 BLOCK DIAGRAM

Rev. 10-000017A

8/5/2013

TMR0CS

Fosc/4

PSA

T0CKI⁽¹⁾

T0_overflow

0

1

T0CKI

TMR0

1

0

Sync Circuit

Q1

Prescaler

PS<2:0>

FOSC/2

write

to

TMR0

R

TMR0SE

set bit

TMR0IF

Note 1: The T0CKI prescale output frequency should not exceed FOSC/8.

DS40001609E-page 152

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

18.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A software programmable prescaler is available for

exclusive use with Timer0. The prescaler is enabled by

clearing the PSA bit of the OPTION_REG register.

Note:

The Watchdog Timer (WDT) uses its own

independent prescaler.

There are eight prescaler options for the Timer0 mod-

ule ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION_REG

register. In order to have a 1:1 prescaler value for the

Timer0 module, the prescaler must be disabled by set-

ting the PSA bit of the OPTION_REG register.

The prescaler is not readable or writable. All instructions

writing to the TMR0 register will clear the prescaler.

18.1.4

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The TMR0IF

interrupt flag bit of the INTCON register is set every

time the TMR0 register overflows, regardless of

whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The Timer0

interrupt enable is the TMR0IE bit of the INTCON

register.

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

18.1.5

8-BIT COUNTER MODE

SYNCHRONIZATION

When in 8-Bit Counter mode, the incrementing edge on

the T0CKI pin must be synchronized to the instruction

clock. Synchronization can be accomplished by

sampling the prescaler output on the Q2 and Q4 cycles

of the instruction clock. The high and low periods of the

external clocking source must meet the timing

requirements as shown in Section 29.0 “Electrical

Specifications”.

18.1.6

OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain

unchanged while the processor is in Sleep mode.

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DS40001609E-page 153

PIC16(L)F1508/9

18.2 Register Definitions: Option Register

REGISTER 18-1: OPTION_REG: OPTION REGISTER

R/W-1/1

WPUEN

R/W-1/1

INTEDG

R/W-1/1

PSA

R/W-1/1

PS<2:0>

R/W-1/1

bit 0

TMR0CS

TMR0SE

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

WPUEN: Weak Pull-Up Enable bit

1= All weak pull-ups are disabled (except MCLR, if it is enabled)

0= Weak pull-ups are enabled by individual WPUx latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

TMR0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

TMR0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is not assigned to the Timer0 module

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register

on Page

Name

ADCON2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TRIGSEL<3:0>

PEIE TMR0IE

—

INTF

—

136

75

INTCON

OPTION_REG

TMR0

GIE

INTE

IOCIE

PSA

TMR0IF

IOCIF

WPUEN

INTEDG TMR0CS TMR0SE

PS<2:0>

154

152*

109

Holding Register for the 8-bit Timer0 Count

TRISA5 TRISA4

(1)

TRISA

—

TRISA2

TRISA1

TRISA0

Legend:

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.

*

Page provides register information.

Note 1: Unimplemented, read as ‘1’.

DS40001609E-page 154

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PIC16(L)F1508/9

• Interrupt on overflow

19.0 TIMER1 MODULE WITH GATE

CONTROL

• Wake-up on overflow (external clock,

Asynchronous mode only)

The Timer1 module is a 16-bit timer/counter with the

following features:

• ADC Auto-Conversion Trigger(s)

• Selectable Gate Source Polarity

• Gate Toggle mode

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Gate Single-Pulse mode

• Gate Value Status

• Optionally synchronized comparator out

• Multiple Timer1 gate (count enable) sources

• Gate Event Interrupt

Figure 19-1 is a block diagram of the Timer1 module.

FIGURE 19-1:

TIMER1 BLOCK DIAGRAM

Rev. 10-000018A

8/5/2013

T1GSS<1:0>

T1GSPM

T1G

00

T0_overflow

C1OUT_sync

C2OUT_sync

01

10

11

1

0

D

Q

T1GVAL

0

1

Single Pulse

Acq. Control

Q1

D

Q

T1GGO/DONE

T1GPOL

TMR1ON

T1GTM

CK

R

Interrupt

det

set bit

TMR1GIF

TMR1GE

set flag bit

TMR1IF

TMR1ON

EN

D

TMR1⁽²⁾

TMR1H TMR1L

T1_overflow

Synchronized Clock Input

Q

0

1

T1CLK

T1SYNC

TMR1CS<1:0>

OUT

SOSCI/T1CKI

SOSCO

Secondary

Oscillator

LFINTOSC

Fosc

11

1

0

10

01

00

Prescaler

Synchronize⁽³⁾

1,2,4,8

Internal Clock

det

EN

2

Fosc/4

Internal Clock

Fosc/2

Internal

Clock

T1CKPS<1:0>

T1OSCEN

Sleep

Input

(1)

Secondary Clock

To Clock Switching

Module

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

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DS40001609E-page 155

PIC16(L)F1508/9

19.1 Timer1 Operation

19.2 Clock Source Selection

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

The TMR1CS<1:0> and T1OSCEN bits of the T1CON

register are used to select the clock source for Timer1.

Table 19-2 displays the clock source selections.

19.2.1

INTERNAL CLOCK SOURCE

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and incre-

ments on every selected edge of the external source.

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

When the FOSC internal clock source is selected, the

Timer1 register value will increment by four counts every

instruction clock cycle. Due to this condition, a 2 LSB

error in resolution will occur when reading the Timer1

value. To utilize the full resolution of Timer1, an

asynchronous input signal must be used to gate the

Timer1 clock input.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 19-1 displays the Timer1 enable

selections.

TABLE 19-1: TIMER1 ENABLE

SELECTIONS

The following asynchronous sources may be used:

• Asynchronous event on the T1G pin to Timer1

gate

Timer1

Operation

TMR1ON

TMR1GE

• C1 or C2 comparator input to Timer1 gate

0

1

0

1

0

1

Off

19.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

Always On

Count Enabled

When enabled to count, Timer1 is incremented on the

rising edge of the external clock input T1CKI. The

external clock source can be synchronized to the

microcontroller system clock or it can run

asynchronously.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON=1) when T1CKI is

low.

TABLE 19-2: CLOCK SOURCE SELECTIONS

TMR1CS<1:0>

T1OSCEN

Clock Source

11

x

1

0

x

LFINTOSC

Secondary Oscillator Circuit on SOSCI/SOSCO Pins

External Clocking on T1CKI Pin

System Clock (FOSC)

10

01

00

Instruction Clock (FOSC/4)

DS40001609E-page 156

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

19.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

19.6 Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 Gate Enable.

19.4 Timer1 (Secondary) Oscillator

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins SOSCI (input) and SOSCO

(amplifier output). This internal circuit is to be used in

conjunction with an external 32.768 kHz crystal. The

oscillator circuit is enabled by setting the T1OSCEN bit

of the T1CON register. The oscillator will continue to

run during Sleep.

Timer1 gate can also be driven by multiple selectable

sources.

19.6.1

TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

Note:

The oscillator requires some time to start-up

and stabilize before use. The SOSCR bit in

the OSCSTAT register monitors the

oscillator and indicates when the oscillator is

ready for use. When T1OSCEN is set, the

SOSCR bit is cleared. After 1024 cycles of

the oscillator are countered, the SOSCR bit

is set, indicating that the oscillator should be

stable and ready for use.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 19-3 for timing details.

TABLE 19-3: TIMER1 GATE ENABLE

SELECTIONS

19.5 Timer1 Operation in

Asynchronous Counter Mode

T1CLK T1GPOL

T1G

Timer1 Operation



0

1

0

1

0

1

Counts

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If the external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 19.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

Holds Count

Counts

19.6.2

TIMER1 GATE SOURCE

SELECTION

Timer1 gate source selections are shown in Table 19-4.

Source selection is controlled by the T1GSS<1:0> bits

of the T1GCON register. The polarity for each available

source is also selectable. Polarity selection is controlled

by the T1GPOL bit of the T1GCON register.

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

TABLE 19-4: TIMER1 GATE SOURCES

T1GSS

Timer1 Gate Source

Timer1 Gate pin (T1G)

00

01

19.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Overflow of Timer0 (T0_overflow)

(TMR0 increments from FFh to 00h)

(1)

10

11

Comparator 1 Output (C1OUT_sync)

Comparator 2 Output (C2OUT_sync)

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

Note 1: Optionally synchronized comparator output.

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19.6.2.1

T1G Pin Gate Operation

19.6.5

TIMER1 GATE VALUE STATUS

The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1

gate circuitry.

When Timer1 Gate Value Status is utilized, it is possible

to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON

register. The T1GVAL bit is valid even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

19.6.2.2

Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a low-to-

high pulse will automatically be generated and inter-

nally supplied to the Timer1 gate circuitry.

19.6.6

TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is pos-

sible to generate an interrupt upon the completion of a

gate event. When the falling edge of T1GVAL occurs,

the TMR1GIF flag bit in the PIR1 register will be set. If

the TMR1GIE bit in the PIE1 register is set, then an

interrupt will be recognized.

19.6.3

TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possi-

ble to measure the full-cycle length of a Timer1 gate

signal, as opposed to the duration of a single level

pulse.

The TMR1GIF flag bit operates even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

The Timer1 gate source is routed through a flip-flop that

changes state on every incrementing edge of the sig-

nal. See Figure 19-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

Note:

Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

19.6.4

TIMER1 GATE SINGLE-PULSE

MODE

When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the T1GGO/

DONE bit in the T1GCON register must be set. The

Timer1 will be fully enabled on the next incrementing

edge. On the next trailing edge of the pulse, the T1GGO/

DONE bit will automatically be cleared. No other gate

events will be allowed to increment Timer1 until the

T1GGO/DONE bit is once again set in software. See

Figure 19-5 for timing details.

If the Single Pulse Gate mode is disabled by clearing the

T1GSPM bit in the T1GCON register, the T1GGO/DONE

bit should also be cleared.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1 gate

source to be measured. See Figure 19-6 for timing

details.

DS40001609E-page 158

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19.8.1

ALTERNATE PIN LOCATIONS

19.7 Timer1 Interrupt

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

register, APFCON. To determine which pins can be

moved and what their default locations are upon a

Reset, see Section 11.1 “Alternate Pin Function” for

more information.

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

19.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1CS bits of the T1CON register must be

configured

• T1OSCEN bit of the T1CON register must be

configured

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine.

Timer1 oscillator will continue to operate in Sleep

regardless of the T1SYNC bit setting.

FIGURE 19-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

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PIC16(L)F1508/9

FIGURE 19-3:

TIMER1 GATE ENABLE MODE

TMR1GE

T1GPOL

t1g_in

T1CKI

T1GVAL

Timer1

N

N + 1

N + 2

N + 3

N + 4

FIGURE 19-4:

TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

t1g_in

T1CKI

T1GVAL

Timer1

N

N + 1 N + 2 N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

DS40001609E-page 160

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FIGURE 19-5:

TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

t1g_in

T1CKI

T1GVAL

Timer1

N

N + 1

N + 2

Cleared by

software

Set by hardware on

falling edge of T1GVAL

Cleared by software

TMR1GIF

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PIC16(L)F1508/9

FIGURE 19-6:

TMR1GE

T1GPOL

TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

T1GSPM

T1GTM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

t1g_in

T1CKI

T1GVAL

Timer1

N + 2 N + 3 N + 4

Set by hardware on

N

N + 1

Cleared by

software

Cleared by software

falling edge of T1GVAL

TMR1GIF

DS40001609E-page 162

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PIC16(L)F1508/9

19.9 Register Definitions: Timer1 Control

REGISTER 19-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u

T1SYNC

U-0

—

R/W-0/u

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

TMR1CS<1:0>: Timer1 Clock Source Select bits

11=Timer1 clock source is LFINTOSC

10=Timer1 clock source is pin or oscillator:

If T1OSCEN = 0:

External clock from T1CKI pin (on the rising edge)

If T1OSCEN = 1:

Crystal oscillator on SOSCI/SOSCO pins

01=Timer1 clock source is system clock (FOSC)

00=Timer1 clock source is instruction clock (FOSC/4)

bit 5-4

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T1OSCEN: LP Oscillator Enable Control bit

1= Secondary oscillator circuit enabled for Timer1

0= Secondary oscillator circuit disabled for Timer1

T1SYNC: Timer1 Synchronization Control bit

1= Do not synchronize asynchronous clock input

0= Synchronize asynchronous clock input with system clock (FOSC)

bit 1

bit 0

Unimplemented: Read as ‘0’

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1 and clears Timer1 gate flip-flop

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REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u

T1GPOL

R/W-0/u

T1GTM

R/W-0/u

R/W/HC-0/u

R-x/x

R/W-0/u

TMR1GE

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 counting is controlled by the Timer1 gate function

0= Timer1 counts regardless of Timer1 gate function

bit 6

bit 5

T1GPOL: Timer1 Gate Polarity bit

1= Timer1 gate is active-high (Timer1 counts when gate is high)

0= Timer1 gate is active-low (Timer1 counts when gate is low)

T1GTM: Timer1 Gate Toggle Mode bit

1= Timer1 Gate Toggle mode is enabled

0= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4

T1GSPM: Timer1 Gate Single-Pulse Mode bit

1= Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate

0= Timer1 gate Single-Pulse mode is disabled

bit 3

T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1= Timer1 gate single-pulse acquisition is ready, waiting for an edge

0= Timer1 gate single-pulse acquisition has completed or has not been started

bit 2

T1GVAL: Timer1 Gate Value Status bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

bit 1-0

T1GSS<1:0>: Timer1 Gate Source Select bits

11= Comparator 2 optionally synchronized output (C2OUT_sync)

10= Comparator 1 optionally synchronized output (C1OUT_sync)

01= Timer0 overflow output (T0_overflow)

00= Timer1 gate pin (T1G)

DS40001609E-page 164

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TABLE 19-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

APFCON

—

ANSA4

SSSEL

—

ANSA2

—

ANSA1

ANSA0

110

107

75

T1GSEL

CLC1SEL

NCO1SEL

INTCON

OSCSTAT

PIE1

GIE

PEIE

—

TMR0IE

OSTS

RCIE

INTE

HFIOFR

TXIE

IOCIE

—

TMR0IF

INTF

IOCIF

SOSCR

TMR1GIE

TMR1GIF

—

LFIOFR

TMR2IE

TMR2IF

HFIOFS

TMR1IE

TMR1IF

60

ADIE

ADIF

SSP1IE

SSP1IF

76

PIR1

RCIF

TXIF

79

TMR1H

TMR1L

TRISA

Holding Register for the Most Significant Byte of the 16-bit TMR1 Count

159*

109

163

164

Holding Register for the Least Significant Byte of the 16-bit TMR1 Count

(1)

—

TRISA5

TRISA4

—

TRISA2

T1SYNC

T1GVAL

TRISA1

—

TRISA0

T1CON

T1GCON

TMR1CS<1:0>

TMR1GE T1GPOL

T1CKPS<1:0>

T1OSCEN

TMR1ON

T1GTM

T1GSPM

T1GGO/

DONE

T1GSS<1:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.

*

Page provides register information.

Note 1: Unimplemented, read as ‘1’.

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PIC16(L)F1508/9

20.0 TIMER2 MODULE

The Timer2 module incorporates the following features:

• 8-bit Timer and Period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16,

and 1:64)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match with PR2

See Figure 20-1 for a block diagram of Timer2.

FIGURE 20-1:

TIMER2 BLOCK DIAGRAM

Rev. 10-000019A

7/30/2013

T2_match

To Peripherals

Prescaler

TMR2

R

Fosc/4

1:1, 1:4, 1:16, 1:64

2

Postscaler

set bit

TMR2IF

Comparator

PR2

T2CKPS<1:0>

1:1 to 1:16

4

T2OUTPS<3:0>

FIGURE 20-2:

TIMER2 TIMING DIAGRAM

Rev. 10-000020A

7/30/2013

FOSC/4

Prescale

PR2

1:4

0x03

0x00

0x01

0x02

0x00

0x01

0x02

TMR2

Pulse Width⁽¹⁾

T2_match

Note 1: The Pulse Width of T2_match is equal to the scaled input of TMR2.

DS40001609E-page 166

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20.1 Timer2 Operation

20.3 Timer2 Output

The clock input to the Timer2 module is the system

instruction clock (FOSC/4).

The output of TMR2 is T2_match. T2_match is available

to the following peripherals:

TMR2 increments from 00h on each clock edge.

• Configurable Logic Cell (CLC)

• Master Synchronous Serial Port (MSSP)

• Numerically Controlled Oscillator (NCO)

• Pulse Width Modulator (PWM)

A 4-bit counter/prescaler on the clock input allows direct

input, divide-by-4 and divide-by-16 prescale options.

These options are selected by the prescaler control bits,

T2CKPS<1:0> of the T2CON register. The value of

TMR2 is compared to that of the Period register, PR2, on

each clock cycle. When the two values match, the

comparator generates a match signal as the timer

output. This signal also resets the value of TMR2 to 00h

on the next cycle and drives the output counter/

postscaler (see Section 20.2 “Timer2 Interrupt”).

The T2_match signal is synchronous with the system

clock. Figure 20-3 shows two examples of the timing of

the T2_match signal relative to FOSC and prescale

value, T2CKPS<1:0>. The upper diagram illustrates 1:1

prescale timing and the lower diagram, 1:X prescale

timing.

The TMR2 and PR2 registers are both directly readable

and writable. The TMR2 register is cleared on any

device Reset, whereas the PR2 register initializes to

FFh. Both the prescaler and postscaler counters are

cleared on the following events:

FIGURE 20-3:

T2_MATCH TIMING

DIAGRAM

Rev. 10-000021A

7/30/2013

Q1

Q2

Q3

Q4

Q1

• a write to the TMR2 register

• a write to the T2CON register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• MCLR Reset

FOSC

TCY1

FOSC/4

TMR2 = PR2

match

TMR2 = 0

T2_match

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

• RESETInstruction

PRESCALE = 1:1

(T2CKPS<1:0> = 00)

...

TCY1

TCY2

TCYX

Note:

TMR2 is not cleared when T2CON is

written.

...

FOSC/4

20.2 Timer2 Interrupt

T2_match

TMR2 = PR2

match

TMR2 = 0

Timer2 can also generate an optional device interrupt.

The Timer2 output signal (T2_match) provides the input

for the 4-bit counter/postscaler. This counter generates

the TMR2 match interrupt flag which is latched in

TMR2IF of the PIR1 register. The interrupt is enabled by

setting the TMR2 Match Interrupt Enable bit, TMR2IE of

the PIE1 register.

PRESCALE = 1:X

(T2CKPS<1:0> = 01,10,11)

20.4 Timer2 Operation During Sleep

Timer2 cannot be operated while the processor is in

Sleep mode. The contents of the TMR2 and PR2

registers will remain unchanged while the processor is

in Sleep mode.

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, T2OUTPS<3:0>, of the T2CON register.

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20.5 Register Definitions: Timer2 Control

REGISTER 20-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

R/W-0/0

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-3

T2OUTPS<3:0>: Timer2 Output Postscaler Select bits

0000= 1:1 Postscaler

0001= 1:2 Postscaler

0010= 1:3 Postscaler

0011= 1:4 Postscaler

0100= 1:5 Postscaler

0101= 1:6 Postscaler

0110= 1:7 Postscaler

0111= 1:8 Postscaler

1000= 1:9 Postscaler

1001= 1:10 Postscaler

1010= 1:11 Postscaler

1011= 1:12 Postscaler

1100= 1:13 Postscaler

1101= 1:14 Postscaler

1110= 1:15 Postscaler

1111= 1:16 Postscaler

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

10= Prescaler is 16

11= Prescaler is 64

TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

IOCIE

SSP1IE

SSP1IF

TMR0IF

INTF

IOCIF

75

76

TMR1GIE

TMR1GIF

—

TMR2IE

TMR2IF

TMR1IE

TMR1IF

RCIF

PIR1

76

PR2

Timer2 Module Period Register

—

166*

168

166*

T2CON

TMR2

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

Holding Register for the 8-bit TMR2 Count

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.

*

Page provides register information.

DS40001609E-page 168

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The SPI interface supports the following modes and

features:

21.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

• Master mode

• Slave mode

• Clock Parity

21.1 MSSP Module Overview

• Slave Select Synchronization (Slave mode only)

• Daisy-chain connection of slave devices

The Master Synchronous Serial Port (MSSPx) module

is a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSPx module

can operate in one of two modes:

Figure 21-1 is a block diagram of the SPI interface

module.

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

FIGURE 21-1:

MSSP BLOCK DIAGRAM (SPI MODE)

Rev. 10-000076A

12/16/2013

Data bus

Read

Write

8

SSPxBUF

SSPxSR

SDI

SDO_out

Bit 0

Shift clock

SDO

2

(CKP, CKE)

clock select

SSx

SSPM<3:0>

4

Control

Enable

Edge

enable

(T2_match)

2

SCK_out

Edge

enable

Prescaler

4, 16, 64

SCK

TOSC

Baud Rate

Generator

(SSPxADD)

TRIS bit

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The I²C interface supports the following modes and

features:

Note 1: In devices with more than one MSSP

module, it is very important to pay close

attention to SSPxCONx register names.

SSPxCON1 and SSPxCON2 registers

control different operational aspects of

the same module, while SSPxCON1 and

SSP2CON1 control the same features for

two different modules.

• Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited Multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

2: Throughout this section, generic refer-

ences to an MSSPx module in any of its

operating modes may be interpreted as

being equally applicable to MSSPx or

MSSP2. Register names, module I/O sig-

nals, and bit names may use the generic

designator ‘x’ to indicate the use of a

numeral to distinguish a particular mod-

ule when required.

• Clock stretching

• Bus collision detection

• General call address matching

• Address masking

• Address Hold and Data Hold modes

• Selectable SDAx hold times

Figure 21-2 is a block diagram of the I²C interface mod-

ule in Master mode. Figure 21-3 is a diagram of the I²C

interface module in Slave mode.

FIGURE 21-2:

MSSPX BLOCK DIAGRAM (I²C™ MASTER MODE)

Rev. 10-000077A

7/30/2013

Internal data

bus

[SSPM <3:0>]

Write

Read

8

4

Baud Rate

Generator

(SSPxADD)

SSPxBUF

SDAx

SDAx in

Shift clock

SSPxSR

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate

(SSPxCON2)

SCLx

Start bit detected

Stop bit detected

SCLx in

Bus collision

Set/Reset: S, P, SSPxSTAT,

Write collsion detect

Clock arbitration

WCOL, SSPOV

Reset SEN, PEN (SSPxCON2)

Set SSPxIF, BCLxIF

State counter for end

of XMIT/RCV

Address match detect

DS40001609E-page 170

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PIC16(L)F1508/9

FIGURE 21-3:

MSSP BLOCK DIAGRAM (I²C™ SLAVE MODE)

Rev. 10-000078A

7/30/2013

Internal data bus

Read

Write

8

SSPxBUF

8

SCLx

SDAx

Shift clock

SSPxSR

MSb LSb

8

SSPxMSK

8

Match detect

8

Addr Match

SSPxADD

Start and Stop

bit Detect

Set, Reset S, P

bits (SSPxSTAT)

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During each SPI clock cycle, a full-duplex data

transmission occurs. This means that while the master

device is sending out the MSb from its shift register (on

its SDOx pin) and the slave device is reading this bit

and saving it as the LSb of its shift register, that the

slave device is also sending out the MSb from its shift

register (on its SDOx pin) and the master device is

reading this bit and saving it as the LSb of its shift

register.

21.2 SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is a

synchronous serial data communication bus that

operates in Full-Duplex mode. Devices communicate

in a master/slave environment where the master device

initiates the communication.

A slave device is

controlled through a Chip Select known as Slave

Select.

The SPI bus specifies four signal connections:

After eight bits have been shifted out, the master and

slave have exchanged register values.

• Serial Clock (SCKx)

• Serial Data Out (SDOx)

• Serial Data In (SDIx)

• Slave Select (SSx)

If there is more data to exchange, the shift registers are

loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data),

depends on the application software. This leads to

three scenarios for data transmission:

Figure 21-1 shows the block diagram of the MSSP

module when operating in SPI mode.

• Master sends useful data and slave sends dummy

data.

The SPI bus operates with a single master device and

one or more slave devices. When multiple slave

devices are used, an independent Slave Select con-

nection is required from the master device to each

slave device.

• Master sends useful data and slave sends useful

data.

• Master sends dummy data and slave sends useful

data.

Figure 21-4 shows a typical connection between a

master device and multiple slave devices.

Transmissions may involve any number of clock

cycles. When there is no more data to be transmitted,

the master stops sending the clock signal and it dese-

lects the slave.

The master selects only one slave at a time. Most slave

devices have tri-state outputs so their output signal

appears disconnected from the bus when they are not

selected.

Every slave device connected to the bus that has not

been selected through its slave select line must disre-

gard the clock and transmission signals and must not

transmit out any data of its own.

Transmissions involve two shift registers, eight bits in

size, one in the master and one in the slave. With either

the master or the slave device, data is always shifted

out one bit at a time, with the Most Significant bit (MSb)

shifted out first. At the same time, a new Least

Significant bit (LSb) is shifted into the same register.

Figure 21-5 shows a typical connection between two

processors configured as master and slave devices.

Data is shifted out of both shift registers on the pro-

grammed clock edge and latched on the opposite edge

of the clock.

The master device transmits information out on its

SDOx output pin which is connected to, and received

by, the slave’s SDIx input pin. The slave device trans-

mits information out on its SDOx output pin, which is

connected to, and received by, the master’s SDIx input

pin.

To begin communication, the master device first sends

out the clock signal. Both the master and the slave

devices should be configured for the same clock polar-

ity.

The master device starts a transmission by sending out

the MSb from its shift register. The slave device reads

this bit from that same line and saves it into the LSb

position of its shift register.

DS40001609E-page 172

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 21-4:

SPI MASTER AND MULTIPLE SLAVE CONNECTION

Rev. 10-000079A

8/1/2013

SCKx

SDOx

SDIx

SCKx

SDIx

SPI Master

SPI Slave

#1

SDOx

SSx

General I/O

SCKx

SDIx

SDOx

SSx

SPI Slave

#2

SCKx

SDIx

SDOx

SSx

SPI Slave

#3

21.2.1 SPI MODE REGISTERS

During transmission, the SSPxBUF is not buffered. A

write to SSPxBUF will write to both SSPxBUF and

SSPxSR.

The MSSP module has five registers for SPI mode

operation. These are:

• MSSP STATUS register (SSPxSTAT)

• MSSP Control Register 1 (SSPxCON1)

• MSSP Control Register 3 (SSPxCON3)

• MSSP Data Buffer register (SSPxBUF)

• MSSP Address register (SSPxADD)

• MSSP Shift register (SSPxSR)

(Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and

STATUS registers in SPI mode operation. The

SSPxCON1 register is readable and writable. The

lower six bits of the SSPxSTAT are read-only. The

upper two bits of the SSPxSTAT are read/write.

In SPI master mode, SSPxADD can be loaded with a

value used in the Baud Rate Generator. More informa-

tion on the Baud Rate Generator is available in

Section21.7 “Baud Rate Generator”.

SSPxSR is the shift register used for shifting data in

and out. SSPxBUF provides indirect access to the

SSPxSR register. SSPxBUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSPxSR and SSPxBUF

together create a buffered receiver. When SSPxSR

receives a complete byte, it is transferred to SSPxBUF

and the SSPxIF interrupt is set.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 173

PIC16(L)F1508/9

21.2.2 SPI MODE OPERATION

When the application software is expecting to receive

valid data, the SSPxBUF should be read before the

next byte of data to transfer is written to the SSPxBUF.

The Buffer Full bit, BF of the SSPxSTAT register, indi-

cates when SSPxBUF has been loaded with the

received data (transmission is complete). When the

SSPxBUF is read, the BF bit is cleared. This data may

be irrelevant if the SPI is only a transmitter. Generally,

the MSSP interrupt is used to determine when the

transmission/reception has completed. If the interrupt

method is not going to be used, then software polling

can be done to ensure that a write collision does not

occur.

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCKx is the clock output)

• Slave mode (SCKx is the clock input)

• Clock Polarity (Idle state of SCKx)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCKx)

The SSPxSR is not directly readable or writable and

can only be accessed by addressing the SSPxBUF

register. Additionally, the SSPxSTAT register indicates

the various Status conditions.

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port, SSP Enable bit, SSPEN of the

SSPxCON1 register, must be set. To reset or reconfig-

ure SPI mode, clear the SSPEN bit, re-initialize the

SSPxCONx registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed as follows:

• SDIx must have corresponding TRIS bit set

• SDOx must have corresponding TRIS bit cleared

• SCKx (Master mode) must have corresponding

TRIS bit cleared

• SCKx (Slave mode) must have corresponding

TRIS bit set

• SSx must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

The MSSP consists of a transmit/receive shift register

(SSPxSR) and a buffer register (SSPxBUF). The

SSPxSR shifts the data in and out of the device, MSb

first. The SSPxBUF holds the data that was written to

the SSPxSR until the received data is ready. Once the

eight bits of data have been received, that byte is

moved to the SSPxBUF register. Then, the Buffer Full

Detect bit, BF of the SSPxSTAT register, and the

interrupt flag bit, SSPxIF, are set. This double-buffering

of the received data (SSPxBUF) allows the next byte to

start reception before reading the data that was just

received. Any write to the SSPxBUF register during

transmission/reception of data will be ignored and the

write collision detect bit, WCOL of the SSPxCON1

register, will be set. User software must clear the

WCOL bit to allow the following write(s) to the

SSPxBUF register to complete successfully.

DS40001609E-page 174

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 21-5:

SPI MASTER/SLAVE CONNECTION

Rev. 10-000080A

7/30/2013

SPI Master SSPM<3:0> = 00xx

= 1010

SPI Slave SSPM<3:0> = 010x

SDOx

SDIx

Serial Input Buffer

(SSPxBUF)

Serial Input Buffer

(SSPxBUF)

SDIx

SDOx

Shift Register

(SSPxSR)

Shift Register

(SSPxSR)

MSb

LSb

MSb

LSb

Serial clock

SCKx

SSx

Slave Select

(optional)

General I/O

Processor 1

Processor 2

 2011-2015 Microchip Technology Inc.

DS40001609E-page 175

PIC16(L)F1508/9

The clock polarity is selected by appropriately

programming the CKP bit of the SSPxCON1 register

and the CKE bit of the SSPxSTAT register. This then,

would give waveforms for SPI communication as

shown in Figure 21-6, Figure 21-8, Figure 21-9 and

Figure 21-10, where the MSb is transmitted first. In

Master mode, the SPI clock rate (bit rate) is user

programmable to be one of the following:

21.2.3

SPI MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCKx line. The master

determines when the slave (Processor 2, Figure 21-5)

is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPxBUF register is written to. If the SPI

is only going to receive, the SDOx output could be dis-

abled (programmed as an input). The SSPxSR register

will continue to shift in the signal present on the SDIx

pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPxBUF register as

if a normal received byte (interrupts and Status bits

appropriately set).

• FOSC/4 (or TCY)

• FOSC/16 (or 4 * TCY)

• FOSC/64 (or 16 * TCY)

• Timer2 output/2

• Fosc/(4 * (SSPxADD + 1))

Figure 21-6 shows the waveforms for Master mode.

When the CKE bit is set, the SDOx data is valid before

there is a clock edge on SCKx. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPxBUF is loaded with the received

data is shown.

FIGURE 21-6:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPxBUF

SCKx

(CKP = 0

CKE = 0)

SCKx

(CKP = 1

CKE = 0)

4 Clock

Modes

SCKx

(CKP = 0

CKE = 1)

SCKx

(CKP = 1

CKE = 1)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDOx

(CKE = 0)

bit 7

bit 3

SDOx

(CKE = 1)

SDIx

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDIx

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPxIF

SSPxSR to

SSPxBUF

DS40001609E-page 176

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

21.2.4

SPI SLAVE MODE

21.2.5

SLAVE SELECT

SYNCHRONIZATION

In Slave mode, the data is transmitted and received as

external clock pulses appear on SCKx. When the last

bit is latched, the SSPxIF interrupt flag bit is set.

The Slave Select can also be used to synchronize com-

munication. The Slave Select line is held high until the

master device is ready to communicate. When the

Slave Select line is pulled low, the slave knows that a

new transmission is starting.

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCKx pin. The Idle state is

determined by the CKP bit of the SSPxCON1 register.

If the slave fails to receive the communication properly,

it will be reset at the end of the transmission, when the

Slave Select line returns to a high state. The slave is

then ready to receive a new transmission when the

Slave Select line is pulled low again. If the Slave Select

line is not used, there is a risk that the slave will even-

tually become out of sync with the master. If the slave

misses a bit, it will always be one bit off in future trans-

missions. Use of the Slave Select line allows the slave

and master to align themselves at the beginning of

each transmission.

While in Slave mode, the external clock is supplied by

the external clock source on the SCKx pin. This exter-

nal clock must meet the minimum high and low times

as specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. The shift register is clocked from the SCKx pin

input and when a byte is received, the device will gen-

erate an interrupt. If enabled, the device will wake-up

from Sleep.

21.2.4.1 Daisy-Chain Configuration

The SSx pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SSx pin control

enabled (SSPxCON1<3:0> = 0100).

The SPI bus can sometimes be connected in a

daisy-chain configuration. The first slave output is con-

nected to the second slave input, the second slave

output is connected to the third slave input, and so on.

The final slave output is connected to the master input.

Each slave sends out, during a second group of clock

pulses, an exact copy of what was received during the

first group of clock pulses. The whole chain acts as

one large communication shift register. The

daisy-chain feature only requires a single Slave Select

line from the master device.

When the SSx pin is low, transmission and reception

are enabled and the SDOx pin is driven.

When the SSx pin goes high, the SDOx pin is no longer

driven, even if in the middle of a transmitted byte and

becomes a floating output. External pull-up/pull-down

resistors may be desirable depending on the applica-

tion.

Note 1: When the SPI is in Slave mode with SSx

pin control enabled (SSPxCON1<3:0> =

0100), the SPI module will reset if the SSx

pin is set to VDD.

Figure 21-7 shows the block diagram of a typical

daisy-chain connection when operating in SPI mode.

In a daisy-chain configuration, only the most recent

byte on the bus is required by the slave. Setting the

BOEN bit of the SSPxCON3 register will enable writes

to the SSPxBUF register, even if the previous byte has

not been read. This allows the software to ignore data

that may not apply to it.

2: When the SPI is used in Slave mode with

CKE set; the user must enable SSx pin

control.

3: While operated in SPI Slave mode the

SMP bit of the SSPxSTAT register must

remain clear.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SSx pin to

a high level or clearing the SSPEN bit.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 177

PIC16(L)F1508/9

FIGURE 21-7:

SPI DAISY-CHAIN CONNECTION

Rev. 10-000082A

7/30/2013

SCK

SPI Master

SPI Slave

#1

SDOx

SDIx

SDOx

SSx

General I/O

SCK

SDIx

SDOx

SSx

SPI Slave

#2

SCK

SDIx

SPI Slave

#3

SDOx

SSx

FIGURE 21-8:

SLAVE SELECT SYNCHRONOUS WAVEFORM

SSx

SCKx

(CKP = 0

CKE = 0)

SCKx

(CKP = 1

CKE = 0)

Write to

SSPxBUF

Shift register SSPxSR

and bit count are reset

SSPxBUF to

SSPxSR

bit 6

bit 7

bit 0

SDOx

SDIx

bit 7

bit 0

bit 7

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

DS40001609E-page 178

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 21-9:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SSx

Optional

SCKx

(CKP = 0

CKE = 0)

SCKx

(CKP = 1

CKE = 0)

Write to

SSPxBUF

Valid

bit 6

bit 2

bit 5

bit 4

bit 3

bit 1

bit 0

SDOx

bit 7

SDIx

bit 0

bit 7

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

Write Collision

detection active

FIGURE 21-10:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SSx

Not Optional

SCKx

(CKP = 0

CKE = 1)

SCKx

(CKP = 1

CKE = 1)

Write to

SSPxBUF

Valid

bit 6

bit 3

bit 2

bit 5

bit 4

bit 1

bit 0

SDOx

bit 7

SDIx

bit 0

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

Write Collision

detection active

 2011-2015 Microchip Technology Inc.

DS40001609E-page 179

PIC16(L)F1508/9

21.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, module clocks may be operating

at a different speed than when in Full-Power mode; in

the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the MSSP

clock is much faster than the system clock.

In Slave mode, when MSSP interrupts are enabled,

after the master completes sending data, an MSSP

interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSP inter-

rupts should be disabled.

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmis-

sion/reception will remain in that state until the device

wakes. After the device returns to Run mode, the mod-

ule will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

register operates asynchronously to the device. This

allows the device to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

register. When all eight bits have been received, the

MSSP interrupt flag bit will be set and if enabled, will

wake the device.

TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

INTCON

PIE1

—

ANSA4

INTE

TXIE

—

ANSA2

TMR0IF

—

ANSA1

INTF

ANSA0

IOCIF

110

75

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

IOCIE

SSP1IE

SSP1IF

TMR1GIE

TMR1GIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

76

PIR1

RCIF

TXIF

—

79

SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register

173*

219

221

218

109

117

SSP1CON1

WCOL

SSPOV

PCIE

CKE

SSPEN

SCIE

CKP

BOEN

P

SSPM<3:0>

SSP1CON3 ACKTIM

SDAHT

S

SBCDE

R/W

AHEN

UA

DHEN

BF

SSP1STAT

TRISA

SMP

—

D/A

(1)

—

TRISA5

TRISC5

TRISA4

TRISC4

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

TRISC

TRISC7

TRISC6

TRISC3

Legend:

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

*

Page provides register information.

Note 1: Unimplemented, read as ‘1’.

DS40001609E-page 180

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

I²C MASTER/

21.3 I²C MODE OVERVIEW

FIGURE 21-11:

SLAVE CONNECTION

The Inter-Integrated Circuit Bus (I²C) is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment where the master

devices initiate the communication. A slave device is

controlled through addressing.

Rev. 10-000085A

7/30/2013

VDD

The I²C bus specifies two signal connections:

SCLx

SDAx

SCLx

SDAx

• Serial Clock (SCLx)

• Serial Data (SDAx)

VDD

Slave

Master

Figure 21-2 and Figure 21-3 show the block diagrams

of the MSSP module when operating in I²C mode.

Both the SCLx and SDAx connections are bidirectional

open-drain lines, each requiring pull-up resistors for the

supply voltage. Pulling the line to ground is considered

a logical zero and letting the line float is considered a

logical one.

The Acknowledge bit (ACK) is an active-low signal,

which holds the SDAx line low to indicate to the trans-

mitter that the slave device has received the transmit-

ted data and is ready to receive more.

Figure 21-11 shows a typical connection between two

processors configured as master and slave devices.

The I²C bus can operate with one or more master

devices and one or more slave devices.

The transition of a data bit is always performed while

the SCLx line is held low. Transitions that occur while

the SCLx line is held high are used to indicate Start and

Stop bits.

There are four potential modes of operation for a given

device:

If the master intends to write to the slave, then it repeat-

edly sends out a byte of data, with the slave responding

after each byte with an ACK bit. In this example, the

master device is in Master Transmit mode and the

slave is in Slave Receive mode.

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

(master is receiving data from a slave)

• Slave Transmit mode

(slave is transmitting data to a master)

If the master intends to read from the slave, then it

repeatedly receives a byte of data from the slave, and

responds after each byte with an ACK bit. In this exam-

ple, the master device is in Master Receive mode and

the slave is Slave Transmit mode.

• Slave Receive mode

(slave is receiving data from the master)

To begin communication, a master device starts out in

Master Transmit mode. The master device sends out a

Start bit followed by the address byte of the slave it

intends to communicate with. This is followed by a sin-

gle Read/Write bit, which determines whether the mas-

ter intends to transmit to or receive data from the slave

device.

On the last byte of data communicated, the master

device may end the transmission by sending a Stop bit.

If the master device is in Receive mode, it sends the

Stop bit in place of the last ACK bit. A Stop bit is indi-

cated by a low-to-high transition of the SDAx line while

the SCLx line is held high.

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwise known as an ACK.

The master then continues in either Transmit mode or

Receive mode and the slave continues in the comple-

ment, either in Receive mode or Transmit mode,

respectively.

In some cases, the master may want to maintain con-

trol of the bus and re-initiate another transmission. If

so, the master device may send another Start bit in

place of the Stop bit or last ACK bit when it is in receive

mode.

The I²C bus specifies three message protocols;

A Start bit is indicated by a high-to-low transition of the

SDAx line while the SCLx line is held high. Address and

data bytes are sent out, Most Significant bit (MSb) first.

The Read/Write bit is sent out as a logical one when the

master intends to read data from the slave, and is sent

out as a logical zero when it intends to write data to the

slave.

• Single message where a master writes data to a

slave.

• Single message where a master reads data from

a slave.

• Combined message where a master initiates a

minimum of two writes, or two reads, or a

combination of writes and reads, to one or more

slaves.

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DS40001609E-page 181

PIC16(L)F1508/9

When one device is transmitting a logical one, or letting

the line float, and a second device is transmitting a log-

ical zero, or holding the line low, the first device can

detect that the line is not a logical one. This detection,

when used on the SCLx line, is called clock stretching.

Clock stretching gives slave devices a mechanism to

control the flow of data. When this detection is used on

the SDAx line, it is called arbitration. Arbitration

ensures that there is only one master device communi-

cating at any single time.

21.3.2

ARBITRATION

Each master device must monitor the bus for Start and

Stop bits. If the device detects that the bus is busy, it

cannot begin a new message until the bus returns to an

Idle state.

However, two master devices may try to initiate a trans-

mission on or about the same time. When this occurs,

the process of arbitration begins. Each transmitter

checks the level of the SDAx data line and compares it

to the level that it expects to find. The first transmitter to

observe that the two levels do not match, loses arbitra-

tion, and must stop transmitting on the SDAx line.

21.3.1

CLOCK STRETCHING

When a slave device has not completed processing

data, it can delay the transfer of more data through the

process of clock stretching. An addressed slave device

may hold the SCLx clock line low after receiving or

sending a bit, indicating that it is not yet ready to con-

tinue. The master that is communicating with the slave

will attempt to raise the SCLx line in order to transfer

the next bit, but will detect that the clock line has not yet

been released. Because the SCLx connection is

open-drain, the slave has the ability to hold that line low

until it is ready to continue communicating.

For example, if one transmitter holds the SDAx line to

a logical one (lets it float) and a second transmitter

holds it to a logical zero (pulls it low), the result is that

the SDAx line will be low. The first transmitter then

observes that the level of the line is different than

expected and concludes that another transmitter is

communicating.

The first transmitter to notice this difference is the one

that loses arbitration and must stop driving the SDAx

line. If this transmitter is also a master device, it also

must stop driving the SCLx line. It then can monitor the

lines for a Stop condition before trying to reissue its

transmission. In the meantime, the other device that

has not noticed any difference between the expected

and actual levels on the SDAx line continues with its

original transmission. It can do so without any compli-

cations, because so far, the transmission appears

exactly as expected with no other transmitter disturbing

the message.

Clock stretching allows receivers that cannot keep up

with a transmitter to control the flow of incoming data.

Slave Transmit mode can also be arbitrated, when a

master addresses multiple slaves, but this is less com-

mon.

If two master devices are sending a message to two dif-

ferent slave devices at the address stage, the master

sending the lower slave address always wins arbitra-

tion. When two master devices send messages to the

same slave address, and addresses can sometimes

refer to multiple slaves, the arbitration process must

continue into the data stage.

Arbitration usually occurs very rarely, but it is a neces-

sary process for proper multi-master support.

DS40001609E-page 182

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PIC16(L)F1508/9

TABLE 21-2: I²C BUS TERMS

21.4 I²C MODE OPERATION

TERM

Description

All MSSP I²C communication is byte oriented and

shifted out MSb first. Six SFR registers and two

interrupt flags interface the module with the PIC^®

microcontroller and user software. Two pins, SDAx

and SCLx, are exercised by the module to communi-

cate with other external I²C devices.

Transmitter

The device which shifts data out

onto the bus.

Receiver

Master

The device which shifts data in

from the bus.

The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

21.4.1

BYTE FORMAT

All communication in I²C is done in 9-bit segments. A

byte is sent from a master to a slave or vice-versa,

followed by an Acknowledge bit sent back. After the

eighth falling edge of the SCLx line, the device output-

ting data on the SDAx changes that pin to an input and

reads in an acknowledge value on the next clock

pulse.

Slave

The device addressed by the

master.

Multi-master

Arbitration

A bus with more than one device

that can initiate data transfers.

Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

The clock signal, SCLx, is provided by the master.

Data is valid to change while the SCLx signal is low,

and sampled on the rising edge of the clock. Changes

on the SDAx line while the SCLx line is high define

special conditions on the bus, explained below.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle

No master is controlling the bus,

and both SDAx and SCLx lines are

high.

21.4.2

DEFINITION OF I²C TERMINOLOGY

There is language and terminology in the description

of I²C communication that have definitions specific to

I²C. That word usage is defined below and may be

used in the rest of this document without explanation.

This table was adapted from the Philips I²C^TM

specification.

Active

Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSPxADD.

21.4.3

SDAX AND SCLX PINS

Selection of any I²C mode with the SSPEN bit set,

forces the SCLx and SDAx pins to be open-drain.

These pins should be set by the user to inputs by set-

ting the appropriate TRIS bits.

Write Request

Read Request

Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Note: Data is tied to output zero when an I²C

mode is enabled.

21.4.4

SDAX HOLD TIME

The hold time of the SDAx pin is selected by the

SDAHT bit of the SSPxCON3 register. Hold time is the

time SDAx is held valid after the falling edge of SCLx.

Setting the SDAHT bit selects a longer 300 ns mini-

mum hold time and may help on buses with large

capacitance.

Clock Stretching When a device on the bus hold

SCLx low to stall communication.

Bus Collision

Any time the SDAx line is sampled

low by the module while it is out-

putting and expected high state.

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21.4.5 START CONDITION

21.4.7 RESTART CONDITION

The I²C specification defines a Start condition as a

transition of SDAx from a high to a low state while

SCLx line is high. A Start condition is always gener-

ated by the master and signifies the transition of the

bus from an Idle to an Active state. Figure 21-12

shows wave forms for Start and Stop conditions.

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave. Figure 21-13 shows the wave form for a

Restart condition.

A bus collision can occur on a Start condition if the

module samples the SDAx line low before asserting it

low. This does not conform to the I²C Specification that

states no bus collision can occur on a Start.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

21.4.6 STOP CONDITION

A Stop condition is a transition of the SDAx line from

low-to-high state while the SCLx line is high.

Note: At least one SCLx low time must appear

before a Stop is valid, therefore, if the SDAx

line goes low then high again while the SCLx

line stays high, only the Start condition is

detected.

After a full match with R/W clear in 10-bit mode, a prior

match flag is set and maintained. Until a Stop condi-

tion, a high address with R/W clear, or high address

match fails.

21.4.8 START/STOP CONDITION INTERRUPT

MASKING

The SCIE and PCIE bits of the SSPxCON3 register

can enable the generation of an interrupt in Slave

modes that do not typically support this function. Slave

modes where interrupt on Start and Stop detect are

already enabled, these bits will have no effect.

FIGURE 21-12:

I²C START AND STOP CONDITIONS

SDAx

SCLx

S

P

Change of

Data Allowed

Stop

Start

Condition

FIGURE 21-13:

I²C RESTART CONDITION

Sr

Change of

Data Allowed

Restart

Condition

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21.4.9 ACKNOWLEDGE SEQUENCE

21.5.1.1 I²C Slave 7-bit Addressing Mode

The ninth SCLx pulse for any transferred byte in I²C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDAx line low. The transmitter must release con-

trol of the line during this time to shift in the response.

The Acknowledge (ACK) is an active-low signal, pull-

ing the SDAx line low indicated to the transmitter that

the device has received the transmitted data and is

ready to receive more.

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

21.5.1.2 I²C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSbs of the 10-bit address and

stored in bits 2 and 1 of the SSPxADD register.

The result of an ACK is placed in the ACKSTAT bit of

the SSPxCON2 register.

After the acknowledge of the high byte the UA bit is set

and SCLx is held low until the user updates SSPxADD

with the low address. The low address byte is clocked

in and all eight bits are compared to the low address

value in SSPxADD. Even if there is not an address

match; SSPxIF and UA are set, and SCLx is held low

until SSPxADD is updated to receive a high byte

again. When SSPxADD is updated the UA bit is

cleared. This ensures the module is ready to receive

the high address byte on the next communication.

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSPxCON2 reg-

ister is set/cleared to determine the response.

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSPxCON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSPxSTAT regis-

ter or the SSPOV bit of the SSPxCON1 register are

set when a byte is received.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave hard-

ware will then acknowledge the read request and pre-

pare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

When the module is addressed, after the eighth falling

edge of SCLx on the bus, the ACKTIM bit of the

SSPxCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

21.5.2 SLAVE RECEPTION

21.5 I²C Slave Mode Operation

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPxSTAT register is

cleared. The received address is loaded into the

SSPxBUF register and acknowledged.

The MSSP Slave mode operates in one of four modes

selected in the SSPM bits of SSPxCON1 register. The

modes can be divided into 7-bit and 10-bit Addressing

mode. 10-bit Addressing modes operate the same as

7-bit with some additional overhead for handling the

larger addresses.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF of the SSPxSTAT

register is set, or bit SSPOV of the SSPxCON1 register

is set. The BOEN bit of the SSPxCON3 register modi-

fies this operation. For more information see

Register 21-4.

Modes with Start and Stop bit interrupts operate the

same as the other modes with SSPxIF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

An MSSP interrupt is generated for each transferred

data byte. Flag bit, SSPxIF, must be cleared by soft-

ware.

21.5.1 SLAVE MODE ADDRESSES

The SSPxADD register (Register 21-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSPxBUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the soft-

ware that anything happened.

When the SEN bit of the SSPxCON2 register is set,

SCLx will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSPxCON1 register, except

sometimes in 10-bit mode. See Section21.2.3 “SPI

Master Mode” for more detail.

21.5.2.1 7-bit Addressing Reception

The SSP Mask register (Register 21-5) affects the

address matching process. See Section21.5.9 “SSPx

Mask Register” for more information.

This section describes a standard sequence of events

for the MSSP module configured as an I²C slave in

7-bit Addressing mode. Figure 21-14 and Figure 21-15

are used as visual references for this description.

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This is a step by step process of what typically must

be done to accomplish I²C communication.

21.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the eighth

falling edge of SCLx. These additional interrupts allow

the slave software to decide whether it wants to ACK

the receive address or data byte, rather than the hard-

ware. This functionality adds support for PMBus™ that

was not present on previous versions of this module.

1. Start bit detected.

2. S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

3. Matching address with R/W bit clear is received.

4. The slave pulls SDAx low sending an ACK to the

master, and sets SSPxIF bit.

5. Software clears the SSPxIF bit.

This list describes the steps that need to be taken by

slave software to use these options for I²C communi-

cation. Figure 21-16 displays a module using both

address and data holding. Figure 21-17 includes the

operation with the SEN bit of the SSPxCON2 register

set.

6. Software reads received address from

SSPxBUF clearing the BF flag.

7. If SEN = 1; Slave software sets CKP bit to

release the SCLx line.

8. The master clocks out a data byte.

9. Slave drives SDAx low sending an ACK to the

master, and sets SSPxIF bit.

1. S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

10. Software clears SSPxIF.

2. Matching address with R/W bit clear is clocked

in. SSPxIF is set and CKP cleared after the

eighth falling edge of SCLx.

11. Software reads the received byte from

SSPxBUF clearing BF.

12. Steps 8-12 are repeated for all received bytes

from the Master.

3. Slave clears the SSPxIF.

4. Slave can look at the ACKTIM bit of the

SSPxCON3 register to determine if the SSPxIF

was after or before the ACK.

13. Master sends Stop condition, setting P bit of

SSPxSTAT, and the bus goes idle.

5. Slave reads the address value from SSPxBUF,

clearing the BF flag.

6. Slave sets ACK value clocked out to the master

by setting ACKDT.

7. Slave releases the clock by setting CKP.

8. SSPxIF is set after an ACK, not after a NACK.

9. If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSPxIF.

Note: SSPxIF is still set after the ninth falling edge

of SCLx even if there is no clock stretching

and BF has been cleared. Only if NACK is

sent to master is SSPxIF not set

11. SSPxIF set and CKP cleared after eighth falling

edge of SCLx for a received data byte.

12. Slave looks at ACKTIM bit of SSPxCON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSPxBUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK = 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSPSTAT register.

DS40001609E-page 186

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PIC16(L)F1508/9

FIGURE 21-14:

I²C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 187

PIC16(L)F1508/9

FIGURE 21-15:

I²C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

DS40001609E-page 188

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 21-16:

I²C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 189

PIC16(L)F1508/9

FIGURE 21-17:

I²C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)

DS40001609E-page 190

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PIC16(L)F1508/9

21.5.3

SLAVE TRANSMISSION

21.5.3.2

7-bit Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPxSTAT register is set. The received address is

loaded into the SSPxBUF register, and an ACK pulse is

sent by the slave on the ninth bit.

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to

do to accomplish

a

standard transmission.

Figure 21-18 can be used as a reference to this list.

Following the ACK, slave hardware clears the CKP bit

1. Master sends a Start condition on SDAx and

SCLx.

and

the

SCLx

is

held

low

(see

Section21.5.6 “Clock Stretching” for more detail). By

stretching the clock, the master will be unable to assert

another clock pulse until the slave is done preparing

the transmit data.

2. S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

3. Matching address with R/W bit set is received by

the slave setting SSPxIF bit.

The transmit data must be loaded into the SSPxBUF

register which also loads the SSPxSR register. Then

the SCLx pin should be released by setting the CKP bit

of the SSPxCON1 register. The eight data bits are

shifted out on the falling edge of the SCLx input. This

ensures that the SDAx signal is valid during the SCLx

high time.

4. Slave hardware generates an ACK and sets

SSPxIF.

5. SSPxIF bit is cleared by user.

6. Software reads the received address from

SSPxBUF, clearing BF.

7. R/W is set so CKP was automatically cleared

after the ACK.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCLx input pulse. This ACK

value is copied to the ACKSTAT bit of the SSPxCON2

register. If ACKSTAT is set (not ACK), then the data

transfer is complete. In this case, when the not ACK is

latched by the slave, the slave goes idle and waits for

another occurrence of the Start bit. If the SDAx line was

low (ACK), the next transmit data must be loaded into

the SSPxBUF register. Again, the SCLx pin must be

released by setting bit CKP.

8. The slave software loads the transmit data into

SSPxBUF.

9. CKP bit is set releasing SCLx, allowing the mas-

ter to clock the data out of the slave.

10. SSPxIF is set after the ACK response from the

master is loaded into the ACKSTAT register.

11. SSPxIF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

An MSSP interrupt is generated for each data transfer

byte. The SSPxIF bit must be cleared by software and

the SSPxSTAT register is used to determine the status

of the byte. The SSPxIF bit is set on the falling edge of

the ninth clock pulse.

Note 1: If the master ACKs the clock will be

stretched.

2: ACKSTAT is the only bit updated on the

rising edge of SCLx (ninth) rather than the

falling.

21.5.3.1

Slave Mode Bus Collision

13. Steps 9-13 are repeated for each transmitted

byte.

A slave receives a Read request and begins shifting

data out on the SDAx line. If a bus collision is detected

and the SBCDE bit of the SSPxCON3 register is set,

the BCLxIF bit of the PIRx register is set. Once a bus

collision is detected, the slave goes idle and waits to be

addressed again. User software can use the BCLxIF bit

to handle a slave bus collision.

14. If the master sends a not ACK; the clock is not

held, but SSPxIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

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PIC16(L)F1508/9

FIGURE 21-18:

I²C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

DS40001609E-page 192

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PIC16(L)F1508/9

21.5.3.3

7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPxCON3 register

enables additional clock stretching and interrupt gen-

eration after the eighth falling edge of a received

matching address. Once a matching address has

been clocked in, CKP is cleared and the SSPxIF inter-

rupt is set.

Figure 21-19 displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

1. Bus starts idle.

2. Master sends Start condition; the S bit of

SSPxSTAT is set; SSPxIF is set if interrupt on

Start detect is enabled.

3. Master sends matching address with R/W bit

set. After the eighth falling edge of the SCLx line

the CKP bit is cleared and SSPxIF interrupt is

generated.

4. Slave software clears SSPxIF.

5. Slave software reads ACKTIM bit of SSPxCON3

register, and R/W and D/A of the SSPxSTAT

register to determine the source of the interrupt.

6. Slave reads the address value from the

SSPxBUF register clearing the BF bit.

7. Slave software decides from this information if it

wishes to ACK or not ACK and sets the ACKDT

bit of the SSPxCON2 register accordingly.

8. Slave sets the CKP bit releasing SCLx.

9. Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit

and sets SSPxIF after the ACK if the R/W bit is

set.

11. Slave software clears SSPxIF.

12. Slave loads value to transmit to the master into

SSPxBUF setting the BF bit.

Note: SSPxBUF cannot be loaded until after the

ACK.

13. Slave sets the CKP bit, releasing the clock.

14. Master clocks out the data from the slave and

sends an ACK value on the ninth SCLx pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPxCON2 register.

16. Steps 10-15 are repeated for each byte transmit-

ted to the master from the slave.

17. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: Master must send a not ACK on the last byte

to ensure that the slave releases the SCLx

line to receive a Stop.

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DS40001609E-page 193

PIC16(L)F1508/9

FIGURE 21-19:

I²C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

DS40001609E-page 194

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

21.5.4 SLAVE MODE 10-BIT ADDRESS

RECEPTION

21.5.5 10-BIT ADDRESSING WITH ADDRESS OR

DATA HOLD

This section describes a standard sequence of events

for the MSSP module configured as an I²C slave in

10-bit Addressing mode.

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only

difference is the need to update the SSPxADD register

using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCLx line is held low are the

same. Figure 21-21 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 21-20 is used as a visual reference for this

description.

This is a step by step process of what must be done by

slave software to accomplish I²C communication.

Figure 21-22 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

1. Bus starts idle.

2. Master sends Start condition; S bit of SSPxSTAT

is set; SSPxIF is set if interrupt on Start detect is

enabled.

3. Master sends matching high address with R/W

bit clear; UA bit of the SSPxSTAT register is set.

4. Slave sends ACK and SSPxIF is set.

5. Software clears the SSPxIF bit.

6. Software reads received address from

SSPxBUF clearing the BF flag.

7. Slave loads low address into SSPxADD,

releasing SCLx.

8. Master sends matching low address byte to the

slave; UA bit is set.

Note: Updates to the SSPxADD register are not

allowed until after the ACK sequence.

9. Slave sends ACK and SSPxIF is set.

Note: If the low address does not match, SSPxIF

and UA are still set so that the slave soft-

ware can set SSPxADD back to the high

address. BF is not set because there is no

match. CKP is unaffected.

10. Slave clears SSPxIF.

11. Slave reads the received matching address

from SSPxBUF clearing BF.

12. Slave loads high address into SSPxADD.

13. Master clocks a data byte to the slave and

clocks out the slaves ACK on the ninth SCLx

pulse; SSPxIF is set.

14. If SEN bit of SSPxCON2 is set, CKP is cleared

by hardware and the clock is stretched.

15. Slave clears SSPxIF.

16. Slave reads the received byte from SSPxBUF

clearing BF.

17. If SEN is set the slave sets CKP to release the

SCLx.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

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FIGURE 21-20:

I²C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

DS40001609E-page 196

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 21-21:

I²C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 197

PIC16(L)F1508/9

FIGURE 21-22:

I²C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

DS40001609E-page 198

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

21.5.6 CLOCK STRETCHING

21.5.6.2 10-bit Addressing Mode

Clock stretching occurs when a device on the bus

holds the SCLx line low, effectively pausing communi-

cation. The slave may stretch the clock to allow more

time to handle data or prepare a response for the mas-

ter device. A master device is not concerned with

stretching as anytime it is active on the bus and not

transferring data it is stretching. Any stretching done

by a slave is invisible to the master software and han-

dled by the hardware that generates SCLx.

In 10-bit Addressing mode, when the UA bit is set, the

clock is always stretched. This is the only time the

SCLx is stretched without CKP being cleared. SCLx is

released immediately after a write to SSPxADD.

Note: Previous versions of the module did not

stretch the clock if the second address byte

did not match.

21.5.6.3 Byte NACKing

The CKP bit of the SSPxCON1 register is used to con-

trol stretching in software. Any time the CKP bit is

cleared, the module will wait for the SCLx line to go

low and then hold it. Setting CKP will release SCLx

and allow more communication.

When the AHEN bit of SSPxCON3 is set; CKP is

cleared by hardware after the eighth falling edge of

SCLx for a received matching address byte. When the

DHEN bit of SSPxCON3 is set, CKP is cleared after

the eighth falling edge of SCLx for received data.

21.5.6.1 Normal Clock Stretching

Stretching after the eighth falling edge of SCLx allows

the slave to look at the received address or data and

decide if it wants to ACK the received data.

Following an ACK if the R/W bit of SSPxSTAT is set, a

read request, the slave hardware will clear CKP. This

allows the slave time to update SSPxBUF with data to

transfer to the master. If the SEN bit of SSPxCON2 is

set, the slave hardware will always stretch the clock

after the ACK sequence. Once the slave is ready, CKP

is set by software and communication resumes.

21.5.7 CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait

for the SCLx line to go low and then hold it. However,

clearing the CKP bit will not assert the SCLx output

low until the SCLx output is already sampled low.

Therefore, the CKP bit will not assert the SCLx line

until an external I²C master device has already

asserted the SCLx line. The SCLx output will remain

low until the CKP bit is set and all other devices on the

I²C bus have released SCLx. This ensures that a write

to the CKP bit will not violate the minimum high time

requirement for SCLx (see Figure 21-23).

Note 1: The BF bit has no effect on if the clock will

be stretched or not. This is different than

previous versions of the module that

would not stretch the clock, clear CKP, if

SSPxBUF was read before the ninth fall-

ing edge of SCLx.

2: Previous versions of the module did not

stretch the clock for a transmission if

SSPxBUF was loaded before the ninth

falling edge of SCLx. It is now always

cleared for read requests.

FIGURE 21-23:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDAx

SCLx

DX

DX ‚ – 1

Master device

asserts clock

CKP

Master device

releases clock

WR

SSPxCON1

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21.5.8 GENERAL CALL ADDRESS SUPPORT

In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave

will prepare to receive the second byte as data, just as

it would in 7-bit mode.

The addressing procedure for the I²C bus is such that

the first byte after the Start condition usually deter-

mines which device will be the slave addressed by the

master device. The exception is the general call

address which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

If the AHEN bit of the SSPxCON3 register is set, just

as with any other address reception, the slave hard-

ware will stretch the clock after the eighth falling edge

of SCLx. The slave must then set its ACKDT value and

release the clock with communication progressing as it

would normally.

The general call address is a reserved address in the

I²C protocol, defined as address 0x00. When the

GCEN bit of the SSPxCON2 register is set, the slave

module will automatically ACK the reception of this

address regardless of the value stored in SSPxADD.

After the slave clocks in an address of all zeros with

the R/W bit clear, an interrupt is generated and slave

software can read SSPxBUF and respond.

Figure 21-24 shows

sequence.

a

General Call reception

FIGURE 21-24:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data

D5 D4 D3 D2 D1 D0

ACK

9

R/W = 0

General Call Address

ACK

SDAx

D7 D6

SCLx

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

S

SSPxIF

BF (SSPxSTAT<0>)

Cleared by software

SSPxBUF is read

GCEN (SSPxCON2<7>)

’1’

21.5.9 SSPx MASK REGISTER

An SSPx Mask (SSPxMSK) register (Register 21-5) is

available in I²C Slave mode as a mask for the value

held in the SSPxSR register during an address

comparison operation. A zero (‘0’) bit in the SSPxMSK

register has the effect of making the corresponding bit

of the received address a “don’t care”.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSPx operation until written with a mask value.

The SSPx Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSPx mask has no effect during the

reception of the first (high) byte of the address.

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21.6.1 I²C MASTER MODE OPERATION

2

21.6 I C MASTER MODE

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

Master mode is enabled by setting and clearing the

appropriate SSPM bits in the SSPxCON1 register and

by setting the SSPEN bit. In Master mode, the SDAx

and SCKx pins must be configured as inputs. The

MSSP peripheral hardware will override the output

driver TRIS controls when necessary to drive the pins

low.

In Master Transmitter mode, serial data is output

through SDAx, while SCLx outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (seven bits) and the Read/Write (R/W)

bit. In this case, the R/W bit will be logic ‘0’. Serial data

is transmitted eight bits at a time. After each byte is

transmitted, an Acknowledge bit is received. Start and

Stop conditions are output to indicate the beginning

and the end of a serial transfer.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions. The Stop (P) and Start (S) bits are cleared from

a Reset or when the MSSPx module is disabled. Con-

trol of the I²C bus may be taken when the P bit is set,

or the bus is idle.

In Firmware Controlled Master mode, user code

conducts all I²C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDAx and SCLx lines.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(seven bits) and the R/W bit. In this case, the R/W bit

will be logic ‘1’. Thus, the first byte transmitted is a 7-bit

slave address followed by a ‘1’ to indicate the receive

bit. Serial data is received via SDAx, while SCLx out-

puts the serial clock. Serial data is received eight bits at

a time. After each byte is received, an Acknowledge bit

is transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

The following events will cause the SSPx Interrupt Flag

bit, SSPxIF, to be set (SSPx interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

A Baud Rate Generator is used to set the clock

frequency output on SCLx. See Section21.7 “Baud

Rate Generator” for more detail.

Note 1: The MSSPx module, when configured in

I²C Master mode, does not allow queue-

ing of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPxBUF register

to initiate transmission before the Start

condition is complete. In this case, the

SSPxBUF will not be written to and the

WCOL bit will be set, indicating that a

write to the SSPxBUF did not occur

2: When in Master mode, Start/Stop detec-

tion is masked and an interrupt is gener-

ated when the SEN/PEN bit is cleared and

the generation is complete.

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21.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCLx pin (SCLx allowed to float high).

When the SCLx pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCLx pin is actually sampled high. When the

SCLx pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPxADD<7:0> and

begins counting. This ensures that the SCLx high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 21-25).

FIGURE 21-25:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDAx

DX

DX ‚ – 1

SCLx allowed to transition high

SCLx deasserted but slave holds

SCLx low (clock arbitration)

SCLx

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCLx is sampled high, reload takes

place and BRG starts its count

BRG

Reload

21.6.3 WCOL STATUS FLAG

If the user writes the SSPxBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL bit is set and the contents of the buffer are

unchanged (the write does not occur). Any time the

WCOL bit is set it indicates that an action on SSPxBUF

was attempted while the module was not idle.

Note:

Because queuing of events is not allowed,

writing to the lower five bits of SSPxCON2

is disabled until the Start condition is

complete.

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2

21.6.4 I C MASTER MODE START

by hardware; the Baud Rate Generator is suspended,

leaving the SDAx line held low and the Start condition

is complete.

CONDITION TIMING

To initiate a Start condition (Figure 21-26), the user

sets the Start Enable bit, SEN bit of the SSPxCON2

register. If the SDAx and SCLx pins are sampled high,

the Baud Rate Generator is reloaded with the contents

of SSPxADD<7:0> and starts its count. If SCLx and

SDAx are both sampled high when the Baud Rate

Generator times out (TBRG), the SDAx pin is driven

low. The action of the SDAx being driven low while

SCLx is high is the Start condition and causes the S bit

of the SSPxSTAT1 register to be set. Following this,

the Baud Rate Generator is reloaded with the contents

of SSPxADD<7:0> and resumes its count. When the

Baud Rate Generator times out (TBRG), the SEN bit of

the SSPxCON2 register will be automatically cleared

Note 1: If at the beginning of the Start condition,

the SDAx and SCLx pins are already sam-

pled low, or if during the Start condition,

the SCLx line is sampled low before the

SDAx line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLxIF, is set, the Start condition is

aborted and the I²C module is reset into

its Idle state.

2: The Philips I²C Specification states that a

bus collision cannot occur on a Start.

FIGURE 21-26:

FIRST START BIT TIMING

Set S bit (SSPxSTAT<3>)

Write to SEN bit occurs here

At completion of Start bit,

hardware clears SEN bit

and sets SSPxIF bit

SDAx = 1,

SCLx = 1

TBRG

Write to SSPxBUF occurs here

2nd bit

SDAx

1st bit

TBRG

SCLx

S

TBRG

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2

21.6.5 I C MASTER MODE REPEATED

automatically cleared and the Baud Rate Generator will

not be reloaded, leaving the SDAx pin held low. As

soon as a Start condition is detected on the SDAx and

SCLx pins, the S bit of the SSPxSTAT register will be

set. The SSPxIF bit will not be set until the Baud Rate

Generator has timed out.

START CONDITION TIMING

A Repeated Start condition (Figure 21-27) occurs when

the RSEN bit of the SSPxCON2 register is pro-

grammed high and the master state machine is no lon-

ger active. When the RSEN bit is set, the SCLx pin is

asserted low. When the SCLx pin is sampled low, the

Baud Rate Generator is loaded and begins counting.

The SDAx pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDAx is sampled high, the SCLx

pin will be deasserted (brought high). When SCLx is

sampled high, the Baud Rate Generator is reloaded

and begins counting. SDAx and SCLx must be sam-

pled high for one TBRG. This action is then followed by

assertion of the SDAx pin (SDAx = 0) for one TBRG

while SCLx is high. SCLx is asserted low. Following

this, the RSEN bit of the SSPxCON2 register will be

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

• SDAx is sampled low when SCLx

goes from low-to-high.

• SCLx goes low before SDAx is

asserted low. This may indicate

that another master is attempting to

transmit a data ‘1’.

FIGURE 21-27:

REPEAT START CONDITION WAVEFORM

S bit set by hardware

Write to SSPxCON2

occurs here

SDAx = 1,

At completion of Start bit,

hardware clears RSEN bit

and sets SSPxIF

SDAx = 1,

SCLx = 1

SCLx (no change)

TBRG

1st bit

SDAx

SCLx

Write to SSPxBUF occurs here

TBRG

Sr

Repeated Start

TBRG

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21.6.6 I²C MASTER MODE TRANSMISSION

21.6.6.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSPxCON2

register is cleared when the slave has sent an Acknowl-

edge (ACK = 0) and is set when the slave does not

Acknowledge (ACK = 1). A slave sends an Acknowl-

edge when it has recognized its address (including a

general call), or when the slave has properly received

its data.

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPxBUF register. This action will

set the Buffer Full flag bit, BF, and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDAx pin after the falling edge of SCLx is

asserted. SCLx is held low for one Baud Rate Genera-

tor rollover count (TBRG). Data should be valid before

SCLx is released high. When the SCLx pin is released

high, it is held that way for TBRG. The data on the SDAx

pin must remain stable for that duration and some hold

time after the next falling edge of SCLx. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDAx.

This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received prop-

erly. The status of ACK is written into the ACKSTAT bit

on the rising edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSPxIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPxBUF, leaving SCLx low and

SDAx unchanged (Figure 21-28).

21.6.6.4

Typical transmit sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSPxCON2 register.

2. SSPxIF is set by hardware on completion of the

Start.

3. SSPxIF is cleared by software.

4. The MSSPx module will wait the required start

time before any other operation takes place.

5. The user loads the SSPxBUF with the slave

address to transmit.

6. Address is shifted out the SDAx pin until all eight

bits are transmitted. Transmission begins as

soon as SSPxBUF is written to.

7. The MSSPx module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

8. The MSSPx module generates an interrupt at

the end of the ninth clock cycle by setting the

SSPxIF bit.

After the write to the SSPxBUF, each bit of the address

will be shifted out on the falling edge of SCLx until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

release the SDAx pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

clock, the master will sample the SDAx pin to see if the

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT Status bit of the

SSPxCON2 register. Following the falling edge of the

ninth clock transmission of the address, the SSPxIF is

set, the BF flag is cleared and the Baud Rate Generator

is turned off until another write to the SSPxBUF takes

place, holding SCLx low and allowing SDAx to float.

9. The user loads the SSPxBUF with eight bits of

data.

10. Data is shifted out the SDAx pin until all eight

bits are transmitted.

11. The MSSPx module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the

SSPxCON2 register. Interrupt is generated once

the Stop/Restart condition is complete.

21.6.6.1

BF Status Flag

In Transmit mode, the BF bit of the SSPxSTAT register

is set when the CPU writes to SSPxBUF and is cleared

when all eight bits are shifted out.

21.6.6.2

WCOL Status Flag

If the user writes the SSPxBUF when a transmit is

already in progress (i.e., SSPxSR is still shifting out a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write does not occur).

WCOL must be cleared by software before the next

transmission.

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FIGURE 21-28:

I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

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I²C MASTER MODE RECEPTION

21.6.7.4 Typical Receive Sequence:

21.6.7

Master mode reception (Figure 21-29) is enabled by

programming the Receive Enable bit, RCEN bit of the

SSPxCON2 register.

1. The user generates a Start condition by setting

the SEN bit of the SSPxCON2 register.

2. SSPxIF is set by hardware on completion of the

Start.

Note:

The MSSPx module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

3. SSPxIF is cleared by software.

4. User writes SSPxBUF with the slave address to

transmit and the R/W bit set.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCLx pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPxSR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the con-

tents of the SSPxSR are loaded into the SSPxBUF, the

BF flag bit is set, the SSPxIF flag bit is set and the Baud

Rate Generator is suspended from counting, holding

SCLx low. The MSSP is now in Idle state awaiting the

next command. When the buffer is read by the CPU,

the BF flag bit is automatically cleared. The user can

then send an Acknowledge bit at the end of reception

by setting the Acknowledge Sequence Enable, ACKEN

bit of the SSPxCON2 register.

5. Address is shifted out the SDAx pin until all eight

bits are transmitted. Transmission begins as

soon as SSPxBUF is written to.

6. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

7. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the

SSPxIF bit.

8. User sets the RCEN bit of the SSPxCON2 regis-

ter and the master clocks in a byte from the slave.

9. After the eighth falling edge of SCLx, SSPxIF

and BF are set.

10. Master clears SSPxIF and reads the received

byte from SSPxBUF, clears BF.

21.6.7.1

BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPxBUF from SSPxSR. It

is cleared when the SSPxBUF register is read.

11. Master sets ACK value sent to slave in ACKDT

bit of the SSPxCON2 register and initiates the

ACK by setting the ACKEN bit.

21.6.7.2

SSPOV Status Flag

12. Masters ACK is clocked out to the slave and

SSPxIF is set.

In receive operation, the SSPOV bit is set when eight

bits are received into the SSPxSR and the BF flag bit is

already set from a previous reception.

13. User clears SSPxIF.

14. Steps 8-13 are repeated for each received byte

from the slave.

21.6.7.3

WCOL Status Flag

15. Master sends a not ACK or Stop to end

communication.

If the user writes the SSPxBUF when a receive is

already in progress (i.e., SSPxSR is still shifting in a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write does not occur).

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2

FIGURE 21-29:

I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

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21.6.8

ACKNOWLEDGE SEQUENCE

TIMING

21.6.9

STOP CONDITION TIMING

A Stop bit is asserted on the SDAx pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN bit of the SSPxCON2 register. At the end of a

receive/transmit, the SCLx line is held low after the

falling edge of the ninth clock. When the PEN bit is set,

the master will assert the SDAx line low. When the

SDAx line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCLx pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDAx pin will be deasserted. When the SDAx

pin is sampled high while SCLx is high, the P bit of the

SSPxSTAT register is set. A TBRG later, the PEN bit is

cleared and the SSPxIF bit is set (Figure 21-31).

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the

SSPxCON2 register. When this bit is set, the SCLx pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDAx pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCLx pin is deasserted (pulled high).

When the SCLx pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCLx pin

is then pulled low. Following this, the ACKEN bit is auto-

matically cleared, the Baud Rate Generator is turned off

and the MSSP module then goes into Idle mode

(Figure 21-30).

21.6.9.1

WCOL Status Flag

If the user writes the SSPxBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write does

not occur).

21.6.8.1

WCOL Status Flag

If the user writes the SSPxBUF when an Acknowledge

sequence is in progress, then the WCOL bit is set and

the contents of the buffer are unchanged (the write

does not occur).

FIGURE 21-30:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

write to SSPxCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDAx

SCLx

D0

8

9

SSPxIF

Cleared in

SSPxIF set at

the end of receive

software

Cleared in

software

SSPxIF set at the end

of Acknowledge sequence

Note: TBRG = one Baud Rate Generator period.

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FIGURE 21-31:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCLx = 1for TBRG, followed by SDAx = 1for TBRG

after SDAx sampled high. P bit (SSPxSTAT<4>) is set.

Write to SSPxCON2,

set PEN

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

Falling edge of

9th clock

TBRG

SCLx

ACK

SDAx

P

TBRG

SCLx brought high after TBRG

SDAx asserted low before rising edge of clock

to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

21.6.10 SLEEP OPERATION

21.6.13 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

While in Sleep mode, the I²C slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDAx pin, arbitration takes place when the master

outputs a ‘1’ on SDAx, by letting SDAx float high and

another master asserts a ‘0’. When the SCLx pin floats

high, data should be stable. If the expected data on

SDAx is a ‘1’ and the data sampled on the SDAx pin is

‘0’, then a bus collision has taken place. The master will

set the Bus Collision Interrupt Flag, BCLxIF and reset

the I²C port to its Idle state (Figure 21-32).

21.6.11 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

21.6.12 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I²C bus may

be taken when the P bit of the SSPxSTAT register is

set, or the bus is idle, with both the S and P bits clear.

When the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDAx and SCLx lines are deasserted and

the SSPxBUF can be written to. When the user ser-

vices the bus collision Interrupt Service Routine and if

the I²C bus is free, the user can resume communica-

tion by asserting a Start condition.

In Multi-Master mode, the SDAx line must be monitored

for arbitration to see if the signal level is the expected

output level. This check is performed by hardware with

the result placed in the BCLxIF bit.

If a Start, Repeated Start, Stop or Acknowledge condi-

tion was in progress when the bus collision occurred, the

condition is aborted, the SDAx and SCLx lines are deas-

serted and the respective control bits in the SSPxCON2

register are cleared. When the user services the bus col-

lision Interrupt Service Routine and if the I²C bus is free,

the user can resume communication by asserting a Start

condition.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

The master will continue to monitor the SDAx and SCLx

pins. If a Stop condition occurs, the SSPxIF bit will be set.

• A Repeated Start Condition

• An Acknowledge Condition

A write to the SSPxBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I²C bus

can be taken when the P bit is set in the SSPxSTAT

register, or the bus is idle and the S and P bits are

cleared.

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FIGURE 21-32:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDAx. While SCLx is high,

data does not match what is driven

by the master.

Data changes

while SCLx = 0

SDAx line pulled low

by another source

Bus collision has occurred.

SDAx released

by master

SDAx

SCLx

Set bus collision

interrupt (BCLxIF)

BCLxIF

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If the SDAx pin is sampled low during this count, the

BRG is reset and the SDAx line is asserted early

(Figure 21-35). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to zero; if the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

21.6.13.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 21-33).

b) SCL is sampled low before SDAx is asserted

low (Figure 21-34).

During a Start condition, both the SDAx and the SCL

pins are monitored.

Note:

The reason that bus collision is not a fac-

tor during a Start condition is that no two

bus masters can assert a Start condition

at the exact same time. Therefore, one

master will always assert SDAx before the

other. This condition does not cause a bus

collision because the two masters must be

allowed to arbitrate the first address fol-

lowing the Start condition. If the address is

the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted,

• the BCL1IF flag is set and

•

the MSSP module is reset to its Idle state

(Figure 21-33).

The Start condition begins with the SDAx and SCLx

pins deasserted. When the SDAx pin is sampled high,

the Baud Rate Generator is loaded and counts down. If

the SCLx pin is sampled low while SDAx is high, a bus

collision occurs because it is assumed that another

master is attempting to drive a data ‘1’ during the Start

condition.

FIGURE 21-33:

BUS COLLISION DURING START CONDITION (SDAX ONLY)

SDAx goes low before the SEN bit is set.

Set BCLxIF,

S bit and SSPxIF set because

SDAx = 0, SCLx = 1.

SDAx

SCLx

SEN

Set SEN, enable Start

condition if SDAx = 1, SCLx = 1

SEN cleared automatically because of bus collision.

SSP module reset into Idle state.

SDAx sampled low before

Start condition. Set BCLxIF.

S bit and SSPxIF set because

SDAx = 0, SCLx = 1.

BCLxIF

SSPxIF and BCLxIF are

cleared by software

S

SSPxIF

SSPxIF and BCLxIF are

cleared by software

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FIGURE 21-34:

BUS COLLISION DURING START CONDITION (SCLX = 0)

SDAx = 0, SCLx = 1

TBRG

SDAx

Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1

SCLx

SEN

SCLx = 0before SDAx = 0,

bus collision occurs. Set BCLxIF.

SCLx = 0before BRG time-out,

bus collision occurs. Set BCLxIF.

BCLxIF

Interrupt cleared

by software

S

‘0’

SSPxIF

FIGURE 21-35:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDAx = 0, SCLx = 1

Set S

Set SSPxIF

Less than TBRG

TBRG

SDAx pulled low by other master.

Reset BRG and assert SDAx.

SDAx

SCLx

S

SCLx pulled low after BRG

time-out

SEN

Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1

BCLxIF

‘0’

S

SSPxIF

Interrupts cleared

by software

SDAx = 0, SCLx = 1,

set SSPxIF

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If SDAx is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 21-36).

If SDAx is sampled high, the BRG is reloaded and

begins counting. If SDAx goes from high-to-low before

the BRG times out, no bus collision occurs because no

two masters can assert SDAx at exactly the same time.

21.6.13.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDAx when SCLx

goes from low level to high level (Case 1).

If SCLx goes from high-to-low before the BRG times

out and SDAx has not already been asserted, a bus

collision occurs. In this case, another master is

attempting to transmit a data ‘1’ during the Repeated

Start condition, see Figure 21-37.

b) SCLx goes low before SDAx is asserted low,

indicating that another master is attempting to

transmit a data ‘1’ (Case 2).

When the user releases SDAx and the pin is allowed to

float high, the BRG is loaded with SSPxADD and

counts down to zero. The SCLx pin is then deasserted

and when sampled high, the SDAx pin is sampled.

If, at the end of the BRG time-out, both SCLx and SDAx

are still high, the SDAx pin is driven low and the BRG

is reloaded and begins counting. At the end of the

count, regardless of the status of the SCLx pin, the

SCLx pin is driven low and the Repeated Start

condition is complete.

FIGURE 21-36:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDAx

SCLx

Sample SDAx when SCLx goes high.

If SDAx = 0, set BCLxIF and release SDAx and SCLx.

RSEN

BCLxIF

Cleared by software

‘0’

S

‘0’

SSPxIF

FIGURE 21-37:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDAx

SCLx

SCLx goes low before SDAx,

BCLxIF

RSEN

set BCLxIF. Release SDAx and SCLx.

Interrupt cleared

by software

‘0’

S

SSPxIF

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The Stop condition begins with SDAx asserted low.

When SDAx is sampled low, the SCLx pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPxADD and

counts down to 0. After the BRG times out, SDAx is

sampled. If SDAx is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 21-38). If the SCLx pin is

sampled low before SDAx is allowed to float high, a bus

collision occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 21-39).

21.6.13.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDAx pin has been deasserted and

allowed to float high, SDAx is sampled low after

the BRG has timed out (Case 1).

b) After the SCLx pin is deasserted, SCLx is

sampled low before SDAx goes high (Case 2).

FIGURE 21-38:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDAx sampled

low after TBRG,

set BCLxIF

TBRG

SDAx

SDAx asserted low

SCLx

PEN

BCLxIF

P

‘0’

SSPxIF

FIGURE 21-39:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDAx

SCLx goes low before SDAx goes high,

set BCLxIF

Assert SDAx

SCLx

PEN

BCLxIF

P

‘0’

SSPxIF

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TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH I²C™ OPERATION

Reset

Valueson

Page:

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

TMR1GIE

OSFIE

TMR1GIF

OSFIF

—

PEIE

ADIE

C2IE

TMR0IE

RCIE

INTE

TXIE

—

IOCIE

SSP1IE

BCL1IE

SSP1IF

BCL1IF

TMR0IF

—

INTF

TMR2IE

—

IOCIF

TMR1IE

—

75

76

C1IE

PIE2

NCO1IE

—

77

PIR1

ADIF

C2IF

RCIF

C1IF

TXIF

—

TMR2IF

—

TMR1IF

—

79

NCO1IF

TRISA2

PIR2

80

(1)

—

TRISA

TRISA5

TRISA4

TRISA1

TRISA0

109

222

173*

219

220

221

222

218

—

SSP1ADD

SSP1BUF

SSP1CON1

SSP1CON2

SSP1CON3

SSP1MSK

SSP1STAT

ADD<7:0>

MSSP Receive Buffer/Transmit Register

WCOL

GCEN

SSPOV

ACKSTAT

PCIE

SSPEN

ACKDT

SCIE

CKP

ACKEN

BOEN

SSPM<3:0>

RCEN

PEN

RSEN

AHEN

SEN

ACKTIM

SDAHT

SBCDE

DHEN

MSK<7:0>

SMP

CKE

D/A

P

S

R/W

UA

BF

2

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I C™ mode.

*

Page provides register information.

Note 1: Unimplemented, read as ‘1’.

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module clock line. The logic dictating when the reload

signal is asserted depends on the mode the MSSP is

being operated in.

21.7 BAUD RATE GENERATOR

The MSSP module has a Baud Rate Generator avail-

able for clock generation in both I²C and SPI Master

modes. The Baud Rate Generator (BRG) reload value

is placed in the SSPxADD register (Register 21-6).

When a write occurs to SSPxBUF, the Baud Rate Gen-

erator will automatically begin counting down.

Table 21-4 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPxADD.

EQUATION 21-1:

Once the given operation is complete, the internal clock

will automatically stop counting and the clock pin will

remain in its last state.

FOSC

FCLOCK = -------------------------------------------------

SSPxADD + 14

An internal signal “Reload” in Figure 21-40 triggers the

value from SSPxADD to be loaded into the BRG

counter. This occurs twice for each oscillation of the

FIGURE 21-40:

BAUD RATE GENERATOR BLOCK DIAGRAM

Rev. 10-000112A

7/30/2013

4

SSPxADD<7:0>

8

SSPM <3:0>

4

Reload

Control

SSPM <3:0>

SCLx

Reload

8

BRG Down Counter

FOSC/2

SSPxCLK

Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPxADD when used as a Baud Rate

Generator for I²C. This is an implementation

limitation.

TABLE 21-4: MSSP CLOCK RATE W/BRG

FCLOCK

(Two Rollovers of BRG)

FOSC

FCY

BRG Value

16 MHz

4 MHz

1 MHz

09h

0Ch

27h

09h

400 kHz

308 kHz

100 kHz

Note:

Refer to the I/O port electrical and timing specifications in Table 29-9 and Figure 29-7 to ensure the system

is designed to support the I/O timing requirements.

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21.8 Register Definitions: MSSP Control

REGISTER 21-1: SSPxSTAT: SSP STATUS REGISTER

R/W-0/0

SMP

R/W-0/0

CKE

R-0/0

D/A

R-0/0

P

R-0/0

S

R-0/0

R/W

R-0/0

UA

R-0/0

BF

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

SMP: SPI Data Input Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

2

In I C Master or Slave mode:

1 = Slew rate control disabled

0 = Slew rate control enabled

bit 6

CKE: SPI Clock Edge Select bit (SPI mode only)

In SPI Master or Slave mode:

1= Transmit occurs on transition from active to Idle clock state

0= Transmit occurs on transition from Idle to active clock state

2

In I C™ mode only:

1= Enable input logic so that thresholds are compliant with SMBus specification

0= Disable SMBus specific inputs

2

bit 5

bit 4

D/A: Data/Address bit (I C mode only)

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

P: Stop bit

2

(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

bit 3

bit 2

S: Start bit

2

(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

2

R/W: Read/Write bit information (I C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match

to the next Start bit, Stop bit, or not ACK bit.

2

In I C Slave mode:

1= Read

0= Write

2

In I C Master mode:

1= Transmit is in progress

0= Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.

2

bit 1

bit 0

UA: Update Address bit (10-bit I C mode only)

1= Indicates that the user needs to update the address in the SSPxADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

2

Receive (SPI and I C modes):

1= Receive complete, SSPxBUF is full

0= Receive not complete, SSPxBUF is empty

2

Transmit (I C mode only):

1= Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full

0= Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty

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REGISTER 21-2: SSPxCON1: SSP CONTROL REGISTER 1

R/C/HS-0/0

WCOL

R/C/HS-0/0

SSPOV⁽¹⁾

R/W-0/0

SSPEN

R/W-0/0

CKP

R/W-0/0

SSPM<3:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Bit is set by hardware C = User cleared

bit 7

WCOL: Write Collision Detect bit

Master mode:

1= A write to the SSPxBUF register was attempted while the I²C conditions were not valid for a transmission to be started

0= No collision

Slave mode:

1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)

0= No collision

bit 6

SSPOV: Receive Overflow Indicator bit⁽¹⁾

In SPI mode:

1= A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.

Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid

setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the

SSPxBUF register (must be cleared in software).

0= No overflow

In I²C mode:

1= A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode

(must be cleared in software).

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output

In SPI mode:

1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins⁽²⁾

0= Disables serial port and configures these pins as I/O port pins

In I²C mode:

1= Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins⁽³⁾

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

1= Idle state for clock is a high level

0= Idle state for clock is a low level

In I²C Slave mode:

SCLx release control

1= Enable clock

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

In I²C Master mode:

Unused in this mode

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000= SPI Master mode, clock = FOSC/4

0001= SPI Master mode, clock = FOSC/16

0010= SPI Master mode, clock = FOSC/64

0011= SPI Master mode, clock = T2_match/2

0100= SPI Slave mode, clock = SCKx pin, SS pin control enabled

0101= SPI Slave mode, clock = SCKx pin, SS pin control disabled, SSx can be used as I/O pin

0110= I²C Slave mode, 7-bit address

0111= I²C Slave mode, 10-bit address

1000= I²C Master mode, clock = FOSC/(4 * (SSPxADD+1))⁽⁴⁾

1001= Reserved

1010= SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))⁽⁵⁾

1011= I²C firmware controlled Master mode (Slave idle)

1100= Reserved

1101= Reserved

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1:

In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.

When enabled, these pins must be properly configured as input or output.

When enabled, the SDAx and SCLx pins must be configured as inputs.

SSPxADD values of 0, 1 or 2 are not supported for I²C mode.

2:

3:

4:

5:

SSPxADD value of ‘0’ is not supported. Use SSPM = 0000instead.

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REGISTER 21-3: SSPxCON2: SSP CONTROL REGISTER 2⁽¹⁾

R/W-0/0

GCEN

R-0/0

R/W-0/0

ACKDT

R/S/HS-0/0 R/S/HS-0/0

ACKEN RCEN

R/S/HS-0/0

PEN

R/S/HS-0/0 R/W/HS-0/0

RSEN SEN

bit 0

ACKSTAT

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Cleared by hardware S = User set

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (in I²C Slave mode only)

1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (in I²C mode only)

1= Acknowledge was not received

0= Acknowledge was received

ACKDT: Acknowledge Data bit (in I²C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1= Not Acknowledge

0= Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (in I²C Master mode only)

In Master Receive mode:

1= Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence idle

bit 3

bit 2

RCEN: Receive Enable bit (in I²C Master mode only)

1= Enables Receive mode for I²C

0= Receive idle

PEN: Stop Condition Enable bit (in I²C Master mode only)

SCKx Release Control:

1= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.

0= Stop condition idle

bit 1

bit 0

RSEN: Repeated Start Condition Enable bit (in I²C Master mode only)

1= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0= Repeated Start condition idle

SEN: Start Condition Enable/Stretch Enable bit

In Master mode:

1= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0= Start condition idle

In Slave mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0= Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the Idle mode, this bit may not be

set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).

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REGISTER 21-4: SSPxCON3: SSP CONTROL REGISTER 3

R-0/0

ACKTIM⁽³⁾

R/W-0/0

PCIE

R/W-0/0

SCIE

R/W-0/0

BOEN

R/W-0/0

SDAHT

R/W-0/0

SBCDE

R/W-0/0

AHEN

R/W-0/0

DHEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

ACKTIM: Acknowledge Time Status bit (I²C mode only)⁽³⁾

1= Indicates the I²C bus is in an Acknowledge sequence, set on eighth falling edge of SCLx clock

0= Not an Acknowledge sequence, cleared on ninth rising edge of SCLx clock

PCIE: Stop Condition Interrupt Enable bit (I²C mode only)

1= Enable interrupt on detection of Stop condition

0= Stop detection interrupts are disabled⁽²⁾

SCIE: Start Condition Interrupt Enable bit (I²C mode only)

1= Enable interrupt on detection of Start or Restart conditions

0= Start detection interrupts are disabled⁽²⁾

BOEN: Buffer Overwrite Enable bit

In SPI Slave mode:⁽¹⁾

1= SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit

0= If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the

SSPxCON1 register is set, and the buffer is not updated

In I²C Master mode:

This bit is ignored.

In I²C Slave mode:

1= SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the

state of the SSPOV bit only if the BF bit = 0.

0= SSPxBUF is only updated when SSPOV is clear

bit 3

bit 2

SDAHT: SDAx Hold Time Selection bit (I²C mode only)

1= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx

0= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx

SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)

If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the

BCLxIF bit of the PIR2 register is set, and bus goes idle

1= Enable slave bus collision interrupts

0= Slave bus collision interrupts are disabled

bit 1

bit 0

AHEN: Address Hold Enable bit (I²C Slave mode only)

1= Following the eighth falling edge of SCLx for a matching received address byte, CKP bit of the

SSPxCON1 register will be cleared and the SCLx will be held low.

0= Address holding is disabled

DHEN: Data Hold Enable bit (I²C Slave mode only)

1= Following the eighth falling edge of SCLx for a received data byte, slave hardware clears the CKP

bit of the SSPxCON1 register and SCLx is held low.

0= Data holding is disabled

Note 1: For daisy-chained SPI operation, allows the user to ignore all but the last received byte. SSPOV is still set

when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.

2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

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REGISTER 21-5: SSPxMSK: SSP MASK REGISTER

R/W-1/1

MSK<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-1

bit 0

MSK<7:1>: Mask bits

1= The received address bit n is compared to SSPxADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK<0>: Mask bit for I²C Slave mode, 10-bit Address

I²C Slave mode, 10-bit address (SSPM<3:0> = 0111or 1111):

1= The received address bit 0 is compared to SSPxADD<0> to detect I²C address match

0= The received address bit 0 is not used to detect I²C address match

I²C Slave mode, 7-bit address, the bit is ignored

REGISTER 21-6: SSPxADD: MSSP ADDRESS AND BAUD RATE REGISTER (I²C MODE)

R/W-0/0

ADD<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

Master mode:

bit 7-0

ADD<7:0>: Baud Rate Clock Divider bits

SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC

10-Bit Slave mode – Most Significant Address Byte:

bit 7-3

Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit pat-

tern sent by master is fixed by I²C specification and must be equal to ‘11110’. However, those bits are

compared by hardware and are not affected by the value in this register.

bit 2-1

bit 0

ADD<2:1>: Two Most Significant bits of 10-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

10-Bit Slave mode – Least Significant Address Byte:

bit 7-0

ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1

bit 0

ADD<7:1>: 7-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

DS40001609E-page 222

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PIC16(L)F1508/9

The EUSART module includes the following capabilities:

22.0 ENHANCED UNIVERSAL

SYNCHRONOUS

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in synchronous

modes

• Sleep operation

system.

Full-Duplex

mode

is

useful

for

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 22-1 and Figure 22-2.

The EUSART transmit output (TX_out) is available to

the TX/CK pin and internally to the following peripherals:

• Configurable Logic Cell (CLC)

FIGURE 22-1:

EUSART TRANSMIT BLOCK DIAGRAM

Rev. 10-000113A

10/14/2013

Data bus

TXIE

TXIF

8

Interrupt

TXREG register

8

MSb

(8)

LSb

0

TX/CK

Pin Buffer

and Control

Transmit Shift Register (TSR)

TX_out

TXEN

TRMT

Baud Rate Generator

FOSC

÷ n

TX9

n

BRG16

TX9D

+ 1

Multiplier

SYNC

x4

x16 x64

1

x

1

0

1

0

1

0

BRGH

x

SPBRGH SPBRGL

BRG16

 2011-2015 Microchip Technology Inc.

DS40001609E-page 223

PIC16(L)F1508/9

FIGURE 22-2:

EUSART RECEIVE BLOCK DIAGRAM

Rev. 10-000114A

7/30/2013

CREN

OERR

RCIDL

SPEN

RSR Register

MSb

LSb

RX/DT pin

Pin Buffer

and Control

Data

Recovery

Stop (8)

7

1

0

Start

Baud Rate Generator

FOSC

÷ n

RX9

BRG16

n

+ 1

Multiplier

SYNC

x4

x16 x64

1

x

1

0

1

0

1

0

BRGH

x

SPBRGH SPBRGL

FIFO

BRG16

FERR

RX9D

RCREG Register

8

Data Bus

RCIF

RCIE

Interrupt

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These registers are detailed in Register 22-1,

Register 22-2 and Register 22-3, respectively.

When the receiver or transmitter section is not enabled

then the corresponding RX or TX pin may be used for

general purpose input and output.

DS40001609E-page 224

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PIC16(L)F1508/9

22.1.1.2

Transmitting Data

22.1 EUSART Asynchronous Mode

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is eight bits. Each transmitted bit persists for a

period of 1/(Baud Rate). An on-chip dedicated

8-bit/16-bit Baud Rate Generator is used to derive

standard baud rate frequencies from the system

oscillator. See Table 22-5 for examples of baud rate

configurations.

22.1.1.3

Transmit Data Polarity

The polarity of the transmit data can be controlled with

the SCKP bit of the BAUDCON register. The default

state of this bit is ‘0’ which selects high true transmit idle

and data bits. Setting the SCKP bit to ‘1’ will invert the

transmit data resulting in low true idle and data bits. The

SCKP bit controls transmit data polarity in

Asynchronous mode only. In Synchronous mode, the

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

SCKP

bit

has

a

different

function.

See

Section22.5.1.2 “Clock Polarity”.

22.1.1.4

Transmit Interrupt Flag

22.1.1

EUSART ASYNCHRONOUS

TRANSMITTER

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execution. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

The EUSART transmitter block diagram is shown in

Figure 22-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

22.1.1.1

Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

• TXEN = 1

• SYNC = 0

• SPEN = 1

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

All other EUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART and automatically

configures the TX/CK I/O pin as an output. If the TX/CK

pin is shared with an analog peripheral, the analog I/O

function must be disabled by clearing the corresponding

ANSEL bit.

Note:

The TXIF Transmitter Interrupt flag is set

when the TXEN enable bit is set.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 225

PIC16(L)F1508/9

22.1.1.5

TSR Status

22.1.1.7

Asynchronous Transmission Set-up:

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

1. Initialize the SPBRGH, SPBRGL register pair and

the BRGH and BRG16 bits to achieve the desired

baud rate (see Section22.4 “EUSART Baud

Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9 con-

trol bit. A set ninth data bit will indicate that the

eight Least Significant data bits are an address

when the receiver is set for address detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

4. Set SCKP bit if inverted transmit is desired.

22.1.1.6

Transmitting 9-Bit Characters

5. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set, the

EUSART will shift nine bits out for each character trans-

mitted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the eight Least Significant bits into the TXREG. All nine

bits of data will be transferred to the TSR shift register

immediately after the TXREG is written.

6. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

7. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

8. Load 8-bit data into the TXREG register. This

will start the transmission.

A special 9-bit Address mode is available for use with

multiple receivers. See Section22.1.2.7 “Address

Detection” for more information on the address mode.

FIGURE 22-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 22-4:

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

1 TCY

Word 1

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 2

Transmit Shift Reg.

Note:

This timing diagram shows two consecutive transmissions.

DS40001609E-page 226

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PIC16(L)F1508/9

TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

BAUDCON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

RX9

—

SCKP

INTE

TXIE

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

235

75

TMR0IE

RCIE

TMR1GIE

TMR1GIF

SPEN

SSP1IE

SSP1IF

ADDEN

TMR2IE TMR1IE

TMR2IF TMR1IF

76

PIR1

RCIF

TXIF

—

79

RCSTA

SPBRGL

SPBRGH

TRISB

SREN

CREN

FERR

OERR

RX9D

234*

236*

113

225

233

BRG<7:0>

BRG<15:8>

TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

TRISB7

TXREG

TXSTA

EUSART Transmit Data Register

CSRC TX9 TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.

Page provides register information.

*

 2011-2015 Microchip Technology Inc.

DS40001609E-page 227

PIC16(L)F1508/9

22.1.2

EUSART ASYNCHRONOUS

RECEIVER

22.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section22.1.2.4 “Receive Framing

Error” for more information on framing errors.

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 22-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all eight

or nine bits of the character have been shifted in, they

are immediately transferred to

a two character

First-In-First-Out (FIFO) memory. The FIFO buffering

allows reception of two complete characters and the

start of a third character before software must start

servicing the EUSART receiver. The FIFO and RSR

registers are not directly accessible by software.

Access to the received data is via the RCREG register.

22.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART. The programmer

must set the corresponding TRIS bit to configure the

RX/DT I/O pin as an input.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition

is

cleared.

See

Section22.1.2.5 “Receive

Overrun

Error” for more information on overrun

errors.

22.1.2.3

Receive Interrupts

Note:

If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE, Interrupt Enable bit of the PIE1 register

• PEIE, Peripheral Interrupt Enable bit of the

INTCON register

• GIE, Global Interrupt Enable bit of the INTCON

register

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

DS40001609E-page 228

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PIC16(L)F1508/9

22.1.2.4

Receive Framing Error

22.1.2.7

Address Detection

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

register.

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit. All other characters will be ignored.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the EUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

22.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTA register.

22.1.2.6

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 229

PIC16(L)F1508/9

22.1.2.8

Asynchronous Reception Set-up:

22.1.2.9

9-bit Address Detection Mode Set-up

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section22.4 “EUSART

Baud Rate Generator (BRG)”).

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section22.4 “EUSART

Baud Rate Generator (BRG)”).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

2. Clear the ANSEL bit for the RX pin (if applicable).

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

5. If 9-bit reception is desired, set the RX9 bit.

6. Enable reception by setting the CREN bit.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

5. Enable 9-bit reception by setting the RX9 bit.

6. Enable address detection by setting the ADDEN

bit.

8. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

7. Enable reception by setting the CREN bit.

8. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

9. Get the received eight Least Significant data bits

from the receive buffer by reading the RCREG

register.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

9. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received eight Least Significant data bits

from the receive buffer by reading the RCREG

register. Software determines if this is the

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 22-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg.

Word 2

RCREG

Word 1

RCREG

RCIDL

Read Rcv

Buffer Reg.

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

DS40001609E-page 230

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PIC16(L)F1508/9

TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

BAUDCON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

—

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

235

75

TMR0IE

RCIE

TMR1GIE

TMR1GIF

SSP1IE

SSP1IF

TMR2IE TMR1IE

TMR2IF TMR1IF

76

PIR1

RCIF

—

79

RCREG

RCSTA

SPBRGL

SPBRGH

TRISB

EUSART Receive Data Register

SREN CREN ADDEN FERR

BRG<7:0>

BRG<15:8>

TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

TX9 TXEN SYNC SENDB BRGH TRMT TX9D

228*

234*

236*

113

233

SPEN

RX9

OERR

RX9D

TRISB7

CSRC

TXSTA

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.

Page provides register information.

*

 2011-2015 Microchip Technology Inc.

DS40001609E-page 231

PIC16(L)F1508/9

22.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block out-

put (INTOSC). However, the INTOSC frequency may

drift as VDD or temperature changes, and this directly

affects the asynchronous baud rate.

The

Auto-Baud

Detect

feature

(see

Section22.4.1 “Auto-Baud Detect”) can be used to

compensate for changes in the INTOSC frequency.

There may not be fine enough resolution when

adjusting the Baud Rate Generator to compensate for

a gradual change in the peripheral clock frequency.

DS40001609E-page 232

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PIC16(L)F1508/9

22.3 Register Definitions: EUSART Control

REGISTER 22-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-/0

CSRC

R/W-0/0

TX9

R/W-0/0

TXEN⁽¹⁾

R/W-0/0

SYNC

R/W-0/0

SENDB

R/W-0/0

BRGH

R-1/1

R/W-0/0

TX9D

TRMT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

bit 3

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit⁽¹⁾

1= Transmit enabled

0= Transmit disabled

SYNC: EUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send Sync Break on next transmission (cleared by hardware upon completion)

0= Sync Break transmission completed

Synchronous mode:

Don’t care

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 233

PIC16(L)F1508/9

REGISTER 22-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0/0

SPEN

R/W-0/0

RX9

R/W-0/0

SREN

R/W-0/0

CREN

R/W-0/0

ADDEN

R-0/0

RX9D

FERR

OERR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

DS40001609E-page 234

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

REGISTER 22-3: BAUDCON: BAUD RATE CONTROL REGISTER

R-0/0

R-1/1

U-0

—

R/W-0/0

SCKP

R/W-0/0

BRG16

U-0

—

R/W-0/0

WUE

R/W-0/0

ABDEN

ABDOVF

RCIDL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1= Auto-baud timer overflowed

0= Auto-baud timer did not overflow

Synchronous mode:

Don’t care

RCIDL: Receive Idle Flag bit

Asynchronous mode:

1= Receiver is idle

0= Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5

bit 4

Unimplemented: Read as ‘0’

SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:

1= Transmit inverted data to the TX/CK pin

0= Transmit non-inverted data to the TX/CK pin

Synchronous mode:

1= Data is clocked on rising edge of the clock

0= Data is clocked on falling edge of the clock

bit 3

BRG16: 16-bit Baud Rate Generator bit

1= 16-bit Baud Rate Generator is used

0= 8-bit Baud Rate Generator is used

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= Receiver is waiting for a falling edge. No character will be received, RCIF bit will be set. WUE will

automatically clear after RCIF is set.

0= Receiver is operating normally

Synchronous mode:

Don’t care

bit 0

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0= Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

 2011-2015 Microchip Technology Inc.

DS40001609E-page 235

PIC16(L)F1508/9

EXAMPLE 22-1:

CALCULATING BAUD

RATE ERROR

22.4 EUSART Baud Rate Generator

(BRG)

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDCON register selects 16-bit

mode.

FOSC

Desired Baud Rate = -----------------------------------------------------------------------

64[SPBRGH:SPBRGL] + 1

Solving for SPBRGH:SPBRGL:

FOSC

---------------------------------------------

Desired Baud Rate

X = --------------------------------------------- – 1

64

The SPBRGH, SPBRGL register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXSTA

register and the BRG16 bit of the BAUDCON register. In

Synchronous mode, the BRGH bit is ignored.

16000000

-----------------------

9600

= ----------------------- – 1

64

= 25.042 = 25

Table 22-3 contains the formulas for determining the

baud rate. Example 22-1 provides a sample calculation

for determining the baud rate and baud rate error.

16000000

Calculated Baud Rate = --------------------------

6425 + 1

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 22-3. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

= 9615

Calc. Baud Rate – Desired Baud Rate

Error = --------------------------------------------------------------------------------------------

Desired Baud Rate

9615 – 9600

= ---------------------------------- = 0 . 1 6 %

9600

Writing a new value to the SPBRGH, SPBRGL register

pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow

before outputting the new baud rate.

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is idle before

changing the system clock.

DS40001609E-page 236

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 22-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

BRG/EUSART Mode

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend:

x= Don’t care, n = value of SPBRGH, SPBRGL register pair.

TABLE 22-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

RCSTA

ABDOVF RCIDL

—

SCKP

CREN

BRG16

ADDEN

—

WUE

ABDEN

RX9D

235

234

SPEN

CSRC

RX9

SREN

FERR

OERR

SPBRGL

SPBRGH

TXSTA

BRG<7:0>

BRG<15:8>

SYNC SENDB

236*

233

TX9

TXEN

BRGH

TRMT

TX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

Page provides register information.

*

 2011-2015 Microchip Technology Inc.

DS40001609E-page 237

PIC16(L)F1508/9

TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 16.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

—

255

129

32

—

239

119

29

—

207

103

25

—

143

71

17

16

8

1221

2404

9470

10417

19.53k

1.73

0.16

-1.36

0.00

1.73

1200

2400

9600

10286

19.20k

0.00

-1.26

0.00

—

1202

2404

9615

10417

19.23k

0.16

0.00

0.16

—

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

9600

10417

19.2k

57.6k

115.2k

29

27

23

15

14

12

2

—

57.60k

—

7

—

57.60k

—

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

0.00

—

300

1200

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

300

1200

2400

9600

—

191

47

23

5

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

10417

—

0.00

—

2

—

19.20k

0.00

—

0

—

57.60k

—

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 18.432 MHz FOSC = 16.000 MHz

FOSC = 20.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

2400

9600

10417

19.2k

57.6k

—

71

65

35

11

5

9615

10417

19.23k

56.82k

0.16

0.00

0.16

-1.36

129

119

64

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

119

110

59

19

9

9615

10417

19.23k

58.82k

111.1k

0.16

0.00

0.16

2.12

-3.55

103

95

51

16

8

9600

0.00

0.53

0.00

10473

19.20k

57.60k

115.2k

21

115.2k 113.64k -1.36

10

DS40001609E-page 238

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

191

95

23

21

11

3

300

1202

2404

—

0.16

—

207

51

25

—

5

0.16

0.00

0.16

—

1200

0.00

0.53

0.00

2400

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 18.432 MHz FOSC = 16.000 MHz

FOSC = 20.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

2400

9600

10417

19.2k

57.6k

300.0

1200

-0.01

-0.03

0.16

0.00

0.16

-1.36

4166

1041

520

129

119

64

300.0

1200

0.00

-0.37

0.00

3839

959

479

119

110

59

300.03

1200.5

2398

0.01

0.04

-0.08

0.16

0.00

0.16

2.12

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

2303

575

287

71

2399

2400

9615

9600

9615

9600

10417

19.23k

56.818

10378

19.20k

57.60k

115.2k

10417

19.23k

58.82k

10473

19.20k

57.60k

115.2k

65

51

35

21

19

16

11

115.2k 113.636 -1.36

10

9

111.11k -3.55

8

5

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

Error

(decimal)

300

1200

299.9

1199

-0.02

-0.08

0.16

0.00

0.16

-3.55

—

1666

416

207

51

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

300.0

1200

0.00

0.53

0.00

767

191

95

23

21

11

3

300.5

1202

2404

—

0.16

—

207

51

25

—

5

2400

2404

9615

10417

19.23k

55556

—

2400

9600

10417

19.2k

57.6k

115.2k

47

23

10473

19.20k

57.60k

115.2k

10417

—

0.00

—

25

12

—

8

—

1

—

 2011-2015 Microchip Technology Inc.

DS40001609E-page 239

PIC16(L)F1508/9

TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 16.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.01

0.02

-0.03

0.00

0.16

-0.22

0.94

16665

4166

2082

520

479

259

86

300.0

1200

0.00

0.08

0.00

15359

3839

1919

479

441

239

79

300.0

1200.1

2399.5

9592

0.00

0.01

-0.02

-0.08

0.00

0.16

0.64

13332

3332

1666

416

383

207

68

300.0

1200

0.00

0.16

0.00

9215

2303

1151

287

264

143

47

2400

9600

9597

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.47k

116.3k

10425

19.20k

57.60k

115.2k

10417

19.23k

57.97k

10433

19.20k

57.60k

115.2k

42

39

114.29k -0.79

34

23

SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.02

0.04

0.16

0

6666

1666

832

207

191

103

34

300.0

1200

0.01

0.04

0.08

0.16

0.00

0.16

2.12

-3.55

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

3071

767

383

95

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

2400

2401

2398

2400

9600

9615

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.14k

117.6k

10417

19.23k

58.82k

111.1k

10473

19.20k

57.60k

115.2k

87

23

0.16

-0.79

2.12

51

47

12

16

15

—

16

8

7

—

DS40001609E-page 240

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

and SPBRGL registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the

average bit time when clocked at full speed.

22.4.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

Section22.4.3 “Auto-Wake-up

on

Break”).

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

Setting the ABDEN bit of the BAUDCON register starts

the auto-baud calibration sequence (Figure 22-6).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Table 22-6. The fifth rising edge will occur on the RX pin

at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPBRGH, SPBRGL register pair, the ABDEN

bit is automatically cleared and the RCIF interrupt flag

is set. The value in the RCREG needs to be read to

clear the RCIF interrupt. RCREG content should be

discarded. When calibrating for modes that do not use

the SPBRGH register the user can verify that the

SPBRGL register did not overflow by checking for 00h

in the SPBRGH register.

3: During the auto-baud process, the

auto-baud counter starts counting at 1.

Upon completion of the auto-baud

sequence, to achieve maximum accuracy,

subtract 1 from the SPBRGH:SPBRGL

register pair.

TABLE 22-6:

BRG16 BRGH

BRG COUNTER CLOCK RATES

BRG Base

Clock

BRG ABD

Clock

0

1

FOSC/64

FOSC/16

FOSC/512

FOSC/128

1

0

1

FOSC/16

FOSC/4

FOSC/128

FOSC/32

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 22-6. During ABD,

both the SPBRGH and SPBRGL registers are used as

a 16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

Note:

During the ABD sequence, SPBRGL and

SPBRGH registers are both used as a 16-bit

counter, independent of BRG16 setting.

FIGURE 22-6:

AUTOMATIC BAUD RATE CALIBRATION

XXXXh

0000h

001Ch

BRG Value

Edge #1

bit 1

Edge #2

bit 3

Edge #3

bit 5

bit 4

Edge #4

bit 7

Edge #5

Stop bit

RX pin

Start

bit 0

bit 2

bit 6

BRG Clock

Auto Cleared

Set by User

ABDEN bit

RCIDL

RCIF bit

(Interrupt)

Read

RCREG

XXh

1Ch

00h

SPBRGL

SPBRGH

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 241

PIC16(L)F1508/9

22.4.2

AUTO-BAUD OVERFLOW

22.4.3.1

Special Considerations

During the course of automatic baud detection, the

ABDOVF bit of the BAUDxCON register will be set if the

baud rate counter overflows before the fifth rising edge

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in the 16 bits of the SPxBRGH:SPxBRGL

register pair. The overflow condition will set the RCIF

flag. The counter continues to count until the fifth rising

edge is detected on the RX pin. The RCIDL bit will

remain false ('0') until the fifth rising edge, at which time,

the RCIDL bit will be set. If the RCREG is read after the

overflow occurs, but before the fifth rising edge, then

the fifth rising edge will set the RCIF again.

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be ten or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

Terminating the auto-baud process early to clear an

overflow condition will prevent proper detection of the

sync character fifth rising edge. If any falling edges of

the sync character have not yet occurred when the

ABDEN bit is cleared, then those will be falsely detected

as start bits. The following steps are recommended to

clear the overflow condition:

Oscillator Start-up Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the EUSART.

1. Read RCREG to clear RCIF.

2. If RCIDL is zero, then wait for RCIF and repeat step 1.

3. Clear the ABDOVF bit.

22.4.3

AUTO-WAKE-UP ON BREAK

WUE Bit

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared in software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCON register. Once set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a

wake-up event independent of the CPU mode. A

wake-up event consists of a high-to-low transition on the

RX/DT line. (This coincides with the start of a Sync Break

or a wake-up signal character for the LIN protocol.)

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 22-7), and asynchronously if

the device is in Sleep mode (Figure 22-8). The interrupt

condition is cleared by reading the RCREG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

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PIC16(L)F1508/9

FIGURE 22-7:

AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4

OSC1

Auto Cleared

Bit set by user

WUE bit

RX/DT Line

RCIF

Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 22-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q4

Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3

Q1

Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4

Auto Cleared

OSC1

Bit Set by User

WUE bit

RX/DT Line

Note 1

RCIF

Cleared due to User Read of RCREG

Sleep Command Executed

Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

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22.4.4

BREAK CHARACTER SEQUENCE

22.4.5

RECEIVING A BREAK CHARACTER

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘0’ bits and a Stop bit.

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCSTA register and the received data

as indicated by RCREG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

To send a Break character, set the SENDB and TXEN

bits of the TXSTA register. The Break character trans-

mission is then initiated by a write to the TXREG. The

value of data written to TXREG will be ignored and all

‘0’s will be transmitted.

A Break character has been received when;

• RCIF bit is set

• FERR bit is set

• RCREG = 00h

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

The second method uses the Auto-Wake-up feature

described in Section22.4.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RCIF interrupt, and receive the next data byte followed

by another interrupt.

The TRMT bit of the TXSTA register indicates when the

transmit operation is active or idle, just as it does during

normal transmission. See Figure 22-9 for the timing of

the Break character sequence.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCON register before placing the EUSART in

Sleep mode.

22.4.4.1

Break and Sync Transmit Sequence

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

FIGURE 22-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

Dummy Write

BRG Output

(Shift Clock)

TX (pin)

Start bit

bit 0

bit 1

Break

bit 11

Stop bit

TXIF bit

(Transmit

Interrupt Flag)

TRMT bit

(Transmit Shift

Empty Flag)

SENDB Sampled Here

Auto Cleared

SENDB

(send Break

control bit)

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Clearing the SCKP bit sets the Idle state as low. When

the SCKP bit is cleared, the data changes on the rising

edge of each clock.

22.5 EUSART Synchronous Mode

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary cir-

cuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the inter-

nal clock generation circuitry.

22.5.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the EUSART is configured for syn-

chronous master transmit operation.

There are two signal lines in Synchronous mode: a bidi-

rectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The EUSART can operate as either a master or slave

device.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character the new character data is held in the

TXREG until the last bit of the previous character has

been transmitted. If this is the first character, or the pre-

vious character has been completely flushed from the

TSR, the data in the TXREG is immediately transferred

to the TSR. The transmission of the character com-

mences immediately following the transfer of the data

to the TSR from the TXREG.

Start and Stop bits are not used in synchronous trans-

missions.

Each data bit changes on the leading edge of the mas-

ter clock and remains valid until the subsequent leading

clock edge.

22.5.1

SYNCHRONOUS MASTER MODE

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

The following bits are used to configure the EUSART

for synchronous master operation:

• SYNC = 1

22.5.1.4

Synchronous Master Transmission

Set-up:

• CSRC = 1

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section22.4 “EUSART

Baud Rate Generator (BRG)”).

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

22.5.1.1

Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin output driver is automatically enabled

when the EUSART is configured for synchronous

transmit or receive operation. Serial data bits change

on the leading edge to ensure they are valid at the trail-

ing edge of each clock. One clock cycle is generated

for each data bit. Only as many clock cycles are gener-

ated as there are data bits.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. Start transmission by loading data to the TXREG

register.

22.5.1.2

Clock Polarity

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP

bit of the BAUDCON register. Setting the SCKP bit sets

the clock Idle state as high. When the SCKP bit is set,

the data changes on the falling edge of each clock.

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PIC16(L)F1508/9

FIGURE 22-10:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.

FIGURE 22-11:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 22-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

RX9

—

SCKP

INTE

TXIE

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

235

75

TMR0IE

RCIE

TMR1GIE

TMR1GIF

SPEN

SSP1IE

SSP1IF

ADDEN

TMR2IE

TMR2IF

OERR

TMR1IE

TMR1IF

RX9D

76

PIR1

RCIF

TXIF

—

79

RCSTA

SPBRGL

SPBRGH

SREN

CREN

FERR

234

236*

113

225*

233

BRG<7:0>

BRG<15:8>

TRISB4 TRISB3

TRISB

TXREG

TXSTA

TRISB7

CSRC

TRISB6

TX9

TRISB5

TRISB2

TRISB1

TRMT

TRISB0

TX9D

EUSART Transmit Data Register

TXEN SYNC SENDB BRGH

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.

*

Page provides register information.

DS40001609E-page 246

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PIC16(L)F1508/9

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register or by clearing the

SPEN bit which resets the EUSART.

22.5.1.5

Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

EUSART is configured for synchronous master receive

operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

22.5.1.8

Receiving 9-bit Characters

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

22.5.1.9

Synchronous Master Reception

Set-up:

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

Register (RSR). When a complete character is

received into the RSR, the RCIF bit is set and the char-

acter is automatically transferred to the two character

receive FIFO. The Least Significant eight bits of the top

character in the receive FIFO are available in RCREG.

The RCIF bit remains set as long as there are unread

characters in the receive FIFO.

1. Initialize the SPBRGH, SPBRGL register pair for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

4. Ensure bits CREN and SREN are clear.

Note:

If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

5. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

6. If 9-bit reception is desired, set bit RX9.

22.5.1.6

Slave Clock

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The

TX/CK pin output driver is automatically disabled when

the device is configured for synchronous slave transmit

or receive operation. Serial data bits change on the

leading edge to ensure they are valid at the trailing edge

of each clock. One data bit is transferred for each clock

cycle. Only as many clock cycles should be received as

there are data bits.

8. Interrupt flag bit RCIF will be set when reception

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

Note:

If the device is configured as a slave and

the TX/CK function is on an analog pin, the

corresponding ANSEL bit must be

cleared.

22.5.1.7

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

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PIC16(L)F1508/9

FIGURE 22-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 22-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

—

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

235

75

TMR0IE

RCIE

TMR1GIE

TMR1GIF

SSP1IE

SSP1IF

TMR2IE TMR1IE

TMR2IF TMR1IF

76

PIR1

RCIF

—

79

RCREG

RCSTA

SPBRGL

SPBRGH

TRISB

EUSART Receive Data Register

SREN CREN ADDEN FERR

BRG<7:0>

BRG<15:8>

TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

TX9 TXEN SYNC SENDB BRGH TRMT TX9D

228*

234

236*

113

233

SPEN

RX9

OERR

RX9D

TRISB7

CSRC

TXSTA

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.

Page provides register information.

*

DS40001609E-page 248

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PIC16(L)F1508/9

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

22.5.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for synchronous slave operation:

1. The first character will immediately transfer to

the TSR register and transmit.

• SYNC = 1

2. The second word will remain in the TXREG

register.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

3. The TXIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

22.5.2.2

Synchronous Slave Transmission

Set-up:

22.5.2.1

EUSART Synchronous Slave

Transmit

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

The operation of the Synchronous Master and Slave

modes

Section22.5.1.3 “Synchronous

Transmission”), except in the case of the Sleep mode.

2. Clear the ANSEL bit for the CK pin (if applicable).

3. Clear the CREN and SREN bits.

are

identical

(see

Master

4. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant eight bits to the TXREG register.

TABLE 22-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

RX9

—

SCKP

INTE

TXIE

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

235

75

TMR0IE

RCIE

TMR1GIE

TMR1GIF

SSP1IE

SSP1IF

ADDEN

TMR2IE TMR1IE

TMR2IF TMR1IF

76

PIR1

RCIF

TXIF

—

79

SREN

CREN

FERR

OERR

RX9D

RCSTA

SPEN

234

113

225*

233

TRISB

TRISB7

TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

EUSART Transmit Data Register

TXREG

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

Page provides register information.

*

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DS40001609E-page 249

PIC16(L)F1508/9

22.5.2.3

EUSART Synchronous Slave

Reception

22.5.2.4

Synchronous Slave Reception

Set-up:

The operation of the Synchronous Master and Slave

modes is identical (Section22.5.1.5 “Synchronous

Master Reception”), with the following exceptions:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for both the CK and DT pins

(if applicable).

• Sleep

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

• CREN bit is always set, therefore the receiver is

never idle

• SREN bit, which is a “don’t care” in Slave mode

4. If 9-bit reception is desired, set the RX9 bit.

5. Set the CREN bit to enable reception.

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

6. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

8. Retrieve the eight Least Significant bits from the

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

TABLE 22-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

INTCON

PIE1

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

—

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

—

TMR0IF

—

WUE

INTF

ABDEN

IOCIF

235

75

TMR0IE

RCIE

TMR1GIE

TMR1GIF

SSP1IE

SSP1IF

TMR2IE TMR1IE

TMR2IF TMR1IF

76

PIR1

RCIF

—

79

RCREG

RCSTA

EUSART Receive Data Register

SREN CREN ADDEN FERR

228*

234

113

233

RX9

OERR

RX9D

SPEN

TRISB

TXSTA

TRISB7

CSRC

TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

TX9 TXEN SYNC SENDB BRGH TRMT TX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.

Page provides register information.

*

DS40001609E-page 250

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

Figure 23-1 shows a simplified block diagram of PWM

operation.

23.0 PULSE-WIDTH MODULATION

(PWM) MODULE

For a step-by-step procedure on how to set up this

module for PWM operation, refer to Section

23.1.9 “Setup for PWM Operation using PWMx

Pins”.

The PWM module generates a Pulse-Width Modulated

signal determined by the duty cycle, period, and reso-

lution that are configured by the following registers:

• PR2

• T2CON

• PWMxDCH

• PWMxDCL

• PWMxCON

FIGURE 23-1:

SIMPLIFIED PWM BLOCK DIAGRAM

Rev. 10-000022A

8/5/2013

PWMxDCL<7:6>

Duty cycle registers

PWMxDCH

PWMx_out

To Peripherals

10-bit Latch

(Not visible to user)

PWMxOE

R

S

Q

Comparator

0

1

PWMx

TMR2 Module

TRIS Control

PWMxPOL

R

(1)

TMR2

Comparator

PR2

T2_match

Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to

create 10-bit time-base.

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PIC16(L)F1508/9

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

23.1 PWMx Pin Configuration

All PWM outputs are multiplexed with the PORT data

latch. The user must configure the pins as outputs by

clearing the associated TRIS bits.

• TMR2 is cleared

• The PWM output is active. (Exception: When the

PWM duty cycle = 0%, the PWM output will

remain inactive.)

Note:

Clearing the PWMxOE bit will relinquish

control of the PWMx pin.

• The PWMxDCH and PWMxDCL register values

are latched into the buffers.

23.1.1

FUNDAMENTAL OPERATION

Note:

The Timer2 postscaler has no effect on

the PWM operation.

The PWM module produces a 10-bit resolution output.

Timer2 and PR2 set the period of the PWM. The

PWMxDCL and PWMxDCH registers configure the

duty cycle. The period is common to all PWM modules,

whereas the duty cycle is independently controlled.

23.1.4

PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to the PWMxDCH and PWMxDCL register pair.

The PWMxDCH register contains the eight MSbs and

the PWMxDCL<7:6>, the two LSbs. The PWMxDCH

and PWMxDCL registers can be written to at any time.

Note:

The Timer2 postscaler is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

Equation 23-2 is used to calculate the PWM pulse width.

Equation 23-3 is used to calculate the PWM duty cycle

ratio.

All PWM outputs associated with Timer2 are set when

TMR2 is cleared. Each PWMx is cleared when TMR2

is equal to the value specified in the corresponding

PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) reg-

isters. When the value is greater than or equal to PR2,

the PWM output is never cleared (100% duty cycle).

EQUATION 23-2: PULSE WIDTH

Pulse Width = PWMxDCH:PWMxDCL<7:6> 

Note:

The PWMxDCH and PWMxDCL registers

are double buffered. The buffers are

updated when Timer2 matches PR2. Care

should be taken to update both registers

before the timer match occurs.

TOSC  (TMR2 Prescale Value)

Note: TOSC = 1/FOSC

EQUATION 23-3: DUTY CYCLE RATIO

23.1.2

PWM OUTPUT POLARITY

PWMxDCH:PWMxDCL<7:6>

Duty Cycle Ratio = -----------------------------------------------------------------------------------

4PR2 + 1

The output polarity is inverted by setting the PWMxPOL

bit of the PWMxCON register.

23.1.3

PWM PERIOD

The 8-bit timer TMR2 register is concatenated with the

two Least Significant bits of 1/FOSC, adjusted by the

Timer2 prescaler to create the 10-bit time base. The

system clock is used if the Timer2 prescaler is set to 1:1.

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 23-1.

Figure 23-2 shows a waveform of the PWM signal when

the duty cycle is set for the smallest possible pulse.

EQUATION 23-1: PWM PERIOD

PWM Period = PR2 + 1  4  TOSC 

FIGURE 23-2:

PWM OUTPUT

(TMR2 Prescale Value)

Rev. 10-000023A

7/30/2013

Q1

Q2

Q3

Q4

Note:

TOSC = 1/FOSC

FOSC

Pulse Width

TMR2 = PR2

PWM

TMR2 = 0

TMR2 = PWMxDC

DS40001609E-page 252

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PIC16(L)F1508/9

23.1.5

PWM RESOLUTION

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolu-

tion will result in 1024 discrete duty cycles, whereas an

8-bit resolution will result in 256 discrete duty cycles.

The maximum PWM resolution is ten bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 23-4.

EQUATION 23-4: PWM RESOLUTION

log4PR2 + 1

Resolution = ----------------------------------------- bits

log2

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

TABLE 23-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

Timer Prescale

0.31 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

64

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

PR2 Value

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 23-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

Timer Prescale

0.31 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

64

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

PR2 Value

Maximum Resolution (bits)

23.1.6

OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the

PWMx pin is driving a value, it will continue to drive that

value. When the device wakes up, TMR2 will continue

from its previous state.

23.1.7

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency (FOSC). Any changes in the system clock

frequency will result in changes to the PWM frequency.

Refer to Section 5.0 “Oscillator Module (With

Fail-Safe Clock Monitor)” for additional details.

23.1.8

EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

PWM registers to their Reset states.

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PIC16(L)F1508/9

23.1.9

SETUP FOR PWM OPERATION

USING PWMx PINS

The following steps should be taken when configuring

the module for PWM operation using the PWMx pins:

1. Disable the PWMx pin output driver(s) by setting

the associated TRIS bit(s).

2. Clear the PWMxCON register.

3. Load the PR2 register with the PWM period

value.

4. Clear the PWMxDCH register and bits <7:6> of

the PWMxDCL register.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the

PIR1 register. See note below.

• Configure the T2CKPS bits of the T2CON

register with the Timer2 prescale value.

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Enable PWM output pin and wait until Timer2

overflows, TMR2IF bit of the PIR1 register is set.

See note below.

7. Enable the PWMx pin output driver(s) by clear-

ing the associated TRIS bit(s) and setting the

PWMxOE bit of the PWMxCON register.

8. Configure the PWM module by loading the

PWMxCON register with the appropriate values.

Note 1: In order to send a complete duty cycle

and period on the first PWM output, the

above steps must be followed in the order

given. If it is not critical to start with a

complete PWM signal, then move Step 8

to replace Step 4.

2: For operation with other peripherals only,

disable PWMx pin outputs.

DS40001609E-page 254

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23.2 Register Definitions: PWM Control

REGISTER 23-1: PWMxCON: PWM CONTROL REGISTER

R/W-0/0

R-0/0

R/W-0/0

U-0

—

U-0

—

U-0

—

U-0

—

PWMxEN

PWMxOE

PWMxOUT PWMxPOL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

PWMxEN: PWM Module Enable bit

1= PWM module is enabled

0= PWM module is disabled

PWMxOE: PWM Module Output Enable bit

1= Output to PWMx pin is enabled

0= Output to PWMx pin is disabled

bit 5

bit 4

PWMxOUT: PWM Module Output Value bit

PWMxPOL: PWMx Output Polarity Select bit

1= PWM output is active-low

0= PWM output is active-high

bit 3-0

Unimplemented: Read as ‘0’

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DS40001609E-page 255

PIC16(L)F1508/9

REGISTER 23-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS

R/W-x/u

PWMxDCH<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-0

PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.

REGISTER 23-3: PWMxDCL: PWM DUTY CYCLE LOW BITS

R/W-x/u

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

PWMxDCL<7:6>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.

Unimplemented: Read as ‘0’

TABLE 23-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PR2

Timer2 module Period Register

166*

255

256

255

256

255

256

255

256

168

166*

109

117

PWM1CON

PWM1DCH

PWM1DCL

PWM2CON

PWM2DCH

PWM2DCL

PWM3CON

PWM3DCH

PWM3DCL

PWM4CON

PWM4DCH

PWM4DCL

T2CON

PWM1EN

PWM1OE

PWM1OUT

PWM1POL

—

PWM1DCH<7:0>

PWM1DCL<7:6>

—

PWM2EN

PWM2OE

PWM2OUT

PWM2POL

PWM2DCH<7:0>

PWM2DCL<7:6>

—

PWM3EN

PWM3OE

PWM4OE

PWM3OUT

PWM3POL

PWM3DCH<7:0>

PWM3DCL<7:6>

—

PWM4EN

PWM4OUT

PWM4POL

PWM4DCH<7:0>

PWM4DCL<7:6>

—

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

TMR2

Timer2 module Register

—(1)

TRISA

—

TRISA5

TRISC5

TRISA4

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

TRISC

TRISC7

TRISC6

TRISC4

TRISC3

Legend:

*

-= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.

Page provides register information.

Note 1:

Unimplemented, read as ‘1’.

DS40001609E-page 256

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

Refer to Figure 24-1 for a simplified diagram showing

signal flow through the CLCx.

24.0 CONFIGURABLE LOGIC CELL

(CLC)

Possible configurations include:

The Configurable Logic Cell (CLCx) provides program-

mable logic that operates outside the speed limitations

of software execution. The logic cell takes up to 16

input signals, and through the use of configurable

gates, reduces the 16 inputs to four logic lines that drive

one of eight selectable single-output logic functions.

•

Combinatorial Logic

- AND

- NAND

- AND-OR

- AND-OR-INVERT

- OR-XOR

Input sources are a combination of the following:

• I/O pins

- OR-XNOR

• Internal clocks

• Peripherals

• Register bits

• Latches

- S-R

- Clocked D with Set and Reset

- Transparent D with Set and Reset

- Clocked J-K with Reset

The output can be directed internally to peripherals and

to an output pin.

FIGURE 24-1:

CONFIGURABLE LOGIC CELL BLOCK DIAGRAM

Rev. 10-000025A

8/1/2013

LCxOUT

MLCxOUT

D

Q

Q1

LCx_in[0]

LCx_in[1]

LCx_in[2]

LCx_in[3]

LCx_in[4]

LCx_in[5]

LCx_in[6]

LCx_in[7]

LCx_in[8]

LCx_in[9]

LCx_in[10]

LCx_in[11]

LCx_in[12]

LCx_in[13]

LCx_in[14]

LCx_in[15]

to Peripherals

LCxOE

LCxEN

lcxq

lcxg1

lcxg2

lcxg3

lcxg4

TRIS Control

Logic

LCx_out

Function

CLCx

(2)

LCxPOL

LCxMODE<2:0>

Interrupt

det

LCXINTP

LCXINTN

set bit

CLCxIF

Interrupt

det

Note 1: See Figure 24-2.

2: See Figure 24-3.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 257

PIC16(L)F1508/9

each case, paired with a different group. This arrange-

ment makes possible selection of up to two from a

group without precluding a selection from another

group.

24.1 CLCx Setup

Programming the CLCx module is performed by config-

uring the four stages in the logic signal flow. The four

stages are:

Data selection is through four multiplexers as indicated

on the left side of Figure 24-2. Data inputs in the figure

are identified by a generic numbered input name.

• Data selection

• Data gating

• Logic function selection

• Output polarity

Table 24-1 correlates the generic input name to the

actual signal for each CLC module. The columns labeled

lcxd1 through lcxd4 indicate the MUX output for the

selected data input. D1S through D4S are abbreviations

for the MUX select input codes: LCxD1S<2:0> through

LCxD4S<2:0>, respectively. Selecting a data input in a

column excludes all other inputs in that column.

Each stage is setup at run time by writing to the corre-

sponding CLCx Special Function Registers. This has

the added advantage of permitting logic reconfiguration

on-the-fly during program execution.

24.1.1

DATA SELECTION

Data inputs are selected with CLCxSEL0 and

CLCxSEL1 registers (Register 24-3 and Register 24-5,

respectively).

There are 16 signals available as inputs to the configu-

rable logic. Four 8-input multiplexers are used to select

the inputs to pass on to the next stage. The 16 inputs to

the multiplexers are arranged in groups of four. Each

group is available to two of the four multiplexers, in

Note:

Data selections are undefined at power-up.

TABLE 24-1: CLCx DATA INPUT SELECTION

lcxd1 lcxd2 lcxd3 lcxd4

Data Input

CLC 1

CLC 2

CLC 3

CLC3IN0

CLC 4

CLC4IN0

D1S D2S D3S D4S

LCx_in[0]

LCx_in[1]

LCx_in[2]

LCx_in[3]

LCx_in[4]

LCx_in[5]

LCx_in[6]

LCx_in[7]

LCx_in[8]

LCx_in[9]

LCx_in[10]

LCx_in[11]

LCx_in[12]

000

001

010

011

—

100 CLC1IN0

CLC2IN0

101 CLC1IN1

CLC2IN1

C1OUT_sync

C2OUT_sync

FOSC

CLC3IN1

C1OUT_sync

C2OUT_sync

FOSC

CLC4IN1

110 C1OUT_sync

111 C2OUT_sync

C1OUT_sync

C2OUT_sync

FOSC

100 000

101 001

110 010

111 011

—

FOSC

T0_overflow

T1_overflow

T2_match

LC1_out

LC2_out

LC3_out

LC4_out

T0_overflow

T1_overflow

T2_match

LC1_out

T0_overflow

T1_overflow

T2_match

LC1_out

T0_overflow

T1_overflow

T2_match

LC1_out

—

100 000

101 001

110 010

111 011

LC2_out

LC3_out

LC4_out

—

100 000 NCO1_out

LFINTOSC

TX_out

SCK_out (MSSP)

(EUSART)

LCx_in[13]

LCx_in[14]

LCx_in[15]

—

101 001 HFINTOSC

110 010 PWM3_out

111 011 PWM4_out

FRC

LFINTOSC

PWM2_out

PWM3_out

SDO_out (MSSP)

PWM1_out

PWM2_out

PWM4_out

DS40001609E-page 258

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PIC16(L)F1508/9

Data gating is indicated in the right side of Figure 24-2.

Only one gate is shown in detail. The remaining three

gates are configured identically with the exception that

the data enables correspond to the enables for that

gate.

24.1.2

DATA GATING

Outputs from the input multiplexers are directed to the

desired logic function input through the data gating

stage. Each data gate can direct any combination of the

four selected inputs.

24.1.3

LOGIC FUNCTION

Note:

Data gating is undefined at power-up.

There are eight available logic functions including:

The gate stage is more than just signal direction. The

gate can be configured to direct each input signal as

inverted or non-inverted data. Directed signals are

ANDed together in each gate. The output of each gate

can be inverted before going on to the logic function

stage.

• AND-OR

• OR-XOR

• AND

• S-R Latch

• D Flip-Flop with Set and Reset

• D Flip-Flop with Reset

• J-K Flip-Flop with Reset

• Transparent Latch with Set and Reset

The gating is in essence

a

1-to-4 input

AND/NAND/OR/NOR gate. When every input is

inverted and the output is inverted, the gate is an OR of

all enabled data inputs. When the inputs and output are

not inverted, the gate is an AND or all enabled inputs.

Logic functions are shown in Figure 24-3. Each logic

function has four inputs and one output. The four inputs

are the four data gate outputs of the previous stage.

The output is fed to the inversion stage and from there

to other peripherals, an output pin, and back to the

CLCx itself.

Table 24-2 summarizes the basic logic that can be

obtained in gate 1 by using the gate logic select bits.

The table shows the logic of four input variables, but

each gate can be configured to use less than four. If

no inputs are selected, the output will be zero or one,

depending on the gate output polarity bit.

24.1.4

OUTPUT POLARITY

The last stage in the configurable logic cell is the output

polarity. Setting the LCxPOL bit of the CLCxCON reg-

ister inverts the output signal from the logic stage.

Changing the polarity while the interrupts are enabled

will cause an interrupt for the resulting output transition.

TABLE 24-2: DATA GATING LOGIC

CLCxGLS0

LCxG1POL

Gate Logic

0x55

0xAA

0x00

1

0

1

0

1

AND

NAND

NOR

OR

Logic 0

Logic 1

It is possible (but not recommended) to select both the

true and negated values of an input. When this is done,

the gate output is zero, regardless of the other inputs,

but may emit logic glitches (transient-induced pulses).

If the output of the channel must be zero or one, the

recommended method is to set all gate bits to zero and

use the gate polarity bit to set the desired level.

Data gating is configured with the logic gate select

registers as follows:

• Gate 1: CLCxGLS0 (Register 24-5)

• Gate 2: CLCxGLS1 (Register 24-6)

• Gate 3: CLCxGLS2 (Register 24-7)

• Gate 4: CLCxGLS3 (Register 24-8)

Register number suffixes are different than the gate

numbers because other variations of this module have

multiple gate selections in the same register.

 2011-2015 Microchip Technology Inc.

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PIC16(L)F1508/9

24.1.5

CLCx SETUP STEPS

24.2 CLCx Interrupts

The following steps should be followed when setting up

the CLCx:

An interrupt will be generated upon a change in the

output value of the CLCx when the appropriate interrupt

enables are set. A rising edge detector and a falling

edge detector are present in each CLC for this purpose.

• Disable CLCx by clearing the LCxEN bit.

• Select desired inputs using CLCxSEL0 and

CLCxSEL1 registers (See Table 24-1).

• Clear any associated ANSEL bits.

The CLCxIF bit of the associated PIR registers will be

set when either edge detector is triggered and its asso-

ciated enable bit is set. The LCxINTP enables rising

edge interrupts and the LCxINTN bit enables falling

edge interrupts. Both are located in the CLCxCON

register.

• Set all TRIS bits associated with inputs.

• Clear all TRIS bits associated with outputs.

• Enable the chosen inputs through the four gates

using CLCxGLS0, CLCxGLS1, CLCxGLS2, and

CLCxGLS3 registers.

To fully enable the interrupt, set the following bits:

• Select the gate output polarities with the

LCxPOLy bits of the CLCxPOL register.

• LCxON bit of the CLCxCON register

• CLCxIE bit of the associated PIE registers

• Select the desired logic function with the

LCxMODE<2:0> bits of the CLCxCON register.

• LCxINTP bit of the CLCxCON register (for a rising

edge detection)

• Select the desired polarity of the logic output with

the LCxPOL bit of the CLCxPOL register. (This

step may be combined with the previous gate

output polarity step).

• LCxINTN bit of the CLCxCON register (for a

falling edge detection)

• PEIE and GIE bits of the INTCON register

The CLCxIF bit of the associated PIR registers, must

be cleared in software as part of the interrupt service. If

another edge is detected while this flag is being

cleared, the flag will still be set at the end of the

sequence.

• If driving a device, set the LCxOE bit in the

CLCxCON register and also clear the TRIS bit

corresponding to that output.

• If interrupts are desired, configure the following

bits:

- Set the LCxINTP bit in the CLCxCON register

for rising event.

24.3 Output Mirror Copies

Mirror copies of all LCxCON output bits are contained

in the CLCxDATA register. Reading this register reads

the outputs of all CLCs simultaneously. This prevents

any reading skew introduced by testing or reading the

CLCxOUT bits in the individual CLCxCON registers.

- Set the LCxINTN bit in the CLCxCON

register or falling event.

- Set the CLCxIE bit of the associated PIE

registers.

- Set the GIE and PEIE bits of the INTCON

register.

24.4 Effects of a Reset

• Enable the CLCx by setting the LCxEN bit of the

CLCxCON register.

The CLCxCON register is cleared to zero as the result

of a Reset. All other selection and gating values remain

unchanged.

24.5 Operation During Sleep

The CLC module operates independently from the

system clock and will continue to run during Sleep,

provided that the input sources selected remain active.

The HFINTOSC remains active during Sleep when the

CLC module is enabled and the HFINTOSC is

selected as an input source, regardless of the system

clock source selected.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and as a CLC input

source, when the CLC is enabled, the CPU will go idle

during Sleep, but the CLC will continue to operate and

the HFINTOSC will remain active.

This will have a direct effect on the Sleep mode current.

DS40001609E-page 260

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PIC16(L)F1508/9

FIGURE 24-2:

INPUT DATA SELECTION AND GATING

Data Selection

LCx_in[0]

00000

Data GATE 1

lcxd1T

lcxd1N

LCxD1G1T

LCxD1G1N

LCxD2G1T

LCxD2G1N

LCxD3G1T

LCxD3G1N

LCxD4G1T

LCxD4G1N

11111

00000

LCx_in[31]

LCx_in[0]

LCxD1S<4:0>

lcxg1

LCxG1POL

lcxd2T

lcxd2N

11111

00000

LCx_in[31]

LCx_in[0]

LCxD2S<4:0>

LCxD3S<4:0>

LCxD4S<4:0>

Data GATE 2

lcxg2

lcxd3T

lcxd3N

(Same as Data GATE 1)

Data GATE 3

11111

00000

LCx_in[31]

LCx_in[0]

lcxg3

lcxg4

(Same as Data GATE 1)

Data GATE 4

(Same as Data GATE 1)

lcxd4T

lcxd4N

11111

LCx_in[31]

Note:

All controls are undefined at power-up.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 261

PIC16(L)F1508/9

FIGURE 24-3:

PROGRAMMABLE LOGIC FUNCTIONS

Rev. 10-000122A

7/30/2013

AND-OR

OR-XOR

lcxg1

lcxg2

lcxq

lcxg3

lcxg4

lcxg3

lcxg4

LCxMODE<2:0> = 000

LCxMODE<2:0> = 001

4-input AND

S-R Latch

lcxg1

lcxq

S

R

Q

lcxg2

lcxg3

lcxq

lcxg3

lcxg4

LCxMODE<2:0> = 010

LCxMODE<2:0> = 011

1-Input D Flip-Flop with S and R

2-Input D Flip-Flop with R

lcxg4

lcxg2

S

D

Q

D

Q

lcxg2

lcxq

lcxg1

lcxg3

lcxg1

R

lcxg3

LCxMODE<2:0> = 100

LCxMODE<2:0> = 101

J-K Flip-Flop with R

1-Input Transparent Latch with S and R

lcxg4

J

Q

lcxg2

lcxq

S

D

Q

lcxg2

lcxq

lcxg1

lcxg4

K

R

LE

lcxg3

lcxg1

R

lcxg3

LCxMODE<2:0> = 110

LCxMODE<2:0> = 111

DS40001609E-page 262

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PIC16(L)F1508/9

24.6 Register Definitions: CLC Control

REGISTER 24-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER

R/W-0/0

LCxEN

R/W-0/0

LCxOE

R-0/0

R/W-0/0

bit 0

LCxOUT

LCxINTP

LCxINTN

LCxMODE<2:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

LCxEN: Configurable Logic Cell Enable bit

1= Configurable logic cell is enabled and mixing input signals

0= Configurable logic cell is disabled and has logic zero output

LCxOE: Configurable Logic Cell Output Enable bit

1= Configurable logic cell port pin output enabled

0= Configurable logic cell port pin output disabled

bit 5

bit 4

LCxOUT: Configurable Logic Cell Data Output bit

Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.

LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit

1= CLCxIF will be set when a rising edge occurs on lcx_out

0= CLCxIF will not be set

bit 3

LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit

1= CLCxIF will be set when a falling edge occurs on lcx_out

0= CLCxIF will not be set

bit 2-0

LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits

111= Cell is 1-input transparent latch with S and R

110= Cell is J-K flip-flop with R

101= Cell is 2-input D flip-flop with R

100= Cell is 1-input D flip-flop with S and R

011= Cell is S-R latch

010= Cell is 4-input AND

001= Cell is OR-XOR

000= Cell is AND-OR

 2011-2015 Microchip Technology Inc.

DS40001609E-page 263

PIC16(L)F1508/9

REGISTER 24-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER

R/W-0/0

LCxPOL

U-0

—

U-0

—

U-0

—

R/W-x/u

LCxG4POL LCxG3POL

LCxG2POL LCxG1POL

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

LCxPOL: LCOUT Polarity Control bit

1= The output of the logic cell is inverted

0= The output of the logic cell is not inverted

bit 6-4

bit 3

Unimplemented: Read as ‘0’

LCxG4POL: Gate 4 Output Polarity Control bit

1= The output of gate 4 is inverted when applied to the logic cell

0= The output of gate 4 is not inverted

bit 2

bit 1

bit 0

LCxG3POL: Gate 3 Output Polarity Control bit

1= The output of gate 3 is inverted when applied to the logic cell

0= The output of gate 3 is not inverted

LCxG2POL: Gate 2 Output Polarity Control bit

1= The output of gate 2 is inverted when applied to the logic cell

0= The output of gate 2 is not inverted

LCxG1POL: Gate 1 Output Polarity Control bit

1= The output of gate 1 is inverted when applied to the logic cell

0= The output of gate 1 is not inverted

DS40001609E-page 264

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PIC16(L)F1508/9

REGISTER 24-3: CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER

U-0

—

R/W-x/u

LCxD2S<2:0>⁽¹⁾

R/W-x/u

U-0

—

R/W-x/u

LCxD1S<2:0>⁽¹⁾

R/W-x/u

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-4

LCxD2S<2:0>: Input Data 2 Selection Control bits⁽¹⁾

111= LCx_in[11] is selected for lcxd2

110= LCx_in[10] is selected for lcxd2

101= LCx_in[9] is selected for lcxd2

100= LCx_in[8] is selected for lcxd2

011= LCx_in[7] is selected for lcxd2

010= LCx_in[6] is selected for lcxd2

001= LCx_in[5] is selected for lcxd2

000= LCx_in[4] is selected for lcxd2

bit 3

Unimplemented: Read as ‘0’

bit 2-0

LCxD1S<2:0>: Input Data 1 Selection Control bits⁽¹⁾

111= LCx_in[7] is selected for lcxd1

110= LCx_in[6] is selected for lcxd1

101= LCx_in[5] is selected for lcxd1

100= LCx_in[4] is selected for lcxd1

011= LCx_in[3] is selected for lcxd1

010= LCx_in[2] is selected for lcxd1

001= LCx_in[1] is selected for lcxd1

000= LCx_in[0] is selected for lcxd1

Note 1: See Table 24-1 for signal names associated with inputs.

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DS40001609E-page 265

PIC16(L)F1508/9

REGISTER 24-4: CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER

U-0

—

R/W-x/u

LCxD4S<2:0>⁽¹⁾

R/W-x/u

U-0

—

R/W-x/u

LCxD3S<2:0>⁽¹⁾

R/W-x/u

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-4

LCxD4S<2:0>: Input Data 4 Selection Control bits⁽¹⁾

111= LCx_in[3] is selected for lcxd4

110= LCx_in[2] is selected for lcxd4

101= LCx_in[1] is selected for lcxd4

100= LCx_in[0] is selected for lcxd4

011= LCx_in[15] is selected for lcxd4

010= LCx_in[14] is selected for lcxd4

001= LCx_in[13] is selected for lcxd4

000= LCx_in[12] is selected for lcxd4

bit 3

Unimplemented: Read as ‘0’

bit 2-0

LCxD3S<2:0>: Input Data 3 Selection Control bits⁽¹⁾

111= LCx_in[15] is selected for lcxd3

110= LCx_in[14] is selected for lcxd3

101= LCx_in[13] is selected for lcxd3

100= LCx_in[12] is selected for lcxd3

011= LCx_in[11] is selected for lcxd3

010= LCx_in[10] is selected for lcxd3

001= LCx_in[9] is selected for lcxd3

000= LCx_in[8] is selected for lcxd3

Note 1: See Table 24-1 for signal names associated with inputs.

DS40001609E-page 266

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PIC16(L)F1508/9

REGISTER 24-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER

R/W-x/u

LCxG1D4T

LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T

LCxG1D2N

LCxG1D1T LCxG1D1N

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit

1= lcxd4T is gated into lcxg1

0= lcxd4T is not gated into lcxg1

LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit

1= lcxd4N is gated into lcxg1

0= lcxd4N is not gated into lcxg1

LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit

1= lcxd3T is gated into lcxg1

0= lcxd3T is not gated into lcxg1

LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit

1= lcxd3N is gated into lcxg1

0= lcxd3N is not gated into lcxg1

LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit

1= lcxd2T is gated into lcxg1

0= lcxd2T is not gated into lcxg1

LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit

1= lcxd2N is gated into lcxg1

0= lcxd2N is not gated into lcxg1

LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit

1= lcxd1T is gated into lcxg1

0= lcxd1T is not gated into lcxg1

LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit

1= lcxd1N is gated into lcxg1

0= lcxd1N is not gated into lcxg1

 2011-2015 Microchip Technology Inc.

DS40001609E-page 267

PIC16(L)F1508/9

REGISTER 24-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER

R/W-x/u

LCxG2D4T

LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T

LCxG2D2N

LCxG2D1T LCxG2D1N

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit

1= lcxd4T is gated into lcxg2

0= lcxd4T is not gated into lcxg2

LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit

1= lcxd4N is gated into lcxg2

0= lcxd4N is not gated into lcxg2

LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit

1= lcxd3T is gated into lcxg2

0= lcxd3T is not gated into lcxg2

LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit

1= lcxd3N is gated into lcxg2

0= lcxd3N is not gated into lcxg2

LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit

1= lcxd2T is gated into lcxg2

0= lcxd2T is not gated into lcxg2

LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit

1= lcxd2N is gated into lcxg2

0= lcxd2N is not gated into lcxg2

LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit

1= lcxd1T is gated into lcxg2

0= lcxd1T is not gated into lcxg2

LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit

1= lcxd1N is gated into lcxg2

0= lcxd1N is not gated into lcxg2

DS40001609E-page 268

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PIC16(L)F1508/9

REGISTER 24-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER

R/W-x/u

LCxG3D4T

LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T

LCxG3D2N

LCxG3D1T LCxG3D1N

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit

1= lcxd4T is gated into lcxg3

0= lcxd4T is not gated into lcxg3

LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit

1= lcxd4N is gated into lcxg3

0= lcxd4N is not gated into lcxg3

LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit

1= lcxd3T is gated into lcxg3

0= lcxd3T is not gated into lcxg3

LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit

1= lcxd3N is gated into lcxg3

0= lcxd3N is not gated into lcxg3

LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit

1= lcxd2T is gated into lcxg3

0= lcxd2T is not gated into lcxg3

LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit

1= lcxd2N is gated into lcxg3

0= lcxd2N is not gated into lcxg3

LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit

1= lcxd1T is gated into lcxg3

0= lcxd1T is not gated into lcxg3

LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit

1= lcxd1N is gated into lcxg3

0= lcxd1N is not gated into lcxg3

 2011-2015 Microchip Technology Inc.

DS40001609E-page 269

PIC16(L)F1508/9

REGISTER 24-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER

R/W-x/u

LCxG4D4T

LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T

LCxG4D2N

LCxG4D1T LCxG4D1N

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit

1= lcxd4T is gated into lcxg4

0= lcxd4T is not gated into lcxg4

LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit

1= lcxd4N is gated into lcxg4

0= lcxd4N is not gated into lcxg4

LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit

1= lcxd3T is gated into lcxg4

0= lcxd3T is not gated into lcxg4

LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit

1= lcxd3N is gated into lcxg4

0= lcxd3N is not gated into lcxg4

LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit

1= lcxd2T is gated into lcxg4

0= lcxd2T is not gated into lcxg4

LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit

1= lcxd2N is gated into lcxg4

0= lcxd2N is not gated into lcxg4

LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit

1= lcxd1T is gated into lcxg4

0= lcxd1T is not gated into lcxg4

LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit

1= lcxd1N is gated into lcxg4

0= lcxd1N is not gated into lcxg4

DS40001609E-page 270

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PIC16(L)F1508/9

REGISTER 24-9: CLCDATA: CLC DATA OUTPUT

U-0

—

U-0

—

U-0

—

U-0

—

R-0

MLC4OUT

MLC3OUT

MLC2OUT

MLC1OUT

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

bit 2

bit 1

bit 0

Unimplemented: Read as ‘0’

MLC4OUT: Mirror copy of LC4OUT bit

MLC3OUT: Mirror copy of LC3OUT bit

MLC2OUT: Mirror copy of LC2OUT bit

MLC1OUT: Mirror copy of LC1OUT bit

 2011-2015 Microchip Technology Inc.

DS40001609E-page 271

PIC16(L)F1508/9

TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx

Register

on Page

Name

ANSELA

Bit7

Bit6

Bit5

Bit4

BIt3

Bit2

Bit1

Bit0

—

ANSB5

—

ANSA4

ANSB4

—

ANSA2

—

ANSA1

—

ANSA0

—

110

114

118

263

271

267

268

269

270

264

265

266

263

267

268

269

270

264

265

266

263

267

268

269

270

264

265

266

263

267

268

269

270

264

265

266

75

ANSELB

ANSELC

—

ANSC7

ANSC6

ANSC3

ANSC2

ANSC1

ANSC0

CLC1CON

CLCDATA

CLC1GLS0

CLC1GLS1

CLC1GLS2

CLC1GLS3

LC1EN

—

LC1OE

—

LC1OUT

—

LC1INTP

—

LC1INTN

—

LC1MODE<2:0>

MLC2OUT

MLC3OUT

LC1G1D2N

LC1G2D2N

LC1G3D2N

LC1G4D2N

LC1G3POL

MLC1OUT

LC1G1D1N

LC1G2D1N

LC1G3D1N

LC1G4D1N

LC1G1POL

LC1G1D4T

LC1G2D4T

LC1G3D4T

LC1G4D4T

LC1G1D4N

LC1G2D4N

LC1G3D4N

LC1G4D4N

—

LC1G1D3T

LC1G2D3T

LC1G3D3T

LC1G4D3T

LC1G1D3N

LC1G2D3N

LC1G3D3N

LC1G4D3N

—

LC1G1D2T

LC1G2D2T

LC1G3D2T

LC1G4D2T

LC1G1D1T

LC1G2D1T

LC1G3D1T

LC1G4D1T

CLC1POL

CLC1SEL0

CLC1SEL1

LC1POL

—

LC1G4POL

LC1G2POL

LC1D1S<2:0>

LC1D3S<2:0>

—

LC1D2S<2:0>

LC1D4S<2:0>

—

CLC2CON

CLC2GLS0

CLC2GLS1

LC2EN

LC2OE

LC2G1D4N

LC2G2D4N

LC2G3D4N

LC2G4D4N

—

LC2OUT

LC2G1D3T

LC2G2D3T

LC2INTP

LC2G1D3N

LC2G2D3N

LC2G3D3N

LC2G4D3N

—

LC2INTN

LC2G1D2T

LC2G2D2T

LC2MODE<2:0>

LC2G1D1T

LC2G1D4T

LC2G2D4T

LC2G1D2N

LC2G2D2N

LC2G3D2N

LC2G4D2N

LC2G3POL

LC2G1D1N

LC2G2D1N

LC2G3D1N

LC2G4D1N

LC2G1POL

LC2G2D1T

CLC2GLS2

CLC2GLS3

CLC2POL

CLC2SEL0

LC2G3D4T

LC2G4D4T

LC2POL

—

LC2G3D3T

LC2G4D3T

—

LC2G3D2T

LC2G4D2T

LC2G4POL

—

LC2G3D1T

LC2G4D1T

LC2G2POL

LC2D1S<2:0>

LC2D2S<2:0>

CLC2SEL1

CLC3CON

CLC3GLS0

CLC3GLS1

CLC3GLS2

—

LC2D4S<2:0>

LC3OUT

—

LC2D3S<2:0>

LC3MODE<2:0>

LC3G1D1T

LC3EN

LC3OE

LC3G1D4N

LC3G2D4N

LC3G3D4N

LC3G4D4N

—

LC3INTP

LC3G1D3N

LC3G2D3N

LC3G3D3N

LC3G4D3N

—

LC3INTN

LC3G1D2T

LC3G2D2T

LC3G3D2T

LC3G1D4T

LC3G2D4T

LC3G3D4T

LC3G1D3T

LC3G2D3T

LC3G3D3T

LC3G1D2N

LC3G2D2N

LC3G3D2N

LC3G4D2N

LC3G3POL

LC3G1D1N

LC3G2D1N

LC3G3D1N

LC3G4D1N

LC3G1POL

LC3G2D1T

LC3G3D1T

CLC3GLS3

CLC3POL

CLC3SEL0

CLC3SEL1

LC3G4D4T

LC3POL

—

LC3G4D3T

—

LC3G4D2T

LC3G4D1T

LC3G2POL

LC3G4POL

LC3D2S<2:0>

LC3D4S<2:0>

—

LC3D1S<2:0>

LC3D3S<2:0>

—

CLC4CON

CLC4GLS0

CLC4GLS1

CLC4GLS2

CLC4GLS3

LC4EN

LC4OE

LC4G1D4N

LC4G2D4N

LC4G3D4N

LC4G4D4N

—

LC4OUT

LC4G1D3T

LC4G2D3T

LC4G3D3T

LC4G4D3T

LC4INTP

LC4G1D3N

LC4G2D3N

LC4G3D3N

LC4G4D3N

—

LC4INTN

LC4G1D2T

LC4G2D2T

LC4G3D2T

LC4G4D2T

LC4MODE<2:0>

LC4G1D1T

LC4G2D1T

LC4G3D1T

LC4G4D1T

LC4G1D4T

LC4G2D4T

LC4G3D4T

LC4G4D4T

LC4G1D2N

LC4G2D2N

LC4G3D2N

LC4G4D2N

LC4G3POL

LC4G1D1N

LC4G2D1N

LC4G3D1N

LC4G4D1N

CLC4POL

CLC4SEL0

CLC4SEL1

LC4POL

—

LC4G4POL

LC4G2POL LC4G1POL

LC4D1S<2:0>

—

LC4D2S<2:0>

LC4D4S<2:0>

—

LC4D3S<2:0>

INTCON

PIE3

GIE

—

PEIE

—

TMR0IE

—

INTE

—

IOCIE

CLC4IE

CLC4IF

TMR0IF

CLC3IE

CLC3IF

TRISA2

INTF

IOCIF

CLC1IE

CLC1IF

TRISA0

CLC2IE

CLC2IF

TRISA1

78

—

PIR3

81

(1)

—

TRISA5

TRISA4

—

TRISA

TRISB

TRISC

109

113

117

TRISB7

TRISC7

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

—

TRISC3

TRISC2

TRISC1

TRISC0

Legend:

Note 1:

— = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.

Unimplemented, read as ‘1’.

DS40001609E-page 272

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25.1.2

ACCUMULATOR

25.0 NUMERICALLY CONTROLLED

OSCILLATOR (NCO) MODULE

The accumulator is a 20-bit register. Read and write

access to the accumulator is available through three

registers:

The Numerically Controlled Oscillator (NCOx) module

is a timer that uses the overflow from the addition of an

increment value to divide the input frequency. The

advantage of the addition method over simple counter

driven timer is that the resolution of division does not

vary with the divider value. The NCOx is most useful for

applications that require frequency accuracy and fine

resolution at a fixed duty cycle.

• NCOxACCL

• NCOxACCH

• NCOxACCU

25.1.3

ADDER

The NCOx adder is a full adder, which operates

independently from the system clock. The addition of the

previous result and the increment value replaces the

accumulator value on the rising edge of each input clock.

Features of the NCOx include:

• 16-bit increment function

• Fixed Duty Cycle (FDC) mode

• Pulse Frequency (PF) mode

• Output pulse width control

• Multiple clock input sources

• Output polarity control

25.1.4

INCREMENT REGISTERS

The increment value is stored in two 8-bit registers

making up a 16-bit increment. In order of LSB to MSB

they are:

• Interrupt capability

• NCOxINCL

• NCOxINCH

Figure 25-1 is a simplified block diagram of the NCOx

module.

When the NCO module is enabled, the NCOxINCH

should be written first, then the NCOxINCL register.

Writing to the NCOxINCL register initiates the incre-

ment buffer registers to be loaded simultaneously on

the second rising edge of the NCOx_clk signal.

25.1 NCOx Operation

The NCOx operates by repeatedly adding a fixed value

to an accumulator. Additions occur at the input clock rate.

The accumulator will overflow with a carry periodically,

which is the raw NCOx output (NCO_overflow). This

effectively reduces the input clock by the ratio of the

addition value to the maximum accumulator value. See

Equation 25-1.

The registers are readable and writable. The increment

registers are double-buffered to allow value changes to

be made without first disabling the NCOx module.

When the NCO module is disabled, the increment

buffers are loaded immediately after a write to the

increment registers.

The NCOx output can be further modified by stretching

the pulse or toggling a flip-flop. The modified NCOx

output is then distributed internally to other peripherals

and optionally output to a pin. The accumulator

overflow also generates an interrupt (NCO_interrupt).

Note: The increment buffer registers are not

user-accessible.

The NCOx period changes in discrete steps to create

an average frequency. This output depends on the

ability of the receiving circuit (i.e., CWG or external

resonant converter circuitry) to average the NCOx

output to reduce uncertainty.

25.1.1

NCOx CLOCK SOURCES

Clock sources available to the NCOx include:

• HFINTOSC

• FOSC

• LC1_out

• CLKIN pin

The NCOx clock source is selected by configuring the

NxCKS<2:0> bits in the NCOxCLK register.

EQUATION 25-1:

NCO Clock Frequency  Increment Value

FOVERFLOW= ---------------------------------------------------------------------------------------------------------------

2ⁿ

n = Accumulator width in bits

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25.2 Fixed Duty Cycle (FDC) Mode

25.5 Interrupts

In Fixed Duty Cycle (FDC) mode, every time the

accumulator overflows (NCO_overflow), the output is

toggled. This provides a 50% duty cycle, provided that

the increment value remains constant. For more

information, see Figure 25-2.

When the accumulator overflows (NCO_overflow), the

NCOx Interrupt Flag bit, NCOxIF, of the PIRx register is

set. To enable the interrupt event (NCO_interrupt), the

following bits must be set:

• NxEN bit of the NCOxCON register

• NCOxIE bit of the PIEx register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The FDC mode is selected by clearing the NxPFM bit

in the NCOxCON register.

25.3 Pulse Frequency (PF) Mode

The interrupt must be cleared by software by clearing

the NCOxIF bit in the Interrupt Service Routine.

In Pulse Frequency (PF) mode, every time the accumu-

lator overflows (NCO_overflow), the output becomes

active for one or more clock periods. Once the clock

period expires, the output returns to an inactive state.

This provides a pulsed output.

25.6 Effects of a Reset

All of the NCOx registers are cleared to zero as the

result of a Reset.

The output becomes active on the rising clock edge

immediately following the overflow event. For more

information, see Figure 25-2.

25.7 Operation In Sleep

The NCO module operates independently from the

system clock and will continue to run during Sleep,

provided that the clock source selected remains

active.

The value of the active and inactive states depends on

the polarity bit, NxPOL in the NCOxCON register.

The PF mode is selected by setting the NxPFM bit in

the NCOxCON register.

The HFINTOSC remains active during Sleep when the

NCO module is enabled and the HFINTOSC is

selected as the clock source, regardless of the system

clock source selected.

25.3.1

OUTPUT PULSE WIDTH CONTROL

When operating in PF mode, the active state of the out-

put can vary in width by multiple clock periods. Various

pulse widths are selected with the NxPWS<2:0> bits in

the NCOxCLK register.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and the NCO clock

source, when the NCO is enabled, the CPU will go idle

during Sleep, but the NCO will continue to operate and

the HFINTOSC will remain active.

When the selected pulse width is greater than the

accumulator overflow time frame, the output of the

NCOx operation is indeterminate.

This will have a direct effect on the Sleep mode current.

25.4 Output Polarity Control

The last stage in the NCOx module is the output polar-

ity. The NxPOL bit in the NCOxCON register selects the

output polarity. Changing the polarity while the inter-

rupts are enabled will cause an interrupt for the result-

ing output transition.

25.8 Alternate Pin Locations

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

register, APFCON. To determine which pins can be

moved and what their default locations are upon a

Reset, see Section 11.1 “Alternate Pin Function” for

more information.

The NCOx output can be used internally by source

code or other peripherals. Accomplish this by reading

the NxOUT (read-only) bit of the NCOxCON register.

The NCOx output signal is available to the following

peripherals:

• CLC

• CWG

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25.9 Register Definitions: NCOx Control Registers

REGISTER 25-1: NCOxCON: NCOx CONTROL REGISTER

R/W-0/0

NxEN

R/W-0/0

NxOE

R-0/0

R/W-0/0

NxPOL

U-0

—

U-0

—

U-0

—

R/W-0/0

NxPFM

NxOUT

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

NxEN: NCOx Enable bit

1= NCOx module is enabled

0= NCOx module is disabled

NxOE: NCOx Output Enable bit

1= NCOx output pin is enabled

0= NCOx output pin is disabled

NxOUT: NCOx Output bit

1= NCOx output is high

0= NCOx output is low

NxPOL: NCOx Polarity bit

1= NCOx output signal is active low (inverted)

0= NCOx output signal is active high (non-inverted)

bit 3-1

bit 0

Unimplemented: Read as ‘0’

NxPFM: NCOx Pulse Frequency Mode bit

1= NCOx operates in Pulse Frequency mode

0= NCOx operates in Fixed Duty Cycle mode

REGISTER 25-2: NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER

R/W-0/0

U-0

—

U-0

—

U-0

—

R/W-0/0

(1, 2)

NxPWS<2:0>

NxCKS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

(1, 2)

bit 7-5

NxPWS<2:0>: NCOx Output Pulse Width Select bits

111= 128 NCOx clock periods

110= 64 NCOx clock periods

101= 32 NCOx clock periods

100= 16 NCOx clock periods

011= 8 NCOx clock periods

010= 4 NCOx clock periods

001= 2 NCOx clock periods

000= 1 NCOx clock periods

bit 4-2

bit 1-0

Unimplemented: Read as ‘0’

NxCKS<1:0>: NCOx Clock Source Select bits

11= NCO1CLK pin

10= LC1_out

01= FOSC

00= HFINTOSC (16 MHz)

Note 1: NxPWS applies only when operating in Pulse Frequency mode.

2: If NCOx pulse width is greater than NCO_overflow period, operation is indeterminate.

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REGISTER 25-3: NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE

R/W-0/0

NCOxACC<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

NCOxACC<7:0>: NCOx Accumulator, Low Byte

REGISTER 25-4: NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH BYTE

R/W-0/0

NCOxACC<15:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

NCOxACC<15:8>: NCOx Accumulator, High Byte

REGISTER 25-5: NCOxACCU: NCOx ACCUMULATOR REGISTER – UPPER BYTE

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

NCOxACC<19:16>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

NCOxACC<19:16>: NCOx Accumulator, Upper Byte

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REGISTER 25-6: NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE⁽¹⁾

R/W-0/0

R/W-1/1

bit 0

NCOxINC<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

NCOxINC<7:0>: NCOx Increment, Low Byte

Note 1: Write the NCOxINCH register first, then the NCOxINCL register. See 25.1.4 “Increment Registers” for

more information.

REGISTER 25-7: NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE⁽¹⁾

R/W-0/0

bit 0

NCOxINC<15:8>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

NCOxINC<15:8>: NCOx Increment, High Byte

Note 1: Write the NCOxINCH register first, then the NCOxINCL register. See 25.1.4 “Increment Registers” for

more information.

TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCOx

Register on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

APFCON

—

SSSEL

INTE

T1GSEL

IOCIE

—

CLC1SEL

INTF

NCO1SEL

IOCIF

107

75

INTCON

GIE

PEIE

TMR0IE

TMR0IF

NCO1ACCH

NCO1ACCL

NCO1ACCU

NCO1CLK

NCO1ACC<15:8>

NCO1ACC<7:0>

278

277

—

NCO1ACC<19:16>

N1PWS<2:0>

N1OE

—

N1CKS<1:0>

NCO1CON

NCO1INCH

NCO1INCL

PIE2

N1EN

N1OUT

N1POL

—

N1PFM

277

279

77

NCO1INC<15:8>

NCO1INC<7:0>

OSFIE

OSFIF

C2IE

C2IF

C1IE

C1IF

—

BCL1IE

NCO1IE

NCO1IF

—

PIR2

BCL1IF

80

(1)

TRISA

—

TRISA5

TRISC5

TRISA4

TRISC4

—

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

109

117

TRISC

Legend:

TRISC7

TRISC6

TRISC3

x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not used for NCOx

module.

Note 1:

Unimplemented, read as ‘1’.

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DS40001609E-page 279

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26.3 Selectable Input Sources

26.0 COMPLEMENTARY WAVEFORM

GENERATOR (CWG) MODULE

The CWG generates the output waveforms from the

input sources in Table 26-1.

The Complementary Waveform Generator (CWG)

produces a complementary waveform with dead-band

delay from a selection of input sources.

TABLE 26-1: SELECTABLE INPUT

SOURCES

The CWG module has the following features:

• Selectable dead-band clock source control

• Selectable input sources

Source Peripheral

Signal Name

C1OUT_sync

Comparator C1

Comparator C2

PWM1

• Output enable control

C2OUT_sync

PWM1_out

PWM2_out

PWM3_out

PWM4_out

NCO1_out

LC1_out

• Output polarity control

• Dead-band control with independent 6-bit rising

and falling edge dead-band counters

PWM2

PWM3

• Auto-shutdown control with:

- Selectable shutdown sources

- Auto-restart enable

PWM4

NCO1

- Auto-shutdown pin override control

CLC1

The input sources are selected using the GxIS<2:0>

bits in the CWGxCON1 register (Register 26-2).

26.1 Fundamental Operation

The CWG generates two output waveforms from the

selected input source.

26.4 Output Control

The off-to-on transition of each output can be delayed

from the on-to-off transition of the other output, thereby,

creating a time delay immediately where neither output

is driven. This is referred to as dead time and is covered

in Section 26.5 “Dead-Band Control”. A typical

operating waveform, with dead band, generated from a

single input signal is shown in Figure 26-2.

Immediately after the CWG module is enabled, the

complementary drive is configured with both CWGxA

and CWGxB drives cleared.

26.4.1

OUTPUT ENABLES

Each CWG output pin has individual output enable

control. Output enables are selected with the GxOEA

and GxOEB bits of the CWGxCON0 register. When an

output enable control is cleared, the module asserts no

control over the pin. When an output enable is set, the

override value or active PWM waveform is applied to

the pin per the port priority selection. The output pin

enables are dependent on the module enable bit,

GxEN. When GxEN is cleared, CWG output enables

and CWG drive levels have no effect.

It may be necessary to guard against the possibility of

circuit faults or a feedback event arriving too late or not

at all. In this case, the active drive must be terminated

before the Fault condition causes damage. This is

referred to as auto-shutdown and is covered in Section

26.9 “Auto-Shutdown Control”.

26.2 Clock Source

The CWG module allows the following clock sources

to be selected:

26.4.2

POLARITY CONTROL

The polarity of each CWG output can be selected

independently. When the output polarity bit is set, the

corresponding output is active-high. Clearing the output

polarity bit configures the corresponding output as

active-low. However, polarity does not affect the

override levels. Output polarity is selected with the

GxPOLA and GxPOLB bits of the CWGxCON0 register.

• Fosc (system clock)

• HFINTOSC (16 MHz only)

The clock sources are selected using the G1CS0 bit of

the CWGxCON0 register (Register 26-1).

DS40001609E-page 280

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FIGURE 26-2:

TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)

cwg_clock

PWM1

CWGxA

Rising Edge

Dead Band

Rising Edge

Dead Band

Rising Edge

Dead Band

Falling Edge

Dead Band

Falling Edge

Dead Band

CWGxB

26.5 Dead-Band Control

26.7 Falling Edge Dead Band

Dead-band control provides for non-overlapping output

signals to prevent shoot-through current in power

switches. The CWG contains two 6-bit dead-band

counters. One dead-band counter is used for the rising

edge of the input source control. The other is used for

the falling edge of the input source control.

The falling edge dead band delays the turn-on of the

CWGxB output from when the CWGxA output is turned

off. The falling edge dead-band time starts when the

falling edge of the input source goes true. When this

happens, the CWGxA output is immediately turned off

and the falling edge dead-band delay time starts. When

the falling edge dead-band delay time is reached, the

CWGxB output is turned on.

Dead band is timed by counting CWG clock periods

from zero up to the value in the rising or falling dead-

band counter registers. See CWGxDBR and

CWGxDBF registers (Register 26-4 and Register 26-5,

respectively).

The CWGxDBF register sets the duration of the dead-

band interval on the falling edge of the input source sig-

nal. This duration is from 0 to 64 counts of dead band.

Dead band is always counted off the edge on the input

source signal. A count of 0 (zero), indicates that no

dead band is present.

26.6 Rising Edge Dead Band

The rising edge dead-band delays the turn-on of the

CWGxA output from when the CWGxB output is turned

off. The rising edge dead-band time starts when the

rising edge of the input source signal goes true. When

this happens, the CWGxB output is immediately turned

off and the rising edge dead-band delay time starts.

When the rising edge dead-band delay time is reached,

the CWGxA output is turned on.

If the input source signal is not present for enough time

for the count to be completed, no output will be seen on

the respective output.

Refer to Figure 26-3 and Figure 26-4 for examples.

The CWGxDBR register sets the duration of the dead-

band interval on the rising edge of the input source

signal. This duration is from 0 to 64 counts of dead band.

Dead band is always counted off the edge on the input

source signal. A count of 0 (zero), indicates that no

dead band is present.

If the input source signal is not present for enough time

for the count to be completed, no output will be seen on

the respective output.

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26.8 Dead-Band Uncertainty

26.9 Auto-Shutdown Control

When the rising and falling edges of the input source

triggers the dead-band counters, the input may be asyn-

chronous. This will create some uncertainty in the dead-

band time delay. The maximum uncertainty is equal to

one CWG clock period. Refer to Equation 26-1 for more

detail.

Auto-shutdown is a method to immediately override the

CWG output levels with specific overrides that allow for

safe shutdown of the circuit. The shutdown state can be

either cleared automatically or held until cleared by

software.

26.9.1

SHUTDOWN

EQUATION 26-1: DEAD-BAND

UNCERTAINTY

The shutdown state can be entered by either of the

following two methods:

• Software generated

• External Input

1

TDEADBAND_UNCERTAINTY = ----------------------------

Fcwg_clock

26.9.1.1

Software Generated Shutdown

Setting the GxASE bit of the CWGxCON2 register will

force the CWG into the shutdown state.

When auto-restart is disabled, the shutdown state will

persist as long as the GxASE bit is set.

Example:

When auto-restart is enabled, the GxASE bit will clear

automatically and resume operation on the next rising

edge event. See Figure 26-6.

Fcwg_clock = 16 MHz

26.9.1.2

External Input Source

External shutdown inputs provide the fastest way to

safely suspend CWG operation in the event of a Fault

condition. When any of the selected shutdown inputs

goes active, the CWG outputs will immediately go to

the selected override levels without software delay. Any

combination of two input sources can be selected to

cause a shutdown condition. The sources are:

Therefore:

1

TDEADBAND_UNCERTAINTY = ----------------------------

Fcwg_clock

• Comparator C1 – C1OUT_async

• Comparator C2 – C2OUT_async

• CLC2 – LC2_out

1

= ------------------

16 MHz

• CWG1FLT

= 62.5ns

Shutdown inputs are selected in the CWGxCON2

register. (Register 26-3).

Note:

Shutdown inputs are level sensitive, not

edge sensitive. The shutdown state can-

not be cleared, except by disabling auto-

shutdown, as long as the shutdown input

level persists.

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26.11.1 PIN OVERRIDE LEVELS

26.10 Operation During Sleep

The levels driven to the output pins, while the shutdown

input is true, are controlled by the GxASDLA and

GxASDLB bits of the CWGxCON1 register

(Register 26-3). GxASDLA controls the CWG1A

override level and GxASDLB controls the CWG1B

override level. The control bit logic level corresponds to

the output logic drive level while in the shutdown state.

The polarity control does not apply to the override level.

The CWG module operates independently from the

system clock and will continue to run during Sleep,

provided that the clock and input sources selected

remain active.

The HFINTOSC remains active during Sleep, provided

that the CWG module is enabled, the input source is

active, and the HFINTOSC is selected as the clock

source, regardless of the system clock source

selected.

26.11.2 AUTO-SHUTDOWN RESTART

After an auto-shutdown event has occurred, there are

two ways to have resume operation:

In other words, if the HFINTOSC is simultaneously

selected as the system clock and the CWG clock

source, when the CWG is enabled and the input

source is active, the CPU will go idle during Sleep, but

the CWG will continue to operate and the HFINTOSC

will remain active.

• Software controlled

• Auto-restart

The restart method is selected with the GxARSEN bit

of the CWGxCON2 register. Waveforms of software

controlled and automatic restarts are shown in

Figure 26-5 and Figure 26-6.

This will have a direct effect on the Sleep mode current.

26.11 Configuring the CWG

26.11.2.1 Software Controlled Restart

When the GxARSEN bit of the CWGxCON2 register is

cleared, the CWG must be restarted after an auto-shut-

down event by software.

The following steps illustrate how to properly configure

the CWG to ensure a synchronous start:

1. Ensure that the TRIS control bits corresponding

to CWGxA and CWGxB are set so that both are

configured as inputs.

Clearing the shutdown state requires all selected shut-

down inputs to be low, otherwise the GxASE bit will

remain set. The overrides will remain in effect until the

first rising edge event after the GxASE bit is cleared.

The CWG will then resume operation.

2. Clear the GxEN bit, if not already cleared.

3. Set desired dead-band times with the CWGxDBR

and CWGxDBF registers.

4. Setup the following controls in CWGxCON2

auto-shutdown register:

26.11.2.2 Auto-Restart

When the GxARSEN bit of the CWGxCON2 register is

set, the CWG will restart from the auto-shutdown state

automatically.

• Select desired shutdown source.

• Select both output overrides to the desired

levels (this is necessary even if not using

auto-shutdown because start-up will be from

a shutdown state).

The GxASE bit will clear automatically when all shut-

down sources go low. The overrides will remain in

effect until the first rising edge event after the GxASE

bit is cleared. The CWG will then resume operation.

• Set the GxASE bit and clear the GxARSEN

bit.

5. Select the desired input source using the

CWGxCON1 register.

6. Configure the following controls in CWGxCON0

register:

• Select desired clock source.

• Select the desired output polarities.

• Set the output enables for the outputs to be

used.

7. Set the GxEN bit.

8. Clear TRIS control bits corresponding to

CWGxA and CWGxB to be used to configure

those pins as outputs.

9. If auto-restart is to be used, set the GxARSEN

bit and the GxASE bit will be cleared automati-

cally. Otherwise, clear the GxASE bit to start the

CWG.

 2011-2015 Microchip Technology Inc.

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PIC16(L)F1508/9

26.12 Register Definitions: CWG Control

REGISTER 26-1: CWGxCON0: CWG CONTROL REGISTER 0

R/W-0/0

GxEN

R/W-0/0

GxOEB

R/W-0/0

GxOEA

R/W-0/0

GxPOLB

R/W-0/0

GxPOLA

U-0

—

U-0

—

R/W-0/0

GxCS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

bit 4

bit 3

GxEN: CWGx Enable bit

1= Module is enabled

0= Module is disabled

GxOEB: CWGxB Output Enable bit

1= CWGxB is available on appropriate I/O pin

0= CWGxB is not available on appropriate I/O pin

GxOEA: CWGxA Output Enable bit

1= CWGxA is available on appropriate I/O pin

0= CWGxA is not available on appropriate I/O pin

GxPOLB: CWGxB Output Polarity bit

1= Output is inverted polarity

0= Output is normal polarity

GxPOLA: CWGxA Output Polarity bit

1= Output is inverted polarity

0= Output is normal polarity

bit 2-1

bit 0

Unimplemented: Read as ‘0’

GxCS0: CWGx Clock Source Select bit

1= HFINTOSC

0= FOSC

 2011-2015 Microchip Technology Inc.

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PIC16(L)F1508/9

REGISTER 26-2: CWGxCON1: CWG CONTROL REGISTER 1

R/W-x/u

U-0

—

R/W-0/0

GxASDLB<1:0>

GxASDLA<1:0>

GxIS<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

GxASDLB<1:0>: CWGx Shutdown State for CWGxB

When an auto shutdown event is present (GxASE = 1):

11= CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit.

10= CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit.

01= CWGxB pin is tri-stated

00= CWGxB pin is driven to its inactive state after the selected dead-band interval. GxPOLB still will

control the polarity of the output.

bit 5-4

GxASDLA<1:0>: CWGx Shutdown State for CWGxA

When an auto shutdown event is present (GxASE = 1):

11= CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit.

10= CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit.

01= CWGxA pin is tri-stated

00= CWGxA pin is driven to its inactive state after the selected dead-band interval. GxPOLA still will

control the polarity of the output.

bit 3

Unimplemented: Read as ‘0’

bit 2-0

GxIS<2:0>: CWGx Input Source Select bits

111= CLC1 – LC1_out

110= NCO1 – NCO1_out

101= PWM4 – PWM4_out

100= PWM3 – PWM3_out

011= PWM2 – PWM2_out

010= PWM1 – PWM1_out

001= Comparator C2– C2OUT_async

000= Comparator C1 – C1OUT_async

DS40001609E-page 288

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PIC16(L)F1508/9

REGISTER 26-3: CWGxCON2: CWG CONTROL REGISTER 2

R/W-0/0

GxASE

R/W-0/0

U-0

—

U-0

—

R/W-0/0

GxARSEN

GxASDSC2 GxASDSC1 GxASDSFLT GxASDSCLC2

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

GxASE: Auto-Shutdown Event Status bit

1= An auto-shutdown event has occurred

0= No auto-shutdown event has occurred

GxARSEN: Auto-Restart Enable bit

1= Auto-restart is enabled

0= Auto-restart is disabled

bit 5-4

bit 3

Unimplemented: Read as ‘0’

GxASDSC2: CWG Auto-shutdown on Comparator C2 Enable bit

1= Shutdown when Comparator C2 output (C2OUT_async) is high

0= Comparator C2 output has no effect on shutdown

bit 2

bit 1

bit 0

GxASDSC1: CWG Auto-shutdown on Comparator C1 Enable bit

1= Shutdown when Comparator C1 output (C1OUT_async) is high

0= Comparator C1 output has no effect on shutdown

GxASDSFLT: CWG Auto-shutdown on FLT Enable bit

1= Shutdown when CWG1FLT input is low

0= CWG1FLT input has no effect on shutdown

GxASDSCLC2: CWG Auto-shutdown on CLC2 Enable bit

1= Shutdown when CLC2 output (LC2_out) is high

0= CLC2 output has no effect on shutdown

 2011-2015 Microchip Technology Inc.

DS40001609E-page 289

PIC16(L)F1508/9

REGISTER 26-4: CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING

DEAD-BAND COUNT REGISTER

U-0

—

U-0

—

R/W-x/u

CWGxDBR<5:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising Counts

11 1111= 63-64 counts of dead band

11 1110= 62-63 counts of dead band





00 0010= 2-3 counts of dead band

00 0001= 1-2 counts of dead band

00 0000= 0 counts of dead band

REGISTER 26-5: CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING

DEAD-BAND COUNT REGISTER

U-0

—

U-0

—

R/W-x/u

CWGxDBF<5:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling Counts

11 1111= 63-64 counts of dead band

11 1110= 62-63 counts of dead band





00 0010= 2-3 counts of dead band

00 0001= 1-2 counts of dead band

00 0000= 0 counts of dead band. Dead-band generation is bypassed.

DS40001609E-page 290

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH CWG

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

—

ANSA4

—

G1POLA

—

ANSA2

—

ANSA1

—

ANSA0

G1CS0

110

287

288

289

290

109

117

CWG1CON0

CWG1CON1

CWG1CON2

CWG1DBF

CWG1DBR

TRISA

G1EN

G1OEB

G1OEA

G1POLB

G1ASDLB<1:0>

G1ASDLA<1:0>

G1IS<1:0>

—

G1ASE

—

G1ARSEN

—

G1ASDSC2 G1ASDSC1

CWG1DBF<5:0>

G1ASDSFLT

G1ASDSCLC2

—

CWG1DBR<5:0>

—

(1)

—

TRISA5

TRISC5

TRISA4

TRISC4

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

—

TRISC

TRISC7

TRISC6

TRISC3

Legend:

Note 1:

x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by CWG.

Unimplemented, read as ‘1’.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 291

PIC16(L)F1508/9

27.3 Common Programming Interfaces

27.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

Connection to a target device is typically done through

an ICSP™ header. A commonly found connector on

development tools is the RJ-11 in the 6P6C (6-pin,

6-connector) configuration. See Figure 27-1.

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP™

programming:

FIGURE 27-1:

ICD RJ-11 STYLE

CONNECTOR INTERFACE

• ICSPCLK

• ICSPDAT

• MCLR/VPP

• VDD

ICSPDAT

• VSS

NC

2 4 6

VDD

In Program/Verify mode the program memory, user IDs

and the Configuration Words are programmed through

serial communications. The ICSPDAT pin is a bidirec-

tional I/O used for transferring the serial data and the

ICSPCLK pin is the clock input. For more information on

ICSP™ refer to the “PIC12(L)F1501/PIC16(L)F150X

Memory Programming Specification” (DS41573).

ICSPCLK

1 3

5

Target

PC Board

Bottom Side

VPP/MCLR

VSS

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

27.1 High-Voltage Programming Entry

Mode

The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT

pins low then raising the voltage on MCLR/VPP to VIHH.

5 = ICSPCLK

6 = No Connect

27.2 Low-Voltage Programming Entry

Mode

Another connector often found in use with the PICkit™

programmers is a standard 6-pin header with 0.1 inch

spacing. Refer to Figure 27-2.

The Low-Voltage Programming Entry mode allows the

PIC^®Flash MCUs to be programmed using VDD only,

without high voltage. When the LVP bit of Configuration

Words is set to ‘1’, the ICSP Low-Voltage Programming

Entry mode is enabled. To disable the Low-Voltage

ICSP mode, the LVP bit must be programmed to ‘0’.

Entry into the Low-Voltage Programming Entry mode

requires the following steps:

1. MCLR is brought to VIL.

2.

A

32-bit key sequence is presented on

ICSPDAT, while clocking ICSPCLK.

Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mode is to be

maintained.

If low-voltage programming is enabled (LVP = 1), the

MCLR Reset function is automatically enabled and

cannot be disabled. See Section 6.5 “MCLR” for more

information.

The LVP bit can only be reprogrammed to ‘0’ by using

the High-Voltage Programming mode.

DS40001609E-page 292

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 27-2:

PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE

Rev. 10-000128A

7/30/2013

Pin 1 Indicator

Pin Description*

1 = VPP/MCLR

1

2

3

4

5

6

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No connect

*

The 6-pin header (0.100" spacing) accepts 0.025" square pins

For additional interface recommendations, refer to your

specific device programmer manual prior to PCB

design.

It is recommended that isolation devices be used to

separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific

application and may include devices such as resistors,

diodes, or even jumpers. See Figure 27-3 for more

information.

FIGURE 27-3:

TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

Rev. 10-000129A

7/30/2013

External

Programming

Signals

Device to be

Programmed

VDD

VPP

VSS

MCLR/VPP

VSS

Data

ICSPDAT

ICSPCLK

Clock

*

To Normal Connections

*

Isolation devices (as required).

 2011-2015 Microchip Technology Inc.

DS40001609E-page 293

PIC16(L)F1508/9

28.1 Read-Modify-Write Operations

28.0 INSTRUCTION SET SUMMARY

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

Each instruction is a 14-bit word containing the opera-

tion code (opcode) and all required operands. The

opcodes are broken into three broad categories.

• Byte Oriented

• Bit Oriented

• Literal and Control

The literal and control category contains the most

varied instruction word format.

TABLE 28-1: OPCODE FIELD

DESCRIPTIONS

Table 28-3 lists the instructions recognized by the

MPASM^TMassembler.

Field

Description

All instructions are executed within a single instruction

cycle, with the following exceptions, which may take

two or three cycles:

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

• Subroutine takes two cycles (CALL, CALLW)

• Returns from interrupts or subroutines take two

cycles (RETURN, RETLW, RETFIE)

k

x

Don’t care location (= 0or 1).

• Program branching takes two cycles (GOTO, BRA,

BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)

• One additional instruction cycle will be used when

any instruction references an indirect file register

and the file select register is pointing to program

memory.

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

One instruction cycle consists of 4 oscillator cycles; for

an oscillator frequency of 4 MHz, this gives a nominal

instruction execution rate of 1 MHz.

n

FSR or INDF number. (0-1)

mm

Pre-post increment-decrement mode

selection

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

TABLE 28-2: ABBREVIATION

DESCRIPTIONS

Field

Description

PC

TO

C

Program Counter

Time-Out bit

Carry bit

DC

Z

Digit Carry bit

Zero bit

PD

Power-Down bit

DS40001609E-page 294

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 28-1:

GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13

8

7

6

0

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9

7 6

0

OPCODE

b (BIT #)

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

General

13

8

7

0

OPCODE

k (literal)

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

0

k (literal)

k = 11-bit immediate value

MOVLPinstruction only

13

7

6

0

OPCODE

k (literal)

k = 7-bit immediate value

MOVLBinstruction only

13

5 4

OPCODE

k (literal)

k = 5-bit immediate value

BRAinstruction only

13

9

8

0

OPCODE

k (literal)

k = 9-bit immediate value

FSR Offset instructions

13

7

6

5

0

OPCODE

n

k (literal)

n = appropriate FSR

k = 6-bit immediate value

FSRIncrement instructions

13

3

2

n

1

OPCODE

m (mode)

n = appropriate FSR

m = 2-bit mode value

OPCODE only

13

0

OPCODE

 2011-2015 Microchip Technology Inc.

DS40001609E-page 295

PIC16(L)F1508/9

TABLE 28-3: ENHANCED MID-RANGE INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC f, d

ANDWF

ASRF

LSLF

f, d

Add W and f

Add with Carry W and f

AND W with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

Clear W

Complement f

Decrement f

Increment f

Inclusive OR W with f

Move f

Move W to f

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Subtract with Borrow W from f

Swap nibbles in f

Exclusive OR W with f

1

00 0111 dfff ffff C, DC, Z

11 1101 dfff ffff C, DC, Z

00 0101 dfff ffff Z

11 0111 dfff ffff C, Z

11 0101 dfff ffff C, Z

11 0110 dfff ffff C, Z

2

f, d

f

LSRF

CLRF

CLRW

COMF

DECF

INCF

IORWF

MOVF

MOVWF

RLF

RRF

SUBWF

SUBWFB f, d

SWAPF

XORWF

00 0001 lfff ffff

00 0001 0000 00xx

00 1001 dfff ffff

00 0011 dfff ffff

00 1010 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 1fff ffff

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

f, d

2

C

00 0010 dfff ffff C, DC, Z

11 1011 dfff ffff C, DC, Z

00 1110 dfff ffff

f, d

00 0110 dfff ffff

Z

BYTE ORIENTED SKIP OPERATIONS

f, d

Decrement f, Skip if 0

Increment f, Skip if 0

1(2)

00

1011 dfff ffff

1111 dfff ffff

1, 2

DECFSZ

INCFSZ

BIT-ORIENTED FILE REGISTER OPERATIONS

f, b

Bit Clear f

Bit Set f

1

01

00bb bfff ffff

01bb bfff ffff

2

BCF

BSF

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS

f, b

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

01

10bb bfff ffff

11bb bfff ffff

1, 2

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

k

Add literal and W

AND literal with W

Inclusive OR literal with W

Move literal to BSR

Move literal to PCLATH

Move literal to W

1

11

00

11

1110 kkkk kkkk C, DC, Z

1001 kkkk kkkk

1000 kkkk kkkk

0000 001k kkkk

0001 1kkk kkkk

0000 kkkk kkkk

Z

Subtract W from literal

Exclusive OR literal with W

1100 kkkk kkkk C, DC, Z

1010 kkkk kkkk

Z

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one

additional instruction cycle.

DS40001609E-page 296

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 28-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED)

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

CONTROL OPERATIONS

BRA

BRW

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN

k

–

Relative Branch

Relative Branch with W

Call Subroutine

Call Subroutine with W

Go to address

Return from interrupt

Return with literal in W

Return from Subroutine

2

11

00

10

00

10

00

11

00

001k kkkk kkkk

0000 0000 1011

0kkk kkkk kkkk

0000 0000 1010

1kkk kkkk kkkk

0000 0000 1001

0100 kkkk kkkk

0000 0000 1000

k

–

k

–

INHERENT OPERATIONS

CLRWDT

NOP

OPTION

RESET

SLEEP

TRIS

–

f

Clear Watchdog Timer

No Operation

Load OPTION_REG register with W

Software device Reset

Go into Standby mode

Load TRIS register with W

1

00

0000 0110 0100 TO, PD

0000 0000 0000

0000 0110 0010

0000 0000 0001

0000 0110 0011 TO, PD

0000 0110 0fff

C-COMPILER OPTIMIZED

ADDFSR n, k

Add Literal k to FSRn

Move Indirect FSRn to W with pre/post inc/dec

modifier, mm

1

11 0001 0nkk kkkk

00 0000 0001 0nmm

kkkk

MOVIW

n mm

Z

2, 3

k[n]

n mm

Move INDFn to W, Indexed Indirect.

Move W to Indirect FSRn with pre/post inc/dec

modifier, mm

1

11 1111 0nkk 1nmm

00 0000 0001 kkkk

2

2, 3

MOVWI

k[n]

Move W to INDFn, Indexed Indirect.

1

11 1111 1nkk

2

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

3: See Table in the MOVIW and MOVWI instruction descriptions.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 297

PIC16(L)F1508/9

28.2 Instruction Descriptions

ADDFSR

Add Literal to FSRn

ANDLW

AND literal with W

Syntax:

[ label ] ADDFSR FSRn, k

Syntax:

[ label ] ANDLW

0  k  255

k

Operands:

-32  k  31

n  [ 0, 1]

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k)  (W)

Operation:

FSR(n) + k  FSR(n)

Z

Status Affected:

Description:

None

The contents of W register are

AND’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

The signed 6-bit literal ‘k’ is added to

the contents of the FSRnH:FSRnL

register pair.

FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds

will cause the FSR to wrap-around.

ANDWF

AND W with f

ADDLW

Add literal and W

Syntax:

[ label ] ANDWF f,d

Syntax:

[ label ] ADDLW

0  k  255

k

Operands:

0  f  127

d 0,1

Operands:

Operation:

Status Affected:

Description:

(W) + k  (W)

C, DC, Z

Operation:

(W) .AND. (f)  (destination)

Status Affected:

Description:

Z

The contents of the W register are

added to the 8-bit literal ‘k’ and the

result is placed in the W register.

AND the W register with register ‘f’. If

‘d’ is ‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

ASRF

Arithmetic Right Shift

ADDWF

Add W and f

Syntax:

[ label ] ASRF f {,d}

Syntax:

[ label ] ADDWF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d 0,1

Operation:

(f<7>) dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Operation:

(W) + (f)  (destination)

Status Affected:

Description:

C, DC, Z

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the result is

stored in the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. The MSb remains unchanged. If

‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in

register ‘f’.

ADDWFC

ADD W and CARRY bit to f

C

register f

Syntax:

[ label ] ADDWFC

f {,d}

Operands:

0  f  127

d [0,1]

Operation:

(W) + (f) + (C)  dest

Status Affected:

Description:

C, DC, Z

Add W, the Carry flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

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BTFSC

Bit Test f, Skip if Clear

BCF

Bit Clear f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] BCF f,b

Operands:

0  f  127

0  b  7

Operands:

0  f  127

0  b  7

Operation:

skip if (f<b>) = 0

Operation:

0 (f<b>)

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

Bit ‘b’ in register ‘f’ is cleared.

If bit ‘b’, in register ‘f’, is ‘0’, the next

instruction is discarded, and a NOPis

executed instead, making this a

2-cycle instruction.

BTFSS

Bit Test f, Skip if Set

BRA

Relative Branch

Syntax:

[ label ] BTFSS f,b

Syntax:

[ label ] BRA label

[ label ] BRA $+k

Operands:

0  f  127

0  b < 7

Operands:

-256  label - PC + 1  255

-256  k  255

Operation:

skip if (f<b>) = 1

Operation:

(PC) + 1 + k  PC

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOPis

executed instead, making this a

2-cycle instruction.

Add the signed 9-bit literal ‘k’ to the

PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + k.

This instruction is a 2-cycle instruc-

tion. This branch has a limited range.

BRW

Relative Branch with W

Syntax:

[ label ] BRW

None

Operands:

Operation:

Status Affected:

Description:

(PC) + (W)  PC

None

Add the contents of W (unsigned) to

the PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + (W).

This instruction is a 2-cycle instruc-

tion.

BSF

Bit Set f

Syntax:

[ label ] BSF f,b

Operands:

0  f  127

0  b  7

Operation:

1 (f<b>)

Status Affected:

Description:

None

Bit ‘b’ in register ‘f’ is set.

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CALL

Call Subroutine

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CALL

0  k  2047

k

Syntax:

[ label ] CLRWDT

Operands:

Operation:

Operands:

Operation:

None

(PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<6:3>)  PC<14:11>

00h  WDT

0 WDT prescaler,

1 TO

1 PD

Status Affected:

Description:

None

Status Affected:

Description:

TO, PD

Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.

The 11-bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALLis a 2-cycle instruc-

tion.

CLRWDTinstruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT.

Status bits TO and PD are set.

COMF

Complement f

CALLW

Subroutine Call With W

Syntax:

[ label ] COMF f,d

Syntax:

[ label ] CALLW

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

None

(PC) +1  TOS,

(W)  PC<7:0>,

Operation:

(f)  (destination)

(PCLATH<6:0>) PC<14:8>

Status Affected:

Description:

Z

The contents of register ‘f’ are com-

plemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Status Affected:

Description:

None

Subroutine call with W. First, the

return address (PC + 1) is pushed

onto the return stack. Then, the con-

tents of W is loaded into PC<7:0>,

and the contents of PCLATH into

PC<14:8>. CALLWis a 2-cycle

instruction.

DECF

Decrement f

CLRF

Clear f

Syntax:

[ label ] DECF f,d

Syntax:

[ label ] CLRF

0  f  127

f

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

00h  (f)

1 Z

Operation:

(f) - 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

The contents of register ‘f’ are cleared

and the Z bit is set.

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h  (W)

1 Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z) is

set.

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DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - 1  (destination);

skip if result = 0

Operation:

(f) + 1  (destination),

skip if result = 0

Status Affected:

Description:

None

Status Affected:

Description:

None

The contents of register ‘f’ are decre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, then a

NOPis executed instead, making it a

2-cycle instruction.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, a NOPis

executed instead, making it a 2-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO

0  k  2047

k

Syntax:

[ label ] IORLW

0  k  255

(W) .OR. k  (W)

Z

k

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k  PC<10:0>

PCLATH<6:3>  PC<14:11>

Status Affected:

Description:

None

The contents of the W register are

OR’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

GOTOis an unconditional branch. The

11-bit immediate value is loaded into

PC bits <10:0>. The upper bits of PC

are loaded from PCLATH<4:3>. GOTO

is a 2-cycle instruction.

INCF

Increment f

IORWF

Inclusive OR W with f

Syntax:

[ label ] INCF f,d

Syntax:

[ label ] IORWF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) + 1  (destination)

Operation:

(W) .OR. (f)  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

Inclusive OR the W register with regis-

ter ‘f’. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

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LSLF

Logical Left Shift

MOVF

Move f

Syntax:

[ label ] LSLF f {,d}

Syntax:

[ label ] MOVF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f<7>)  C

Operation:

(f)  (dest)

(f<6:0>)  dest<7:1>

0  dest<0>

Status Affected:

Description:

Z

The contents of register f is moved to

a destination dependent upon the

status of d. If d = 0,

destination is W register. If d = 1, the

destination is file register f itself. d = 1

is useful to test a file register since

status flag Z is affected.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the left through the Carry flag.

A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,

the result is placed in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Words:

1

C

register f

0

Cycles:

Example:

MOVF

FSR, 0

After Instruction

LSRF

Logical Right Shift

W

Z

=

value in FSR register

1

Syntax:

[ label ] LSRF f {,d}

Operands:

0  f  127

d [0,1]

Operation:

0  dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. A ‘0’ is shifted into the MSb. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is stored back in register ‘f’.

0

C

register f

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MOVIW

Move INDFn to W

MOVLP

Move literal to PCLATH

Syntax:

[ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

Syntax:

[ label ] MOVLP

0  k  127

k  PCLATH

None

k

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

The 7-bit literal ‘k’ is loaded into the

PCLATH register.

INDFn  W

Effective address is determined by

MOVLW

Move literal to W

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

Syntax:

[ label ] MOVLW

0  k  255

k  (W)

k

Operands:

Operation:

Status Affected:

Description:

After the Move, the FSR value will be

either:

None

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Unchanged

The 8-bit literal ‘k’ is loaded into W reg-

ister. The “don’t cares” will assemble as

‘0’s.

Status Affected:

Z

Words:

1

Cycles:

Example:

Mode

Syntax

mm

00

01

10

11

MOVLW

0x5A

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

After Instruction

W

=

0x5A

MOVWF

Move W to f

[ label ] MOVWF

0  f  127

(W)  (f)

Syntax:

f

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Operands:

Operation:

Status Affected:

Description:

None

Move data from W register to register

‘f’.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

Words:

1

Cycles:

Example:

MOVWF

Before Instruction

OPTION_REG = 0xFF

OPTION_REG

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

W

= 0x4F

After Instruction

OPTION_REG = 0x4F

W

= 0x4F

MOVLB

Move literal to BSR

Syntax:

[ label ] MOVLB

0  k  31

k  BSR

None

k

Operands:

Operation:

Status Affected:

Description:

The 5-bit literal ‘k’ is loaded into the

Bank Select Register (BSR).

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NOP

No Operation

MOVWI

Move W to INDFn

Syntax:

[ label ] NOP

Syntax:

[ label ] MOVWI ++FSRn

[ label ] MOVWI --FSRn

[ label ] MOVWI FSRn++

[ label ] MOVWI FSRn--

[ label ] MOVWI k[FSRn]

Operands:

Operation:

Status Affected:

Description:

Words:

None

No operation

None

No operation.

Operands:

Operation:

n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

1

Cycles:

1

W  INDFn

Effective address is determined by

Example:

NOP

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

After the Move, the FSR value will be

either:

Load OPTION_REG Register

with W

OPTION

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Syntax:

[ label ] OPTION

None

Unchanged

Operands:

Operation:

Status Affected:

Description:

Status Affected:

None

(W)  OPTION_REG

None

Mode

Syntax

mm

00

01

10

11

Move data from W register to

OPTION_REG register.

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

RESET

Software Reset

Syntax:

[ label ] RESET

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Operands:

Operation:

None

Execute a device Reset. Resets the

nRI flag of the PCON register.

Status Affected:

Description:

None

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

This instruction provides a way to

execute a hardware Reset by soft-

ware.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

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RETURN

Return from Subroutine

RETFIE

Syntax:

Return from Interrupt

[ label ] RETFIE

None

Syntax:

[ label ] RETURN

None

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

TOS  PC

None

TOS  PC,

1 GIE

Status Affected:

Description:

None

Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a 2-cycle instruction.

Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global Interrupt Enable bit,

GIE (INTCON<7>). This is a 2-cycle

instruction.

Words:

1

Cycles:

Example:

2

RETFIE

After Interrupt

PC

=

TOS

GIE =

1

RETLW

Syntax:

Return with literal in W

RLF

Rotate Left f through Carry

[ label ] RETLW

0  k  255

k

Syntax:

Operands:

[ label ]

RLF f,d

Operands:

Operation:

0  f  127

d  [0,1]

k  (W);

TOS  PC

Operation:

See description below

C

Status Affected:

Description:

None

Status Affected:

Description:

The W register is loaded with the 8-bit

literal ‘k’. The program counter is

loaded from the top of the stack (the

return address). This is a 2-cycle

instruction.

The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Words:

1

2

C

Register f

Cycles:

Example:

CALL TABLE;W contains table

;offset value

Words:

1

Cycles:

Example:

•

;W now has table value

TABLE

RLF

REG1,0

Before Instruction

ADDWF PC ;W = offset

RETLW k1 ;Begin table

REG1

C

=

1110 0110

0

RETLW k2

;

After Instruction

•

REG1

W

C

=

1110 0110

1100 1100

1

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

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SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW

0 k 255

k

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Status Affected:

Description:

Operands:

0  f  127

d  [0,1]

k - (W) W)

C, DC, Z

Operation:

See description below

C

The W register is subtracted (2’s com-

plement method) from the 8-bit literal

‘k’. The result is placed in the W regis-

ter.

Status Affected:

Description:

The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

C = 0

W  k

C = 1

W  k

C

Register f

DC = 0

DC = 1

W<3:0>  k<3:0>

W<3:0>  k<3:0>

SUBWF

Subtract W from f

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

[ label ] SUBWF f,d

Syntax:

Operands:

0 f 127

d  [0,1]

Operands:

Operation:

00h  WDT,

0 WDT prescaler,

1 TO,

Operation:

(f) - (W) destination)

Status Affected:

Description:

C, DC, Z

0 PD

Subtract (2’s complement method) W

register from register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

C = 0

W  f

The processor is put into Sleep mode

with the oscillator stopped.

C = 1

W  f

DC = 0

DC = 1

W<3:0>  f<3:0>

W<3:0>  f<3:0>

SUBWFB

Subtract W from f with Borrow

SUBWFB f {,d}

Syntax:

Operands:

0  f  127

d  [0,1]

Operation:

(f) – (W) – (B) dest

Status Affected:

Description:

C, DC, Z

Subtract W and the BORROW flag

(CARRY) from register ‘f’ (2’s comple-

ment method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

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SWAPF

Swap Nibbles in f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORLW

0 k 255

k

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k W)

Z

Operation:

(f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

The contents of the W register are

XOR’ed with the 8-bit

literal ‘k’. The result is placed in the

W register.

Status Affected:

Description:

None

The upper and lower nibbles of regis-

ter ‘f’ are exchanged. If ‘d’ is ‘0’, the

result is placed in the W register. If ‘d’

is ‘1’, the result is placed in register ‘f’.

XORWF

Exclusive OR W with f

TRIS

Load TRIS Register with W

Syntax:

[ label ] XORWF f,d

Syntax:

[ label ] TRIS f

5  f  7

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

(W)  TRIS register ‘f’

None

Operation:

(W) .XOR. (f) destination)

Status Affected:

Description:

Z

Move data from W register to TRIS

register.

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

When ‘f’ = 7, TRISC is loaded.

Exclusive OR the contents of the W

register with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in regis-

ter ‘f’.

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PIC16(L)F1508/9

NOTES:

DS40001609E-page 308

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

29.0 ELECTRICAL SPECIFICATIONS

(†)

29.1 Absolute Maximum Ratings

Ambient temperature under bias...................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on pins with respect to VSS

on VDD pin

PIC16F1508/9 ........................................................................................................... -0.3V to +6.5V

PIC16LF1508/9 ......................................................................................................... -0.3V to +4.0V

on MCLR pin ........................................................................................................................... -0.3V to +9.0V

on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)

Maximum current

on VSS pin⁽¹⁾

-40°C  TA  +85°C .............................................................................................................. 250 mA

+85°C  TA  +125°C ............................................................................................................. 85 mA

on VDD pin⁽¹⁾

-40°C  TA  +85°C .............................................................................................................. 250 mA

+85°C  TA  +125°C ............................................................................................................. 85 mA

Sunk by any standard I/O pin ............................................................................................................... 50 mA

Sourced by any standard I/O pin .......................................................................................................... 50 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA

Total power dissipation⁽²⁾...............................................................................................................................800 mW

Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be

limited by the device package power dissipation characterizations, see Table 29-6 to calculate device

specifications.

2: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 309

PIC16(L)F1508/9

29.2 Standard Operating Conditions

The standard operating conditions for any device are defined as:

Operating Voltage:

Operating Temperature:

VDDMIN VDD VDDMAX

TA_MIN TA TA_MAX

VDD — Operating Supply Voltage⁽¹⁾

PIC16LF1508/9

VDDMIN (Fosc  16 MHz).......................................................................................................... +1.8V

VDDMIN (16 MHz < Fosc  20 MHz) ......................................................................................... +2.5V

VDDMAX .................................................................................................................................... +3.6V

PIC16F1508/9

VDDMIN (Fosc  16 MHz).......................................................................................................... +2.3V

VDDMIN (16 MHz < Fosc  20 MHz) ......................................................................................... +2.5V

VDDMAX .................................................................................................................................... +5.5V

TA — Operating Ambient Temperature Range

Industrial Temperature

TA_MIN ...................................................................................................................................... -40°C

TA_MAX .................................................................................................................................... +85°C

Extended Temperature

TA_MIN ...................................................................................................................................... -40°C

TA_MAX .................................................................................................................................. +125°C

Note 1: See Parameter D001, DC Characteristics: Supply Voltage.

DS40001609E-page 310

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 29-1:

VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16F1508/9 ONLY

Rev. 10-000130A

8/6/2013

5.5

2.5

2.3

0

16

20

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 29-8 for each Oscillator mode’s supported frequencies.

FIGURE 29-2:

VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16LF1508/9 ONLY

Rev. 10-000131A

8/5/2013

3.6

2.5

1.8

0

16

20

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 29-8 for each Oscillator mode’s supported frequencies.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 311

PIC16(L)F1508/9

29.3 DC Characteristics

TABLE 29-1: SUPPLY VOLTAGE

PIC16LF1508/9

Standard Operating Conditions (unless otherwise stated)

PIC16F1508/9

Param.

No.

Sym.

Characteristic

Supply Voltage

Min.

Typ†

Max.

Units

Conditions

D001

VDD

VDDMIN

1.8

2.5

VDDMAX

3.6

—

V

FOSC  16 MHz

FOSC  20 MHz

D001

2.3

2.5

—

5.5

V

FOSC  16 MHz

FOSC  20 MHz

(1)

D002*

VDR

RAM Data Retention Voltage

1.5

1.7

—

V

Device in Sleep mode

D002*

(2)

D002A* VPOR

Power-on Reset Release Voltage

—

1.6

—

V

D002A*

(2)

D002B* VPORR*

Power-on Reset Rearm Voltage

—

0.8

1.5

—

V

D002B*

D003

VFVR

Fixed Voltage Reference Voltage

1x gain (1.024V nominal)

2x gain (2.048V nominal)

4x gain (4.096V nominal)

VDD 2.5V, -40°C  TA  +85°C

VDD 4.75V, -40°C  TA  +85°C

-4

-3

—

+4

+7

%

(2)

D004*

SVDD

VDD Rise Rate

0.05

—

V/ms Ensures that the Power-on Reset

signal is released properly.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

2: See Figure 29-3, POR and POR REARM with Slow Rising VDD.

DS40001609E-page 312

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 29-3:

POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

SVDD

VSS

(1)

NPOR

POR REARM

VSS

(2)

(3)

TPOR

TVLOW

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 313

PIC16(L)F1508/9

TABLE 29-2: SUPPLY CURRENT (IDD)^(1,2)

PIC16LF1508/9

PIC16F1508/9

Standard Operating Conditions (unless otherwise stated)

Conditions

Note

Param.

No.

Device

Characteristics

Min.

Typ†

Max. Units

VDD

D010

—

8

20

25

A

1.8

3.0

FOSC = 32 kHz,

LP Oscillator,

-40°C  TA  +85°C

10

D010

—

15

17

31

33

A

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

FOSC = 32 kHz,

LP Oscillator,

-40°C  TA  +85°C

21

39

D011

60

100

180

220

280

240

360

320

410

500

65

FOSC = 1 MHz,

XT Oscillator

100

130

170

140

250

210

280

340

30

FOSC = 1 MHz,

XT Oscillator

D012

FOSC = 4 MHz,

XT Oscillator

FOSC = 4 MHz,

XT Oscillator

D013

FOSC = 1 MHz,

External Clock (ECM),

Medium Power mode

55

100

—

65

85

110

140

190

310

A

2.3

3.0

5.0

1.8

3.0

FOSC = 1 MHz,

External Clock (ECM),

Medium Power mode

115

210

D014

FOSC = 4 MHz,

External Clock (ECM),

Medium Power mode

—

180

240

295

3.2

270

365

460

12

A

2.3

3.0

5.0

1.8

3.0

FOSC = 4 MHz,

External Clock (ECM),

Medium Power mode

D015

FOSC = 31 kHz,

LFINTOSC,

-40°C  TA  +85°C

5.4

20

—

13

15

17

28

30

36

A

2.3

3.0

5.0

FOSC = 31 kHz,

LFINTOSC,

-40°C  TA  +85°C

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can

be extended by the formula IR = VDD/2REXT (mA) with REXT in k.

DS40001609E-page 314

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 29-2: SUPPLY CURRENT (IDD)^(1,2)(CONTINUED)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1508/9

PIC16F1508/9

Conditions

Note

Param.

No.

Device

Characteristics

Min.

Typ†

Max. Units

VDD

D016

—

215

275

270

300

350

410

630

530

660

730

600

970

780

1000

1090

1030

360

480

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

3.0

FOSC = 500 kHz,

HFINTOSC

D016

450

FOSC = 500 kHz,

HFINTOSC

500

620

D017*

660

FOSC = 8 MHz,

HFINTOSC

970

750

FOSC = 8 MHz,

HFINTOSC

1100

1200

940

D018

FOSC = 16 MHz,

HFINTOSC

1400

1200

1550

1700

1500

FOSC = 16 MHz,

HFINTOSC

D019A

FOSC = 20 MHz,

External Clock (ECH),

High-Power mode

—

1060

1220

1600

1800

A

3.0

5.0

FOSC = 20 MHz,

External Clock (ECH),

High-Power mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can

be extended by the formula IR = VDD/2REXT (mA) with REXT in k.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 315

PIC16(L)F1508/9

TABLE 29-2: SUPPLY CURRENT (IDD)^(1,2)(CONTINUED)

PIC16LF1508/9

PIC16F1508/9

Standard Operating Conditions (unless otherwise stated)

Conditions

Note

Param.

No.

Device

Characteristics

Min.

Typ†

Max. Units

VDD

D019B

—

6

8

16

22

A

1.8

3.0

FOSC = 32 kHz,

External Clock (ECL),

Low-Power mode

D019B

—

13

15

16

19

32

28

31

36

35

55

A

2.3

3.0

5.0

1.8

3.0

FOSC = 32 kHz,

External Clock (ECL),

Low-Power mode

D019C

FOSC = 500 kHz,

External Clock (ECL),

Low-Power mode

—

31

38

52

65

A

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

3.0

FOSC = 500 kHz,

External Clock (ECL),

Low-Power mode

44

74

D020

140

250

210

280

350

1135

210

330

290

380

470

1700

FOSC = 4 MHz,

EXTRC (Note 3)

FOSC = 4 MHz,

EXTRC (Note 3)

D021

FOSC = 20 MHz,

HS Oscillator

—

1170

1555

1800

2300

A

3.0

5.0

FOSC = 20 MHz,

HS Oscillator

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can

be extended by the formula IR = VDD/2REXT (mA) with REXT in k.

DS40001609E-page 316

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 29-3: POWER-DOWN CURRENTS (IPD)^(1,2)

Operating Conditions: (unless otherwise stated)

Low-Power Sleep Mode

PIC16LF1508/9

PIC16F1508/9

Param.

Low-Power Sleep Mode, VREGPM = 1

Conditions

Max.

+85°C +125°C

Max.

Device Characteristics

Min.

Typ†

Units

No.

VDD

Note

D022

Base IPD

—

0.020

0.025

0.25

0.30

0.40

9.8

1.0

2.0

3.0

4.0

6.0

16

8.0

9.0

10

12

15

18

20

26

A

1.8

3.0

2.3

3.0

5.0

2.3

3.0

5.0

WDT, BOR, FVR and SOSC

disabled, all Peripherals inactive

D022

WDT, BOR, FVR and SOSC

disabled, all Peripherals inactive,

Low-Power Sleep mode

D022A

Base IPD

WDT, BOR, FVR and SOSC

disabled, all Peripherals inactive,

Normal Power Sleep mode,

VREGPM = 0

10.3

11.5

18

21

D023

—

0.26

0.44

0.43

0.53

0.64

15

2.0

3.0

6.0

7.0

8.0

28

9.0

10

15

20

22

30

33

35

37

39

20

30

40

10

14

17

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

3.0

5.0

3.0

5.0

WDT Current

D023A

FVR Current

18

30

18

33

19

35

20

37

D024

6.0

17

BOR Current

7.0

17

8.0

20

D24A

0.1

4.0

5.0

8.0

LPBOR Current

0.35

0.45

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be

used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.

3: ADC clock source is FRC.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 317

PIC16(L)F1508/9

TABLE 29-3: POWER-DOWN CURRENTS (IPD)^(1,2)(CONTINUED)

Operating Conditions: (unless otherwise stated)

Low-Power Sleep Mode

PIC16LF1508/9

Low-Power Sleep Mode, VREGPM = 1

PIC16F1508/9

Conditions

Param.

No.

Max.

+85°C +125°C

Max.

Device Characteristics

Min.

Typ†

Units

VDD

Note

SOSC Current

D025

—

0.7

2.3

1.0

2.4

6.9

0.11

0.12

0.30

0.35

0.45

250

280

7

4.0

8.0

6.0

8.5

20

1.5

2.7

4.0

5.0

8.0

—

9.0

12

11

20

25

9.0

10

11

13

16

—

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

SOSC Current

D026

ADC Current (Note 3),

No conversion in progress

ADC Current (Note 3),

No conversion in progress

D026A*

ADC Current (Note 3),

Conversion in progress

—

ADC Current (Note 3),

Conversion in progress

—

D027

22

23

35

37

38

25

27

37

38

40

Comparator,

CxSP = 0

8

17

Comparator,

CxSP = 0

18

19

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be

used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.

3: ADC clock source is FRC.

DS40001609E-page 318

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 29-4: I/O PORTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O PORT:

D030

D030A

D031

with TTL buffer

—

0.8

V

4.5V  VDD  5.5V

0.15 VDD

0.2 VDD

0.3 VDD

0.8

1.8V  VDD  4.5V

2.0V  VDD  5.5V

with Schmitt Trigger buffer

2

with I C levels

with SMbus levels

MCLR, OSC1 (EXTRC mode)

OSC1 (HS mode)

Input High Voltage

I/O PORT:

2.7V  VDD  5.5V

D032

D033

0.2 VDD

0.3 VDD

(Note 1)

VIH

D040

with TTL buffer

2.0

—

V

4.5V  VDD 5.5V

1.8V  VDD  4.5V

D040A

0.25 VDD +

0.8

D041

with Schmitt Trigger buffer

0.8 VDD

0.7 VDD

2.1

—

V

2.0V  VDD  5.5V

2.7V  VDD  5.5V

2

with I C levels

with SMbus levels

MCLR

D042

0.8 VDD

0.7 VDD

0.9 VDD

D043A

D043B

OSC1 (HS mode)

OSC1 (EXTRC mode)

VDD  2.0V (Note 1)

(2)

IIL

Input Leakage Current

D060

I/O Ports

—

± 5

± 125

± 1000

± 200

nA

VSS  VPIN  VDD,

Pin at high-impedance, 85°C

VSS  VPIN  VDD,

Pin at high-impedance, 125°C

(3)

D061

MCLR

± 50

VSS  VPIN  VDD,

Pin at high-impedance, 85°C

IPUR

VOL

Weak Pull-up Current

D070*

25

100

140

200

300

A

VDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS

Output Low Voltage

D080

I/O Ports

IOL = 8 mA, VDD = 5V

IOL = 6 mA, VDD = 3.3V

IOL = 1.8 mA, VDD = 1.8V

—

0.6

—

V

VOH

Output High Voltage

D090

I/O Ports

IOH = 3.5 mA, VDD = 5V

IOH = 3 mA, VDD = 3.3V

IOH = 1 mA, VDD = 1.8V

VDD - 0.7

D101*

COSC2 Capacitive Loading Specifications on Output Pins

OSC2 pin

In XT, HS, LP modes when

external clock is used to drive

OSC1

—

15

50

pF

D101A* CIO

All I/O pins

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an

external clock in EXTRC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 319

PIC16(L)F1508/9

TABLE 29-5: MEMORY PROGRAMMING SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

No.

Program Memory

Programming Specifications

Voltage on MCLR/VPP pin

VDD for Bulk Erase

D110

D112

D113

VIHH

8.0

2.7

—

9.0

V

(Note 2)

VPBE

VPEW

VDDMAX

VDD for Write or Row Erase

VDDMIN

D114

IPPPGM Current on MCLR/VPP during

Erase/Write

—

1.0

—

mA

D115

IDDPGM Current on VDD during

Erase/Write

—

5.0

—

mA

Program Flash Memory

D121

EP

Cell Endurance

10K

—

E/W -40C  TA  +85C

(Note 1)

D122

D123

D124

VPRW

TIW

VDD for Read/Write

VDDMIN

—

2

VDDMAX

2.5

V

Self-timed Write Cycle Time

Characteristic Retention

ms

TRETD

—

40

—

Year Provided no other

specifications are violated

D125

EHEFC High-Endurance Flash Cell

100K

—

E/W 0C  TA  +60°C, lower

byte last 128 addresses

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Self-write and Block Erase.

2: Required only if single-supply programming is disabled.

TABLE 29-6: THERMAL CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Typ.

Units

Conditions

20-pin DIP package

No.

TH01

^JA

Thermal Resistance Junction to Ambient

62.2

77.7

87.3

46.2

32.8

27.5

C/W

20-pin SOIC package

20-pin SSOP package

20-pin QFN 4X4mm package

20-pin UQFN 4X4mm package

TH02

^JC

Thermal Resistance Junction to Case

20-pin DIP package

23.1

31.1

13.2

27.4

150

—

C/W

C

20-pin SOIC package

20-pin SSOP package

20-pin QFN 4X4mm package

20-pin UQFN 4X4mm package

TH03

TH04

TH05

TH06

TH07

TJMAX

PD

Maximum Junction Temperature

Power Dissipation

W

PD = PINTERNAL + PI/O

(1)

PINTERNAL Internal Power Dissipation

—

W

PINTERNAL = IDD x VDD

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

(2)

PDER

—

W

PDER = PDMAX (TJ - TA)/JA

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature; TJ = Junction Temperature

DS40001609E-page 320

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PIC16(L)F1508/9

29.4 AC Characteristics

Timing Parameter Symbology has been created with one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

CLKIN

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCKx

SS

SDIx

do

dt

SDO

Data in

I/O PORT

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 29-4:

LOAD CONDITIONS

Rev. 10-000133A

8/1/2013

Load Condition

CL

VSS

Legend: CL=50 pF for all pins

 2011-2015 Microchip Technology Inc.

DS40001609E-page 321

PIC16(L)F1508/9

FIGURE 29-5:

CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

CLKIN

OS12

OS03

OS11

OS02

CLKOUT

(CLKOUT mode)

Note:

See Table 29-9.

TABLE 29-7: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

No.

(1)

OS01

FOSC

External CLKIN Frequency

DC

—

0.5

4

MHz External Clock (ECL)

MHz

kHz

External Clock (ECM)

DC

—

20

External Clock (ECH)

LP Oscillator

(1)

—

0.1

1

32.768

—

4

Oscillator Frequency

MHz XT Oscillator

—

4

MHz HS Oscillator

1

—

20

4

MHz HS Oscillator, VDD > 2.7V

MHz EXTRC, VDD > 2.0V

DC

27

250

50

—

(1)

OS02

TOSC

External CLKIN Period

—



µs

ns

µs

ns

µs

ns

LP Oscillator

XT Oscillator

HS Oscillator

External Clock (EC)

LP Oscillator

XT Oscillator

HS Oscillator

EXTRC

—



—



—



(1)

Oscillator Period

30.5

—

250

50

250

200

2

10,000

1,000

—

(1)

OS03

TCY

Instruction Cycle Time

TCY

—

DC

—

TCY = 4/FOSC

LP Oscillator

XT Oscillator

HS Oscillator

LP Oscillator

XT Oscillator

HS Oscillator

OS04*

TosH,

TosL

External CLKIN High

External CLKIN Low

100

20

0

—

OS05*

TosR,

TosF

External CLKIN Rise

External CLKIN Fall

—

0

—

0

—

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-

sumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external

clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

DS40001609E-page 322

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PIC16(L)F1508/9

TABLE 29-8: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Freq.

Tolerance

Sym.

Characteristic

Min. Typ† Max. Units

Conditions

OS08

HFOSC

Internal Calibrated HFINTOSC

Frequency

±2%

—

16.0

—

MHz VDD = 3.0V, TA = 25°C,

(1)

(Note 2)

OS09

LFOSC

Internal LFINTOSC Frequency

—

31

5

—

kHz (Note 3)

s

OS10* TIOSC ST HFINTOSC

Wake-up from Sleep Start-up Time

OS10A* TLFOSC ST LFINTOSC

Wake-up from Sleep Start-up Time

These parameters are characterized but not tested.

15

—

0.5

—

ms

-40°C  TA  +125°C

*

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

2: See Figure 29-6: “HFINTOSC Frequency Accuracy over Device VDD and Temperature”,

Figure 30-72: “HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1508/9 Only”, and

Figure 30-73: “HFINTOSC Accuracy Over Temperature, 2.3V  VDD 5.5V”.

3: See Figure 30-70: “LFINTOSC Frequency over VDD and Temperature, PIC16LF1508/9 Only”, and

Figure 30-71: “LFINTOSC Frequency over VDD and Temperature, PIC16F1508/9”.

FIGURE 29-6:

HFINTOSC FREQUENCY ACCURACY OVER VDD AND TEMPERATURE

Rev. 10-000135A

7/30/2013

125

85

12ꢀ

-4.5ꢀ to +7ꢀ

60

25

4.5ꢀ

12ꢀ

0

-40

1.8

2.3

5.5

VDD (V)

Note:

See Figure 30-72: “HFINTOSC Accuracy Over Temperature, VDD = 1.8V, PIC16LF1508/9 Only”, and

Figure 30-73: “HFINTOSC Accuracy Over Temperature, 2.3V VDD  5.5V”.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 323

PIC16(L)F1508/9

FIGURE 29-7:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

FOSC

OS12

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS18

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

TABLE 29-9: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

No.

(1)

OS11

OS12

OS13

TosH2ckL

TosH2ckH

TckL2ioV

FOSC to CLKOUT

—

70

72

20

ns

3.3V  VDD 5.0V

(1)

FOSC to CLKOUT

CLKOUT to Port out valid

Port input valid before CLKOUT

(1)

OS14

OS15

OS16

TioV2ckH

TosH2ioV

TosH2ioI

TOSC + 200 ns

—

50

—

70*

—

ns

Fosc (Q1 cycle) to Port out valid

—

3.3V  VDD 5.0V

Fosc (Q2 cycle) to Port input invalid

50

(I/O in setup time)

OS17

TioV2osH

TioR

Port input valid to Fosc(Q2 cycle)

(I/O in setup time)

20

—

ns

OS18*

OS19*

Port output rise time

Port output fall time

—

40

15

72

32

VDD = 1.8V

3.3V  VDD 5.0V

TioF

—

28

15

55

30

VDD = 1.8V

3.3V  VDD 5.0V

OS20*

OS21*

Tinp

Tioc

INT pin input high or low time

25

—

ns

Interrupt-on-change new input level time

*

†

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC.

DS40001609E-page 324

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PIC16(L)F1508/9

FIGURE 29-8:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Start-up Time

Internal Reset⁽¹⁾

Watchdog Timer

Reset⁽¹⁾

31

34

I/O pins

Note 1:Asserted low.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 325

PIC16(L)F1508/9

TABLE 29-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

TMCL

Characteristic

Min. Typ† Max. Units

Conditions

No.

30

MCLR Pulse Width (low)

2

—

s

31

TWDTLP Low-Power Watchdog Timer

Time-out Period

10

16

27

ms VDD = 3.3V-5V,

1:16 Prescaler used

Oscillator Start-up Timer Period⁽¹⁾

TOST

32

—

1024

—

TOSC

33*

34*

TPWRT Power-up Timer Period

40

—

65

—

140

2.0

ms PWRTE = 0

s

TIOZ

I/O high-impedance from MCLR Low

or Watchdog Timer Reset

35

VBOR

Brown-out Reset Voltage⁽²⁾

2.55 2.70 2.85

V

BORV = 0

2.35 2.45 2.58

1.80 1.90 2.05

V

BORV = 1 (PIC16LF1508/9)

BORV = 1(PIC16LF1508/9)

36*

37*

38

VHYST

Brown-out Reset Hysteresis

0

1

25

16

75

35

mV -40°C  TA  +85°C

s VDD  VBOR

TBORDC Brown-out Reset DC Response Time

VLPBOR Low-Power Brown-out Reset Voltage

1.8

2.1

2.5

V

LPBOR = 1

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.

2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

FIGURE 29-9:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR and VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

37

Reset

33

(due to BOR)

DS40001609E-page 326

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PIC16(L)F1508/9

FIGURE 29-10:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

TABLE 29-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

TT0H

Characteristic

Min.

Typ†

Max.

Units

Conditions

No.

40*

T0CKI High Pulse Width

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

41*

42*

TT0L

TT0P

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

ns N = prescale value

45*

46*

47*

TT1H

TT1L

TT1P

T1CKI High Synchronous, No Prescaler

0.5 TCY + 20

—

ns

Time

Synchronous, with Prescaler

Asynchronous

15

ns

30

ns

T1CKI Low Synchronous, No Prescaler

0.5 TCY + 20

ns

Time

Synchronous, with Prescaler

Asynchronous

15

30

ns

T1CKI Input Synchronous

Period

Greater of:

30 or TCY + 40

N

ns N = prescale value

Asynchronous

60

—

ns

48

FT1

Secondary Oscillator Input Frequency Range

(Oscillator enabled by setting bit T1OSCEN)

32.4

32.768

33.1

kHz

49*

TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC

—

7 TOSC

—

Timers in Sync

mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 327

PIC16(L)F1508/9

FIGURE 29-11:

CLC PROPAGATION TIMING

Rev. 10-000031A

7/30/2013

LCx_in[n]⁽¹⁾

CLC

CLCxINn

CLCx

LCx_out⁽¹⁾

Input time

Module

Output time

CLC

Input time

CLC

Module

CLC

Output time

CLC01

CLC02

CLC03

Note 1: See FIGURE 24-1:, Configurable Logic Cell Block Diagram, to identify specific CLC signals.

TABLE 29-12: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min. Typ† Max. Units

Conditions

CLC01* TCLCIN

CLC02* TCLC

CLC input time

CLC module input to output propagation time

—

7

—

ns

—

24

12

—

ns VDD = 1.8V

ns VDD > 3.6V

CLC03* TCLCOUT CLC output time

Rise Time

Fall Time

—

OS18

OS19

45

—

(Note 1)

CLC04* FCLCMAX CLC maximum switching frequency

MHz

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1:See Table 29-9 for OS18 and OS19 rise and fall times.

DS40001609E-page 328

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE 29-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS^(1,2,3)

Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA = 25°C

Param.

No.

Sym.

Characteristic

Resolution

Min.

Typ†

Max. Units

Conditions

AD01

AD02

AD03

NR

—

±1

10

±1.7

±1

bit

EIL

EDL

Integral Error

LSb VREF = 3.0V

Differential Error

LSb No missing codes

VREF = 3.0V

AD04

AD05

AD06

AD07

AD08

EOFF Offset Error

—

±1

—

±2.5

±2.0

VDD

VREF

10

LSb VREF = 3.0V

EGN Gain Error

VREF Reference Voltage

VAIN Full-Scale Range

1.8

VSS

—

V

VREF = (VRPOS - VRNEG) (Note 4)

ZAIN Recommended Impedance of

Analog Voltage Source

k Can go higher if external 0.01F capacitor is

present on input pin.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:Total Absolute Error includes integral, differential, offset and gain errors.

2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.

3: See Section 30.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

4: ADC VREF is selected by ADPREF<0> bit.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 329

PIC16(L)F1508/9

FIGURE 29-12:

ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)

BSF ADCON0, GO

AD133

Q4

1 TCY

AD131

AD130

ADC_clk

9

8

7

6

3

2

1

0

ADC Data

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

FIGURE 29-13:

ADC CONVERSION TIMING (ADC CLOCK FROM FRC)

BSF ADCON0, GO

AD133

Q4

1 TCY

AD131

AD130

ADC_clk

9

8

7

3

2

1

0

6

ADC Data

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1:If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the

SLEEPinstruction to be executed.

DS40001609E-page 330

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PIC16(L)F1508/9

TABLE 29-14: ADC CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD130* TAD

ADC Clock Period (TADC)

ADC Internal FRC Oscillator Period (TFRC)

AD131 TCNV Conversion Time

(not including Acquisition Time)

AD132* TACQ Acquisition Time

AD133* THCD Holding Capacitor Disconnect Time

1.0

—

2.0

11

6.0

—

s FOSC-based

s ADCS<2:0> = x11(ADC FRC mode)

TAD Set GO/DONE bit to conversion

complete

(1)

—

5.0

—

s

—

1/2 TAD

1/2 TAD + 1TCY

—

FOSC-based

ADCS<2:0> = x11 (ADC FRC mode)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The ADRES register may be read on the following TCY cycle.

TABLE 29-15: COMPARATOR SPECIFICATIONS⁽¹⁾

Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA = 25°C

Param.

No.

Sym.

Characteristics

Input Offset Voltage

Min.

Typ.

Max.

Units

Comments

CM01

VIOFF

—

±7.5

±60

mV CxSP = 1,

VICM = VDD/2

CM02

VICM

Input Common Mode Voltage

Common Mode Rejection Ration

Response Time Rising Edge

Response Time Falling Edge

Response Time Rising Edge

Response Time Falling Edge

0

—

50

VDD

—

V

CM03

CMRR

—

dB

CM04A

CM04B

CM04C

CM04D

CM05*

400

200

1200

550

—

800

400

—

ns

s

CxSP = 1

CxSP = 0

(2)

TRESP

—

TMC2OV Comparator Mode Change to

Output Valid

10

CM06

CHYSTER Comparator Hysteresis

—

25

—

mV CxHYS = 1,

CxSP = 1

*

These parameters are characterized but not tested.

Note 1: See Section 30.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

2: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to

VDD.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 331

PIC16(L)F1508/9

TABLE 29-16: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS⁽¹⁾

Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA = 25°C

Param.

No.

Sym.

Characteristics

Step Size

Min.

Typ.

Max.

Units

Comments

DAC01*

DAC02*

DAC03*

DAC04*

*

CLSB

—

VDD/32

—

 1/2

—

V

LSb



CACC

CR

Absolute Accuracy

Unit Resistor Value (R)

Settling Time⁽²⁾

5K

CST

—

10

s

These parameters are characterized but not tested.

Note 1: See Section 30.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

2: Settling time measured while DACR<4:0> transitions from ‘00000’ to ‘01111’.

FIGURE 29-14:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK

DT

US121

US122

US120

Refer to Figure 29-4 for load conditions.

Note:

TABLE 29-17: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Symbol

Characteristic

Min.

Max.

Units

Conditions

US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid

—

80

100

45

ns

3.0V  VDD  5.5V

1.8V  VDD  5.5V

3.0V  VDD  5.5V

1.8V  VDD  5.5V

3.0V  VDD  5.5V

1.8V  VDD  5.5V

US121 TCKRF

Clock out rise time and fall time

(Master mode)

50

US122 TDTRF

Data-out rise time and fall time

45

50

FIGURE 29-15:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK

DT

US125

US126

Note: Refer to Figure 29-4 for load conditions.

DS40001609E-page 332

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PIC16(L)F1508/9

TABLE 29-18: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Symbol

Characteristic

Min.

Max. Units

Conditions

US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK  (DT hold time)

10

15

—

ns

US126 TCKL2DTL Data-hold after CK  (DT hold time)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 333

PIC16(L)F1508/9

FIGURE 29-16:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

SP81

SCK

(CKP = 0)

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

bit 6 - - - - - -1

MSb

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

LSb In

SP74

SP73

Note: Refer to Figure 29-4 for load conditions.

FIGURE 29-17:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81

SCK

(CKP = 0)

SP71

SP73

SP72

SP79

SCK

(CKP = 1)

SP80

SP78

bit 6 - - - - - -1

LSb

MSb

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

SP74

Note: Refer to Figure 29-4 for load conditions.

LSb In

DS40001609E-page 334

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 29-18:

SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK

(CKP = 0)

SP83

SP79

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

MSb

SDO

SDI

bit 6 - - - - - -1

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

SP73

LSb In

Note: Refer to Figure 29-4 for load conditions.

FIGURE 29-19:

SPI SLAVE MODE TIMING (CKE = 1)

SP82

SP70

SS

SP83

SCK

(CKP = 0)

SP72

SP71

SCK

(CKP = 1)

SP80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note: Refer to Figure 29-4 for load conditions.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 335

PIC16(L)F1508/9

TABLE 29-19: SPI MODE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

Symbol

Characteristic

Min.

Typ† Max. Units

Conditions

No.

SP70* TSSL2SCH, SS to SCK or SCK input

2.25 TCY

—

ns

TSSL2SCL

SP71* TSCH

SP72* TSCL

SCK input high time (Slave mode)

SCK input low time (Slave mode)

1 TCY + 20

100

—

ns

SP73* TDIV2SCH, Setup time of SDI data input to SCK

TDIV2SCL

edge

SP74* TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK

edge

100

—

ns

SP75* TDOR

SDO data output rise time

—

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns 3.0V  VDD  5.5V

ns 1.8V  VDD  5.5V

SP76* TDOF

SDO data output fall time

—

ns

SP77* TSSH2DOZ SS to SDO output high-impedance

10

ns

SP78* TSCR

SCK output rise time

(Master mode)

—

ns 3.0V  VDD  5.5V

ns 1.8V  VDD  5.5V

ns

—

SP79* TSCF

SCK output fall time (Master mode)

—

SP80* TSCH2DOV, SDO data output valid after SCK

TSCL2DOV edge

—

ns 3.0V  VDD  5.5V

ns 1.8V  VDD  5.5V

ns

—

SP81* TDOV2SCH, SDO data output setup to SCK edge

TDOV2SCL

1 Tcy

SP82* TSSL2DOV

SDO data output valid after SS

edge

—

50

—

ns

SP83* TSCH2SSH, SS after SCK edge

1.5 TCY + 40

TSCL2SSH

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS40001609E-page 336

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 29-20:

I²C BUS START/STOP BITS TIMING

SCL

SP93

SP91

SP90

SP92

SDA

Stop

Condition

Start

Condition

Note: Refer to Figure 29-4 for load conditions.

TABLE 29-20: I²C BUS START/STOP BITS REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

Symbol

Characteristic

Min. Typ Max. Units

Conditions

No.

SP90* TSU:STA Start condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns Only relevant for Repeated

Start condition

SP91* THD:STA Start condition

Hold time

4000

600

ns After this period, the first

clock pulse is generated

SP92* TSU:STO Stop condition

Setup time

4700

600

ns

SP93 THD:STO Stop condition

Hold time

4000

600

ns

*

These parameters are characterized but not tested.

FIGURE 29-21:

I²C BUS DATA TIMING

SP100

SP102

SP103

SP101

SCL

SP90

SP91

SP106

SP107

SP92

SDA

In

SP110

SP109

SDA

Out

Note: Refer to Figure 29-4 for load conditions.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 337

PIC16(L)F1508/9

TABLE 29-21: I²C BUS DATA REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

Symbol

Characteristic

Min.

Max. Units

Conditions

No.

SP100* THIGH

Clock high time

Clock low time

100 kHz mode

4.0

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY

4.7

—

SP101* TLOW

100 kHz mode

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY

—

SP102* TR

SP103* TF

SDA and SCL rise 100 kHz mode

1000

ns

time

400 kHz mode

20 + 0.1CB 300

CB is specified to be from

10-400 pF

SDA and SCL fall

time

100 kHz mode

400 kHz mode

—

250

ns

20 + 0.1CB 250

CB is specified to be from

10-400 pF

SP106* THD:DAT Data input hold time 100 kHz mode

400 kHz mode

0

—

0.9

—

ns

s

ns

s

0

SP107* TSU:DAT Data input setup

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

250

100

—

(Note 2)

(Note 1)

—

SP109* TAA

Output valid from

clock

3500

—

SP110* TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

SP111 CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification), before the SCL line is released.

DS40001609E-page 338

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”

represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each

temperature range.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 339

PIC16(L)F1508/9

FIGURE 30-1:

IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16LF1508/9 ONLY

18

16

14

12

10

8

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

6

4

2

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-2:

IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16F1508/9 ONLY

30

Max.

Max: 85°C + 3ı

Typical: 25°C

25

20

15

10

5

Typical

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 340

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-3:

IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1508/9 ONLY

350

Typical: 25°C

300

250

200

150

100

50

4 MHz EXTRC

4 MHz XT

1 MHz XT

1 MHz EXTRC

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-4:

IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1508/9 ONLY

400

350

300

250

200

150

100

50

Max: 85°C + 3ı

4 MHz XT

4 MHz EXTRC

1 MHz XT

1 MHz EXTRC

2.8

0

1.6

1.8

2.0

2.2

2.4

2.6

3.0

3.2

3.4

3.6

3.8

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 341

PIC16(L)F1508/9

FIGURE 30-5:

IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1508/9 ONLY

400

350

300

250

200

150

100

50

4 MHz EXTRC

4 MHz XT

Typical: 25°C

1 MHz XT

1 MHz EXTRC

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 30-6:

IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1508/9 ONLY

500

450

400

350

300

250

200

150

100

50

4 MHz XT

Max: 85°C + 3ı

4 MHz EXTRC

1 MHz XT

1 MHz EXTRC

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 342

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-7:

IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz,

PIC16LF1508/9 ONLY

14

12

10

8

Max.

Typical

6

4

Max: 85°C + 3ı

Typical: 25°C

2

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-8:

IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz,

PIC16F1508/9 ONLY

25

Max.

20

15

10

5

Typical

Max: 85°C + 3ı

Typical: 25°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 343

PIC16(L)F1508/9

FIGURE 30-9:

IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz,

PIC16LF1508/9 ONLY

50

45

40

35

30

25

20

15

10

5

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-10:

IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz,

PIC16F1508/9 ONLY

60

50

40

30

20

10

Max.

Typical

Max: 85°C + 3ı

Typical: 25°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 344

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-11:

IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE,

PIC16LF1508/9 ONLY

300

250

200

150

100

50

Typical: 25°C

4 MHz

1 MHz

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-12:

IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE,

PIC16LF1508/9 ONLY

350

300

250

200

150

100

50

Max: 85°C + 3ı

4 MHz

1 MHz

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 345

PIC16(L)F1508/9

FIGURE 30-13:

IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE,

PIC16F1508/9 ONLY

350

300

250

200

150

100

50

4 MHz

Typical: 25°C

1 MHz

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 30-14:

IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE,

PIC16F1508/9 ONLY

400

350

300

250

200

150

100

50

4 MHz

Max: 85°C + 3ı

1 MHz

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 346

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-15:

IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,

PIC16LF1508/9 ONLY

1.4

1.2

1.0

0.8

0.6

0.4

0.2

20 MHz

16 MHz

Typical: 25°C

8 MHz

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

DD (V)

3.0

3.2

3.4

3.6

3.8

V

FIGURE 30-16:

IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,

PIC16LF1508/9 ONLY

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

20 MHz

Max: 85°C + 3ı

16 MHz

8 MHz

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

DD (V)

3.0

3.2

3.4

3.6

3.8

V

 2011-2015 Microchip Technology Inc.

DS40001609E-page 347

PIC16(L)F1508/9

FIGURE 30-17:

IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,

PIC16F1508/9 ONLY

1.4

1.2

1.0

0.8

0.6

0.4

0.2

20 MHz

16 MHz

Typical: 25°C

8 MHz

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 30-18:

IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,

PIC16F1508/9 ONLY

1.6

20 MHz

16 MHz

Max: 85°C + 3ı

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

8 MHz

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 348

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-19:

IDD, LFINTOSC, FOSC = 31 kHz, PIC16LF1508/9 ONLY

12

Max.

Max: 85°C + 3ı

Typical: 25°C

10

8

6

Typical

4

2

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-20:

IDD, LFINTOSC, FOSC = 31 kHz, PIC16F1508/9 ONLY

25

Max.

20

15

10

5

Typical

Max: 85°C + 3ı

Typical: 25°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 349

PIC16(L)F1508/9

FIGURE 30-21:

IDD, MFINTOSC, FOSC = 500 kHz, PIC16LF1508/9 ONLY

400

350

300

250

200

150

100

50

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-22:

IDD, MFINTOSC, FOSC = 500 kHz, PIC16F1508/9 ONLY

450

Max: 85°C + 3ı

Typical: 25°C

Max.

400

350

300

250

200

150

100

50

Typical

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 350

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-23:

IDD TYPICAL, HFINTOSC, PIC16LF1508/9 ONLY

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Typical: 25°C

16 MHz

8 MHz

4 MHz

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-24:

IDD MAXIMUM, HFINTOSC, PIC16LF1508/9 ONLY

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Max: 85°C + 3ı

16 MHz

8 MHz

4 MHz

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 351

PIC16(L)F1508/9

FIGURE 30-25:

IDD TYPICAL, HFINTOSC, PIC16F1508/9 ONLY

1.2

16 MHz

1.0

0.8

0.6

0.4

0.2

8 MHz

4 MHz

Typical: 25°C

2.5

0.0

2.0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 30-26:

IDD MAXIMUM, HFINTOSC, PIC16F1508/9 ONLY

1.4

1.2

1.0

0.8

0.6

0.4

0.2

16 MHz

8 MHz

4 MHz

Max: 85°C + 3ı

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 352

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-27:

IDD TYPICAL, HS OSCILLATOR, PIC16LF1508/9 ONLY

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Typical: 25°C

20 MHz

8 MHz

4 MHz

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

DD (V)

3.0

3.2

3.4

3.6

3.8

V

FIGURE 30-28:

IDD MAXIMUM, HS OSCILLATOR, PIC16LF1508/9 ONLY

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Max: 85°C + 3ı

20 MHz

8 MHz

4 MHz

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

DD (V)

3.0

3.2

3.4

3.6

3.8

V

 2011-2015 Microchip Technology Inc.

DS40001609E-page 353

PIC16(L)F1508/9

FIGURE 30-29:

IDD TYPICAL, HS OSCILLATOR, PIC16F1508/9 ONLY

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

20 MHz

Typical: 25°C

8 MHz

4 MHz

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 30-30:

IDD MAXIMUM, HS OSCILLATOR, PIC16F1508/9 ONLY

2.5

Max: 85°C + 3ı

20 MHz

2.0

1.5

1.0

0.5

8 MHz

4 MHz

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 354

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-31:

IPD BASE, LOW-POWER SLEEP MODE, PIC16LF1508/9 ONLY

450

400

350

300

250

200

150

100

50

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-32:

IPD BASE, LOW-POWER SLEEP MODE, VREGPM = 1, PIC16F1508/9 ONLY

600

Max.

Max: 85°C + 3ı

Typical: 25°C

500

400

300

200

100

Typical

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 355

PIC16(L)F1508/9

FIGURE 30-33:

IPD, WATCHDOG TIMER (WDT), PIC16LF1508/9 ONLY

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

2.8

0.0

1.6

1.8

2.0

2.2

2.4

2.6

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-34:

IPD, WATCHDOG TIMER (WDT), PIC16F1508/9 ONLY

1.4

Max.

1.2

1.0

0.8

0.6

0.4

0.2

Typical

Max: 85°C + 3ı

Typical: 25°C

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 356

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-35:

IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1508/9 ONLY

45

40

35

30

25

20

15

10

5

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-36:

IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1508/9 ONLY

30

Max.

25

20

15

10

5

Typical

Max: 85°C + 3ı

Typical: 25°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 357

PIC16(L)F1508/9

FIGURE 30-37:

IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC16LF1508/9 ONLY

10

9

Max.

Max: 85°C + 3ı

Typical: 25°C

8

7

6

5

4

3

2

1

0

Typical

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-38:

IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1508/9 ONLY

12

Max.

Max: 85°C + 3ı

Typical: 25°C

10

8

Typical

6

4

2

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

DS40001609E-page 358

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-39:

IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC16F1508/9 ONLY

12

Max.

Max: 85°C + 3ı

Typical: 25°C

10

8

Typical

6

4

2

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 30-40:

IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1508/9 ONLY

14

Max.

Max: 85°C + 3ı

Typical: 25°C

12

10

8

Typical

6

4

2

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 359

PIC16(L)F1508/9

FIGURE 30-41:

IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16LF1508/9 ONLY

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

2.8

0.0

1.6

1.8

2.0

2.2

2.4

2.6

VDD (V)

3.0

3.2

3.4

3.6

3.8

FIGURE 30-42:

IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16F1508/9 ONLY

16

14

12

10

8

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

6

4

2

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 360

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-43:

IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16LF1508/9 ONLY

14

12

10

8

Max.

Typical

6

4

Max: 85°C + 3ı

Typical: 25°C

2

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-44:

IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16F1508/9 ONLY

30

25

20

15

10

5

Max.

Typical

Max: 85°C + 3ı

Typical: 25°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 361

PIC16(L)F1508/9

FIGURE 30-45:

IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC16LF1508/9 ONLY

40

35

30

25

20

15

10

5

Max.

Typical

Max: 85°C + 3ı

Typical: 25°C

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-46:

IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC16F1508/9 ONLY

60

50

40

30

20

Max.

Typical

Max: 85°C + 3ı

Typical: 25°C

10

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

DS40001609E-page 362

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-47:

VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1508/9 ONLY

6

Max: 125°C + 3ı

Typical: 25°C

5

4

3

2

1

0

Min: -40°C - 3ı

Min. (-40°C)

Typical (25°C)

Max. (125°C)

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

I

OH (mA)

FIGURE 30-48:

VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1508/9 ONLY

5

Max: 125°C + 3ı

Typical: 25°C

Min: -40°C - 3ı

Max. (125°C)

4

3

2

1

0

Typical (25°C)

Min. (-40°C)

0

10

20

30

40

50

OL (mA)

60

70

80

90

100

I

 2011-2015 Microchip Technology Inc.

DS40001609E-page 363

PIC16(L)F1508/9

FIGURE 30-49:

VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V

3.5

Max: 125°C + 3ı

Typical: 25°C

3.0

2.5

2.0

1.5

1.0

0.5

Min: -40°C - 3ı

Min. (-40°C)

Typical (25°C)

-9

Max. (125°C)

-5

0.0

-15

-13

-11

-7

-3

-1

I

OH (mA)

FIGURE 30-50:

VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V

3.0

Max: 125°C + 3ı

2.5

2.0

1.5

1.0

0.5

Typical: 25°C

Min: -40°C - 3ı

Min. (-40°C)

Typical (25°C)

Max. (125°C)

0.0

0

5

10

15

20

25

30

35

40

I

OL (mA)

DS40001609E-page 364

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-51:

VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1508/9 ONLY

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Max: 125°C + 3ı

Typical: 25°C

Min: -40°C - 3ı

Max. (125°C)

Min. (-40°C)

Typical (25°C)

-4.5

-4.0

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

I

OH (mA)

FIGURE 30-52:

VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1508/9 ONLY

1.8

Max: 125°C + 3ı

Typical: 25°C

Min: -40°C - 3ı

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Max. (125°C)

Min. (-40°C)

Typical (25°C)

0

1

2

3

4

5

6

7

8

9

10

I

OL (mA)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 365

PIC16(L)F1508/9

FIGURE 30-53:

POR RELEASE VOLTAGE

1.70

1.68

1.66

1.64

1.62

1.60

1.58

1.56

1.54

1.52

Max.

Typical

Min.

Max: Typical + 3ı

Typical: 25°C

Min: Typical - 3ı

1.50

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

FIGURE 30-54:

POR REARM VOLTAGE, PIC16F1508/9 ONLY

1.54

1.52

1.50

1.48

1.46

1.44

1.42

1.40

1.38

1.36

Max: Typical + 3ı

Typical: 25°C

Min: Typical - 3ı

Max.

Typical

Min.

1.34

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

DS40001609E-page 366

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-55:

BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1508/9 ONLY

2.00

Max.

1.95

1.90

1.85

Typical

Min.

Max: Typical + 3ı

Min: Typical - 3ı

1.80

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

FIGURE 30-56:

BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1508/9 ONLY

60

50

Max.

Max: Typical + 3ı

Typical: 25°C

Min: Typical - 3ı

40

30

20

10

0

Typical

Min.

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 367

PIC16(L)F1508/9

FIGURE 30-57:

BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1508/9 ONLY

2.60

Max.

2.55

2.50

2.45

2.40

2.35

Typical

Min.

Max: Typical + 3ı

Min: Typical - 3ı

2.30

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

FIGURE 30-58:

BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1508/9 ONLY

70

Max.

60

50

40

30

20

10

Max: Typical + 3ı

Typical: 25°C

Min: Typical - 3ı

Typical

Min.

0

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

DS40001609E-page 368

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-59:

BROWN-OUT RESET VOLTAGE, BORV = 0

2.80

2.75

2.70

2.65

2.60

Max.

Typical

Min.

Max: Typical + 3ı

Min: Typical - 3ı

2.55

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 369

PIC16(L)F1508/9

FIGURE 30-60:

LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0

2.50

Max.

Max: Typical + 3ı

Min: Typical - 3ı

2.40

2.30

2.20

2.10

2.00

1.90

Typical

Min.

1.80

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

FIGURE 30-61:

LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0

45

40

35

30

25

20

15

10

5

Max: Typical + 3ı

Max.

Typical: 25°C

Min: Typical - 3ı

Typical

Min.

0

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

DS40001609E-page 370

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-62:

WDT TIME-OUT PERIOD

24

22

20

18

16

14

12

Max.

Typical

Min.

Max: Typical + 3ı (-40°C to +125°C)

Typical: statistical mean @ 25°C

Min: Typical - 3ı (-40°C to +125°C)

10

1.5

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

6.0

FIGURE 30-63:

PWRT PERIOD

100

Max: Typical + 3ı (-40°C to +125°C)

Typical: statistical mean @ 25°C

Min: Typical - 3ı (-40°C to +125°C)

90

80

70

60

50

Max.

Typical

Min.

40

1.5

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

6.0

 2011-2015 Microchip Technology Inc.

DS40001609E-page 371

PIC16(L)F1508/9

FIGURE 30-64:

FVR STABILIZATION PERIOD

60

Max: Typical + 3ı

50

40

30

20

10

Typical: statistical mean @ 25°C

Max.

Typical

Note:

The FVR Stabilization Period applies when:

1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices.

2) when exiting sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices

In all other cases, the FVR is stable when released from RESET.

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

DS40001609E-page 372

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-65:

COMPARATOR HYSTERESIS, NORMAL POWER MODE (CxSP = 1, CxHYS = 1)

40

35

30

25

20

15

10

5

Max.

Typical

Min.

Max: Typical + 3ı

Typical: 25°C

Min: Typical - 3ı

0

1.5

2.0

2.5

3.0

3.5

4.0

VDD (V)

4.5

5.0

5.5

6.0

FIGURE 30-66:

COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1)

8

7

6

5

4

3

2

1

Max.

Typical

Max: Typical + 3ı

Typical: 25°C

Min: Typical - 3ı

Min.

0

1.5

2.0

2.5

3.0

3.5

4.0

VDD (V)

4.5

5.0

5.5

6.0

 2011-2015 Microchip Technology Inc.

DS40001609E-page 373

PIC16(L)F1508/9

FIGURE 30-67:

COMPARATOR RESPONSE TIME, NORMAL POWER MODE (CxSP = 1)

350

300

250

200

150

100

50

Max.

Typical

Max: Typical + 3ı

Typical: 25°C

0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 30-68:

COMPARATOR RESPONSE TIME OVER TEMPERATURE,

NORMAL POWER MODE (CxSP = 1)

400

350

300

250

200

150

100

50

Max: 125°C + 3ı

Typical: 25°C

Min: -45°C - 3ı

Max. (125°C)

Typical (25°C)

Min. (-40°C)

0

1.5

2.0

2.5

3.0

3.5

4.0

DD (V)

4.5

5.0

5.5

6.0

V

DS40001609E-page 374

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-69:

COMPARATOR INPUT OFFSET AT 25°C, NORMAL POWER MODE (CxSP = 1),

PIC16F1508/9 ONLY

50

40

30

20

10

0

Max.

Typical

Min.

-10

-20

-30

-40

Max: Typical + 3ı

Typical: 25°C

Min: Typical - 3ı

-50

0.0

1.0

2.0

3.0

4.0

5.0

Common Mode Voltage (V)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 375

PIC16(L)F1508/9

FIGURE 30-70:

LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1508/9 ONLY

36

34

32

30

28

26

24

22

Max.

Typical

Min.

Max: Typical + 3ı (-40°C to +125°C)

Typical: statistical mean @ 25°C

Min: Typical - 3ı (-40°C to +125°C)

20

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 30-71:

LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1508/9 ONLY

36

34

32

30

28

26

24

22

Max.

Typical

Min.

Max: Typical + 3ı (-40°C to +125°C)

Typical: statistical mean @ 25°C

Min: Typical - 3ı (-40°C to +125°C)

20

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

6.0

DS40001609E-page 376

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-72:

HFINTOSC ACCURACY OVER TEMPERATURE, VDD = 1.8V,

PIC16LF1508/9 ONLY

8%

6%

Max: Typical + 3ı

Max.

Typical

Min.

Typical: statistical mean

Min: Typical - 3ı

4%

2%

0%

-2%

-4%

-6%

-8%

-10%

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

FIGURE 30-73:

HFINTOSC ACCURACY OVER TEMPERATURE, 2.3V  VDD 5.5V

8%

6%

Max: Typical + 3ı

Typical: statistical mean

Max.

Min: Typical - 3ı

4%

2%

Typical

Min.

0%

-2%

-4%

-6%

-8%

-10%

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

 2011-2015 Microchip Technology Inc.

DS40001609E-page 377

PIC16(L)F1508/9

FIGURE 30-74:

SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, PIC16LF1508/9 ONLY

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Max.

Typical

Max: 85°C + 3ı

Typical: 25°C

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

DS40001609E-page 378

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 30-75:

LOW-POWER SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE,

VREGPM = 1, PIC16F1508/9 ONLY

35

30

25

20

15

10

5

Max.

Typical

Max: 85°C + 3ı

Typical: 25°C

0

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

6.0

FIGURE 30-76:

SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 0,

PIC16F1508/9 ONLY

12

10

8

Max.

Typical

6

4

Max: 85°C + 3ı

Typical: 25°C

2

0

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

6.0

 2011-2015 Microchip Technology Inc.

DS40001609E-page 379

PIC16(L)F1508/9

31.1 MPLAB X Integrated Development

Environment Software

31.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers (MCU) and dsPIC^®digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

hardware development tool that runs on Windows^®,

Linux and Mac OS^®X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

• Integrated Development Environment

- MPLAB^®X IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

• Simulators

- MPLAB X SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

Feature-Rich Editor:

- PICkit™ 3

• Color syntax highlighting

• Device Programmers

- MPLAB PM3 Device Programmer

• Smart code completion makes suggestions and

provides hints as you type

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Automatic code formatting based on user-defined

rules

• Third-party development tools

• Live parsing

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker

DS40001609E-page 380

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

31.2 MPLAB XC Compilers

31.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16, and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other relo-

catable object files and archives to create an execut-

able file. MPLAB XC Compiler uses the assembler to

produce its object file. Notable features of the assem-

bler include:

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

31.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

31.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multipurpose

source files

• Directives that allow complete control over the

assembly process

 2011-2015 Microchip Technology Inc.

DS40001609E-page 381

PIC16(L)F1508/9

31.6 MPLAB X SIM Software Simulator

31.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB X SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

31.9 PICkit 3 In-Circuit Debugger/

Programmer

The MPLAB PICkit 3 allows debugging and program-

ming of PIC and dsPIC Flash microcontrollers at a most

affordable price point using the powerful graphical user

interface of the MPLAB IDE. The MPLAB PICkit 3 is

connected to the design engineer’s PC using a full-

speed USB interface and can be connected to the tar-

get via a Microchip debug (RJ-11) connector (compati-

ble with MPLAB ICD 3 and MPLAB REAL ICE). The

connector uses two device I/O pins and the Reset line

to implement in-circuit debugging and In-Circuit Serial

Programming™ (ICSP™).

31.7 MPLAB REAL ICE In-Circuit

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

31.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a mod-

ular, detachable socket assembly to support various

package types. The ICSP cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.

The emulator is field upgradable through future firmware

downloads in MPLAB X IDE. MPLAB REAL ICE offers

significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

DS40001609E-page 382

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

31.11 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

31.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide applica-

tion firmware and source code for examination and

modification.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

• Demonstration Boards from companies, such as

MikroElektronika, Digilent^®and Olimex

• Embedded Ethernet Solutions from companies,

such as EZ Web Lynx, WIZnet and IPLogika^®

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a line of evaluation kits and demonstra-

®

tion software for analog filter design, KEELOQ security

ICs, CAN, IrDA^®, PowerSmart battery management,

SEEVAL^®evaluation system, Sigma-Delta ADC, flow

rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 383

PIC16(L)F1508/9

32.0 PACKAGING INFORMATION

32.1 Package Marking Information

20-Lead PDIP (300 mil)

Example

PIC16F1508

XXXXXXXXXXXXXXXXX

e

3

-E/P

YYWWNNN

1120123

20-Lead SOIC (7.50 mm)

Example

PIC16F1508

e

3

-E/SO

1120123

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro^®device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

DS40001609E-page 384

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

Package Marking Information (Continued)

20-Lead SSOP (5.30 mm)

Example

PIC16F1508

e

3

-E/SS

1120123

20-Lead QFN (4x4x0.9 mm)

20-Lead UQFN (4x4x0.5 mm)

Example

PIC16

F1508

PIN 1

e

3

E/ML

120123

 2011-2015 Microchip Technology Inc.

DS40001609E-page 385

PIC16(L)F1508/9

32.2 Package Details

The following sections give the technical details of the packages.

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DS40001609E-page 386

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011-2015 Microchip Technology Inc.

DS40001609E-page 387

PIC16(L)F1508/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001609E-page 388

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011-2015 Microchip Technology Inc.

DS40001609E-page 389

PIC16(L)F1508/9

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DS40001609E-page 390

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011-2015 Microchip Technology Inc.

DS40001609E-page 391

PIC16(L)F1508/9

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DS40001609E-page 392

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

ꢛꢗꢋꢄꢜ 6ꢉꢇꢀ)ꢋꢆꢀ*ꢉ$)ꢀꢊ%ꢇꢇꢆꢃ)ꢀꢑꢄꢊ7ꢄꢏꢆꢀ&ꢇꢄ-ꢂꢃꢏ$+ꢀꢑꢅꢆꢄ$ꢆꢀ$ꢆꢆꢀ)ꢋꢆꢀꢒꢂꢊꢇꢉꢊꢋꢂꢑꢀ"ꢄꢊ7ꢄꢏꢂꢃꢏꢀꢎꢑꢆꢊꢂ(ꢂꢊꢄ)ꢂꢉꢃꢀꢅꢉꢊꢄ)ꢆ&ꢀꢄ)ꢀ

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 2011-2015 Microchip Technology Inc.

DS40001609E-page 393

PIC16(L)F1508/9

20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM B)

(DATUM A)

2X

0.20 C

2X

TOP VIEW

0.20 C

0.10 C

A1

C

A

SEATING

PLANE

20X

(A3)

0.08 C

C A B

SIDE VIEW

0.10

D2

L

0.10

C A B

E2

2

1

K

N

NOTE 1

20X b

0.10

C A B

e

BOTTOM VIEW

Microchip Technology Drawing C04-255A Sheet 1 of 2

DS40001609E-page 394

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Terminals

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Terminal Width

Terminal Length

N

20

0.50 BSC

0.50

e

A

A1

A3

E

E2

D

D2

b

L

0.45

0.00

0.55

0.05

0.02

0.127 REF

4.00 BSC

2.70

4.00 BSC

2.70

2.60

2.80

2.60

0.20

0.30

0.20

2.80

0.30

0.50

-

0.25

0.40

-

Terminal-to-Exposed-Pad

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-255A Sheet 2 of 2

 2011-2015 Microchip Technology Inc.

DS40001609E-page 395

PIC16(L)F1508/9

20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

20

1

2

C2 Y2

G1

Y1

X1

E

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.50 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

X2

Y2

C1

C2

X1

Y1

G1

2.80

4.00

Contact Pad Spacing

Contact Pad Width (X20)

Contact Pad Length (X20)

Contact Pad to Center Pad (X20)

0.30

0.80

0.20

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2255A

DS40001609E-page 396

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A (10/2011)

Original release.

Revision B (6/2013)

Updated Electrical Specifications and added

Characterization Data.

Revision C (7/2013)

Corrected upper and lower bit definitions of address,

Section 3.2. Added clarification of Buffer Gain

Selection bits, Section 13.2. Removed "Preliminary"

status from Section 30. Updated Figures 15-1, 29-9.

Clarified information in Registers 7-1,13-1, 15-2.

Clarified information in Tables 29-5, 29-10, 29-13.

Removed Index.

Revision D (10/2014)

Document re-release.

Revision E (10/2015)

Added Section 3.2 High-Endurance Flash. Updated

Figure 26-1; Registers 4-2, 7-5, and 26-3; Sections

22.4.2, 24.1.5, 26.9.1.2, 26.11.1, and 29.1; and Table

26-2.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 397

PIC16(L)F1508/9

THE MICROCHIP WEBSITE

CUSTOMER SUPPORT

Microchip provides online support via our website at

www.microchip.com. This website is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the website contains the following information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers

should

contact

their

distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the website

at: http://www.microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip website at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

DS40001609E-page 398

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

[X]

PART NO.

X

/XX

XXX

-

Examples:

Device Tape and Reel

Option

Temperature

Range

Package

Pattern

a)

PIC16LF1508T - I/SO

Tape and Reel,

Industrial temperature,

SOIC package

b)

c)

PIC16F1509 - I/P

Industrial temperature

PDIP package

Device:

PIC16LF1508, PIC16F1508,

PIC16LF1509, PIC16F1509

PIC16F1508 - E/ML 298

Extended temperature,

QFN package

Tape and Reel

Option:

Blank = Standard packaging (tube or tray)

T

= Tape and Reel⁽¹⁾

QTP pattern #298

Temperature

Range:

I

E

=

-40C to +85C (Industrial)

-40C to +125C (Extended)

Package:⁽²⁾

GZ

ML

P

SO

SS

=

UQFN

QFN

Plastic DIP

SOIC

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This

identifier is used for ordering purposes and is

not printed on the device package. Check

with your Microchip Sales Office for package

availability with the Tape and Reel option.

SSOP

Pattern:

QTP, SQTP, Code or Special Requirements

(blank otherwise)

2:

For other small form-factor package

availability and marking information, please

visit www.microchip.com/packaging or

contact your local sales office.

 2011-2015 Microchip Technology Inc.

DS40001609E-page 399

PIC16(L)F1508/9

NOTES:

DS40001609E-page 400

 2011-2015 Microchip Technology Inc.

PIC16(L)F1508/9

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

32

OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,

Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-63277-918-2

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2011-2015 Microchip Technology Inc.

DS40001609E-page 401

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

Germany - Dusseldorf

Tel: 49-2129-3766400

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Germany - Karlsruhe

Tel: 49-721-625370

India - Pune

Tel: 91-20-3019-1500

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Austin, TX

Tel: 512-257-3370

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Dongguan

Tel: 86-769-8702-9880

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

Cleveland

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Poland - Warsaw

Tel: 48-22-3325737

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Sweden - Stockholm

Tel: 46-8-5090-4654

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Novi, MI

UK - Wokingham

Tel: 44-118-921-5800

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Tel: 248-848-4000

Fax: 44-118-921-5820

Houston, TX

Tel: 281-894-5983

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

New York, NY

Tel: 631-435-6000

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

San Jose, CA

Tel: 408-735-9110

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-673-0699

Fax: 905-673-6509

07/14/15

DS40001609E-page 402

 2011-2015 Microchip Technology Inc.


型号：	PIC16LF1508T-I/SS
厂家：	MICROCHIP
描述：	8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO20, 5.30 MM, LEAD FREE, PLASTIC, SSOP-20 时钟微控制器光电二极管外围集成电路
文件：	总401页 (文件大小：3703K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16LF1508T-I/SS [MICROCHIP]

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