PIC16LF1782-I/SO [MICROCHIP]
8-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PDSO28, 7.50 MM, LEAD FREE, PLASTIC, SOIC-28;型号: | PIC16LF1782-I/SO |
厂家: | MICROCHIP |
描述: | 8-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PDSO28, 7.50 MM, LEAD FREE, PLASTIC, SOIC-28 光电二极管 |
文件: | 总434页 (文件大小:6461K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16(L)F1782/3
28-Pin 8-Bit Advanced Analog Flash Microcontroller
High-Performance RISC CPU:
Extreme Low-Power Management
PIC16LF1782/3 with XLP:
• Only 49 Instructions
• Sleep mode: 50 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Timer1 Oscillator: 500 nA @ 32 kHz
• Operating Current:
• Operating Speed:
- DC – 32 MHz clock input
- DC – 125 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
- 8 A @ 32 kHz, 1.8V, typical
- 32 A/MHz @ 1.8V, typical
• 16-Level Deep Hardware Stack with optional
Overflow/Underflow Reset
Analog Peripheral Features:
• Direct, Indirect and Relative Addressing modes:
• Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
• Analog-to-Digital Converter (ADC):
- Fully differential 12-bit converter
- Up to 75 ksps conversion rate
- 11 single-ended channels
Memory Features:
- 5 differential channels
• Up to 4 KW Flash Program Memory:
- Self-programmable under software control
- Programmable code protection
- Programmable write protection
• 256 Bytes of Data EEPROM
- Positive and negative reference selection
• 8-bit Digital-to-Analog Converter (DAC):
- Output available externally
- Positive and negative reference selection
- Internal connections to comparators, op amps,
Fixed Voltage Reference (FVR) and ADC
• Up to 512 Bytes of RAM
• Three High-Speed Comparators:
- 50 ns response time @ VDD = 5V
- Rail-to-rail inputs
High Performance PWM Controller:
• Two Programmable Switch Mode Controller
(PSMC) modules:
- Software selectable hysteresis
- Internal connection to op amps, FVR and DAC
• Two Operational Amplifiers:
- Digital and/or analog feedback control of
PWM frequency and pulse begin/end times
- 16-bit Period, Duty Cycle and Phase
- 16 ns clock resolution
- Rail-to-rail inputs/outputs
- High/Low selectable Gain Bandwidth Product
- Internal connection to DAC and FVR
• Fixed Voltage Reference (FVR):
- Supports Single PWM, Complementary,
Push-Pull and 3-phase modes of operation
- Dead-band control with 8-bit counter
- Auto-shutdown and restart
- Leading and falling edge blanking
- Burst mode
-
1.024V, 2.048V and 4.096V output levels
- Internal connection to ADC, comparators and
DAC
I/O Features:
• 25 I/O Pins and 1 Input-only Pin:
• High current sink/source for LED drivers
• Individually programmable interrupt-on-change pins
• Individually programmable weak pull-ups
• Individual input level selection
• Individually programmable slew rate control
• Individually programmable open drain outputs
2011-2014 Microchip Technology Inc.
DS40001579E-page 1
PIC16(L)F1782/3
Digital Peripheral Features:
General Microcontroller Features:
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Power-Saving Sleep mode
• Power-on Reset (POR)
• Enhanced Timer1:
• Power-up Timer (PWRT)
- 16-bit timer/counter with prescaler
- External Gate Input mode
• Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with Selectable Trip Point
• Extended Watchdog Timer (WDT)
- Dedicated low-power 32 kHz oscillator driver
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• In-Circuit Serial ProgrammingTM (ICSPTM
)
• In-Circuit Debug (ICD)
• Two Capture/Compare/PWM modules (CCP):
- 16-bit capture, maximum resolution 12.5 ns
- 16-bit compare, max resolution 31.25 ns
- 10-bit PWM, max frequency 32 kHz
• Enhanced Low-Voltage Programming (LVP)
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1782/3)
- 2.3V to 5.5V (PIC16F1782/3)
• Master Synchronous Serial Port (SSP) with SPI
and I2CTM with:
- 7-bit address masking
- SMBus/PMBusTM compatibility
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART):
- RS-232, RS-485 and LIN compatible
- Auto-baud detect
- Auto-wake-up on start
Oscillator Features:
• Operate up to 32 MHz from Precision Internal
Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
32 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• 32.768 kHz Timer1 Oscillator:
- Available as system clock
- Low-power RTC
• External Oscillator Block with:
- 4 crystal/resonator modes up to 32 MHz
using 4x PLL
- 3 external clock modes up to 32 MHz
• 4x Phase-Locked Loop (PLL)
• Fail-Safe Clock Monitor:
- Detect and recover from external oscillator
failure
• Two-Speed Start-up:
- Minimize latency between code execution
and external oscillator start-up
DS40001579E-page 2
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
PIC16(L)F178X Family Types
Device
PIC12(L)F1782
PIC16(L)F1783
PIC16(L)F1784
PIC16(L)F1786
PIC16(L)F1787
PIC16(L)F1788
PIC16(L)F1789
(1)
(1)
(2)
(2)
(2)
2048
4096
4096
8192
8192
256
256
256
256 25 11
512 25 11
512 36 15
3
3
4
4
4
4
4
2
2
3
2
3
2
3
1/0
1/0
1/0
1/0
1/0
1/3
1/3
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2
2
3
3
3
4
4
2
2
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
I
I
I
I
I
Y
Y
Y
Y
Y
Y
Y
256 1024 25 11
256 1024 36 15
(3) 16384 256 2048 25 11
(3) 16384 256 2048 36 15
Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS40001579
2: DS40001637
3: DS40001675
PIC16(L)F1782/3 Data Sheet, 28-Pin Flash, 8-bit Advanced Analog MCUs.
PIC16(L)F1784/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs.
PIC16(L)F1788/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs.
Note:
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
2011-2014 Microchip Technology Inc.
DS40001579E-page 3
PIC16(L)F1782/3
Pin Diagram – 28-Pin SPDIP, SOIC, SSOP
1
28
27
26
25
24
23
RB7/ICSPDAT
RB6/ICSPCLK
RB5
VPP/MCLR/RE3
2
RA0
3
RA1
4
RB4
RB3
RB2
RA2
5
RA3
6
RA4
7
22
21
RB1
RB0
RA5
8
VSS
20
19
18
17
16
15
9
VDD
VSS
RA7
10
11
12
RA6
RC0
RC1
RC2
RC3
RC7
RC6
RC5
RC4
13
14
Note:
See Table 1 for the location of all peripheral functions.
Pin Diagram – 28-Pin QFN, UQFN
1
2
3
4
5
6
7
21
20
19
18
17 VDD
16
15
RB3
RB2
RB1
RB0
RA2
RA3
RA4
RA5
VSS
RA7
RA6
PIC16(L)F1782/3
VSS
RC7
Note:
See Table 1 for the location of all peripheral functions.
DS40001579E-page 4
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
PIN ALLOCATION TABLE
TABLE 1:
28-PIN ALLOCATION TABLE (PIC16(L)F1782/3)
RA0
RA1
RA2
2
3
4
27 AN0
28 AN1
—
—
C1IN0-
C2IN0-
C3IN0-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
Y
Y
Y
—
—
—
C1IN1- OPA1OUT
C2IN1-
C3IN1-
1
AN2
VREF-
C1IN0+
C2IN0+
C3IN0+
—
DACOUT1
DACVREF-
RA3
RA4
RA5
5
6
7
2
3
4
7
AN3
—
VREF+
—
C1IN1+
C1OUT
—
DACVREF+
—
T0CKI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
IOC
Y
Y
Y
Y
—
—
—
OPA1IN+
OPA1IN-
—
—
—
—
AN4
—
—
C2OUT
C2OUT(1)
SS
—
RA6 10
—
—
OSC2/
CLKOUT
RA7
9
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP1(1)
—
—
—
—
—
—
—
IOC
Y
Y
Y
OSC1/
CLKIN
PSMC1CLK
PSMC2CLK
RB0 21 18 AN12
RB1 22 19 AN10
C2IN1+
INT/
IOC
—
PSMC1IN
PSMC2IN
C1IN3- OPA2OUT
C2IN3-
—
IOC
—
C3IN3-
RB2 23 20 AN8
RB3 24 21 AN9
—
—
—
OPA2IN-
OPA2IN+
—
—
—
—
—
—
—
CCP2(1)
—
—
—
—
IOC
IOC
Y
Y
CLKR
—
C1IN2-
C2IN2-
C3IN2-
RB4 25 22 AN11
RB5 26 23 AN13
—
—
—
C3IN1+
C3OUT
—
—
—
—
—
—
—
—
T1G
—
—
—
—
—
—
—
—
—
—
IOC
Y
Y
Y
—
—
SDO(1) IOC
SDI(1)
IOC
RB6 27 24
—
—
—
TX(1)
ICSPCLK
CK(1) SDA(1)
RB7 28 25
—
—
—
—
—
—
DACOUT2
—
—
—
—
—
RX(1) SCK(1) IOC
Y
Y
ICSPDAT
—
DT(1)
—
SCL(1)
—
RC0 11
RC1 12
8
9
T1OSO
T1CKI
PSMC1A
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1OSI
—
PSMC1B
PSMC1C
PSMC1D
CCP2
CCP1
—
—
—
—
—
—
IOC
IOC
IOC
Y
Y
Y
—
—
—
RC2 13 10
RC3 14 11
—
SCK
SCL
RC4 15 12
—
—
—
—
—
—
PSMC1E
—
—
—
SDI
SDA
IOC
Y
—
RC5 16 13
RC6 17 14
—
—
—
—
—
—
—
—
—
—
—
—
PSMC1F
PSMC2A
—
—
SDO
—
IOC
IOC
Y
Y
—
—
TX
CK
RC7 18 15
—
—
—
—
—
—
—
—
—
—
—
—
PSMC2B
—
—
—
RX
DT
—
—
IOC
IOC
Y
Y
—
RE3
1
26
—
MCLR/
VPP
VDD 20 17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
VSS 8, 5,
19 16
Note 1:
Alternate pin function selected with the APFCON1 (Register 13-1) register.
2011-2014 Microchip Technology Inc.
DS40001579E-page 5
PIC16(L)F1782/3
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization................................................................................................................................................................. 15
4.0 Device Configuration .................................................................................................................................................................. 40
5.0 Resets ........................................................................................................................................................................................ 46
6.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 54
7.0 Reference Clock Module ............................................................................................................................................................ 72
8.0 Interrupts .................................................................................................................................................................................... 75
9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 88
10.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 92
11.0 Watchdog Timer (WDT) ............................................................................................................................................................. 93
12.0 Data EEPROM and Flash Program Memory Control................................................................................................................. 97
13.0 I/O Ports ................................................................................................................................................................................... 110
14.0 Interrupt-On-Change ................................................................................................................................................................ 132
15.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 136
16.0 Temperature Indicator Module ................................................................................................................................................. 139
17.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 141
18.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 156
19.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 159
20.0 Comparator Module.................................................................................................................................................................. 164
21.0 Timer0 Module ......................................................................................................................................................................... 173
22.0 Timer1 Module with Gate Control............................................................................................................................................. 176
23.0 Timer2 Module ......................................................................................................................................................................... 187
24.0 Programmable Switch Mode Control (PSMC).......................................................................................................................... 191
25.0 Capture/Compare/PWM Modules ............................................................................................................................................ 247
26.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 257
27.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 311
28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 340
29.0 Instruction Set Summary.......................................................................................................................................................... 342
30.0 Electrical Specifications............................................................................................................................................................ 356
31.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 389
32.0 Development Support............................................................................................................................................................... 413
33.0 Packaging Information.............................................................................................................................................................. 418
The Microchip Web Site..................................................................................................................................................................... 432
Customer Change Notification Service .............................................................................................................................................. 432
Customer Support.............................................................................................................................................................................. 432
Product Identification System............................................................................................................................................................. 433
DS40001579E-page 6
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
1.0
DEVICE OVERVIEW
The PIC16(L)F1782/3 are described within this data
sheet. The block diagram of these devices are shown in
Figure 1-1. The available peripherals are shown in
Table 1-1, and the pin out descriptions are shown in
Table 1-2.
TABLE 1-1:
DEVICE PERIPHERAL SUMMARY
Peripheral
Analog-to-Digital Converter (ADC)
Fixed Voltage Reference (FVR)
Reference Clock Module
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Temperature Indicator
Capture/Compare/PWM (CCP/ECCP) Modules
CCP1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
CCP2
CCP3
Comparators
C1
C2
C3
C4
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Digital-to-Analog Converter (DAC)
(8-bit DAC) D1
(5-bit DAC) D2
(5-bit DAC) D3
(5-bit DAC) D4
●
●
●
●
●
●
●
●
●
●
Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART)
EUSART
MSSP
●
●
●
●
●
●
●
●
●
●
Master Synchronous Serial Ports
Op Amp
●
●
●
●
Op Amp 1
Op Amp 2
Op Amp 3
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Programmable Switch Mode Controller (PSMC)
PSMC1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
PSMC2
PSMC3
PSMC4
Timers
Timer0
Timer1
Timer2
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
2011-2014 Microchip Technology Inc.
DS40001579E-page 7
PIC16(L)F1782/3
FIGURE 1-1:
PIC16(L)F1782/3 BLOCK DIAGRAM
Program
Flash Memory
RAM
PORTA
PORTB
PORTC
PORTE
CLKOUT
CLKIN
Timing
Generation
HFINTOSC/
LFINTOSC
Oscillator
CPU
Figure 2-1
MCLR
Op Amps
PSMCs
Timer0
Timer1
Timer2
MSSP
Comparators
Temp.
Indicator
ADC
12-Bit
FVR
DAC
CCPs
EUSART
Note 1:
See applicable chapters for more information on peripherals.
DS40001579E-page 8
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 1-2:
PIC16(L)F1782/3 PINOUT DESCRIPTION
Input Output
Function
Name
Description
Type
Type
RA0/AN0/C1IN0-/C2IN0-/C3IN0-
RA0
AN0
TTL/ST CMOS General purpose I/O.
AN
AN
AN
AN
—
—
—
—
A/D Channel 0 input.
Comparator C1 negative input.
Comparator C2 negative input.
Comparator C3 negative input.
C1IN0-
C2IN0-
C3IN0-
RA1
RA1/AN1/C1IN1-/C2IN1-/
C3IN1-/OPA1OUT
TTL/ST CMOS General purpose I/O.
AN1
AN
AN
AN
AN
—
—
—
A/D Channel 1 input.
C1IN1-
C2IN1-
C3IN1-
OPA1OUT
RA2
Comparator C1 negative input.
Comparator C2 negative input.
Comparator C3 negative input.
Operational Amplifier 1 output.
—
—
AN
RA2/AN2/C1IN0+/C2IN0+/
C3IN0+/DACOUT1/VREF-/
DACVREF-
TTL/ST CMOS General purpose I/O.
AN2
AN
AN
AN
AN
—
—
—
A/D Channel 2 input.
C1IN0+
C2IN0+
C3IN0+
DACOUT1
VREF-
Comparator C1 positive input.
—
Comparator C2 positive input.
—
Comparator C3 positive input.
AN
—
—
Digital-to-Analog Converter output.
A/D Negative Voltage Reference input.
Digital-to-Analog Converter negative reference.
AN
AN
DACVREF-
RA3
RA3/AN3/VREF+/C1IN1+/
DACVREF+
TTL/ST CMOS General purpose I/O.
AN3
AN
AN
AN
AN
—
—
—
—
A/D Channel 3 input.
VREF+
C1IN1+
DACVREF+
RA4
A/D Voltage Reference input.
Comparator C1 positive input.
Digital-to-Analog Converter positive reference.
RA4/C1OUT/OPA1IN+/T0CKI
TTL/ST CMOS General purpose I/O.
C1OUT
OPA1IN+
T0CKI
RA5
—
AN
ST
CMOS Comparator C1 output.
—
—
Operational Amplifier 1 non-inverting input.
Timer0 clock input.
(1)
RA5/AN4/C2OUT /OP1INA-/
TTL/ST CMOS General purpose I/O.
SS
AN4
AN
—
—
A/D Channel 4 input.
C2OUT
OPA1IN-
SS
CMOS Comparator C2 output.
AN
ST
—
—
Operational Amplifier 1 inverting input.
Slave Select input.
RA6/C2OUT/OSC2/CLKOUT
RA6
TTL/ST CMOS General purpose I/O.
C2OUT
OSC2
CLKOUT
RA7
—
—
—
CMOS Comparator C2 output.
XTAL Crystal/Resonator (LP, XT, HS modes).
CMOS FOSC/4 output.
RA7/PSMC1CLK/
TTL/ST CMOS General purpose I/O.
PSMC2CLK/OSC1/CLKIN
ST
—
—
PSMC1 clock input.
PSMC2 clock input.
PSMC1CLK
PSMC2CLK
OSC1
ST
—
st
XTAL Crystal/Resonator (LP, XT, HS modes).
External clock input (EC mode).
OD = Open Drain
CLKIN
—
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.
2: All pins have Interrupt-on-Change functionality.
2011-2014 Microchip Technology Inc.
DS40001579E-page 9
PIC16(L)F1782/3
TABLE 1-2:
PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED)
Input Output
Type Type
Name
Function
Description
RB0/AN12/C2IN1+/PSMC1IN/
PSMC2IN/CCP1 /INT
RB0
AN12
C2IN1+
PSMC1IN
PSMC2IN
CCP1
INT
TTL/ST CMOS General purpose I/O.
(1)
AN
AN
ST
ST
ST
ST
—
—
—
—
A/D Channel 12 input.
Comparator C2 positive input.
PSMC1 Event Trigger input.
PSMC2 Event Trigger input.
CMOS Capture/Compare/PWM1.
External interrupt.
—
RB1/AN10/C1IN3-/C2IN3-/
C3IN3-/OPA2OUT
RB1
TTL/ST CMOS General purpose I/O.
AN10
C1IN3-
C2IN3-
C3IN3-
OPA2OUT
RB2
AN
AN
AN
AN
—
—
—
A/D Channel 10 input.
Comparator C1 negative input.
Comparator C2 negative input.
Comparator C3 negative input.
Operational Amplifier 2 output.
—
—
AN
RB2/AN8/OPA2IN-/CLKR
RB3/AN9/C1IN2-/C2IN2-/
TTL/ST CMOS General purpose I/O.
AN8
AN
AN
—
—
—
A/D Channel 8 input.
OPA2IN-
CLKR
RB3
Operational Amplifier 2 inverting input.
Clock output.
CMOS
TTL/ST CMOS General purpose I/O.
(1)
C3IN2-/OPA2IN+/CCP2
AN9
AN
AN
AN
AN
AN
ST
—
—
—
—
—
A/D Channel 9 input.
Comparator C1 negative input.
Comparator C2 negative input.
Comparator C3 negative input.
Operational Amplifier 2 non-inverting input.
C1IN2-
C2IN2-
C3IN2-
OPA2IN+
CCP2
RB4
CMOS Capture/Compare/PWM2.
RB4/AN11/C3IN1+
TTL/ST CMOS General purpose I/O.
AN11
AN
AN
—
—
A/D Channel 11 input.
C3IN1+
RB5
Comparator C3 positive input.
(1)
RB5/AN13/C3OUT/T1G/SDO
TTL/ST CMOS General purpose I/O.
AN13
C3OUT
T1G
AN
—
—
A/D Channel 13 input.
CMOS Comparator C3 output.
Timer1 gate input.
CMOS SPI data output.
ST
—
—
SDO
(1)
(1)
(1)
(1)
RB6/TX /CK /SDI /SDA
ICSPCLK
/
RB6
TTL/ST CMOS General purpose I/O.
TX
—
ST
ST
CMOS USART asynchronous transmit.
CMOS USART synchronous clock.
CK
SDI
—
OD
—
SPI data input.
2
2
SDA
I C
I C™ data input/output.
ICSPCLK
ST
Serial Programming Clock.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.
2: All pins have Interrupt-on-Change functionality.
DS40001579E-page 10
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 1-2:
PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED)
Input Output
Type Type
Name
Function
Description
(1)
(1)
RB7/DACOUT2/RX /DT
/
RB7
DACOUT2
RX
TTL/ST CMOS General purpose I/O.
(1)
(1)
SCK /SCL /ICSPDAT
—
ST
ST
ST
AN
—
Voltage Reference output.
USART asynchronous input.
DT
CMOS USART synchronous data.
SCK
CMOS SPI clock.
2
2
SCL
I C
OD
I C™ clock.
ICSPDAT
RC0
ST
CMOS ICSP™ Data I/O.
RC0/T1OSO/T1CKI/PSMC1A
TTL/ST CMOS General purpose I/O.
T1OSO
T1CKI
PSMC1A
RC1
XTAL
ST
XTAL Timer1 oscillator connection.
Timer1 clock input.
CMOS PSMC1 output A.
—
—
(1)
RC1/T1OSI/PSMC1B/CCP2
TTL/ST CMOS General purpose I/O.
T1OSI
PSMC1B
CCP2
RC2
XTAL
—
XTAL Timer1 oscillator connection.
CMOS PSMC1 output B.
ST
CMOS Capture/Compare/PWM2.
(1)
RC2/PSMC1C/CCP1
TTL/ST CMOS General purpose I/O.
PSMC1C
CCP1
RC3
—
CMOS PSMC1 output C.
ST
CMOS Capture/Compare/PWM1.
(1)
(1)
RC3/PSMC1D/SCK /SCL
TTL/ST CMOS General purpose I/O.
PSMC1D
SCK
—
CMOS PSMC1 output D.
ST
CMOS SPI clock.
2
2
SCL
I C
OD
I C™ clock.
(1)
(1)
RC4/PSMC1E/SDI /SDA
RC4
TTL/ST CMOS General purpose I/O.
PSMC1E
SDI
—
CMOS PSMC1 output E.
ST
—
SPI data input.
2
2
SDA
I C
OD
I C™ data input/output.
(1)
RC5/PSMC1F/SDO
RC5
TTL/ST CMOS General purpose I/O.
PSMC1F
SDO
—
—
CMOS PSMC1 output F.
CMOS SPI data output.
(1)
(1)
(1)
RC6/PSMC2A/TX /CK
RC6
TTL/ST CMOS General purpose I/O.
PSMC2A
TX
—
—
CMOS PSMC2 output A.
CMOS USART asynchronous transmit.
CMOS USART synchronous clock.
CK
ST
(1)
RC7/PSMC2B/RX /DT
RC7
TTL/ST CMOS General purpose I/O.
PSMC2B
RX
—
ST
CMOS PSMC2 output B.
—
USART asynchronous input.
DT
ST
CMOS USART synchronous data.
RE3
TTL/ST
ST
—
—
—
—
—
General purpose input.
Master Clear with internal pull-up.
Programming voltage.
Positive supply.
RE3/MCLR/VPP
MCLR
VPP
HV
VDD
VSS
VDD
Power
Power
VSS
Ground reference.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1.
2: All pins have Interrupt-on-Change functionality.
2011-2014 Microchip Technology Inc.
DS40001579E-page 11
PIC16(L)F1782/3
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
2.0
ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
FIGURE 2-1:
CORE BLOCK DIAGRAM
15
Configuration
15
8
Data Bus
Program Counter
Flash
Program
Memory
16-LevelStack
(15-bit)
RAM
Program
Bus
14
RAM Addr
Program Memory
Read (PMR)
12
Addr MUX
InstructionReg
Indirect
Addr
7
Direct Addr
12
12
5
BSR Reg
15
FSR0 Reg
FSR1 Reg
15
STATUSReg
8
3
MUX
Power-up
Timer
Oscillator
Instruction
Decodeand
Control
Start-up Timer
ALU
Power-on
Reset
OSC1/CLKIN
8
Timing
Generation
Watchdog
Timer
W reg
OSC2/CLKOUT
Brown-out
Reset
Internal
Oscillator
Block
VDD
VSS
DS40001579E-page 12
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
2.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See 8.5 “Automatic Context Saving”, for more
information.
2.2
16-level Stack with Overflow and
Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft-
ware Reset. See Section 3.5 “Stack” for more details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.6 “Indirect Addressing” for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 29.0 “Instruction Set Summary” for more
details.
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PIC16(L)F1782/3
The following features are associated with access and
control of program memory and data memory:
3.0
MEMORY ORGANIZATION
These devices contain the following types of memory:
• PCL and PCLATH
• Stack
• Program Memory
- Configuration Words
- Device ID
• Indirect Addressing
- User ID
3.1
Program Memory Organization
- Flash Program Memory
• Data Memory
The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1782/3 family. Accessing
a location above these boundaries will cause a
wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1 and 3-2).
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
• Data EEPROM memory(1)
Note 1: The Data EEPROM Memory and the
method to access Flash memory through
the EECON registers is described in
Section 12.0 “Data EEPROM and Flash
Program Memory Control”.
TABLE 3-1:
DEVICE SIZES AND ADDRESSES
Device
Program Memory Space (Words)
Last Program Memory Address
PIC16(L)F1782
PIC16(L)F1783
2,048
4,096
07FFh
0FFFh
DS40001579E-page 14
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR
FIGURE 3-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1782
PIC16(L)F1783
PC<14:0>
PC<14:0>
15
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
CALL, CALLW
15
RETURN, RETLW
Interrupt, RETFIE
Stack Level 0
Stack Level 0
Stack Level 1
Stack Level 1
Stack Level 15
Reset Vector
Stack Level 15
Reset Vector
0000h
0000h
Interrupt Vector
Page 0
Interrupt Vector
Page 0
0004h
0005h
0004h
0005h
On-chip
Program
Memory
On-chip
Program
Memory
07FFh
0800h
07FFh
0800h
Rollover to Page 0
Page 1
0FFFh
1000h
Rollover to Page 0
Rollover to Page 0
Rollover to Page 1
7FFFh
7FFFh
2011-2014 Microchip Technology Inc.
DS40001579E-page 15
PIC16(L)F1782/3
3.1.1
READING PROGRAM MEMORY AS
DATA
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
my_function
;Index0 data
;Index1 data
3.1.1.1
RETLWInstruction
;… LOTS OF CODE…
MOVLW
MOVWF
MOVLW
MOVWF
MOVIW
LOW constants
FSR1L
HIGH constants
FSR1H
0[FSR1]
The RETLWinstruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1:
RETLWINSTRUCTION
;THE PROGRAM MEMORY IS IN W
constants
BRW
;Add Index in W to
;program counter to
;select data
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
;Index0 data
;Index1 data
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRWinstruction is not available so the older table read
method must be used.
3.1.1.2
Indirect Read with FSR
The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower 8 bits of the addressed word in the W
register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.
The high directive will set bit<7> if a label points to a
location in program memory.
DS40001579E-page 16
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
3.2.1
CORE REGISTERS
3.2
Data Memory Organization
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-7.
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
TABLE 3-2:
CORE REGISTERS
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.6 “Indirect
Addressing” for more information.
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
Data memory uses a 12-bit address. The upper 5 bits
of the address define the Bank address and the lower
7 bits select the registers/RAM in that bank.
WREG
PCLATH
INTCON
x0Ah or x8Ah
x0Bh or x8Bh
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DS40001579E-page 17
PIC16(L)F1782/3
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u= unchanged).
3.2.1.1
STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 29.0
“Instruction Set Summary”).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note:
The C and DC bits operate as Borrow and
Digit Borrow out bits, respectively, in
subtraction.
3.3
Register Definitions: Status
REGISTER 3-1:
STATUS: STATUS REGISTER
U-0
U-0
—
U-0
—
R-1/q
TO
R-1/q
PD
R/W-0/u
Z
R/W-0/u
DC(1)
R/W-0/u
C(1)
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-5
bit 4
Unimplemented: Read as ‘0’
TO: Time-Out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
bit 3
bit 2
bit 1
bit 0
PD: Power-Down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
DS40001579E-page 18
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
3.3.1
SPECIAL FUNCTION REGISTER
FIGURE 3-3:
BANKED MEMORY
PARTITIONING
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.
Memory Region
7-bit Bank Offset
00h
Core Registers
(12 bytes)
0Bh
0Ch
3.3.2
GENERAL PURPOSE RAM
Special Function Registers
(20 bytes maximum)
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
1Fh
20h
3.3.2.1
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.6.2
“Linear Data Memory” for more information.
General Purpose RAM
(80 bytes maximum)
3.3.3
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
2011-2014 Microchip Technology Inc.
DS40001579E-page 19
3.3.4
DEVICE MEMORY MAPS
The memory maps for Bank 0 through Bank 31 are shown in the tables in this section.
TABLE 3-3:
PIC16(L)F1782/3 MEMORY MAP (BANKS 0-7)
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
000h
080h
100h
180h
200h
280h
300h
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
PORTA
PORTB
PORTC
—
TRISA
TRISB
TRISC
—
LATA
LATB
ANSELA
ANSELB
—
WPUA
WPUB
ODCONA
ODCONB
ODCONC
—
SLRCONA
INLVLA
INLVLB
INLVLC
—
SLRCONB
LATC
WPUC
SLRCONC
—
—
—
—
—
—
—
—
—
—
—
PORTE
PIR1
TRISE
PIE1
PIE2
—
—
—
WPUE
—
INLVLE
IOCAP
IOCAN
IOCAF
IOCBP
IOCBN
IOCBF
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
CCPR1L
CCPR1H
CCP1CON
—
PIR2
—
PIR4
PIE4
TMR0
TMR1L
095h OPTION_REG 115h
—
096h
PCON
116h
—
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
TMR1H
T1CON
T1GCON
TMR2
PR2
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
FVRCON
DACCON0
DACCON1
—
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
VREGCON(2)
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
SSP1CON3
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
CCPR2L
CCPR2H
CCP2CON
—
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
—
—
—
—
—
—
—
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
IOCCP
IOCCN
IOCCF
—
—
—
—
—
—
—
—
—
RCREG
TXREG
SPBRG
SPBRGH
RCSTA
TXSTA
—
—
T2CON
—
ADRESH
ADCON0
ADCON1
—
—
—
APFCON
CM3CON0
—
IOCEP
IOCEN
—
—
01Fh
020h
—
09Fh
0A0h
ADCON2
11Fh
120h
CM3CON1
19Fh
1A0h
BAUDCON
21Fh
220h
—
29Fh
2A0h
—
31Fh
320h
—
39Fh
3A0h
IOCEF
General Purpose
Register
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
General
Purpose
General
Purpose
16 Bytes(1)
13Fh
140h
32Fh
330h
Unimplemented
Read as ‘0’
Register
Register
Register
80 Bytes(1)
80 Bytes(1)
80 Bytes(1)
Unimplemented
Read as ‘0’
36Fh
370h
3EFh
3F0h
06Fh
070h
0EFh
0F0h
16Fh
170h
1EFh
1F0h
26Fh
270h
2EFh
2F0h
Common RAM
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
07Fh
0FFh
17Fh
1FFh
27Fh
2FFh
37Fh
3FFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
Note 1:
2:
PIC16(L)F1783 only.
PIC16F1782/3 only.
TABLE 3-4:
PIC16(L)F1782/3 MEMORY MAP (BANKS 8-31)
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
BANK 15
400h
480h
500h
580h
600h
680h
700h
780h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
40Bh
40Ch
48Bh
48Ch
50Bh
50Ch
58Bh
58Ch
60Bh
60Ch
68Bh
68Ch
70Bh
70Ch
78Bh
78Ch
Unimplemented
Read as ‘0’
510h
511h
512h
OPA1CON
—
OPA2CON
513h
514h
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
519h
CLKRCON
51Ah
51Bh
Unimplemented
Read as ‘0’
46Fh
470h
4EFh
4F0h
56Fh
570h
5EFh
5F0h
66Fh
670h
6EFh
6F0h
76Fh
770h
7EFh
7F0h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
4FFh
57Fh
47Fh
800h
5FFh
67Fh
6FFh
77Fh
7FFh
BANK 16
BANK 17
BANK 18
BANK 19
BANK 20
BANK 21
BANK 22
BANK 23
880h
900h
980h
A00h
A80h
B00h
B80h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
80Bh
80Ch
88Bh
88Ch
90Bh
90Ch
98Bh
98Ch
A0Bh
A0Ch
A8Bh
A8Ch
B0Bh
B0Ch
B8Bh
B8Ch
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
See Table 3-5
9EFh
9F0h
AEFh
AF0h
BEFh
BF0h
86Fh
870h
8EFh
8F0h
96Fh
970h
A6Fh
A70h
B6Fh
B70h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
87Fh
C00h
8FFh
97Fh
9FFh
A7Fh
AFFh
B7Fh
BFFh
BANK 24
BANK 25
BANK 26
BANK 27
BANK 28
BANK 29
BANK 30
BANK 31
C80h
D00h
D80h
E00h
E80h
F00h
F80h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
C0Bh
C0Ch
C8Bh
C8Ch
D0Bh
D0Ch
D8Bh
D8Ch
E0Bh
E0Ch
E8Bh
E8Ch
F0Bh
F0Ch
F8Bh
F8Ch
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
See Table 3-6
C6Fh
C70h
CEFh
CF0h
D6Fh
D70h
DEFh
DF0h
E6Fh
E70h
EEFh
EF0h
F6Fh
F70h
FEFh
FF0h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
CFFh
D7Fh
DFFh
E7Fh
EFFh
F7Fh
FFFh
C7Fh
Legend:
= Unimplemented data memory locations, read as ‘0’
PIC16(L)F1782/3
TABLE 3-5:
PIC16(L)F1782/3 MEMORY
MAP (BANK 16 DETAILS)
TABLE 3-6:
PIC16(L)F1782/3 MEMORY
MAP (BANK 31 DETAILS)
BANK 16
BANK 16
BANK 31
PSMC1CON
PSMC1MDL
PSMC1SYNC
PSMC1CLK
PSMC1OEN
PSMC1POL
PSMC1BLNK
PSMC1REBS
PSMC1FEBS
PSMC1PHS
PSMC1DCS
PSMC1PRS
PSMC1ASDC
PSMC1ASDD
PSMC1ASDS
PSMC1INT
PSMC2CON
PSMC2MDL
PSMC2SYNC
PSMC2CLK
PSMC2OEN
PSMC2POL
PSMC2BLNK
PSMC2REBS
PSMC2FEBS
PSMC2PHS
PSMC2DCS
PSMC2PRS
PSMC2ASDC
PSMC2ASDD
PSMC2ASDS
PSMC2INT
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
81Fh
820h
821h
822h
823h
824h
825h
826h
827h
828h
829h
82Ah
82Bh
82Ch
82Dh
82Eh
82Fh
830h
831h
832h
833h
834h
835h
836h
837h
838h
839h
83Ah
83Bh
83Ch
83Dh
83Eh
83Fh
840h
841h
842h
843h
844h
845h
846h
847h
848h
849h
84Ah
84Bh
84Ch
84Dh
84Eh
84Fh
840h
F8Ch
Unimplemented
Read as ‘0’
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
TOSH
PSMC1PHL
PSMC1PHH
PSMC1DCL
PSMC1DCH
PSMC1PRL
PSMC1PRH
PSMC1TMRL
PSMC1TMRH
PSMC1DBR
PSMC1DBF
PSMC1BLKR
PSMC1BLKF
PSMC1FFA
PSMC1STR0
PSMC1STR1
—
PSMC2PHL
PSMC2PHH
PSMC2DCL
PSMC2DCH
PSMC2PRL
PSMC2PRH
PSMC2TMRL
PSMC2TMRH
PSMC2DBR
PSMC2DBF
PSMC2BLKR
PSMC2BLKF
PSMC1FFA
PSMC2STR0
PSMC2STR1
Unimplemented
Read as ‘0’
86Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
Legend:
= Unimplemented data memory locations, read as ‘0’.
DS40001579E-page 22
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
3.3.5
CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-7 can be
addressed from any Bank.
TABLE 3-7:
CORE FUNCTION REGISTERS SUMMARY
Value on
POR, BOR other Resets
Value on all
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0-31
x00h or
x80h
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
INDF0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 0000 0000 0000
x01h or
x81h
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
INDF1
PCL
x02h or
x82h
Program Counter (PC) Least Significant Byte
x03h or
x83h
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
x04h or
x84h
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
x05h or
x85h
x06h or
x86h
x07h or
x87h
x08h or
x88h
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
x09h or
x89h
WREG
PCLATH
INTCON
Working Register
x0Ahor
x8Ah
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
x0Bhor
x8Bh
GIE
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
2011-2014 Microchip Technology Inc.
DS40001579E-page 23
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00Ch PORTA
00Dh PORTB
00Eh PORTC
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
Unimplemented
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
00Fh
—
—
—
010h PORTE
011h PIR1
012h PIR2
—
TMR1GIF
OSFIF
—
—
—
RE3
—
CCP1IF
—
—
—
---- x--- ---- u---
0000 0000 0000 0000
0000 0-00 0000 0-00
ADIF
C2IF
RCIF
C1IF
TXIF
EEIF
SSP1IF
BCL1IF
TMR2IF
C3IF
TMR1IF
CCP2IF
013h
—
Unimplemented
—
—
—
014h PIR4
—
PSMC2TIF
PSMC1TIF
—
—
PSMC2SIF PSMC1SIF --00 --00 --00 --00
xxxx xxxx uuuu uuuu
015h TMR0
016h TMR1L
017h TMR1H
018h T1CON
019h T1GCON
Timer0 Module Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1CS1
TMR1GE
TMR1CS0
T1GPOL
T1CKPS1
T1GTM
T1CKPS0
T1GSPM
T1OSCEN
T1SYNC
T1GVAL
—
TMR1ON 0000 00-0 uuuu uu-u
T1GGO/
DONE
T1GSS<1:0>
0000 0x00 uuuu uxuu
016h TMR2
017h PR2
018h T2CON
01Dh
Holding Register for the Least Significant Byte of the 16-bit TMR2 Register
Holding Register for the Most Significant Byte of the 16-bit TMR2 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
-000 0000 -000 0000
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
to
—
Unimplemented
—
—
01Fh
Bank 1
08Ch TRISA
08Dh TRISB
08Eh TRISC
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
08Fh
—
—
—
(2)
090h TRISE
091h PIE1
092h PIE2
—
TMR1GIE
OSEIE
Unimplemented
—
—
—
—
—
—
CCP1IE
—
—
—
---- 1--- ---- 1---
0000 0000 0000 0000
0000 0-00 0000 0-00
ADIE
C2IE
RCIE
C1IE
TXIE
EEIE
SSP1IE
BCL1IE
TMR2IE
C3IE
TMR1IE
CCP2IE
093h
—
—
—
094h PIE4
—
INTEDG
STKUNF
—
PSMC2TIE
TMR0CS
—
PSMC1TIE
TMR0SE
RWDT
—
PSA
—
RI
PSMC2SIE PSMC1SIE --00 --00 --00 --00
095h OPTION_REG
096h PCON
WPUEN
STKOVF
—
PS<2:0>
POR
1111 1111 1111 1111
00-1 11qq qq-q qquu
RMCLR
BOR
097h WDTCON
098h OSCTUNE
099h OSCCON
09Ah OSCSTAT
09Bh ADRESL
09Ch ADRESH
09Dh ADCON0
09Eh ADCON1
09Fh ADCON2
WDTPS<4:0>
SWDTEN --01 0110 --01 0110
—
—
TUN<5:0>
--00 0000 --00 0000
SPLLEN
T1OSCR
IRCF<3:0>
—
SCS<1:0>
0011 1-00 0011 1-00
00q0 --00 qqqq --0q
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 -000 0000 -000
000- -000 000- -000
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
A/D Result Register Low
A/D Result Register High
ADRMD
CHS<4:0>
GO/DONE
ADON
ADFM
ADCS<2:0>
—
ADNREF
ADPREF<1:0>
TRIGSEL<3:0>
CHSN<3:0>
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Note 1:
2:
3:
PIC16F1782/3 only.
DS40001579E-page 24
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
10Ch LATA
10Dh LATB
10Eh LATC
PORTA Data Latch
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PORTB Data Latch
PORTC Data Latch
Unimplemented
10Fh
110h
—
—
—
—
—
—
Unimplemented
111h CM1CON0
112h CM1CON1
113h CM2CON0
114h CM2CON1
115h CMOUT
116h BORCON
117h FVRCON
118h DACCON0
119h DACCON1
11Ah
C1ON
C1INTP
C2ON
C1OUT
C1OE
C2OE
C1POL
C1PCH<2:0>
C2POL
C1ZLF
C2ZLF
C1SP
C2SP
C1HYS
C1NCH<2:0>
C2HYS
C1SYNC 0000 0100 0000 0100
0000 0000 0000 0000
C1INTN
C2OUT
C2INTN
—
C2SYNC 0000 0100 0000 0100
0000 0000 0000 0000
C2INTP
—
C2PCH<2:0>
—
C2NCH<2:0>
MC2OUT
—
—
—
—
—
MC3OUT
—
MC1OUT ---- -000 ---- -000
BORRDY 1x-- ---q uu-- ---u
SBOREN
FVREN
DACEN
BORFS
FVRRDY
—
—
TSEN
DACOE1
TSRNG
DACOE2
CDAFVR<1:0>
DACPSS<1:0>
ADFVR<1:0>
0q00 0000 0q00 0000
DACNSS 0-00 00-0 0-00 00-0
0000 0000 0000 0000
—
DACR<7:0>
to
—
Unimplemented
—
—
11Ch
11Dh APFCON
11Eh CM3CON0
11Fh CM3CON1
Bank 3
C2OUTSEL CC1PSEL
SDOSEL
C3OE
SCKSEL
C3POL
SDISEL
TXSEL
C3SP
RXSEL
C3HYS
CCP2SEL 0000 0000 0000 0000
C3SYNC 0000 0100 0000 0100
0000 0000 0000 0000
C3ON
C3OUT
C3INTN
C3ZLF
C3INTP
C3PCH<2:0>
C3NCH<2:0>
18Ch ANSELA
18Dh ANSELB
18Eh
ANSA7
—
—
—
ANSA5
ANSB5
ANSA4
ANSB4
ANSA3
ANSB3
ANSA2
ANSB2
ANSA1
ANSB1
ANSA0
ANSB0
1-11 1111 1-11 1111
--11 1111 --11 1111
to
—
Unimplemented
—
—
190h
191h EEADRL
192h EEADRH
193h EEDATL
194h EEDATH
195h EECON1
196h EECON2
197h VREGCON(3)
EEPROM / Program Memory Address Register Low Byte
0000 0000 0000 0000
1000 0000 1000 0000
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
0000 x000 0000 q000
0000 0000 0000 0000
(2)
—
EEPROM / Program Memory Address Register High Byte
EEPROM / Program Memory Read Data Register Low Byte
—
—
EEPROM / Program Memory Read Data Register High Byte
EEPGD
CFGS
LWLO
FREE
—
WRERR
WREN
WR
RD
EEPROM / Program Memory Control Register 2
—
—
—
—
—
VREGPM
Reserved ---- --01 ---- --01
198h
—
Unimplemented
—
—
199h RCREG
19Ah TXREG
19Bh SPBRG
19Ch SPBRGH
19Dh RCSTA
19Eh TXSTA
19Fh BAUDCON
USART Receive Data Register
USART Transmit Data Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0010 0000 0010
01-0 0-00 01-0 0-00
BRG<7:0>
BRG<15:8>
SPEN
CSRC
RX9
TX9
SREN
TXEN
—
CREN
ADDEN
SENDB
BRG16
FERR
BRGH
—
OERR
TRMT
WUE
RX9D
TX9D
SYNC
SCKP
ABDOVF
RCIDL
ABDEN
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Note 1:
2:
3:
PIC16F1782/3 only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 25
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 4
20Ch WPUA
20Dh WPUB
20Eh WPUC
WPUA7
WPUB7
WPUA6
WPUB6
WPUC6
WPUA5
WPUB5
WPUC5
WPUA4
WPUB4
WPUC4
WPUA3
WPUB3
WPUC3
WPUA2
WPUB2
WPUC2
WPUA1
WPUB1
WPUC1
WPUA0
WPUB0
WPUC0
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
WPUC7
20Fh
—
Unimplemented
—
—
—
210h WPUE
—
—
—
WPUE3
—
—
—
---- 1--- ---- 1---
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
211h SSP1BUF
212h SSP1ADD
Synchronous Serial Port Receive Buffer/Transmit Register
ADD<7:0>
MSK<7:0>
213h SSP1MSK
214h SSP1STAT
215h SSP1CON1
216h SSP1CON2
217h SSP1CON3
218h
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
SMP
WCOL
GCEN
ACKTIM
CKE
SSPOV
ACKSTAT
PCIE
D/A
P
S
R/W
UA
BF
SSPEN
ACKDT
SCIE
CKP
ACKEN
BOEN
SSPM<3:0>
RCEN
PEN
RSEN
AHEN
SEN
SDAHT
SBCDE
DHEN
—
21Fh
—
Unimplemented
—
—
Bank 5
28Ch ODCONA
28Dh ODCONB
28Eh ODCONC
Open Drain Control for PORTA
Open Drain Control for PORTB
Open Drain Control for PORTC
Unimplemented
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
28Fh
290h
—
—
—
—
—
—
Unimplemented
291h CCPR1L
292h CCPR1H
293h CCP1CON
294h
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
—
—
DC1B<1:0>
CCP1M<3:0>
—
—
Unimplemented
—
—
297h
298h CCPR2L
299h CCPR2H
29Ah CCP2CON
29Bh
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
—
—
DC2B<1:0>
CCP2M<3:0>
—
—
Unimplemented
—
—
29Fh
Bank 6
30Ch SLRCONA
30Dh SLRCONB
30Eh SLRCONC
30Fh
Slew Rate Control for PORTA
Slew Rate Control for PORTB
Slew Rate Control for PORTC
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
—
—
Unimplemented
—
—
31Fh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Note 1:
2:
3:
PIC16F1782/3 only.
DS40001579E-page 26
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 7
38Ch INLVLA
38Dh INLVLB
38Eh INLVLC
Input Type Control for PORTA
Input Type Control for PORTB
Input Type Control for PORTC
Unimplemented
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
38Fh
—
—
—
390h INLVLE
391h IOCAP
392h IOCAN
393h IOCAF
394h IOCBP
395h IOCBN
396h IOCBF
397h IOCCP
398h IOCCN
399h IOCCF
39Ah
—
—
—
—
INLVLE3
—
—
—
---- 1--- ---- 1---
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
IOCAP<7:0>
IOCAN<7:0>
IOCAF<7:0>
IOCBP<7:0>
IOCBN<7:0>
IOCBF<7:0>
IOCCP<7:0>
IOCCN<7:0>
IOCCF<7:0>
—
—
Unimplemented
—
—
39Ch
39Dh IOCEP
39Eh IOCEN
39Fh IOCEF
Bank 8-9
—
—
—
—
—
—
—
—
—
—
IOCEP3
IOCEN3
IOCEF3
—
—
—
—
—
—
—
—
—
---- 0--- ---- 0---
---- 0--- ---- 0---
---- 0--- ---- 0---
—
—
40Ch
or
41Fh
and
48Ch
or
—
Unimplemented
—
—
49Fh
Bank 10
50Ch
—
—
Unimplemented
—
—
510h
511h OPA1CON
512h
513h OPA2CON
OPA1EN
Unimplemented
OPA2EN
OPA1SP
OPA2SP
—
—
—
—
—
—
—
—
OPA1PCH<1:0>
00-- --00 00-- --00
—
—
—
OPA2PCH<1:0>
00-- --00 00-- --00
514h
—
—
Unimplemented
CLKREN
—
—
519h
51Ah CLKRCON
51Bh
—
51Fh
CLKROE
CLKRSLR
CLKRDC<1:0>
CLKRDIV<2:0>
0011 0000 0011 0000
—
Unimplemented
—
—
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Note 1:
2:
3:
PIC16F1782/3 only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 27
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 11-15
x0Ch
or
x8Ch
to
—
Unimplemented
—
—
x6Fh
or
xEFh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Note 1:
2:
3:
PIC16F1782/3 only.
DS40001579E-page 28
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 16
80Ch
—
810h
—
Unimplemented
PSMC1EN
—
—
811h PSMC1CON
812h PSMC1MDL
813h PSMC1SYNC
814h PSMC1CLK
815h PSMC1OEN
816h PSMC1POL
817h PSMC1BLNK
818h PSMC1REBS
819h PSMC1FEBS
81Ah PSMC1PHS
81Bh PSMC1DCS
81Ch PSMC1PRS
81Dh PSMC1ASDC
81Eh PSMC1ASDL
81Fh PSMC1ASDS
820h PSMC1INT
821h PSMC1PHL
822h PSMC1PHH
823h PSMC1DCL
PSMC1LD PSMC1DBFE PSMC1DBRE
P1MODE<3:0>
P1MSRC<3:0>
P1SYNC<1:0>
P1CSRC<1:0>
0000 0000 0000 0000
000- 0000 000- 0000
---- --00 ---- --00
--00 --00 --00 --00
--00 0000 --00 0000
-000 0000 -000 0000
--00 --00 --00 --00
0--- 000- 0--- 000-
0--- 000- 0--- 000-
0--- 0000 0--- 0000
0--- 0000 0--- 0000
0--- 0000 0--- 0000
P1MDLEN P1MDLPOL P1MDLBIT
—
—
—
—
—
—
—
—
—
—
P1CPRE<1:0>
—
P1OEC
P1POLC
—
—
—
P1OEF
P1OEE
P1OED
P1POLD
—
P1OEB
P1POLB
P1OEA
—
P1INPOL
P1POLF
P1POLE
P1POLA
—
—
P1FEBM<1:0>
P1REBM<1:0>
P1REBIN
P1FEBIN
P1PHSIN
P1DCSIN
P1PRSIN
P1ASE
—
—
—
—
P1REBSC3 P1REBSC2 P1REBSC1
P1FEBSC3 P1FEBSC2 P1FEBSC1
—
—
—
—
—
—
—
—
P1PHSC3
P1DCSC3
P1PRSC3
—
P1PHSC2
P1DCSC2
P1PRSC2
—
P1PHSC1
P1DCSC1
P1PRSC1
—
P1PHST
P1DCST
P1PRST
—
—
—
—
—
—
P1ASDEN
—
P1ARSEN
P1ASDLF
—
—
P1ASDOV 000- ---0 000- ---0
P1ASDLA --00 0000 --00 0000
P1ASDLE
—
P1ASDLD
P1ASDLC
P1ASDLB
P1ASDSIN
P1TOVIE
—
P1ASDSC3 P1ASDSC2 P1ASDSC1
P1TOVIF P1TPHIF P1TDCIF
—
0--- 000- 0--- 000-
P1TPHIE
P1TDCIE
P1TPRIE
P1TPRIF 0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0001 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
---- 0000 ---- 0000
Phase Low Count
Phase High Count
Duty Cycle Low Count
824h PSMC1DCH Duty Cycle High Count
825h PSMC1PRL
826h PSMC1PRH
Period Low Count
Period High Count
827h PSMC1TMRL Time base Low Counter
828h PSMC1TMRH Time base High Counter
829h PSMC1DBR
82Ah PSMC1DBF
rising Edge Dead-band Counter
Falling Edge Dead-band Counter
82Bh PSMC1BLKR rising Edge Blanking Counter
82Ch PSMC1BLKF Falling Edge Blanking Counter
82Dh PSMC1FFA
82Eh PSMC1STR0
82Fh PSMC1STR1
—
—
—
—
—
—
P1STRF
—
—
P1STRE
—
Fractional Frequency Adjust Register
P1STRD
—
P1STRC
—
P1STRB
P1STRA
P1HSMEN 0--- --00 0--- --00
--00 0001 --00 0001
P1SYNC
Unimplemented
P1LSMEN
830h
—
—
—
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Note 1:
2:
3:
PIC16F1782/3 only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 29
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 16 (Continued)
831h PSMC2CON
832h PSMC2MDL
833h PSMC2SYNC
834h PSMC2CLK
835h PSMC2OEN
836h PSMC2POL
837h PSMC2BLNK
838h PSMC2REBS
839h PSMC2FEBS
83Ah PSMC2PHS
83Bh PSMC2DCS
83Ch PSMC2PRS
83Dh PSMC2ASDC
83Eh PSMC2ASDL
83Fh PSMC2ASDS
840h PSMC2INT
841h PSMC2PHL
842h PSMC2PHH
843h PSMC2DCL
PSMC2EN
PSMC2LD PSMC2DBFE PSMC2DBRE
P2MODE<3:0>
P2MSRC<3:0>
P2SYNC<1:0>
P2CSRC<1:0>
0000 0000 0000 0000
000- 0000 000- 0000
---- --00 ---- --00
--00 --00 --00 --00
---- --00 ---- --00
-0-- --00 -0-- --00
--00 --00 --00 --00
0--- 000- 0--- 000-
0--- 000- 0--- 000-
0--- 0000 0--- 0000
P2MDLEN P2MDLPOL P2MDLBIT
—
—
—
—
—
—
—
—
—
—
—
—
—
P2CPRE<1:0>
—
—
—
—
—
—
—
—
—
—
P2OEB
P2POLB
P2OEA
—
P2INPOL
P2POLA
—
—
P2FEBM<1:0>
P2REBM<1:0>
P2REBIN
P2FEBIN
P2PHSIN
P2DCSIN
P2PRSIN
P2ASE
—
—
—
—
P2REBSC3 P2REBSC2 P2REBSC1
P2FEBSC3 P2FEBSC2 P2FEBSC1
—
—
—
—
—
—
—
—
P2PHSC3
P2DCSC3
P2PRSC3
—
P2PHSC2
P2DCSC2
P2PRSC2
—
P2PHSC1
P2DCSC1
P2PRSC1
—
P2PHST
—
—
—
—
—
P2DCST 0--- 0000 0--- 0000
P2PRST 0--- 0000 0--- 0000
—
P2ASDEN
—
P2ARSEN
P2ASDLF
—
—
P2ASDOV 000- ---0 000- ---0
P2ASDLA --00 0000 --00 0000
P2ASDLE
—
P2ASDLD
P2ASDLC
P2ASDLB
P2ASDSIN
P2TOVIE
—
P2ASDSC3 P2ASDSC2 P2ASDSC1
P2TOVIF P2TPHIF P2TDCIF
—
0--- 000- 0--- 000-
P2TPHIE
P2TDCIE
P2TPRIE
P2TPRIF 0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0001 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
---- 0000 ---- 0000
Phase Low Count
Phase High Count
Duty Cycle Low Count
844h PSMC2DCH Duty Cycle High Count
845h PSMC2PRL
846h PSMC2PRH
Period Low Count
Period High Count
847h PSMC2TMRL Time base Low Counter
848h PSMC2TMRH Time base High Counter
849h PSMC2DBR
84Ah PSMC2DBF
rising Edge Dead-band Counter
Falling Edge Dead-band Counter
84Bh PSMC2BLKR rising Edge Blanking Counter
84Ch PSMC2BLKF Falling Edge Blanking Counter
84Dh PSMC2FFA
84Eh PSMC2STR0
84Fh PSMC2STR1
850h
—
—
—
—
—
—
—
—
—
—
—
Fractional Frequency Adjust Register
—
—
—
—
P2STRB
P2STRA
---- --01 ---- --01
P2SYNC
P2LSMEN
P2HSMEN 0--- --00 0--- --00
—
86Fh
—
Unimplemented
—
—
—
—
Bank 17-30
x0Ch
or
x8Ch
to
—
Unimplemented
x1Fh
or
x9Fh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Note 1:
2:
3:
PIC16F1782/3 only.
DS40001579E-page 30
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 31
F8Ch
to
FE3h
—
Unimplemented
—
—
—
FE4h STATUS_
SHAD
—
—
—
—
—
Z
DC
C
---- -xxx ---- -uuu
FE5h WREG_SHAD Working Register Shadow
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
-xxx xxxx uuuu uuuu
FE6h BSR_SHAD
—
—
—
Bank Select Register Shadow
FE7h PCLATH_
SHAD
Program Counter Latch High Register Shadow
FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
FE9h FSR0H_
SHAD
Indirect Data Memory Address 0 High Pointer Shadow
FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
FEBh FSR1H_
SHAD
Indirect Data Memory Address 1 High Pointer Shadow
FECh
FEDh
FEEh
—
Unimplemented
—
—
—
—
—
Current Stack Pointer
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
-xxx xxxx -uuu uuuu
STKPTR
TOSL
TOSH
Top of Stack Low byte
Top of Stack High byte
FEFh
—
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
Note 1:
2:
3:
PIC16F1782/3 only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 31
PIC16(L)F1782/3
3.4.3
COMPUTED FUNCTION CALLS
3.4
PCL and PCLATH
A computed function CALLallows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.
If using the CALLinstruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
FIGURE 3-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
The CALLW instruction enables computed calls by
combining PCLATH and W to form the destination
address. A computed CALLW is accomplished by
loading the W register with the desired address and
executing CALLW. The PCL register is loaded with the
value of W and PCH is loaded with PCLATH.
14
0
Instruction with
PCL as
Destination
PCH
PCL
PC
8
7
6
0
ALU Result
PCLATH
14
0
PCH
PCL
3.4.4
BRANCHING
GOTO, CALL
PC
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
4
11
6
0
0
PCLATH
OPCODE <10:0>
14
0
PCH
PCL
CALLW
PC
7
8
6
W
PCLATH
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
14
0
0
PCH
PCH
PCL
BRW
PC
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRAinstruction.
15
PC + W
14
PCL
BRA
PC
15
PC + OPCODE <8:0>
3.4.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 7 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register, all
15 bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.
3.4.2
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTOmethod, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).
DS40001579E-page 32
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
3.5.1
ACCESSING THE STACK
3.5
Stack
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-1 and 3-2). The stack space is
not part of either program or data space. The PC is
PUSHed onto the stack when CALLor CALLWinstruc-
tions are executed or an interrupt causes a branch. The
stack is POPed in the event of a RETURN, RETLWor a
RETFIEinstruction execution. PCLATH is not affected
by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Words). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Over-
flow/Underflow, regardless of whether the Reset is
enabled.
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and
interrupts will increment STKPTR while RETLW,
RETURN, and RETFIEwill decrement STKPTR. At any
time, STKPTR can be inspected to see how much
stack is left. The STKPTR always points at the currently
used place on the stack. Therefore, a CALLor CALLW
will increment the STKPTR and then write the PC, and
a return will unload the PC and then decrement the
STKPTR.
Note:
There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
CALLW, RETURN, RETLW and RETFIE
instructions or the vectoring to an interrupt
address.
Reference Figure 3-5 through Figure 3-8 for examples
of accessing the stack.
FIGURE 3-5:
ACCESSING THE STACK EXAMPLE 1
Stack Reset Disabled
(STVREN = 0)
TOSH:TOSL
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x1F
STKPTR = 0x1F
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
Stack Reset Enabled
STKPTR = 0x1F
TOSH:TOSL
0x0000
(STVREN = 1)
2011-2014 Microchip Technology Inc.
DS40001579E-page 33
PIC16(L)F1782/3
FIGURE 3-6:
ACCESSING THE STACK EXAMPLE 2
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
This figure shows the stack configuration
after the first CALLor a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
TOSH:TOSL
Return Address
STKPTR = 0x00
FIGURE 3-7:
ACCESSING THE STACK EXAMPLE 3
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURNinstructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
STKPTR = 0x06
TOSH:TOSL
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
DS40001579E-page 34
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
FIGURE 3-8:
ACCESSING THE STACK EXAMPLE 4
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
When the stack is full, the next CALLor
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
TOSH:TOSL
STKPTR = 0x10
3.5.2
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.6
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
2011-2014 Microchip Technology Inc.
DS40001579E-page 35
PIC16(L)F1782/3
FIGURE 3-9:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
0x1FFF
0x2000
Reserved
Linear
Data Memory
0x29AF
0x29B0
Reserved
0x0000
FSR
Address
Range
0x7FFF
0x8000
Program
Flash Memory
0xFFFF
0x7FFF
Note:
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS40001579E-page 36
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
3.6.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-10:
TRADITIONAL DATA MEMORY MAP
Direct Addressing
From Opcode
Indirect Addressing
4
BSR
6
7
FSRxH
0
7
FSRxL
0
0
0
0
0
0
0
Location Select
Bank Select
Bank Select
Location Select
00000 00001 00010
11111
0x00
0x7F
Bank 0 Bank 1 Bank 2
Bank 31
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3.6.2
LINEAR DATA MEMORY
3.6.3
PROGRAM FLASH MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-12:
PROGRAM FLASH
MEMORY MAP
FIGURE 3-11:
LINEAR DATA MEMORY
MAP
7
7
0
0
FSRnH
FSRnL
7
1
7
0
0
FSRnH
FSRnL
0
0 1
Location Select
0x8000
0x0000
Location Select
0x2000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x7FFF
0xFFFF
0xF6F
0x29AF
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PIC16(L)F1782/3
4.0
DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.
4.1
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note:
The DEBUG bit in Configuration Words is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
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4.2
Register Definitions: Configuration Words
REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1
R/P-1
R/P-1
IESO
R/P-1
R/P-1
R/P-1
R/P-1
CPD
FCMEN
CLKOUTEN
BOREN<1:0>
bit 13
bit 8
R/P-1
CP
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
bit 0
MCLRE
PWRTE
WDTE<1:0>
FOSC<2:0>
bit 7
Legend:
R = Readable bit
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
-n = Value when blank or after Bulk Erase
bit 13
bit 12
bit 11
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor and internal/external switchover are both enabled.
0= Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1= Internal/External Switchover mode is enabled
0= Internal/External Switchover mode is disabled
CLKOUTEN: Clock Out Enable bit
If FOSC configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC modes:
1= CLKOUT function is disabled. I/O function on the CLKOUT pin.
0= CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
11= BOR enabled
10= BOR enabled during operation and disabled in Sleep
01= BOR controlled by SBOREN bit of the BORCON register
00= BOR disabled
bit 8
bit 7
bit 6
CPD: Data Code Protection bit(1)
1= Data memory code protection is disabled
0= Data memory code protection is enabled
CP: Code Protection bit
1= Program memory code protection is disabled
0= Program memory code protection is enabled
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1= MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0= MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11= WDT enabled
10= WDT enabled while running and disabled in Sleep
01= WDT controlled by the SWDTEN bit in the WDTCON register
00= WDT disabled
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REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111= ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin
110= ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
101= ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
100= INTOSC oscillator: I/O function on CLKIN pin
011= EXTRC oscillator: External RC circuit connected to CLKIN pin
010= HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001= XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000= LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins
Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase.Once the
Data Code Protection bit is enabled, (CPD = 0), the Bulk Erase Program Memory Command (through
ICSP) can disable the Data Code Protection (CPD =1). When a Bulk Erase Program Memory Command
is executed, the entire Program Flash Memory, Data EEPROM and configuration memory will be erased.
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PIC16(L)F1782/3
REGISTER 4-2:
CONFIG2: CONFIGURATION WORD 2
R/P-1
LVP
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
DEBUG
LPBOR
BORV
STVREN
PLLEN
bit 13
bit 8
U-1
—
U-1
—
R/P-1
U-1
—
U-1
—
U-1
—
R/P-1
R/P-1
WRT<1:0>
VCAPEN
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
-n = Value when blank or after Bulk Erase
(1)
bit 13
bit 12
bit 11
bit 10
bit 9
LVP: Low-Voltage Programming Enable bit
1= Low-voltage programming enabled
0= High-voltage on MCLR must be used for programming
(3)
DEBUG: In-Circuit Debugger Mode bit
1= In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0= In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
LPBOR: Low-Power BOR Enable bit
1= Low-Power Brown-out Reset is disabled
0= Low-Power Brown-out Reset is enabled
(4)
BORV: Brown-out Reset Voltage Selection bit
1= Brown-out Reset voltage (VBOR), low trip point selected.
0= Brown-out Reset voltage (VBOR), high trip point selected.
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Stack Overflow or Underflow will cause a Reset
0= Stack Overflow or Underflow will not cause a Reset
bit 8
PLLEN: PLL Enable bit
1= 4xPLL enabled
0= 4xPLL disabled
bit 7-6
bit 5
Unimplemented: Read as ‘1’
(2)
VCAPEN: Voltage Regulator Capacitor Enable bit
1= VCAP functionality is disabled on RA6
0= VCAP functionality is enabled on RA6
bit 4-2
bit 1-0
Unimplemented: Read as ‘1’
WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory (PIC16(L)F1782 only):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control
01= 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control
00= 000h to 7FFh write-protected, no addresses may be modified by EECON control
4 kW Flash memory (PIC16(L)F1783 only):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control
01= 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control
00= 000h to FFFh write-protected, no addresses may be modified by EECON control
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: Not implemented on “LF” devices.
3: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers
and programmers. For normal device operation, this bit should be maintained as a '1'.
4: See VBOR parameter for specific trip point voltages.
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4.3
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data EEPROM protection are controlled independently.
Internal access to the program memory and data
EEPROM are unaffected by any code protection
setting.
4.3.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 4.4
“Write
Protection” for more information.
4.3.2
DATA EEPROM PROTECTION
The entire data EEPROM is protected from external
reads and writes by the CPD bit. When CPD = 0,
external reads and writes of data EEPROM are
inhibited. The CPU can continue to read and write data
EEPROM regardless of the protection bit settings.
4.4
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.5
User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 12.5 “User ID, Device ID and Configuration
Word Access”for more information on accessing
these memory locations. For more information on
checksum calculation, see the “PIC16(L)F178X
Memory Programming Specification” (DS41457).
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4.6
Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 12.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
4.7
Register Definitions: Device and Revision
REGISTER 4-3:
DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
R
R
R
R
DEV<8:3>
bit 13
bit 8
bit 0
R
R
R
R
DEV<2:0>
REV<4:0>
bit 7
Legend:
R = Readable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 13-5
DEV<8:0>: Device ID bits
DEVICEID<13:0> Values
Device
DEV<8:0>
REV<4:0>
PIC16F1782
PIC16LF1782
PIC16F1783
PIC16LF1783
10 1010 000
10 1010 101
10 1010 001
10 1010 110
x xxxx
x xxxx
x xxxx
x xxxx
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to identify the revision (see Table under DEV<8:0> above).
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A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
5.0
RESETS
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Low-Power Brown-Out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESETinstruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
ICSP™ Programming Mode
Exit
RESETInstruction
Stack
Pointer
MCLRE
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
PWRT
R
Done
LPBOR
Reset
PWRTE
LFINTOSC
BOR
Active(1)
Note 1: See Table 5-1 for BOR active conditions.
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5.1
Power-On Reset (POR)
5.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu-
ration Words. The four operating modes are:
• BOR is always on
5.1.1
POWER-UP TIMER (PWRT)
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
The Power-up Timer provides a nominal 64 ms
time-out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
Refer to Table 5-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from
triggering on small events. If VDD falls below VBOR for
a duration greater than parameter TBORDC, the device
will reset. See Figure 5-2 for more information.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 5-1:
BOREN<1:0>
11
BOR OPERATING MODES
Instruction Execution upon:
Release of POR or Wake-up from Sleep
SBOREN
Device Mode
BOR Mode
X
X
X
Awake
Sleep
X
Active
Active
Waits for BOR ready(1) (BORRDY = 1)
10
Waits for BOR ready (BORRDY = 1)
Waits for BOR ready(1) (BORRDY = 1)
Begins immediately (BORRDY = x)
Disabled
Active
1
0
X
01
00
X
Disabled
Disabled
X
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
5.2.1
BOR IS ALWAYS ON
5.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
start-up is not delayed by the BOR ready condition or
the VDD level.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
5.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Words are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is unchanged by Sleep.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
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FIGURE 5-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
(1)
TPWRT
VDD
VBOR
Internal
Reset
< TPWRT
(1)
TPWRT
VDD
VBOR
Internal
Reset
(1)
TPWRT
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
5.3
Register Definitions: BOR Control
REGISTER 5-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
SBOREN
bit 7
R/W-0/u
BORFS
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-q/u
BORRDY
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
SBOREN: Software Brown-out Reset Enable bit
If BOREN <1:0> in Configuration Words 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1= BOR Enabled
0= BOR Disabled
(1)
BORFS: Brown-out Reset Fast Start bit
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1= Band gap is forced on always (covers sleep/wake-up/operating cases)
0= Band gap operates normally, and may turn off
bit 5-1
bit 0
Unimplemented: Read as ‘0’
BORRDY: Brown-out Reset Circuit Ready Status bit
1= The Brown-out Reset circuit is active
0= The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Words.
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5.4
Low-Power Brown-Out Reset
(LPBOR)
5.6
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDTinstruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 11.0
“Watchdog Timer (WDT)” for more information.
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 5-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 5-2.
5.7
RESETInstruction
A RESETinstruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 5-4
for default conditions after a RESET instruction has
occurred.
5.4.1
ENABLING LPBOR
5.8
Stack Overflow/Underflow Reset
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 5.8 “Stack Overflow/Underflow
Reset” for more information.
5.4.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR mod-
ule to provide the generic BOR signal, which goes to
the PCON register and to the power control block.
5.9
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
5.5
MCLR
5.10 Power-Up Timer
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 5-2).
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
TABLE 5-2:
MCLRE
MCLR CONFIGURATION
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
LVP
MCLR
0
1
x
0
0
1
Disabled
Enabled
Enabled
5.11 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
5.5.1
MCLR ENABLED
2. Oscillator start-up timer runs to completion (if
required for oscillator source).
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
3. MCLR must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Section 6.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for more information.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
A Reset does not drive the MCLR pin low.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
start-up timer will expire. Upon bringing MCLR high, the
device will begin execution immediately (see
Figure 5-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
5.5.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 13.9 “PORTE
Registers” for more information.
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FIGURE 5-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
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5.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 5-3 and Table 5-4 show the Reset
conditions of these registers.
TABLE 5-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
0
0
0
0
u
u
u
u
u
u
1
u
0
0
0
0
u
u
u
u
u
u
u
1
1
1
1
u
0
u
u
u
u
u
u
u
1
1
1
1
u
u
u
0
0
u
u
u
1
1
1
1
u
u
u
u
u
0
u
u
0
0
0
u
u
u
u
u
u
u
u
u
x
x
x
0
u
u
u
u
u
u
u
u
1
0
x
1
0
0
1
u
1
u
u
u
1
x
0
1
u
0
0
u
0
u
u
u
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
TABLE 5-4:
RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
0000h
---1 1000
---u uuuu
00-- 110x
uu-- 0uuu
MCLR Reset during normal operation
0000h
MCLR Reset during Sleep
WDT Reset
0000h
0000h
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
1u-- uuuu
u1-- uuuu
WDT Wake-up from Sleep
Brown-out Reset
PC + 1
0000h
Interrupt Wake-up from Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
PC + 1(1)
0000h
0000h
0000h
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
DS40001579E-page 50
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
The PCON register bits are shown in Register 5-2.
5.13 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
5.14 Register Definitions: Power Control
REGISTER 5-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q R/W/HS-0/q
U-0
—
R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF
bit 7
STKUNF
RWDT
RMCLR
RI
POR
BOR
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
U = Unimplemented bit, read as ‘0’
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
-m/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
STKOVF: Stack Overflow Flag bit
1= A Stack Overflow occurred
0= A Stack Overflow has not occurred or cleared by firmware
STKUNF: Stack Underflow Flag bit
1= A Stack Underflow occurred
0= A Stack Underflow has not occurred or cleared by firmware
bit 5
bit 4
Unimplemented: Read as ‘0’
RWDT: Watchdog Timer Reset Flag bit
1= A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0= A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3
bit 2
bit 1
bit 0
RMCLR: MCLR Reset Flag bit
1= A MCLR Reset has not occurred or set to ‘1’ by firmware
0= A MCLR Reset has occurred (cleared by hardware)
RI: RESETInstruction Flag bit
1= A RESETinstruction has not been executed or set to ‘1’ by firmware
0= A RESETinstruction has been executed (cleared by hardware)
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
2011-2014 Microchip Technology Inc.
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TABLE 5-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BORCON SBOREN BORFS
—
—
—
—
RWDT
TO
—
RMCLR
PD
—
RI
Z
—
POR
DC
BORRDY
BOR
47
51
18
94
PCON
STKOVF STKUNF
STATUS
WDTCON
—
—
—
—
C
WDTPS<4:0>
SWDTEN
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
DS40001579E-page 52
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PIC16(L)F1782/3
The oscillator module can be configured in one of eight
clock modes.
6.0
6.1
OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
1. ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)
Overview
2. ECM – External Clock Medium-Power mode
(0.5 MHz to 4 MHz)
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 6-1
illustrates a block diagram of the oscillator module.
3. ECH – External Clock High-Power mode
(4 MHz to 32 MHz)
4. LP – 32 kHz Low-Power Crystal mode.
5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)
Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds
selectable via software. Additional clock features
include:
6. HS – High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz)
7. RC – External Resistor-Capacitor (RC).
8. INTOSC – Internal oscillator (31 kHz to 32 MHz).
Clock Source modes are selected by the FOSC<2:0>
bits in the Configuration Words. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
• Selectable system clock source between external
or internal sources via software.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
The EC clock mode relies on an external logic level
signal as the device clock source. The LP, XT, and HS
clock modes require an external crystal or resonator to
be connected to the device. Each mode is optimized for
a different frequency range. The RC clock mode
requires an external resistor and capacitor to set the
oscillator frequency.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources
The INTOSC internal oscillator block produces low,
medium, and high-frequency clock sources,
designated LFINTOSC, MFINTOSC and HFINTOSC.
(see Internal Oscillator Block, Figure 6-1). A wide
selection of device clock frequencies may be derived
from these three clock sources.
2011-2014 Microchip Technology Inc.
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PIC16(L)F1782/3
FIGURE 6-1:
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Timer1
Oscillator
Timer1 Clock Source Option
for other modules
T1OSO
T1OSI
T1OSCEN
Enable
Oscillator
T1OSC
01
External
LP, XT, HS, RC, EC
Oscillator
OSC2
OSC1
0
Sleep
10
1
Sleep
FOSC
PSMCMUX
÷ 2
00
01
00
PRIMUX
To CPU and
Peripherals
0
1
4 x PLL
PLLMUX
INTOSC
IRCF<3:0>
1X
16 MHz
8 MHz
1111
Internal
Oscillator
Block
4 MHz
2 MHz
SCS<1:0>
1 MHz
HFPLL
PSMC 64 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
16 MHz
(HFINTOSC)
500 kHz
Source
500 kHz
(MFINTOSC)
31 kHz
Source
31 kHz
0000
31 kHz (LFINTOSC)
WDT, PWRT, Fail-Safe Clock Monitor
Two-Speed Start-up and other modules
PLLEN or
SPLLEN
SCS FOSC<2:0>
PRIMUX
PSMCMUX
PLLMUX
0
1
0
1
1
0
0
X
1
1
1
0
1
10
01
10
00
XX
=100
=00
≠100
(1)
1
≠00
XXX
X
Note 1: This selection should not be made when the PSMC is using the 64 MHz clock option.
DS40001579E-page 54
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PIC16(L)F1782/3
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
6.2
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator
modules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
Internal clock sources are contained within the
oscillator module. The internal oscillator block has two
internal oscillators and a dedicated Phase-Lock Loop
(HFPLL) that are used to generate three internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC)
and the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC).
FIGURE 6-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
OSC1/CLKIN
PIC® MCU
Clock from
Ext. System
OSC2/CLKOUT
(1)
FOSC/4 or
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 6.3
“Clock Switching” for additional information.
I/O
Note 1: Output depends upon CLKOUTEN bit of the
Configuration Words.
6.2.1
EXTERNAL CLOCK SOURCES
6.2.1.2
LP, XT, HS Modes
An external clock source can be used as the device
system clock by performing one of the following
actions:
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 6-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
• Program the FOSC<2:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- Timer1 oscillator during run-time, or
- An external clock source determined by the
value of the FOSC bits.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
See Section 6.3 “Clock Switching”for more informa-
tion.
6.2.1.1
EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 6-2 shows the pin connections for EC
mode.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 6-3 and Figure 6-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
EC mode has three power modes to select from through
Configuration Words:
• High power, 4-32 MHz (FOSC = 111)
• Medium power, 0.5-4 MHz (FOSC = 110)
• Low power, 0-0.5 MHz (FOSC = 101)
2011-2014 Microchip Technology Inc.
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FIGURE 6-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 6-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC® MCU
PIC® MCU
OSC1/CLKIN
OSC1/CLKIN
C1
C1
To Internal
Logic
To Internal
Logic
Quartz
Crystal
(2)
Sleep
RF
(3)
(2)
RP
RF
Sleep
OSC2/CLKOUT
(1)
C2
RS
OSC2/CLKOUT
(1)
C2
RS
Ceramic
Resonator
Note 1: A series resistor (RS) may be required for
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
6.2.1.3
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended,
unless either FSCM or Two-Speed Start-Up are
enabled. In this case, code will continue to execute at
the selected INTOSC frequency while the OST is
counting. The OST ensures that the oscillator circuit,
using a quartz crystal resonator or ceramic resonator,
has started and is providing a stable system clock to
the oscillator module.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 6.4
“Two-Speed Clock Start-up Mode”).
DS40001579E-page 56
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
6.2.1.4
4x PLL
Note 1: Quartz
crystal
characteristics
vary
The oscillator module contains a 4x PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4x PLL must fall within specifications. See the PLL
Clock Timing Specifications in Section 30.0
“Electrical Specifications”.
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
The 4x PLL may be enabled for use by one of two
methods:
3: For oscillator design assistance, reference
1. Program the PLLEN bit in Configuration Words
the following Microchip Applications Notes:
to a ‘1’.
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
2. Write the SPLLEN bit in the OSCCON register to
a ‘1’. If the PLLEN bit in Configuration Words is
programmed to a ‘1’, then the value of SPLLEN
is ignored.
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
6.2.1.5
TIMER1 Oscillator
The Timer1 oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is opti-
mized for timekeeping operations with a 32.768 kHz
crystal connected between the T1OSO and T1OSI
device pins.
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
The Timer1 oscillator can be used as an alternate
system clock source and can be selected during
run-time using clock switching. Refer to Section 6.3
“Clock Switching” for more information.
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)
FIGURE 6-5:
QUARTZ CRYSTAL
OPERATION (TIMER1
OSCILLATOR)
PIC® MCU
T1OSI
C1
To Internal
Logic
32.768 kHz
Quartz
Crystal
T1OSO
C2
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6.2.1.6
External RC Mode
6.2.2
INTERNAL CLOCK SOURCES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The device may be configured to use the internal
oscillator block as the system clock by performing one
of the following actions:
• Program the FOSC<2:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 6.3
“Clock Switching”for more information.
Figure 6-6 shows the external RC mode connections.
FIGURE 6-6:
EXTERNAL RC MODES
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
VDD
PIC® MCU
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in Configuration Words.
REXT
OSC1/CLKIN
Internal
Clock
The internal oscillator block has two independent
oscillators and a dedicated Phase-Lock Loop, HFPLL
that can produce one of three internal system clock
sources.
CEXT
VSS
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The HFINTOSC source is generated
from the 500 kHz MFINTOSC source and the
dedicated Phase-Lock Loop, HFPLL. The
frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 6-3).
OSC2/CLKOUT
(1)
FOSC/4 or I/O
Recommended values: 10 k REXT 100 k, <3V
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Output depends upon CLKOUTEN bit of the
Configuration Words.
2. The MFINTOSC (Medium-Frequency Internal
Oscillator) is factory calibrated and operates at
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 6-3).
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
3. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
DS40001579E-page 58
2011-2014 Microchip Technology Inc.
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6.2.2.1
HFINTOSC
6.2.2.3
Internal Oscillator Frequency
Adjustment
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 6-3).
The 500 kHz internal oscillator is factory calibrated.
This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 6-3). Since
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator a change in
the OSCTUNE register value will apply to both.
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 6-1). One of multiple
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 6.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
A fast startup oscillator allows internal circuits to power
up and stabilize before switching to HFINTOSC.
The High Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value.
6.2.2.4
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The High Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.
The output of the LFINTOSC connects to a multiplexer
(see Figure 6-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See
Section 6.2.2.7 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also
the frequency for the Power-up Timer (PWRT),
Watchdog Timer (WDT) and Fail-Safe Clock Monitor
(FSCM).
6.2.2.2
The
MFINTOSC
Medium-Frequency
Internal
Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 6-3).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 6-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 6.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• FOSC<2:0> = 100, or
The MFINTOSC is enabled by:
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
Peripherals that use the LFINTOSC are:
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running.
• Fail-Safe Clock Monitor (FSCM)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
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6.2.2.5
Internal Oscillator Frequency
Selection
6.2.2.6
32 MHz Internal Oscillator
Frequency Selection
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The Internal Oscillator Block can be used with the
4x PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz
internal clock source:
The output of the 16 MHz HFINTOSC, 500 kHz
MFINTOSC, and 31 kHz LFINTOSC connects to a
postscaler and multiplexer (see Figure 6-1). The
Internal Oscillator Frequency Select bits IRCF<3:0> of
the OSCCON register select the frequency output of the
internal oscillators. One of the following frequencies
can be selected via software:
• The FOSC bits in Configuration Words must be
set to use the INTOSC source as the device
system clock (FOSC<2:0> = 100).
• The SCS bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<2:0> in Configuration Words
(SCS<1:0> = 00).
- 32 MHz (requires 4x PLL)
- 16 MHz
• The IRCF bits in the OSCCON register must be
set to the 8 MHz or 16 MHz HFINTOSC set to use
(IRCF<3:0> = 111x).
- 8 MHz
- 4 MHz
- 2 MHz
• The SPLLEN bit in the OSCCON register must be
set to enable the 4x PLL, or the PLLEN bit of the
Configuration Words must be programmed to a
‘1’.
- 1 MHz
- 500 kHz (default after Reset)
- 250 kHz
- 125 kHz
Note:
When using the PLLEN bit of the
Configuration Words, the 4x PLL cannot
be disabled by software and the SPLLEN
option will not be available.
- 62.5 kHz
- 31.25 kHz
- 31 kHz (LFINTOSC)
The 4x PLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4x PLL with the internal oscillator.
Note:
Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli-
cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi-
tion times can be obtained between frequency changes
that use the same oscillator source.
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PIC16(L)F1782/3
6.2.2.7
Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 6-7). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
1. IRCF<3:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
See Figure 6-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 6-1.
Start-up delay specifications are located in the
oscillator tables of Section 30.0 “Electrical
Specifications”.
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FIGURE 6-7:
INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/
MFINTOSC
LFINTOSC (FSCM and WDT disabled)
HFINTOSC/
MFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
0
0
IRCF <3:0>
System Clock
HFINTOSC/
MFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC/
MFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
0
0
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Running
LFINTOSC
Start-up Time 2-cycle Sync
HFINTOSC/
MFINTOSC
= 0
0
IRCF <3:0>
System Clock
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PIC16(L)F1782/3
6.3.3
TIMER1 OSCILLATOR
6.3
Clock Switching
The Timer1 oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the T1OSO and T1OSI device
pins.
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
The Timer1 oscillator is enabled using the T1OSCEN
control bit in the T1CON register. See Section 22.0
“Timer1 Module with Gate Control” for more
information about the Timer1 peripheral.
• Default system oscillator determined by FOSC
bits in Configuration Words
• Timer1 32 kHz crystal oscillator
• Internal Oscillator Block (INTOSC)
6.3.4
TIMER1 OSCILLATOR READY
(T1OSCR) BIT
6.3.1
SYSTEM CLOCK SELECT (SCS)
BITS
The user must ensure that the Timer1 oscillator is
ready to be used before it is selected as a system clock
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the OSCSTAT register indicates whether the Timer1
oscillator is ready to be used. After the T1OSCR bit is
set, the SCS bits can be configured to select the Timer1
oscillator.
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by the
value of the FOSC<2:0> bits in the Configuration
Words.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 6-1.
6.3.2
OSCILLATOR START-UP TIMER
STATUS (OSTS) BIT
The Oscillator Start-up Timer Status (OSTS) bit of the
OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
timed out for LP, XT or HS modes. The OST does not
reflect the status of the Timer1 oscillator.
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6.4.1
TWO-SPEED START-UP MODE
CONFIGURATION
6.4
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Words) = 1;
Internal/External Switchover bit (Two-Speed
Start-up mode enabled).
• SCS (of the OSCCON register) = 00.
• FOSC<2:0> bits in the Configuration Words
configured for LP, XT or HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
Two-Speed Start-up provides benefits when the oscil-
lator module is configured for LP, XT or HS modes.
The Oscillator Start-up Timer (OST) is enabled for
these modes and must count 1024 oscillations before
the oscillator can be used as the system clock source.
• Wake-up from Sleep.
If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT
register is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
TABLE 6-1:
Switch From
OSCILLATOR SWITCHING DELAYS
Switch To
Frequency
Oscillator Delay
LFINTOSC(1)
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Sleep/POR
Oscillator Warm-up Delay (TWARM)
Sleep/POR
LFINTOSC
EC, RC(1)
EC, RC(1)
DC – 32 MHz
DC – 32 MHz
2 cycles
1 cycle of each
Timer1 Oscillator
LP, XT, HS(1)
Sleep/POR
32 kHz-20 MHz
1024 Clock Cycles (OST)
MFINTOSC(1)
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Any clock source
2 s (approx.)
HFINTOSC(1)
Any clock source
Any clock source
PLL inactive
LFINTOSC(1)
Timer1 Oscillator
PLL active
31 kHz
1 cycle of each
32 kHz
1024 Clock Cycles (OST)
2 ms (approx.)
16-32 MHz
Note 1: PLL inactive.
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PIC16(L)F1782/3
6.4.2
TWO-SPEED START-UP
SEQUENCE
6.4.3
CHECKING TWO-SPEED CLOCK
STATUS
1. Wake-up from Power-on Reset or Sleep.
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Words, or the
internal oscillator.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
FIGURE 6-8:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
0
1
1022 1023
OSC2
Program Counter
PC - N
PC + 1
PC
System Clock
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6.5.3
FAIL-SAFE CONDITION CLEARING
6.5
Fail-Safe Clock Monitor
The Fail-Safe condition is cleared after a Reset,
executing a SLEEPinstruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared after successfully
switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
OSFIF flag will again become set by hardware.
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, Timer1
Oscillator and RC).
FIGURE 6-9:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
6.5.4
RESET OR WAKE-UP FROM SLEEP
External
Clock
S
Q
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
LFINTOSC
Oscillator
÷ 64
R
Q
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
Clock
Failure
Detected
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.
6.5.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 6-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
6.5.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
DS40001579E-page 66
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PIC16(L)F1782/3
FIGURE 6-10:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
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PIC16(L)F1782/3
6.6
Register Definitions: Oscillator Control
REGISTER 6-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1
IRCF<3:0>
R/W-0/0
SPLLEN
bit 7
U-0
—
R/W-0/0
R/W-0/0
SCS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
SPLLEN: Software PLL Enable bit
If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Words = 0:
1= 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
1111= 16 MHz HF or 32 MHz HF(2)
1110= 8 MHz or 32 MHz HF(2)
1101= 4 MHz HF
1100= 2 MHz HF
1011= 1 MHz HF
1010= 500 kHz HF(1)
1001= 250 kHz HF(1)
1000= 125 kHz HF(1)
0111= 500 kHz MF (default upon Reset)
0110= 250 kHz MF
0101= 125 kHz MF
0100= 62.5 kHz MF
0011= 31.25 kHz HF(1)
0010= 31.25 kHz MF
000x= 31 kHz LF
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x= Internal oscillator block
01= Timer1 oscillator
00= Clock determined by FOSC<2:0> in Configuration Words.
Note 1: Duplicate frequency derived from HFINTOSC.
2: 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency
Selection”.
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PIC16(L)F1782/3
REGISTER 6-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
R-1/q
T1OSCR
bit 7
R-0/q
PLLR
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Conditional
bit 7
T1OSCR: Timer1 Oscillator Ready bit
If T1OSCEN = 1:
1= Timer1 oscillator is ready
0= Timer1 oscillator is not ready
If T1OSCEN = 0:
1 = Timer1 clock source is always ready
bit 6
bit 5
PLLR 4x PLL Ready bit
1= 4x PLL is ready
0= 4x PLL is not ready
OSTS: Oscillator Start-up Timer Status bit
1= Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0= Running from an internal oscillator (FOSC<2:0> = 100)
bit 4
bit 3
bit 2
bit 1
bit 0
HFIOFR: High-Frequency Internal Oscillator Ready bit
1= HFINTOSC is ready
0= HFINTOSC is not ready
HFIOFL: High-Frequency Internal Oscillator Locked bit
1= HFINTOSC is at least 2% accurate
0= HFINTOSC is not 2% accurate
MFIOFR: Medium-Frequency Internal Oscillator Ready bit
1= MFINTOSC is ready
0= MFINTOSC is not ready
LFIOFR: Low-Frequency Internal Oscillator Ready bit
1= LFINTOSC is ready
0= LFINTOSC is not ready
HFIOFS: High-Frequency Internal Oscillator Stable bit
1= HFINTOSC is at least 0.5% accurate
0= HFINTOSC is not 0.5% accurate
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REGISTER 6-3:
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
TUN<5:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: Frequency Tuning bits
100000= Minimum frequency
•
•
•
111111=
000000= Oscillator module is running at the factory-calibrated frequency.
000001=
•
•
•
011110=
011111= Maximum frequency
TABLE 6-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
OSCSTAT
OSCTUNE
PIE2
SPLLEN
T1OSCR
—
IRCF<3:0>
—
SCS<1:0>
68
69
PLLR
—
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
TUN<5:0>
70
OSEIE
OSFIF
C2IE
C2IF
C1IE
C1IF
EEIE
EEIF
BCL1IE
BCL1IF
—
—
C3IE
C3IF
—
CCP2IE
CCP2IF
81
PIR2
84
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
T1SYNC
TMR1ON
183
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 6-3:
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0>
FOSC<2:0>
CPD
CONFIG1
40
CP
MCLRE
WDTE<1:0>
Legend:
Note 1:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
PIC16F1782/3 only.
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PIC16(L)F1782/3
7.3
Conflicts with the CLKR Pin
7.0
REFERENCE CLOCK MODULE
There are two cases when the reference clock output
signal cannot be output to the CLKR pin, if:
The reference clock module provides the ability to send
a divided clock to the clock output pin of the device
(CLKR). This module is available in all oscillator config-
urations and allows the user to select a greater range
of clock submultiples to drive external devices in the
application. The reference clock module includes the
following features:
• LP, XT or HS Oscillator mode is selected.
• CLKOUT function is enabled.
7.3.1
OSCILLATOR MODES
If LP, XT or HS oscillator modes are selected, the
OSC2/CLKR pin must be used as an oscillator input pin
and the CLKR output cannot be enabled. See
Section 6.2 “Clock Source Types”for more informa-
tion on different oscillator modes.
• System clock is the source
• Available in all oscillator configurations
• Programmable clock divider
• Output enable to a port pin
• Selectable duty cycle
7.3.2
CLKOUT FUNCTION
• Slew rate control
The CLKOUT function has a higher priority than the
reference clock module. Therefore, if the CLKOUT
function is enabled by the CLKOUTEN bit in Configura-
tion Words, FOSC/4 will always be output on the port
pin. Reference Section 4.0 “Device Configuration”
for more information.
The reference clock module is controlled by the
CLKRCON register (Register 7-1) and is enabled when
setting the CLKREN bit. To output the divided clock
signal to the CLKR port pin, the CLKROE bit must be
set. The CLKRDIV<2:0> bits enable the selection of
eight
different
clock
divider
options.
The
CLKRDC<1:0> bits can be used to modify the duty
cycle of the output clock(1). The CLKRSLR bit controls
slew rate limiting.
7.4
Operation During Sleep
As the reference clock module relies on the system
clock as its source, and the system clock is disabled in
Sleep, the module does not function in Sleep, even if
an external clock source or the Timer1 clock source is
configured as the system clock. The module outputs
will remain in their current state until the device exits
Sleep.
Note 1: If the base clock rate is selected without
a divider, the output clock will always
have a duty cycle equal to that of the
source clock, unless a 0% duty cycle is
selected. If the clock divider is set to base
clock/2, then 25% and 75% duty cycle
accuracy will be dependent upon the
source clock.
7.1
Slew Rate
The slew rate limitation on the output port pin can be
disabled. The slew rate limitation is removed by
clearing the CLKRSLR bit in the CLKRCON register.
7.2
Effects of a Reset
Upon any device Reset, the reference clock module is
disabled. The user’s firmware is responsible for
initializing the module before enabling the output. The
registers are reset to their default values.
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7.5
Register Definition: Reference Clock Control
REGISTER 7-1:
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0
CLKREN
bit 7
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CLKROE
CLKRSLR
CLKRDC<1:0>
CLKRDIV<2:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CLKREN: Reference Clock Module Enable bit
1= Reference clock module is enabled
0= Reference clock module is disabled
bit 6
CLKROE: Reference Clock Output Enable bit
1= Reference clock output is enabled on CLKR pin
0= Reference clock output disabled on CLKR pin
bit 5
CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit
1= Slew rate limiting is enabled
0= Slew rate limiting is disabled
bit 4-3
CLKRDC<1:0>: Reference Clock Duty Cycle bits
11= Clock outputs duty cycle of 75%
10= Clock outputs duty cycle of 50%
01= Clock outputs duty cycle of 25%
00= Clock outputs duty cycle of 0%
bit 2-0
CLKRDIV<2:0> Reference Clock Divider bits
111= Base clock value divided by 128
110= Base clock value divided by 64
101= Base clock value divided by 32
100= Base clock value divided by 16
011= Base clock value divided by 8
010= Base clock value divided by 4
001= Base clock value divided by 2(1)
000= Base clock value(2)
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3: To route CLKR to pin, CLKOUTEN of Configuration Words = 1is required. CLKOUTEN of Configuration
Words = 0will result in FOSC/4. See Section 7.3 “Conflicts with the CLKR Pin” for details.
DS40001579E-page 72
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PIC16(L)F1782/3
TABLE 7-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
CLKRCON
CLKREN
CLKROE CLKRSLR
CLKRDC<1:0>
CLKRDIV<2:0>
72
Legend:
— = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.
TABLE 7-2:
SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0>
FOSC<2:0>
CPD
CONFIG1
40
CP
MCLRE
WDTE1<:0>
Legend:
— = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.
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DS40001579E-page 73
PIC16(L)F1782/3
8.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 8-1.
FIGURE 8-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Wake-up
(If in Sleep mode)
INTF
INTE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IE) PIE1<0>
IOCIF
IOCIE
Interrupt
to CPU
PEIE
GIE
PIRn<7>
PIEn<7>
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8.1
Operation
8.2
Interrupt Latency
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 8-2 and Figure 8.3 for more details.
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 or PIE2 registers)
The INTCON, PIR1 and PIR2 registers record individ-
ual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 8.5 “Automatic
Context Saving”.”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 8-2:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC-1
PC
PC+1
0004h
0005h
PC
1 Cycle Instruction at PC
Execute
Inst(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC+1/FSR
ADDR
New PC/
PC+1
PC-1
PC
0004h
0005h
PC
Execute
2 Cycle Instruction at PC
Inst(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
PC+2
0004h
0005h
PC
Execute
3 Cycle Instruction at PC
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
PC+2
0004h
0005h
PC
NOP
Execute
3 Cycle Instruction at PC
NOP
NOP
NOP
Inst(0004h)
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FIGURE 8-3:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
INTF
(1)
(1)
(2)
(5)
Interrupt Latency
GIE
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Forced NOP
Forced NOP
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 30.0 “Electrical Specifications””.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
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8.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEPinstruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 9.0
“Power-Down Mode (Sleep)” for more details.
8.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
8.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
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8.6
Register Definitions: Interrupt Control
REGISTER 8-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
GIE
R/W-0/0
PEIE
R/W-0/0
TMR0IE
R/W-0/0
INTE
R/W-0/0
IOCIE
R/W-0/0
TMR0IF
R/W-0/0
INTF
R-0/0
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1= Enables all active interrupts
0= Disables all interrupts
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEIE: Peripheral Interrupt Enable bit
1= Enables all active peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: Timer0 Overflow Interrupt Enable bit
1= Enables the Timer0 interrupt
0= Disables the Timer0 interrupt
INTE: INT External Interrupt Enable bit
1= Enables the INT external interrupt
0= Disables the INT external interrupt
IOCIE: Interrupt-on-Change Enable bit
1= Enables the interrupt-on-change
0= Disables the interrupt-on-change
TMR0IF: Timer0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed
0= TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1= The INT external interrupt occurred
0= The INT external interrupt did not occur
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1= When at least one of the interrupt-on-change pins changed state
0= None of the interrupt-on-change pins have changed state
Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-change flags in the IOCBF register
have been cleared by software.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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REGISTER 8-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
TMR1GIE
bit 7
R/W-0/0
ADIE
R/W-0/0
RCIE
R/W-0/0
TXIE
R/W-0/0
SSP1IE
R/W-0/0
CCP1IE
R/W-0/0
TMR2IE
R/W-0/0
TMR1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIE: Timer1 Gate Interrupt Enable bit
1= Enables the Timer1 gate acquisition interrupt
0= Disables the Timer1 gate acquisition interrupt
ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1= Enables the ADC interrupt
0= Disables the ADC interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the Timer2 to PR2 match interrupt
0= Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 8-3:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
OSFIE
bit 7
R/W-0/0
C2IE
R/W-0/0
C1IE
R/W-0/0
EEIE
R/W-0/0
BCL1IE
U-0
—
R/W-0/0
C3IE
R/W-0/0
CCP2IE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables the Oscillator Fail interrupt
0= Disables the Oscillator Fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1= Enables the Comparator C2 interrupt
0= Disables the Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1= Enables the Comparator C1 interrupt
0= Disables the Comparator C1 interrupt
EEIE: EEPROM Write Completion Interrupt Enable bit
1= Enables the EEPROM Write Completion interrupt
0= Disables the EEPROM Write Completion interrupt
BCL1IE: MSSP Bus Collision Interrupt Enable bit
1= Enables the MSSP Bus Collision Interrupt
0= Disables the MSSP Bus Collision Interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
C3IE: Comparator C3 Interrupt Enable bit
1= Enables the Comparator C3 Interrupt
0= Disables the Comparator C3 Interrupt
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 8-4:
PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
U-0
—
U-0
—
R/W-0/0
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
PSMC2TIE PSMC1TIE
PSMC2SIE PSMC1SIE
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
Unimplemented: Read as ‘0’
PSMC2TIE: PSMC2 Time Base Interrupt Enable bit
1= Enables PSMC2 time base generated interrupts
0= Disables PSMC2 time base generated interrupts
bit 4
PSMC1TIE: PSMC1 Time Base Interrupt Enable bit
1= Enables PSMC1 time base generated interrupts
0= Disables PSMC1 time base generated interrupts
bit 3-2
bit 1
Unimplemented: Read as ‘0’
PSMC2SIE: PSMC2 Auto-Shutdown Interrupt Enable bit
1= Enables PSMC2 auto-shutdown interrupts
0= Disables PSMC2 auto-shutdown interrupts
bit 0
PSMC1SIE: PSMC1 Auto-Shutdown Interrupt Enable bit
1= Enables PSMC1 auto-shutdown interrupts
0= Disables PSMC1 auto-shutdown interrupts
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 8-5:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
TMR1GIF
bit 7
R/W-0/0
ADIF
R-0/0
RCIF
R-0/0
TXIF
R/W-0/0
SSP1IF
R/W-0/0
CCP1IF
R/W-0/0
TMR2IF
R/W-0/0
TMR1IF
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIF: Timer1 Gate Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
ADIF: ADC Converter Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
RCIF: USART Receive Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TXIF: USART Transmit Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
CCP1IF: CCP1 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TMR1IF: Timer1 Overflow Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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REGISTER 8-6:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
OSFIF
R/W-0/0
C2IF
R/W-0/0
C1IF
R/W-0/0
EEIF
R/W-0/0
BCL1IF
U-0
—
R/W-0/0
C3IF
R/W-0/0
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
OSFIF: Oscillator Fail Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
C2IF: Comparator C2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
C1IF: Comparator C1 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
EEIF: EEPROM Write Completion Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
BCL1IF: MSSP Bus Collision Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 2
bit 1
Unimplemented: Read as ‘0’
C3IF: Comparator C3 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 0
CCP2IF: CCP2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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REGISTER 8-7:
PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
U-0
—
U-0
—
R/W-0/0
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
PSMC2TIF PSMC1TIF
PSMC2SIF PSMC1SIF
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
Unimplemented: Read as ‘0’
PSMC2TIF: PSMC2 Time Base Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 4
PSMC1TIF: PSMC1 Time Base Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 3-2
bit 1
Unimplemented: Read as ‘0’
PSMC2SIF: PSMC2 Auto-shutdown Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 0
PSMC1SIF: PSMC1 Auto-shutdown Flag bit
1= Interrupt is pending
0= Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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TABLE 8-1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
OPTION_REG
PIE1
GIE
PEIE
INTEDG
ADIE
TMR0IE
TMR0CS
RCIE
INTE
TMR0SE
TXIE
IOCIE
PSA
TMR0IF
INTF
PS<2:0>
TMR2IE
C3IE
IOCIF
79
174
80
81
—
WPUEN
TMR1GIE
OSEIE
SSP1IE
BCL1IE
CCP1IE
—
TMR1IE
CCP2IE
PIE2
C2IE
C1IE
EEIE
—
Unimplemented
—
PIE4
—
PSMC2TIE PSMC1TIE
—
—
CCP1IF
—
PSMC2SIE PSMC1SIE
82
83
84
—
PIR1
TMR1GIF
OSFIF
ADIF
C2IF
RCIF
C1IF
TXIF
EEIF
SSP1IF
BCL1IF
TMR2IF
C3IF
TMR1IF
CCP2IF
PIR2
—
Unimplemented
—
PIR4
—
PSMC2TIF PSMC1TIF
—
—
PSMC2SIF PSMC1SIF
85
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.
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9.1
Wake-up from Sleep
9.0
POWER-DOWN MODE (SLEEP)
The device can wake-up from Sleep through one of the
following events:
The Power-down mode is entered by executing a
SLEEPinstruction.
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
Upon entering Sleep mode, the following conditions
exist:
3. POR Reset
1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.
4. Watchdog Timer, if enabled
5. Any external interrupt
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
The first three events will cause a device Reset. The
last three events are considered a continuation of
program execution. To determine whether a device
Reset or wake-up event occurred, refer to
Section 5.12 “Determining the Cause of a Reset”.
6. Timer1 and peripherals that operate from Tim-
er1 continue operation in Sleep when the Tim-
er1 clock source selected is:
•
•
•
LFINTOSC
T1CKI
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEPinstruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
Timer1 oscillator
7. ADC is unaffected, if the dedicated FRC
oscillator is selected.
8. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or
high-impedance).
9. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• Modules using Timer1 oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 19.0 “Digital-to-Analog
Converter (DAC) Module” and Section 15.0 “Fixed
Voltage Reference (FVR)” for more information on
these modules.
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• If the interrupt occurs during or after the
execution of a SLEEPinstruction
9.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
- SLEEPinstruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
• If the interrupt occurs before the execution of a
SLEEPinstruction
- SLEEPinstruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
- PD bit of the STATUS register will not be
cleared.
FIGURE 9-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
(3)
CLKOUT(2)
T1OSC
Interrupt Latency(4)
Interrupt flag
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Instruction
Executed
Forced NOP
Forced NOP
Sleep
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1:
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
T1OSC; See Section 30.0 “Electrical Specifications”.
GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
2:
3:
4:
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9.2.2
PERIPHERAL USAGE IN SLEEP
9.2
Low-Power Sleep Mode
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the normal power
mode when those peripherals are enabled. The
Low-Power Sleep mode is intended for use with these
peripherals:
“F” devices contain an internal Low Dropout (LDO)
voltage regulator, which allows the device I/O pins to
operate at voltages up to 5.5V while the internal device
logic operates at a lower voltage. The LDO and its
associated reference circuitry must remain active when
the device is in Sleep mode. “F” devices allow the user
to optimize the operating current in Sleep, depending
on the application requirements.
• Brown-Out Reset (BOR)
• Watchdog Timer (WDT)
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
• External interrupt pin/Interrupt-on-change pins
• Timer1 (with external clock source)
Note:
“LF” devices do not have a configurable
Low-Power Sleep mode. “LF” devices are
an unregulated device and are always in
the lowest power state when in Sleep, with
no wake-up time penalty. These devices
have a lower maximum VDD and I/O
9.2.1
SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
voltage
than
“F”
devices.
See
Section 30.0 “Electrical Specifications”
for more information.
The Low-Power Sleep mode is beneficial for applica-
tions that stay in Sleep mode for long periods of time.
The normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
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9.3
Register Definitions: Voltage Regulator Control
REGISTER 9-1:
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-1/1
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
VREGPM: Voltage Regulator Power Mode Selection bit
1= Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0= Normal-Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0
Reserved: Read as ‘1’. Maintain this bit set.
Note 1: “F” devices only.
2: See Section 30.0 “Electrical Specifications”.
TABLE 9-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
IOCBF
IOCBN
IOCBP
PIE1
GIE
PEIE
IOCBF6
IOCBN6
IOCBP6
ADIE
TMR0IE
IOCBF5
IOCBN5
IOCBP5
RCIE
INTE
IOCBF4
IOCBN4
IOCBP4
TXIE
IOCIE
IOCBF3
IOCBN3
IOCBP3
SSP1IE
BCL1IE
TMR0IF
IOCBF2
IOCBN2
IOCBP2
CCP1IE
—
INTF
RAIF
79
134
133
133
80
IOCBF7
IOCBN7
IOCBP7
TMR1GIE
OSEIE
IOCBF1
IOCBN1
IOCBP1
TMR2IE
C3IE
IOCBF0
IOCBN0
IOCBP0
TMR1IE
CCP2IE
PIE2
C2IE
C1IE
EEIE
81
—
Unimplemented
—
PIE4
—
—
PSMC2TIE PSMC1TIE
—
—
CCP1IF
—
PSMC2SIE PSMC1SIE
82
PIR1
TMR1GIF
ADIF
C2IF
RCIF
C1IF
TXIF
EEIF
SSP1IF
BCL1IF
TMR2IF
C3IF
TMR1IF
CCP2IF
80
PIR2
OSFIF
84
—
Unimplemented
—
PIR4
—
—
—
—
—
—
—
—
PSMC2TIF PSMC1TIF
—
—
Z
PSMC2SIF PSMC1SIF
85
STATUS
VREGCON
WDTCON
Legend:
—
—
TO
—
PD
—
DC
C
18
—
VREGPM
Reserved
SWDTEN
90
WDTPS<4:0>
94
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.
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On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is held in Reset while a constant current source
charges the external capacitor. After the cap is fully
charged, the device is released from Reset. For more
information on the constant current rate, refer to the
LDO Regulator Characteristics Table in Section 30.0
“Electrical Specifications”.
10.0 LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The “F” devices have an internal Low Dropout
Regulator (LDO) which provide operation above 3.6V.
The LDO regulates a voltage for the internal device
logic while permitting the VDD and I/O pins to operate
at a higher voltage. There is no user enable/disable
control available for the LDO, it is always active. The
“LF” devices operate at a maximum VDD of 3.6V and
does not incorporate an LDO.
A device I/O pin may be configured as the LDO voltage
output, identified as the VCAP pin. Although not
required, an external low-ESR capacitor may be
connected to the VCAP pin for additional regulator
stability.
The VCAPEN bit of Configuration Words determines if
which pin is assigned as the VCAP pin. Refer to
Table 10-1.
TABLE 10-1: VCAPEN SELECT BIT
VCAPEN
Pin
1
0
No VCAP
RA6
TABLE 10-2: SUMMARY OF CONFIGURATION WORD WITH LDO
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
—
—
LVP
VCAPEN(1)
DEBUG
—
LPBOR
—
BORV
—
STVREN
PLLEN
CONFIG2
42
WRT<1:0>
Legend:
— = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
Note 1: “F” devices only.
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11.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 11-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
23-bit Programmable
Prescaler WDT
WDTE<1:0> = 11
LFINTOSC
WDT Time-out
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
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11.1 Independent Clock Source
11.3 Time-Out Period
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Section 30.0 “Electrical Specifications” for the
LFINTOSC tolerances.
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.
11.4 Clearing the WDT
11.2 WDT Operating Modes
The WDT is cleared when any of the following
conditions occur:
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Words. See Table 11-1.
• Any Reset
• CLRWDTinstruction is executed
• Device enters Sleep
11.2.1
WDT IS ALWAYS ON
• Device wakes up from Sleep
• Oscillator fail
When the WDTE bits of Configuration Words are set to
‘11’, the WDT is always on.
• WDT is disabled
WDT protection is active during Sleep.
• Oscillator Start-up TImer (OST) is running
11.2.2
WDT IS OFF IN SLEEP
See Table 11-2 for more information.
When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep.
11.5 Operation During Sleep
WDT protection is not active during Sleep.
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
11.2.3
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Words are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 6.0 “Oscillator
Module (with Fail-Safe Clock Monitor)” for more
information on the OST.
WDT protection is unchanged by Sleep. See
Table 11-1 for more details.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See Section 3.0 “Memory Organization” and
Status Register (Register 3-1) for more information.
TABLE 11-1: WDT OPERATING MODES
Device
Mode
WDT
Mode
WDTE<1:0>
SWDTEN
11
10
X
X
X
Active
Awake Active
Sleep Disabled
1
0
X
Active
X
01
00
Disabled
X
Disabled
TABLE 11-2: WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDTCommand
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
Unaffected
Change INTOSC divider (IRCF bits)
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11.6 Register Definitions: Watchdog Control
REGISTER 11-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
WDTPS<4:0>
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-m/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-1
Unimplemented: Read as ‘0’
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1= WDT is turned on
0= WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.
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TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
STATUS
SPLLEN
IRCF<3:0>
—
Z
SCS<1:0>
68
18
94
—
—
—
—
—
TO
PD
DC
C
WDTCON
WDTPS<4:0>
SWDTEN
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Watchdog Timer.
TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0>
FOSC<2:0>
CPD
CONFIG1
40
CP
MCLRE
WDTE<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
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12.1 EEADRL and EEADRH Registers
12.0 DATA EEPROM AND FLASH
PROGRAM MEMORY
CONTROL
The EEADRH:EEADRL register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 32K words of program memory.
The data EEPROM and Flash program memory are
readable and writable during normal operation (full VDD
range). These memories are not directly mapped in the
register file space. Instead, they are indirectly
addressed through the Special Function Registers
(SFRs). There are six SFRs used to access these
memories:
When selecting a program address value, the MSB of
the address is written to the EEADRH register and the
LSB is written to the EEADRL register. When selecting
a EEPROM address value, only the LSB of the address
is written to the EEADRL register.
12.1.1
EECON1 AND EECON2 REGISTERS
• EECON1
• EECON2
• EEDATL
• EEDATH
• EEADRL
• EEADRH
EECON1 is the control register for EE memory
accesses.
Control bit EEPGD determines if the access will be a
program or data memory access. When clear, any
subsequent operations will operate on the EEPROM
memory. When set, any subsequent operations will
operate on the program memory. On Reset, EEPROM is
selected by default.
When interfacing the data memory block, EEDATL
holds the 8-bit data for read/write, and EEADRL holds
the address of the EEDATL location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 0h to 0FFh.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
When accessing the program memory block, the
EEDATH:EEDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
EEADRL and EEADRH registers form a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The EEPROM data memory allows byte read and write.
An EEPROM byte write automatically erases the
location and writes the new data (erase before write).
Interrupt flag bit EEIF of the PIR2 register is set when
write is complete. It must be cleared in the software.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
Reading EECON2 will read all ‘0’s. The EECON2
register is used exclusively in the data EEPROM write
sequence. To enable writes, a specific pattern must be
written to EECON2.
Depending on the setting of the Flash Program
Memory Self Write Enable bits WRT<1:0> of the
Configuration Words, the device may or may not be
able to write certain blocks of the program memory.
However, reads from the program memory are always
allowed.
When the device is code-protected, the device
programmer can no longer access data or program
memory. When code-protected, the CPU may continue
to read and write the data EEPROM memory and Flash
program memory.
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12.2.2
WRITING TO THE DATA EEPROM
MEMORY
12.2 Using the Data EEPROM
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often). When
variables in one section change frequently, while
variables in another section do not change, it is
possible to exceed the total number of write cycles to
the EEPROM without exceeding the total number of
write cycles to a single byte. Refer to Section 30.0
“Electrical Specifications”. If this is the case, then a
refresh of the array must be performed. For this reason,
variables that change infrequently (such as constants,
IDs, calibration, etc.) should be stored in Flash program
memory.
To write an EEPROM data location, the user must first
write the address to the EEADRL register and the data
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set the WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
12.2.1
READING THE DATA EEPROM
MEMORY
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD and
CFGS control bits of the EECON1 register, and then
set control bit RD. The data is available at the very next
cycle, in the EEDATL register; therefore, it can be read
in the next instruction. EEDATL will hold this value until
another read or until it is written to by the user (during
a write operation).
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
12.2.3
PROTECTION AGAINST SPURIOUS
WRITE
EXAMPLE 12-1:
DATA EEPROM READ
BANKSELEEADRL
;
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also, the
Power-up Timer (64 ms duration) prevents EEPROM
write.
MOVLW
MOVWF
DATA_EE_ADDR ;
EEADRL
;Data Memory
;Address to read
EECON1, CFGS ;Deselect Config space
EECON1, EEPGD;Point to DATA memory
BCF
BCF
BSF
MOVF
EECON1, RD
EEDATL, W
;EE Read
;W = EEDATL
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• Brown-out
Note:
Data EEPROM can be read regardless of
the setting of the CPD bit.
• Power Glitch
• Software Malfunction
12.2.4
DATA EEPROM OPERATION
DURING CODE-PROTECT
Data memory can be code-protected by programming
the CPD bit in the Configuration Words to ‘0’.
When the data memory is code-protected, only the
CPU is able to read and write data to the data
EEPROM. It is recommended to code-protect the
program memory when code-protecting data memory.
This prevents anyone from replacing your program with
a program that will access the contents of the data
EEPROM.
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EXAMPLE 12-2:
DATA EEPROM WRITE
BANKSEL EEADRL
;
MOVLW
MOVWF
MOVLW
MOVWF
BCF
DATA_EE_ADDR
EEADRL
DATA_EE_DATA
EEDATL
;
;Data Memory Address to write
;
;Data Memory Value to write
;Deselect Configuration space
EECON1, CFGS
BCF
EECON1, EEPGD ;Point to DATA memory
BSF
EECON1, WREN
;Enable writes
BCF
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
EECON1, WR
$-2
;Disable INTs.
;
;Write 55h
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BTFSC
GOTO
;Write AAh
;Set WR bit to begin write
;Enable Interrupts
;Disable writes
;Wait for write to complete
;Done
FIGURE 12-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
PC + 1
EEADRH,EEADRL
PC + 3
PC + 4
PC + 5
Flash ADDR
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDATL
INSTR (PC + 3)
INSTR (PC + 4)
BSF PMCON1,RD
executed here
INSTR(PC - 1)
executed here
INSTR(PC + 1)
executed here
Forced NOP
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
EEDATH
EEDATL
Register
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12.3.1
READING THE FLASH PROGRAM
MEMORY
12.3 Flash Program Memory Overview
It is important to understand the Flash program
memory structure for erase and programming
operations. Flash program memory is arranged in
rows. A row consists of a fixed number of 14-bit
program memory words. A row is the minimum block
size that can be erased by user software.
To read a program memory location, the user must:
1. Write the Least and Most Significant address
bits to the EEADRH:EEADRL register pair.
2. Clear the CFGS bit of the EECON1 register.
3. Set the EEPGD control bit of the EECON1
register.
Flash program memory may only be written or erased
if the destination address is in a segment of memory
that is not write-protected, as defined in bits WRT<1:0>
of Configuration Words.
4. Then, set control bit RD of the EECON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF EECON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the EEDATH:EEDATL register pair; therefore, it can
be read as two bytes in the following instructions.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the EEDATH:EEDATL register pair.
EEDATH:EEDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Note 1: The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
The number of data write latches may not be equivalent
to the number of row locations. During programming,
user software may need to fill the set of write latches
and initiate a programming operation multiple times in
order to fully reprogram an erased row. For example, a
device with a row size of 32 words and eight write
latches will need to load the write latches with data and
initiate a programming operation four times.
2: Flash program memory can be read
regardless of the setting of the CP bit.
The size of a program memory row and the number of
program memory write latches may vary by device.
See Table 12-1 for details.
TABLE 12-1: FLASH MEMORY ORGANIZATION BY DEVICE
Device
Erase Block (Row) Size/Boundary
Number of Write Latches/Boundary
PIC16(L)F1782/3
32 words, EEADRL<4:0> = 00000
32 words, EEADRL<4:0> = 00000
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EXAMPLE 12-3:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
*
*
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL
; Select Bank for EEPROM registers
MOVLW
MOVWF
MOVLW
MOVWL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
; Do not select Configuration Space
; Select Program Memory
; Disable interrupts
; Initiate read
; Executed (Figure 12-1)
; Ignored (Figure 12-1)
; Restore interrupts
INTCON,GIE
MOVF
EEDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
EEDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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PIC16(L)F1782/3
unlock sequence is required to load a write latch with
data or initiate a Flash programming operation. This
unlock sequence should not be interrupted.
12.3.2
ERASING FLASH PROGRAM
MEMORY
While executing code, program memory can only be
erased by rows. To erase a row:
1. Set the EEPGD and WREN bits of the EECON1
register.
1. Load the EEADRH:EEADRL register pair with
the address of new row to be erased.
2. Clear the CFGS bit of the EECON1 register.
3. Set the LWLO bit of the EECON1 register. When
the LWLO bit of the EECON1 register is ‘1’, the
write sequence will only load the write latches
and will not initiate the write to Flash program
memory.
2. Clear the CFGS bit of the EECON1 register.
3. Set the EEPGD, FREE, and WREN bits of the
EECON1 register.
4. Write 55h, then AAh, to EECON2 (Flash
programming unlock sequence).
4. Load the EEADRH:EEADRL register pair with
the address of the location to be written.
5. Set control bit WR of the EECON1 register to
begin the erase operation.
5. Load the EEDATH:EEDATL register pair with
the program memory data to be written.
6. Poll the FREE bit in the EECON1 register to
determine when the row erase has completed.
6. Write 55h, then AAh, to EECON2, then set the
WR bit of the EECON1 register (Flash
programming unlock sequence). The write latch
is now loaded.
See Example 12-4.
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOPinstructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the EECON1 write instruction.
7. Increment the EEADRH:EEADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the EECON1 register.
When the LWLO bit of the EECON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
12.3.3
WRITING TO FLASH PROGRAM
MEMORY
10. Load the EEDATH:EEDATL register pair with
the program memory data to be written.
Program memory is programmed using the following
steps:
11. Write 55h, then AAh, to EECON2, then set the
WR bit of the EECON1 register (Flash
programming unlock sequence). The entire
latch block is now written to Flash program
memory.
1. Load the starting address of the word(s) to be
programmed.
2. Load the write latches with data.
3. Initiate a programming operation.
It is not necessary to load the entire write latch block
with user program data. However, the entire write latch
block will be written to program memory.
4. Repeat steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten.
Program memory can only be erased one row at a time.
No automatic erase occurs upon the initiation of the
write.
An example of the complete write sequence for eight
words is shown in Example 12-5. The initial address is
loaded into the EEADRH:EEADRL register pair; the
eight words of data are loaded using indirect addressing.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 12-2 (block writes to program memory with 32
write latches) for more details. The write latches are
aligned to the address boundary defined by EEADRL
as shown in Table 12-1. Write operations do not cross
these boundaries. At the completion of a program
memory write operation, the write latches are reset to
contain 0x3FFF.
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the write operation. The
user must place two NOPinstructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
continue to run. The processor does not stall when
LWLO = 1, loading the write latches. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 WRITEinstruction.
The following steps should be completed to load the
write latches and program a block of program memory.
These steps are divided into two parts. First, all write
latches are loaded with data except for the last program
memory location. Then, the last write latch is loaded
and the programming sequence is initiated. A special
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FIGURE 12-2:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
7
5
0
0 7
EEDATH
6
EEDATA
8
Last word of block
to be written
First word of block
to be written
14
14
14
14
EEADRL<4:0> = 00000
EEADRL<4:0> = 00001
EEADRL<4:0> = 00010
EEADRL<4:0> = 11111
Buffer Register
Buffer Register
Buffer Register
Buffer Register
Program Memory
EXAMPLE 12-4:
ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase block is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
INTCON,GIE
EEADRL
ADDRL,W
EEADRL
ADDRH,W
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
BSF
BSF
EEADRH
EECON1,EEPGD
EECON1,CFGS
EECON1,FREE
EECON1,WREN
; Point to program memory
; Not configuration space
; Specify an erase operation
; Enable writes
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
0AAh
EECON2
EECON1,WR
; Start of required sequence to initiate erase
; Write 55h
;
; Write AAh
; Set WR bit to begin erase
; Any instructions here are ignored as processor
; halts to begin erase sequence
; Processor will stop here and wait for erase complete.
NOP
NOP
; after erase processor continues with 3rd instruction
BCF
BSF
EECON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
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EXAMPLE 12-5:
WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
;
stored in little endian format
; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
BCF
INTCON,GIE
EEADRH
ADDRH,W
EEADRH
ADDRL,W
EEADRL
; Disable ints so required sequences will execute properly
; Bank 3
; Load initial address
;
;
;
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
LOW DATA_ADDR ; Load initial data address
FSR0L
HIGH DATA_ADDR ; Load initial data address
;
FSR0H
;
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,LWLO
; Point to program memory
; Not configuration space
; Enable writes
BCF
BSF
BSF
; Only Load Write Latches
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
EEDATL
FSR0++
EEDATH
; Load first data byte into lower
;
; Load second data byte into upper
;
MOVF
EEADRL,W
0x07
0x07
STATUS,Z
START_WRITE
; Check if lower bits of address are '000'
; Check if we're on the last of 8 addresses
;
; Exit if last of eight words,
;
XORLW
ANDLW
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
0AAh
EECON2
EECON1,WR
; Start of required write sequence:
; Write 55h
;
; Write AAh
; Set WR bit to begin write
NOP
; Any instructions here are ignored as processor
; halts to begin write sequence
NOP
; Processor will stop here and wait for write to complete.
; After write processor continues with 3rd instruction.
INCF
GOTO
EEADRL,F
LOOP
; Still loading latches Increment address
; Write next latches
START_WRITE
BCF
EECON1,LWLO
; No more loading latches - Actually start Flash program
; memory write
MOVLW
55h
EECON2
0AAh
EECON2
EECON1,WR
; Start of required write sequence:
; Write 55h
;
MOVWF
MOVLW
MOVWF
BSF
; Write AAh
; Set WR bit to begin write
; Any instructions here are ignored as processor
; halts to begin write sequence
; Processor will stop here and wait for write complete.
NOP
NOP
; after write processor continues with 3rd instruction
; Disable writes
; Enable interrupts
BCF
BSF
EECON1,WREN
INTCON,GIE
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12.4 Modifying Flash Program Memory
12.5 User ID, Device ID and
Configuration Word Access
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
Instead of accessing program memory or EEPROM
data memory, the User ID’s, Device ID/Revision ID and
Configuration Words can be accessed when CFGS = 1
in the EECON1 register. This is the region that would
be pointed to by PC<15> = 1, but not all addresses are
accessible. Different access may exist for reads and
writes. Refer to Table 12-2.
1. Load the starting address of the row to be
modified.
2. Read the existing data from the row into a RAM
image.
When read access is initiated on an address outside the
parameters listed in Table 12-2, the EEDATH:EEDATL
register pair is cleared.
3. Modify the RAM image to contain the new data
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
8. Repeat steps 6 and 7 as many times as required
to reprogram the erased row.
TABLE 12-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
8006h
User IDs
Yes
Yes
Yes
Yes
No
No
Device ID/Revision ID
Configuration Words 1 and 2
8007h-8008h
EXAMPLE 12-3: CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL
; Select correct Bank
;
; Store LSB of address
; Clear MSB of address
MOVLW
MOVWF
CLRF
PROG_ADDR_LO
EEADRL
EEADRH
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
INTCON,GIE
EECON1,RD
; Select Configuration Space
; Disable interrupts
; Initiate read
; Executed (See Figure 12-1)
; Ignored (See Figure 12-1)
; Restore interrupts
INTCON,GIE
MOVF
EEDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
EEDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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12.6 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM or program memory should be verified (see
Example 12-6) to the desired value to be written.
Example 12-6 shows how to verify a write to EEPROM.
EXAMPLE 12-6:
EEPROM WRITE VERIFY
BANKSELEEDATL
;
MOVF
EEDATL, W ;EEDATL not changed
;from previous write
BSF
EECON1, RD ;YES, Read the
;value written
XORWF
BTFSS
GOTO
:
EEDATL, W
;
STATUS, Z ;Is data the same
WRITE_ERR ;No, handle error
;Yes, continue
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12.7 Register Definitions: EEPROM and Flash Control
REGISTER 12-1: EEDATL: EEPROM DATA LOW BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory
REGISTER 12-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
EEDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 12-3: EEADRL: EEPROM ADDRESS REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
REGISTER 12-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER
U-1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
(1)
—
EEADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘1’
bit 6-0
Note 1:
EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address
Unimplemented, read as ‘1’.
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REGISTER 12-5: EECON1: EEPROM CONTROL 1 REGISTER
R/W-0/0
EEPGD
R/W-0/0
CFGS
R/W-0/0
LWLO
R/W/HC-0/0
FREE
R/W-x/q
WRERR
R/W-0/0
WREN
R/S/HC-0/0 R/S/HC-0/0
WR RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
bit 5
EEPGD: Flash Program/Data EEPROM Memory Select bit
1= Accesses program space Flash memory
0= Accesses data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Accesses Configuration, User ID and Device ID registers
0= Accesses Flash program or data EEPROM memory
LWLO: Load Write Latches Only bit
If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash):
1= The next WR command does not initiate a write; only the program memory latches are
updated.
0= The next WR command writes a value from EEDATH:EEDATL into program memory latches
and initiates a write of all the data stored in the program memory latches.
If CFGS = 0 and EEPGD = 0: (Accessing data EEPROM)
LWLO is ignored. The next WR command initiates a write to the data EEPROM.
bit 4
FREE: Program Flash Erase Enable bit
If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash):
1= Performs an erase operation on the next WR command (cleared by hardware after comple-
tion of erase).
0= Performs a write operation on the next WR command.
If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM)
FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.
bit 3
WRERR: EEPROM Error Flag bit
1= Condition indicates an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (write ‘1’) of the WR bit).
0= The program or erase operation completed normally.
bit 2
bit 1
WREN: Program/Erase Enable bit
1= Allows program/erase cycles
0= Inhibits programming/erasing of program Flash and data EEPROM
WR: Write Control bit
1= Initiates a program Flash or data EEPROM program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0= Program/erase operation to the Flash or data EEPROM is complete and inactive.
bit 0
RD: Read Control bit
1= Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in
hardware. The RD bit can only be set (not cleared) in software.
0= Does not initiate a program Flash or data EEPROM data read.
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REGISTER 12-6: EECON2: EEPROM CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
EEPROM Control Register 2
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit can only be set
‘1’ = Bit is set
bit 7-0
Data EEPROM Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
EECON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes. Refer to Section 12.2.2 “Writing to the Data EEPROM
Memory” for more information.
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EECON1
EECON2
EEADRL
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
107
108*
106
106
106
106
79
EEPROM Control Register 2 (not a physical register)
EEADRL<7:0>
(1)
EEADRH
EEDATL
—
EEADRH<6:0>
EEDATL<7:0>
EEDATH
INTCON
PIE2
—
—
EEDATH<5:0>
GIE
PEIE
C2IE
C2IF
TMR0IE
C1IE
INTE
EEIE
EEIF
IOCIE
BCL1IE
BCL1IF
TMR0IF
INTF
C3IE
C3IF
IOCIF
CCP2IE
CCP2IF
OSEIE
OSFIF
—
—
81
PIR2
C1IF
84
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by data EEPROM module.
*
Page provides register information.
2: Unimplemented, read as ‘1’.
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FIGURE 13-1:
GENERIC I/O PORT
OPERATION
13.0 I/O PORTS
Each port has three standard registers for its operation.
These registers are:
• TRISx registers (data direction)
Read LATx
• PORTx registers (reads the levels on the pins of
the device)
TRISx
D
Q
• LATx registers (output latch)
Write LATx
Write PORTx
Some ports may have one or more of the following
additional registers. These registers are:
CK
Data Register
VDD
• ANSELx (analog select)
• WPUx (weak pull-up)
Data Bus
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
I/O pin
Read PORTx
To digital peripherals
To analog peripherals
VSS
ANSELx
TABLE 13-1: PORT AVAILABILITY PER
DEVICE
Device
PIC16(L)F1782
PIC16(L)F1783
●
●
●
●
●
●
●
●
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 13-1.
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13.1 Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 13-1. For this device family, the
following functions can be moved between different
pins.
• C2OUT output
• CCP1 output
• SDO output
• SCL/SCK output
• SDA/SDI output
• TX/RX output
• CCP2 output
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
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13.2 Register Definitions: Alternate Pin Function Control
REGISTER 13-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SCKSEL
R/W-0/0
SDISEL
R/W-0/0
TXSEL
R/W-0/0
RXSEL
R/W-0/0
C2OUTSEL
CCP1SEL
SDOSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C2OUTSEL: C2OUT Pin Selection bit
1= C2OUT is on pin RA6
0= C2OUT is on pin RA5
CCP1SEL: CCP1 Input/Output Pin Selection bit
1= CCP1 is on pin RB0
0= CCP1 is on pin RC2
SDOSEL: MSSP SDO Pin Selection bit
1= SDO is on pin RB5
0= SDO is on pin RC5
SCKSEL: MSSP Serial Clock (SCL/SCK) Pin Selection bit
1= SCL/SCK is on pin RB7
0= SCL/SCK is on pin RC3
SDISEL: MSSP Serial Data (SDA/SDI) Output Pin Selection bit
1= SDA/SDI is on pin RB6
0= SDA/SDI is on pin RC4
TXSEL: TX Pin Selection bit
1= TX is on pin RB6
0= TX is on pin RC6
RXSEL: RX Pin Selection bit
1= RX is on pin RB7
0= RX is on pin RC7
CCP2SEL: CCP2 Input/Output Pin Selection bit
1= CCP2 is on pin RB3
0= CCP2 is on pin RC1
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13.3.5
INPUT THRESHOLD CONTROL
13.3 PORTA Registers
The INLVLA register (Register 13-9) controls the input
voltage threshold for each of the available PORTA input
pins. A selection between the Schmitt Trigger CMOS or
the TTL Compatible thresholds is available. The input
threshold is important in determining the value of a
read of the PORTA register and also the level at which
an interrupt-on-change occurs, if that feature is
enabled. See Section TABLE 30-1: “Supply Voltage”
for more information on threshold levels.
13.3.1
DATA REGISTER
PORTA is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 13-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 13-1 shows how to
initialize PORTA.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
Reading the PORTA register (Register 13-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
active may inadvertently generate
a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
13.3.2
DIRECTION CONTROL
13.3.6
ANALOG CONTROL
The TRISA register (Register 13-3) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.
The ANSELA register (Register 13-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
13.3.3
OPEN DRAIN CONTROL
The ODCONA register (Register 13-7) controls the
open-drain feature of the port. Open drain operation is
independently selected for each pin. When an
ODCONA bit is set, the corresponding port output
becomes an open drain driver capable of sinking
current only. When an ODCONA bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
13.3.4
SLEW RATE CONTROL
EXAMPLE 13-1:
INITIALIZING PORTA
The SLRCONA register (Register 13-8) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONA bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONA bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
BANKSEL PORTA
CLRF PORTA
BANKSEL LATA
CLRF LATA
BANKSEL ANSELA
CLRF ANSELA
BANKSEL TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
MOVLW
MOVWF
B'00111000' ;Set RA<5:3> as inputs
TRISA
;and set RA<2:0> as
;outputs
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13.3.7
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 13-2.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC, and comparator
inputs, are not shown in the priority lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELx registers. Digital output functions may
control the pin when it is in Analog mode with the
priority shown in the priority list.
TABLE 13-2: PORTA OUTPUT PRIORITY
Pin Name
Function Priority(1)
RA0
RA1
RA0
OPA1OUT
RA1
RA2
DACOUT1
RA2
RA3
RA4
RA3
C1OUT
RA4
RA5
RA6
C2OUT
RA5
CLKOUT
C2OUT
RA6
RA7
RA7
Note 1: Priority listed from highest to lowest.
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13.4 Register Definitions: PORTA
REGISTER 13-2: PORTA: PORTA REGISTER
R/W-x/x
RA7
R/W-x/x
RA6
R/W-x/x
RA5
R/W-x/x
RA4
R/W-x/x
RA3
R/W-x/x
RA2
R/W-x/x
RA1
R/W-x/x
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
(1)
bit 7-0
RA<7:0>: PORTA I/O Value bits
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of
actual I/O pin values.
REGISTER 13-3: TRISA: PORTA TRI-STATE REGISTER
R/W-1/1
TRISA7
R/W-1/1
TRISA6
R/W-1/1
TRISA5
R/W-1/1
TRISA4
R/W-1/1
TRISA3
R/W-1/1
TRISA2
R/W-1/1
TRISA1
R/W-1/1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
TRISA<7:0>: PORTA Tri-State Control bits
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
REGISTER 13-4: LATA: PORTA DATA LATCH REGISTER
R/W-x/u
LATA7
R/W-x/u
LATA6
R/W-x/u
LATA5
R/W-x/u
LATA4
R/W-x/u
LATA3
R/W-x/u
LATA2
R/W-x/u
LATA1
R/W-x/u
LATA0
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
(1)
bit 7-4
LATA<7:0>: PORTA Output Latch Value bits
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of
actual I/O pin values.
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REGISTER 13-5: ANSELA: PORTA ANALOG SELECT REGISTER
R/W-1/1
ANSA7
U-0
—
R/W-1/1
ANSA5
R/W-1/1
ANSA4
R/W-1/1
ANSA3
R/W-1/1
ANSA2
R/W-1/1
ANSA1
R/W-1/1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 5
ANSA7: Analog Select between Analog or Digital Function on pins RA7, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 6
Unimplemented: Read as ‘0’
bit 5-0
ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 13-6: WPUA: WEAK PULL-UP PORTA REGISTER
R/W-1/1
WPUA7
R/W-1/1
WPUA6
R/W-1/1
WPUA5
R/W-1/1
WPUA4
R/W-1/1
WPUA3
R/W-1/1
WPUA2
R/W-1/1
WPUA1
R/W-1/1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
WPUA<7:0>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
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REGISTER 13-7: ODCONA: PORTA OPEN DRAIN CONTROL REGISTER
R/W-0/0
ODA7
R/W-0/0
ODA6
R/W-0/0
ODA5
R/W-0/0
ODA4
R/W-0/0
ODA3
R/W-0/0
ODA2
R/W-0/0
ODA1
R/W-0/0
ODA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ODA<7:0>: PORTA Open Drain Enable bits
For RA<7:0> pins, respectively
1= Port pin operates as open-drain drive (sink current only)
0= Port pin operates as standard push-pull drive (source and sink current)
REGISTER 13-8: SLRCONA: PORTA SLEW RATE CONTROL REGISTER
R/W-1/1
SLRA7
R/W-1/1
SLRA6
R/W-1/1
SLRA5
R/W-1/1
SLRA4
R/W-1/1
SLRA3
R/W-1/1
SLRA2
R/W-1/1
SLRA1
R/W-1/1
SLRA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
SLRA<7:0>: PORTA Slew Rate Enable bits
For RA<7:0> pins, respectively
1= Port pin slew rate is limited
0= Port pin slews at maximum rate
REGISTER 13-9: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER
R/W-0/0
INLVLA7
R/W-0/0
INLVLA6
R/W-0/0
INLVLA5
R/W-0/0
INLVLA4
R/W-0/0
INLVLA3
R/W-0/0
INLVLA2
R/W-0/0
INLVLA1
R/W-0/0
INLVLA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
INLVLA<7:0>: PORTA Input Level Select bits
For RA<7:0> pins, respectively
1= ST input used for PORT reads and interrupt-on-change
0= TTL input used for PORT reads and interrupt-on-change
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TABLE 13-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
ANSA7
INLVLA7
LATA7
—
ANSA5
INLVLA5
LATA5
ANSA4
INLVLA4
LATA4
ANSA3
INLVLA3
LATA3
ODA3
ANSA2
INLVLA2
LATA2
ANSA1
INLVLA1
LATA1
ANSA0
INLVLA0
LATA0
115
116
114
116
174
114
116
114
115
INLVLA
INLVLA6
LATA6
ODA6
LATA
ODCONA
OPTION_REG
PORTA
ODA7
ODA5
ODA4
ODA2
ODA1
ODA0
WPUEN
RA7
INTEDG
RA6
TMR0CS
RA5
TMR0SE
RA4
PSA
PS<2:0>
RA1
RA3
RA2
RA0
SLRCONA
TRISA
SLRA7
TRISA7
WPUA7
SLRA6
TRISA6
WPUA6
SLRA5
TRISA5
WPUA5
SLRA4
TRISA4
WPUA4
SLRA3
TRISA3
WPUA3
SLRA2
TRISA2
WPUA2
SLRA1
TRISA1
WPUA1
SLRA0
TRISA0
WPUA0
WPUA
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 13-4: SUMMARY OF CONFIGURATION WORD WITH PORTA
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0>
FOSC<2:0>
CPD
CONFIG1
40
CP
MCLRE
WDTE<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
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13.5.4
INPUT THRESHOLD CONTROL
13.5 PORTB Registers
The INLVLB register (Register 13-17) controls the input
voltage threshold for each of the available PORTB
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTB register and also the level
at which an interrupt-on-change occurs, if that feature
is enabled. See Section TABLE 30-1: “Supply Volt-
age” for more information on threshold levels.
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 13-11). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 13-1 shows how to initialize an I/O port.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a tran-
sition associated with an input pin, regard-
less of the actual voltage level on that pin.
Reading the PORTB register (Register 13-10) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATB).
13.5.1
DIRECTION CONTROL
13.5.5
ANALOG CONTROL
The TRISB register (Register 13-11) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog inputs
always read ‘0’.
The ANSELB register (Register 13-13) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELB set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when
executing read-modify-write instructions on the affected
port.
13.5.2
OPEN DRAIN CONTROL
The ODCONB register (Register 13-15) controls the
open-drain feature of the port. Open drain operation is
independently selected for each pin. When an
ODCONB bit is set, the corresponding port output
becomes an open drain driver capable of sinking
current only. When an ODCONB bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
Note:
The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
13.5.3
SLEW RATE CONTROL
The SLRCONB register (Register 13-16) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONB bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONB bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
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13.5.6
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 13-5.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
TABLE 13-5: PORTB OUTPUT PRIORITY
Pin Name
Function Priority(1)
RB0
CCP1
RB0
RB1
RB2
RB3
OPA2OUT
RB1
CLKR
RB2
CCP2
RB3
RB4
RB5
RB4
SDO
C3OUT
RB5
RB6
RB7
ICSPCLK
SDA
TX/CK
RB6
ICSPDAT
DACOUT2
SCL/SCK
DT
RB7
Note 1: Priority listed from highest to lowest.
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13.6 Register Definitions: PORTB
REGISTER 13-10: PORTB: PORTB REGISTER
R/W-x/u
RB7
R/W-x/u
RB6
R/W-x/u
RB5
R/W-x/u
RB4
R/W-x/u
RB3
R/W-x/u
RB2
R/W-x/u
RB1
R/W-x/u
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RB<7:0>: PORTB General Purpose I/O Pin bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of
actual I/O pin values.
REGISTER 13-11: TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
TRISB7
R/W-1/1
TRISB6
R/W-1/1
TRISB5
R/W-1/1
TRISB4
R/W-1/1
TRISB3
R/W-1/1
TRISB2
R/W-1/1
TRISB1
R/W-1/1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISB<7:0>: PORTB Tri-State Control bits
1= PORTB pin configured as an input (tri-stated)
0= PORTB pin configured as an output
REGISTER 13-12: LATB: PORTB DATA LATCH REGISTER
R/W-x/u
LATB7
R/W-x/u
LATB6
R/W-x/u
LATB5
R/W-x/u
LATB4
R/W-x/u
LATB3
R/W-x/u
LATB2
R/W-x/u
LATB1
R/W-x/u
LATB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATB<7:0>: PORTB Output Latch Value bits(1)
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
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REGISTER 13-13: ANSELB: PORTB ANALOG SELECT REGISTER
U-0
—
U-0
—
R/W-1/1
ANSB5
R/W-1/1
ANSB4
R/W-1/1
ANSB3
R/W-1/1
ANSB2
R/W-1/1
ANSB1
R/W-1/1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 13-14: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
WPUB7
R/W-1/1
WPUB6
R/W-1/1
WPUB5
R/W-1/1
WPUB4
R/W-1/1
WPUB3
R/W-1/1
WPUB2
R/W-1/1
WPUB1
R/W-1/1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
WPUB<7:0>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
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PIC16(L)F1782/3
REGISTER 13-15: ODCONB: PORTB OPEN DRAIN CONTROL REGISTER
R/W-0/0
ODB7
R/W-0/0
ODB6
R/W-0/0
ODB5
R/W-0/0
ODB4
R/W-0/0
ODB3
R/W-0/0
ODB2
R/W-0/0
ODB1
R/W-0/0
ODB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ODB<7:0>: PORTB Open Drain Enable bits
For RB<7:0> pins, respectively
1= Port pin operates as open-drain drive (sink current only)
0= Port pin operates as standard push-pull drive (source and sink current)
REGISTER 13-16: SLRCONB: PORTB SLEW RATE CONTROL REGISTER
R/W-1/1
SLRB7
R/W-1/1
SLRB6
R/W-1/1
SLRB5
R/W-1/1
SLRB4
R/W-1/1
SLRB3
R/W-1/1
SLRB2
R/W-1/1
SLRB1
R/W-1/1
SLRB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
SLRB<7:0>: PORTB Slew Rate Enable bits
For RB<7:0> pins, respectively
1= Port pin slew rate is limited
0= Port pin slews at maximum rate
REGISTER 13-17: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER
R/W-0/0
INLVLB7
R/W-0/0
INLVLB6
R/W-0/0
INLVLB5
R/W-0/0
INLVLB4
R/W-0/0
INLVLB3
R/W-0/0
INLVLB2
R/W-0/0
INLVLB1
R/W-0/0
INLVLB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
INLVLB<7:0>: PORTB Input Level Select bits
For RB<7:0> pins, respectively
1= ST input used for PORT reads and interrupt-on-change
0= TTL input used for PORT reads and interrupt-on-change
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2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 13-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELB
INLVLB
LATB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
121
122
120
122
120
122
120
121
INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0
LATB7
ODB7
LATB6
ODB6
LATB5
ODB5
LATB4
ODB4
LATB3
ODB3
RB3
LATB2
ODB2
RB2
LATB1
ODB1
RB1
LATB0
ODB0
RB0
ODCONB
PORTB
SLRCONB
TRISB
RB7
RB6
RB5
RB4
SLRB7
TRISB7
WPUB7
SLRB6
TRISB6
WPUB6
SLRB5
TRISB5
WPUB5
SLRB4
TRISB4
WPUB4
SLRB3
TRISB3
SLRB2
SLRB1
SLRB0
TRISB2 TRISB1 TRISB0
WPUB
WPUB3 WPUB2 WPUB1 WPUB0
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTB.
2011-2014 Microchip Technology Inc.
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PIC16(L)F1782/3
Voltage” for more information on threshold levels.
13.7 PORTC Registers
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the thresh-
old level during the time a module is active
may inadvertently generate a transition
associated with an input pin, regardless of
the actual voltage level on that pin.
13.7.1
DATA REGISTER
PORTC is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISC
(Register 13-19). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 13-1 shows how to initialize an I/O port.
13.7.6
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
Reading the PORTC register (Register 13-18) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
Each PORTC pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 13-7.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
13.7.2
DIRECTION CONTROL
The TRISC register (Register 13-19) controls the
PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
TABLE 13-7: PORTC OUTPUT PRIORITY
Pin Name
Function Priority(1)
RC0
T1OSO
PSMC1A
RC0
13.7.3
OPEN DRAIN CONTROL
The ODCONC register (Register 13-22) controls the
open-drain feature of the port. Open drain operation is
independently selected for each pin. When an
ODCONC bit is set, the corresponding port output
becomes an open drain driver capable of sinking
current only. When an ODCONC bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
RC1
RC2
RC3
PSMC1B
CCP2
RC1
PSMC1C
CCP1
RC2
PSMC1D
SCL
13.7.4
SLEW RATE CONTROL
SCK
RC3
The SLRCONC register (Register 13-23) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONC bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONC bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
RC4
RC5
RC6
RC7
PSMC1E
SDA
RC4
PSMC1F
SDO
RC5
13.7.5
INPUT THRESHOLD CONTROL
PSMC2A
TX/CK
RC6
The INLVLC register (Register 13-24) controls the input
voltage threshold for each of the available PORTC
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTC register and also the
level at which an interrupt-on-change occurs, if that
feature is enabled. See Section TABLE 30-1: “Supply
PSMC2B
DT
RC7
Note 1: Priority listed from highest to lowest.
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2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
13.8 Register Definitions: PORTC
REGISTER 13-18: PORTC: PORTC REGISTER
R/W-x/u
RC7
R/W-x/u
RC6
R/W-x/u
RC5
R/W-x/u
RC4
R/W-x/u
RC3
R/W-x/u
RC2
R/W-x/u
RC1
R/W-x/u
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RC<7:0>: PORTC General Purpose I/O Pin bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
REGISTER 13-19: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
TRISC7
R/W-1/1
TRISC6
R/W-1/1
TRISC5
R/W-1/1
TRISC4
R/W-1/1
TRISC3
R/W-1/1
TRISC2
R/W-1/1
TRISC1
R/W-1/1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISC<7:0>: PORTC Tri-State Control bits
1= PORTC pin configured as an input (tri-stated)
0= PORTC pin configured as an output
REGISTER 13-20: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
LATC7
R/W-x/u
LATC6
R/W-x/u
LATC5
R/W-x/u
LATC4
R/W-x/u
LATC3
R/W-x/u
LATC2
R/W-x/u
LATC1
R/W-x/u
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATC<7:0>: PORTC Output Latch Value bits(1)
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
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REGISTER 13-21: WPUC: WEAK PULL-UP PORTC REGISTER
R/W-1/1
WPUC7
R/W-1/1
WPUC6
R/W-1/1
WPUC5
R/W-1/1
WPUC4
R/W-1/1
WPUC3
R/W-1/1
WPUC2
R/W-1/1
WPUC1
R/W-1/1
WPUC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
WPUC<7:0>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
REGISTER 13-22: ODCONC: PORTC OPEN DRAIN CONTROL REGISTER
R/W-0/0
ODC7
R/W-0/0
ODC6
R/W-0/0
ODC5
R/W-0/0
ODC4
R/W-0/0
ODC3
R/W-0/0
ODC2
R/W-0/0
ODC1
R/W-0/0
ODC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ODC<7:0>: PORTC Open Drain Enable bits
For RC<7:0> pins, respectively
1= Port pin operates as open-drain drive (sink current only)
0= Port pin operates as standard push-pull drive (source and sink current)
REGISTER 13-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER
R/W-1/1
SLRC7
R/W-1/1
SLRC6
R/W-1/1
SLRC5
R/W-1/1
SLRC4
R/W-1/1
SLRC3
R/W-1/1
SLRC2
R/W-1/1
SLRC1
R/W-1/1
SLRC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
SLRC<7:0>: PORTC Slew Rate Enable bits
For RC<7:0> pins, respectively
1= Port pin slew rate is limited
0= Port pin slews at maximum rate
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PIC16(L)F1782/3
REGISTER 13-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER
R/W-1/1
INLVLC7
R/W-1/1
INLVLC6
R/W-1/1
INLVLC5
R/W-1/1
INLVLC4
R/W-1/1
INLVLC3
R/W-1/1
INLVLC2
R/W-1/1
INLVLC1
R/W-1/1
INLVLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
INLVLC<7:0>: PORTC Input Level Select bits
For RC<7:0> pins, respectively
1= ST input used for PORT reads and interrupt-on-change
0= TTL input used for PORT reads and interrupt-on-change
TABLE 13-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LATC
LATC7
RC7
LATC6
RC6
LATC5
RC5
LATC4
RC4
LATC3
RC3
LATC2
RC2
LATC1
RC1
LATC0
RC0
125
125
125
126
127
125
126
125
126
PORTC
TRISC
TRISC7
TRISC6
TRISC5
WPUC5
TRISC4
TRISC3 TRISC2 TRISC1 TRISC0
WPUC
WPUC7 WPUC6
WPUC4 WPUC3 WPUC2 WPUC1 WPUC0
INLVLC
LATC
INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
LATC7
ODC7
RC7
LATC6
ODC6
RC6
LATC5
ODC5
RC5
LATC4
ODC4
RC4
LATC3
ODC3
RC3
LATC2
ODC2
RC2
LATC1
ODC1
RC1
LATC0
ODC0
RC0
ODCONC
PORTC
SLRCONC
Legend:
SLRC7
SLRC6
SLRC5
SLRC4
SLRC3
SLRC2
SLRC1
SLRC0
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTC.
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PIC16(L)F1782/3
13.9 PORTE Registers
RE3 is input only, and also functions as MCLR. The
MCLR feature can be disabled via a configuration fuse.
RE3 also supplies the programming voltage. The TRIS bit
for RE3 (TRISE3) always reads ‘1’.
13.9.1
INPUT THRESHOLD CONTROL
The INLVLE register (Register 13-28) controls the input
voltage threshold for each of the available PORTE
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTE register and also the level
at which an interrupt-on-change occurs, if that feature
is enabled. See Section TABLE 30-1: “Supply Volt-
age” for more information on threshold levels.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate
a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
13.9.2
PORTE FUNCTIONS AND OUTPUT
PRIORITIES
No output priorities. RE3 is an input-only pin.
DS40001579E-page 128
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
13.10 Register Definitions: PORTE
REGISTER 13-25: PORTE: PORTE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-x/u
RE3
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’
RE3: PORTE Input Pin bit
1= Port pin is > VIH
0= Port pin is < VIL
bit 2-0
Unimplemented: Read as ‘0’
REGISTER 13-26: TRISE: PORTE TRI-STATE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-1(1)
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘1’
Unimplemented: Read as ‘0’
bit 2-0
Note 1: Unimplemented, read as ‘1’.
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PIC16(L)F1782/3
REGISTER 13-27: WPUE: WEAK PULL-UP PORTE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1/1
WPUE3
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’
WPUE3: Weak Pull-up Register bit
1= Pull-up enabled
0= Pull-up disabled
bit 2-0
Unimplemented: Read as ‘0’
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
REGISTER 13-28: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1/1
INLVLE3
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’
INLVLE3: PORTE Input Level Select bit(1)
1= ST input used for PORT reads and interrupt-on-change
0= TTL input used for PORT reads and interrupt-on-change
bit 2-0
Unimplemented: Read as ‘0’
TABLE 13-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON0
INLVLE
PORTE
TRISE
ADRMD
CHS<4:0>
GO/DONE
ADON
—
147
130
129
129
130
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INLVLE3
RE3
—
—
—
—
—
—
—
—
—
(1)
—
—
WPUE
WPUE3
—
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Unimplemented, read as ‘1’.
2: PIC16(L)F1783 only
DS40001579E-page 130
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
14.3 Interrupt Flags
14.0 INTERRUPT-ON-CHANGE
The bits located in the IOCxF registers are status flags
that correspond to the Interrupt-on-change pins of each
port. If an expected edge is detected on an appropriately
enabled pin, then the status flag for that pin will be set,
and an interrupt will be generated if the IOCIE bit is set.
The IOCIF bit of the INTCON register reflects the status
of all IOCxF bits.
All pins on all ports can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual pin, or combination
of pins, can be configured to generate an interrupt. The
interrupt-on-change module has the following features:
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
14.4 Clearing Interrupt Flags
• Rising and falling edge detection
• Individual pin interrupt flags
The individual status flags, (IOCxF register bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 14-1 is a block diagram of the IOC module.
14.1 Enabling the Module
To allow individual pins to generate an interrupt, the
IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 14-1:
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
14.2 Individual Pin Configuration
For each pin, a rising edge detector and a falling edge
detector are present. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register is set. To
enable a pin to detect a falling edge, the associated bit
of the IOCxN register is set.
MOVLW 0xff
XORWF IOCAF, W
ANDWF IOCAF, F
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in
both of the IOCxP and IOCxN registers.
14.5 Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the affected
IOCxF register will be updated prior to the first
instruction executed out of Sleep.
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PIC16(L)F1782/3
FIGURE 14-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
Q4Q1
IOCBNx
D
Q
CK
edge
detect
R
RBx
data bus =
0 or 1
S
to data bus
IOCBFx
IOCBPx
D
Q
D
Q
write IOCBFx
CK
CK
IOCIE
R
Q2
from all other
IOCBFx individual
pin detectors
IOC interrupt
to CPU core
Q1
Q1
Q1
Q2
Q3
Q2
Q2
Q3
Q3
Q4
Q4
Q4Q1
Q4
Q4
Q4Q1
Q4Q1
Q4Q1
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PIC16(L)F1782/3
14.6 Register Definitions: Interrupt-on-Change Control
REGISTER 14-1: IOCxP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER
R/W-0/0
IOCxP7
R/W-0/0
IOCxP6
R/W-0/0
IOCxP5
R/W-0/0
IOCxP4
R/W-0/0
IOCxP3
R/W-0/0
IOCxP2
R/W-0/0
IOCxP1
R/W-0/0
IOCxP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
IOCxP<7:0>: Interrupt-on-Change Positive Edge Enable bits(1)
1= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
Note 1: For IOCEP register, bit 3 (IOCEP3) is the only implemented bit in the register.
REGISTER 14-2: IOCxN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER
R/W-0/0
IOCxN7
R/W-0/0
IOCxN6
R/W-0/0
IOCxN5
R/W-0/0
IOCxN4
R/W-0/0
IOCxN3
R/W-0/0
IOCxN2
R/W-0/0
IOCxN1
R/W-0/0
IOCxN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
IOCxN<7:0>: Interrupt-on-Change Negative Edge Enable bits(1)
1= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
Note 1: For IOCEN register, bit 3 (IOCEN3) is the only implemented bit in the register.
2011-2014 Microchip Technology Inc.
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PIC16(L)F1782/3
REGISTER 14-3: IOCxF: INTERRUPT-ON-CHANGE FLAG REGISTER
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCxF7
bit 7
IOCxF6
IOCxF5
IOCxF4
IOCxF3
IOCxF2
IOCxF1
IOCxF0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
bit 7-0
IOCxF<7:0>: Interrupt-on-Change Flag bits(1)
1= An enabled change was detected on the associated pin.
Set when IOCxPx = 1and a rising edge was detected RBx, or when IOCxNx = 1and a falling edge
was detected on RBx.
0= No change was detected, or the user cleared the detected change.
Note 1: For IOCEF register, bit 3 (IOCEF3) is the only implemented bit in the register.
TABLE 14-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELB
INTCON
IOCAF
IOCAN
IOCAP
IOCBF
IOCBN
IOCBP
IOCCF
IOCCN
IOCCP
IOCEF
IOCEN
IOCEP
—
—
ANSB5
ANSB4
INTE
ANSB3
IOCIE
ANSB2
ANSB1
INTF
ANSB0
IOCIF
121
79
GIE
PEIE
TMR0IE
TMR0IF
IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
134
133
133
134
133
133
134
133
133
134
133
133
120
—
—
—
—
—
—
—
—
—
—
—
—
IOCEF3
IOCEN3
IOCEP3
—
—
—
—
—
—
—
—
—
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISB
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
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PIC16(L)F1782/3
15.1 Independent Gain Amplifiers
15.0 FIXED VOLTAGE REFERENCE
(FVR)
The output of the FVR supplied to the ADC,
Comparators, and DAC is routed through two
independent programmable gain amplifiers. Each
amplifier can be programmed for a gain of 1x, 2x or 4x,
to produce the three possible voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The ADFVR<1:0> bits of the FVRCON register are used
to enable and configure the gain amplifier settings for
the reference supplied to the ADC module. Reference
Section 17.0 “Analog-to-Digital Converter (ADC)
Module” for additional information.
• ADC input channel
• ADC positive reference
• Comparator positive input
• Digital-to-Analog Converter (DAC)
The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the DAC and comparator
module. Reference Section 19.0 “Digital-to-Analog
Converter (DAC) Module” and Section 20.0
“Comparator Module” for additional information.
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
15.2 FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 30.0 “Electrical Specifications” for the
minimum delay requirement.
15.3 FVR Buffer Stabilization Period
When either FVR Buffer1 or FVR Buffer 2 is enabled,
the buffer amplifier circuits require 30 s to stabilize.
This stabilization time is required even when the FVR
is already operating and stable.
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PIC16(L)F1782/3
FIGURE 15-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
X1
X2
X4
FVR BUFFER1
(To ADC Module)
CDAFVR<1:0>
2
X1
X2
X4
FVR BUFFER2
(To Comparators, DAC)
HFINTOSC Enable
HFINTOSC
To BOR, LDO
+
_
FVREN
FVRRDY
Any peripheral requiring the
Fixed Reference
(See Table 15-1)
TABLE 15-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral
Conditions
Description
HFINTOSC
FOSC<2:0> = 100and
IRCF<3:0> 000x
INTOSC is active and device is not in Sleep
BOREN<1:0> = 11
BOR always enabled
BOR
LDO
BOREN<1:0> = 10and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN<1:0> = 01and BORFS = 1 BOR under software control, BOR Fast Start enabled
All PIC16F1782/3 devices, when
The device runs off of the ULP regulator when in Sleep mode.
VREGPM = 1and not in Sleep
PSMC 64 MHz PxSRC<1:0>
64 MHz clock forces HFINTOSC on during Sleep.
DS40001579E-page 136
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PIC16(L)F1782/3
15.4 Register Definitions: FVR Control
REGISTER 15-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
FVREN
R-q/q
FVRRDY(1)
R/W-0/0
TSEN
R/W-0/0
TSRNG
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CDAFVR<1:0>
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
bit 3-2
FVREN: Fixed Voltage Reference Enable bit
1= Fixed Voltage Reference is enabled
0= Fixed Voltage Reference is disabled
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1= Fixed Voltage Reference output is ready for use
0= Fixed Voltage Reference output is not ready or not enabled
TSEN: Temperature Indicator Enable bit(3)
1= Temperature Indicator is enabled
0= Temperature Indicator is disabled
TSRNG: Temperature Indicator Range Selection bit(3)
1= VOUT = VDD - 4VT (High Range)
0= VOUT = VDD - 2VT (Low Range)
CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit
11= Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10= Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01= Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00= Comparator and DAC Fixed Voltage Reference Peripheral output is off.
bit 1-0
ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit
11= ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00= ADC Fixed Voltage Reference Peripheral output is off.
Note 1: FVRRDY is always ‘1’ on “F” devices only.
2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 16.0 “Temperature Indicator Module” for additional information.
TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
137
Legend:
Shaded cells are not used with the Fixed Voltage Reference.
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PIC16(L)F1782/3
FIGURE 16-1:
TEMPERATURE CIRCUIT
DIAGRAM
16.0 TEMPERATURE INDICATOR
MODULE
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
VDD
TSEN
TSRNG
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
VOUT
To ADC
16.1 Circuit Operation
16.2 Minimum Operating VDD
Figure 16-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
Equation 16-1 describes the output characteristics of
the temperature indicator.
EQUATION 16-1: VOUT RANGES
Table 16-1 shows the recommended minimum VDD vs.
range setting.
High Range: VOUT = VDD - 4VT
Low Range: VOUT = VDD - 2VT
TABLE 16-1: RECOMMENDED VDD VS.
RANGE
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 15.0 “Fixed Voltage Reference (FVR)” for
more information.
3.6V
1.8V
16.3 Temperature Output
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 17.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
16.4 ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low-
voltage operation.
DS40001579E-page 138
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PIC16(L)F1782/3
TABLE 16-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
ADFVR<1:0>
136
Legend:
Shaded cells are unused by the temperature indicator module.
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PIC16(L)F1782/3
the conversion result into the ADC result registers
(ADRESH:ADRESL register pair). Figure 17-1 shows
the block diagram of the ADC.
17.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of a single-ended and differential analog
input signals to a 12-bit binary representation of that
signal. This device uses analog inputs, which are
multiplexed into a single sample and hold circuit. The
output of the sample and hold is connected to the input
of the converter. The converter generates a 12-bit
binary result via successive approximation and stores
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 17-1:
ADC BLOCK DIAGRAM
ADPREF = 11
VDD
ADPREF = 00
ADPREF = 01
VREF+
AN0
AN1
00000
00001
00010
00011
00100
00101
VREF-/AN2
VREF+/AN3
AN4
ADNREF = 1
ADPNEF = 0
Reserved
Reserved
Reserved
AN8
00110
00111
01000
01001
01010
01011
01100
01101
10
Ref+ Ref-
1
+
-
ADC
12
AN9
0
GO/DONE
12
AN10
ADRMD
AN11
0= Sign Magnitude
1= 2’s Complement
AN12
ADFM
ADON(1)
AN13
16
VSS
ADRESH ADRESL
11101
11110
11111
Temperature Indicator
DAC_output
FVR Buffer1
CHS<4:0>(2)
CHSN<3:0>
Note 1: When ADON = 0, all multiplexer inputs are disconnected.
2: See ADCON0 register (Register 17-1) and ADCON2 register (Register 17-3) for detailed
analog channel selection per device.
DS40001579E-page 140
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
17.1.3
ADC VOLTAGE REFERENCE
17.1 ADC Configuration
The ADPREF bits of the ADCON1 register provide
control of the positive voltage reference. The positive
voltage reference can be:
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
- Single-ended
• VREF+
• VDD
• FVR Buffer1
- Differential
The ADNREF bits of the ADCON1 register provide
control of the negative voltage reference. The negative
voltage reference can be:
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• VREF- pin
• VSS
• Result formatting
17.1.1
PORT CONFIGURATION
See Section 15.0 “Fixed Voltage Reference (FVR)”
for more details on the Fixed Voltage Reference.
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 13.0 “I/O Ports” for more information.
17.1.4
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
• FOSC/2
• FOSC/4
• FOSC/8
17.1.2
CHANNEL SELECTION
• FOSC/16
There are up to 14 channel selections available:
• FOSC/32
• AN<13:8, 4:0> pins
• FOSC/64
• Temperature Indicator
• DAC_output
• FRC (dedicated internal FRC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 12-bit conversion requires 15 TAD periods
as shown in Figure 17-2.
• FVR (Fixed Voltage Reference) Output
Refer to Section 15.0 “Fixed Voltage Reference
(FVR)” and Section 16.0 “Temperature Indicator
Module” for more information on these channel
selections.
For correct conversion, the appropriate TAD specification
must be met. Refer to the ADC conversion requirements
in Section 30.0 “Electrical Specifications” for more
information. Table 17-1 gives examples of appropriate
ADC clock selections.
When converting differential signals, the negative input
for the channel is selected with the CHSN<3:0> bits of
the ADCON2 register. Any positive input can be paired
with any negative input to determine the differential
channel.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
The CHS<4:0> bits of the ADCON0 register determine
which positive channel is selected.
When CHSN<3:0> = 1111then the ADC is effectively
a single ended ADC converter.
When changing channels, a delay is required before
starting the next conversion.
2011-2014 Microchip Technology Inc.
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PIC16(L)F1782/3
TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
ADCS<2:0>
Clock Source
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC
000
100
001
101
010
110
x11
62.5ns(2)
125 ns(2)
0.5 s(2)
800 ns
100 ns(2)
200 ns(2)
400 ns(2)
800 ns
125 ns(2)
250 ns(2)
0.5 s(2)
1.0 s
250 ns(2)
500 ns(2)
1.0 s
500 ns(2)
1.0 s
2.0 s
4.0 s
8.0 s(3)
16.0 s(3)
32.0 s(3)
64.0 s(3)
2.0 s
2.0 s
4.0 s
1.0 s
1.6 s
2.0 s
4.0 s
8.0 s(3)
8.0 s(3)
16.0 s(3)
2.0 s
3.2 s
4.0 s
1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend:
Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 17-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD
TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD14 TAD15 TAD16 TAD17
b1 b0
TAD1 TAD2 TAD3 TAD4 TAD5
sign
b6
b3
b2
b11
b10
b9
b8
b7
b5
b4
Conversion
starts
Holding cap.
discharge
Holding cap disconnected
from input
Set GO
bit
Input
Sample
On the following cycle:
GO bit is cleared, ADIF bit is set,
holding capacitor is connected to analog input.
DS40001579E-page 142
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PIC16(L)F1782/3
17.1.5
INTERRUPTS
17.1.6
RESULT FORMATTING
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
The 10-bit and 12-bit ADC conversion results can be
supplied in two formats: 2’s complement or
sign-magnitude. The ADFM bit of the ADCON1 register
controls the output format. Sign magnitude is left
justified with the sign bit in the LSb position. Negative
numbers are indicated when the sign bit is '1'.
Two's complement is right justified with the sign
extended into the most significant bits.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
Figure 17-3 shows the two output formats. Table 17-2
shows conversion examples.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the GIE and PEIE bits of the INTCON
register must be disabled. If the GIE and PEIE bits of
the INTCON register are enabled, execution will switch
to the Interrupt Service Routine.
FIGURE 17-3:
ADC CONVERSION RESULT FORMAT
12-bit sign and magnitude
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
bit 7 bit 0
Bit 3 Bit 2 Bit 1 Bit 0 ‘0’
‘0’
‘0’ Sign
ADFM = 0
bit 7
bit 0
ADRMD = 0
12-bit ADC Result
Loaded with ‘0’
12-bit 2’s compliment
Bit 12 Bit 12 Bit 12 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
bit 7 bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADFM = 1
bit 7
bit 0
ADRMD = 0
Loaded with Sign bits’
12-bit ADC Result
10-bit sign and magnitude
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
bit 7 bit 0
Bit 1 Bit 0 ‘0’
‘0’
‘0’
‘0’
‘0’ Sign
ADFM = 0
bit 7
bit 0
ADRMD = 1
10-bit ADC Result
Loaded with ‘0’
10-bit 2’s compliment
Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 9 Bit 8
bit 7 bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADFM = 1
bit 7
bit 0
ADRMD = 1
Loaded with Sign bits’
10-bit ADC Result
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PIC16(L)F1782/3
TABLE 17-2: ADC OUTPUT RESULTS FORMAT
Sign and Magnitude Result
2’s Compliment Result
ADFM = 0, ADRMD = 0
ADFM = 1, ADRMD = 0
Absolute ADC Value
(decimal)
ADRESH
ADRESL
ADRESH
ADRESL
(ADRES<15:8>)
(ADRES<7:0>)
(ADRES<15:8>)
(ADRES<7:0>)
+ 4095
+ 2355
+ 0001
0000
1111 1111
1001 0011
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
1111 0000
0011 0000
0001 0000
0000 0000
0001 0001
1111 0001
0000 0001
0000 1111
0000 1001
0000 0000
0000 0000
1111 1111
1111 0000
1111 0000
1111 1111
0011 0011
0000 0001
0000 0000
1111 1111
0000 0001
0000 0000
- 0001
- 4095
- 4096
Note 1: For the RSD ADC, the raw 13-bits from the ADC is presented in 2’s compliment format, so no data
translation is required for 2’s compliment results.
2: For the SAR ADC, the raw 13-bits from the ADC is presented in sign and magnitude format, so no data
translation is required for sign and magnitude results
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17.2.4
ADC OPERATION DURING SLEEP
17.2 ADC Operation
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC oscillator source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
17.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the
GO/DONE bit of the ADCON0 register to a ‘1’ will clear
the ADRESH and ADRESL registers and start the
Analog-to-Digital conversion.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 17.2.6 “A/D Conversion
Procedure”.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
17.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
17.2.5
AUTO-CONVERSION TRIGGER
• Set the ADIF Interrupt Flag bit
The Auto-conversion Trigger allows periodic ADC mea-
surements without software intervention. When a rising
edge of the selected source occurs, the GO/DONE bit
is set by hardware.
17.2.3
TERMINATING A CONVERSION
When a conversion is terminated before completion by
clearing the GO/DONE bit then the partial results are
discarded and the results in the ADRESH and ADRESL
registers from the previous conversion remain
unchanged.
The Auto-conversion Trigger source is selected with
the TRIGSEL<3:0> bits of the ADCON2 register.
Using the Auto-conversion Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
Auto-conversion sources are:
• CCP1
• CCP2
• PSMC1(1)
• PSMC2(1)
Note:
The PSMC clock frequency, after the
prescaler, must be less than FOSC/4 to
ensure that the ADC detects the
auto-conversion trigger. This limitation can
be overcome by synchronizing a slave
PSMC, running at the required slower
clock frequency, to the first PSMC and
triggering the conversion from the slave
PSMC.
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17.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 17-1:
A/D CONVERSION
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
;This code block configures the ADC
;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
1. Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
;Conversion start & polling for completion
; are included.
;
• Configure pin as analog (Refer to the ANSEL
register)
BANKSEL
MOVLW
ADCON1
;
B’11110000’ ;2’s complement, Frc
;clock
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
MOVWF
MOVLW
MOVWF
ADCON1
;Vdd and Vss Vref
B’00001111’ ;set negative input
ADCON2
;to negative
;reference
BANKSEL
BSF
BANKSEL
BSF
BANKSEL
MOVLW
MOVWF
CALL
TRISA
TRISA,0
ANSEL
ANSEL,0
ADCON0
;
;Set RA0 to input
;
;Set RA0 to analog
;
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
B’00000001’ ;Select channel AN0
ADCON0
SampleTime
;Turn ADC On
;Acquisiton delay
4. Wait the required acquisition time(2)
.
BSF
ADCON0,ADGO ;Start conversion
5. Start conversion by setting the GO/DONE bit.
BTFSC
GOTO
BANKSEL
MOVF
ADCON0,ADGO ;Is conversion done?
$-1
;No, test again
;
6. Wait for ADC conversion to complete by one of
the following:
ADRESH
ADRESH,W
RESULTHI
;Read upper 2 bits
;store in GPR space
• Polling the GO/DONE bit
MOVWF
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer
to
Section 17.4
“ADC
Acquisition Requirements”.
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17.3 Register Definitions: ADC Control
REGISTER 17-1: ADCON0: ADC CONTROL REGISTER 0
R/W-0/0
ADRMD
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADON
CHS<4:0>
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
ADRMD: ADC Result Mode bit
1= ADRESL and ADRESH provide data formatted for a 10-bit result
0= ADRESL and ADRESH provide data formatted for a 12-bit result
See Figure 17-3 for details
bit 6-2
CHS<4:0>: Positive Differential Input Channel Select bits
11111= FVR (Fixed Voltage Reference) Buffer 1 Output(3)
11110= DAC_output(2)
11101= Temperature Indicator(4)
11100= Reserved. No channel connected.
•
•
•
01110= Reserved. No channel connected.
01101= AN13
01100= AN12
01011= AN11
01010= AN10
01001= AN9
01000= AN8
00111= Reserved. No channel connected.
00110= Reserved. No channel connected.
00101= Reserved. No channel connected.
00100= AN4
00011= AN3
00010= AN2
00001= AN1
00000= AN0
bit 1
bit 0
GO/DONE: ADC Conversion Status bit
1= ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0= ADC conversion completed/not in progress
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: See Section 19.0 “Digital-to-Analog Converter (DAC) Module” for more information.
2: See Section 15.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 16.0 “Temperature Indicator Module” for more information.
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REGISTER 17-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
ADCS<2:0>
ADNREF
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
ADFM: ADC Result Format Select bit (see Figure 17-3)
1= 2’s complement format.
0= Sign-magnitude result format.
bit 6-4
ADCS<2:0>: ADC Conversion Clock Select bits
111=FRC (clock supplied from a dedicated FRC oscillator)
110=FOSC/64
101=FOSC/16
100=FOSC/4
011=FRC (clock supplied from a dedicated FRC oscillator)
010=FOSC/32
001=FOSC/8
000=FOSC/2
bit 3
bit 2
Unimplemented: Read as ‘0’
ADNREF: ADC Negative Voltage Reference Configuration bit
1= VREF- is connected to external VREF- pin(1)
0= VREF- is connected to VSS
bit 1-0
ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
11= VREF+ is connected internally to FVR Buffer 1
10= Reserved
01= VREF+ is connected to VREF+ pin
00= VREF+ is connected to VDD
Note 1: When selecting the FVR or VREF+ pin as the source of the positive reference, be aware that a minimum
voltage specification exists. See Section 30.0 “Electrical Specifications” for details.
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REGISTER 17-3: ADCON2: ADC CONTROL REGISTER 2
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TRIGSEL<3:0>
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
CHSN<3:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
TRIGSEL<3:0>: ADC Auto-conversion Trigger Source Selection bits
1111= Reserved. Auto-conversion Trigger disabled.
1110= Reserved. Auto-conversion Trigger disabled.
1101= Reserved. Auto-conversion Trigger disabled.
1100= Reserved. Auto-conversion Trigger disabled.
1011= Reserved. Auto-conversion Trigger disabled.
1010= Reserved. Auto-conversion Trigger disabled.
1001= PSMC2 Falling Edge Event
1000= PSMC2 Rising Edge Event
0111= PSMC2 Period Match Event
0110= PSMC1 Falling Edge Event
0101= PSMC1 Rising Edge Event
0100= PSMC1 Period Match Event
0011= Reserved. Auto-conversion Trigger disabled.
0010= CCP2, Auto-conversion Trigger
0001= CCP1, Auto-conversion Trigger
0000= Disabled
bit 3-0
CHSN<3:0>: Negative Differential Input Channel Select bits
When ADON = 0, all multiplexer inputs are disconnected.
1111= ADC Negative reference - selected by ADNREF
1110= Reserved. No channel connected.
1101= AN13
1100= AN12
1011= AN11
1010= AN10
1001= AN9
1000= AN8
0111= Reserved. No channel connected.
0110= Reserved. No channel connected.
0101= Reserved. No channel connected.
0100= AN4
0011= AN3
0010= AN2
0001= AN1
0000= AN0
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REGISTER 17-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
AD<11:4>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
AD<11:4>: ADC Result Register bits
Upper 8 bits of 12-bit conversion result
REGISTER 17-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
ADSIGN
AD<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
AD<3:0>: ADC Result Register bits
Lower 4 bits of 12-bit conversion result
bit 3-1
bit 0
Extended LSb bits: These are cleared to zero by DC conversion.
ADSIGN: ADC Result Sign bit
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REGISTER 17-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADSIGN AD<11:8>
R/W-x/u
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
bit 3-0
ADSIGN: Extended AD Result Sign bit
AD<11:8>: ADC Result Register bits
Most Significant 4 bits of 12-bit conversion result
REGISTER 17-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
AD<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
AD<7:0>: ADC Result Register bits
Least Significant 8 bits of 12-bit conversion result
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source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an ADC acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 17-1 may be
used. This equation assumes that 1/2 LSb error is used
(4,096 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
17.4 ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 17-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 17-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 17-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + Temperature - 25°C0.05µs/°C
The value for TC can be approximated with the following equations:
1
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED1 – -------------------------- = VCHOLD
2n + 1 – 1
–TC
---------
RC
VAPPLIED 1 – e
= VCHOLD
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
–Tc
--------
RC
1
= VAPPLIED1 – --------------------------
2n + 1 – 1
VAPPLIED 1 – e
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –CHOLDRIC + RSS + RS ln(1/8191)
= –10pF1k + 7k + 10k ln(0.000122)
= 1.62µs
Therefore:
TACQ = 2µs + 1.62µs + 50°C- 25°C0.05µs/°C
= 4.87µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: Maximum source impedance feeding the input pin should be considered so that the pin leakage does not
cause a voltage divider, thereby limiting the absolute accuracy.
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FIGURE 17-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Sampling
Switch
VT 0.6V
SS
RIC 1k
Rss
Rs
(1)
CPIN
5 pF
VA
I LEAKAGE
CHOLD = 10 pF
VSS/VREF-
VT 0.6V
6V
5V
VDD 4V
3V
RSS
Legend:
CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 1011
Sampling Switch
RIC
RSS
SS
VT
= Interconnect Resistance
= Resistance of Sampling Switch
= Sampling Switch
(k)
= Threshold Voltage
Note 1: Refer to Section 30.0 “Electrical Specifications”.
FIGURE 17-5:
ADC TRANSFER FUNCTION
Full-Scale Range
FFFh
FFEh
FFDh
FFCh
FFBh
03h
02h
01h
00h
Analog Input Voltage (Positive input channel
relative to negative
0.5 LSB
1.5 LSB
input channel)
Zero-Scale
Transition
VREF-
Full-Scale
Transition
VREF+
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TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
147
148
149
ADCON0
ADCON1
ADCON2
ADRESH
ADRMD
ADFM
CHS<4:0>
GO/DONE
ADON
ADCS<2:0>
—
ADNREF
ADPREF<1:0>
TRIGSEL<3:0>
CHSN<3:0>
A/D Result Register High
A/D Result Register Low
150, 151
150, 151
115
ADRESL
ANSELA
ANSELB
INTCON
ANSA7
—
—
—
ANSA5
ANSB5
TMR0IE
ANSA4
ANSB4
INTE
ANSA3
ANSB3
IOCIE
ANSA2
ANSB2
TMR0IF
ANSA1
ANSB1
INTF
ANSA0
ANSB0
IOCIF
121
GIE
PEIE
79
TMR1GIE
TMR1GIF
TRISA7
TRISB7
FVREN
PIE1
ADIE
ADIF
RCIE
RCIF
TXIE
TXIF
SSP1IE
SSP1IF
TRISA3
TRISB3
CCP1IE
CCP1IF
TRISA2
TRISB2
TMR2IE
TMR2IF
TRISA1
TRISB1
TMR1IE
TMR1IF
TRISA0
TRISB0
80
PIR1
83
TRISA
TRISB
FVRCON
Legend:
TRISA6
TRISB6
FVRRDY
TRISA5
TRISB5
TSEN
TRISA4
TRISB4
TSRNG
114
120
CDAFVR<1:0>
ADFVR<1:0>
137
x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not
used for the ADC module.
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18.0 OPERATIONAL AMPLIFIER
(OPA) MODULES
The Operational Amplifier (OPA) is
a standard
three-terminal device requiring external feedback to
operate. The OPA module has the following features:
• External connections to I/O ports
• Low leakage inputs
• Factory Calibrated Input Offset Voltage
FIGURE 18-1:
OPAx MODULE BLOCK DIAGRAM
OPAXEN
OPAXSP(1)
0x
OPAxIN+
10
11
DAC_output
FVR Buffer 2
OPAXOUT
OPA
OPAxIN-
OPAxNCH<1:0>
Note 1: The OPAxSP bit must be set to ‘1’. Low Power mode is not supported.
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18.1 Effects of Reset
18.3 OPAxCON Control Register
A device Reset forces all registers to their Reset state.
This disables the OPA module.
The OPAxCON register, shown in Register 18-1,
controls the OPA module.
The OPA module is enabled by setting the OPAxEN bit
of the OPAxCON register. When enabled, the OPA
forces the output driver of OPAxOUT pin into tri-state to
prevent contention between the driver and the OPA
output.
18.2 OPA Module Performance
Common AC and DC performance specifications for
the OPA module:
• Common Mode Voltage Range
• Leakage Current
Note:
When the OPA module is enabled, the
OPAxOUT pin is driven by the op amp out-
put, not by the PORT digital driver. Refer
to the Electrical specifications for the op
amp output drive capability.
• Input Offset Voltage
• Open Loop Gain
• Gain Bandwidth Product
Common mode voltage range is the specified voltage
range for the OPA+ and OPA- inputs, for which the OPA
module will perform to within its specifications. The
OPA module is designed to operate with input voltages
between VSS and VDD. Behavior for Common mode
voltages greater than VDD, or below VSS, are not guar-
anteed.
Leakage current is a measure of the small source or
sink currents on the OPA+ and OPA- inputs. To mini-
mize the effect of leakage currents, the effective imped-
ances connected to the OPA+ and OPA- inputs should
be kept as small as possible and equal.
Input offset voltage is a measure of the voltage differ-
ence between the OPA+ and OPA- inputs in a closed
loop circuit with the OPA in its linear region. The offset
voltage will appear as a DC offset in the output equal to
the input offset voltage, multiplied by the gain of the cir-
cuit. The input offset voltage is also affected by the
Common mode voltage. The OPA is factory calibrated
to minimize the input offset voltage of the module.
Open loop gain is the ratio of the output voltage to the
differential input voltage, (OPA+) - (OPA-). The gain is
greatest at DC and falls off with frequency.
Gain Bandwidth Product or GBWP is the frequency
at which the open loop gain falls off to 0 dB.
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18.4 Register Definitions: Op Amp Control
REGISTER 18-1: OPAxCON: OPERATIONAL AMPLIFIERS (OPAx) CONTROL REGISTERS
R/W-0/0
OPAxEN
R/W-0/0
OPAxSP
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
OPAxCH<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
OPAxEN: Op Amp Enable bit
1 = Op amp is enabled
0 = Op amp is disabled and consumes no active power
OPAxSP: Op Amp Speed/Power Select bit
1 = Comparator operates in high GBWP mode
0 = Reserved. Do not use.
bit 5-2
bit 1-0
Unimplemented: Read as ‘0’
OPAxCH<1:0>: Non-inverting Channel Selection bits
11 = Non-inverting input connects to FVR Buffer 2 output
10 = Non-inverting input connects to DAC_output
0x = Non-inverting input connects to OPAxIN+ pin
TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
ANSELB
DACCON0
DACCON1
OPA1CON
OPA2CON
TRISA
ANSA7
—
—
—
—
ANSA5
ANSB5
ANSA4
ANSB4
ANSA3
ANSB3
ANSA2
ANSB2
ANSA1
ANSB1
—
ANSA0
ANSB0
115
121
161
161
157
157
114
120
125
DACEN
DACOE1
DACOE2
DACPSS<1:0>
DACNSS
DACR<7:0>
OPA1EN
OPA2EN
TRISA7
TRISB7
TRISC7
OPA1SP
OPA2SP
TRISA6
TRISB6
TRISC6
—
—
—
—
OPA1PCH<1:0>
OPA2PCH<1:0>
—
—
—
—
TRISA5
TRISB5
TRISC5
TRISA4
TRISB4
TRISC4
TRISA3
TRISB3
TRISC3
TRISA2
TRISB2
TRISC2
TRISA1
TRISA0
TRISB0
TRISC0
TRISB
TRISB1
TRISC1
TRISC
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by op amps.
Note 1: PIC16(L)F1783 only
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The Digital-to-Analog Converter (DAC) is enabled by
setting the DACEN bit of the DACCON0 register.
19.0 DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with the input source,
with 256 selectable output levels.
19.1 Output Voltage Selection
The DAC has 256 voltage level ranges. The 256 levels
are set with the DACR<7:0> bits of the DACCON1
register.
The input of the DAC can be connected to:
• External VREF pins
The DAC output voltage is determined by Equation 19-1:
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• Op amp positive input
• ADC input channel
• DACOUT1 pin
• DACOUT2 pin
EQUATION 19-1: DAC OUTPUT VOLTAGE
IF DACxEN = 1
DACxR7:0
VOUT = VSOURCE+ – VSOURCE- -------------------------------- + VSOURCE-
28
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
19.2 Ratiometric Output Level
The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Section 30.0 “Electrical
Specifications”.
19.3 DAC Voltage Reference Output
The DAC voltage can be output to the DACOUT1 and
DACOUT2 pins by setting the respective DACOE1 and
DACOE2 pins of the DACCON0 register. Selecting the
DAC reference voltage for output on either DACOUTX
pin automatically overrides the digital output buffer and
digital input threshold detector functions of that pin.
Reading the DACOUTX pin when it has been
configured for DAC reference voltage output will
always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to either DACOUTx pin.
Figure 19-2 shows an example buffering technique.
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FIGURE 19-1:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC)
FVR BUFFER2
VSOURCE+
VDD
DACxR<7:0>
8
VREF+
R
R
DACxPSS<1:0>
DACxEN
2
R
R
R
256
Steps
DAC_Output
(To Comparator and
ADC Modules)
R
R
R
DACXOUT1
DACXOE1
DACxNSS
DACXOUT2
DACXOE2
VREF-
VSS
VSOURCE-
FIGURE 19-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module
R
+
–
Buffered DAC Output
DACXOUTX
Voltage
Reference
Output
Impedance
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19.4 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
19.5 Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DACOUT pin.
• The DACR<7:0> range select bits are cleared.
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19.6 Register Definitions: DAC Control
REGISTER 19-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0
DACEN
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
DACOE1
DACOE2
DACPSS<1:0>
DACNSS
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
DACEN: DAC Enable bit
1= DAC is enabled
0= DAC is disabled
bit 6
bit 5
Unimplemented: Read as ‘0’
DACOE1: DAC Voltage Output 1 Enable bit
1= DAC voltage level is also an output on the DACOUT1 pin
0= DAC voltage level is disconnected from the DACOUT1 pin
bit 4
DACOE2: DAC Voltage Output 2 Enable bit
1= DAC voltage level is also an output on the DACOUT2 pin
0= DAC voltage level is disconnected from the DACOUT2 pin
bit 3-2
DACPSS<1:0>: DAC Positive Source Select bits
11= Reserved, do not use
10= FVR Buffer2 output
01= VREF+ pin
00= VDD
bit 1
bit 0
Unimplemented: Read as ‘0’
DACNSS: DAC Negative Source Select bits
1= VREF- pin
0= VSS
REGISTER 19-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DACR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
DACR<7:0>: DAC Voltage Output Select bits
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TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
DACCON0
DACCON1
Legend:
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DACPSS<1:0>
DACR<7:0>
— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.
ADFVR<1:0>
137
161
161
DACEN
—
DACOE1 DACOE2
—
DACNSS
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FIGURE 20-1:
SINGLE COMPARATOR
20.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
VIN+
VIN-
+
Output
–
VIN-
VIN+
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
Output
• Wake-up from Sleep
• Programmable Speed/Power optimization
• PWM shutdown
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
• Programmable and fixed voltage reference
20.1
Comparator Overview
A single comparator is shown in Figure 20-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 20-1.
TABLE 20-1: COMPARATORAVAILABILITY
PER DEVICE
Device
C1
C2
C3
PIC16(L)F1782
PIC16(L)F1783
●
●
●
●
●
●
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FIGURE 20-2:
COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
CxNCH<2:0>
CxON(1)
3
CxINTP
Interrupt
det
CXIN0-
CXIN1-
CXIN2-
CXIN3-
0
Set CxIF
1
CxINTN
Interrupt
det
2
MUX
(2)
3
CXPOL
CxVN
CxVP
Reserved
Reserved
Reserved
4
5
-
0
1
to CMXCON0 (CXOUT)
and CM2CON1 (MCXOUT)
D
Q
Cx
ZLF
+
6
Q1
EN
7
CxHYS
AGND
CxZLF
CxSP
async_CxOUT
CXSYNC
CXOE
TRIS bit
CXOUT
0
1
D
Q
0
CXIN0+
From Timer1
tmr1_clk
sync_CxOUT
To Timer1
and PSMC Logic
1
CXIN1+
MUX
(2)
2
3
Reserved
Reserved
4
5
6
7
Reserved
DAC_Output
FVR Buffer2
AGND
CxON
CXPCH<2:0>
3
Note 1: When CxON = 0, the comparator will produce a ‘0’ at the output.
2: When CxON = 0, all multiplexer inputs are disconnected.
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20.2.3
COMPARATOR OUTPUT POLARITY
20.2 Comparator Control
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Each comparator has two control registers: CMxCON0
and CMxCON1.
The CMxCON0 register (see Register 20-1) contains
Control and Status bits for the following:
• Enable
Table 20-2 shows the output state versus input
conditions, including polarity control.
• Output selection
• Output polarity
TABLE 20-2: COMPARATOR OUTPUT
STATE VS. INPUT
• Speed/Power selection
• Hysteresis enable
• Output synchronization
CONDITIONS
Input Condition
CxPOL
CxOUT
The CMxCON1 register (see Register 20-2) contains
Control bits for the following:
CxVN > CxVP
CxVN < CxVP
CxVN > CxVP
CxVN < CxVP
0
0
1
1
0
1
1
0
• Interrupt enable
• Interrupt edge polarity
• Positive input channel selection
• Negative input channel selection
20.2.4
COMPARATOR SPEED/POWER
SELECTION
20.2.1
COMPARATOR ENABLE
The trade-off between speed or power can be
optimized during program execution with the CxSP
control bit. The default state for this bit is ‘1’ which
selects the normal speed mode. Device power
consumption can be optimized at the cost of slower
comparator propagation delay by clearing the CxSP bit
to ‘0’.
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
20.2.2
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit of the CMxCON0 register
overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
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20.3 Comparator Hysteresis
20.5 Comparator Interrupt
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
See Section 30.0 “Electrical Specifications” for
more information.
20.4 Timer1 Gate Operation
To enable the interrupt, you must set the following bits:
• CxON, CxPOL and CxSP bits of the CMxCON0
register
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 22.6 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
20.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
The output from a comparator can be synchronized
with Timer1 by setting the CxSYNC bit of the CMx-
CON0 register.
Note:
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 20-2) and the Timer1 Block
Diagram (Figure 22-1) for more information.
20.6 Comparator Positive Input
Selection
Configuring the CxPCH<2:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• CxIN+ analog pin
• DAC output
• FVR (Fixed Voltage Reference)
• VSS (Ground)
See Section 15.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 19.0 “Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
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Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage
Reference Specifications in Section 30.0 “Electrical
Specifications” for more details.
20.7 Comparator Negative Input
Selection
The CxNCH<2:0> bits of the CMxCON0 register direct
an analog input pin or analog ground to the inverting
input of the comparator:
20.9 Zero Latency Filter
• CxIN- pin
• Analog Ground
In high-speed operation, and under proper circuit
conditions, it is possible for the comparator output to
oscillate. This oscillation can have adverse effects on
the hardware and software relying on this signal.
Therefore, a digital filter has been added to the
comparator output to suppress the comparator output
oscillation. Once the comparator output changes, the
output is prevented from reversing the change for a
nominal time of 20 ns. This allows the comparator
output to stabilize without affecting other dependent
devices. Refer to Figure 20-3.
Some inverting input selections share a pin with the
operational amplifier output function. Enabling both
functions at the same time will direct the operational
amplifier output to the comparator inverting input.
Note:
To use CxINy+ and CxINy- pins as analog
input, the appropriate bits must be set in
the ANSEL register and the correspond-
ing TRIS bits must also be set to disable
the output drivers.
20.8 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
FIGURE 20-3:
COMPARATOR ZERO LATENCY FILTER OPERATION
CxOUT From Comparator
CxOUT From ZLF
TZLF
Output waiting for TZLF to expire before an output change is allowed
TZLF has expired so output change of ZLF is immediate based on
comparator output change
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20.10.1 ALTERNATE PIN LOCATIONS
20.10 Analog Input Connection
Considerations
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 13.1 “Alternate Pin Function” for
more information.
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
FIGURE 20-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
VT 0.6V
RIC
Rs < 10K
To Comparator
(1)
ILEAKAGE
CPIN
5 pF
VA
VT 0.6V
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
VT
= Threshold Voltage
Note 1: See Section 30.0 “Electrical Specifications”
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20.11 Register Definitions: Comparator Control
REGISTER 20-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0
CxON
R-0/0
R/W-0/0
CxOE
R/W-0/0
CxPOL
R/W-0/0
CxZLF
R/W-1/1
CxSP
R/W-0/0
CxHYS
R/W-0/0
CxSYNC
CxOUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
CxON: Comparator Enable bit
1= Comparator is enabled
0= Comparator is disabled and consumes no active power
CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1= CxVP < CxVN
0= CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1= CxVP > CxVN
0= CxVP < CxVN
bit 5
CxOE: Comparator Output Enable bit
1= CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0= CxOUT is internal only
bit 4
bit 3
bit 2
bit 1
bit 0
CxPOL: Comparator Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
CxZLF: Comparator Zero Latency Filter Enable bit
1= Comparator output is filtered
0= Comparator output is unfiltered
CxSP: Comparator Speed/Power Select bit
1= Comparator operates in normal power, higher speed mode
0= Comparator operates in low-power, low-speed mode
CxHYS: Comparator Hysteresis Enable bit
1= Comparator hysteresis enabled
0= Comparator hysteresis disabled
CxSYNC: Comparator Output Synchronous Mode bit
1= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0= Comparator output to Timer1 and I/O pin is asynchronous.
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REGISTER 20-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
R/W-0/0
CxINTP
R/W-0/0
CxINTN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
CxPCH<2:0>
CxNCH<2:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
CxINTP: Comparator Interrupt on Positive Going Edge Enable bits
1= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0= No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6
CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0= No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-3
CxPCH<2:0>: Comparator Positive Input Channel Select bits
111= CxVP connects to AGND
110= CxVP connects to FVR Buffer 2
101= CxVP connects to DAC_output
100= Reserved, input floating
011= Reserved, input floating
010= Reserved, input floating
001= CxVP connects to CxIN1+ pin
000= CxVP connects to CxIN0+ pin
bit 2-0
CxNCH<2:0>: Comparator Negative Input Channel Select bits
111= CxVN connects to AGND
110= CxVN unconnected, input floating
101= Reserved, input floating
100= Reserved, input floating
011= CxVN connects to CxIN3- pin
010= CxVN connects to CxIN2- pin
001= CxVN connects to CxIN1- pin
000= CxVN connects to CxIN0- pin
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REGISTER 20-3: CMOUT: COMPARATOR OUTPUT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0/0
R-0/0
R-0/0
MC3OUT
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-3
bit 2
Unimplemented: Read as ‘0’
MC3OUT: Mirror Copy of C3OUT bit
MC2OUT: Mirror Copy of C2OUT bit
MC1OUT: Mirror Copy of C1OUT bit
bit 1
bit 0
TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
ANSELB
CM1CON0
CM2CON0
CM1CON1
CM2CON1
CM3CON0
CM3CON1
CMOUT
FVRCON
DACCON0
DACCON1
INTCON
PIE2
ANSA7
—
—
—
ANSA5
ANSB5
C1OE
ANSA4
ANSB4
ANSA3
ANSB3
C1ZLF
C2ZLF
ANSA2
ANSB2
C1SP
ANSA1
ANSB1
ANSA0
ANSB0
115
121
169
169
170
170
169
170
171
137
161
161
79
C1ON
C2ON
C1NTP
C2NTP
C3ON
C3INTP
—
C1OUT
C2OUT
C1INTN
C2INTN
C3OUT
C3INTN
—
C1POL
C1HYS
C1SYNC
C2SYNC
C2OE
C2POL
C2SP
C2HYS
C1PCH<2:0>
C2PCH<2:0>
C3POL
C1NCH<2:0>
C2NCH<2:0>
C3HYS
C3OE
C3ZLF
—
C3SP
C3SYNC
C3PCH<2:0>
—
C3NCH<2:0>
—
MC3OUT MC2OUT MC1OUT
ADFVR<1:0>
FVREN
DACEN
FVRRDY
—
TSEN
TSRNG
CDAFVR<1:0>
DACPSS<1:0>
DACOE1
DACOE2
—
DACNSS
DACR<7:0>
GIE
PEIE
C2IE
TMR0IE
C1IE
INTE
EEIE
IOCIE
BCL1IE
BCL1IF
TRISA3
TRISB3
TRISC3
TMR0IF
—
INTF
C3IE
IOCIF
OSEIE
OSFIF
CCP2IE
CCP2IF
TRISA0
TRISB0
TRISC0
81
PIR2
C2IF
C1IF
EEIF
—
C3IF
84
TRISA
TRISA7
TRISB7
TRISC7
TRISA6
TRISB6
TRISC6
TRISA5
TRISB5
TRISC5
TRISA4
TRISB4
TRISC4
TRISA2
TRISB2
TRISC2
TRISA1
TRISB1
TRISC1
115
121
125
TRISB
TRISC
Note 1: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
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21.1.2
8-BIT COUNTER MODE
21.0 TIMER0 MODULE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
The Timer0 module is an 8-bit timer/counter with the
following features:
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’.
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
• TMR0 can be used to gate Timer1
Figure 21-1 is a block diagram of the Timer0 module.
21.1 Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
21.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 21-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
1
8
T0CKI
1
Sync
TMR0
2 TCY
0
Set Flag bit TMR0IF
TMR0SE
TMR0CS
8-bit
Prescaler
on Overflow
PSA
Overflow to Timer1
8
PS<2:0>
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21.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are eight prescaler options for the Timer0
module ranging from 1:2 to 1:256. The prescale values
are selectable via the PS<2:0> bits of the
OPTION_REG register. In order to have a 1:1 prescaler
value for the Timer0 module, the prescaler must be
disabled by setting the PSA bit of the OPTION_REG
register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
21.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
21.1.5
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 30.0 “Electrical
Specifications”.
21.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
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21.2 Register Definitions: Option Register
REGISTER 21-1: OPTION_REG: OPTION REGISTER
R/W-1/1
WPUEN
R/W-1/1
INTEDG
R/W-1/1
R/W-1/1
R/W-1/1
PSA
R/W-1/1
R/W-1/1
PS<2:0>
R/W-1/1
bit 0
TMR0CS
TMR0SE
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-Up Enable bit
1= All weak pull-ups are disabled (except MCLR, if it is enabled)
0= Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of INT pin
0= Interrupt on falling edge of INT pin
TMR0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
TMR0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is not assigned to the Timer0 module
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Register
on Page
Name
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
TMR0IE
INTE
IOCIE
PSA
TMR0IF
INTF
IOCIF
79
174
172*
114
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
PS<2:0>
TMR0
TRISA
Timer0 Module Register
TRISA7 TRISA6 TRISA5 TRISA4
TRISA3
TRISA2
TRISA1 TRISA0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
Page provides register information.
*
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• Gate Toggle mode
22.0 TIMER1 MODULE WITH GATE
CONTROL
• Gate Single-pulse mode
• Gate Value Status
The Timer1 module is a 16-bit timer/counter with the
following features:
• Gate Event Interrupt
Figure 22-1 is a block diagram of the Timer1 module.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Dedicated 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Auto-conversion Trigger (with CCP)
• Selectable Gate Source Polarity
FIGURE 22-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1G
T1GSPM
00
From Timer0
Overflow
0
01
10
11
t1g_in
Data Bus
T1GVAL
0
1
D
Q
Single-Pulse
Acq. Control
RD
sync_C1OUT
sync_C2OUT
1
T1GCON
Q1 EN
D
Q
Q
Interrupt
Set
T1GGO/DONE
CK
TMR1ON
T1GTM
TMR1GIF
det
R
T1GPOL
TMR1GE
Set flag bit
TMR1IF on
Overflow
TMR1ON
To Comparator Module
TMR1(2)
EN
D
Synchronized
clock input
0
To ADC Auto-Conversion
T1CLK
TMR1H
TMR1L
Q
1
TMR1CS<1:0>
Reserved
T1SYNC
T1OSO
T1OSI
OUT
11
10
Synchronize(3)
det
T1OSC
EN
Prescaler
1, 2, 4, 8
1
0
2
T1CKPS<1:0>
FOSC
Internal
Clock
01
00
FOSC/2
Internal
Clock
T1OSCEN
T1CKI
Sleep input
FOSC/4
Internal
Clock
(1)
To Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
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22.1 Timer1 Operation
22.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> and T1OSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Table 22-2 displays the clock source selections.
22.2.1
INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and
increments on every selected edge of the external
source.
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 22-1 displays the Timer1 enable
selections.
The following asynchronous sources may be used:
TABLE 22-1: TIMER1 ENABLE
SELECTIONS
• Asynchronous event on the T1G pin to Timer1
gate
Timer1
Operation
TMR1ON
TMR1GE
• C1 or C2 comparator input to Timer1 gate
0
0
1
1
0
1
0
1
Off
Off
22.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
Always On
Count Enabled
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI, which can
be synchronized to the microcontroller system clock or
can run asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 22-2: CLOCK SOURCE SELECTIONS
TMR1CS<1:0>
T1OSCEN
Clock Source
11
10
10
01
00
x
1
0
x
x
Reserved
Timer1 Oscillator
External Clocking on T1CKI Pin
System Clock (FOSC)
Instruction Clock (FOSC/4)
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22.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
22.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
22.4 Timer1 Oscillator
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins T1OSI (input) and T1OSO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
The oscillator circuit is enabled by setting the T1OS-
CEN bit of the T1CON register. The oscillator will con-
tinue to run during Sleep.
22.6 Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to using Timer1. A
suitable delay similar to the OST delay
can be implemented in software by
clearing the TMR1IF bit then presetting
the TMR1H:TMR1L register pair to
FC00h. The TMR1IF flag will be set when
1024 clock cycles have elapsed, thereby
indicating that the oscillator is running and
reasonably stable.
Timer1 gate can also be driven by multiple selectable
sources.
22.6.1
TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 22-3 for timing details.
22.5 Timer1 Operation in
Asynchronous Counter Mode
If the control bit T1SYNC of the T1CON register is set,
the external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 22.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
TABLE 22-3: TIMER1 GATE ENABLE
SELECTIONS
T1CLK T1GPOL
T1G
Timer1 Operation
0
0
1
1
0
1
0
1
Counts
Holds Count
Holds Count
Counts
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
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Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
22.6.2
TIMER1 GATE SOURCE
SELECTION
Timer1 gate source selections are shown in Table 22-4.
Source selection is controlled by the T1GSS bits of the
T1GCON register. The polarity for each available source
is also selectable. Polarity selection is controlled by the
T1GPOL bit of the T1GCON register.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TABLE 22-4: TIMER1 GATE SOURCES
22.6.4
TIMER1 GATE SINGLE-PULSE
MODE
T1GSS
Timer1 Gate Source
Timer1 Gate Pin
00
01
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is enabled by first setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software. See Figure 22-5 for timing details.
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
Comparator 1 Output sync_C1OUT
(optionally Timer1 synchronized output)
Comparator 2 Output sync_C2OUT
(optionally Timer1 synchronized output)
22.6.2.1
T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
If the Single-Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
22.6.2.2
Timer0 Overflow Gate Operation
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 22-6 for timing
details.
When Timer0 increments from FFh to 00h,
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
a
22.6.2.3
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 gate control. The
22.6.5
TIMER1 GATE VALUE
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is accessible by reading the T1GVAL bit in
the T1GCON register. The T1GVAL bit is valid even
when the Timer1 gate is not enabled (TMR1GE bit is
cleared).
Comparator
1
output (sync_C1OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 20.4.1 “Comparator
Output Synchronization”.
22.6.2.4
Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 gate control.
The Comparator 2 output (sync_C2OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 20.4.1 “Comparator
Output Synchronization”.
22.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR1 register will be
set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
22.6.3
TIMER1 GATE TOGGLE MODE
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 22-4 for timing details.
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22.7 Timer1 Interrupt
22.9 CCP Capture/Compare Time Base
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Auto-conversion Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
For
more
information,
see
Section 25.0
“Capture/Compare/PWM Modules”.
Note:
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
22.10 CCP Auto-Conversion Trigger
When any of the CCP’s are configured to trigger a
auto-conversion, the trigger will clear the
TMR1H:TMR1L register pair. This auto-conversion
does not cause a Timer1 interrupt. The CCP module
may still be configured to generate a CCP interrupt.
22.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
Timer1 should be synchronized and FOSC/4 should be
selected as the clock source in order to utilize the
Auto-conversion Trigger. Asynchronous operation of
Timer1 can cause a Auto-conversion Trigger to be
missed.
• TMR1CS bits of the T1CON register must be
configured
In the event that a write to TMR1H or TMR1L coincides
with a Auto-conversion Trigger from the CCP, the write
will take precedence.
• T1OSCEN bit of the T1CON register must be
configured
For
more
information,
see
Section 25.2.4
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
“Auto-Conversion Trigger”.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 22-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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FIGURE 22-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
N + 3
N + 4
FIGURE 22-4:
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1 N + 2 N + 3 N + 4
N + 5 N + 6 N + 7 N + 8
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FIGURE 22-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
Cleared by
software
Set by hardware on
falling edge of T1GVAL
Cleared by software
TMR1GIF
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FIGURE 22-6:
TMR1GE
T1GPOL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1GSPM
T1GTM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
N + 4
N + 2 N + 3
N
N + 1
Set by hardware on
falling edge of T1GVAL
Cleared by
software
Cleared by software
TMR1GIF
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22.11 Register Definitions: Timer1 Control
T
REGISTER 22-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
T1SYNC
U-0
—
R/W-0/u
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
11= Reserved, do not use.
10= Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
01= Timer1 clock source is system clock (FOSC)
00= Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: LP Oscillator Enable Control bit
1= Dedicated Timer1 oscillator circuit enabled
0= Dedicated Timer1 oscillator circuit disabled
T1SYNC: Timer1 Synchronization Control bit
1= Do not synchronize asynchronous clock input
0= Synchronize asynchronous clock input with system clock (FOSC)
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1 and clears Timer1 gate flip-flop
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REGISTER 22-2: T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
T1GPOL
R/W-0/u
T1GTM
R/W-0/u
R/W/HC-0/u
R-x/x
R/W-0/u
R/W-0/u
TMR1GE
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1= Timer1 counting is controlled by the Timer1 gate function
0= Timer1 counts regardless of Timer1 gate function
bit 6
bit 5
T1GPOL: Timer1 Gate Polarity bit
1= Timer1 gate is active-high (Timer1 counts when gate is high)
0= Timer1 gate is active-low (Timer1 counts when gate is low)
T1GTM: Timer1 Gate Toggle Mode bit
1= Timer1 Gate Toggle mode is enabled
0= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single-Pulse Mode bit
1= Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0= Timer1 Gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1= Timer1 gate single-pulse acquisition is ready, waiting for an edge
0= Timer1 gate single-pulse acquisition has completed or has not been started
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits
11= Comparator 2 optionally synchronized output (sync_C2OUT)
10= Comparator 1 optionally synchronized output (sync_C1OUT)
01= Timer0 overflow output
00= Timer1 gate pin
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TABLE 22-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELB
CCP1CON
CCP2CON
INTCON
PIE1
—
—
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
121
255
255
79
DC1B<1:0>
DC2B<1:0>
CCP1M<3:0>
CCP2M<3:0>
—
—
GIE
PEIE
ADIE
ADIF
TMR0IE
INTE
TXIE
TXIF
IOCIE
SSP1IE
SSP1IF
TMR0IF
INTF
IOCIF
TMR1IE
TMR1IF
TMR1GIE
TMR1GIF
RCIE
RCIF
CCP1IE
CCP1IF
TMR2IE
TMR2IF
80
PIR1
83
TMR1H
TMR1L
TRISB
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
175*
175*
120
125
183
184
TRISB7
TRISC7
TRISB6
TRISC6
TRISB5
TRISC5
TRISB4
TRISC4
TRISB3
TRISC3
TRISB2
TRISC2
T1SYNC
T1GVAL
TRISB1
TRISC1
—
TRISB0
TRISC0
TMR1ON
TRISC
T1CON
T1GCON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GSS<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
*
Page provides register information.
2011-2014 Microchip Technology Inc.
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23.0 TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
• Optional use as the shift clock for the MSSP
module
See Figure 23-1 for a block diagram of Timer2.
FIGURE 23-1:
TIMER2 BLOCK DIAGRAM
Prescaler
TMR2
Reset
EQ
TMR2 Output
FOSC/4
1:1, 1:4, 1:16, 1:64
Postscaler
1:1 to 1:16
2
Comparator
Sets Flag bit TMR2IF
T2CKPS<1:0>
PR2
4
T2OUTPS<3:0>
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23.1 Timer2 Operation
23.3 Timer2 Output
The clock input to the Timer2 modules is the system
instruction clock (FOSC/4).
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 26.0
“Master Synchronous Serial Port (MSSP) Module”
23.4 Timer2 Operation During Sleep
The Timer2 timers cannot be operated while the
processor is in Sleep mode. The contents of the TMR2
and PR2 registers will remain unchanged while the
processor is in Sleep mode.
counter/postscaler
(see
Section 23.2
“Timer2
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESETInstruction
Note:
TMR2 is not cleared when T2CON is
written.
23.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE, of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
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23.5 Register Definitions: Timer2 Control
REGISTER 23-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
1111= 1:16 Postscaler
1110= 1:15 Postscaler
1101= 1:14 Postscaler
1100= 1:13 Postscaler
1011= 1:12 Postscaler
1010= 1:11 Postscaler
1001= 1:10 Postscaler
1000= 1:9 Postscaler
0111= 1:8 Postscaler
0110= 1:7 Postscaler
0101= 1:6 Postscaler
0100= 1:5 Postscaler
0011= 1:4 Postscaler
0010= 1:3 Postscaler
0001= 1:2 Postscaler
0000= 1:1 Postscaler
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
11= Prescaler is 64
10= Prescaler is 16
01= Prescaler is 4
00= Prescaler is 1
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TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP2CON
INTCON
PIE1
—
—
DC2B<1:0>
CCP2M<3:0>
255
79
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
TMR1GIE
TMR1GIF
ADIE
ADIF
RCIE
RCIF
TXIE
TXIF
SSP1IE
SSP1IF
CCP1IE TMR2IE
TMR1IE
TMR1IF
80
PIR1
CCP1IF
TMR2IF
83
PR2
Timer2 Module Period Register
T2OUTPS<3:0>
Holding Register for the 8-bit TMR2 Register
186*
188
186*
T2CON
TMR2
—
TMR2ON
T2CKPS<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
Page provides register information.
*
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Modes of operation include:
24.0 PROGRAMMABLE SWITCH
MODE CONTROL (PSMC)
• Single-phase
• Complementary Single-phase
• Push-Pull
The Programmable Switch Mode Controller (PSMC) is
a high-performance Pulse Width Modulator (PWM) that
can be configured to operate in one of several modes
to support single or multiple phase applications.
• Push-Pull 4-Bridge
• Complementary Push-Pull 4-Bridge
• Pulse Skipping
A simplified block diagram indicating the relationship
between inputs, outputs, and controls is shown in
Figure 24-1.
• Variable Frequency Fixed Duty Cycle
• Complementary Variable Frequency Fixed Duty
Cycle
This section begins with the fundamental aspects of the
PSMC operation. A more detailed description of opera-
tion for each mode is located later in Section 24.3
“Modes of Operation”
• ECCP Compatible modes
- Full-Bridge
- Full-Bridge Reverse
• 3-Phase 6-Step PWM
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FIGURE 24-1:
PSMC SIMPLIFIED BLOCK DIAGRAM
PXCPRE<1:0>
PXCSRC<1:0>
PSMCXCLK
64 MHZ
FOSC
1,2,
4, 8
psmc_clk
PSMCXTMR
CLR
sync_in
PSMCXPR =
FFA
sync_out
PSMCXPOL
PSMCXOEN
PSMCXPRS
PSMCXPH
PSMCXA
PSMCXB
PSMCXC
PSMCXD
PSMCXE
PSMCXF
=
S
Q
PSMCXPHS
PSMCXDC
=
R
PXMODE
PSMCXDCS
PSMCXSTR
Shutdown
PSMCXREBS
PSMCXFEBS
Blanking
PSMCXASDS
sync_C1OUT
sync_C2OUT
sync_C3OUT
PSMCXIN
CCP1
CCP2
PSMCXMDL
PIC16(L)F1782/3
The basic waveform generated from these events is
shown in Figure 24-2.
24.1 Fundamental Operation
PSMC operation is based on the sequence of three
events:
• Period Event – Determines the frequency of the
active signal.
• Rising Edge Event – Determines start of the
active pulse. This is also referred to as the phase.
• Falling Edge Event – Determines the end of the
active pulse. This is also referred to as the duty
cycle.
FIGURE 24-2:
BASIC PWM WAVEFORM GENERATION
1
2
3
PWM Cycle Number
Inputs
Period Event
Rising Edge Event
Falling Edge Event
Outputs
PWM output
Each of the three types of events is triggered by a user
selectable combination of synchronous timed and
asynchronous external inputs.
PSMC operation can be quickly terminated without
software intervention by the auto-shutdown control.
Auto-shutdown can be triggered by any combination of
the following:
Asynchronous event inputs may come directly from an
input pin or through the comparators.
• PSMCxIN pin
• sync_C1OUT
• sync_C2OUT
• sync_C3OUT
Synchronous timed events are determined from the
PSMCxTMR counter, which is derived from internal
clock sources. See Section 24.2.5 “PSMC Time Base
Clock Sources” for more detail.
The active pulse stream can be further modulated by
one of several internal or external sources:
• Register control bit
• Comparator output
• CCP output
• Input pin
User selectable deadtime can be inserted in the drive
outputs to prevent shoot through of configurations with
two devices connected in series between the supply
rails.
Applications requiring very small frequency granularity
control when the PWM frequency is large can do so
with the fractional frequency control available in the
variable frequency fixed Duty Cycle modes.
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prevent the PSMC output from chattering in the
presence of spurious event inputs. A rising edge event
is also suppressed when it occurs after a falling edge
event in the same period.
24.1.1
PERIOD EVENT
The period event determines the frequency of the
active pulse. Period event sources include any
combination of the following:
The rising edge event also triggers the start of two other
timers when needed: falling edge blanking and
dead-band period. For more detail refer to
Section 24.2.8 “Input Blanking” and Section 24.4
“Dead-Band Control”.
• PSMCxTMR counter match
• PSMC input pin
• sync_C1OUT
• sync_C2OUT
• sync_C3OUT
•
When the rising edge event is delayed from the period
start, the amount of delay subtracts from the total amount
of time available for the drive duty cycle. For example, if
the rising edge event is delayed by 10% of the period
time, the maximum duty cycle for that period is 90%. A
100% duty cycle is still possible in this example, but duty
cycles from 90% to 100% are not possible.
Period event sources are selected with the PSMC
Period Source (PSMCxPRS) register (Register 24-13).
Section 24.2.1.2 “16-bit Period Register” contains
details on configuring the PSMCxTMR counter match
for synchronous period events.
24.1.3
FALLING EDGE EVENT
All period events cause the PSMCxTMR counter to
reset on the counting clock edge immediately following
the period event. The PSMCxTMR counter resumes
counting from zero on the counting clock edge after the
period event Reset.
The falling edge event determines the end of the active
drive period. The falling edge event is also referred to
as the duty cycle because varying the falling edge
event, while keeping the rising edge event and period
events fixed, varies the active drive duty cycle.
During a period, the rising event and falling event are
each permitted to occur only once. Subsequent rising
or falling events that may occur within the period are
suppressed, thereby preventing output chatter from
spurious inputs.
Depending on the PSMC mode, one or more of the
PSMC outputs will change in immediate response to
the falling edge event. Falling edge event sources
include any combination of the following:
• Synchronous:
- PSMCxTMR time base counter match
• Asynchronous:
- PSMC input pin
- sync_C1OUT
24.1.2
RISING EDGE EVENT
The rising edge event determines the start of the active
drive period. The rising edge event is also referred to
as the phase because two synchronized PSMC periph-
erals may have different rising edge events relative to
the period start, thereby creating a phase relationship
between the two PSMC peripheral outputs.
- sync_C2OUT
- sync_C3OUT
Depending on the PSMC mode, one or more of the
PSMC outputs will change in immediate response to
the rising edge event. Rising edge event sources
include any combination of the following:
-
Falling edge event sources are selected with PSMC Duty
Cycle Source (PSMCxDCS) register (Register 24-12).
For configuring the PSMCxTMR time base counter
match for synchronous falling edge events, see
Section 24.2.1.4 “16-bit Duty Cycle Register”.
• Synchronous:
- PSMCxTMR time base counter match
• Asynchronous:
- PSMC input pin
- sync_C1OUT
The first falling edge event in a cycle period is the only
one permitted to cause action. All subsequent falling
edge events in the same period are suppressed to
prevent the PSMC output from chattering in the
presence of spurious event inputs.
- sync_C2OUT
- sync_C3OUT
-
A falling edge event suppresses any subsequent rising
edges that may occur in the same period. In other words,
if an asynchronous falling event input should come late
and occur early in the period, following that for which it
was intended, the rising edge in that period will be sup-
pressed. This will have a similar effect as pulse skipping.
Rising edge event sources are selected with the PSMC
Phase Source (PSMCxPHS) register (Register 24-11).
For configuring the PSMCxTMR time base counter
match for synchronous rising edge events, see
Section 24.2.1.3 “16-bit Phase Register”.
The falling edge event also triggers the start of two
other timers: rising edge blanking and dead-band
period. For more detail refer to Section 24.2.8 “Input
Blanking” and Section 24.4 “Dead-Band Control”.
The first rising edge event in a cycle period is the only
one permitted to cause action. All subsequent rising
edge events in the same period are suppressed to
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24.2.1.2
16-bit Period Register
24.2 Event Sources
The PSMCxPR Period register is used to determine a
synchronous period event referenced to the 16-bit
PSMCxTMR digital counter. A match between the
PSMCxTMR and PSMCxPR register values will
generate a period event.
There are two main sources for the period, rising edge
and falling edge events:
• Synchronous input
- Time base
• Asynchronous Inputs
- Digital Inputs
The match will generate a period match interrupt,
thereby setting the PxTPRIF bit of the PSMC Time Base
Interrupt Control (PSMCxINT) register (Register 24-32).
- Analog inputs
The 16-bit period value is accessible to software as
two 8-bit registers:
24.2.1
TIME BASE
The Time Base section consists of several smaller
pieces.
• PSMC Period Count Low Byte (PSMCxPRL)
register (Register 24-23)
• 16-bit time base counter
• PSMC Period Count High Byte (PSMCxPRH)
register (Register 24-24)
• 16-bit Period register
• 16-bit Phase register (rising edge event)
• 16-bit Duty Cycle register (falling edge event)
• Clock control
The 16-bit period value is double-buffered before it is
presented to the 16-bit time base for comparison. The
buffered registers are updated on the first period event
Reset after the PSMCxLD bit of the PSMCxCON
register is set.
• Interrupt Generator
An example of a fully synchronous PWM waveform
generated with the time base is shown in Figure 24-2.
The synchronous PWM period time can be determined
from Equation 24-1.
The PSMCxLD bit of the PSMCxCON register is
provided to synchronize changes to the event Count
registers. Changes are withheld from taking action until
the first period event Reset after the PSMCxLD bit is
set. For example, to change the PWM frequency, while
maintaining the same effective duty cycle, the Period
and Duty Cycle registers need to be changed. The
changes to all four registers take effect simultaneously
on the period event Reset after the PSMCxLD bit is set.
EQUATION 24-1: PWM PERIOD
PSMCxPR[15:0] + 1
Period = -------------------------------------------------
Fpsmc_clk
24.2.1.3
16-bit Phase Register
The PSMCxPH Phase register is used to determine a
synchronous rising edge event referenced to the 16-bit
PSMCxTMR digital counter. A match between the
PSMCxTMR and the PSMCxPH register values will
generate a rising edge event.
24.2.1.1
16-bit Counter (Time Base)
The PSMCxTMR is the counter used as a timing
reference for each synchronous PWM period. The
counter starts at 0000h and increments to FFFFh on
the rising edge of the psmc_clk signal.
The match will generate a phase match interrupt,
thereby setting the PxTPHIF bit of the PSMC Time
When the counter rolls over from FFFFh to 0000h
without a period event occurring, the overflow interrupt
will be generated, thereby setting the PxTOVIF bit of
the PSMC Time Base Interrupt Control (PSMCxINT)
register (Register 24-32).
Base
Interrupt
Control
(PSMCxINT)
register
(Register 24-32).
The 16-bit phase value is accessible to software as
two 8-bit registers:
The PSMCxTMR counter is reset on both synchronous
and asynchronous period events.
• PSMC Phase Count Low Byte (PSMCxPHL)
register (Register 24-32)
The PSMCxTMR is accessible to software as two 8-bit
registers:
• PSMC Phase Count High Byte (PSMCxPHH)
register (Register 24-32)
• PSMC Time Base Counter Low (PSMCxTMRL)
register (Register 24-17)
The 16-bit phase value is double-buffered before it is
presented to the 16-bit PSMCxTMR for comparison.
The buffered registers are updated on the first period
event Reset after the PSMCxLD bit of the PSMCxCON
register is set.
• PSMC PSMC Time Base Counter High
(PSMCxTMRH) register (Register 24-18)
PSMCxTMR is reset to the default POR value when the
PSMCxEN bit is cleared.
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Each interrupt has an interrupt flag bit and an interrupt
enable bit. The interrupt flag bit is set anytime a given
event occurs, regardless of the status of the enable bit.
24.2.1.4
The PSMCxDC Duty Cycle register is used to
determine synchronous falling edge event
16-bit Duty Cycle Register
a
Time base interrupt enables and flags are located in
the PSMC Time Base Interrupt Control (PSMCxINT)
register (Register 24-32).
referenced to the 16-bit PSMCxTMR digital counter. A
match between the PSMCxTMR and PSMCxDC
register values will generate a falling edge event.
The match will generate a duty cycle match interrupt,
thereby setting the PxTDCIF bit of the PSMC Time Base
Interrupt Control (PSMCxINT) register (Register 24-32).
PSMC time base interrupts also require that the
PSMCxTIE bit in the PIE4 register and the PEIE and
GIE bits in the INTCON register be set in order to
generate an interrupt. The PSMCxTIF interrupt flag in
the PIR4 register will only be set by a time base
interrupt when one or more of the enable bits in the
PSMCxINT register is set.
The 16-bit duty cycle value is accessible to software
as two 8-bit registers:
• PSMC Duty Cycle Count Low Byte (PSMCxDCL)
register (Register 24-21)
The interrupt flag bits need to be cleared in software.
However, all PMSCx time base interrupt flags, except
PSMCxTIF, are cleared when the PSMCxEN bit is
cleared.
• PSMC Duty Cycle Count High Byte (PSMCxDCH)
register (Register 24-22)
The 16-bit duty cycle value is double-buffered before it
is presented to the 16-bit time base for comparison.
The buffered registers are updated on the first period
event Reset after the PSMCxLD bit of the PSMCxCON
register is set.
Interrupt bits that are set by software will generate an
interrupt provided that the corresponding interrupt is
enabled.
When the period, phase, and duty cycle are all deter-
mined from the time base, the effective PWM duty
cycle can be expressed as shown in Equation 24-2.
Note:
Interrupt flags in both the PIE4 and
PSMCxINT registers must be cleared to
clear the interrupt. The PSMCxINT flags
must be cleared first.
EQUATION 24-2: PWM DUTY CYCLE
24.2.5
PSMC TIME BASE CLOCK
SOURCES
PSMCxDC[15:0] – PSMCxPH[15:0]
DUTYCYCLE = ----------------------------------------------------------------------------------------
PSMCxPR[15:0] + 1
There are three clock sources available to the module:
• Internal 64 MHz clock
• Fosc system clock
• External clock input pin
24.2.2
0% DUTY CYCLE OPERATION
USING TIME BASE
The clock source is selected with the PxCSRC<1:0>
bits of the PSMCx Clock Control (PSMCxCLK) register
(Register 24-5).
To configure the PWM for 0% duty cycle set
PSMCxDC<15:0> = PSMCxPH<15:0>. This will trigger
a falling edge event simultaneous with the rising edge
event and prevent the PWM from being asserted.
When the Internal 64 MHz clock is selected as the
source, the HFINTOSC continues to operate and clock
the PSMC circuitry in Sleep. However, the system
clock to other peripherals and the CPU is suppressed.
24.2.3
100% DUTY CYCLE OPERATION
USING TIME BASE
To configure the PWM for 100% duty cycle set
PSMCxDC<15:0> > PSMCxPR<15:0>.
Note:
When the 64 MHz clock is selected, the
clock continues to operate in Sleep, even
This will prevent a falling edge event from occurring as
the PSMCxDC<15:0> value and the time base value
PSMCxTMR<15:0> will never be equal.
when
the
PSMC
is
disabled
(PSMCxEN = 0). Select a clock other than
the 64 MHz clock to minimize power con-
sumption when the PSMC is not enabled.
24.2.4
TIME BASE INTERRUPT
GENERATION
The Internal 64 MHz clock utilizes the system clock
4x PLL. When the system clock source is external and
the PSMC is using the Internal 64 MHz clock, the
4x PLL should not be used for the system clock.
The Time Base section can generate four unique
interrupts:
• Time Base Counter Overflow Interrupt
• Time Base Phase Register Match Interrupt
• Time Base Duty Cycle Register Match Interrupt
• Time Base Period Register Match Interrupt
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The clock source is selected with the PxCPRE<1:0>
bits of the PSMCx Clock Control (PSMCxCLK) register
(Register 24-5).
24.2.6
CLOCK PRESCALER
There are four prescaler choices available to be
applied to the selected clock:
The prescaler output is psmc_clk, which is the clock
used by all of the other portions of the PSMC module.
• Divide by 1
• Divide by 2
• Divide by 4
• Divide by 8
FIGURE 24-3:
TIME BASE WAVEFORM GENERATION
1
Period
psmc_clk
Counter 0030h 0000h 0001h 0002h 0003h
0027h 0028h 0029h 0030h 0000h
PSMCxPH<15:0>
0002h
0028h
0030h
PSMCxDC<15:0>
PSMCxPR<15:0>
Inputs
Period Event
Rising Edge Event
Falling Edge Event
Output
PWM Output
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The Falling Edge Blanking mode is set with the
PxFEBM<1:0> bits of the PSMCx Blanking Control
(PSMCxBLNK) register (Register 24-8).
24.2.7
ASYNCHRONOUS INPUTS
The PSMC module supports asynchronous inputs
alone or in combination with the synchronous inputs.
asynchronous inputs include:
The Rising Edge Blanking mode is set with the
PxREBM<1:0> bits of the PSMCx Blanking Control
(PSMCxBLNK) register (Register 24-8).
• Analog
- sync_C1OUT
- sync_C2OUT
- sync_C3OUT
• Digital
24.2.8.1
Blanking Disabled
With blanking disabled, the asynchronous inputs are
passed to the PSMC module without any intervention.
- PSMCxIN pin
24.2.8.2
Immediate Blanking
24.2.7.1
Comparator Inputs
With Immediate blanking, a counter is used to
determine the blanking period. The desired blanking
time is measured in psmc_clk periods. A rising edge
event will start incrementing the rising edge blanking
counter. A falling edge event will start incrementing the
falling edge blanking counter.
The outputs of any combination of the synchronized
comparators may be used to trigger any of the three
events as well as auto-shutdown.
The event triggers on the rising edge of the compara-
tor output. Except for auto-shutdown, the event input is
not level sensitive.
The rising edge blanking time is set with the PSMC
Rising Edge Blanking Time (PSMCxBLKR) register
(Register 24-28). The inputs to be blanked are
selected with the PSMC Rising Edge Blanked Source
(PSMCxREBS) register (Register 24-9). During rising
edge blanking, the selected blanked sources are
suppressed for falling edge as well as rising edge,
auto-shutdown and period events.
24.2.7.2
PSMCxIN Pin Input
The PSMCxIN pin may be used to trigger PSMC
events. Data is passed through straight to the PSMC
module without any synchronization to a system clock.
This is so that input blanking may be applied to any
external circuit using the module.
The event triggers on the rising edge of the PSMCxIN
signal.
The falling edge blanking time is set with the PSMC
Falling Edge Blanking Time (PSMCxBLKF) register
(Register 24-29). The inputs to be blanked are
selected with the PSMC Falling Edge Blanked Source
(PSMCxFEBS) register (Register 24-10). During
falling edge blanking, the selected blanked sources
are suppressed for rising edge, as well as falling edge,
auto-shutdown, and period events.
24.2.8
INPUT BLANKING
Input blanking is a function whereby the inputs from
any selected asynchronous input may be driven
inactive for a short period of time. This is to prevent
electrical transients from the turn-on/off of power
components from generating a false event.
The blanking counters are incremented on the rising
edge of psmc_clk. Blanked sources are suppressed
until the counter value equals the blanking time
register causing the blanking to terminate.
Blanking is initiated by either or both:
• Rising event
• Falling event
Blanked inputs are suppressed from causing all
asynchronous events, including:
As the rising and falling edge events are from
asynchronous inputs, there may be some uncertainty
in the actual blanking time implemented in each cycle.
The maximum uncertainty is equal to one psmc_clk
period.
• Rising
• Falling
• Period
• Shutdown
Rising edge and falling edge blanking are controlled
independently. The following features are available for
blanking:
• Blanking enable
• Blanking time counters
• Blanking mode
The following Blanking modes are available:
• Blanking disabled
• Immediate blanking
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24.2.9
OUTPUT WAVEFORM
GENERATION
24.3 Modes of Operation
All modes of operation use the period, rising edge, and
falling edge events to generate the various PWM
output waveforms.
The PSMC PWM output waveform is generated based
upon the different input events. However, there are
several other factors that affect the PWM waveshapes:
The 3-phase 6-step PWM mode makes special use of
the software controlled steering to generate the
required waveform.
• Output Control
- Output Enable
- Output Polarity
Modes of operation are selected with the PSMC
Control (PSMCxCON) register (Register 24-1).
• Waveform Mode Selection
• Dead-band Control
• Steering control
24.3.1
SINGLE-PHASE MODE
The single PWM is the most basic of all the
waveshapes generated by the PSMC module. It
consists of a single output that uses all three events
(rising edge, falling edge and period events) to
generate the waveform.
24.2.10 OUTPUT CONTROL
24.2.10.1 Output Pin Enable
Each PSMC PWM output pin has individual output
enable control.
24.3.1.1
Mode Features
When the PSMC output enable control is disabled, the
module asserts no control over the pin. In this state,
the pin can be used for general purpose I/O or other
associate peripheral use.
• No dead-band control available
• PWM can be steered to any combination of the
following PSMC outputs:
- PSMCxA
- PSMCxB
- PSMCxC
- PSMCxD
- PSMCxE
- PSMCxF
When the PSMC output enable is enabled, the active
PWM waveform is applied to the pin per the port
priority selection.
PSMC output enable selections are made with the
PSMC Output Enable Control (PSMCxOEN) register
(Register 24-6).
• Identical PWM waveform is presented to all pins
for which steering is enabled.
24.2.10.2 Output Steering
PWM output will be presented only on pins for which
output steering is enabled. The PSMC has up to six
PWM outputs. The PWM signal in some modes can be
steered to one or more of these outputs.
24.3.1.2
Waveform Generation
Rising Edge Event
• All outputs with PxSTR enabled are set to the
active state
Steering differs from output enable in the following
manner: When the output is enabled but the PWM
steering to the corresponding output is not enabled,
then general purpose output to the pin is disabled and
the pin level will remain constantly in the inactive PWM
state. Output steering is controlled with the PSMCS
Falling Edge Event
• All outputs with PxSTR enabled are set to the
inactive state
Code for setting up the PSMC generate the
single-phase waveform shown in Figure 24-4, and given
in Example 24-1.
Steering
Control
0
(PSMCxSTR0)
register
(Register 24-30).
Steering operates only in the following modes:
• Single-phase
• Complementary Single-phase
• 3-phase 6-step PWM
24.2.10.3 Polarity Control
Each PSMC output has individual output polarity
control. Polarity is set with the PSMC Polarity Control
(PSMCxPOL) register (Register 24-7).
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EXAMPLE 24-1:
SINGLE-PHASE SETUP
; Single-phase PWM PSMC setup
; Fully synchronous operation
; Period = 10 us
; Duty cycle = 50%
BANKSEL PSMC1CON
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CLRF
0x02
PSMC1PRH
0x7F
PSMC1PRL
0x01
PSMC1DCH
0x3F
PSMC1DCL
PSMC1PHH
PSMC1PHL
0x01
; set period
; set duty cycle
; no phase offset
CLRF
MOVLW
MOVWF
; PSMC clock=64 MHz
PSMC1CLK
; output on A, normal polarity
BSF
BCF
BSF
PSMC1STR0,P1STRA
PSMC1POL, P1POLA
PSMC1OEN, P1OEA
; set time base as source for all events
BSF
BSF
BSF
PSMC1PRS, P1PRST
PSMC1PHS, P1PHST
PSMC1DCS, P1DCST
; enable PSMC in Single-Phase Mode
; this also loads steering and time buffers
MOVLW
MOVWF
B’11000000’
PSMC1CON
BANKSEL TRISC
BCF
TRISC, 0
; enable pin driver
FIGURE 24-4:
SINGLE PWM WAVEFORM – PSMCXSTR0 = 01H
1
2
3
PWM Period Number
Period Event
Rising Edge Event
Falling Edge Event
PSMCxA
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24.3.2
COMPLEMENTARY PWM
EXAMPLE 24-2:
COMPLEMENTARY
SINGLE-PHASE SETUP
The complementary PWM uses the same events as
the single PWM, but two waveforms are generated
instead of only one.
; Complementary Single-phase PWM PSMC setup
; Fully synchronous operation
; Period = 10 us
; Duty cycle = 50%
; Deadband = 93.75 +15.6/-0 ns
BANKSEL PSMC1CON
The two waveforms are opposite in polarity to each
other. The two waveforms may also have dead-band
control as well.
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CLRF
0x02
PSMC1PRH
0x7F
PSMC1PRL
0x01
PSMC1DCH
0x3F
PSMC1DCL
PSMC1PHH
PSMC1PHL
0x01
; set period
24.3.2.1
Mode Features and Controls
• Dead-band control available
• PWM primary output can be steered to the
following pins:
; set duty cycle
- PSMCxA
- PSMCxC
- PSMCxE
; no phase offset
CLRF
MOVLW
MOVWF
; PSMC clock=64 MHz
• PWM complementary output can be steered to
the following pins:
PSMC1CLK
; output on A, normal polarity
- PSMCxB
- PSMCxD
- PSMCxE
MOVLW
MOVWF
MOVWF
CLRF
B’00000011’; A and B enables
PSMC1OEN
PSMC1STR0
PSMC1POL
; set time base as source for all events
24.3.2.2
Waveform Generation
BSF
BSF
BSF
PSMC1PRS, P1PRST
PSMC1PHS, P1PHST
PSMC1DCS, P1DCST
Rising Edge Event
• Complementary output is set inactive
• Optional rising edge dead band is activated
• Primary output is set active
; set rising and falling dead-band times
MOVLW
MOVWF
MOVWF
D’6’
PSMC1DBR
PSMC1DBF
Falling Edge Event
; enable PSMC in Complementary Single Mode
; this also loads steering and time buffers
; and enables rising and falling deadbands
• Primary output is set inactive
• Optional falling edge dead band is activated
• Complementary output is set active
MOVLW
MOVWF
B’11110001’
PSMC1CON
Code for setting up the PSMC generate the
complementary single-phase waveform shown in
Figure 24-5, and given in Example 24-2.
BANKSEL TRISC
BCF
BCF
TRISC, 0
TRISC, 1
; enable pin drivers
FIGURE 24-5:
COMPLEMENTARY PWM WAVEFORM – PSMCXSTR0 = 03H
1
2
3
PWM Period Number
Period Event
Rising Edge Event
Falling Edge Event
PSMCxA
(Primary Output)
Rising Edge Dead Band
Rising Edge Dead Band
Falling Edge Dead Band
Falling Edge Dead Band
PSMCxB
(Complementary Output)
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Code for setting up the PSMC generate the comple-
mentary single-phase waveform shown in Figure 24-6,
and given in Example 24-3.
24.3.3
PUSH-PULL PWM
The push-pull PWM is used to drive transistor bridge
circuits. It uses at least two outputs and generates
PWM signals that alternate between the two outputs in
even and odd cycles.
EXAMPLE 24-3:
PUSH-PULL SETUP
; Push-Pull PWM PSMC setup
; Fully synchronous operation
; Period = 10 us
; Duty cycle = 50% (25% each phase)
BANKSEL PSMC1CON
Variations of the push-pull waveform include four
outputs with two outputs being complementary or two
sets of two identical outputs. Refer to Sections 24.3.4
through 24.3.6 for the other Push-Pull modes.
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CLRF
0x02
PSMC1PRH
0x7F
PSMC1PRL
0x01
PSMC1DCH
0x3F
PSMC1DCL
PSMC1PHH
PSMC1PHL
0x01
; set period
24.3.3.1
Mode Features
• No dead-band control available
• No steering control available
• Output is on the following two pins only:
- PSMCxA
; set duty cycle
- PSMCxB
; no phase offset
CLRF
MOVLW
MOVWF
; PSMC clock=64 MHz
Note: This is a subset of the 6-pin output of the
push-pull PWM output, which is why pin
functions are fixed in these positions, so
they are compatible with that mode. See
Section 24.3.6 “Push-Pull PWM with Four
Full-Bridge and Complementary Out-
puts”
PSMC1CLK
; output on A and B, normal polarity
MOVLW
MOVWF
CLRF
B’00000011’
PSMC1OEN
PSMC1POL
; set time base as source for all events
BSF
BSF
BSF
PSMC1PRS, P1PRST
PSMC1PHS, P1PHST
PSMC1DCS, P1DCST
24.3.3.2
Waveform Generation
; enable PSMC in Push-Pull Mode
; this also loads steering and time buffers
Odd numbered period rising edge event:
• PSMCxA is set active
MOVLW
MOVWF
B’11000010’
PSMC1CON
BANKSEL TRISC
Odd numbered period falling edge event:
• PSMCxA is set inactive
BCF
BCF
TRISC, 0
TRISC, 1
; enable pin drivers
Even numbered period rising edge event:
• PSMCxB is set active
Even numbered period falling edge event:
• PSMCxB is set inactive
FIGURE 24-6:
PUSH-PULL PWM WAVEFORM
1
2
3
PWM Period Number
A Output
A Output
Period Event
B Output
Rising Edge Event
Falling Edge Event
PSMCxA
PSMCxB
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24.3.4
PUSH-PULL PWM WITH
24.3.4.2
Waveform Generation
COMPLEMENTARY OUTPUTS
Push-Pull waveforms generate alternating outputs on
the output pairs. Therefore, there are two sets of rising
edge events and two sets of falling edge events
The complementary push-pull PWM is used to drive
transistor bridge circuits as well as synchronous
switches on the secondary side of the bridge. The
PWM waveform is output on four pins presented as
two pairs of two-output signals with a normal and
complementary output in each pair. Dead band can be
inserted between the normal and complementary
outputs at the transition times.
Odd numbered period rising edge event:
• PSMCxE is set inactive
• Dead-band rising is activated (if enabled)
• PSMCxA is set active
Odd numbered period falling edge odd event:
• PSMCxA is set inactive
24.3.4.1
Mode Features
• Dead-band falling is activated (if enabled)
• PSMCxE is set active
• Dead-band control is available
• No steering control available
• Primary PWM output is only on:
- PSMCxA
Even numbered period rising edge event:
• PSMCxF is set inactive
- PSMCxB
• Dead-band rising is activated (if enabled)
• PSMCxB is set active
• Complementary PWM output is only on:
- PSMCxE
Even numbered period falling edge event:
- PSMCxF
• PSMCxB is set inactive
• Dead-band falling is activated (if enabled)
• PSMCxF is set active
Note: This is a subset of the 6-pin output of the
push-pull PWM output, which is why pin func-
tions are fixed in these positions, so they are
compatible
with
that
mode.
See
Section 24.3.6 “Push-Pull PWM with Four
Full-Bridge and Complementary Outputs”.
FIGURE 24-7:
PUSH-PULL WITH COMPLEMENTARY OUTPUTS PWM WAVEFORM
1
2
3
PWM Period Number
Period Event
Rising Edge Event
Falling Edge Event
Rising Edge Dead Band
Rising Edge Dead Band
PSMCxA
Falling Edge Dead Band
Falling Edge Dead Band
PSMCxE
PSMCxB
Falling Edge Dead Band
Rising Edge Dead Band
PSMCxF
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24.3.5
PUSH-PULL PWM WITH FOUR
FULL-BRIDGE OUTPUTS
Note: This is a subset of the 6-pin output of the
push-pull PWM output, which is why pin func-
tions are fixed in these positions, so they are
The full-bridge push-pull PWM is used to drive
transistor bridge circuits as well as synchronous
switches on the secondary side of the bridge.
compatible
with
that
mode.
See
Section 24.3.6 “Push-Pull PWM with Four
24.3.5.1
Mode Features
Full-Bridge and Complementary Outputs”.
• No Dead-band control
• No Steering control available
• PWM is output on the following four pins only:
- PSMCxA
24.3.5.2
Waveform generation
Push-pull waveforms generate alternating outputs on
the output pairs. Therefore, there are two sets of rising
edge events and two sets of falling edge events.
- PSMCxB
Odd numbered period rising edge event:
- PSMCxC
• PSMCxOUT0 and PSMCxOUT2 is set active
Odd numbered period falling edge event:
• PSMCxOUT0 and PSMCxOUT2 is set inactive
Even numbered period rising edge event:
• PSMCxOUT1 and PSMCxOUT3 is set active
Even numbered period falling edge event:
• PSMCxOUT1 and PSMCxOUT3 is set inactive
- PSMCxD
Note: PSMCxA and PSMCxC are identical
waveforms, and PSMCxB and PSMCxD are
identical waveforms.
FIGURE 24-8:
PUSH-PULL PWM WITH 4 FULL-BRIDGE OUTPUTS
1
2
3
PWM Period Number
Period Event
Rising Edge Event
Falling Edge Event
PSMCxA
PSMCxC
PSMCxB
PSMCxD
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24.3.6
PUSH-PULL PWM WITH FOUR
FULL-BRIDGE AND
COMPLEMENTARY OUTPUTS
24.3.6.2
Waveform Generation
Push-pull waveforms generate alternating outputs on
two sets of pin. Therefore, there are two sets of rising
edge events and two sets of falling edge events
The push-pull PWM is used to drive transistor bridge
circuits as well as synchronous switches on the
secondary side of the bridge. It uses six outputs and
generates PWM signals with dead band that alternate
between the six outputs in even and odd cycles.
Odd numbered period rising edge event:
• PSMCxE is set inactive
• Dead-band rising is activated (if enabled)
• PSMCxA and PSMCxC are set active
24.3.6.1
Mode Features and Controls
Odd numbered period falling edge event:
• Dead-band control is available
• No steering control available
• Primary PWM is output on the following four pins:
- PSMCxA
• PSMCxA and PSMCxC are set inactive
• Dead-band falling is activated (if enabled)
• PSMCxE is set active
Even numbered period rising edge event:
- PSMCxB
• PSMCxF is set inactive
- PSMCxC
• Dead-band rising is activated (if enabled)
• PSMCxB and PSMCxD are set active
- PSMCxD
• Complementary PWM is output on the following
two pins:
Even numbered period falling edge event:
- PSMCxE
- PSMCxF
• PSMCxB and PSMCxOUT3 are set inactive
• Dead-band falling is activated (if enabled)
• PSMCxF is set active
Note: PSMCxA and PSMCxC are identical
waveforms, and PSMCxB and PSMCxD are
identical waveforms.
FIGURE 24-9:
PUSH-PULL 4 FULL-BRIDGE AND COMPLEMENTARY PWM
1
2
3
PWM Period Number
Period Event
Rising Edge Event
Falling Edge Event
Rising Edge Dead Band
Rising Edge Dead Band
PSMCxA
PSMCxC
Falling Edge Dead Band
Falling Edge Dead Band
PSMCxE
PSMCxB
PSMCxD
PSMCxF
Falling Edge Dead Band
Rising Edge Dead Band
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24.3.7
PULSE-SKIPPING PWM
24.3.7.2
Waveform Generation
The pulse-skipping PWM is used to generate a series
of fixed-length pulses that can be triggered at each
period event. A rising edge event will be generated
when any enabled asynchronous rising edge input is
active when the period event occurs, otherwise no
event will be generated.
Rising Edge Event
If any enabled asynchronous rising edge event = 1
when there is a period event, then upon the next
synchronous rising edge event:
•
PSMCxA is set active
Falling Edge Event
The rising edge event occurs based upon the value in
the PSMCxPH register pair.
• PSMCxA is set inactive
The falling edge event always occurs according to the
enabled event inputs without qualification between any
two inputs.
Note: To use this mode, an external source must
be used for the determination of whether or
not to generate the set pulse. If the phase
time base is used, it will either always gener-
ate a pulse or never generate a pulse based
on the PSMCxPH value.
24.3.7.1
Mode Features
• No dead-band control available
• No steering control available
• PWM is output to only one pin:
- PSMCxA
FIGURE 24-10:
PULSE-SKIPPING PWM WAVEFORM
1
2
3
4
5
6
7
8
9
10
11
12
PWM Period Number
period_event
Asynchronous
Rising Edge Event
Synchronous
Rising Edge Event
Falling Edge Event
PSMCxA
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24.3.8
PULSE-SKIPPING PWM WITH
COMPLEMENTARY OUTPUTS
24.3.8.2
Waveform Generation
Rising Edge Event
The pulse-skipping PWM is used to generate a series
of fixed-length pulses that may or not be triggered at
each period event. If any of the sources enabled to
generate a rising edge event are high when a period
event occurs, a pulse will be generated. If the rising
edge sources are low at the period event, no pulse will
be generated.
If any enabled asynchronous rising edge event = 1
when there is a period event, then upon the next
synchronous rising edge event:
• Complementary output is set inactive
• Dead-band rising is activated (if enabled)
• Primary output is set active
The rising edge occurs based upon the value in the
PSMCxPH register pair.
Falling Edge Event
• Primary output is set inactive
The falling edge event always occurs according to the
enabled event inputs without qualification between any
two inputs.
• Dead-band falling is activated (if enabled)
• Complementary output is set active
24.3.8.1
Mode Features
Note: To use this mode, an external source must
be used for the determination of whether or
not to generate the set pulse. If the phase
time base is used, it will either always gener-
ate a pulse or never generate a pulse based
on the PSMCxPH value.
• Dead-band control is available
• No steering control available
• Primary PWM is output on only PSMCxA.
• Complementary PWM is output on only PSMCxB.
FIGURE 24-11:
PULSE-SKIPPING WITH COMPLEMENTARY OUTPUT PWM WAVEFORM
1
2
3
4
5
6
7
8
9
10
PWM Period Number
Period Event
Asynchronous
Rising Edge Event
Synchronous
Rising Edge Event
PSMCxA
PSMCxB
Falling Edge Dead Band
Rising Edge Dead Band
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24.3.9
ECCP COMPATIBLE FULL-BRIDGE
PWM
24.3.9.2
Waveform Generation - Forward
In this mode of operation, three of the four pins are
static. PSMCxA is the only output that changes based
on rising edge and falling edge events.
This mode of operation is designed to match the
Full-Bridge mode from the ECCP module. It is called
ECCP compatible as the term “full-bridge” alone has
different connotations in regards to the output
waveforms.
Static Signal Assignment
• Outputs set to active state
- PSMCxD
Full-Bridge Compatible mode uses the same
waveform events as the single PWM mode to
generate the output waveforms.
• Outputs set to inactive state
- PSMCxB
- PSMCxC
There are both Forward and Reverse modes available
for this operation, again to match the ECCP implemen-
tation. Direction is selected with the mode control bits.
Rising Edge Event
• PSMCxA is set active
Falling Edge Event
24.3.9.1
Mode Features
• PSMCxA is set inactive
• Dead-band control available on direction switch
- Changing from forward to reverse uses the
falling edge dead-band counters.
24.3.9.3
Waveform Generation – Reverse
In this mode of operation, three of the four pins are
static. Only PSMCxB toggles based on rising edge
and falling edge events.
- Changing from reverse to forward uses the
rising edge dead-band counters.
• No steering control available
Static Signal Assignment
• PWM is output on the following four pins only:
• Outputs set to active state
- PSMCxC
- PSMCxA
- PSMCxB
- PSMCxC
- PSMCxD
• Outputs set to inactive state
- PSMCxA
- PSMCxD
Rising Edge Event
• PSMCxB is set active
Falling Edge Event
• PSMCxB is set inactive
FIGURE 24-12:
ECCP COMPATIBLE FULL-BRIDGE PWM WAVEFORM – PSMCXSTR0 = 0FH
1
2
3
4
5
6
7
8
9
10
11
12
PWM Period Number
Forward mode operation
Reverse mode operation
Period Event
Falling Edge Event
PSMCxA
PSMCxB
PSMCxC
Rising Edge Dead Band
Falling Edge Dead Band
PSMCxD
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24.3.10 VARIABLE FREQUENCY – FIXED
DUTY CYCLE PWM
24.3.10.2 Waveform Generation
Period Event
This mode of operation is quite different from all of the
other modes. It uses only the period event for
waveform generation. At each period event, the PWM
output is toggled.
• Output of PSMCxA is toggled
• FFA counter is incremented by the 4-bit value in
PSMCxF FA
The rising edge and falling edge events are unused in
this mode.
24.3.10.1 Mode Features
• No dead-band control available
• No steering control available
• Fractional Frequency Adjust
- Fine period adjustments are made with the
PSMC Fractional Frequency Adjust
(PSMCxFFA) register (Register 24-27)
• PWM is output on the following pin only:
- PSMCxA
FIGURE 24-13:
VARIABLE FREQUENCY – FIXED DUTY CYCLE PWM WAVEFORM
1
2
3
4
5
6
7
8
9
10
PWM Period Number
period_event
Rising Edge Event
Falling Edge Event
Unused in this mode
Unused in this mode
PSMCxA
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24.3.11 VARIABLE FREQUENCY - FIXED
DUTY CYCLE PWM WITH
24.3.11.2 Waveform Generation
Period Event
COMPLEMENTARY OUTPUTS
When output is going inactive to active:
• Complementary output is set inactive
This mode is the same as the single output Fixed Duty
Cycle mode except a complementary output with
dead-band control is generated.
• FFA counter is incremented by the 4-bit value in
PSMCFFA register.
The rising edge and falling edge events are unused in
this mode. Therefore, a different triggering mechanism
is required for the dead-band counters.
• Dead-band rising is activated (if enabled)
• Primary output is set active
When output is going active to inactive:
• Primary output is set inactive
A period events that generate a rising edge on
PSMCxA use the rising edge dead-band counters.
• FFA counter is incremented by the 4-bit value in
PSMCFFA register
A period events that generate a falling edge on
PSMCxA use the falling edge dead-band counters.
• Dead-band falling is activated (if enabled)
• Complementary output is set active
24.3.11.1 Mode Features
• Dead-band control is available
• No steering control available
• Fractional Frequency Adjust
- Fine period adjustments are made with the
PSMC Fractional Frequency Adjust
(PSMCxFFA) register (Register 24-27)
• Primary PWM is output to the following pin:
- PSMCxA
• Complementary PWM is output to the following
pin:
- PSMCxB
FIGURE 24-14:
VARIABLE FREQUENCY – FIXED DUTY CYCLE PWM WITH COMPLEMENTARY
OUTPUTS WAVEFORM
1
2
3
4
5
6
7
8
9
10
PWM Period Number
period_event
Rising Edge Event
Falling Edge Event
Unused in this mode
Unused in this mode
PSMCxA
PSMCxB
Falling Edge Dead Band
Rising Edge Dead Band
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24.3.12 3-PHASE PWM
24.3.12.2 Waveform Generation
The 3-Phase mode of operation is used in 3-phase
power supply and motor drive applications configured
as three half-bridges. A half-bridge configuration
consists of two power driver devices in series,
between the positive power rail (high side) and nega-
tive power rail (low side). The three outputs come from
the junctions between the two drivers in each
half-bridge. When the steering control selects a phase
drive, power flows from the positive rail through a
high-side power device to the load and back to the
power supply through a low-side power device.
3-phase steering has a more complex waveform
generation scheme than the other modes. There are
several factors which go into what waveforms are
created.
The PSMC outputs are grouped into three sets of
drivers: one for each phase. Each phase has two
associated PWM outputs: one for the high-side drive
and one for the low-side drive.
High Side drives are indicated by 1H, 2H and 3H.
Low Side drives are indicated by 1L, 2L, 3L.
In this mode of operation, all six PSMC outputs are
used, but only two are active at a time.
Phase grouping is mapped as shown in Table 24-1.
There are six possible phase drive combinations.
Each phase drive combination activates two of the six
outputs and deactivates the other four. Phase drive is
selected with the steering control as shown in
Table 24-2.
The two active outputs consist of a high-side driver
and low-side driver output.
24.3.12.1 Mode Features
TABLE 24-1:
PHASE GROUPING
PSMC grouping
• No dead-band control is available
• PWM can be steered to the following six pairs:
- PSMCxA and PSMCxD
PSMCxA
1H
1L
2H
2L
3H
3L
- PSMCxA and PSMCxF
PSMCxB
PSMCxC
PSMCxD
PSMCxE
PSMCxF
- PSMCxC and PSMCxF
- PSMCxC and PSMCxB
- PSMCxE and PSMCxB
- PSMCxE and PSMCxD
TABLE 24-2: 3-PHASE STEERING CONTROL
PSMCxSTR0 Value( 1)
PSMC outputs
00h
01h
02h
04h
08h
10h
20h
PSMCxA
PSMCxB
PSMCxC
PSMCxD
PSMCxE
PSMCxF
1H
inactive
inactive
inactive
inactive
inactive
inactive
active
inactive
inactive
active
active
inactive
inactive
inactive
inactive
active
inactive
inactive
active
inactive
active
inactive
active
inactive
inactive
inactive
active
1L
2H
2L
3H
3L
active
inactive
inactive
active
inactive
inactive
active
inactive
inactive
inactive
inactive
inactive
active
inactive
inactive
Note 1: Steering for any value other than those shown will default to the output combination of the Least Significant
steering bit that is set.
High/Low Side Modulation Enable
When both the PxHSMEN and PxLSMEN bits are
cleared, the active outputs listed in Table 24-2 go
immediately to the rising edge event states and do not
change.
It is also possible to enable the PWM output on the low
side or high side drive independently using the
PxLSMEN and PXHSMEN bits of the PSMC Steering
Control 1 (PSMCxSTR1) register (Register 24-31).
Rising Edge Event
When the PxHSMEN bit is set, the active-high side
output listed in Table 24-2 is modulated using the
normal rising edge and falling edge events.
• Active outputs are set to their active states
Falling Edge Event
• Active outputs are set to their inactive state
When the PxLSMEN bit is set, the active-low side
output listed in Table 24-2 is modulated using the
normal rising edge and falling edge events.
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FIGURE 24-15:
3-PHASE PWM STEERING WAVEFORM (PXHSMEN = 0AND PXLSMEN = 1)
1
2
3
4
5
6
3-Phase State
01h
02h
04h
08h
10h
20h
PSMCxSTR0
Period Event
Rising Edge Event
Falling Edge Event
PSMCxA (1H)
PSMCxB (1L)
PSMCxC (2H)
PSMCxD (2L)
PSMCxE (3H)
PSMCxF (3L)
PIC16(L)F1782/3
24.4.3
DEAD-BAND CLOCK SOURCE
24.4 Dead-Band Control
The dead-band counters are incremented on every
rising edge of the psmc_clk signal.
The dead-band control provides non-overlapping
PWM signals to prevent shoot-through current in
series connected power switches. Dead-band control
is available only in modes with complementary drive
and when changing direction in the ECCP compatible
Full-Bridge modes.
24.4.4
DEAD-BAND UNCERTAINTY
When the rising and falling edge events that trigger the
dead-band counters come from asynchronous inputs,
there will be uncertainty in the actual dead-band time of
each cycle. The maximum uncertainty is equal to one
psmc_clk period. The one clock of uncertainty may still
be introduced, even when the dead-band count time is
cleared to zero.
The module contains independent 8-bit dead-band
counters for rising edge and falling edge dead-band
control.
24.4.1
DEAD-BAND TYPES
There are two separate dead-band generators
available, one for rising edge events and the other for
falling edge events.
24.4.5
DEAD-BAND OVERLAP
There are two cases of dead-band overlap and each is
treated differently due to system requirements.
24.4.1.1
Rising Edge Dead Band
24.4.5.1
Rising to Falling Overlap
Rising edge dead-band control is used to delay the
turn-on of the primary switch driver from when the
complementary switch driver is turned off.
In this case, the falling edge event occurs while the
rising edge dead-band counter is still counting. The
following sequence occurs:
Rising edge dead band is initiated with the rising edge
event.
1. Dead-band rising count is terminated.
2. Dead-band falling count is initiated.
3. Primary output is suppressed.
Rising edge dead-band time is adjusted with the
PSMC Rising Edge Dead-Band Time (PSMCxDBR)
register (Register 24-25).
24.4.5.2
Falling to Rising Overlap
If the PSMCxDBR register value is changed when the
PSMC is enabled, the new value does not take effect
until the first period event after the PSMCxLD bit is set.
In this case, the rising edge event occurs while the
falling edge dead-band counter is still counting. The
following sequence occurs:
24.4.1.2
Falling Edge Dead Band
1. Dead-band falling count is terminated.
2. Dead-band rising count is initiated.
3. Complementary output is suppressed.
Falling edge dead-band control is used to delay the
turn-on of the complementary switch driver from when
the primary switch driver is turned off.
24.4.5.3
Rising Edge-to-Rising Edge or
Falling Edge-to-Falling Edge
Falling edge dead band is initiated with the falling
edge event.
In cases where one of the two dead-band counters is
set for a short period, or disabled all together, it is
possible to get rising-to-rising or falling-to-falling
overlap. When this is the case, the following sequence
occurs:
Falling edge dead-band time is adjusted with the
PSMC Falling Edge Dead-Band Time (PSMCxDBF)
register (Register 24-26).
If the PSMCxDBF register value is changed when the
PSMC is enabled, the new value does not take effect
until the first period event after the PSMCxLD bit is set.
1. Dead-band count is terminated.
2. Dead-band count is restarted.
24.4.2
DEAD-BAND ENABLE
3. Output waveform control freezes in the present
state.
When a mode is selected that may use dead-band
control, dead-band timing is enabled by setting one of
the enable bits in the PSMC Control (PSMCxCON)
register (Register 24-1).
4. Restarted dead-band count completes.
5. Output control resumes normally.
Rising edge dead band is enabled with the PxDBRE
bit.
Rising edge dead band is enabled with the PxDBFE
bit.
Enable changes take effect immediately.
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24.5.1
3-PHASE STEERING
24.5 Output Steering
3-phase steering is available in the 3-Phase Modulation
mode only. For more details on 3-phase steering refer to
Section 24.3.12 “3-Phase PWM”.
Output steering allows for PWM signals generated by
the PSMC module to be placed on different pins under
software control. Synchronized steering will hold steer-
ing changes until the first period event after the
PSMCxLD bit is set. Unsynchronized steering
changes will take place immediately.
24.5.2
SINGLE PWM STEERING
In Single PWM Steering mode, the single PWM signal
can be routed to any combination of the PSMC output
pins. Examples of unsynchronized single PWM
steering are shown in Figure 24-16.
Output steering is available in the following modes:
• 3-phase PWM
• Single PWM
• Complementary PWM
FIGURE 24-16:
SINGLE PWM STEERING WAVEFORM (NO SYNCHRONIZATION)
Base_PWM_signal
PxSTRA
PSMCxA
PxSTRB
PSMCxB
PxSTRC
PSMCxC
PxSTRD
PSMCxD
PxSTRE
PSMCxE
PxSTRF
PSMCxF
With synchronization disabled, it is possible to get glitches on the PWM outputs.
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The complementary PWM signal can be steered to any
of the following outputs:
24.5.3
COMPLEMENTARY PWM
STEERING
• PSMCxB
• PSMCxD
• PSMCxE
In Complementary PWM Steering mode, the primary
PWM signal (non-complementary) and complementary
signal can be steered according to their respective type.
Primary PWM signal can be steered to any of the
following outputs:
Examples of unsynchronized complementary steering
are shown in Figure 24-17.
• PSMCxA
• PSMCxC
• PSMCxE
FIGURE 24-17:
COMPLEMENTARY PWM STEERING WAVEFORM (NO SYNCHRONIZATION,
ZERO DEAD-BAND TIME)
Base_PWM_signal
PxSTRA
PSMCxA
PSMCxB
PxSTRB
Arrows indicate where a change in the steering bit automatically
forces a change in the corresponding PSMC output.
PxSTRC
PSMCxC
PSMCxD
PxSTRD
PxSTRE
PSMCxE
PSMCxF
PxSTRF
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Examples of synchronized steering are shown in
Figure 24-18.
24.5.4
SYNCHRONIZED PWM STEERING
In Single, Complementary and 3-phase PWM modes,
it is possible to synchronize changes to steering
selections with the period event. This is so that PWM
outputs do not change in the middle of a cycle and
therefore, disrupt operation of the application.
24.5.5
INITIALIZING SYNCHRONIZED
STEERING
If synchronized steering is to be used, special care
should be taken to initialize the PSMC Steering
Control 0 (PSMCxSTR0) register (Register 24-30) in a
safe configuration before setting either the PSMCxEN
or PSMCxLD bits. When either of those bits are set,
the PSMCxSTR0 value at that time is loaded into the
synchronized steering output buffer. The buffer load
occurs even if the PxSSYNC bit is low. When the
PxSSYNC bit is set, the outputs will immediately go to
the drive states in the preloaded buffer.
Steering synchronization is enabled by setting the
PxSSYNC bit of the PSMC Steering Control 1
(PSMCxSTR1) register (Register 24-31).
When synchronized steering is enabled while the
PSMC module is enabled, steering changes do not
take effect until the first period event after the
PSMCxLD bit is set.
FIGURE 24-18:
PWM STEERING WITH SYNCHRONIZATION WAVEFORM
1
2
3
4
5
6
7
Period Number
PWM Signal
PxSTRA
Synchronized PxSTRA
PxSTRB
Synchronized PxSTRB
PSMCxA
PSMCxB
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24.6.2.1
PxMDLBIT Bit
24.6 PSMC Modulation (Burst Mode)
The PxMDLBIT bit of the PSMC Modulation Control
(PSMCxMDL) register (Register 24-2) allows for
software modulation control without having to
enable/disable other module functions.
PSMC modulation is a method to stop/start PWM
operation of the PSMC without having to disable the
module. It also allows other modules to control the
operational period of the PSMC. This is also referred
to as Burst mode.
24.6.3
MODULATION EFFECT ON PWM
SIGNALS
This is a method to implement PWM dimming.
When modulation starts, the PSMC begins operation
on a new period, just as if it had rolled over from one
period to another during continuous operation.
24.6.1
MODULATION ENABLE
The modulation function is enabled by setting the
PxMDLEN bit of PSMC Modulation Control
(PSMCxMDL) register (Register 24-2).
When modulation stops, its operation depends on the
type of waveform being generated.
When modulation is enabled, the modulation source
controls when the PWM signals are active and
inactive.
In operation modes other than Fixed Duty Cycle, the
PSMC completes its current PWM period and then
freezes the module. The PSMC output pins are forced
into the default inactive state ready for use when
modulation starts.
When modulation is disabled, the PWM signals
operate continuously, regardless of the selected
modulation source.
In Fixed Duty Cycle mode operation, the PSMC
continues to operate until the period event changes
the PWM to its inactive state, at which point the PSMC
module is frozen. The PSMC output pins are forced
into the default inactive state ready for use when
modulation starts.
24.6.2
MODULATION SOURCES
There are multiple sources that can be used for
modulating the PSMC. However, unlike the PSMC
input sources, only one modulation source can be
selected at a time. Modulation sources include:
• PSMCxIN pin
• Any CCP output
• Any Comparator output
• PxMDLBIT of the PSMCxMDL register
FIGURE 24-19:
PSMC MODULATION WAVEFORM
1
2
3
4
5
6
7
1
1
2
3
4
5
Modulation Input
PWM Period
PWM Off
PWM Off
PWM
Off
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24.7.2
PIN OVERRIDE LEVELS
24.7 Auto-Shutdown
The logic levels driven to the output pins during an
auto-shutdown event are determined by the PSMC
Auto-shutdown Output Level (PSMCxASDL) register
(Register 24-15).
Auto-shutdown is a method to immediately override
the PSMC output levels with specific overrides that
allow for safe shutdown of the application.
Auto-shutdown includes a mechanism to allow the
application to restart under different conditions.
24.7.2.1
PIN Override Enable
Auto-shutdown is enabled with the PxASDEN bit of the
PSMC Auto-shutdown Control (PSMCxASDC) register
(Register 24-14). All auto-shutdown features are
enabled when PxASDEN is set and disabled when
cleared.
Setting the PxASDOV bit of the PSMC Auto-shutdown
Control (PSMCxASDC) register (Register 24-14) will
also force the override levels onto the pins, exactly like
what happens when the auto-shutdown is used.
However, whereas setting PxASE causes an
auto-shutdown interrupt, setting PxASDOV does not
generate an interrupt.
24.7.1
SHUTDOWN
There are two ways to generate a shutdown event:
24.7.3
RESTART FROM
AUTO-SHUTDOWN
• Manual
• External Input
After an auto-shutdown event has occurred, there are
two ways for the module to resume operation:
24.7.1.1
Manual Override
• Manual restart
The auto-shutdown control register can be used to
manually override the pin functions. Setting the PxASE
bit of the PSMC Auto-shutdown Control (PSMCxASDC)
• Automatic restart
The restart method is selected with the PxARSEN bit of
the PSMC Auto-shutdown Control (PSMCxASDC)
register (Register 24-14).
register (Register 24-14) generates
shut-down event.
a
software
The auto-shutdown override will persist as long as
PxASE remains set.
24.7.3.1
Manual Restart
When PxARSEN is cleared, and once the PxASDE bit
is set, it will remain set until cleared by software.
24.7.1.2
External Input Source
Any of the given sources that are available for event
generation are also available for system shut-down.
This is so that external circuitry can monitor and force
The PSMC will restart on the period event after
PxASDE bit is cleared in software.
a
shutdown without any software overhead.
24.7.3.2
Auto-Restart
Auto-shutdown sources are selected with the PSMC
Auto-shutdown Source (PSMCxASDS) register
(Register 24-16).
When PxARSEN is set, the PxASDE bit will clear
automatically when the source causing the Reset and
no longer asserts the shut-down condition.
When any of the selected external auto-shutdown
sources go high, the PxASE bit is set and an
auto-shutdown interrupt is generated.
The PSMC will restart on the next period event after
the auto-shutdown condition is removed.
Examples of manual and automatic restart are shown
in Figure 24-20.
Note: The external shutdown sources are level
sensitive, not edge sensitive. The shutdown
condition will persist as long as the circuit is
driving the appropriate logic level.
Note: Whether manual or auto-restart is selected,
the PxASDE bit cannot be cleared in
software when the auto-shutdown condition
is still present.
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FIGURE 24-20:
AUTO-SHUTDOWN AND RESTART WAVEFORM
1
2
3
4
5
Base PWM signal
PxARSEN
Next Period Event
Auto-Shutdown Source
cleared
in software
cleared
in software
PSMCx Auto-shutdown int flag bit
Cleared
in hardware
Next Period Event
PxASE
Cleared
in software
PSMCxA
PSMCxB
Normal
Output
Auto-
shutdown
Auto-
shutdown
Normal
Output
Normal
Output
Operating State
Manual Restart
Auto-restart
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24.8 PSMC Synchronization
It is possible to synchronize the periods of two or more
PSMC modules together, provided that all modules
are on the same device.
Synchronization is achieved by sending a sync signal
from the master PSMC module to the desired slave
modules. This sync signal generates a period event in
each slave module, thereby aligning all slaves with the
master. This is useful when an application requires
different PWM signal generation from each module but
the waveforms must be consistent within a PWM
period.
24.8.1
SYNCHRONIZATION SOURCES
The synchronization source can be any PSMC module
on the same device. For example, in a device with two
PSMC modules, the possible sources for each device
is as shown below:
• Sources for PSMC1
- PSMC2
• Sources for PSMC2
- PSMC1
24.8.1.1
PSMC Internal Connections
The sync signal from the master PSMC module is
essentially that modules period event trigger. The
slave PSMC modules reset their PSMCxTMR with the
sync signal instead of their own period event.
Enabling a module as a slave recipient is done with
the PxSYNC bits of the PSMC Synchronization
Control (PSMCxSYNC) registers; registers 24-3
and 24-4.
24.8.1.2
Synchronization Skid
When the sync_out source is the Period Event, the
slave synchronous rising and falling events will lag by
one psmc_clk period. When the sync_out source is the
Rising Event, the synchronous events will lag by two
clock periods. To compensate for this, the values in
PHH:PHL and DCH:DCL registers can be reduced by
the number of lag cycles.
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psmc_clk period (TPSMC_CLK) every N events, then
the effective resolution of the average event period is
TPSMC_CLK/N.
24.9 Fractional Frequency Adjust (FFA)
FFA is a method by which PWM resolution can be
improved on 50% fixed duty cycle signals. Higher
resolution is achieved by altering the PWM period by a
single count for calculated intervals. This increased
resolution is based upon the PWM frequency
averaged over a large number of PWM periods. For
example, if the period event time is increased by one
When active, after every period event the FFA
hardware adds the PSMCxFFA value with the
previously accumulated result. Each time the addition
causes an overflow, the period event time is increased
by one. Refer to Figure 24-21.
FIGURE 24-21:
FFA BLOCK DIAGRAM.
PSMCxPR<15:0>
PSMCxFFA<3:0>
carry
Comparator
Accumulator<3:0>
=
Period Event
PSMCxTMR<15:0>
psmc_clk
The FFA function is only available when using one of
the two Fixed Duty Cycle modes of operation. In fixed
duty cycle operation each PWM period is comprised of
two period events. That is why the PWM periods in
Table 24-3 example calculations are multiplied by two
as opposed to the normal period calculations for
normal mode operation.
TABLE 24-3: FRACTIONAL FREQUENCY
ADJUST CALCULATIONS
Parameter
Value
FPSMC_CLK
TPSMC_CLK
64 MHz
15.625 ns
PSMCxPR<15:0> 00FFh = 255
TPWM
= (PSMCxPR<15:0>+1)*2*TPSMC_CLK
= 256*2*15.625ns
= 8 us
The extra resolution gained by the FFA is based upon
the number of bits in the FFA register and the psmc_-
clk frequency. The parameters of interest are:
FPWM
125 kHz
• TPWM – this is the lower bound of the PWM period
that will be adjusted
TPWM+1
= (PSMCxPR<15:0>+2)*2*TPSMC_CLK
= 257*2*15.625ns
= 8.03125 us
• TPWM+1 – this is the upper bound of the PWM
period that will be adjusted. This is used to help
determine the step size for each increment of the
FFA register
FPWM+1
= 124.513 kHz
TRESOLUTION
= (TPWM+1-TPWM)/2FFA-Bits
= (8.03125us - 8.0 us)/16
= 0.03125us/16
~ 1.95 ns
(FPWM+1-FPWM)/2FFA-Bits
• TRESOLUTION – each increment of the FFA
register will add this amount of period to average
PWM frequency
FRESOLUTION
~ -30.4 Hz
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TABLE 24-4: SAMPLE FFA OUTPUT PERIODS/FREQUENCIES
FFA number
Output Frequency (kHz)
Step Size (Hz)
0
1
125.000
124.970
124.939
124.909
124.878
124.848
124.818
124.787
124.757
124.726
124.696
124.666
124.635
124.605
124.574
124.544
0
-30.4
2
-60.8
3
-91.2
4
-121.6
-152.0
-182.4
-212.8
-243.2
-273.6
-304.0
-334.4
-364.8
-395.2
-425.6
-456.0
5
6
7
8
9
10
11
12
13
14
15
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24.10 Register Updates
24.11 Operation During Sleep
There are 10 double-buffered registers that can be
updated “on the fly”. However, due to the
asynchronous nature of the potential updates, a
special hardware system is used for the updates.
The PSMC continues to operate in Sleep with the
following clock sources:
• Internal 64 MHz
• External clock
There are two operating cases for the PSMC:
• module is enabled
• module is disabled
24.10.1 DOUBLE BUFFERED REGISTERS
The double-buffered registers that are affected by the
special hardware update system are:
• PSMCxPRL
• PSMCxPRH
• PSMCxDCL
• PSMCxDCH
• PSMCxPHL
• PSMCxPHH
• PSMCxDBR
• PSMCxDBF
• PSMCxBLKR
• PSMCxBLKF
• PSMCxSTR0 (when the PxSSYNC bit is set)
24.10.2 MODULE DISABLED UPDATES
When the PSMC module is disabled (PSMCxEN = 0),
any write to one of the buffered registers will also write
directly to the buffer. This means that all buffers are
loaded and ready for use when the module is enabled.
24.10.3 MODULE ENABLED UPDATES
When the PSMC module is enabled (PSMCxEN = 1),
the PSMCxLD bit of the PSMC Control (PSMCxCON)
register (Register 24-1) must be used.
When the PSMCxLD bit is set, the transfer from the
register to the buffer occurs on the next period event.
The PSMCxLD bit is automatically cleared by hardware
after the transfer to the buffers is complete.
The reason that the PSMCxLD bit is required is that
depending on the customer application and operation
conditions, all 10 registers may not be updated in one
PSMC period. If the buffers are loaded at different
times (i.e., DCL gets updated, but DCH does not OR
DCL and DCL are updated by PRH and PRL are not),
then unintended operation may occur.
The sequence for loading the buffer registers when the
PSMC module is enabled is as follows:
1. Software updates all registers.
2. Software sets the PSMCxLD bit.
3. Hardware updates all buffers on the next period
event.
4. Hardware clears PSMCxLD bit.
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24.12 Register Definitions: PSMC Control
REGISTER 24-1: PSMCxCON: PSMC CONTROL REGISTER
R/W-0/0
R/W/HC-0/0
PSMCxLD
R/W-0/0
PxDBFE
R/W-0/0
PxDBRE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
PSMCxEN
PxMODE<3:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-0
PSMCxEN: PSMC Module Enable bit
1= PSMCx module is enabled
0= PSMCx module is disabled
PSMCxLD: PSMC Load Buffer Enable bit
1= PSMCx registers are ready to be updated with the appropriate register contents
0= PSMCx buffer update complete
PxDBFE: PSMC Falling Edge Dead-Band Enable bit
1= PSMCx falling edge dead band enabled
0= PSMCx falling edge dead band disabled
PxDBRE: PSMC Rising Edge Dead-Band Enable bit
1= PSMCx rising edge dead band enabled
0= PSMCx rising edge dead band disabled
PxMODE<3:0> PSMC Operating Mode bits
1111= Reserved
1110= Reserved
1101= Reserved
1100= 3-phase steering PWM
1011= Fixed duty cycle, variable frequency, complementary PWM
1010= Fixed duty cycle, variable frequency, single PWM
1001= ECCP compatible Full-Bridge forward output
1000= ECCP compatible Full-Bridge reverse output
0111= Pulse-skipping with complementary output
0110= Pulse-skipping PWM output
0101= Push-pull with four full-bridge outputs and complementary outputs
0100= Push-pull with four full-bridge outputs
0011= Push-pull with complementary outputs
0010= Push-pull output
0001= Single PWM with complementary output (with PWM steering capability)
0000= Single PWM waveform generation (with PWM steering capability)
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REGISTER 24-2: PSMCxMDL: PSMC MODULATION CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxMDLEN
PxMDLPOL PxMDLBIT
PxMSRC<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
PxMDLEN: PSMC Periodic Modulation Mode Enable bit
1= PSMCx is active when input signal selected by PxMSRC<3:0> is in its active state (see PxMPOL)
0= PSMCx module is always active
PxMDLPOL: PSMC Periodic Modulation Polarity bit
1= PSMCx is active when the PSMCx Modulation source output equals logic ‘0’ (active-low)
0= PSMCx is active when the PSMCx Modulation source output equals logic ‘1’ (active-high)
PxMDLBIT: PSMC Periodic Modulation Software Control bit
PxMDLEN = 1AND PxMSRC<3:0> = 0000
1= PSMCx is active when the PxMDLPOL equals logic ‘0’
0= PSMCx is active when the PxMDLPOL equals logic ‘1’
PxMDLEN = 0OR (PxMDLEN = 1and PxMSRC<3:0> <> ‘0000’)
Does not affect module operation
bit 4
Unimplemented: Read as ‘0’
bit 3-0
PxMSRC<3:0> PSMC Periodic Modulation Source Selection bits
1111= Reserved
1110= Reserved
1101= Reserved
1100= Reserved
1011= Reserved
1010= Reserved
1001= Reserved
1000= PSMCx Modulation Source is PSMCxIN pin
0111= Reserved
0110= PSMCx Modulation Source is CCP2
0101= PSMCx Modulation Source is CCP1
0100= Reserved
0011= PSMCx Modulation Source is sync_C3OUT
0010= PSMCx Modulation Source is sync_C2OUT
0001= PSMCx Modulation Source is sync_C1OUT
0000= PSMCx Modulation Source is PxMDLBIT register bit
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REGISTER 24-3: PSMC1SYNC: PSMC1 SYNCHRONIZATION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
P1SYNC<1:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
P1SYNC<1:0>: PSMC1 Period Synchronization Mode bits
11= Reserved – Do not use
10= PSMC1 is synchronized with the PSMC2 module
01= Reserved – Do not use
00= PSMC1 is synchronized with period event
REGISTER 24-4: PSMC2SYNC: PSMC2 SYNCHRONIZATION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
P2SYNC<1:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
P2SYNC<1:0>: PSMC2 Period Synchronization Mode bits
11= Reserved – Do not use
10= Reserved – Do not use
01= PSMC2 is synchronized with the PSMC1 module
00= PSMC2 is synchronized with period event
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REGISTER 24-5: PSMCxCLK: PSMC CLOCK CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
PxCPRE<1:0>
PxCSRC<1:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
PxCPRE<1:0>: PSMCx Clock Prescaler Selection bits
11= PSMCx Clock frequency/8
10= PSMCx Clock frequency/4
01= PSMCx Clock frequency/2
00= PSMCx Clock frequency/1
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
PxCSRC<1:0>: PSMCx Clock Source Selection bits
11= Reserved
10= PSMCxCLK pin
01= 64 MHz clock in from PLL
00= FOSC system clock
REGISTER 24-6: PSMCxOEN: PSMC OUTPUT ENABLE CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
PxOEF(1)
R/W-0/0
PxOEE(1)
R/W-0/0
PxOED(1)
R/W-0/0
PxOEC(1)
R/W-0/0
PxOEB
R/W-0/0
PxOEA
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
PxOEy: PSMCx Output y Enable bit(1)
1= PWM output is active on PSMCx output y pin
0= PWM output is not active, normal port functions in control of pin
Note 1: These bits are not implemented on PSMC2.
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REGISTER 24-7:
PSMCxPOL: PSMC POLARITY CONTROL REGISTER
U-0
R/W-0/0
PxPOLIN
R/W-0/0
PxPOLF(1)
R/W-0/0
PxPOLE(1) PxPOLD(1)
R/W-0/0
R/W-0/0
PxPOLC(1)
R/W-0/0
PxPOLB
R/W-0/0
PxPOLA
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
Unimplemented: Read as ‘0’
PxPOLIN: PSMCxIN Polarity bit
1= PSMCxIN input is active-low
0= PSMCxIN input is active-high
bit 5-0
PxPOLy: PSMCx Output y Polarity bit(1)
1= PWM PSMCx output y is active-low
0= PWM PSMCx output y is active-high
Note 1: These bits are not implemented on PSMC2.
REGISTER 24-8: PSMCxBLNK: PSMC BLANKING CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
PxFEBM1
PxFEBM0
PxREBM1
PxREBM0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
PxFEBM<1:0> PSMC Falling Edge Blanking Mode bits
11= Reserved – do not use
10= Reserved – do not use
01= Immediate blanking
00= No blanking
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
PxREBM<1:0> PSMC Rising Edge Blanking Mode bits
11= Reserved – do not use
10= Reserved – do not use
01= Immediate blanking
00= No blanking
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REGISTER 24-9: PSMCxREBS: PSMC RISING EDGE BLANKED SOURCE REGISTER
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
PxREBSIN
PxREBSC3
PxREBSC2
PxREBSC1
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PxREBSIN: PSMCx Rising Edge Event Blanked from PSMCxIN pin
1= PSMCxIN pin cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register
0= PSMCxIN pin is not blanked
bit 6-4
bit 3
Unimplemented: Read as ‘0’
PxREBSC3: PSMCx Rising Edge Event Blanked from sync_C3OUT
1= sync_C3OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register
0 = sync_C3OUT is not blanked
bit 2
bit 1
bit 0
PxREBSC2: PSMCx Rising Edge Event Blanked from sync_C2OUT
1= sync_C2OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register
0 = sync_C2OUT is not blanked
PxREBSC1: PSMCx Rising Edge Event Blanked from sync_C1OUT
1= sync_C1OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register
0 = sync_C1OUT is not blanked
Unimplemented: Read as ‘0’
REGISTER 24-10: PSMCxFEBS: PSMC FALLING EDGE BLANKED SOURCE REGISTER
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
PxFEBSIN
PxFEBSC3
PxFEBSC2
PxFEBSC1
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PxFEBSIN: PSMCx Falling Edge Event Blanked from PSMCxIN pin
1= PSMCxIN pin cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register
0= PSMCxIN pin is not blanked
bit 6-4
bit 3
Unimplemented: Read as ‘0’
PxFEBSC3: PSMCx Falling Edge Event Blanked from sync_C3OUT
1= sync_C3OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register
0= sync_C3OUT is not blanked
bit 2
bit 1
bit 0
PxFEBSC2: PSMCx Falling Edge Event Blanked from sync_C2OUT
1= sync_C2OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register
0= sync_C2OUT is not blanked
PxFEBSC1: PSMCx Falling Edge Event Blanked from sync_C1OUT
1= sync_C1OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register
0= sync_C1OUT is not blanked
Unimplemented: Read as ‘0’
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REGISTER 24-11: PSMCxPHS: PSMC PHASE SOURCE REGISTER(1)
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxPHST
PxPHSIN
PxPHSC3
PxPHSC2
PxPHSC1
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PxPHSIN: PSMCx Rising Edge Event occurs on PSMCxIN pin
1= Rising edge event will occur when PSMCxIN pin goes true
0 = PSMCxIN pin will not cause rising edge event
bit 6-4
bit 3
Unimplemented: Read as ‘0’
PxPHSC3: PSMCx Rising Edge Event occurs on sync_C3OUT output
1= Rising edge event will occur when sync_C3OUT output goes true
0 = sync_C3OUT will not cause rising edge event
bit 2
bit 1
bit 0
PxPHSC2: PSMCx Rising Edge Event occurs on sync_C2OUT output
1= Rising edge event will occur when sync_C2OUT output goes true
0 = sync_C2OUT will not cause rising edge event
PxPHSC1: PSMCx Rising Edge Event occurs on sync_C1OUT output
1= Rising edge event will occur when sync_C1OUT output goes true
0 = sync_C1OUT will not cause rising edge event
PxPHST: PSMCx Rising Edge Event occurs on Time Base match
1= Rising edge event will occur when PSMCxTMR = PSMCxPH
0 = Time base will not cause rising edge event
Note 1: Sources are not mutually exclusive: more than one source can cause a rising edge event.
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REGISTER 24-12: PSMCxDCS: PSMC DUTY CYCLE SOURCE REGISTER(1)
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxDCST
PxDCSIN
PxDCSC3
PxDCSC2
PxDCSC1
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PxDCSIN: PSMCx Falling Edge Event occurs on PSMCxIN pin
1= Falling edge event will occur when PSMCxIN pin goes true
0= PSMCxIN pin will not cause falling edge event
bit 6-4
bit 3
Unimplemented: Read as ‘0’
PxDCSC3: PSMCx Falling Edge Event occurs on sync_C3OUT output
1= Falling edge event will occur when sync_C3OUT output goes true
0= sync_C3OUT will not cause falling edge event
bit 2
bit 1
bit 0
PxDCSC2: PSMCx Falling Edge Event occurs on sync_C2OUT output
1= Falling edge event will occur when sync_C2OUT output goes true
0= sync_C2OUT will not cause falling edge event
PxDCSC1: PSMCx Falling Edge Event occurs on sync_C1OUT output
1= Falling edge event will occur when sync_C1OUT output goes true
0= sync_C1OUT will not cause falling edge event
PxDCST: PSMCx Falling Edge Event occurs on Time Base match
1= Falling edge event will occur when PSMCxTMR = PSMCxDC
0= Time base will not cause falling edge event
Note 1: Sources are not mutually exclusive: more than one source can cause a falling edge event.
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REGISTER 24-13: PSMCxPRS: PSMC PERIOD SOURCE REGISTER(1)
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxPRST
PxPRSIN
PxPRSC3
PxPRSC2
PxPRSC1
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PxPRSIN: PSMCx Period Event occurs on PSMCxIN pin
1= Period event will occur and PSMCxTMR will reset when PSMCxIN pin goes true
0 = PSMCxIN pin will not cause period event
bit 6-4
bit 3
Unimplemented: Read as ‘0’
PxPRSC3: PSMCx Period Event occurs on sync_C3OUT output
1= Period event will occur and PSMCxTMR will reset when sync_C3OUT output goes true
0= sync_C3OUT will not cause period event
bit 2
bit 1
bit 0
PxPRSC2: PSMCx Period Event occurs on sync_C2OUT output
1= Period event will occur and PSMCxTMR will reset when sync_C2OUT output goes true
0= sync_C2OUT will not cause period event
PxPRSC1: PSMCx Period Event occurs on sync_C1OUT output
1= Period event will occur and PSMCxTMR will reset when sync_C1OUT output goes true
0= sync_C1OUT will not cause period event
PxPRST: PSMCx Period Event occurs on Time Base match
1= Period event will occur and PSMCxTMR will reset when PSMCxTMR = PSMCxPR
0= Time base will not cause period event
Note 1: Sources are not mutually exclusive: more than one source can force the period event and reset the
PSMCxTMR.
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REGISTER 24-14: PSMCxASDC: PSMC AUTO-SHUTDOWN CONTROL REGISTER
R/W-0/0
PxASE
R/W-0/0
R/W-0/0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
PxASDEN
PxARSEN
PxASDOV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
PxASE: PWM Auto-Shutdown Event Status bit(1)
1= A shutdown event has occurred, PWM outputs are inactive and in their shutdown states
0= PWM outputs are operating normally
PxASDEN: PWM Auto-Shutdown Enable bit
1= Auto-shutdown is enabled. If any of the sources in PSMCxASDS assert a logic ‘1’, then the out-
puts will go into their auto-shutdown state and PSMCxSIF flag will be set.
0= Auto-shutdown is disabled
bit 5
PxARSEN: PWM Auto-Restart Enable bit
1= PWM restarts automatically when the shutdown condition is removed.
0= The PxASE bit must be cleared in firmware to restart PWM after the auto-shutdown condition is
cleared.
bit 4-1
bit 0
Unimplemented: Read as ‘0’
PxASDOV: PWM Auto-Shutdown Override bit
PxASDEN = 1:
1= Force PxASDL[n] levels on the PSMCx[n] pins without causing a PSMCxSIF interrupt
0= Normal PWM and auto-shutdown execution
PxASDEN = 0:
No effect
Note 1: PASE bit may be set in software. When this occurs the functionality is the same as that caused by
hardware.
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REGISTER 24-15: PSMCxASDL: PSMC AUTO-SHUTDOWN OUTPUT LEVEL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxASDLF(1) PxASDLE(1) PxASDLD(1) PxASDLC(1)
PxASDLB
PxASDLA
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
Unimplemented: Read as ‘0’
PxASDLF: PSMCx Output F Auto-Shutdown Pin Level bit(1)
1= When auto-shutdown is asserted, pin PSMCxF will drive logic ‘1’
0= When auto-shutdown is asserted, pin PSMCxF will drive logic ‘0’
bit 4
bit 3
bit 2
bit 1
bit 0
PxASDLE: PSMCx Output E Auto-Shutdown Pin Level bit(1)
1= When auto-shutdown is asserted, pin PSMCxE will drive logic ‘1’
0= When auto-shutdown is asserted, pin PSMCxE will drive logic ‘0’
PxASDLD: PSMCx Output D Auto-Shutdown Pin Level bit(1)
1= When auto-shutdown is asserted, pin PSMCxD will drive logic ‘1’
0= When auto-shutdown is asserted, pin PSMCxD will drive logic ‘0’
PxASDLC: PSMCx Output C Auto-Shutdown Pin Level bit(1)
1= When auto-shutdown is asserted, pin PSMCxC will drive logic ‘1’
0= When auto-shutdown is asserted, pin PSMCxC will drive logic ‘0’
PxASDLB: PSMCx Output B Auto-Shutdown Pin Level bit
1= When auto-shutdown is asserted, pin PSMCxB will drive logic ‘1’
0= When auto-shutdown is asserted, pin PSMCxB will drive logic ‘0’
PxASDLA: PSMCx Output A Auto-Shutdown Pin Level bit
1= When auto-shutdown is asserted, pin PSMCxA will drive logic ‘1’
0= When auto-shutdown is asserted, pin PSMCxA will drive logic ‘0’
Note 1: These bits are not implemented on PSMC2.
2011-2014 Microchip Technology Inc.
DS40001579E-page 233
PIC16(L)F1782/3
REGISTER 24-16: PSMCxASDS: PSMC AUTO-SHUTDOWN SOURCE REGISTER
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
PxASDSIN
PxASDSC3
PxASDSC2
PxASDSC1
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PxASDSIN: Auto-shutdown occurs on PSMCxIN pin
1= Auto-shutdown will occur when PSMCxIN pin goes true
0= PSMCxIN pin will not cause auto-shutdown
bit 6-4
bit 3
Unimplemented: Read as ‘0’
PxASDSC3: Auto-shutdown occurs on sync_C3OUT output
1= Auto-shutdown will occur when sync_C3OUT output goes true
0= sync_C3OUT will not cause auto-shutdown
bit 2
bit 1
bit 0
PxASDSC2: Auto-shutdown occurs on sync_C2OUT output
1= Auto-shutdown will occur when sync_C2OUT output goes true
0= sync_C2OUT will not cause auto-shutdown
PxASDSC1: Auto-shutdown occurs on sync_C1OUT output
1= Auto-shutdown will occur when sync_C1OU output goes true
0= sync_C1OU will not cause auto-shutdown
Unimplemented: Read as ‘0’
DS40001579E-page 234
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
REGISTER 24-17: PSMCxTMRL: PSMC TIME BASE COUNTER LOW REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
PSMCxTMRL<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxTMRL<7:0>: 16-bit PSMCx Time Base Counter Least Significant bits
= PSMCxTMR<7:0>
REGISTER 24-18: PSMCxTMRH: PSMC TIME BASE COUNTER HIGH REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
PSMCxTMRH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxTMRH<7:0>: 16-bit PSMCx Time Base Counter Most Significant bits
= PSMCxTMR<15:8>
2011-2014 Microchip Technology Inc.
DS40001579E-page 235
PIC16(L)F1782/3
REGISTER 24-19: PSMCxPHL: PSMC PHASE COUNT LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxPHL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
PSMCxPHL<7:0>: 16-bit Phase Count Least Significant bits
PSMCxPH<7:0>
=
REGISTER 24-20: PSMCxPHH: PSMC PHASE COUNT HIGH BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxPHH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxPHH<7:0>: 16-bit Phase Count Most Significant bits
PSMCxPH<15:8>
=
DS40001579E-page 236
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
REGISTER 24-21: PSMCxDCL: PSMC DUTY CYCLE COUNT LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxDCL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxDCL<7:0>: 16-bit Duty Cycle Count Least Significant bits
PSMCxDC<7:0>
=
REGISTER 24-22: PSMCxDCH: PSMC DUTY CYCLE COUNT HIGH REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxDCH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxDCH<7:0>: 16-bit Duty Cycle Count Most Significant bits
PSMCxDC<15:8>
=
2011-2014 Microchip Technology Inc.
DS40001579E-page 237
PIC16(L)F1782/3
REGISTER 24-23: PSMCxPRL: PSMC PERIOD COUNT LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxPRL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
PSMCxPRL<7:0>: 16-bit Period Time Least Significant bits
PSMCxPR<7:0>
=
REGISTER 24-24: PSMCxPRH: PSMC PERIOD COUNT HIGH BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxPRH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxPRH<7:0>: 16-bit Period Time Most Significant bits
PSMCxPR<15:8>
=
DS40001579E-page 238
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
REGISTER 24-25: PSMCxDBR: PSMC RISING EDGE DEAD-BAND TIME REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxDBR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxDBR<7:0>: Rising Edge Dead-Band Time bits
= Unsigned number of PSMCx psmc_clk clock periods in rising edge dead band
REGISTER 24-26: PSMCxDBF: PSMC FALLING EDGE DEAD-BAND TIME REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxDBF<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxDBF<7:0>: Falling Edge Dead-Band Time bits
Unsigned number of PSMCx psmc_clk clock periods in falling edge dead band
=
REGISTER 24-27: PSMCxFFA: PSMC FRACTIONAL FREQUENCY ADJUST REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxFFA<3:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
PSMCxFFA<3:0>: Fractional Frequency Adjustment bits
=
Unsigned number of fractional PSMCx psmc_clk clock periods to add to each period event time.
The fractional time period = 1/(16*psmc_clk)
2011-2014 Microchip Technology Inc.
DS40001579E-page 239
PIC16(L)F1782/3
REGISTER 24-28: PSMCxBLKR: PSMC RISING EDGE BLANKING TIME REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxBLKR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxBLKR<7:0>: Rising Edge Blanking Time bits
Unsigned number of PSMCx psmc_clk clock periods in rising edge blanking
=
REGISTER 24-29: PSMCxBLKF: PSMC FALLING EDGE BLANKING TIME REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PSMCxBLKF<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
PSMCxBLKF<7:0>: Falling Edge Blanking Time bits
Unsigned number of PSMCx psmc_clk clock periods in falling edge blanking
=
DS40001579E-page 240
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
REGISTER 24-30: PSMCxSTR0: PSMC STEERING CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0/0
PxSTRF(2)
R/W-0/0
PxSTRE(2) PxSTRD(2)
R/W-0/0
R/W-0/0
PxSTRC(2)
R/W-0/0
PxSTRB
R/W-1/1
PxSTRA
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
Unimplemented: Read as ‘0’
PxSTRF: PWM Steering PSMCxF Output Enable bit(2)
If PxMODE<3:0> = 0000 (Single-phase PWM):
1= Single PWM output is active on pin PSMCxF
0= Single PWM output is not active on pin PSMCxF. PWM drive is in inactive state
If PxMODE<3:0> = 0001 (Complementary Single-phase PWM):
1= Complementary PWM output is active on pin PSMCxF
0= Complementary PWM output is not active on pin PSMCxOUT5. PWM drive is in inactive state
IF PxMODE<3:0> = 1100 (3-phase Steering):(1)
1= PSMCxD and PSMCxE are high. PSMCxA, PMSCxB, PSMCxC and PMSCxF are low.
0= 3-phase output combination is not active
bit 4
PxSTRE: PWM Steering PSMCxE Output Enable bit(2)
If PxMODE<3:0> = 000x (single-phase PWM or Complementary PWM):
1= Single PWM output is active on pin PSMCxE
0= Single PWM output is not active on pin PSMCxE. PWM drive is in inactive state
IF PxMODE<3:0> = 1100 (3-phase Steering):(1)
1= PSMCxB and PSMCxE are high. PSMCxA, PMSCxC, PSMCxD and PMSCxF are low.
0= 3-phase output combination is not active
bit 3
PxSTRD: PWM Steering PSMCxD Output Enable bit(2)
If PxMODE<3:0> = 0000 (Single-phase PWM):
1= Single PWM output is active on pin PSMCxD
0= Single PWM output is not active on pin PSMCxD. PWM drive is in inactive state
If PxMODE<3:0> = 0001 (Complementary single-phase PWM):
1= Complementary PWM output is active on pin PSMCxD
0= Complementary PWM output is not active on pin PSMCxD. PWM drive is in inactive state
IF PxMODE<3:0> = 1100 (3-phase Steering):(1)
1= PSMCxB and PSMCxC are high. PSMCxA, PMSCxD, PSMCxE and PMSCxF are low.
0= 3-phase output combination is not active
bit 2
PxSTRC: PWM Steering PSMCxC Output Enable bit(2)
If PxMODE<3:0> = 000x (Single-phase PWM or Complementary PWM):
1= Single PWM output is active on pin PSMCxC
0= Single PWM output is not active on pin PSMCxC. PWM drive is in inactive state
IF PxMODE<3:0> = 1100 (3-phase Steering):(1)
1= PSMCxC and PSMCxF are high. PSMCxA, PMSCxB, PSMCxD and PMSCxE are low.
0= 3-phase output combination is not active
2011-2014 Microchip Technology Inc.
DS40001579E-page 241
PIC16(L)F1782/3
REGISTER 24-30: PSMCxSTR0: PSMC STEERING CONTROL REGISTER 0
bit 1
PxSTRB: PWM Steering PSMCxB Output Enable bit
If PxMODE<3:0> = 0000 (Single-phase PWM):
1= Single PWM output is active on pin PSMCxOUT1
0= Single PWM output is not active on pin PSMCxOUT1. PWM drive is in inactive state
If PxMODE<3:0> = 0001 (Complementary Single-phase PWM):
1= Complementary PWM output is active on pin PSMCxB
0= Complementary PWM output is not active on pin PSMCxB. PWM drive is in inactive state
IF PxMODE<3:0> = 1100 (3-phase Steering):(1)
1= PSMCxA and PSMCxF are high. PSMCxB, PMSCxC, PSMCxD and PMSCxE are low.
0= 3-phase output combination is not active
bit 0
PxSTRA: PWM Steering PSMCxA Output Enable bit
If PxMODE<3:0> = 000x (Single-phase PWM or Complementary PWM):
1= Single PWM output is active on pin PSMCxA
0= Single PWM output is not active on pin PSMCxA. PWM drive is in inactive state
IF PxMODE<3:0> = 1100 (3-phase Steering):(1)
1= PSMCxA and PSMCxD are high. PSMCxB, PMSCxC, PSMCxE and PMSCxF are low.
0= 3-phase output combination is not active
Note 1: In 3-phase Steering mode, only one PSTRx bit should be set at a time. If more than one is set, then the
lowest bit number steering combination has precedence.
2: These bits are not implemented on PSMC2.
DS40001579E-page 242
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
REGISTER 24-31: PSMCxSTR1: PSMC STEERING CONTROL REGISTER 1
R/W-0/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
PxSSYNC
PxLSMEN
PxHSMEN
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
PxSSYNC: PWM Steering Synchronization bit
1= PWM outputs are updated on period boundary
0= PWM outputs are updated immediately
bit 6-2
bit 1
Unimplemented: Read as ‘0’
PxLSMEN: 3-Phase Steering Low Side Modulation Enable bit
PxMODE = 1100:
1= Low side driver PSMCxB, PSMCxD and PSMCxF outputs are modulated according to
PSMCxMDL when the output is high and driven low without modulation when the output is low.
0= PSMCxB, PSMCxD, and PSMCxF outputs are driven high and low by PSMCxSTR0 control
without modulation.
PxMODE <> 1100:
No effect on output
bit 0
PxHSMEN: 3-Phase Steering High Side Modulation Enable bit
PxMODE = 1100:
1= High side driver PSMCxA, PSMCxC and PSMCxE outputs are modulated according to
PSMCxMDL when the output is high and driven low without modulation when the output is low.
0= PSMCxA, PSMCxC and PSMCxE outputs are driven high and low by PSMCxSTR0 control
without modulation.
PxMODE <> 1100:
No effect on output
2011-2014 Microchip Technology Inc.
DS40001579E-page 243
PIC16(L)F1782/3
REGISTER 24-32: PSMCxINT: PSMC TIME BASE INTERRUPT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxTOVIE
PxTPHIE
PxTDCIE
PxTPRIE
PxTOVIF
PxTPHIF
PxTDCIF
PxTPRIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PxTOVIE: PSMC Time Base Counter Overflow Interrupt Enable bit
1= Time base counter overflow interrupts are enabled
0= Time base counter overflow interrupts are disabled
PxTPHIE: PSMC Time Base Phase Interrupt Enable bit
1= Time base phase match interrupts are enabled
0= Time base phase match interrupts are disabled
PxTDCIE: PSMC Time Base Duty Cycle Interrupt Enable bit
1= Time base duty cycle match interrupts are enabled
0= Time base duty cycle match interrupts are disabled
PxTPRIE: PSMC Time Base Period Interrupt Enable bit
1= Time base period match interrupts are enabled
0= Time base period match Interrupts are disabled
PxTOVIF: PSMC Time Base Counter Overflow Interrupt Flag bit
1= The 16-bit PSMCxTMR has overflowed from FFFFh to 0000h
0= The 16-bit PSMCxTMR counter has not overflowed
PxTPHIF: PSMC Time Base Phase Interrupt Flag bit
1= The 16-bit PSMCxTMR counter has matched PSMCxPH<15:0>
0= The 16-bit PSMCxTMR counter has not matched PSMCxPH<15:0>
PxTDCIF: PSMC Time Base Duty Cycle Interrupt Flag bit
1= The 16-bit PSMCxTMR counter has matched PSMCxDC<15:0>
0= The 16-bit PSMCxTMR counter has not matched PSMCxDC<15:0>
PxTPRIF: PSMC Time Base Period Interrupt Flag bit
1= The 16-bit PSMCxTMR counter has matched PSMCxPR<15:0>
0= The 16-bit PSMCxTMR counter has not matched PSMCxPR<15:0>
DS40001579E-page 244
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 24-5: SUMMARY OF REGISTERS ASSOCIATED WITH PSMC
Register
on Page
Name
INTCON
Bit7
Bit6
Bit5
Bit4
BIt3
Bit2
Bit1
Bit0
GIE
ODC7
—
PEIE
TMR0IE
ODC5
INTE
IOCIE
ODC3
—
TMR0IF
ODC2
—
INTF
IOCIF
ODC0
79
ODCONC
ODC6
ODC4
ODC1
126
82
PIE4
—
PSMC2TIE PSMC1TIE
PSMC2SIE PSMC1SIE
PSMC2SIF PSMC1SIF
PIR4
—
—
PxASDEN
—
PSMC2TIF
PxARSEN
PSMC1TIF
—
—
—
85
PSMCxASDC
PSMCxASDL
PSMCxASDS
PSMCxBLKF
PSMCxBLKR
PSMCxBLNK
PSMCxCLK
PSMCxCON
PSMCxDBF
PSMCxDBR
PSMCxDCH
PSMCxDCL
PSMCxDCS
PSMCxFEBS
PSMCxFFA
PSMCxINT
PSMCxMDL
PSMCxOEN
PSMCxPHH
PSMCxPHL
PSMCxPHS
PSMCxPOL
PSMCxPRH
PSMCxPRL
PSMCxPRS
PSMCxREBS
PSMCxSTR0
PSMCxSTR1
PSMCxSYNC
PSMCxTMRH
PSMCxTMRL
SLRCONC
TRISC
PxASE
—
—
—
—
PxASDOV
PxASDLA
—
232
233
234
240
240
227
226
223
239
239
237
237
230
228
239
244
224
226
236
236
229
227
238
238
231
228
241
243
225
235
235
126
125
(1)
(1)
(1)
(1)
PxASDLF
—
PxASDLE
—
PxASDLD
PxASDLC
PxASDLB
PxASDSIN
—
PxASDSC3 PxASDSC2 PxASDSC1
PSMCxBLKF<7:0>
PSMCxBLKR<7:0>
—
—
—
—
PxFEBM1
PxFEBM0
—
—
—
—
PxREBM1
PxREBM0
PxCPRE<1:0>
PxCSRC<1:0>
PSMCxEN
PSMCxLD
PxDBFE
PxDBRE
PxMODE<3:0>
PSMCxDBF<7:0>
PSMCxDBR<7:0>
PSMCxDC<15:8>
PSMCxDC<7:0>
PxDCSIN
PxFEBSIN
—
—
—
—
—
—
—
PxDCSC3
PxDCSC2
PxDCSC1
PxDCST
—
PxFEBSC3 PxFEBSC2 PxFEBSC1
PSMCxFFA<3:0>
—
—
—
PxTOVIE
PxTPHIE
PxTDCIE
PxTPRIE
—
PxTOVIF
PxTPHIF
PxTDCIF
PxTPRIF
PxOEA
PxMDLEN PxMDLPOL PxMDLBIT
PxMSRC<3:0>
(1)
(1)
(1)
(1)
—
—
PxOEF
PxOEE
PxOED
PxOEC
PxOEB
PSMCxPH<15:8>
PSMCxPH<7:0>
PxPHSIN
—
—
—
—
PxPHSC3
PxPHSC2
PxPHSC1
PxPOLB
PxPHST
PxPOLA
(1)
(1)
(1)
(1)
PxPOLIN
PxPOLF
PxPOLE
PxPOLD
PxPOLC
PSMCxPR<15:8>
PSMCxPR<7:0>
PxPRSIN
PxREBSIN
—
—
—
—
—
—
—
—
—
—
PxPRSC3
PxPRSC2
PxPRSC1
PxPRST
—
PxREBSC3 PxREBSC2 PxREBSC1
(1)
(1)
(1)
(1)
PxSTRF
—
PxSTRE
—
PxSTRD
PxSTRC
PxSTRB
PxSTRA
PxHSMEN
PxSSYNC
—
—
—
—
—
PxLSMEN
—
—
PxSYNC<1:0>
PSMCxTMR<15:8>
PSMCxTMR<7:0>
SLRC7
SLRC6
TRISC6
SLRC5
SLRC4
SLRC3
TRISC3
SLCR2
TRISC2
SRC1
SLRC0
TRISC7
TRISC5
TRISC4
TRISC1
TRISC0
Legend:
Note 1:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PSMC module.
Unimplemented in PSMC2.
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25.0 CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
that allows the user to time and control different events,
and to generate Pulse-Width Modulation (PWM)
signals. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate Pulse-Width Modulated signals of
varying frequency and duty cycle.
This family of devices contains two standard
Capture/Compare/PWM modules (CCP1 and CCP2).
The Capture and Compare functions are identical for all
CCP modules.
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout
this
section,
generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to CCPx module.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.
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25.1.2
TIMER1 MODE RESOURCE
25.1 Capture Mode
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
The Capture mode function described in this section is
available and identical for all CCP modules.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
See Section 22.0 “Timer1 Module with Gate
Control” for more information on configuring Timer1.
25.1.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in Operating mode.
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
Figure 25-1 shows a simplified diagram of the capture
operation.
25.1.4
CCP PRESCALER
25.1.1
CCP PIN CONFIGURATION
There are four prescaler settings specified by the
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCP2 pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 13.1 “Alternate Pin Function” for more
details.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler. Equation 25-1 demonstrates the code to
perform this function.
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 25-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
EXAMPLE 25-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSELCCPxCON
;Set Bank bits to point
;to CCPxCON
;Turn CCP module off
Set Flag bit CCPxIF
(PIRx register)
Prescaler
1, 4, 16
CLRF
CCPxCON
MOVLW
NEW_CAPT_PS;Load the W reg with
;the new prescaler
CCPx
pin
CCPRxH
CCPRxL
;move value and CCP ON
Capture
Enable
MOVWF
CCPxCON
;Load CCPxCON with this
;value
and
Edge Detect
TMR1H
TMR1L
CCPxM<3:0>
System Clock (FOSC)
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25.1.5
CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
25.1.6
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 13.1 “Alternate Pin Function” for
more information.
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See Section 22.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
25.2 Compare Mode
The Compare mode function described in this section
is available and identical for all CCP modules.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCPx output
25.2.3
SOFTWARE INTERRUPT MODE
• Set the CCPx output
• Clear the CCPx output
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
• Generate an Auto-conversion Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
25.2.4
AUTO-CONVERSION TRIGGER
When Auto-conversion Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
All Compare modes can generate an interrupt.
Figure 25-2 shows a simplified diagram of the compare
operation.
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
FIGURE 25-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
The CCPx module does not assert control of the CCPx
pin in this mode.
The Auto-conversion Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. The
Auto-conversion Trigger output starts an ADC conver-
sion (if the ADC module is enabled). This allows the
CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1.
CCPxM<3:0>
Mode Select
Set CCPxIF Interrupt Flag
(PIRx)
4
CCPx
Pin
CCPRxH CCPRxL
Comparator
Q
S
R
Output
Logic
Match
TMR1H TMR1L
Refer to Section 17.2.5 “Auto-Conversion Trigger”
for more information.
TRIS
Output Enable
Auto-conversion Trigger
Note 1: The Auto-conversion Trigger from the
CCP module does not set interrupt flag
bit TMR1IF of the PIR1 register.
25.2.1
CCPX PIN CONFIGURATION
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
clock
edge that
generates
the
The CCP2 pin function can be moved to alternate pins
using the APFCON register (Register 13-1). Refer to
Section 13.1 “Alternate Pin Function” for more
details.
Auto-conversion Trigger and the clock
edge that generates the Timer1 Reset,
will preclude the Reset from occurring.
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
25.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
25.2.2
TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
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25.2.6
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 13.1 “Alternate Pin Function”for
more information.
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FIGURE 25-3:
CCP PWM OUTPUT SIGNAL
25.3 PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPRxH:CCPxCON<5:4>
TMR2 = 0
FIGURE 25-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
To PSMC module
CCP1
CCPR1H(2) (Slave)
Comparator
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
R
S
Q
(1)
TMR2
TRIS
Figure 25-3 shows a typical waveform of the PWM
signal.
Comparator
PR2
Clear Timer,
toggle CCP1 pin and
latch duty cycle
25.3.1
STANDARD PWM OPERATION
The standard PWM function described in this section is
available and identical for all CCP modules.
Note 1: The 8-bit timer TMR2 register is
concatenated with the 2-bit internal system
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
clock (FOSC), or 2 bits of the prescaler, to
create the 10-bit time base.
2: In PWM mode, CCPR1H is a read-only
register.
• PR2 registers
• T2CON registers
• CCPRxL registers
• CCPxCON registers
Figure 25-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.
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25.3.2
SETUP FOR PWM OPERATION
25.3.4
PWM PERIOD
The following steps should be taken when configuring
the CCP module for standard PWM operation:
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 25-1.
1. Disable the CCPx pin output driver by setting the
associated TRIS bit.
EQUATION 25-1: PWM PERIOD
2. Load the PR2 register with the PWM period
value.
PWM Period = PR2 + 1 4 TOSC
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
(TMR2 Prescale Value)
Note 1: TOSC = 1/FOSC
4. Load the CCPRxL register and the DCxBx bits
of the CCPxCON register, with the PWM duty
cycle value.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
5. Configure and start Timer2:
• TMR2 is cleared
• Clear the TMR2IF interrupt flag bit of the
PIRx register. See Note below.
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• Configure the T2CKPS bits of the T2CON
register with the Timer prescale value.
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
• Enable the Timer by setting the TMR2ON
bit of the T2CON register.
Note:
The Timer postscaler (see Section 23.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
6. Enable PWM output pin:
• Wait until the Timer overflows and the
TMR2IF bit of the PIR1 register is set. See
Note below.
25.3.5
PWM DUTY CYCLE
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPRxH
register is read-only.
Note:
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
25.3.3
TIMER2 TIMER RESOURCE
Equation 25-2 is used to calculate the PWM pulse
width.
The PWM standard mode makes use of the 8-bit
Timer2 timer resources to specify the PWM period.
Equation 25-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 25-2: PULSE WIDTH
Pulse Width = CCPRxL:CCPxCON<5:4>
TOSC (TMR2 Prescale Value)
EQUATION 25-3: DUTY CYCLE RATIO
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = ----------------------------------------------------------------------
4PR2 + 1
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
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The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 25-4.
EQUATION 25-4: PWM RESOLUTION
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 25-4).
log4PR2 + 1
Resolution = ----------------------------------------- bits
log2
25.3.6
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 25-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
Timer Prescale
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
PR2 Value
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 25-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
Timer Prescale
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
16
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
PR2 Value
Maximum Resolution (bits)
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25.3.7
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
25.3.8
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 6.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
25.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Registeron
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
CCP1CON
CCP2CON
INTCON
PIE1
C2OUTSEL
CC1PSEL
—
SDOSEL
SCKSEL
SDISEL
TXSEL
RXSEL
CCP2SEL
111
255
255
79
—
—
DC1B<1:0>
DC2B<1:0>
CCP1M<3:0>
CCP2M<3:0>
—
GIE
PEIE
ADIE
TMR0IE
INTE
TXIE
IOCIE
TMR0IF
INTF
IOCIF
TMR1GIE
RCIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
79
81
PIE2
OSEIE
TMR1GIF
OSFIF
C2IE
ADIF
C2IF
C1IE
RCIF
C1IF
EEIE
TXIF
EEIF
BCL1IE
SSP1IF
BCL1IF
—
CCP1IF
—
C3IE
TMR2IF
C3IF
CCP2IE
TMR1IF
CCP2IF
PIR1
PIR2
PR2
83
84
Timer2 Period Register
—
186*
T2CON
T2OUTPS<3:0>
TMR2ON
TRISA2
T2CKPS<1:0>
188
186
114
TMR2
TRISA
Timer2 Module Register
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA1
TRISA0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Page provides register information.
*
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25.4 Register Definitions: CCP Control
REGISTER 25-1: CCPxCON: CCPx CONTROL REGISTER
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DCxB<1:0>
CCPxM<3:0>
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM<3:0>: CCPx Mode Select bits
11xx= PWM mode
1011= Compare mode: Auto-conversion Trigger (sets CCPxIF bit (CCP2), starts ADC conversion if
ADC module is enabled)(1)
1010= Compare mode: generate software interrupt only
1001= Compare mode: clear output on compare match (set CCPxIF)
1000= Compare mode: set output on compare match (set CCPxIF)
0111= Capture mode: every 16th rising edge
0110= Capture mode: every 4th rising edge
0101= Capture mode: every rising edge
0100= Capture mode: every falling edge
0011= Reserved
0010= Compare mode: toggle output on match
0001= Reserved
0000= Capture/Compare/PWM off (resets CCPx module)
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26.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
26.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 26-1 is a block diagram of the SPI interface
module.
FIGURE 26-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Write
Read
SSPBUF Reg
SSPSR Reg
SDI
Shift
Clock
bit 0
SDO
SS
Control
Enable
SS
2 (CKP, CKE)
Clock Select
Edge
Select
SSPM<3:0>
4
TMR2 Output
(
)
2
SCK
TOSC
Prescaler
4, 16, 64
Edge
Select
Baud Rate
Generator
(SSPADD)
TRIS bit
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The I2C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 26-2 is a block diagram of the I2C interface
module in Master mode. Figure 26-3 is a diagram of the
I2C interface module in Slave mode.
FIGURE 26-2:
MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal
data bus
[SSPM<3:0>]
Read
Write
SSP1BUF
SSPSR
Baud rate
generator
(SSPADD)
SDA
Shift
Clock
SDA in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPCON2)
SCL
Start bit detect,
Stop bit detect
SCL in
Bus Collision
Write collision detect
Clock arbitration
State counter for
Set/Reset: S, P, SSPSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPCON2)
Set SSP1IF, BCL1IF
end of XMIT/RCV
Address Match detect
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FIGURE 26-3:
MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE)
Internal
Data Bus
Read
Write
SSPBUF Reg
SSPSR Reg
SCL
SDA
Shift
Clock
MSb
LSb
SSPMSK Reg
Match Detect
SSPADD Reg
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
Start and
Stop bit Detect
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PIC16(L)F1782/3
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift register
(on its SDO pin) and the master device is reading this
bit and saving it as the LSb of its shift register.
26.2 SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication.
A slave device is
controlled through a Chip Select known as Slave
Select.
After 8 bits have been shifted out, the master and slave
have exchanged register values.
The SPI bus specifies four signal connections:
• Serial Clock (SCK)
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Slave Select (SS)
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
Figure 26-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Master sends useful data and slave sends dummy
data.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select
connection is required from the master device to each
slave device.
• Master sends useful data and slave sends useful
data.
• Master sends dummy data and slave sends useful
data.
Figure 26-4 shows a typical connection between a
master device and multiple slave devices.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it
deselects the slave.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Every slave device connected to the bus that has not
been selected through its slave select line must
disregard the clock and transmission signals and must
not transmit out any data of its own.
Transmissions involve two shift registers, 8 bits in size,
one in the master and one in the slave. With either the
master or the slave device, data is always shifted out
one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 26-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits
information out on its SDO output pin, which is
connected to, and received by, the master’s SDI input
pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock
polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
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FIGURE 26-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCK
SDO
SCK
SDI
SDO
SS
SPI Master
SPI Slave
#1
SDI
General I/O
General I/O
General I/O
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
26.2.1 SPI MODE REGISTERS
The MSSP module has five registers for SPI mode
operation. These are:
• MSSP STATUS register (SSPSTAT)
• MSSP Control register 1 (SSPCON1)
• MSSP Control register 3 (SSPCON3)
• MSSP Data Buffer register (SSPBUF)
• MSSP Address register (SSPADD)
• MSSP Shift register (SSPSR)
(Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper 2 bits of the
SSPSTAT are read/write.
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 26.7 “Baud Rate Generator”.
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSP1IF interrupt is set.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.
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26.2.2 SPI MODE OPERATION
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full Detect bit, BF of the
SSPSTAT register, and the interrupt flag bit, SSP1IF,
are set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit WCOL
of the SSPCON1 register, will be set. User software
must clear the WCOL bit to allow the following write(s)
to the SSPBUF register to complete successfully.
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur.
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
The SSPSR is not directly readable or writable and can
• SS must have corresponding TRIS bit set
FIGURE 26-5:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010
SPI Slave SSPM<3:0> = 010x
SDO
SDI
Serial Input Buffer
Serial Input Buffer
(SSPBUF)
(BUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
SS
Slave Select
(optional)
General I/O
Processor 2
Processor 1
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The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register
and the CKE bit of the SSPSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 26-6, Figure 26-8 and Figure 26-9,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
26.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 26-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
• FOSC/4 (or TCY)
• FOSC/16 (or 4 * TCY)
• FOSC/64 (or 16 * TCY)
• Timer2 output/2
• Fosc/(4 * (SSPADD + 1))
Figure 26-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 26-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSP1IF
SSPSR to
SSPBUF
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26.2.4
SPI SLAVE MODE
26.2.5
SLAVE SELECT
SYNCHRONIZATION
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last
bit is latched, the SSP1IF interrupt flag bit is set.
The Slave Select can also be used to synchronize
communication. The Slave Select line is held high until
the master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
eventually become out of sync with the master. If the
slave misses a bit, it will always be one bit off in future
transmissions. Use of the Slave Select line allows the
slave and master to align themselves at the beginning
of each transmission.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will
generate an interrupt. If enabled, the device will
wake-up from Sleep.
26.2.4.1 Daisy-Chain Configuration
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 0100).
The SPI bus can sometimes be connected in a
daisy-chain configuration. The first slave output is con-
nected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one large communication shift register. The
daisy-chain feature only requires a single Slave Select
line from the master device.
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the
application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0>
=
Figure 26-7 shows the block diagram of a typical
daisy-chain connection when operating in SPI mode.
0100), the SPI module will reset if the SS
pin is set to VDD.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPCON3 register will enable writes
to the SSPBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSPSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
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FIGURE 26-7:
SPI DAISY-CHAIN CONNECTION
SCK
SDO
SCK
SDI
SDO
SS
SPI Master
SPI Slave
#1
SDI
General I/O
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
FIGURE 26-8:
SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Shift register SSPSR
and bit count are reset
SSPBUF to
SSPSR
bit 6
bit 6
bit 7
bit 7
bit 0
SDO
SDI
bit 7
bit 0
bit 7
Input
Sample
SSP1IF
Interrupt
Flag
SSPSR to
SSPBUF
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FIGURE 26-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
bit 0
bit 7
Input
Sample
SSP1IF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
FIGURE 26-10:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
SDI
bit 0
Input
Sample
SSP1IF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
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26.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if enabled, will wake the
device.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
APFCON
INTCON
ANSA7
—
ANSA5
SDOSEL
TMR0IE
ANSA4
SCKSEL
INTE
ANSA3
SDISEL
IOCIE
ANSA2
TXSEL
TMR0IF
ANSA1
RXSEL
INTF
ANSA0
CCP2SEL
IOCIF
115
111
79
C2OUTSEL CCP1SEL
GIE
PEIE
ADIE
ADIF
PIE1
TMR1GIE
TMR1GIF
RCIE
RCIF
TXIE
TXIF
SSP1IE
SSP1IF
CCP1IE
CCP1IF
TMR2IE
TMR2IF
TMR1IE
TMR1IF
80
PIR1
83
SSP1BUF
SSP1CON1
Synchronous Serial Port Receive Buffer/Transmit Register
260*
306
308
304
114
125
WCOL
SSPOV
PCIE
SSPEN
SCIE
CKP
SSPM<3:0>
SSP1CON3 ACKTIM
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSP1STAT
TRISA
SMP
CKE
D/A
P
S
R/W
UA
BF
TRISA7
TRISC7
TRISA6
TRISC6
TRISA5
TRISC5
TRISA4
TRISC4
TRISA3
TRISC3
TRISA2
TRISC2
TRISA1
TRISC1
TRISA0
TRISA0
TRISC
Legend:
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
*
Page provides register information.
Note 1: PIC16(L)F1783 only.
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I2C MASTER/
26.3 I2C MODE OVERVIEW
FIGURE 26-11:
SLAVE CONNECTION
The Inter-Integrated Circuit Bus (I2C) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A Slave device is
controlled through addressing.
VDD
SCL
SDA
SCL
The I2C bus specifies two signal connections:
VDD
• Serial Clock (SCL)
• Serial Data (SDA)
Master
Slave
SDA
Figure 26-11 shows the block diagram of the MSSP
module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDA line low to indicate to the transmit-
ter that the slave device has received the transmitted
data and is ready to receive more.
Figure 26-11 shows a typical connection between two
processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
The transition of a data bit is always performed while
the SCL line is held low. Transitions that occur while the
SCL line is held high are used to indicate Start and Stop
bits.
If the master intends to write to the slave, then it repeat-
edly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this
example, the master device is in Master Receive mode
and the slave is Slave Transmit mode.
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is
indicated by a low-to-high transition of the SDA line
while the SCL line is held high.
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a
single Read/Write bit, which determines whether the
master intends to transmit to or receive data from the
slave device.
In some cases, the master may want to maintain
control of the bus and re-initiate another transmission.
If so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
The I2C bus specifies three message protocols;
• Single message where a master writes data to a
slave.
A Start bit is indicated by a high-to-low transition of the
SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
• Single message where a master reads data from
a slave.
• Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
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When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a
logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
26.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a trans-
mission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels do not match, loses arbitra-
tion, and must stop transmitting on the SDA line.
26.3.1
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device
may hold the SCL clock line low after receiving or send-
ing a bit, indicating that it is not yet ready to continue.
The master that is communicating with the slave will
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
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TABLE 26-2: I2C BUS TERMS
26.4 I2C MODE OPERATION
TERM
Description
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two
interrupt flags interface the module with the PIC®
microcontroller and user software. Two pins, SDA and
SCL, are exercised by the module to communicate
with other external I2C devices.
Transmitter
The device which shifts data out
onto the bus.
Receiver
Master
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and
terminates a transfer.
26.4.1 BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a master to a slave or vice-versa,
followed by an Acknowledge bit sent back. After the
8th falling edge of the SCL line, the device outputting
data on the SDA changes that pin to an input and
reads in an acknowledge value on the next clock
pulse.
Slave
The device addressed by the
master.
Multi-master
Arbitration
A bus with more than one device
that can initiate data transfers.
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
26.4.2 DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPADD.
26.4.3 SDA AND SCL PINS
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
Write Request
Read Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Note: Data is tied to output zero when an I2C
mode is enabled.
26.4.4 SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPCON3 register. Hold time is the time SDA
is held valid after the falling edge of SCL. Setting the
SDAHT bit selects a longer 300 ns minimum hold time
and may help on buses with large capacitance.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
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26.4.5 START CONDITION
26.4.7 RESTART CONDITION
The I2C specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 26-10 shows wave
forms for Start and Stop conditions.
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I2C Specification that
states no bus collision can occur on a Start.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
26.4.6 STOP CONDITION
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop
condition, a high address with R/W clear, or high
address match fails.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
26.4.8 START/STOP CONDITION INTERRUPT
MASKING
The SCIE and PCIE bits of the SSPCON3 register can
enable the generation of an interrupt in Slave modes
that do not typically support this function. Slave modes
where interrupt on Start and Stop detect are already
enabled, these bits will have no effect.
FIGURE 26-12:
I2C START AND STOP CONDITIONS
SDA
SCL
S
P
Change of
Change of
Data Allowed
Data Allowed
Stop
Start
Condition
Condition
FIGURE 26-13:
I2C RESTART CONDITION
Sr
Change of
Change of
Data Allowed
Data Allowed
Restart
Condition
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26.5 I2C SLAVE MODE OPERATION
26.4.9 ACKNOWLEDGE SEQUENCE
The 9th SCL pulse for any transferred byte in I2C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicated to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The MSSP Slave mode operates in one of four modes
selected in the SSPM bits of SSPCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operated the
same as the other modes with SSP1IF additionally
getting set upon detection of a Start, Restart, or Stop
condition.
The result of an ACK is placed in the ACKSTAT bit of
the SSPCON2 register.
26.5.1 SLAVE MODE ADDRESSES
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPCON2
register is set/cleared to determine the response.
The SSPADD register (Register 26-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPBUF register and an
interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the
software that anything happened.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPSTAT register
or the SSPOV bit of the SSPCON1 register are set
when a byte is received.
The SSP Mask register (Register 26-5) affects the
address matching process. See Section 26.5.9 “SSP
Mask Register” for more information.
When the module is addressed, after the 8th falling
edge of SCL on the bus, the ACKTIM bit of the SSP-
CON3 register is set. The ACKTIM bit indicates the
acknowledge time of the active bus. The ACKTIM Sta-
tus bit is only active when the AHEN bit or DHEN bit is
enabled.
26.5.1.1 I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
26.5.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADD
with the low address. The low address byte is clocked
in and all 8 bits are compared to the low address value
in SSPADD. Even if there is not an address match;
SSP1IF and UA are set, and SCL is held low until
SSPADD is updated to receive a high byte again.
When SSPADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hard-
ware will then acknowledge the read request and
prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
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26.5.2 SLAVE RECEPTION
26.5.2.2 7-bit Reception with AHEN and DHEN
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPSTAT register is cleared.
The received address is loaded into the SSPBUF
register and acknowledged.
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th
falling edge of SCL. These additional interrupts allow
the slave software to decide whether it wants to ACK
the receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set, or bit SSPOV of the SSPCON1 register
is set. The BOEN bit of the SSPCON3 register modifies
this operation. For more information see Register 26-4.
This list describes the steps that need to be taken by
slave software to use these options for I2C communi-
cation. Figure 26-15 displays a module using both
address and data holding. Figure 26-16 includes the
operation with the SEN bit of the SSPCON2 register
set.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSP1IF, must be cleared by soft-
ware.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each received
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in
10-bit mode. See Section 26.2.3 “SPI Master Mode”
for more detail.
1. S bit of SSPSTAT is set; SSP1IF is set if inter-
rupt on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSP1IF is set and CKP cleared after the 8th
falling edge of SCL.
3. Slave clears the SSP1IF.
26.5.2.1 7-bit Addressing Reception
4. Slave can look at the ACKTIM bit of the
SSPCON3 register to determine if the SSP1IF
was after or before the ACK.
This section describes a standard sequence of events
for the MSSP module configured as an I2C Slave in
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 26-13 and Figure 26-14 is used as a visual
reference for this description.
5. Slave reads the address value from SSPBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
This is a step by step process of what typically must
be done to accomplish I2C communication.
7. Slave releases the clock by setting CKP.
8. SSP1IF is set after an ACK, not after a NACK.
1. Start bit detected.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
2. S bit of SSPSTAT is set; SSP1IF is set if inter-
rupt on Start detect is enabled.
10. Slave clears SSP1IF.
3. Matching address with R/W bit clear is received.
Note: SSP1IF is still set after the 9th falling edge
of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to master is SSP1IF not set
4. The slave pulls SDA low sending an ACK to the
master, and sets SSP1IF bit.
5. Software clears the SSP1IF bit.
6. Software reads received address from SSPBUF
clearing the BF flag.
11. SSP1IF set and CKP cleared after 8th falling
edge of SCL for a received data byte.
7. If SEN = 1; Slave software sets CKP bit to
12. Slave looks at ACKTIM bit of SSPCON3 to
determine the source of the interrupt.
release the SCL line.
8. The master clocks out a data byte.
13. Slave reads the received data from SSPBUF
clearing BF.
9. Slave drives SDA low sending an ACK to the
master, and sets SSP1IF bit.
14. Steps 7-14 are the same for each received data
byte.
10. Software clears SSP1IF.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
11. Software reads the received byte from SSPBUF
clearing BF.
12. Steps 8-12 are repeated for all received bytes
from the master.
13. Master sends Stop condition, setting P bit of
SSPSTAT, and the bus goes idle.
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FIGURE 26-14:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
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FIGURE 26-15:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
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FIGURE 26-16:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
2011-2014 Microchip Technology Inc.
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FIGURE 26-17:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
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26.5.3
SLAVE TRANSMISSION
26.5.3.2
7-bit Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish
a
standard transmission.
Figure 26-17 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 26.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1. Master sends a Start condition on SDA and
SCL.
2. S bit of SSPSTAT is set; SSP1IF is set if inter-
rupt on Start detect is enabled.
3. Matching address with R/W bit set is received by
the Slave setting SSP1IF bit.
The transmit data must be loaded into the SSPBUF
register which also loads the SSPSR register. Then the
SCL pin should be released by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time.
4. Slave hardware generates an ACK and sets
SSP1IF.
5. SSP1IF bit is cleared by user.
6. Software reads the received address from
SSPBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, the SCL pin must be
released by setting bit CKP.
8. The slave software loads the transmit data into
SSPBUF.
9. CKP bit is set releasing SCL, allowing the
master to clock the data out of the slave.
10. SSP1IF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSP1IF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
An MSSP interrupt is generated for each data transfer
byte. The SSP1IF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSP1IF bit is set on the falling edge of
the ninth clock pulse.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
26.5.3.1
Slave Mode Bus Collision
13. Steps 9-13 are repeated for each transmitted
byte.
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPCON3 register is set, the
BCL1IF bit of the PIR register is set. Once a bus colli-
sion is detected, the slave goes idle and waits to be
addressed again. User software can use the BCL1IF bit
to handle a slave bus collision.
14. If the master sends a not ACK; the clock is not
held, but SSP1IF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
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FIGURE 26-18:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
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26.5.3.3
7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPCON3 register
enables additional clock stretching and interrupt
generation after the 8th falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSP1IF
interrupt is set.
Figure 26-18 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPSTAT is set; SSP1IF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSP1IF interrupt is
generated.
4. Slave software clears SSP1IF.
5. Slave software reads ACKTIM bit of SSPCON3
register, and R/W and D/A of the SSPSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSP1IF after the ACK if the R/W bit is
set.
11. Slave software clears SSP1IF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
Note: SSPBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.
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FIGURE 26-19:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
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26.5.4 SLAVE MODE 10-BIT ADDRESS
RECEPTION
26.5.5 10-BIT ADDRESSING WITH ADDRESS OR
DATA HOLD
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
10-bit Addressing mode.
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 26-20 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 26-19 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
Figure 26-21 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
1. Bus starts Idle.
2. Master sends Start condition; S bit of SSPSTAT
is set; SSP1IF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
4. Slave sends ACK and SSP1IF is set.
5. Software clears the SSP1IF bit.
6. Software reads received address from SSPBUF
clearing the BF flag.
7. Slave loads low address into SSPADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPADD register are not
allowed until after the ACK sequence.
9. Slave sends ACK and SSP1IF is set.
Note: If the low address does not match, SSP1IF
and UA are still set so that the slave soft-
ware can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSP1IF.
11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSP1IF is set.
14. If SEN bit of SSPCON2 is set, CKP is cleared by
hardware and the clock is stretched.
15. Slave clears SSP1IF.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
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FIGURE 26-20:
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
DS40001579E-page 282
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FIGURE 26-21:
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
2011-2014 Microchip Technology Inc.
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FIGURE 26-22:
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
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26.5.6 CLOCK STRETCHING
26.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus
holds the SCL line low effectively pausing communica-
tion. The slave may stretch the clock to allow more
time to handle data or prepare a response for the
master device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
In 10-bit Addressing mode, when the UA bit is set the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
26.5.6.3 Byte NACKing
The CKP bit of the SSPCON1 register is used to
control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
When AHEN bit of SSPCON3 is set; CKP is cleared by
hardware after the 8th falling edge of SCL for a
received matching address byte. When DHEN bit of
SSPCON3 is set; CKP is cleared after the 8th falling
edge of SCL for received data.
26.5.6.1 Normal Clock Stretching
Stretching after the 8th falling edge of SCL allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
Following an ACK if the R/W bit of SSPSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPBUF with data to
transfer to the master. If the SEN bit of SSPCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
26.5.7 CLOCK SYNCHRONIZATION AND
THE CKP BIT
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. There-
fore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 26-22).
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPBUF was read before the 9th falling
edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPBUF was loaded before the 9th fall-
ing edge of SCL. It is now always cleared
for read requests.
FIGURE 26-23:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX ‚ – 1
Master device
asserts clock
CKP
Master device
releases clock
WR
SSPCON1
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26.5.8 GENERAL CALL ADDRESS SUPPORT
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed
by the master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
Figure 26-23 shows
sequence.
a
general call reception
FIGURE 26-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1 D0
ACK
9
R/W = 0
General Call Address
ACK
SDA
D7 D6
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
SSP1IF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
’1’
26.5.9 SSP MASK REGISTER
An SSP Mask (SSPMSK) register (Register 26-5) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
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26.6.1 I2C MASTER MODE OPERATION
2
26.6 I C Master Mode
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in the SSPCON1 register and
by setting the SSPEN bit. In Master mode, the SDA and
SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set, or the bus is Idle.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
The following events will cause the SSP Interrupt Flag
bit, SSP1IF, to be set (SSP interrupt, if enabled):
• Start condition detected
• Stop condition detected
• Data transfer byte transmitted/received
• Acknowledge transmitted/received
• Repeated Start generated
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 26.7 “Baud
Rate Generator” for more detail.
Note 1: The MSSP module, when configured in
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPBUF did not occur
2: When in Master mode, Start/Stop
detection is masked and an interrupt is
generated when the SEN/PEN bit is
cleared and the generation is complete.
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26.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<7:0> and begins count-
ing. This ensures that the SCL high time will always be
at least one BRG rollover count in the event that the
clock is held low by an external device (Figure 26-25).
FIGURE 26-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX ‚ – 1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
26.6.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not idle.
Note:
Because queuing of events is not allowed,
writing to the lower 5 bits of SSPCON2 is
disabled until the Start condition is
complete.
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26.6.4 I C MASTER MODE START
CONDITION TIMING
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCL1IF, is set, the Start condition is
aborted and the I2C module is reset into
its Idle state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate
Generator is reloaded with the contents of
SSPADD<7:0> and resumes its count. When the Baud
Rate Generator times out (TBRG), the SEN bit of the
SSPCON2 register will be automatically cleared by
hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
2: The Philips I2C specification states that a
bus collision cannot occur on a Start.
FIGURE 26-26:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here
At completion of Start bit,
hardware clears SEN bit
and sets SSP1IF bit
SDA = 1,
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
1st bit
2nd bit
SDA
TBRG
SCL
S
TBRG
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2
26.6.5 I C MASTER MODE REPEATED
CON2 register will be automatically cleared and the
Baud Rate Generator will not be reloaded, leaving the
SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSP1IF bit will not
be set until the Baud Rate Generator has timed out.
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
master state machine is no longer active. When the
RSEN bit is set, the SCL pin is asserted low. When the
SCL pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDA pin is released
(brought high) for one Baud Rate Generator count
(TBRG). When the Baud Rate Generator times out, if
SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. SCL is
asserted low. Following this, the RSEN bit of the SSP-
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data ‘1’.
FIGURE 26-27:
REPEAT START CONDITION WAVEFORM
S bit set by hardware
Write to SSPCON2
occurs here
SDA = 1,
At completion of Start bit,
hardware clears RSEN bit
and sets SSP1IF
SDA = 1,
SCL = 1
SCL (no change)
TBRG
TBRG
TBRG
1st bit
SDA
SCL
Write to SSPBUF occurs here
TBRG
Sr
Repeated Start
TBRG
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26.6.6 I2C MASTER MODE TRANSMISSION
26.6.6.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received
properly. The status of ACK is written into the
ACKSTAT bit on the rising edge of the ninth clock. If the
master receives an Acknowledge, the Acknowledge
Status bit, ACKSTAT, is cleared. If not, the bit is set.
After the ninth clock, the SSP1IF bit is set and the mas-
ter clock (Baud Rate Generator) is suspended until the
next data byte is loaded into the SSPBUF, leaving SCL
low and SDA unchanged (Figure 26-27).
26.6.6.4 Typical transmit sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSP1IF is set by hardware on completion of the
Start.
3. SSP1IF is cleared by software.
4. The MSSP module will wait the required start
time before any other operation takes place.
5. The user loads the SSPBUF with the slave
address to transmit.
6. Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
7. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
8. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSP1IF bit.
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSP1IF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPBUF takes place,
holding SCL low and allowing SDA to float.
9. The user loads the SSPBUF with eight bits of
data.
10. Data is shifted out the SDA pin until all 8 bits are
transmitted.
11. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the SSP-
CON2 register. Interrupt is generated once the
Stop/Restart condition is complete.
26.6.6.1
BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
26.6.6.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
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FIGURE 26-28:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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I2C MASTER MODE RECEPTION
26.6.7.4 Typical Receive Sequence:
26.6.7
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPCON2
register.
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSP1IF is set by hardware on completion of the
Start.
Note:
The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
3. SSP1IF is cleared by software.
4. User writes SSPBUF with the slave address to
transmit and the R/W bit set.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the
contents of the SSPSR are loaded into the SSPBUF,
the BF flag bit is set, the SSP1IF flag bit is set and the
Baud Rate Generator is suspended from counting,
holding SCL low. The MSSP is now in Idle state
awaiting the next command. When the buffer is read by
the CPU, the BF flag bit is automatically cleared. The
user can then send an Acknowledge bit at the end of
reception by setting the Acknowledge Sequence
Enable, ACKEN bit of the SSPCON2 register.
5. Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
6. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
7. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSP1IF bit.
8. User sets the RCEN bit of the SSPCON2 register
and the master clocks in a byte from the slave.
9. After the 8th falling edge of SCL, SSP1IF and
BF are set.
10. User clears the SSP1IF bit and reads the received
byte from SSPUF, which clears the BF flag.
26.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
11. The user either clears the SSPCON2 register’s
ACKDT bit to receive another byte or sets the
ADKDT bit to suppress further data and then initi-
ates the acknowledge sequence by setting the
ACKEN bit.
26.6.7.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
12. Master’s ACK or ACK is clocked out to the slave
and SSP1IF is set.
13. User clears SSP1IF.
26.6.7.3
WCOL Status Flag
14. Steps 8-13 are repeated for each received byte
from the slave.
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
15. If the ACKST bit was set in step 11 then the user
can send a STOP to release the bus.
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FIGURE 26-29:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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26.6.8
ACKNOWLEDGE SEQUENCE
TIMING
26.6.9
STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSP1IF bit is set (Figure 26-30).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCL pin is deasserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode
(Figure 26-29).
26.6.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
26.6.8.1
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 26-30:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDA
SCL
D0
8
9
SSP1IF
Cleared in
SSP1IF set at
the end of receive
software
Cleared in
software
SSP1IF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
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FIGURE 26-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSP1IF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
26.6.10 SLEEP OPERATION
26.6.13 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCL1IF and reset the
I2C port to its Idle state (Figure 26-31).
26.6.11 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
26.6.12 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPSTAT register is set,
or the bus is Idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCL1IF bit.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
if the I2C bus is free, the user can resume communica-
tion by asserting a Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSP1IF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
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FIGURE 26-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data does not match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCL1IF)
BCL1IF
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If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 26-34). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
26.6.13.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 26-32).
b) SCL is sampled low before SDA is asserted low
(Figure 26-33).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a fac-
tor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCL1IF flag is set and
•
the MSSP module is reset to its Idle state
(Figure 26-32).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus colli-
sion occurs because it is assumed that another master
is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 26-33:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCL1IF,
S bit and SSP1IF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSP1IF set because
SDA = 0, SCL = 1.
BCL1IF
SSP1IF and BCL1IF are
cleared by software
S
SSP1IF
SSP1IF and BCL1IF are
cleared by software
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FIGURE 26-34:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCL1IF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCL1IF.
BCL1IF
Interrupt cleared
by software
S
’0’
’0’
’0’
’0’
SSP1IF
FIGURE 26-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSP1IF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
’0’
BCL1IF
S
SSP1IF
Interrupts cleared
by software
SDA = 0, SCL = 1,
set SSP1IF
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If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 26-35).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
26.6.13.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 26-36.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and counts
down to zero. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 26-36:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCL1IF and release SDA and SCL.
RSEN
BCL1IF
Cleared by software
’0’
S
’0’
SSP1IF
FIGURE 26-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCL1IF. Release SDA and SCL.
BCL1IF
RSEN
Interrupt cleared
by software
’0’
S
SSP1IF
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The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 26-37). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 26-38).
26.6.13.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 26-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCL1IF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCL1IF
P
’0’
’0’
SSP1IF
FIGURE 26-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCL1IF
Assert SDA
SCL
PEN
BCL1IF
P
’0’
’0’
SSP1IF
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TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Valueson
Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
INTCON
PIE1
C2OUTSEL CCP1SEL
SDOSEL
TMR0IE
RCIE
SCKSEL
INTE
SDISEL
IOCIE
TXSEL
TMR0IF
CCP1IE
RXSEL
INTF
CCP2SEL
IOCIF
111
79
GIE
PEIE
ADIE
TMR1GIE
TXIE
SSP1IE
TMR2IE
TMR1IE
80
81
PIE2
PIR1
OSFIE
C2IE
ADIF
C1IE
RCIF
EEIE
TXIF
BCL1IE
SSP1IF
—
C3IE
CCP2IE
TMR1IF
TMR1GIF
CCP1IF
TMR2IF
83
84
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
—
C3IF
CCP2IF
SSP1ADD
SSP1BUF
309
ADD<7:0>
Synchronous Serial Port Receive Buffer/Transmit Register
260*
306
307
306
309
304
125
SSP1CON1
SSP1CON2
SSP1CON3
SSP1MSK
SSP1STAT
TRISC
WCOL
GCEN
SSPOV
ACKSTAT
PCIE
SSPEN
ACKDT
SCIE
CKP
ACKEN
BOEN
SSPM<3:0>
RCEN
PEN
RSEN
AHEN
SEN
ACKTIM
SDAHT
SBCDE
DHEN
MSK<7:0>
SMP
CKE
D/A
P
S
R/W
UA
BF
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISA0
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
*
Page provides register information.
Note 1: PIC16(L)F1783 only.
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clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
26.7 BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator
available for clock generation in both I2C and SPI
Master modes. The Baud Rate Generator (BRG)
reload value is placed in the SSPADD register
(Register 26-6). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting
down.
Table 26-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 26-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
FOSC
FCLOCK = -------------------------------------------------
SSPxADD + 14
An internal signal “Reload” in Figure 26-39 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 26-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
BRG Down Counter
SSPCLK
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 26-4: MSSP CLOCK RATE W/BRG
FCLOCK
(2 Rollovers of BRG)
FOSC
FCY
BRG Value
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
13h
19h
4Fh
09h
0Ch
27h
09h
400 kHz(1)
308 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
100 kHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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26.8 Register Definitions: MSSP Control
REGISTER 26-1: SSPSTAT: SSP STATUS REGISTER
R/W-0/0
SMP
R/W-0/0
CKE
R-0/0
D/A
R-0/0
P
R-0/0
S
R-0/0
R/W
R-0/0
UA
R-0/0
BF
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
In I2C™ mode only:
1= Enable input logic so that thresholds are compliant with SMBus specification
0= Disable SMBus specific inputs
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0= Stop bit was not detected last
bit 3
bit 2
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0= Start bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I2C Slave mode:
1= Read
0= Write
In I2C Master mode:
1= Transmit is in progress
0= Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1
UA: Update Address bit (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
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REGISTER 26-1: SSPSTAT: SSP STATUS REGISTER (CONTINUED)
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
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REGISTER 26-2: SSPCON1: SSP CONTROL REGISTER 1
R/C/HS-0/0
WCOL
R/C/HS-0/0
SSPOV
R/W-0/0
SSPEN
R/W-0/0
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware C = User cleared
bit 7
WCOL: Write Collision Detect bit
Master mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0= No collision
Slave mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register (must be cleared in software).
0= No overflow
In I2C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1= Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
In I2C Slave mode:
SCL release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1000= I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)
1001= Reserved
1010= SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5)
1011= I2C firmware controlled Master mode (Slave idle)
1100= Reserved
1101= Reserved
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
2:
3:
4:
5:
SSPADD values of 0, 1 or 2 are not supported for I2C mode.
SSPADD value of ‘0’ is not supported. Use SSPM = 0000instead.
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REGISTER 26-3: SSPCON2: SSP CONTROL REGISTER 2
R/W-0/0
GCEN
R-0/0
R/W-0/0
ACKDT
R/S/HS-0/0 R/S/HS-0/0
ACKEN RCEN
R/S/HS-0/0
PEN
R/S/HS-0/0 R/W/HS-0/0
RSEN SEN
bit 0
ACKSTAT
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware S = User set
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (in I2C Slave mode only)
1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1= Acknowledge was not received
0= Acknowledge was received
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1= Not Acknowledge
0= Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
bit 3
bit 2
RCEN: Receive Enable bit (in I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
bit 1
bit 0
RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
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REGISTER 26-4: SSPCON3: SSP CONTROL REGISTER 3
R-0/0
R/W-0/0
PCIE
R/W-0/0
SCIE
R/W-0/0
BOEN
R/W-0/0
SDAHT
R/W-0/0
SBCDE
R/W-0/0
AHEN
R/W-0/0
DHEN
ACKTIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)
1= Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock
0= Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Stop condition
0= Stop detection interrupts are disabled(2)
SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Start or Restart conditions
0= Start detection interrupts are disabled(2)
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1= SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
This bit is ignored.
In I2C Slave mode:
1= SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0= SSPBUF is only updated when SSPOV is clear
bit 3
bit 2
SDAHT: SDA Hold Time Selection bit (I2C mode only)
1= Minimum of 300 ns hold time on SDA after the falling edge of SCL
0= Minimum of 100 ns hold time on SDA after the falling edge of SCL
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes idle
1= Enable slave bus collision interrupts
0= Slave bus collision interrupts are disabled
bit 1
bit 0
AHEN: Address Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSP-
CON1 register will be cleared and the SCL will be held low.
0= Address holding is disabled
DHEN: Data Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
of the SSPCON1 register and SCL is held low.
0= Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
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REGISTER 26-5: SSPMSK: SSP MASK REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-1
bit 0
MSK<7:1>: Mask bits
1= The received address bit n is compared to SSPADD<n> to detect I2C address match
0= The received address bit n is not used to detect I2C address match
MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111or 1111):
1= The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0= The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 26-6: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
Master mode:
bit 7-0
ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most Significant Address Byte:
bit 7-3
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
ADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode — Least Significant Address Byte:
bit 7-0
ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1
bit 0
ADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
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The EUSART module includes the following capabilities:
27.0 ENHANCED UNIVERSAL
SYNCHRONOUS
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
• Sleep operation
system.
Full-Duplex
mode
is
useful
for
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 27-1 and Figure 27-2.
FIGURE 27-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXIF
TXREG Register
8
TX/CK pin
MSb
(8)
LSb
0
Pin Buffer
and Control
• • •
Transmit Shift Register (TSR)
TXEN
TRMT
SPEN
Baud Rate Generator
BRG16
FOSC
÷ n
TX9
n
+ 1
Multiplier x4
x16 x64
TX9D
SYNC
BRGH
BRG16
1
X
X
X
1
1
0
1
0
0
0
1
0
0
0
SPBRGH
SPBRGL
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FIGURE 27-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
OERR
RCIDL
RX/DT pin
RSR Register
MSb
Stop (8)
LSb
0
START
Pin Buffer
and Control
Data
Recovery
7
1
• • •
Baud Rate Generator
FOSC
RX9
÷ n
BRG16
n
+ 1
Multiplier x4
x16 x64
SYNC
BRGH
BRG16
1
X
X
X
1
1
0
1
0
0
0
1
0
0
0
FIFO
SPBRGH
SPBRGL
RX9D
FERR
RCREG Register
8
Data Bus
RCIF
RCIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 27-1,
Register 27-2 and Register 27-3, respectively.
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
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27.1.1.2
Transmitting Data
27.1 EUSART Asynchronous Mode
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the Mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 27-5
for examples of baud rate configurations.
27.1.1.3
Transmit Data Polarity
The polarity of the transmit data can be controlled with
the SCKP bit of the BAUDxCON register. The default
state of this bit is ‘0’ which selects high true transmit idle
and data bits. Setting the SCKP bit to ‘1’ will invert the
transmit data resulting in low true idle and data bits. The
SCKP bit controls transmit data polarity in
Asynchronous mode only. In Synchronous mode, the
SCKP bit has a different function. See Section 27.5.1.2
“Clock Polarity”.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
27.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
27.1.1.4
Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The EUSART transmitter block diagram is shown in
Figure 27-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
27.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
All other EUSART control bits are assumed to be in
their default state.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral, the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
Note:
The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.
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27.1.1.5
TSR Status
27.1.1.7
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
1. Initialize the SPBRGH, SPBRGL register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 27.4 “EUSART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the 8 Least Significant data bits are an address
when the receiver is set for address detection.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
4. Set SCKP bit if inverted transmit is desired.
27.1.1.6
Transmitting 9-Bit Characters
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set, the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the eight Least Significant bits into the TXREG. All 9
bits of data will be transferred to the TSR shift register
immediately after the TXREG is written.
6. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
8. Load 8-bit data into the TXREG register. This
will start the transmission.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 27.1.2.7 “Address
Detection” for more information on the address mode.
FIGURE 27-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
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FIGURE 27-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
Word 2
1 TCY
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 27-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Register on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
111
322
79
APFCON
BAUDCON
INTCON
PIE1
C2OUTSEL CC1PSEL SDOSEL
SCKSEL
SCKP
INTE
SDISEL
BRG16
IOCIE
TXSEL
—
RXSEL
WUE
CCP2SEL
ABDEN
IOCIF
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
RX9
—
TMR0IE
RCIE
TMR0IF
CCP1IE
CCP1IF
FERR
INTF
TMR1GIE
TMR1GIF
SPEN
TXIE
SSP1IE
SSP1IF
ADDEN
TMR2IE
TMR2IF
OERR
TMR1IE
TMR1IF
RX9D
80
PIR1
RCIF
TXIF
83
RCSTA
SPBRGL
SPBRGH
TRISC
SREN
CREN
321
323
323
125
312*
320
BRG<7:0>
BRG<15:8>
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
BRGH
TRISC1
TRMT
TRISC0
TX9D
TXREG
TXSTA
EUSART Transmit Data Register
CSRC TX9 TXEN
SYNC
SENDB
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.
*
Page provides register information.
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27.1.2
EUSART ASYNCHRONOUS
RECEIVER
27.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 27.1.2.4 “Receive Framing
Error” for more information on framing errors.
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 27-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all 8 or 9
bits of the character have been shifted in, they are
immediately transferred to
a
two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register.
27.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The programmer
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input.
Note:
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 27.1.2.5
“Receive Overrun Error” for more
information on overrun errors.
27.1.2.3
Receive Interrupts
Note:
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
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27.1.2.4
Receive Framing Error
27.1.2.7
Address Detection
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
27.1.2.5
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
27.1.2.6
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
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27.1.2.8
Asynchronous Reception Set-up:
27.1.2.9
9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 27.4 “EUSART
Baud Rate Generator (BRG)”).
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 27.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
8. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
9. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 27-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX/DT pin
bit 7/8
bit 7/8
bit 0 bit 1
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg.
Word 2
RCREG
Word 1
RCREG
RCIDL
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
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TABLE 27-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
BAUDCON
INTCON
PIE1
C2OUTSEL CC1PSEL SDOSEL
SCKSEL
SCKP
INTE
SDISEL
BRG16
IOCIE
TXSEL
—
RXSEL
WUE
CCP2SEL
ABDEN
IOCIF
111
322
79
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
TMR0IE
RCIE
TMR0IF
CCP1IE
CCP1IF
INTF
TMR1GIE
TMR1GIF
TXIE
SSP1IE
SSP1IF
TMR2IE
TMR2IF
TMR1IE
TMR1IF
80
PIR1
RCIF
TXIF
83
RCREG
RCSTA
SPBRGL
SPBRGH
TRISC
EUSART Receive Data Register
315*
321
323
323
125
320
SPEN
RX9
SREN
CREN
BRG<7:0>
BRG<15:8>
ADDEN
FERR
OERR
RX9D
TRISC7
CSRC
TRISC6
TX9
TRISC5
TXEN
TRISC4
SYNC
TRISC3
SENDB
TRISC2
BRGH
TRISC1
TRMT
TRISC0
TX9D
TXSTA
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.
*
Page provides register information.
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27.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 6.2.2
“Internal Clock Sources” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 27.4.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
2011-2014 Microchip Technology Inc.
DS40001579E-page 319
PIC16(L)F1782/3
27.3 Register Definitions: EUSART Control
REGISTER 27-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0
CSRC
R/W-0/0
TX9
R/W-0/0
TXEN(1)
R/W-0/0
SYNC
R/W-0/0
SENDB
R/W-0/0
BRGH
R-1/1
R/W-0/0
TX9D
TRMT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS40001579E-page 320
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
REGISTER 27-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0/0
SPEN
R/W-0/0
RX9
R/W-0/0
SREN
R/W-0/0
CREN
R/W-0/0
ADDEN
R-0/0
R-0/0
R-0/0
RX9D
FERR
OERR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
2011-2014 Microchip Technology Inc.
DS40001579E-page 321
PIC16(L)F1782/3
REGISTER 27-3: BAUDCON: BAUD RATE CONTROL REGISTER
R-0/0
R-1/1
U-0
—
R/W-0/0
SCKP
R/W-0/0
BRG16
U-0
—
R/W-0/0
WUE
R/W-0/0
ABDEN
ABDOVF
RCIDL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1= Auto-baud timer overflowed
0= Auto-baud timer did not overflow
Synchronous mode:
Don’t care
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1= Receiver is idle
0= Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1= Transmit inverted data to the TX/CK pin
0= Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1= Data is clocked on rising edge of the clock
0= Data is clocked on falling edge of the clock
bit 3
BRG16: 16-bit Baud Rate Generator bit
1= 16-bit Baud Rate Generator is used
0= 8-bit Baud Rate Generator is used
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0= Receiver is operating normally
Synchronous mode:
Don’t care
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0= Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
DS40001579E-page 322
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
EXAMPLE 27-1:
CALCULATING BAUD
RATE ERROR
27.4 EUSART Baud Rate Generator
(BRG)
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
FOSC
Desired Baud Rate = -----------------------------------------------------------------------
64[SPBRGH:SPBRGL] + 1
Solving for SPBRGH:SPBRGL:
FOSC
---------------------------------------------
Desired Baud Rate
X = --------------------------------------------- – 1
64
The SPBRGH, SPBRGL register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
16000000
-----------------------
9600
= ----------------------- – 1
64
= 25.042 = 25
Table 27-3 contains the formulas for determining the
baud rate. Example 27-1 provides a sample calculation
for determining the baud rate and baud rate error.
16000000
Calculated Baud Rate = --------------------------
6425 + 1
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 27-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
= 9615
Calc. Baud Rate – Desired Baud Rate
Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
9615 – 9600
= ---------------------------------- = 0 . 1 6 %
9600
Writing a new value to the SPBRGH, SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.
2011-2014 Microchip Technology Inc.
DS40001579E-page 323
PIC16(L)F1782/3
TABLE 27-3: BAUD RATE FORMULAS
Configuration Bits
Baud Rate Formula
BRG/EUSART Mode
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend:
x= Don’t care, n = value of SPBRGH, SPBRGL register pair
TABLE 27-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
RCSTA
ABDOVF RCIDL
—
SCKP
CREN
BRG16
ADDEN
—
WUE
ABDEN
RX9D
322
321
323
323
320
SPEN
CSRC
RX9
SREN
FERR
OERR
SPBRGL
SPBRGH
TXSTA
BRG<7:0>
BRG<15:8>
SYNC SENDB
TX9
TXEN
BRGH
TRMT
TX9D
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
Page provides register information.
*
DS40001579E-page 324
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
—
—
—
—
—
—
—
—
255
129
32
—
—
—
239
119
29
—
—
—
143
71
17
16
8
—
1221
2404
9470
10417
19.53k
1.73
0.16
-1.36
0.00
1.73
1200
2400
9600
10286
19.20k
0.00
0.00
0.00
-1.26
0.00
0.00
—
1200
2400
9600
10165
19.20k
0.00
0.00
0.00
-2.42
0.00
0.00
—
2400
2404
9615
10417
19.23k
0.16
0.16
0.00
0.16
207
51
47
25
9600
10417
19.2k
57.6k
115.2k
29
27
15
14
2
55.55k
—
-3.55
—
3
—
—
—
—
—
—
57.60k
—
7
57.60k
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
0.00
0.00
0.00
0.00
—
300
1200
—
1202
2404
9615
10417
—
—
0.16
0.16
0.16
0.00
—
—
103
51
12
11
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
300
1200
2400
9600
—
191
47
23
5
300
1202
—
0.16
0.16
—
51
12
—
—
—
—
—
—
2400
9600
—
—
10417
19.2k
57.6k
115.2k
10417
—
0.00
—
—
2
—
—
—
—
—
—
19.20k
0.00
0.00
—
—
—
—
—
—
—
—
0
—
—
57.60k
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1200
2400
9600
10417
19.2k
57.6k
—
—
—
—
—
—
—
—
—
—
—
—
—
71
65
35
11
5
9615
10417
19.23k
57.14k
0.16
0.00
0.16
-0.79
2.12
207
191
103
34
9615
10417
19.23k
56.82k
0.16
0.00
0.16
-1.36
129
119
64
9600
10378
19.20k
57.60k
115.2k
0.00
-0.37
0.00
0.00
0.00
119
110
59
19
9
9600
0.00
0.53
0.00
0.00
0.00
10473
19.20k
57.60k
115.2k
21
115.2k 117.64k
16
113.64k -1.36
10
2011-2014 Microchip Technology Inc.
DS40001579E-page 325
PIC16(L)F1782/3
TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 8.000 MHz
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
—
—
—
—
—
—
300
1200
—
1202
2404
9615
10417
19.23k
—
—
—
207
103
25
—
—
—
191
95
23
21
11
3
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
0.16
0.16
0.16
0.00
0.16
—
1200
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2400
2404
9615
10417
19231
55556
—
0.16
0.16
0.00
0.16
-3.55
—
207
51
47
25
8
2400
9600
9600
10417
19.2k
57.6k
115.2k
23
10473
19.2k
57.60k
115.2k
10417
—
0.00
—
12
—
—
—
—
—
—
—
—
—
—
1
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
300.0
1200
0.00
-0.02
-0.04
0.16
0.00
0.16
-0.79
2.12
6666
3332
832
207
191
103
34
300.0
1200
-0.01
-0.03
-0.03
0.16
0.00
0.16
-1.36
4166
1041
520
129
119
64
300.0
1200
0.00
0.00
0.00
0.00
-0.37
0.00
0.00
0.00
3839
959
479
119
110
59
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2303
575
287
71
2400
2401
2399
2400
2400
9600
9615
9615
9600
9600
10417
19.2k
57.6k
115.2k
10417
19.23k
57.14k
117.6k
10417
19.23k
56.818
10378
19.20k
57.60k
115.2k
10473
19.20k
57.60k
115.2k
65
35
21
19
11
16
113.636 -1.36
10
9
5
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
299.9
1199
-0.02
-0.08
0.16
0.16
0.00
0.16
-3.55
—
1666
416
207
51
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
767
191
95
23
21
11
3
300.5
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
2400
2404
9615
10417
19.23k
55556
—
2400
9600
9600
10417
19.2k
57.6k
115.2k
47
23
10473
19.20k
57.60k
115.2k
10417
—
0.00
—
25
12
—
—
—
8
—
—
—
—
—
—
—
1
—
—
DS40001579E-page 326
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
300.0
1200
0.00
0.00
0.01
0.04
0.00
-0.08
-0.08
0.64
26666
6666
3332
832
300.0
1200
0.00
-0.01
0.02
-0.03
0.00
0.16
-0.22
0.94
16665
4166
2082
520
479
259
86
300.0
1200
0.00
0.00
0.00
0.00
0.08
0.00
0.00
0.00
15359
3839
1919
479
441
239
79
300.0
1200
0.00
0.00
0.00
0.00
0.16
0.00
0.00
0.00
9215
2303
1151
287
264
143
47
2400
2400
2400
2400
2400
9600
9604
9597
9600
9600
10417
19.2k
57.6k
115.2k
10417
19.18k
57.55k
115.9k
767
10417
19.23k
57.47k
116.3k
10425
19.20k
57.60k
115.2k
10433
19.20k
57.60k
115.2k
416
138
68
42
39
23
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
300.0
1200
0.00
-0.02
0.04
0.16
0
6666
1666
832
207
191
103
34
300.0
1200
0.01
0.04
0.08
0.16
0.00
0.16
2.12
-3.55
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
3071
767
383
95
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
2400
2401
2398
2400
9600
9615
9615
9600
10417
19.2k
57.6k
115.2k
10417
19.23k
57.14k
117.6k
10417
19.23k
58.82k
111.1k
10473
19.20k
57.60k
115.2k
87
23
0.16
-0.79
2.12
51
47
12
16
15
—
16
8
7
—
—
—
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PIC16(L)F1782/3
and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
27.4.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Section 27.4.3
“Auto-Wake-up
on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 27-6).
While the ABD sequence takes place, the EUSART
state machine is held in idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 27-6. The fifth rising edge will occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH, SPBRGL register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the
SPBRGL register did not overflow by checking for 00h
in the SPBRGH register.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRGL
register pair.
TABLE 27-6:
BRG16 BRGH
BRG COUNTER CLOCK RATES
BRG Base
Clock
BRG ABD
Clock
0
0
0
1
FOSC/64
FOSC/16
FOSC/512
FOSC/128
1
1
0
1
FOSC/16
FOSC/4
FOSC/128
FOSC/32
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 27-6. During ABD,
both the SPBRGH and SPBRGL registers are used as
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
Note:
During the ABD sequence, SPBRGL and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 27-6:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
0000h
001Ch
BRG Value
Edge #5
Stop bit
Edge #1
bit 1
Edge #2
bit 3
Edge #3
bit 5
Edge #4
bit 7
bit 6
RX pin
Start
bit 0
bit 2
bit 4
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
XXh
XXh
1Ch
00h
SPBRGL
SPBRGH
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
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27.4.2
AUTO-BAUD OVERFLOW
27.4.3.1
Special Considerations
During the course of automatic baud detection, the
ABDOVF bit of the BAUDCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRGL register
pair. After the ABDOVF bit has been set, the counter
continues to count until the fifth rising edge is detected
on the RX pin. Upon detecting the fifth RX edge, the
hardware will set the RCIF interrupt flag and clear the
ABDEN bit of the BAUDCON register. The RCIF flag
can be subsequently cleared by reading the RCREG
register. The ABDOVF flag of the BAUDCON register
can be cleared by software directly.
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
To terminate the auto-baud process before the RCIF
flag is set, clear the ABDEN bit then clear the ABDOVF
bit of the BAUDCON register. The ABDOVF bit will
remain set if the ABDEN bit is not cleared first.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
27.4.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
WUE Bit
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 27-7), and asynchronously if
the device is in Sleep mode (Figure 27-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
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FIGURE 27-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4
OSC1
Auto Cleared
Bit set by user
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in idle while the WUE bit is set.
FIGURE 27-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q4
Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3
Q1
Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
Auto Cleared
OSC1
Bit Set by User
WUE bit
RX/DT Line
Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed
Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in idle while the WUE bit is set.
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27.4.4
BREAK CHARACTER SEQUENCE
27.4.5
RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character
transmission is then initiated by a write to the TXREG.
The value of data written to TXREG will be ignored and
all ‘0’s will be transmitted.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The second method uses the Auto-Wake-up feature
described in Section 27.4.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or idle, just as it does during
normal transmission. See Figure 27-9 for the timing of
the Break character sequence.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
27.4.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
FIGURE 27-9:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here
Auto Cleared
SENDB
(send Break
control bit)
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Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
27.5 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
27.5.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the EUSART is configured for
synchronous master transmit operation.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately trans-
ferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXREG.
Start and Stop bits are not used in synchronous
transmissions.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
27.5.1
SYNCHRONOUS MASTER MODE
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
The following bits are used to configure the EUSART
for synchronous master operation:
• SYNC = 1
27.5.1.4
Synchronous Master Transmission
Set-up:
• CSRC = 1
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
1. Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 27.4 “EUSART
Baud Rate Generator (BRG)”).
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
27.5.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the
trailing edge of each clock. One clock cycle is
generated for each data bit. Only as many clock cycles
are generated as there are data bits.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the TXREG
register.
27.5.1.2
Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
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FIGURE 27-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note:
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 27-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 27-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
BAUDCON
INTCON
PIE1
C2OUTSEL CC1PSEL SDOSEL
SCKSEL
SCKP
INTE
SDISEL
BRG16
IOCIE
TXSEL
—
RXSEL
WUE
CCP2SEL
ABDEN
IOCIF
111
322
79
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
RX9
—
TMR0IE
RCIE
TMR0IF
CCP1IE
CCP1IF
FERR
INTF
TMR1GIE
TMR1GIF
SPEN
TXIE
SSP1IE
SSP1IF
ADDEN
TMR2IE
TMR2IF
OERR
TMR1IE
TMR1IF
RX9D
80
PIR1
RCIF
TXIF
83
RCSTA
SPBRGL
SPBRGH
TRISC
SREN
CREN
321
323
323
125
312*
320
BRG<7:0>
BRG<15:8>
TRISC4 TRISC3
TRISC7
CSRC
TRISC6
TX9
TRISC5
TRISC2
TRISC1
TRMT
TRISC0
TX9D
TXREG
EUSART Transmit Data Register
TXEN SYNC SENDB
TXSTA
BRGH
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.
*
Page provides register information.
2011-2014 Microchip Technology Inc.
DS40001579E-page 333
PIC16(L)F1782/3
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
27.5.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
27.5.1.8
Receiving 9-bit Characters
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
27.5.1.9
Synchronous Master Reception
Set-up:
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char-
acter is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
1. Initialize the SPBRGH, SPBRGL register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
Note:
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
5. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
6. If 9-bit reception is desired, set bit RX9.
27.5.1.6
Slave Clock
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
8. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
Note:
If the device is configured as a slave and
the TX/CK function is on an analog pin, the
corresponding ANSEL bit must be cleared.
27.5.1.7
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
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FIGURE 27-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 27-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
BAUDCON
INTCON
PIE1
C2OUTSEL CC1PSEL SDOSEL
SCKSEL
SCKP
INTE
SDISEL
BRG16
IOCIE
TXSEL
—
RXSEL
WUE
CCP2SEL
ABDEN
IOCIF
111
322
79
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
TMR0IE
RCIE
TMR0IF
CCP1IE
CCP1IF
INTF
TMR1GIE
TMR1GIF
TXIE
SSP1IE
SSP1IF
TMR2IE
TMR2IF
TMR1IE
TMR1IF
80
PIR1
RCIF
TXIF
83
RCREG
RCSTA
SPBRGL
SPBRGH
TRISC
EUSART Receive Data Register
315*
321
323
323
125
320
SPEN
RX9
SREN
CREN
BRG<7:0>
BRG<15:8>
ADDEN
FERR
OERR
RX9D
TRISC7
CSRC
TRISC6
TX9
TRISC5
TXEN
TRISC4
SYNC
TRISC3
SENDB
TRISC2
BRGH
TRISC1
TRMT
TRISC0
TX9D
TXSTA
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
*
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If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
27.5.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for synchronous slave operation:
1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
• CSRC = 0
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
27.5.2.2
Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
27.5.2.1
EUSART Synchronous Slave
Transmit
2. Clear the ANSEL bit for the CK pin (if applicable).
3. Clear the CREN and SREN bits.
The operation of the Synchronous Master and Slave
modes are identical (see Section 27.5.1.3
“Synchronous Master Transmission”), except in the
4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
case of the Sleep mode.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 27-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
BAUDCON
INTCON
PIE1
C2OUTSEL CC1PSEL SDOSEL
SCKSEL
SCKP
INTE
SDISEL
BRG16
IOCIE
TXSEL
—
RXSEL
WUE
CCP2SEL
ABDEN
IOCIF
111
322
79
ABDOVF
GIE
RCIDL
PEIE
—
TMR0IE
RCIE
TMR0IF
CCP1IE
CCP1IF
FERR
INTF
TMR1GIE
TMR1GIF
SPEN
ADIE
TXIE
SSP1IE
SSP1IF
ADDEN
TRISC3
TMR2IE
TMR2IF
OERR
TRISC1
TMR1IE
TMR1IF
RX9D
80
PIR1
ADIF
RCIF
TXIF
83
RCSTA
TRISC
TXREG
RX9
SREN
TRISC5
CREN
TRISC4
321
125
312*
320
TRISC7
TRISC6
TRISC2
TRISC0
EUSART Transmit Data Register
TXEN SYNC SENDB
TXSTA
CSRC
TX9
BRGH
TRMT
TX9D
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
*
Page provides register information.
DS40001579E-page 336
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
27.5.2.3
EUSART Synchronous Slave
Reception
27.5.2.4
Synchronous Slave Reception
Set-up:
The operation of the Synchronous Master and Slave
modes is identical (Section 27.5.1.5 “Synchronous
Master Reception”), with the following exceptions:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for both the CK and DT pins
(if applicable).
• Sleep
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• CREN bit is always set, therefore the receiver is
never idle
• SREN bit, which is a “don’t care” in Slave mode
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 27-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
BAUDCON
INTCON
PIE1
C2OUTSEL CC1PSEL SDOSEL
SCKSEL
SCKP
INTE
SDISEL
BRG16
IOCIE
TXSEL
—
RXSEL
WUE
CCP2SEL
ABDEN
IOCIF
111
322
79
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
TMR0IE
RCIE
TMR0IF
CCP1IE
CCP1IF
INTF
TMR1GIE
TMR1GIF
TXIE
SSP1IE
SSP1IF
TMR2IE
TMR2IF
TMR1IE
TMR1IF
80
PIR1
RCIF
TXIF
83
RCREG
RCSTA
TRISC
EUSART Receive Data Register
315*
321
125
320
SPEN
TRISC7
CSRC
RX9
TRISC6
TX9
SREN
TRISC5
TXEN
CREN
TRISC4
SYNC
ADDEN
TRISC3
SENDB
FERR
TRISC2
BRGH
OERR
TRISC1
TRMT
RX9D
TRISC0
TX9D
TXSTA
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.
*
Page provides register information.
2011-2014 Microchip Technology Inc.
DS40001579E-page 337
PIC16(L)F1782/3
27.6.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
27.6 EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for synchronous slave transmission
(see Section 27.5.2.2 “Synchronous Slave
Transmission Set-up:”).
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
• The TXIF interrupt flag must be cleared by writing
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
27.6.1
SYNCHRONOUS RECEIVE DURING
SLEEP
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON reg-
ister.
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 27.5.2.4 “Synchronous Slave
Reception Set-up:”).
• Interrupt enable bits TXIE of the PIE1 register and
PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
• If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• The RCIF interrupt flag must be cleared by read-
ing RCREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the
SLEEPinstruction will be executed. If the Global Inter-
rupt Enable (GIE) bit of the INTCON register is also set,
then the Interrupt Service Routine at address 004h will
be called.
27.6.3
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 13.1 “Alternate Pin Function” for
more information.
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PIC16(L)F1782/3
28.3 Common Programming Interfaces
28.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin, 6
connector) configuration. See Figure 28-1.
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
FIGURE 28-1:
ICD RJ-11 STYLE
CONNECTOR INTERFACE
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
ICSPDAT
• VSS
NC
2 4 6
VDD
In Program/Verify mode the program memory, user IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is
bidirectional I/O used for transferring the serial data
and the ICSPCLK pin is the clock input. For more
information on ICSP™ refer to the “PIC16(L)F178X
Memory Programming Specification” (DS41457).
ICSPCLK
1 3
5
Target
PC Board
Bottom Side
a
VPP/MCLR
VSS
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
28.1 High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
5 = ICSPCLK
6 = No Connect
28.2 Low-Voltage Programming Entry
Mode
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 28-2.
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’.
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 28-3 for more
information.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2.
A
32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 5.5 “MCLR” for more
information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
2011-2014 Microchip Technology Inc.
DS40001579E-page 339
PIC16(L)F1782/3
FIGURE 28-2:
PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
1
2
3
4
5
6
5 = ICSPCLK
6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
FIGURE 28-3:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
VSS
MCLR/VPP
VSS
Data
ICSPDAT
ICSPCLK
Clock
*
*
*
To Normal Connections
Isolation devices (as required).
*
DS40001579E-page 340
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
29.1 Read-Modify-Write Operations
29.0 INSTRUCTION SET SUMMARY
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
Each instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most
varied instruction word format.
TABLE 29-1: OPCODE FIELD
DESCRIPTIONS
Table 29-3 lists the instructions recognized by the
MPASMTM assembler.
Field
Description
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
k
x
Don’t care location (= 0or 1).
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
TABLE 29-2: ABBREVIATION
DESCRIPTIONS
Field
Description
PC
TO
C
Program Counter
Time-out bit
Carry bit
DC
Z
Digit carry bit
Zero bit
PD
Power-down bit
2011-2014 Microchip Technology Inc.
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PIC16(L)F1782/3
FIGURE 29-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
7 6
0
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLPinstruction only
13
7
6
0
0
OPCODE
k (literal)
k = 7-bit immediate value
MOVLBinstruction only
13
5 4
OPCODE
k (literal)
k = 5-bit immediate value
BRAinstruction only
13
9
8
0
OPCODE
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
7
6
5
0
0
OPCODE
n
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSRIncrement instructions
13
3
2
n
1
OPCODE
m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
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PIC16(L)F1782/3
TABLE 29-3: INSTRUCTION SET
14-Bit Opcode
Status
Mnemonic,
Operands
Description
Cycles
Notes
Affected
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC f, d
ANDWF
ASRF
LSLF
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C, DC, Z
11 1101 dfff ffff C, DC, Z
00 0101 dfff ffff Z
11 0111 dfff ffff C, Z
11 0101 dfff ffff C, Z
11 0110 dfff ffff C, Z
2
2
2
2
2
2
2
f, d
f, d
f, d
f, d
f
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB f, d
SWAPF
XORWF
00 0001 lfff ffff
00 0001 0000 00xx
00 1001 dfff ffff
00 0011 dfff ffff
00 1010 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 1fff ffff
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
Z
Z
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
2
2
2
2
2
2
2
2
2
2
2
2
C
C
00 0010 dfff ffff C, DC, Z
11 1011 dfff ffff C, DC, Z
00 1110 dfff ffff
f, d
f, d
00 0110 dfff ffff
Z
BYTE ORIENTED SKIP OPERATIONS
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00
1011 dfff ffff
1111 dfff ffff
1, 2
1, 2
DECFSZ
INCFSZ
BIT-ORIENTED FILE REGISTER OPERATIONS
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
BCF
BSF
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1, 2
1, 2
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110 kkkk kkkk C, DC, Z
1001 kkkk kkkk
1000 kkkk kkkk
0000 001k kkkk
0001 1kkk kkkk
0000 kkkk kkkk
Z
Z
Subtract W from literal
Exclusive OR literal with W
1100 kkkk kkkk C, DC, Z
1010 kkkk kkkk
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
2011-2014 Microchip Technology Inc.
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PIC16(L)F1782/3
TABLE 29-3: INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k kkkk kkkk
0000 0000 1011
0kkk kkkk kkkk
0000 0000 1010
1kkk kkkk kkkk
0000 0000 1001
0100 kkkk kkkk
0000 0000 1000
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
00
00
00
00
00
00
0000 0110 0100 TO, PD
0000 0000 0000
0000 0110 0010
0000 0000 0001
0000 0110 0011 TO, PD
0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
1
1
11 0001 0nkk kkkk
00 0000 0001 0nmm
MOVIW
n mm
Z
Z
2, 3
k[n]
n mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
1
1
11 1111 0nkk kkkk
00 0000 0001 1nmm
2
2, 3
MOVWI
k[n]
Move W to INDFn, Indexed Indirect.
1
11 1111 1nkk kkkk
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
DS40001579E-page 344
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
29.2 Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
-32 k 31
n [ 0, 1]
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
FSR(n) + k FSR(n)
Z
Status Affected:
Description:
None
The contents of W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ANDWF
AND W with f
ADDLW
Add literal and W
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] ADDLW
0 k 255
k
Operands:
0 f 127
d 0,1
Operands:
Operation:
Status Affected:
Description:
(W) + k (W)
C, DC, Z
Operation:
(W) .AND. (f) (destination)
Status Affected:
Description:
Z
The contents of the W register are
added to the 8-bit literal ‘k’ and the
result is placed in the W register.
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
ADDWF
Add W and f
Syntax:
[ label ] ASRF f {,d}
Syntax:
[ label ] ADDWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d 0,1
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Operation:
(W) + (f) (destination)
Status Affected:
Description:
C, DC, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
ADDWFC
ADD W and CARRY bit to f
C
register f
Syntax:
[ label ] ADDWFC
f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(W) + (f) + (C) dest
Status Affected:
Description:
C, DC, Z
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
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BTFSC
Bit Test f, Skip if Clear
BCF
Bit Clear f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] BCF f,b
Operands:
0 f 127
0 b 7
Operands:
0 f 127
0 b 7
Operation:
skip if (f<b>) = 0
Operation:
0 (f<b>)
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
Bit ‘b’ in register ‘f’ is cleared.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOPis
executed instead, making this a
2-cycle instruction.
BTFSS
Bit Test f, Skip if Set
BRA
Relative Branch
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Operands:
0 f 127
0 b < 7
Operands:
-256 label - PC + 1 255
-256 k 255
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOPis
executed instead, making this a
2-cycle instruction.
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a 2-cycle instruc-
tion. This branch has a limited range.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
None
Operands:
Operation:
Status Affected:
Description:
(PC) + (W) PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a 2-cycle instruc-
tion.
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0 f 127
0 b 7
Operation:
1 (f<b>)
Status Affected:
Description:
None
Bit ‘b’ in register ‘f’ is set.
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CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL
0 k 2047
k
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
Description:
None
Status Affected:
Description:
TO, PD
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a 2-cycle instruc-
tion.
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
COMF
Complement f
CALLW
Subroutine Call With W
Syntax:
[ label ] COMF f,d
Syntax:
[ label ] CALLW
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
(PC) +1 TOS,
(W) PC<7:0>,
Operation:
(f) (destination)
(PCLATH<6:0>) PC<14:8>
Status Affected:
Description:
Z
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Status Affected:
Description:
None
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLWis a 2-cycle
instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] CLRF
0 f 127
f
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h (f)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.
The contents of register ‘f’ are cleared
and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h (W)
1 Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z) is
set.
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DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
Description:
None
Status Affected:
Description:
None
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOPis executed instead, making it a
2-cycle instruction.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOPis
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO
0 k 2047
k
Syntax:
[ label ] IORLW
0 k 255
(W) .OR. k (W)
Z
k
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<6:3> PC<14:11>
Status Affected:
Description:
None
The contents of the W register are
OR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
GOTOis an unconditional branch. The
11-bit immediate value is loaded into
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ] INCF f,d
Syntax:
[ label ] IORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
(W) .OR. (f) (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
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LSLF
Logical Left Shift
MOVF
Move f
Syntax:
[ label ] LSLF f {,d}
Syntax:
[ label ] MOVF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
Operation:
(f) (dest)
(f<6:0>) dest<7:1>
0 dest<0>
Status Affected:
Description:
Z
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1is useful to test a
file register since status flag Z is
affected.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Words:
1
1
C
register f
0
Cycles:
Example:
MOVF
FSR, 0
After Instruction
LSRF
Logical Right Shift
W
Z
=
=
value in FSR register
1
Syntax:
[ label ] LSRF f {,d}
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0
C
register f
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MOVIW
Move INDFn to W
MOVLP
Move literal to PCLATH
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
Syntax:
[ label ] MOVLP
0 k 127
k PCLATH
None
k
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
The 7-bit literal ‘k’ is loaded into the
PCLATH register.
INDFn W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
MOVLW
Move literal to W
Syntax:
[ label ] MOVLW
0 k 255
k (W)
k
Operands:
Operation:
Status Affected:
Description:
None
The 8-bit literal ‘k’ is loaded into W reg-
ister. The “don’t cares” will assemble as
‘0’s.
Status Affected:
Z
Words:
1
1
Cycles:
Example:
Mode
Syntax
mm
00
01
10
11
MOVLW
0x5A
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
After Instruction
W
=
0x5A
MOVWF
Move W to f
[ label ] MOVWF
0 f 127
(W) (f)
Syntax:
f
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Operands:
Operation:
Status Affected:
Description:
None
Move data from W register to register
‘f’.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
Words:
1
1
Cycles:
Example:
MOVWF
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
OPTION_REG
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
After Instruction
OPTION_REG = 0x4F
W = 0x4F
MOVLB
Move literal to BSR
Syntax:
[ label ] MOVLB
0 k 31
k BSR
None
k
Operands:
Operation:
Status Affected:
Description:
The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
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NOP
No Operation
[ label ] NOP
None
MOVWI
Move W to INDFn
Syntax:
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Operands:
Operation:
No operation
Status Affected:
Description:
Words:
None
No operation.
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
1
Cycles:
1
W INDFn
Example:
NOP
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
Unchanged
Load OPTION_REG Register
with W
OPTION
Syntax:
[ label ] OPTION
None
Operands:
Operation:
Status Affected:
Description:
Status Affected:
None
(W) OPTION_REG
None
Mode
Syntax
mm
00
01
10
11
Move data from W register to
OPTION_REG register.
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
Words:
1
Cycles:
Example:
1
OPTION
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
Operation:
None
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
Execute a device Reset. Resets the
RI flag of the PCON register.
Status Affected:
Description:
None
This instruction provides a way to
execute a hardware Reset by soft-
ware.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
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RETURN
Return from Subroutine
RETFIE
Syntax:
Return from Interrupt
[ label ] RETFIE
None
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
TOS PC
None
TOS PC,
1 GIE
Status Affected:
Description:
None
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a 2-cycle instruction.
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Words:
1
Cycles:
Example:
2
RETFIE
After Interrupt
PC
=
TOS
GIE =
1
RETLW
Syntax:
Return with literal in W
RLF
Rotate Left f through Carry
[ label ] RETLW
0 k 255
k
Syntax:
Operands:
[ label ]
RLF f,d
Operands:
Operation:
0 f 127
d [0,1]
k (W);
TOS PC
Operation:
See description below
C
Status Affected:
Description:
None
Status Affected:
Description:
The W register is loaded with the 8-bit
literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a 2-cycle
instruction.
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words:
1
2
C
Register f
Cycles:
Example:
CALL TABLE;W contains table
;offset value
Words:
1
1
Cycles:
Example:
•
•
•
;W now has table value
TABLE
RLF
REG1,0
Before Instruction
ADDWF PC ;W = offset
RETLW k1 ;Begin table
REG1
C
=
=
1110 0110
0
RETLW k2
;
After Instruction
•
•
•
REG1
W
C
=
=
=
1110 0110
1100 1100
1
RETLW kn ; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
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SUBLW
Subtract W from literal
RRF
Rotate Right f through Carry
Syntax:
[ label ] SUBLW
0 k 255
k
Syntax:
[ label ] RRF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 f 127
d [0,1]
k - (W) W)
C, DC, Z
Operation:
See description below
C
The W register is subtracted (2’s com-
plement method) from the 8-bit literal
‘k’. The result is placed in the W regis-
ter.
Status Affected:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
C = 0
W k
C = 1
W k
C
Register f
DC = 0
DC = 1
W<3:0> k<3:0>
W<3:0> k<3:0>
SUBWF
Subtract W from f
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Syntax:
[ label ] SUBWF f,d
Syntax:
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
Operation:
(f) - (W) destination)
Status Affected:
Description:
C, DC, Z
0 PD
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
Status Affected:
Description:
TO, PD
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
C = 0
W f
The processor is put into Sleep mode
with the oscillator stopped.
C = 1
W f
DC = 0
DC = 1
W<3:0> f<3:0>
W<3:0> f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(f) – (W) – (B) dest
Status Affected:
Description:
C, DC, Z
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
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SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW
0 k 255
k
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k W)
Z
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
The contents of the W register are
XOR’ed with the 8-bit
literal ‘k’. The result is placed in the
W register.
Status Affected:
Description:
None
The upper and lower nibbles of regis-
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
XORWF
Exclusive OR W with f
TRIS
Load TRIS Register with W
Syntax:
[ label ] XORWF f,d
Syntax:
[ label ] TRIS f
5 f 7
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) TRIS register ‘f’
None
Operation:
(W) .XOR. (f) destination)
Status Affected:
Description:
Z
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.
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30.0 ELECTRICAL SPECIFICATIONS
(†)
30.1 Absolute Maximum Ratings
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F1782/3 ........................................................................................................... -0.3V to +6.5V
PIC16LF1782/3 ......................................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C TA +85°C .............................................................................................................. 170 mA
-40°C TA +125°C .............................................................................................................. 70 mA
on VDD pin(1)
-40°C TA +85°C ................................................................................................................ 85 mA
-40°C TA +125°C .............................................................................................................. 35 mA
on any I/O pin ..................................................................................................................................... 25 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Section 30.4 “Thermal
Considerations” to calculate device specifications.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
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30.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
VDDMIN VDD VDDMAX
TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF1782/3
VDDMIN (Fosc 16 MHz).......................................................................................................... +1.8V
VDDMIN (16 MHz < Fosc 32 MHz) ......................................................................................... +2.7V
VDDMAX .................................................................................................................................... +3.6V
PIC16F1782/3
VDDMIN (Fosc 16 MHz).......................................................................................................... +2.3V
VDDMIN (16 MHz < Fosc 32 MHz) ......................................................................................... +2.7V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1: See Parameter D001, DC Characteristics: Supply Voltage.
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PIC16(L)F1782/3
FIGURE 30-1:
PIC16F1782/3 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
5.5
2.7
2.3
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-6 for each Oscillator mode’s supported frequencies.
FIGURE 30-2:
PIC16LF1782/3 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
3.6
2.7
1.8
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-6 for each Oscillator mode’s supported frequencies.
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PIC16(L)F1782/3
30.3
DC Characteristics
TABLE 30-1: SUPPLY VOLTAGE
PIC16LF1782/3
Standard Operating Conditions (unless otherwise stated)
PIC16F1782/3
Param
. No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
D001
VDD
Supply Voltage (VDDMIN, VDDMAX)
1.8
2.7
—
—
3.6
3.6
V
V
FOSC 16 MHz:
FOSC 32 MHz (Note 2)
D001
2.3
2.7
—
—
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 32 MHz (Note 2)
(1)
D002* VDR
D002*
RAM Data Retention Voltage
1.5
1.7
—
—
—
—
—
—
V
V
V
Device in Sleep mode
Device in Sleep mode
VPOR*
Power-on Reset Release Voltage
Power-on Reset Rearm Voltage
1.6
VPORR*
—
—
0.8
1.5
—
—
—
4
V
V
Device in Sleep mode
Device in Sleep mode
1.024V, VDD 2.5V
2.048V, VDD 2.5V
4.096V, VDD 4.75V
D003
VFVR
Fixed Voltage Reference
Voltage
-4
%
%
%
(3)
-4
—
4
-5
—
5
D004* SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
—
—
V/ms See Section 5.1 “Power-On Reset
(POR)” for details.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: PLL required for 32 MHz operation.
3: Industrial temperature range only.
DS40001579E-page 358
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
FIGURE 30-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
(2)
(3)
TPOR
TVLOW
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.
2011-2014 Microchip Technology Inc.
DS40001579E-page 359
PIC16(L)F1782/3
TABLE 30-2: SUPPLY VOLTAGE (IDD)(1,2)
PIC16LF1782/3
Standard Operating Conditions (unless otherwise stated)
PIC16F1782/3
Conditions
Note
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
LDO Regulator
D009
—
—
—
75
15
—
—
—
A
A
A
—
—
—
High-Power mode, normal operation
Sleep VREGCON<1> = 0
0.3
Sleep VREGCON<1> = 1
D010
D010
—
—
8
20
24
A
A
1.8
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40°C TA +85°C
12
—
—
—
—
—
—
—
—
18
20
63
74
A
A
A
A
A
A
A
A
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
FOSC = 32 kHz
LP Oscillator mode (Note 4, 5),
-40°C TA +85°C
22
79
D012
D012
160
320
260
330
380
650
1000
700
1100
1300
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode (Note 5)
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP.
6: 8 MHz crystal oscillator with 4x PLL enabled.
DS40001579E-page 360
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 30-2: SUPPLY VOLTAGE (IDD)(1,2) (CONTINUED)
PIC16LF1782/3
Standard Operating Conditions (unless otherwise stated)
PIC16F1782/3
Conditions
Note
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
D014
—
—
125
280
550
A
A
1.8
3.0
FOSC = 4 MHz
EC Oscillator mode
Medium-Power mode
1100
D014
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
220
290
350
2.1
2.5
2.1
2.2
130
150
150
170
220
0.8
1.2
1.0
1.3
1.4
2.1
2.5
2.1
2.2
2.1
2.5
2.1
2.2
650
1000
1200
6.2
A
A
2.3
3.0
5.0
3.0
3.6
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
3.0
3.6
3.0
5.0
3.0
3.6
3.0
5.0
FOSC = 4 MHz
EC Oscillator mode (Note 5)
Medium-Power mode
A
D015
D015
D017
D017
mA
mA
mA
mA
A
FOSC = 32 MHz
EC Oscillator High-Power mode
7.5
6.5
FOSC = 32 MHz
EC Oscillator High-Power mode (Note 5)
7.5
180
250
250
330
430
2.2
FOSC = 500 kHz
MFINTOSC mode
A
A
FOSC = 500 kHz
MFINTOSC mode (Note 5)
A
A
D019
D019
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
FOSC = 16 MHz
HFINTOSC mode
3.7
2.3
FOSC = 16 MHz
HFINTOSC mode (Note 5)
3.9
4.1
D020
D020
D022
D022
6.2
FOSC = 32 MHz
HFINTOSC mode
7.5
6.5
FOSC = 32 MHz
HFINTOSC mode
7.5
6.2
FOSC = 32 MHz
HS Oscillator mode (Note 6)
7.5
6.5
FOSC = 32 MHz
HS Oscillator mode (Note 5, 6)
7.5
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP.
6: 8 MHz crystal oscillator with 4x PLL enabled.
2011-2014 Microchip Technology Inc.
DS40001579E-page 361
PIC16(L)F1782/3
TABLE 30-3: POWER-DOWN CURRENTS (IPD)(1,2,4)
Operating Conditions: (unless otherwise stated)
Low-Power Sleep Mode
PIC16LF1782/3
PIC16F1782/3
Param
Low-Power Sleep Mode, VREGPM = 1
Conditions
Note
Max.
+85°C +125°C
Max.
Device Characteristics
Min.
Typ†
Units
No.
VDD
(2)
Power-down Base Current (IPD)
D023
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.05
0.08
0.3
0.4
0.5
0.5
0.8
0.8
0.9
1.0
15
1.0
2.0
3
8.0
9.0
11
12
15
14
17
15
20
22
30
33
35
37
39
28
28
31
10
14
17
9
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
3.0
3.0
5.0
3.0
3.0
5.0
1.8
3.0
2.3
3.0
5.0
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
D023
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
4
6
D024
D024
6
LPWDT Current
LPWDT Current
7
6
7
8
D025
D025
28
30
33
35
37
25
25
28
4
FVR Current
FVR Current
18
18
19
20
D026
D026
7.5
40
BOR Current
BOR Current
87
D027
D027
0.5
0.8
1
LPBOR Current
LPBOR Current
6
8
D028
D028
0.5
0.8
1.1
1.3
1.4
5
SOSC Current
SOSC Current
8.5
6
12
10
20
25
8.5
10
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled.
The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should
be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC oscillator source is FRC.
4: 0.1 F capacitor on VCAP.
5: VREGPM = 0.
DS40001579E-page 362
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 30-3: POWER-DOWN CURRENTS (IPD)(1,2,4) (CONTINUED)
Operating Conditions: (unless otherwise stated)
Low-Power Sleep Mode
PIC16LF1782/3
PIC16F1782/3
Param
Low-Power Sleep Mode, VREGPM = 1
Conditions
Note
Max.
+85°C +125°C
Max.
Device Characteristics
Min.
Typ†
Units
No.
VDD
(2)
Power-down Base Current (IPD)
D029
—
—
—
—
—
—
—
—
—
—
—
0.05
0.08
0.3
2
3
9
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
3.0
3.0
5.0
1.8
3.0
2.3
3.0
5.0
ADC Current (Note 3),
no conversion in progress
10
12
13
16
—
—
—
—
—
—
—
—
—
—
—
—
—
D029
4
ADC Current (Note 3),
no conversion in progress
0.4
5
0.5
7
D030
D030
250
280
230
250
350
250
250
350
250
300
280
300
310
—
ADC Current (Note 3),
conversion in progress
—
—
ADC Current (Note 3, Note 4,
Note 5), conversion in progress
—
—
D031
D031
650
650
650
650
700
650
700
700
Op Amp (High power)
Op Amp (High power) (Note 5)
—
—
—
—
—
—
D032
D032
Comparator, Normal-Power mode
Comparator, Normal-Power mode
(Note 5)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled.
The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should
be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC oscillator source is FRC.
4: 0.1 F capacitor on VCAP.
5: VREGPM = 0.
2011-2014 Microchip Technology Inc.
DS40001579E-page 363
PIC16(L)F1782/3
TABLE 30-4: I/O PORTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
VIL
Input Low Voltage
I/O PORT:
D034
D034A
D035
with TTL buffer
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.8
V
V
V
V
V
V
V
4.5V VDD 5.5V
0.15 VDD
0.2 VDD
0.3 VDD
0.8
1.8V VDD 4.5V
2.0V VDD 5.5V
with Schmitt Trigger buffer
with I2C™ levels
with SMBus levels
MCLR, OSC1 (RC mode)(1)
OSC1 (HS mode)
Input High Voltage
I/O ports:
2.7V VDD 5.5V
D036
0.2 VDD
0.3 VDD
D036A
VIH
D040
with TTL buffer
2.0
—
—
—
—
V
V
4.5V VDD 5.5V
1.8V VDD 4.5V
D040A
0.25 VDD +
0.8
D041
with Schmitt Trigger buffer
with I2C™ levels
with SMBus levels
MCLR
0.8 VDD
0.7 VDD
2.1
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
2.0V VDD 5.5V
2.7V VDD 5.5V
D042
0.8 VDD
0.7 VDD
0.9 VDD
D043A
D043B
OSC1 (HS mode)
OSC1 (RC mode)
(Note 1)
(2)
IIL
Input Leakage Current
D060
I/O ports
—
—
± 5
± 125
nA
VSS VPIN VDD, Pin at
high-impedance @ 85°C
± 5
± 1000
± 200
nA 125°C
D061
MCLR(3)
± 50
nA
A
V
VSS VPIN VDD @ 85°C
IPUR
VOL
Weak Pull-up Current
D070*
25
25
100
140
200
300
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
(4)
Output Low Voltage
D080
I/O ports
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
—
—
—
0.6
—
(4)
VOH
Output High Voltage
D090
I/O ports
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
VDD - 0.7
V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
DS40001579E-page 364
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 30-4: I/O PORTS (CONTINUED)
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ†
—
Max.
15
Units
pF
Conditions
Capacitive Loading Specs on Output Pins
D101*
COSC2 OSC2 pin
—
—
In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO
All I/O pins
—
50
pF
VCAP Capacitor Charging
Charging current
D102
—
—
200
0.0
—
—
A
mA
D102A
Source/sink capability when
charging complete
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
2011-2014 Microchip Technology Inc.
DS40001579E-page 365
PIC16(L)F1782/3
TABLE 30-5: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
No.
Program Memory
Programming Specifications
D110
D111
VIHH
IDDP
Voltage on MCLR/VPP/RE3 pin
8.0
—
—
—
9.0
10
V
(Note 3)
Supply Current during
Programming
mA
VDD for Bulk Erase
2.7
—
—
VDDMAX
VDDMAX
V
V
D112
D113
VPEW
VDD for Write or Row Erase
VDDMIN
IPPPGM Current on MCLR/VPP during
Erase/Write
—
—
1.0
mA
D114
D115
IDDPGM Current on VDD during Erase/Write
—
5.0
mA
Data EEPROM Memory
—
—
D116
D117
D118
D119
ED
Byte Endurance
100K
VDDMIN
—
—
VDDMAX
5.0
E/W -40C to +85C
VDRW VDD for Read/Write
V
TDEW Erase/Write Cycle Time
TRETD Characteristic Retention
4.0
40
ms
—
—
Year Provided no other
specifications are violated
D120
TREF
Number of Total Erase/Write
Cycles before Refresh
100k
—
—
E/W -40°C to +85°C
(2)
Program Flash Memory
Cell Endurance
—
—
2
D121
D122
D123
D124
EP
10K
VDDMIN
—
—
VDDMAX
2.5
E/W -40C to +85C (Note 1)
VPR
TIW
VDD for Read
V
Self-timed Write Cycle Time
ms
TRETD Characteristic Retention
—
40
—
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Refer to Section 12.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Required only if single-supply programming is disabled.
DS40001579E-page 366
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
30.4 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Typ.
Units
Conditions
28-pin SPDIP package
TH01
JA
Thermal Resistance Junction to Ambient
60
80
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C
28-pin SOIC package
90
28-pin SSOP package
27.5
27.5
31.4
24
28-pin UQFN 4x4mm package
28-pin QFN 6x6mm package
28-pin SPDIP package
TH02
JC
Thermal Resistance Junction to Case
28-pin SOIC package
24
28-pin SSOP package
24
28-pin UQFN 4x4mm package
28-pin QFN 6x6mm package
24
TH03
TH04
TH05
TH06
TH07
TJMAX
PD
Maximum Junction Temperature
Power Dissipation
150
—
W
PD = PINTERNAL + PI/O
(1)
PINTERNAL Internal Power Dissipation
—
W
PINTERNAL = IDD x VDD
PI/O
I/O Power Dissipation
Derated Power
—
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
(2)
PDER
—
W
PDER = PDMAX (TJ - TA)/JA
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
2011-2014 Microchip Technology Inc.
DS40001579E-page 367
PIC16(L)F1782/3
30.5 AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O PORT
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 30-4:
LOAD CONDITIONS
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins
DS40001579E-page 368
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
FIGURE 30-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 30-6: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
No.
OS01
FOSC
External CLKIN Frequency(1)
DC
DC
DC
—
—
—
0.5
4
MHz EC Oscillator mode (low)
MHz EC Oscillator mode (medium)
MHz EC Oscillator mode (high)
—
20
—
4
Oscillator Frequency(1)
32.768
—
kHz
LP Oscillator mode
0.1
1
MHz XT Oscillator mode
—
4
MHz HS Oscillator mode
1
—
20
4
MHz HS Oscillator mode, VDD > 2.7V
MHz RC Oscillator mode, VDD > 2.0V
DC
27
250
50
50
—
—
OS02
TOSC
External CLKIN Period(1)
Oscillator Period(1)
—
s
ns
ns
ns
s
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
TCY = 4/FOSC
—
—
—
30.5
—
—
10,000
1,000
—
DC
—
—
—
250
50
250
200
2
—
—
OS03
TCY
Instruction Cycle Time(1)
TCY
—
OS04*
TosH,
TosL
External CLKIN High,
External CLKIN Low
LP oscillator
100
20
0
—
XT oscillator
—
HS oscillator
OS05*
TosR,
TosF
External CLKIN Rise,
External CLKIN Fall
—
LP oscillator
0
—
XT oscillator
0
—
HS oscillator
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2011-2014 Microchip Technology Inc.
DS40001579E-page 369
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TABLE 30-7: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Freq.
Tolerance
Sym.
Characteristic
Min. Typ† Max. Units
Conditions
OS08
HFOSC
Internal Calibrated HFINTOSC
Frequency(2)
±2%
±3%
—
—
16.0
16.0
—
—
MHz 0°C TA +60°C, VDD 2.5V
MHz 60°C TA 85°C, VDD 2.5V
±5%
—
16.0
—
MHz -40°C TA +125°C
OS08A MFOSC Internal Calibrated MFINTOSC
Frequency(2)
±2%
±3%
—
—
500
500
—
—
kHz 0°C TA +60°C, VDD 2.5V
kHz 60°C TA 85°C, VDD 2.5V
±5%
—
—
—
—
500
31
—
—
8
kHz -40°C TA +125°C
kHz -40°C TA +125°C
OS09
OS10* TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
LFOSC
Internal LFINTOSC Frequency
—
3.2
s
VREGPM = 0
MFINTOSC
Wake-up from Sleep Start-up Time
—
—
24
35
s
VREGPM = 0
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
FIGURE 30-6:
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
± 5%
125
85
60
25
± 3%
± 2%
0
-20
± 5%
-40
1.8
2.0
2.5
3.5
4.0
VDD (V)
4.5
5.0
5.5
3.0
DS40001579E-page 370
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 30-8: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units Conditions
F10
FOSC Oscillator Frequency Range
4
16
—
—
—
—
8
32
MHz
MHz
ms
F11
FSYS On-Chip VCO System Frequency
F12
F13*
TRC
PLL Start-up Time (Lock Time)
—
2
CLK CLKOUT Stability (Jitter)
-0.25%
+0.25%
%
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 30-7:
CLKOUT AND I/O TIMING
Cycle
Write
Q4
Fetch
Q1
Read
Q2
Execute
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS13
OS18
OS16
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
2011-2014 Microchip Technology Inc.
DS40001579E-page 371
PIC16(L)F1782/3
TABLE 30-9: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
OS11 TosH2ckL FOSC to CLKOUT (1)
OS12 TosH2ckH FOSC to CLKOUT (1)
OS13 TckL2ioV CLKOUT to Port out valid(1)
—
—
—
—
—
—
70
72
20
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
ns
OS14 TioV2ckH Port input valid before CLKOUT(1)
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid
TOSC + 200 ns
—
50
—
—
70*
—
ns
—
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
OS16 TosH2ioI
Fosc (Q2 cycle) to Port input invalid
50
(I/O in hold time)
OS17 TioV2osH Port input valid to Fosc(Q2 cycle)
20
—
—
ns
(I/O in setup time)
OS18* TioR
OS19* TioF
Port output rise time
—
—
40
15
72
32
ns
ns
VDD = 1.8V
VDD = 3.3-5.0V
Port output fall time
—
—
28
15
55
30
VDD = 1.8V
VDD = 3.3-5.0V
OS20* Tinp
OS21* Tioc
INT pin input high or low time
25
25
—
—
—
—
ns
ns
Interrupt-on-change new input level
time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS40001579E-page 372
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
FIGURE 30-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 30-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
TPWRT
Reset
33(1)
(due to BOR)
Note 1: The delay, (TPWRT) releasing Reset, only occurs when the Power-up Timer is enabled, (PWRTE = 0).
2011-2014 Microchip Technology Inc.
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PIC16(L)F1782/3
TABLE 30-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
TMCL
Characteristic
Min. Typ† Max. Units
Conditions
No.
30
MCLR Pulse Width (low)
2
5
—
—
—
—
s VDD = 3.3-5V, -40°C to +85°C
s VDD = 3.3-5V
31
TWDTLP Low-Power Watchdog Timer
Time-out Period
10
16
27
ms VDD = 3.3V-5V
1:16 Prescaler used
32
TOST
Oscillator Start-up Timer Period(1), (2)
—
1024
65
—
140
2.0
Tosc (Note 3)
33*
34*
TPWRT Power-up Timer Period, PWRTE = 0 40
ms
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
—
—
s
35
VBOR
Brown-out Reset Voltage
2.55 2.70 2.85
2.30 2.45 2.6
1.80 1.90 2.10
V
V
V
BORV = 0
BORV=1 (F device)
BORV=1 (LF device)
35A
36*
37*
VLPBOR Low-Power Brown-out
Brown-out Reset Hysteresis
1.8
0
2.1
25
3
2.5
75
5
V
LPBOR = 1
VHYST
mV -40°C to +85°C
TBORDC Brown-out Reset DC Response
Time
1
s VDD VBOR
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
DS40001579E-page 374
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
FIGURE 30-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 30-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
TT0H
Characteristic
Min.
Typ†
Max.
Units
Conditions
No.
40*
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45*
TT1H
T1CKI High Synchronous, No Prescaler
0.5 TCY + 20
15
—
—
—
—
ns
ns
Time
Synchronous,
with Prescaler
Asynchronous
30
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
46*
47*
TT1L
TT1P
T1CKI Low Synchronous, No Prescaler
0.5 TCY + 20
Time
Synchronous, with Prescaler
Asynchronous
15
30
T1CKI Input Synchronous
Period
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
—
—
ns
48
FT1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
32.4
32.768 33.1
kHz
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC
—
7 TOSC
—
Timers in Sync
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2011-2014 Microchip Technology Inc.
DS40001579E-page 375
PIC16(L)F1782/3
FIGURE 30-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)
CC01
CC02
CC03
Note: Refer to Figure 30-5 for load conditions.
TABLE 30-12: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
CC01* TccL CCPx Input Low Time
CC02* TccH CCPx Input High Time
CC03* TccP CCPx Input Period
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
20
0.5TCY + 20
20
3TCY + 40
N
ns N = prescale value (1, 4 or 16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS40001579E-page 376
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 30-13: ADC CONVERTER (ADC) 12-BIT DIFFERENTIAL CHARACTERISTICS:
Operating Conditions
VDD = 3V, Temp. = 25°C, Single-ended 2 s TAD, VREF+ = 3V, VREF- = VSS
Param
No.
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
AD01 NR
AD02 EIL
AD03 EDL
Resolution
—
—
—
—
—
1.8
—
—
—
±1
±1
±1
±1
—
—
—
10
±1.6
±1.4
±3.5
±2
bit
Integral Error
LSb
Differential Error
LSb No missing codes
AD04 EOFF Offset Error
LSb
LSb
AD05 EGN Gain Error
AD06 VREF Reference Voltage(3)
VDD
VREF
10
V
V
VREF = (VREF+ minus VREF-) (Note 5)
AD07 VAIN Full-Scale Range
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
Can go higher if external 0.01F capacitor is
present on input pin.
k
AD09 NR
AD10 EIL
AD11 EDL
Resolution
—
—
—
—
—
1.8
—
—
—
±2
±2
±1
±1
—
—
—
12
—
bit
LSb
LSb
LSb
LSb
V
Integral Error
Differential Error
—
AD12 EOFF Offset Error
—
AD13 EGN Gain Error
AD14 VREF Reference Voltage(3)
—
VDD
VREF
10
VREF = (VREF+ minus VREF-) (Note 5)
AD15 VAIN Full-Scale Range
V
AD16 ZAIN Recommended Impedance of
Analog Voltage Source
Can go higher if external 0.01F capacitor is
present on input pin.
k
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
5: FVR voltage selected must be 2.048V or 4.096V.
TABLE 30-14: ADC CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
ADC Clock Period
Min.
Typ†
Max. Units
Conditions
AD130* TAD
1.0
1.0
—
9.0
6.0
s
s
TOSC-based
ADCS<1:0> = 11(ADRC mode)
ADC Internal RC Oscillator
Period
2.5
AD131 TCNV Conversion Time (not including
Acquisition Time)(1)
—
15 (12-bit)
13 (10-bit)
—
—
TAD Set GO/DONE bit to conversion
complete
AD132* TACQ Acquisition Time
—
5.0
s
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
2011-2014 Microchip Technology Inc.
DS40001579E-page 377
PIC16(L)F1782/3
FIGURE 30-12:
ADC CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 Tcy
AD134
Q4
(TOSC/2(1)
)
AD131
AD130
ADC CLK
7
6
5
4
3
2
1
0
ADC Data
ADRES
NEW_DATA
1 Tcy
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This
allows the SLEEPinstruction to be executed.
FIGURE 30-13:
ADC CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
Q4
(1)
(TOSC/2 + TCY
1 Tcy
)
AD131
AD130
ADC CLK
ADC Data
7
6
5
3
2
1
0
4
NEW_DATA
1 Tcy
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This
allows the SLEEPinstruction to be executed.
DS40001579E-page 378
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 30-15: OPERATIONAL AMPLIFIER (OPA)
Standard Operating Conditions (unless otherwise stated):
VDD = 3.0 Temperature 25°C, High-Power Mode
DC CHARACTERISTICS
Param.
Symbol
No.
Parameters
Min.
Typ.
Max.
Units
Conditions
OPA01* GBWP Gain Bandwidth Product
—
—
—
—
—
55
—
0
2
—
—
MHz
s
High-Power mode
OPA02*
OPA03*
OPA04*
OPA05
OPA06
OPA07*
OPA08
TON
PM
Turn on Time
Phase Margin
Slew Rate
Offset
10
40
3
—
degrees
V/s
mV
SR
—
OFF
±3
70
90
—
80
±9
—
CMRR Common Mode Rejection Ratio
dB
AOL
Open Loop Gain
—
dB
VICM
Input Common Mode Voltage
VDD
—
V
VDD > 2.5
OPA09* PSRR Power Supply Rejection Ratio
—
dB
TABLE 30-16: COMPARATOR SPECIFICATIONS
Operating Conditions: VDD = 3.0V, Temperature = 25°C (unless otherwise stated).
Param.
Sym.
Characteristics
Min.
Typ.
Max. Units
Comments
No.
CM01
VIOFF
Input Offset Voltage
—
±2.5
±9
mV Normal-Power mode
VICM = VDD/2
CM02
CM03
CM04A
VICM
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time Rising Edge
0
—
50
60
VDD
—
V
CMRR
40
—
dB
125
ns Normal-Power mode
measured at VDD/2 (Note 1)
CM04B
CM04C
CM04D
CM05
Response Time Falling Edge
Response Time Rising Edge
Response Time Falling Edge
—
—
—
—
20
60
85
85
—
45
110
—
ns Normal-Power mode
measured at VDD/2 (Note 1)
TRESP
ns Low-Power mode measured
at VDD/2 (Note 1)
—
ns Low-Power mode measured
at VDD/2 (Note 1)
Tmc2ov Comparator Mode Change to
Output Valid*
10
75
s
CM06
CHYSTER Comparator Hysteresis
mV Hystersis ON, High Power
measured at VDD/2 (Note 2)
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
2011-2014 Microchip Technology Inc.
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PIC16(L)F1782/3
TABLE 30-17: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions: VDD = 3V, Temperature = 25°C (unless otherwise stated).
Param.
No.
Sym.
Characteristics
Step Size
Min.
Typ.
Max.
Units
Comments
DAC01*
DAC02*
DAC03*
DAC04*
*
CLSB
—
—
—
—
VDD/256
—
—
1.5
—
V
LSb
CACC
CR
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
600
CST
—
10
s
These parameters are characterized but not tested.
Note 1: Settling time measured while DACR<7:0> transitions from ‘0x00’ to ‘0xFF’.
FIGURE 30-14:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
DT
US121
US121
US122
US120
Refer to Figure 30-4 for load conditions.
Note:
TABLE 30-18: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Max.
Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
US121 TCKRF
Clock out rise time and fall time
(Master mode)
50
US122 TDTRF
Data-out rise time and fall time
45
50
FIGURE 30-15:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
DT
US125
US126
Note: Refer to Figure 30-4 for load conditions.
DS40001579E-page 380
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 30-19: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK (DT hold time)
10
15
—
—
ns
ns
US126 TCKL2DTL Data-hold after CK (DT hold time)
2011-2014 Microchip Technology Inc.
DS40001579E-page 381
PIC16(L)F1782/3
FIGURE 30-16:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP70
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
LSb In
SP74
SP73
Note: Refer to Figure 30-4 for load conditions.
FIGURE 30-17:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71
SP73
SP72
SP79
SCK
(CKP = 1)
SP80
SP78
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
SP74
Note: Refer to Figure 30-4 for load conditions.
LSb In
DS40001579E-page 382
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
FIGURE 30-18:
SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK
(CKP = 0)
SP83
SP79
SP71
SP72
SP78
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
SDO
SDI
bit 6 - - - - - -1
SP75, SP76
bit 6 - - - -1
SP77
MSb In
SP74
SP73
LSb In
Note: Refer to Figure 30-4 for load conditions.
FIGURE 30-19:
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SS
SP83
SCK
(CKP = 0)
SP72
SP71
SCK
(CKP = 1)
SP80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
SP77
SP75, SP76
bit 6 - - - -1
MSb In
SP74
LSb In
Note: Refer to Figure 30-4 for load conditions.
2011-2014 Microchip Technology Inc.
DS40001579E-page 383
PIC16(L)F1782/3
TABLE 30-20: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min.
Typ† Max. Units Conditions
SP70* TSSL2SCH, SS to SCK or SCK input
2.25*TCY
—
—
ns
TSSL2SCL
SP71* TSCH
SP72* TSCL
SCK input high time (Slave mode)
SCK input low time (Slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK edge
TDIV2SCL
SP74* TSCH2DIL, Hold time of SDI data input to SCK edge
TSCL2DIL
100
—
—
ns
SP75* TDOR
SDO data output rise time
3.0-5.5V
1.8-5.5V
—
—
—
10
—
—
—
—
—
Tcy
10
25
10
—
10
25
10
—
—
—
25
50
25
50
25
50
25
50
145
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP76* TDOF
SDO data output fall time
SP77* TSSH2DOZ SS to SDO output high-impedance
SP78* TSCR
SCK output rise time
(Master mode)
3.0-5.5V
1.8-5.5V
SP79* TSCF
SCK output fall time (Master mode)
SP80* TSCH2DOV, SDO data output valid after
TSCL2DOV SCK edge
3.0-5.5V
1.8-5.5V
SP81* TDOV2SCH, SDO data output setup to SCK edge
TDOV2SCL
SP82* TSSL2DOV SDO data output valid after SS edge
—
—
—
50
—
ns
ns
SP83* TSCH2SSH, SS after SCK edge
1.5TCY + 40
TSCL2SSH
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 30-20:
I2C™ BUS START/STOP BITS TIMING
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 30-4 for load conditions.
DS40001579E-page 384
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
TABLE 30-21: I2C™ BUS START/STOP BITS REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min. Typ Max. Units
Conditions
SP90* TSU:STA Start condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
Start condition
SP91* THD:STA Start condition
Hold time
4000
600
ns After this period, the first
clock pulse is generated
SP92* TSU:STO Stop condition
Setup time
4700
600
ns
SP93 THD:STO Stop condition
Hold time
4000
600
ns
*
These parameters are characterized but not tested.
FIGURE 30-21:
I2C™ BUS DATA TIMING
SP100
SP103
SP102
SP101
SCL
SP90
SP106
SP107
SP92
SP91
SDA
In
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 30-4 for load conditions.
2011-2014 Microchip Technology Inc.
DS40001579E-page 385
PIC16(L)F1782/3
TABLE 30-22: I2C™ BUS DATA REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
SP100* THIGH
SP101* TLOW
Clock high time
Clock low time
100 kHz mode
4.0
—
—
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
4.7
—
—
100 kHz mode
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
SSP module
1.3
—
Device must operate at a
minimum of 10 MHz
1.5TCY
—
—
SP102* TR
SP103* TF
SDA and SCL rise 100 kHz mode
time
1000
ns
ns
400 kHz mode
20 + 0.1CB 300
CB is specified to be from
10-400 pF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
250
ns
ns
20 + 0.1CB 250
CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode
400 kHz mode
0
—
0.9
—
ns
s
ns
ns
ns
ns
s
s
0
SP107* TSU:DAT Data input setup
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
250
100
—
(Note 2)
(Note 1)
—
SP109* TAA
Output valid from
clock
3500
—
—
SP110* TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
SP111 CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to
the Standard mode I2C bus specification), before the SCL line is released.
DS40001579E-page 386
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
NOTES:
2011-2014 Microchip Technology Inc.
DS40001579E-page 387
PIC16(L)F1782/3
DS40001579E-page 388
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
31.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each
temperature range.
2011-2014 Microchip Technology Inc.
DS40001579E-page 389
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
35
14
Max.
Max: 85°C + 3σ
Typical: 25°C
Max.
Max: 85°C + 3σ
Typical: 25°C
30
25
20
15
10
5
12
10
8
Typical
Typical
6
4
2
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-1:
IDD, LP Oscillator Mode,
FIGURE 31-2:
IDD, LP Oscillator Mode,
Fosc = 32 kHz, PIC16LF1782/3 Only.
Fosc = 32 kHz, PIC16F1782/3 Only.
500
450
400
4 MHz XT
Max: 85°C + 3σ
Typical: 25°C
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
4 MHz XT
4 MHz EXTRC
4 MHz EXTRC
1 MHz XT
1 MHz XT
1 MHz EXTRC
1 MHz EXTRC
0
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-3:
IDD Typical, XT and EXTRC
FIGURE 31-4:
IDD Maximum, XT and
Oscillator, PIC16LF1782/3 Only.
EXTRC Oscillator, PIC16LF1782/3 Only.
600
450
4 MHz XT
4 MHz XT
Max: 85°C + 3σ
400
350
300
250
200
150
100
50
Typical: 25°C
500
400
300
200
100
0
4 MHz EXTRC
4 MHz EXTRC
1 MHz XT
1 MHz XT
1 MHz EXTRC
1 MHz EXTRC
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 31-5:
IDD Typical, XT and EXTRC
FIGURE 31-6:
IDD Maximum, XT and
Oscillator, PIC16F1782/3 Only.
EXTRC Oscillator, PIC16F1782/3 Only.
DS40001579E-page 390
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
9
8
7
6
5
4
3
2
1
0
30
25
20
15
10
5
Max.
Max: 85°C + 3σ
Typical: 25°C
Max.
Max: 85°C + 3σ
Typical: 25°C
Typical
Typical
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 31-7:
IDD, EC Oscillator LP Mode,
FIGURE 31-8:
IDD, EC Oscillator LP Mode,
Fosc = 32 kHz, PIC16LF1782/3 Only.
Fosc = 32 kHz, PIC16F1782/3 Only.
70
60
Max.
Max: 85°C + 3σ
Max: 85°C + 3σ
60
50
40
30
20
10
0
Typical: 25°C
50
Typical: 25°C
Max.
40
Typical
Typical
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-9:
IDD, EC Oscillator LP Mode,
FIGURE 31-10:
IDD, EC Oscillator LP Mode,
Fosc = 500 kHz, PIC16LF1782/3 Only.
Fosc = 500 kHz, PIC16F1782/3 Only.
350
400
4 MHz
350
300
250
200
150
100
50
Max: 85°C + 3σ
4 MHz
300
250
200
150
100
50
Typical: 25°C
1 MHz
1 MHz
0
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-11:
IDD Typical, EC Oscillator
FIGURE 31-12:
IDD Maximum, EC Oscillator
MP Mode, PIC16LF1782/3 Only.
MP Mode, PIC16LF1782/3 Only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 391
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
450
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
Max: 85°C + 3σ
Typical: 25°C
4 MHz
1 MHz
4 MHz
1 MHz
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 31-13:
IDD Typical, EC Oscillator
FIGURE 31-14:
IDD Maximum, EC Oscillator
MP Mode, PIC16F1782/3 Only.
MP Mode, PIC16F1782/3 Only.
3.5
3.0
Typical: 25°C
Max: 85°C + 3σ
3.0
2.5
32 MHz
32 MHz
2.5
2.0
1.5
2.0
1.5
16 MHz
16 MHz
1.0
0.5
0.0
1.0
0.5
0.0
8 MHz
8 MHz
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-15:
IDD Typical, EC Oscillator
FIGURE 31-16:
IDD Maximum, EC Oscillator
HP Mode, PIC16LF1782/3 Only.
HP Mode, PIC16LF1782/3 Only.
3.0
2.5
32 MHz
Max: 85°C + 3σ
32 MHz
Typical: 25°C
2.5
2.0
2.0
1.5
16 MHz
1.5
1.0
0.5
0.0
16 MHz
1.0
8 MHz
8 MHz
0.5
0.0
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-17:
IDD Typical, EC Oscillator
FIGURE 31-18:
IDD Maximum, EC Oscillator
HP Mode, PIC16F1782/3 Only.
HP Mode, PIC16F1782/3 Only.
DS40001579E-page 392
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
9
8
7
6
5
4
3
2
1
0
30
25
20
15
10
5
Max.
Max.
Max: 85°C + 3σ
Typical: 25°C
Typical
Typical
Max: 85°C + 3σ
Typical: 25°C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-19:
IDD, LFINTOSC Mode,
FIGURE 31-20:
IDD, LFINTOSC Mode,
Fosc = 31 kHz, PIC16LF1782/3 Only.
Fosc = 31 kHz, PIC16F1782/3 Only.
700
600
550
Max.
Max: 85°C + 3σ
Typical: 25°C
Max.
600
Max: 85°C + 3σ
Typical: 25°C
500
Typical
450
400
500
400
300
200
100
350
Typical
300
250
200
150
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-21:
IDD, MFINTOSC Mode,
FIGURE 31-22:
IDD, MFINTOSC Mode,
Fosc = 500 kHz, PIC16LF1782/3 Only.
Fosc = 500 kHz, PIC16F1782/3 Only.
1.8
1.8
16 MHz
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
16 MHz
Max: 85°C + 3σ
Typical: 25°C
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
2 MHz
1 MHz
1 MHz
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-23:
IDD Typical, HFINTOSC
FIGURE 31-24:
IDD Maximum, HFINTOSC
Mode, PIC16LF1782/3 Only.
Mode, PIC16LF1782/3 Only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 393
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
1.6
1.8
16 MHz
16 MHz
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Typical: 25°C
Max: 85°C + 3σ
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
2 MHz
1 MHz
1 MHz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 31-25:
IDD Typical, HFINTOSC
FIGURE 31-26:
IDD Maximum, HFINTOSC
Mode, PIC16F1782/3 Only.
Mode, PIC16F1782/3 Only.
2.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
20 MHz
16 MHz
Max: 85°C + 3σ
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
20 MHz
16 MHz
8 MHz
4 MHz
8 MHz
4 MHz
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.4
2.6
2.8
3.0
3.2
VDD (V)
3.4
3.6
3.8
VDD (V)
FIGURE 31-27:
IDD Typical, HS Oscillator,
FIGURE 31-28:
IDD Maximum, HS Oscillator,
25°C, PIC16LF1782/3 Only.
PIC16LF1782/3 Only.
2.1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
20 MHz
16 MHz
Max: 85°C + 3σ
20 MHz
16 MHz
1.8
1.5
1.2
0.9
0.6
0.3
0.0
8 MHz
4 MHz
8 MHz
4 MHz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 31-29:
IDD Typical, HS Oscillator,
FIGURE 31-30:
IDD Maximum, HS Oscillator,
25°C, PIC16F1782/3 Only.
PIC16F1782/3 Only.
DS40001579E-page 394
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max.
Max.
Typical
Typical
Typical: 25°C
Typical: 25°C
Max: 85°C + 3σ
Max: 85°C + 3σ
2.4
2.6
2.8
3.0
3.2
VDD (V)
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
FIGURE 31-31:
IDD, HS Oscillator, 32 MHz
FIGURE 31-32:
IDD, HS Oscillator, 32 MHz
(8 MHz + 4x PLL), PIC16LF1782/3 Only.
(8 MHz + 4x PLL), PIC16F1782/3 Only.
450
1.2
400
Max.
Max.
1.0
350
300
250
0.8
Max: 85°C + 3σ
Typical: 25°C
0.6
0.4
0.2
0.0
Max: 85°C + 3σ
Typical: 25°C
200
150
100
50
Typical
Typical
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-33:
IPD Base, LP Sleep Mode,
FIGURE 31-34:
IPD Base, LP Sleep Mode
PIC16LF1782/3 Only.
(VREGPM = 1), PIC16F1782/3 Only.
2.5
3.0
Max: 85°C + 3σ
Typical: 25°C
2.5
Max: 85°C + 3σ
Typical: 25°C
2.0
Max.
Max.
2.0
1.5
1.0
0.5
0.0
1.5
1.0
Typical
Typical
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 31-35:
IPD, Watchdog Timer (WDT),
FIGURE 31-36:
IPD, Watchdog Timer (WDT),
PIC16LF1782/3 Only.
PIC16F1782/3 Only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 395
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
35
30
25
20
15
10
5
35
30
25
20
15
10
5
Max: 85°C + 3σ
Typical: 25°C
Max.
Max.
Typical
Typical
Max: 85°C + 3σ
Typical: 25°C
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-37:
IPD, Fixed Voltage Reference
FIGURE 31-38:
IPD, Fixed Voltage Reference
(FVR), PIC16LF1782/3 Only.
(FVR), PIC16F1782/3 Only.
13
11
Max: 85°C + 3σ
Typical: 25°C
Max: 85°C + 3σ
Typical: 25°C
12
11
10
9
Max.
10
9
Max.
Typical
8
Typical
8
7
6
5
4
7
6
5
4
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
VDD (V)
VDD (V)
FIGURE 31-39:
IPD, Brown-Out Reset
FIGURE 31-40:
IPD, Brown-Out Reset
(BOR), BORV = 1, PIC16LF1782/3 Only.
(BOR), BORV = 1, PIC16F1782/3 Only.
Ipd, Low-Power Brown-Out Reset (LPBOR = 0)
Ipd, Low-Power Brown-Out Reset (LPBOR = 0)
1.8
1.8
Max.
Max: 85°C + 3σ
Typical: 25°C
1.6
1.6
Max.
1.4
1.4
1.2
1.2
1.0
0.8
0.6
Max: 85°C + 3σ
1.0
0.8
0.6
0.4
0.2
0.0
Typical: 25°C
Typical
Typical
0.4
0.2
0.0
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
FIGURE 31-41:
IPD, LP Brown-Out Reset
FIGURE 31-42:
IPD, LP Brown-Out Reset
(LPBOR = 0), PIC16LF1782/3 Only.
(LPBOR = 0), PIC16F1782/3 Only.
DS40001579E-page 396
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
7
6
5
4
3
2
1
0
12
10
8
Max: 85°C + 3σ
Typical: 25°C
Max: 85°C + 3σ
Typical: 25°C
Max.
Max.
6
Typical
Typical
4
2
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-43:
IPD, Timer1 Oscillator,
FIGURE 31-44:
IPD, Timer1 Oscillator,
FOSC = 32 kHz, PIC16LF1782/3 Only.
FOSC = 32 kHz, PIC16F1782/3 Only.
700
900
Max: 85°C + 3σ
Typical: 25°C
Max: 85°C + 3σ
Typical: 25°C
800
600
500
400
300
200
100
0
Max.
700
600
Max.
500
Typical
Typical
400
300
200
100
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
VDD (V)
FIGURE 31-45:
IPD, Op Amp, High GBWP
FIGURE 31-46:
IPD, Op Amp, High GBWP
Mode (OPAxSP = 1), PIC16LF1782/3 Only.
Mode (OPAxSP = 1), PIC16F1782/3 Only.
500
1.4
Max: 85°C + 3σ
Typical: 25°C
450
400
350
300
250
200
150
100
50
Max: 85°C + 3σ
Max.
Typical: 25°C
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Max.
Typical
Typical
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
1.5
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-47:
PIC16LF1782/3 Only.
IPD, ADC Non-Converting,
FIGURE 31-48:
PIC16F1782/3 Only.
IPD, ADC Non-Converting,
2011-2014 Microchip Technology Inc.
DS40001579E-page 397
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
800
700
600
500
400
300
200
800
700
600
500
400
300
200
Max: -40°C + 3σ
Typical: 25°C
Max: -40°C + 3σ
Typical: 25°C
Max.
Max.
Typical
Typical
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 31-49:
IPD, Comparator, NP Mode
FIGURE 31-50:
IPD, Comparator, NP Mode
(CxSP = 1), PIC16LF1782/3 Only.
(CxSP = 1), PIC16F1782/3 Only.
6
5
4
3
5
Max: -40°C max + 3σ
Typical;:statistical mean @ 25°C
4
3
2
1
0
Min: +125°C min - 3σ
Min.
Typical
Max.
Max.
Typical
Min.
2
1
0
Max: -40°C max + 3σ
Typical: statistical mean @ 25°C
Min: +125°C min - 3σ
-30
-25
-20
-15
IOH (mA)
-10
-5
0
0
10
20
30
40
IOL (mA)
50
60
70
80
FIGURE 31-51:
VOH vs. IOH Over
FIGURE 31-52:
VOL vs. IOL Over
Temperature, VDD = 5.0V, PIC16F1782/3 Only.
Temperature, VDD = 5.0V, PIC16F1782/3 Only.
3.0
3.5
Max: -40°C max + 3σ
Max: -40°C max + 3σ
Typical: statistical mean @ 25°C
Typical: statistical mean @ 25°C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
Min: +125°C min - 3σ
Min: +125°C min - 3σ
Max.
Typical
Min.
Max.
Typical
Min.
-14
-12
-10
-8
-6
-4
-2
0
0
5
10
15
20
25
30
IOH (mA)
IOL (mA)
FIGURE 31-53:
Temperature, VDD = 3.0V.
VOH vs. IOH Over
FIGURE 31-54:
Temperature, VDD = 3.0V.
VOL vs. IOL Over
DS40001579E-page 398
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
Voh vs. Ioh over Temperature, Vdd = 1.8V
Vol vs. Iol over Temperature, Vdd = 1.8V
2.0
1.8
Max: -40°C max + 3σ
Max: -40°C max + 3σ
1.8
1.6
1.4
1.2
1
Typical: statistical mean @ 25°C
Typical: statistical mean @ 25°C
Min: +125°C min - 3σ
Min: +125°C min - 3σ
1.6
1.4
1.2
1.0
Min.
Typical
Max.
Min.
Typical
Max.
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0.0
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0
1
2
3
4
5
6
7
8
9
10
FIGURE 31-55:
VOH vs. IOH Over
FIGURE 31-56:
VOL vs. IOL Over
Temperature, VDD = 1.8V, PIC16LF1782/3 Only.
Temperature, VDD = 1.8V, PIC16LF1782/3 Only.
40
38
40
Max.
36
38
Max.
36
34
Typical
34
32
Typical
32
30
30
Min.
Min.
28
28
26
26
Max: Typical + 3σ (-40°C to +125°C)
24
Typical; statistical mean @ 25°C
24
22
20
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3σ (-40°C to +125°C)
Min: Typical - 3σ (-40°C to +125°C)
22
20
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
VDD (V)
2
2.5
3
3.5
VDD (V)
4
4.5
5
5.5
6
FIGURE 31-57:
LFINTOSC Frequency,
FIGURE 31-58:
LFINTOSC Frequency,
PIC16LF1782/3 Only.
PIC16F1782/3 Only.
24
22
20
18
16
14
12
10
24
22
20
18
16
14
12
10
Max.
Max.
Typical
Min.
Typical
Min.
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3σ (-40°C to +125°C)
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3σ (-40°C to +125°C)
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
6.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 31-59:
WDT Time-Out Period,
FIGURE 31-60:
WDT Time-Out Period,
PIC16F1782/3 Only.
PIC16LF1782/3 Only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 399
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
70
60
50
40
30
20
10
0
2.00
1.95
1.90
1.85
1.80
Max: Typical + 3σ
Typical: Statistical Mean
Min: Typical - 3σ
Max.
Max.
Typical
Min.
Typical
Min.
Max: Typical + 3σ
Typical: Statistical Mean
Min: Typical - 3σ
-60
-40
-20
0
20
40
60
80
100
120
140
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-61:
Brown-Out Reset Voltage,
FIGURE 31-62:
Brown-Out Reset Hysteresis,
Low Trip Point (BORV = 1), PIC16LF1782/3 Only.
Low Trip Point (BORV = 1), PIC16LF1782/3 Only.
70
2.60
Max: Typical + 3σ
Typical: Statistical Mean
60
50
40
30
20
10
0
Min: Typical - 3σ
2.55
Max.
Max.
Typical
2.50
Min.
Typical
Min.
2.45
2.40
Max: Typical + 3σ
2.35
2.30
Typical: Statistical Mean
Min: Typical - 3σ
-60
-40
-20
0
20
40
60
80
100
120
140
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-63:
Brown-Out Reset Voltage,
FIGURE 31-64:
Brown-Out Reset Hysteresis,
Low Trip Point (BORV = 1), PIC16F1782/3 Only.
Low Trip Point (BORV = 1), PIC16F1782/3 Only.
2.85
80
Max: Typical + 3σ
Max: Typical + 3σ
Typical: Statistical Mean
Typical: Statistical Mean
70
Min: Typical - 3σ
Min: Typical - 3σ
2.80
Max.
60
Max.
50
2.75
Typical
Typical
40
Min.
2.70
2.65
2.60
30
20
Min.
10
0
-60
-40
-20
0
20
40
60
80
100
120
140
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-65:
Brown-Out Reset Voltage,
FIGURE 31-66:
Brown-Out Reset Hysteresis,
High Trip Point (BORV = 0).
High Trip Point (BORV = 0).
DS40001579E-page 400
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
50
45
40
35
30
25
20
15
10
5
Max.
Max.
Max: Typical + 3σ
Typical: Statistical Mean
Min: Typical - 3σ
Max: Typical + 3σ
Typical: Statistical Mean
Typical
Min.
Typical
0
-60
-40
-20
0
20
40
60
80
100
120
140
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-67:
LPBOR Reset Voltage.
FIGURE 31-68:
LPBOR Reset Hysteresis.
110
100
90
100
90
80
70
60
50
40
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3σ (-40°C to +125°C)
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3σ (-40°C to +125°C)
Max.
Max.
80
Typical
Min.
Typical
70
60
Min.
50
40
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-69:
PWRT Period,
FIGURE 31-70:
PWRT Period,
PIC16F1782/3 Only.
PIC16LF1782/3 Only.
1.58
1.70
1.68
1.66
1.64
1.62
1.60
1.58
1.56
1.56
Max.
Max.
1.54
Typical
Typical
Min.
1.52
Min.
1.50
1.48
Max: Typical + 3σ
Typical: Statistical Mean
Min: Typical - 3σ
Max: Typical + 3σ
Typical: Statistical Mean
Min: Typical - 3σ
1.54
1.52
1.50
1.46
20 40 60
140
1.44
-60
-40
-20
0
80
100
120
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-71:
POR Release Voltage.
FIGURE 31-72:
POR Rearm Voltage,
NP Mode (VREGPM = 0), PIC16F1782/3 Only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 401
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
12
10
8
Max.
Typical
Max.
6
Typical
4
Min.
Max: Typical + 3σ (-40°C to +125°C)
Max: Typical + 3σ
Typical: Statistical Mean
Min: Typical - 3σ
2
Typical; statistical mean @ 25°C
0
-60
-40
-20
0
20
40
60
80
100
120
140
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Temperature (°C)
VDD (V)
FIGURE 31-73:
POR Rearm Voltage,
FIGURE 31-74:
Wake From Sleep,
NP Mode, PIC16LF1782/3 Only.
VREGPM = 0.
50
45
40
35
30
25
Max: Typical + 3σ
Typical: statistical mean @ 25°C
40
Max.
Max.
35
30
Typical
Typical
25
20
15
10
20
Note:
The FVR Stabilization Period applies when:
1) coming out of Reset or exiting Sleep mode for PIC12/16LFxxxx devices.
2) when exiting Sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices
In all other cases, the FVR is stable when released from Reset.
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
15
10
5
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (mV)
VDD (V)
FIGURE 31-75:
Wake From Sleep,
FIGURE 31-76:
FVR Stabilization Period.
VREGPM = 1.
1.0
0.5
1.0
0.5
0.0
0.0
-0.5
-1.0
-0.5
-1.0
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
Output Code
Output Code
FIGURE 31-77:
ADC 10-bit Mode,
FIGURE 31-78:
ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S, 25°C.
Single-Ended DNL, VDD = 3.0V, TAD = 4 S, 25°C.
DS40001579E-page 402
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
1.0
1.0
0.5
0.5
0.0
0.0
-0.5
-0.5
-1.0
0
128
256
384
640
768
896
1024
-1.0
512
0
128
256
384
512
640
768
896
1024
Output Code
Output Code
FIGURE 31-79:
ADC 10-bit Mode,
FIGURE 31-80:
ADC 10-bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25°C.
Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25°C.
2.0
1.5
2.5
2.0
1.5
Max -40C
1.0
0.5
Max 125C
Max 125C
Max 25C
1.0
Max -40C
Max 25C
0.5
0.0
0.0
Min 25C
-0.5
Min 25C
Min 125C
-0.5
-1.0
Min 125C
Min -40C
-1.0
Min -40C
-1.5
-2.0
-2.5
-1.5
-2.0
0.5
1.0
2.0
4.0
8.0
0.5
1.0
2.0
4.0
8.0
TAD (μs)
TAD (μs)
FIGURE 31-81:
ADC 10-bit Mode,
FIGURE 31-82:
ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V.
Single-Ended INL, VDD = 3.0V, VREF = 3.0V.
2.0
2.0
Max -40C
1.5
Max 125C
1.5
Max 125C
Max 25C
1.0
0.5
1.0
Max -40C
Max 25C
0.5
0.0
Min -40C
Min 25C
0.0
-0.5
-1.0
-1.5
Min -40C
-0.5
Min 125C
Min 25C
-1.0
Min 125C
-2.0
-2.5
-3.0
-1.5
-2.0
1.8
2.3
3.0
1.8
2.3
3.0
Reference Voltage (V)
Reference Voltage (V)
FIGURE 31-83:
ADC 10-bit Mode,
FIGURE 31-84:
ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S.
Single-Ended INL, VDD = 3.0V, TAD = 1 S.
2011-2014 Microchip Technology Inc.
DS40001579E-page 403
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
Output Code
Output Code
FIGURE 31-85:
ADC 12-bit Mode,
FIGURE 31-86:
ADC 12-bit Mode,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S, 25°C.
Single-Ended DNL, VDD = 3.0V, TAD = 4 S, 25°C.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
Output Code
Output Code
FIGURE 31-87:
ADC 12-bit Mode,
FIGURE 31-88:
ADC 12-bit Mode,
Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25°C.
Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25°C.
4.5
5.5
Max -40C
Max -40C
3
Max 125C
3.5
Max 125C
Max 25C
Max 25C
1.5
1.5
0
-0.5
Min 25C
Min 25C
Min -40C
Min 125C
Min -40C
-1.5
-2.5
Min 125C
8.0
-3
-4.5
0.5
1.0
2.0
4.0
8.0
0.5
1.0
2.0
4.0
TAD (μs)
TAD (μs)
FIGURE 31-89:
ADC 12-bit Mode,
FIGURE 31-90:
ADC 12-bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V.
Single-Ended INL, VDD = 3.0V, VREF = 3.0V.
DS40001579E-page 404
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
6
5
5
4
Max -40C
4
Max -40C
Max 25C
3
3
Max 25C
Max 125C
2
2
1
Max 125C
1
0
Min 125C
-1
-2
-3
-4
0
Min 125C
Min 25C
Min -40C
Min -40C
Min 25C
-1
-2
1.8
2.3
3.0
1.8
2.3
3.0
Reference Voltage (V)
Reference Voltage (V)
FIGURE 31-91:
ADC 12-bit Mode,
FIGURE 31-92:
ADC 12-bit Mode,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S.
Single-Ended INL, VDD = 3.0V, TAD = 1 S.
2.5
2.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
Output Code
Output Code
FIGURE 31-93:
ADC 12-bit Mode,
FIGURE 31-94:
ADC 12-bit Mode,
Single-Ended DNL, VDD = 5.5V, TAD = 1 S, 25°C.
Single-Ended DNL, VDD = 5.5V, TAD = 4 S, 25°C.
3.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
500
1000
1500
3000
3500
4000
-0.5
2000
2500
0
500
1000
1500
2000
2500
3000
3500
4000
Output Code
Output Code
FIGURE 31-95:
ADC 12-bit Mode,
FIGURE 31-96:
ADC 12-bit Mode,
Single-Ended INL, VDD = 5.5V, TAD = 1 S, 25°C.
Single-Ended INL, VDD = 5.5V, TAD = 4 S, 25°C.
2011-2014 Microchip Technology Inc.
DS40001579E-page 405
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
4
3
Max 25C
Max -40C
3
Max -40C
Max 125C
Max 25C
2
2
Max 125C
1
1
0
0
Min 25C
Min -40C
-1
-1
Min 25C
Min -40C
Min 125C
Min 125C
-2
-2
1.0
2.0
TAD (μs)
4.0
1.0
2.0
TAD (μs)
4.0
FIGURE 31-97:
ADC 12-bit Mode,
FIGURE 31-98:
ADC 12-bit Mode,
Single-Ended DNL, VDD = 5.5V, VREF = 5.5V.
Single-Ended INL, VDD = 5.5V, VREF = 5.5V.
900
800
ADC Vref+ set to Vdd
ADC Vref- set to Gnd
ADC Vref+ set to Vdd
ADC Vref- set to Gnd
Max.
700
800
700
600
500
400
300
Max.
Typical
600
500
Typical
Min.
400
300
Min.
Max: Typical + 3σ
Typical; statistical mean
Min: Typical - 3σ
200
Max: Typical + 3σ
Typical; statistical mean
100
0
Min: Typical - 3σ
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
5.6
6
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 31-99:
Temp. Indicator Initial Offset,
FIGURE 31-100:
Temp. Indicator Initial Offset,
High Range, Temp. = 20°C, PIC16F1782/3 Only.
Low Range, Temp. = 20°C, PIC16F1782/3 Only.
800
150
ADC Vref+ set to Vdd
ADC Vref- set to Gnd
ADC Vref+ set to Vdd
Max.
ADC Vref- set to Gnd
125
100
75
700
Max.
600
Min.
500
50
Min.
25
400
0
Typical
300
200
100
Max: Typical + 3σ
Typical; statistical mean
Min: Typical - 3σ
-25
-50
-75
Max: Typical + 3σ
Typical; statistical mean
Min: Typical - 3σ
Typical
-60 -40
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
-20
0
20
40
60
80
100
120
140
VDD (V)
Temperature (°C)
FIGURE 31-101:
Temp. Indicator Initial Offset,
FIGURE 31-102:
Temp. Indicator Slope
Low Range, Temp. = 20°C, PIC16LF1782/3 Only.
Normalized to 20°C, High Range, VDD = 5.5V,
PIC16F1782/3 Only.
DS40001579E-page 406
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
250
200
150
100
50
150
100
50
Max.
Min.
Max.
Min.
ADC Vref+ set to Vdd
ADC Vref- set to Gnd
ADC Vref+ set to Vdd
ADC Vref- set to Gnd
0
0
-50
-100
-150
-50
-100
Typical
Max: Typical + 3σ
Typical
Max: Typical + 3σ
Typical; statistical mean
Typical; statistical mean
Min: Typical - 3σ
Min: Typical - 3σ
-60
-40
-20
0
20
40
60
80
100
120
140
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-103:
Temp. Indicator Slope
FIGURE 31-104:
Temp. Indicator Slope
Normalized to 20°C, High Range, VDD = 3.6V,
PIC16F1782/3 Only.
Normalized to 20°C, Low Range, VDD = 3.0V,
PIC16F1782/3 Only.
250
150
Max.
ADC Vref+ set to Vdd
ADC Vref- set to Gnd
ADC Vref+ set to Vdd
ADC Vref- set to Gnd
Max.
200
150
100
50
100
50
Min.
Min.
0
0
-50
-100
-150
-50
-100
Typical
Typical
Max: Typical + 3σ
Max: Typical + 3σ
Typical; statistical mean
Typical; statistical mean
Min: Typical - 3σ
Min: Typical - 3σ
-60
-40
-20
0
20
40
60
80
100
120
140
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-105:
Temp. Indicator Slope
FIGURE 31-106:
Temp. Indicator Slope
Normalized to 20°C, Low Range, VDD = 1.8V,
PIC16LF1782/3 Only.
Normalized to 20°C, Low Range, VDD = 3.0V,
PIC16LF1782/3 Only.
250
80
ADC Vref+ set to Vdd
ADC Vref- set to Gnd
Max
Max.
200
150
100
50
75
70
Min.
Typical
65
60
Min
55
0
50
-50
-100
-150
Max: Typical + 3σ
Max: Typical + 3σ
Typical
Typical; statistical mean
45
Typical; statistical mean
Min: Typical - 3σ
Min: Typical - 3σ
40
-50
-30
-10
10
30
50
70
90
110
130
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-107:
Temp. Indicator Slope
FIGURE 31-108:
Op Amp, Common Mode
Normalized to 20°C, High Range, VDD = 3.6V,
PIC16LF1782/3 Only.
Rejection Ratio (CMRR), VDD = 3.0V.
2011-2014 Microchip Technology Inc.
DS40001579E-page 407
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
35%
8
Sample Size = 3,200
Max
30%
6
4
25%
Typical
2
20%
-40°C
0
25°C
Min
15%
85°C
-2
-4
125°C
10%
Max: Typical + 3σ
Typical; statistical mean
Min: Typical - 3σ
-6
5%
-8
0%
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
-7
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
Common Mode Voltage (V)
Offset Voltage (mV)
FIGURE 31-109:
Op Amp, Output Voltage
FIGURE 31-110:
Op Amp, Offset Over
Histogram, VDD = 3.0V, VCM = VDD/2.
Common Mode Voltage, VDD = 3.0V,
Temp. = 25°C.
8
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
Max
Vdd = 3.6V
Vdd = 5.5V
6
4
Typical
2
0
Vdd = 2.3V
Vdd = 3V
-2
-4
Min
Max: Typical + 3σ
Typical; statistical mean
-6
-8
Min: Typical - 3σ
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-60
-40
-20
0
20
40
60
80
100
120
140
Common Mode Voltage (V)
Temperature (°C)
FIGURE 31-111:
Op Amp, Offset Over
FIGURE 31-112:
Op Amp, Output Slew Rate,
Common Mode Voltage, VDD = 5.0V,
Temp. = 25°C, PIC16F1782/3 Only.
Rising Edge.
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
45
43
41
39
37
35
33
31
29
27
25
Vdd = 2.3V
Vdd = 3.6V
-40°C
25°C
85°C
125°
Vdd = 5.5V
Vdd = 3V
-60
-40
-20
0
20
40
60
80
100
120
140
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Temperature (°C)
Common Mode Voltage (V)
FIGURE 31-113:
Op Amp, Output Slew Rate,
FIGURE 31-114:
Comparator Hysteresis,
Falling Edge.
NP Mode (CxSP = 1), VDD = 3.0V, Typical
Measured Values.
DS40001579E-page 408
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
30
25
20
15
10
5
30
25
20
15
10
5
MAX
MAX
MIN
0
0
-5
-5
-10
-15
-20
-10
-15
-20
MIN
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Common Mode Voltage (V)
Common Mode Voltage (V)
FIGURE 31-115:
Comparator Offset, NP Mode
FIGURE 31-116:
Comparator Offset, NP Mode
(CxSP = 1), VDD = 3.0V, Typical Measured Values
(CxSP = 1), VDD = 3.0V, Typical Measured Values
at 25°C.
From -40°C to 125°C.
30
25
20
15
50
45
40
MAX
10
25°C
125°
5
0
35
85°
30
-5
-40°C
-10
MIN
25
-15
-20
20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Voltage (V)
Common Mode Voltage (V)
FIGURE 31-117:
Comparator Hysteresis,
FIGURE 31-118:
Comparator Offset, NP Mode
NP Mode (CxSP = 1), VDD = 5.5V, Typical
(CxSP = 1), VDD = 5.0V, Typical Measured Values
Measured Values, PIC16F1782/3 Only.
at 25°C, PIC16F1782/3 Only.
140
40
30
20
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
120
Min: Typical - 3σ (-40°C to +125°C)
100
125°C
MAX
80
10
25°C
60
0
40
-40°C
-10
20
MIN
-20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.8
2.1
2.4
2.7
3.0
3.3
3.6
Common Mode Voltage (V)
VDD (V)
FIGURE 31-119:
Comparator Offset, NP Mode
FIGURE 31-120:
Comparator Response Time
(CxSP = 1), VDD = 5.0V, Typical Measured Values
Over Voltage, NP Mode (CxSP = 1), Typical
From -40°C to 125°C, PIC16F1782/3 Only.
Measured Values, PIC16LF1782/3 Only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 409
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
90
80
70
60
50
40
30
20
10
0
1,400
1,200
1,000
800
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3σ (-40°C to +125°C)
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3σ (-40°C to +125°C)
125°C
25°C
125°C
25°C
600
400
-40°C
200
-40°C
0
2.2
2.5
2.8
3.1
3.4
3.7
4.0
4.3
4.6
4.9
5.2
5.5
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VDD (V)
VDD (V)
FIGURE 31-122:
Delay Time Over Temp., NP Mode (CxSP = 1),
Typical Measured Values, PIC16LF1782/3 Only.
Comparator Output Filter
FIGURE 31-121:
Over Voltage, NP Mode (CxSP = 1), Typical
Measured Values, PIC16F1782/3 Only.
Comparator Response Time
0.025
0.020
0.015
0.010
800
Max: Typical + 3σ (-40°C to +125°C)
Typical; statistical mean @ 25°C
700
600
500
400
300
200
100
0
Min: Typical - 3σ (-40°C to +125°C)
0.005
125°C
-40°C
25°C
0.000
85°C
25°C
-0.005
-0.010
-0.015
-0.020
125°C
-40°C
3.4
2.2
2.5
2.8
3.1
3.7
4.0
4.3
4.6
4.9
5.2
5.5
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Output Code
VDD (V)
FIGURE 31-123:
Comparator Output Filter
FIGURE 31-124:
Typical DAC DNL Error,
Delay Time Over Temp., NP Mode (CxSP = 1),
VDD = 3.0V, VREF = External 3V.
Typical Measured Values, PIC16F1782/3 Only.
0.020
0.015
0.010
0.005
0.000
-0.005
-0.010
-0.015
0.00
-0.05
-0.10
-0.15
-0.20
-40°C
25°C
85°C
125°C
-40°C
25°C
-0.25
85°C
-0.30
-0.35
-0.40
-0.45
125°C
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Output Code
Output Code
FIGURE 31-125:
Typical DAC INL Error,
FIGURE 31-126:
Typical DAC INL Error,
VDD = 3.0V, VREF = External 3V.
VDD = 5.0V, VREF = External 5V, PIC16F1782/3
Only.
DS40001579E-page 410
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
0.4
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
Vref = Int. Vdd
0.3
Vref = Ext.
1.8V
Vref = Ext.
2.0V
-40°C
25°C
85°C
125°C
0.2
0.1
0.0
-60
-40
-20
0
20
40
60
80
100
120
140
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Temperature (°C)
Output Code
FIGURE 31-128:
Error, VDD = 3.0V, VREF = VDD.
Absolute Value of DAC DNL
FIGURE 31-127:
VDD = 5.0V, VREF = External 5V, PIC16F1782/3
Only.
Typical DAC INL Error,
0.90
0.30
Vref = Int. Vdd
Vref = Ext.
Vref = Int. Vdd
0.88
0.26
Vref = Ext.
1.8V
1.8V
Vref = Ext.
Vref = Ext.
0.86
2.0V
2.0V
Vref = Ext.
Vref = Ext.
0.22
3.0V
3.0V
0.84
Vref = Ext.
5.0V
0.18
0.82
-60
0
0.14
0.80
0.78
0.10
-60
-40
-20
0
20
40
60
80
100
120
140
-40
-20
20
40
60
80
100
120
140
Temperature (°C)
Temperature (°C)
FIGURE 31-129:
Absolute Value of DAC INL
FIGURE 31-130:
Absolute Value of DAC DNL
Error, VDD = 3.0V.
Error, VDD = 5.0V, PIC16F1782/3 Only.
0.9
Vref = Int. Vdd
0.88
Vref = Ext.
1.8V
Vref = Ext.
0.86
2.0V
Vref = Ext.
0.84
3.0V
0.82
0.8
0.78
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
FIGURE 31-131:
Absolute Value of DAC INL
Error, VDD = 5.0V, PIC16F1782/3 Only.
2011-2014 Microchip Technology Inc.
DS40001579E-page 411
PIC16(L)F1782/3
32.1 MPLAB X Integrated Development
Environment Software
32.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
- MPLAB PM3 Device Programmer
• Smart code completion makes suggestions and
provides hints as you type
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Automatic code formatting based on user-defined
rules
• Third-party development tools
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
DS40001579E-page 412
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
32.2 MPLAB XC Compilers
32.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler include:
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
32.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
32.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
2011-2014 Microchip Technology Inc.
DS40001579E-page 413
PIC16(L)F1782/3
32.6 MPLAB X SIM Software Simulator
32.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
32.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
32.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
32.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
DS40001579E-page 414
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
32.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
32.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
®
tion software for analog filter design, KEELOQ security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2011-2014 Microchip Technology Inc.
DS40001579E-page 415
PIC16(L)F1782/3
33.0 PACKAGING INFORMATION
33.1 Package Marking Information
28-Lead SPDIP (.300”)
Example
PIC16F1782
e
3
-I/SP
1204017
28-Lead SOIC (7.50 mm)
Example
PIC16F1782
-I/SO
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
e
3
1204017
YYWWNNN
28-Lead SSOP (5.30 mm)
Example
PIC16F1782
e
3
-I/SS
1204017
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS40001579E-page 416
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Package Marking Information (Continued)
28-Lead QFN (6x6 mm)
Example
PIN 1
PIN 1
16F1782
XXXXXXXX
XXXXXXXX
YYWWNNN
e
3
-I/ML
120417
28-Lead UQFN (4x4x0.5 mm)
Example
PIC16
LF1782
I/MV
PIN 1
PIN 1
204017
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011-2014 Microchip Technology Inc.
DS40001579E-page 417
PIC16(L)F1782/3
33.2 Package Details
The following sections give the technical details of the packages.
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DS40001579E-page 418
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2014 Microchip Technology Inc.
DS40001579E-page 419
PIC16(L)F1782/3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001579E-page 420
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2014 Microchip Technology Inc.
DS40001579E-page 421
PIC16(L)F1782/3
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ꢀꢁ ꢂꢃꢄꢀꢄ!ꢂ"#ꢅꢆꢄꢂꢃ$ꢇ%ꢄ&ꢇꢅ'#ꢈꢇꢄ(ꢅꢉꢄ!ꢅꢈꢉ)ꢄ*#'ꢄ(#"'ꢄ*ꢇꢄꢆꢊꢋꢅ'ꢇ$ꢄ+ꢂ'ꢌꢂꢃꢄ'ꢌꢇꢄꢌꢅ'ꢋꢌꢇ$ꢄꢅꢈꢇꢅꢁ
ꢍꢁ ꢑꢂ(ꢇꢃ"ꢂꢊꢃ"ꢄꢑꢄꢅꢃ$ꢄ/ꢀꢄ$ꢊꢄꢃꢊ'ꢄꢂꢃꢋꢆ#$ꢇꢄ(ꢊꢆ$ꢄ&ꢆꢅ"ꢌꢄꢊꢈꢄꢒꢈꢊ'ꢈ#"ꢂꢊꢃ"ꢁꢄꢓꢊꢆ$ꢄ&ꢆꢅ"ꢌꢄꢊꢈꢄꢒꢈꢊ'ꢈ#"ꢂꢊꢃ"ꢄ"ꢌꢅꢆꢆꢄꢃꢊ'ꢄꢇ%ꢋꢇꢇ$ꢄꢔꢁꢍꢔꢄ((ꢄꢒꢇꢈꢄ"ꢂ$ꢇꢁ
.ꢁ ꢑꢂ(ꢇꢃ"ꢂꢊꢃꢂꢃꢐꢄꢅꢃ$ꢄ'ꢊꢆꢇꢈꢅꢃꢋꢂꢃꢐꢄꢒꢇꢈꢄꢖꢏꢓ/ꢄ1ꢀꢕꢁꢗꢓꢁ
2ꢏ-3 2ꢅ"ꢂꢋꢄꢑꢂ(ꢇꢃ"ꢂꢊꢃꢁꢄꢘꢌꢇꢊꢈꢇ'ꢂꢋꢅꢆꢆꢉꢄꢇ%ꢅꢋ'ꢄ!ꢅꢆ#ꢇꢄ"ꢌꢊ+ꢃꢄ+ꢂ'ꢌꢊ#'ꢄ'ꢊꢆꢇꢈꢅꢃꢋꢇ"ꢁ
ꢜ/43 ꢜꢇ&ꢇꢈꢇꢃꢋꢇꢄꢑꢂ(ꢇꢃ"ꢂꢊꢃ)ꢄ#"#ꢅꢆꢆꢉꢄ+ꢂ'ꢌꢊ#'ꢄ'ꢊꢆꢇꢈꢅꢃꢋꢇ)ꢄ&ꢊꢈꢄꢂꢃ&ꢊꢈ(ꢅ'ꢂꢊꢃꢄꢒ#ꢈꢒꢊ"ꢇ"ꢄꢊꢃꢆꢉꢁ
ꢓꢂꢋꢈꢊꢋꢌꢂꢒ ꢘꢇꢋꢌꢃꢊꢆꢊꢐꢉ ꢑꢈꢅ+ꢂꢃꢐ -ꢔꢕꢝꢔꢛ.2
DS40001579E-page 422
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2014 Microchip Technology Inc.
DS40001579E-page 423
PIC16(L)F1782/3
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ(ꢓꢅꢆꢇ)ꢎꢅꢐ*ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ+ꢄꢇꢕ,ꢃꢖꢇMꢇ-.-ꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ()!
/ꢊꢐ#ꢇꢘ'&&ꢇꢙꢙꢇ0ꢛꢋꢐꢅꢑꢐꢇꢃꢄꢋ+ꢐ#
!ꢛꢐꢄ" 4ꢊꢈꢄ'ꢌꢇꢄ(ꢊ"'ꢄꢋ#ꢈꢈꢇꢃ'ꢄꢒꢅꢋ5ꢅꢐꢇꢄ$ꢈꢅ+ꢂꢃꢐ")ꢄꢒꢆꢇꢅ"ꢇꢄ"ꢇꢇꢄ'ꢌꢇꢄꢓꢂꢋꢈꢊꢋꢌꢂꢒꢄ ꢅꢋ5ꢅꢐꢂꢃꢐꢄꢏꢒꢇꢋꢂ&ꢂꢋꢅ'ꢂꢊꢃꢄꢆꢊꢋꢅ'ꢇ$ꢄꢅ'ꢄ
ꢌ''ꢒ366+++ꢁ(ꢂꢋꢈꢊꢋꢌꢂꢒꢁꢋꢊ(6ꢒꢅꢋ5ꢅꢐꢂꢃꢐ
D
D2
EXPOSED
PAD
e
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b
E2
2
1
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K
N
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NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
7ꢃꢂ'"
ꢑꢂ(ꢇꢃ"ꢂꢊꢃꢄ:ꢂ(ꢂ'"
ꢓꢙ::ꢙꢓ/ꢘ/ꢜꢏ
8;ꢓ
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;!ꢇꢈꢅꢆꢆꢄ?ꢂ$'ꢌ
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8
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ꢔꢁ@ꢗꢄ2ꢏ-
ꢔꢁꢚꢔ
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ꢔꢁꢔꢔ
ꢀꢁꢔꢔ
ꢔꢁꢔꢗ
ꢔꢁꢔꢍ
ꢔꢁꢍꢔꢄꢜ/4
@ꢁꢔꢔꢄ2ꢏ-
.ꢁꢛꢔ
@ꢁꢔꢔꢄ2ꢏ-
.ꢁꢛꢔ
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M
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ꢕꢁꢍꢔ
ꢑꢍ
*
:
.ꢁ@ꢗ
ꢔꢁꢍ.
ꢔꢁꢗꢔ
ꢔꢁꢍꢔ
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ꢔꢁ.ꢗ
ꢔꢁꢛꢔ
M
B
!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢀꢄ!ꢂ"#ꢅꢆꢄꢂꢃ$ꢇ%ꢄ&ꢇꢅ'#ꢈꢇꢄ(ꢅꢉꢄ!ꢅꢈꢉ)ꢄ*#'ꢄ(#"'ꢄ*ꢇꢄꢆꢊꢋꢅ'ꢇ$ꢄ+ꢂ'ꢌꢂꢃꢄ'ꢌꢇꢄꢌꢅ'ꢋꢌꢇ$ꢄꢅꢈꢇꢅꢁ
ꢍꢁ ꢅꢋ5ꢅꢐꢇꢄꢂ"ꢄ"ꢅ+ꢄ"ꢂꢃꢐ#ꢆꢅ'ꢇ$ꢁ
.ꢁ ꢑꢂ(ꢇꢃ"ꢂꢊꢃꢂꢃꢐꢄꢅꢃ$ꢄ'ꢊꢆꢇꢈꢅꢃꢋꢂꢃꢐꢄꢒꢇꢈꢄꢖꢏꢓ/ꢄ1ꢀꢕꢁꢗꢓꢁ
2ꢏ-3 2ꢅ"ꢂꢋꢄꢑꢂ(ꢇꢃ"ꢂꢊꢃꢁꢄꢘꢌꢇꢊꢈꢇ'ꢂꢋꢅꢆꢆꢉꢄꢇ%ꢅꢋ'ꢄ!ꢅꢆ#ꢇꢄ"ꢌꢊ+ꢃꢄ+ꢂ'ꢌꢊ#'ꢄ'ꢊꢆꢇꢈꢅꢃꢋꢇ"ꢁ
ꢜ/43 ꢜꢇ&ꢇꢈꢇꢃꢋꢇꢄꢑꢂ(ꢇꢃ"ꢂꢊꢃ)ꢄ#"#ꢅꢆꢆꢉꢄ+ꢂ'ꢌꢊ#'ꢄ'ꢊꢆꢇꢈꢅꢃꢋꢇ)ꢄ&ꢊꢈꢄꢂꢃ&ꢊꢈ(ꢅ'ꢂꢊꢃꢄꢒ#ꢈꢒꢊ"ꢇ"ꢄꢊꢃꢆꢉꢁ
ꢓꢂꢋꢈꢊꢋꢌꢂꢒ ꢘꢇꢋꢌꢃꢊꢆꢊꢐꢉ ꢑꢈꢅ+ꢂꢃꢐ -ꢔꢕꢝꢀꢔꢗ2
DS40001579E-page 424
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ(ꢓꢅꢆꢇ)ꢎꢅꢐ*ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ+ꢄꢇꢕ,ꢃꢖꢇMꢇ-.-ꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ()!
/ꢊꢐ#ꢇꢘ'&&ꢇꢙꢙꢇ0ꢛꢋꢐꢅꢑꢐꢇꢃꢄꢋ+ꢐ#
!ꢛꢐꢄ" 4ꢊꢈꢄ'ꢌꢇꢄ(ꢊ"'ꢄꢋ#ꢈꢈꢇꢃ'ꢄꢒꢅꢋ5ꢅꢐꢇꢄ$ꢈꢅ+ꢂꢃꢐ")ꢄꢒꢆꢇꢅ"ꢇꢄ"ꢇꢇꢄ'ꢌꢇꢄꢓꢂꢋꢈꢊꢋꢌꢂꢒꢄ ꢅꢋ5ꢅꢐꢂꢃꢐꢄꢏꢒꢇꢋꢂ&ꢂꢋꢅ'ꢂꢊꢃꢄꢆꢊꢋꢅ'ꢇ$ꢄꢅ'ꢄ
ꢌ''ꢒ366+++ꢁ(ꢂꢋꢈꢊꢋꢌꢂꢒꢁꢋꢊ(6ꢒꢅꢋ5ꢅꢐꢂꢃꢐ
2011-2014 Microchip Technology Inc.
DS40001579E-page 425
PIC16(L)F1782/3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001579E-page 426
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2014 Microchip Technology Inc.
DS40001579E-page 427
PIC16(L)F1782/3
DS40001579E-page 428
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (04/2011)
Original release.
Revision B (06/2011)
Revised Section 18.0; Revised Table 30-8; Add
Operational Amplifier Table.
Revision C (03/2012)
Electrical Specifications update.
Revision D (11/2012)
Revised: Table 5-4, Section 6.2.1.3, 9.0, Table 15-1
(LDO), Figure 16-1, Section 17.1.6, 17.2.3, 20.7, 24.1,
24.1.1-24.1.3, 24.2.7, 24.2.8, 24.3.4.1, 24.3.11,
24.8.1.1-24.8.1.3; Register 24.2 (PxMSRC descrip-
tion); Registers 24-9-24-13, 24-16, 25-1 (Bits 0-3
descriptions); Add Table 16-2, Section 24.2.7.3.
Electrical Specifications update: Revised 30.2 (D010,
D012), 30.3 (D023, D025, D026, D029-D031); Table
30-4 (delete Note 2); Table 30-1 (Param. OPA08,
OPA09), Table 30-11, Table 30-12 (Param. DAC02).
Revision E (3/2014)
Change from Preliminary to Final data sheet.
Corrected the following Tables: Family Types Table on
page 3, Table 3-3, Table 3-8, Table 20-3, Table 22-2,
Table 22-3, Table 23-1, Table 25-3, Table 30-1, Table
30-2, Table 30-3, Table 30-6, Table 30-7, Table 30-13,
Table 30-14, Table 30-15, Table 30-16, Table 30-20.
Corrected the following Sections: Section 3.2, Section
9.2, Section 13.3, Section 17.1.6, Section 15.1, Section
15.3, Section 17.2.5, Section 18.2, Section 18.3, Sec-
tion 19.0, Section 22.6.5, Section 22.9, Section 23.0,
Section 23.1, Section 24.2.4, Section 24.2.5, Section
24.2.7, Section 24.8, Section 25.0, Section 26.6.7.4,
Section 30.3.
Corrected the following Registers: Register 4-2, Regis-
ter 8-2, Register 8-5, Register 17-3, Register 18-1,
Register 24-3, Register 24-4.
Corrected Equation 17-1.
Corrected Figure 30-9. Removed Figure 24-21.
2011-2014 Microchip Technology Inc.
DS40001579E-page 429
PIC16(L)F1782/3
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
DS40001579E-page 430
2011-2014 Microchip Technology Inc.
PIC16(L)F1782/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
[X]
PART NO.
X
/XX
XXX
-
Examples:
Device Tape and Reel
Option
Temperature
Range
Package
Pattern
a)
PIC16LF1782T- I/MV 301
Tape and Reel,
Industrial temperature,
UQFN package,
QTP pattern #301
b)
c)
PIC16LF1783- I/P
Industrial temperature
SPDIP package
Device:
PIC16F1782, PIC16LF1782,
PIC16F1783, PIC16LF1783
PIC16F1783- E/SS
Extended temperature,
SSOP package
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T
= Tape and Reel(1)
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:
ML
MV
SP
SO
SS
= QFN
= UQFN
= SPDIP
= SOIC
= SSOP
Note 1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
Pattern:
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2:
Small form-factor packaging options may
be available. Please check
www.microchip.com/packaging for
small-form factor package availability, or
contact your local Sales Office.
2011-2014 Microchip Technology Inc.
DS40001579E-page 431
PIC16(L)F1782/3
NOTES:
DS40001579E-page 432
2011-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-63276-249-8
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2011-2014 Microchip Technology Inc.
DS40001579E-page 433
Worldwide Sales and Service
AMERICAS
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EUROPE
Corporate Office
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Technical Support:
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support
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Fax: 82-53-744-4302
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Poland - Warsaw
Tel: 48-22-3325737
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Sweden - Stockholm
Tel: 46-8-5090-4654
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Novi, MI
Tel: 248-848-4000
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
DS40001579E-page 434
2011-2014 Microchip Technology Inc.
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