PIC16LF18445-E/SSSQTP

PIC16(L)F18425/45

14/20-Pin Full-Featured, Low Pin Count Microcontrollers

with XLP

Description

PIC16(L)F184XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and

communication peripherals combined with eXtreme Low-Power (XLP) for a wide range of general purpose and low-

power applications. Features such as a 12-bit Analog-to-Digital Converter with Computation (ADC²), Memory Access

Partitioning (MAP), the Device Information Area (DIA), Power-Saving operating modes, and Peripheral Pin Select

(PPS), offer flexible solutions for a wide variety of custom applications.

Core Features

•

C Compiler Optimized RISC Architecture

Operating Speed:

– DC – 32 MHz clock input

– 125 ns minimum instruction cycle

Interrupt Capability

•

16-Level Deep Hardware Stack

Up to Four 8-Bit Timers

Up to Four 16-Bit Timers

Low-Current Power-on Reset (POR)

Configurable Power-up Timer (PWRT)

Brown-out Reset (BOR)

Low-Power BOR (LPBOR) Option

Windowed Watchdog Timer (WWDT):

– Variable prescaler selection

– Variable window size selection

– All sources configurable in hardware or software

Programmable Code Protection

•

Memory

•

Up to 28 Kbytes Program Flash Memory

Up to 2 KB Data SRAM Memory

256B Data EEPROM

Direct, Indirect and Relative Addressing Modes

Memory Access Partition (MAP):

– Write-protect

– Customizable partition

•

Device Information Area (DIA)

Device Characteristics Information (DCI)

DS40002002B-page 1

Datasheet

PIC16(L)F18425/45

Operating Characteristics

•

Operating Voltage Range:

– 1.8V to 3.6V (PIC16LF184XX)

– 2.3V to 5.5V (PIC16F184XX)

Temperature Range:

•

– Industrial: -40°C to 85°C

– Extended: -40°C to 125°C

eXtreme Low-Power (XLP) Features

•

Doze: CPU and Peripherals Running at Different Cycle Rates (Typically CPU is Lower)

Idle: CPU Halted While Peripherals Operate

Sleep: Lowest Power Consumption

Peripheral Module Disable (PMD):

– Ability to selectively disable hardware module to minimize active power consumption of unused peripherals

Extreme Low-Power Mode (XLP)

•

– Sleep: 500 nA typical @ 1.8V

– Sleep and Watchdog Timer: 900 nA typical @ 1.8V

Power-Saving Operation Modes

•

Sleep Mode: 50 nA @ 1.8V, Typical

Watchdog Timer: 500 nA @ 1.8V, Typical

Secondary Oscillator: 500 nA @ 32 kHz

Operating Current:

– 8 uA @ 32 kHz, 1.8V, typical

– 32 uA/MHz @ 1.8V, typical

Digital Peripherals

•

Configurable Logic Cell (CLC):

– Four CLCs

– Integrated combinational and sequential logic

Complementary Waveform Generator (CWG):

– Two CWGs

•

– Rising and falling edge dead-band control

– Full-bridge, half-bridge, 1-channel drive

– Multiple signal sources

•

Capture/Compare/PWM (CCP) Modules:

– Four CCPs

– 16-bit resolution for Capture/Compare modes

– 10-bit resolution for PWM mode

Pulse-Width Modulators (PWM):

•

– Two 10-bit PWMs

Numerically Controlled Oscillator (NCO):

– Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock

– Input Clock: 0 Hz < f_NCO< 32 MHz

– Resolution: f_NCO/2²⁰

DS40002002B-page 2

Datasheet

PIC16(L)F18425/45

•

Serial Communications:

– EUSART

•

One EUSART(s)

RS-232, RS-485, LIN compatible

Auto-Baud Detect, Auto-wake-up on Start.

– Master Synchronous Serial Port (MSSP)

•

Two MSSP(s)

SPI

I²C, SMBus and PMBus^™compatible

•

Data Signal Modulator (DSM):

– Modulates a carrier signal with digital data to create custom carrier synchronized output waveforms

Up to 18 I/O Pins:

– Individually programmable pull-ups

– Slew rate control

– Interrupt-on-change with edge-select

– Input level selection control (ST or TTL)

– Digital open-drain enable

Peripheral Pin Select (PPS):

– I/O pin remapping of digital peripherals

Timer Modules:

•

– Timer0:

•

8/16-bit timer/counter

Synchronous or asynchronous operation

Programmable prescaler/postscaler

Time base for capture/compare function

– Timer1/3/5 with gate control:

•

16-bit timer/counter

Programmable internal or external clock sources

Multiple gate sources

Multiple gate modes

Time base for capture/compare function

– Timer2/4/6 with Hardware Limit Timer:

•

8-bit timers

Programmable prescaler/postscaler

Time base for PWM function

Hardware Limit (HLT) and one-shot extensions

Selectable clock sources

– Signal Measurement Timer (SMT):

•

One SMT(s)

24-bit timer/counter with programmable prescaler

Analog Peripherals

•

12-bit Analog-to-Digital Converter with Computation (ADC²):

– up to 140 ksps

– up to 17 external channels

– Conversion available during Sleep

– Automated post-processing

– Automated math functions on input signals:

DS40002002B-page 3

Datasheet

PIC16(L)F18425/45

•

Averaging, filter calculations, oversampling and threshold comparison

– Integrated charge pump for low-voltage operation

– CVD support

•

Zero-Cross Detect (ZCD):

– AC high voltage zero-crossing detection

– Synchronized switching control and timing

Temperature Sensor Circuit

•

Comparator:

– Two Comparators

– Fixed Voltage Reference at (non)inverting input(s)

– Comparator outputs externally accessible

Digital-to-Analog Converter (DAC):

– 5-bit resolution, rail-to-rail

•

– Positive Reference Selection

– Unbuffered I/O pin output

– Internal connections to ADC²and comparators

Fixed Voltage Reference with 1.024V, 2.048V and 4.096V Output Levels

Flexible Oscillator Structure

•

High-Precision Internal Oscillator:

– Software-selectable frequency range up to 32 MHz

– ±2% at calibration (nominal)

•

4x PLL for use with External Sources:

– up to 32 MHz (4-8 MHz input)

2x PLL for use with the HFINTOSC:

– up to 32 MHz

•

Low-Power Internal 31 kHz Oscillator (LFINTOSC)

External 32.768 kHz Crystal Oscillator (SOCS)

External Oscillator Block with:

– Three crystal/resonator modes up to 20 MHz

– Three external clock modes up to 32 MHz

Fail-Safe Clock Monitor:

•

– Detects clock source failure

Oscillator Start-up Timer (OST):

– Ensures stability of crystal oscillator sources

DS40002002B-page 4

Datasheet

PIC16(L)F18425/45

PIC16(L)F184XX Family Types

Table 1.ꢀDevices Included In This Data Sheet

PIC16(L)F18425

PIC16(L)F18445

8

14 256 1024 12 11

14 256 1024 18 17

1

2

1

4/4

4

2

1

2

4

1

Y

I

Note:ꢀ

1. One pin is input-only.

2. Debugging Methods: (I) - Integrated on Chip; (E) - using Emulation Header.

Table 2.ꢀDevices Not Included In This Data Sheet

PIC16(L)F18424

PIC16(L)F18426

PIC16(L)F18444

PIC16(L)F18446

PIC16(L)F18455

PIC16(L)F18456

4

7

256 512 12 11

16 28 256 2048 12 11

256 512 18 17

16 28 256 2048 18 17

14 256 1024 26 24

16 28 256 2048 26 24

1

2

3

1

4/4

4

5

2

1

2

1

2

1

2

4

1

Y

I

4

7

8

Data Sheet Index:

1. DS40001985A, PIC16(L)F18426/46 Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with

XLP

2. DS40002000A, PIC16(L)F18424/44 Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with

XLP

3. DS40002038B, PIC16(L)F18455/56 Data Sheet, 28-Pin Full-Featured, Low Pin Count Microcontrollers with

XLP

DS40002002B-page 5

Datasheet

PIC16(L)F18425/45

Packages

UQFN

Packages

PDIP

SOIC

SSOP

TSSOP

(4x4)

PIC16(L)F18425

PIC16(L)F18445

●

Note:ꢀ Pin details are subject to change.

Important:ꢀ For other small form-factor package availability and marking information, visit

www.microchip.com/ packaging or contact your local sales office.

Pin Diagrams

14/16-Pin Diagrams

Figure 1.ꢀ14-Pin PDIP, SOIC, TSSOP

Rev. 00-000014A

6/21/2017

VDD

RA5

RA4

1

2

3

VSS

14

13 RA0/ICSPDAT

12

11

10

9

RA1/ICSPCLK

RA2

MCLR/VPP/RA3

4

5

6

7

RC5

RC4

RC3

RC0

RC1

RC2

8

Figure 2.ꢀ16-Pin UQFN (4x4)

Rev. 00-000016A

6/21/2017

16 15 14

13

RA0/ICSPDAT

RA1/ICSPCLK

RA2

12

11

10

9

1

2

3

4

RA5

RA4

MCLR/VPP/RA3

RC5

RC0

8

6

7

5

Note:ꢀ It is recommended that the exposed bottom pad be connected to V_SS

.

See Table 3 for more information.

DS40002002B-page 6

Datasheet

PIC16(L)F18425/45

20-Pin Diagrams

Figure 3.ꢀ20-Pin PDIP, SOIC, SSOP

Rev. 00-000020A

6/21/2017

VSS

VDD

RA5

RA4

1

2

3

4

5

6

7

8

20

19 RA0/ICSPDAT

RA1/ICSPCLK

18

17 RA2

MCLR/VPP/RA3

16

15

14

RC5

RC4

RC3

RC6

RC7

RB7

RC0

RC1

RC2

RB4

RB5

RB6

13

12

11

9

10

Figure 4.ꢀ20-Pin UQFN (4x4)

Rev. 00-000020B

6/21/2016

20 19 18

17 16

RA1/ICSPCLK

15

14

13

12

11

1

2

3

4

5

MCLR/VPP/RA3

RA2

RC0

RC1

RC2

RC5

RC4

RC3

RC6

9

10

7

8

6

Note:ꢀ It is recommended that the exposed bottom pad be connected to V_SS

.

See Table 4 for more information.

DS40002002B-page 7

Datasheet

PIC16(L)F18425/45

Pin Allocation Tables

Table 3.ꢀ14/16-Pin Allocation Table

ICDDAT

(1)

RA0

RA1

RA2

RA3

13

12

11

4

12

11

10

3

ANA0

ANA1

ANA2

—

C1IN0+

—

DAC1OUT1

DAC1VREF+

DAC1VREF-

—

MDSRC

—

SS2

—

IOCA0

IOCA1

IOCA2

IOCA3

Y

ICSPDAT

C1IN0

ICDCLK

ADCVREF+

ADCVREF-

—

C2IN0-

ICSPCLK

(1)

CWG1IN

CWG2IN

(1)

—

T0CKI

CCP3IN

—

ZCD1

—

INT

MCLR

(1)

T6IN

—

V

PP

CLKOUT

SOSCO

OSC2

(1)

T1G

SMT1WIN

RA4

RA5

3

2

1

ANA4

—

IOCA4

IOCA5

Y

(1)

T1CKI

CLKIN

SOSCI

OSC1

(1)

ANA5

ANC0

—

T2IN

—

CLCIN3

(1)

SMT1SIG

(1)

SCK1

(1)

RC0

RC1

RC2

RC3

RC4

RC5

10

9

8

7

6

5

4

—

C2IN0+

—

T5CKI

—

CCP4IN

—

CLCIN2

—

IOCC0

IOCC1

IOCC2

IOCC3

IOCC4

IOCC5

Y

—

(1,3,4)

SCL1

(1)

C1IN1-

C2IN1-

SDI1

(1)

ANC1

ANC2

T4IN

(1,3,4)

SDA1

C1IN2-

C2IN2-

(1)

8

MDCARL

—

(1)

ADACT

C1IN3-

C2IN3-

(1)

7

ANC3

—

T5G

T3G

CCP2IN

—

SS1

CLCIN0

CLCIN1

—

(1,5)

SCK2

(1)

(1,3)

(1)

6

ANC4

ANC5

—

CK1

(1,3,4,5)

SCL2

(1,5)

(1)

SDI2

RX1

(1)

5

MDCARH

T3CKI

CCP1IN

(1,3,4,5)

(1,3)

DT1

SDA2

V

1

16

13

—

V

DD

V

14

—

V

SS

CWG1A

CWG2A

(3)

—

ADCGRDA

—

C1OUT

C2OUT

—

NCO1OUT

—

DSM1OUT

TMR0OUT

CCP1OUT

CCP2OUT

CCP3OUT

CCP4OUT

PWM6OUT

SDO1 SDO2

SCK1 SCK2

—

DT1

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

CLKR

—

CWG1B

CWG2B

(3)

ADCGRDB

—

PWM7OUT

CK1

(2)

OUT

(3)

CWG1C

CWG2C

SCL1

—

TX1

—

(3)

SCL2

(3)

CWG1D

CWG2D

SDA1

—

(3)

SDA2

Table 4.ꢀ20-Pin Allocation Table

ICDDAT/

ICSPDAT

RA0

RA1

RA2

RA3

19

18

17

4

16

15

14

1

ANA0

ANA1

ANA2

—

C1IN0+

—

DAC1OUT1

DAC1VREF+

DAC1VREF-

—

IOCA0

IOCA1

IOCA2

IOCA3

Y

C1IN0-

C2IN0-

ICDCLK/

ICSPCLK

(1)

ADCVREF+

ADCVREF-

—

MDSRC

SS2

(1)

CWG1IN

CWG2IN

(1)

—

T0CKI

—

ZCD1

—

CLCIN0

INT

(1)

MCLR

—

V

PP

DS40002002B-page 8

Datasheet

PIC16(L)F18425/45

...........continued

CLKOUT

SOSCO

OSC2

(1)

T1G

SMT1WIN

(1)

RA4

RA5

3

2

20

19

ANA4

ANA5

—

CCP4IN

—

IOCA4

IOCA5

Y

(1)

T1CKI

CLKIN

SOSCI

OSC1

(1)

T2IN

—

(1)

SMT1SIG

(1)

SDI1

(1)

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

13

12

11

10

16

15

14

7

10

9

ANB4

ANB5

ANB6

ANB7

ANC0

—

T5G

—

CCP3IN

—

CLCIN2

CLCIN3

—

IOCB4

IOCB5

IOCB6

IOCB7

IOCC0

IOCC1

IOCC2

IOCC3

Y

—

(1,3,4)

SDA1

(1,5)

(1)

RX1

SDI2

(1)

—

(1,3,4,5)

(1,3)

SDA2

DT1

(1)

SCK1

8

—

(1,3,4)

SCL1

(1,5)

SCK2

(1)

T6IN

(1,3)

CK1

7

—

(1,3,4,5)

SCL2

(1)

T3CKI

13

12

11

4

C2IN0+

—

(1)

T3G

C1IN1-

C2IN1-

ANC1

ANC2

—

C1IN2-

C2IN2-

(1)

MDCARL

T5CKI

—

(1)

ADACT

C1IN3-

C2IN3-

(1)

ANC3

—

CCP2IN

CLCIN1

RC4

RC5

RC6

RC7

6

5

3

2

ANC4

ANC5

ANC6

ANC7

—

CCP1IN

—

IOCC4

IOCC5

IOCC6

IOCC7

—

Y

—

(1)

MDCARH

T4IN

(1)

8

5

—

SS1

Y

9

6

—

Y

V

DD

1

18

17

—

V

DD

V

20

—

V

SS

CWG1A

CWG2A

(3)

—

ADCGRDA

—

C1OUT

C2OUT

—

NCO1OUT

—

DSM1OUT

TMR0OUT

CCP1OUT

CCP2OUT

CCP3OUT

CCP4OUT

PWM6OUT

SDO1 SDO2

SCK1 SCK2

—

DT1

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

CLKR

—

CWG1B

CWG2B

(3)

ADCGRDB

—

PWM7OUT

CK1

(2)

OUT

(3)

CWG1C

CWG2C

SCL1

—

TX1

—

(3)

SCL2

(3)

CWG1D

CWG2D

SDA1

—

(3)

SDA2

Note:ꢀ

1. Default peripheral input. Input can be moved to any other pin with the PPS input selections registers.

2. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripherals output with the PPS

output selection registers.

3. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin

selections.

4. These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins.

Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected y

the INLVL register.

DS40002002B-page 9

Datasheet

PIC16(L)F18425/45

Table of Contents

Description..................................................................................................................................................... 1

Core Features................................................................................................................................................ 1

Memory.......................................................................................................................................................... 1

Operating Characteristics...............................................................................................................................2

eXtreme Low-Power (XLP) Features............................................................................................................. 2

Power-Saving Operation Modes.................................................................................................................... 2

Digital Peripherals.......................................................................................................................................... 2

Analog Peripherals.........................................................................................................................................3

Flexible Oscillator Structure........................................................................................................................... 4

PIC16(L)F184XX Family Types......................................................................................................................5

Packages........................................................................................................................................................6

Pin Diagrams..................................................................................................................................................6

Pin Allocation Tables...................................................................................................................................... 8

1. Device Overview................................................................................................................................... 13

2. Guidelines for Getting Started with PIC16(L)F18425/45 Microcontrollers............................................ 19

3. Enhanced Mid-Range CPU...................................................................................................................24

4. Device Configuration.............................................................................................................................26

5. Memory Organization............................................................................................................................39

6. NVM - Nonvolatile Memory Control ......................................................................................................76

7. Interrupts...............................................................................................................................................98

8. OSC - Oscillator Module..................................................................................................................... 122

9. REFCLK - Reference Clock Output Module........................................................................................143

10. Resets.................................................................................................................................................148

11. WWDT - Windowed Watchdog Timer .................................................................................................161

12. Power-Saving Operation Modes......................................................................................................... 172

13. PMD - Peripheral Module Disable.......................................................................................................181

14. I/O Ports..............................................................................................................................................191

15. IOC - Interrupt-On-Change................................................................................................................. 221

16. PPS - Peripheral Pin Select Module .................................................................................................. 233

DS40002002B-page 10

Datasheet

PIC16(L)F18425/45

17. CLC - Configurable Logic Cell.............................................................................................................244

18. TMR0 - Timer0 Module....................................................................................................................... 267

19. TMR1 - Timer1 Module with Gate Control...........................................................................................275

20. TMR2 - Timer2 Module....................................................................................................................... 293

21. SMT - Signal Measurement Timer...................................................................................................... 315

22. Capture/Compare/PWM Module.........................................................................................................338

23. CCP/PWM Timer Resource Selection.................................................................................................351

24. PWM - Pulse-Width Modulation.......................................................................................................... 355

25. CWG - Complementary Waveform Generator.................................................................................... 363

26. NCO - Numerically Controlled Oscillator.............................................................................................390

27. DSM - Data Signal Modulator Module.................................................................................................400

28. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter...........................411

29. MSSP - Master Synchronous Serial Port Module............................................................................... 441

30. FVR - Fixed Voltage Reference.......................................................................................................... 500

31. Temperature Indicator Module............................................................................................................ 504

32. ADC²- Analog-to-Digital Converter.....................................................................................................507

33. DAC - 5-Bit Digital-to-Analog Converter..............................................................................................552

34. CMP - Comparator Module................................................................................................................. 558

35. ZCD - Zero-Cross Detection Module...................................................................................................570

36. Register Summary.............................................................................................................................. 577

™

37. ICSP - In-Circuit Serial Programming ........................................................................................... 602

38. Instruction Set Summary.....................................................................................................................605

39. Development Support......................................................................................................................... 625

40. Electrical Specifications...................................................................................................................... 629

41. DC and AC Characteristics Graphs and Tables..................................................................................661

42. Packaging Information........................................................................................................................ 682

43. Revision History.................................................................................................................................. 704

The Microchip Website...............................................................................................................................705

Product Change Notification Service..........................................................................................................705

Customer Support...................................................................................................................................... 705

DS40002002B-page 11

Datasheet

PIC16(L)F18425/45

Product Identification System.....................................................................................................................706

Microchip Devices Code Protection Feature..............................................................................................706

Legal Notice............................................................................................................................................... 707

Trademarks................................................................................................................................................ 707

Quality Management System..................................................................................................................... 707

Worldwide Sales and Service.....................................................................................................................708

DS40002002B-page 12

Datasheet

PIC16(L)F18425/45

Device Overview

1.

Device Overview

This document contains device-specific information for the following devices:

•

PIC16F18425

PIC16F18445

•

PIC16LF18425

PIC16LF18445

1.1

New Core Features

1.1.1

XLP Technology

All of the devices in the PIC16(L)F184XX family incorporate a range of features that can significantly reduce power

consumption during operation. Key items include:

•

Alternate Run Modes: By clocking the controller from the secondary oscillator or the internal oscillator block,

power consumption during code execution can be reduced by as much as 90%.

•

Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In

these states, power consumption can be reduced even further, to as little as 4% of normal operation

requirements.

•

On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing

the user to incorporate power-saving ideas into their application’s software design.

Peripheral Module Disable: Modules that are not being used in the code can be selectively disabled using the

PMD module. This further reduces the power consumption.

1.1.2

Multiple Oscillator Options and Features

All of the devices in the PIC16(L)F184XX family offer several different oscillator options. The PIC16(L)F184XX family

can be clocked from several different sources:

•

HFINTOSC

– 1-32 MHz precision digitally controlled internal oscillator

LFINTOSC

– 31 kHz internal oscillator

EXTOSC

– External clock (EC)

– Low-power oscillator (LP)

– Medium-power oscillator (XT)

– High-power oscillator (HS)

SOSC

•

– Secondary oscillator circuit optimized for 32 kHz clock crystals

•

A Phase Lock Loop (PLL) frequency multiplier (2x/4x) is available to the External Oscillator modes enabling

clock speeds of up to 32 MHz

Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal

provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal oscillator block,

allowing for continued operation or a safe application shutdown.

1.2

Other Special Features

•

12-bit A/D Converter with Computation: This module incorporates programmable acquisition time, allowing for a

channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce

code overhead. It has a new module called ADC²with computation features, which provides a digital filter and

threshold interrupt functions.

DS40002002B-page 13

Datasheet

PIC16(L)F18425/45

Device Overview

•

Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many

thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without

refresh is conservatively estimated to be greater than 40 years.

Self-programmability: These devices can write to their own program memory spaces under internal software

control. By using a boot loader routine located in the protected Boot Block at the top of program memory, it

becomes possible to create an application that can update itself in the field.

Enhanced Peripheral Pin Select: The Peripheral Pin Select (PPS) module connects peripheral inputs and

outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs

remain fixed to their assigned pins.

Windowed Watchdog Timer (WWDT):

– Timer monitoring of overflow and underflow events

– Variable prescaler selection

– Variable window size selection

– All sources configurable in hardware or software

1.3

Details on Individual Family Members

The devices of the PIC16(L)F184XX family described in the current datasheet are available in 14/20-pin packages.

The block diagram for this device is shown in Figure 1-1.

The devices have the following differences:

1. Program Flash Memory

2. Data Memory SRAM

3. Data Memory EEPROM

4. A/D channels

5. I/O ports

6. Enhanced USART

7. Input Voltage Range/Power Consumption

All other features for devices in this family are identical. These are summarized in the following Device Features

table.

The pinouts for all devices are listed in the pin summary tables.

Table 1-1.ꢀDevice Features

Features

PIC16(L)F18425

14

PIC16(L)F18445

14

Program Memory (KBytes)

Program Memory (Instructions)

Data Memory (Bytes)

8192

1024

Data EEPROM Memory (Bytes)

256

14 - PDIP

14 - SOIC (3.9 mm)

14 - TSSOP

16 - uQFN (4x4)

20 - PDIP

20 - SOIC (7.5 mm)

20 - SSOP

20 - uQFN (4x4)

Packages

I/O Ports

A, C

4

A, B, C

4

Capture/Compare/PWM Modules

(CCP)

Configurable Logic Cell (CLC)

4

2

4

2

10-Bit Pulse-Width Modulator (PWM)

DS40002002B-page 14

Datasheet

PIC16(L)F18425/45

Device Overview

...........continued

Features

PIC16(L)F18425

PIC16(L)F18445

12-Bit Analog-to-Digital Module

(ADC²) with Computation Accelerator

11 channels

17 channels

5-Bit Digital-to-Analog Module (DAC)

Comparators

1

2

1

2

Numerical Contolled Oscillator

(NCO)

1

Interrupt Sources

Timers (16-/8-bit)

40

4

40

4

2 MSSP

1 EUSART

2 MSSP

1 EUSART

Serial Communications

Complementary Waveform

Generator (CWG)

2

Zero-Cross Detect (ZCD)

1

Data Signal Modulator (DSM)

Reference Clock Output Module

Peripheral Pin Select (PPS)

Peripheral Module Disable (PMD)

1

YES

Programmable Brown-out Reset

(BOR)

YES

POR, BOR, RESETInstruction, Stack POR, BOR, RESETInstruction, Stack

Resets (and Delays)

Overflow, Stack Underflow (PWRT,

OST), MCLR, WDT

Overflow, Stack Underflow (PWRT,

OST), MCLR, WDT

50 instructions

Instruction Set

16-levels hardware stack

Operating Frequency

DC – 32 MHz

DS40002002B-page 15

Datasheet

PIC16(L)F18425/45

Device Overview

Figure 1-1.ꢀPIC16(L)F18425/45 Device Block Diagram

Program

Flash Memory

Rev. 10-000039V

7/7/2017

RAM

PORTA

Timing

Generation

PORTB⁽²⁾

PORTC

CLKOUT/OSC2

CLKIN/OSC1

EXTOSC

Oscillator

CPU

Secondary

Oscillator

(SOSC)

SOSCI

SOSCO

MCLR

ADC²

12-bit

NCO1

PWM7

PWM6

Timer6

Timer4

Timer3

Timer2

Timer1

Timer0

C2

C1

DAC1

FVR

Timer5

Temp

Indicator

CWG2

CWG1

WDT

EUSART1

MSSP1

CLC4

CLC3

CLC2

CLC1

SMU1

CCP4

CCP3

CCP2

CCP1

MSSP2

Note:ꢀ

1. See applicable chapters for more information on peripherals.

2. PORTB available only on 20-pin or higher pin-count devices.

1.4

Register and Bit Naming Conventions

1.4.1

Register Names

When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted

as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section

will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This

naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device

to maintain compatibility with other devices in the family that contain more than one.

1.4.2

Bit Names

There are two variants for bit names:

•

Short name: Bit function abbreviation

Long name: Peripheral abbreviation + short name

1.4.2.1 Short Bit Names

Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit.

The bit names shown in the registers are the short name variant.

Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short

name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the CM1CON0 register can be set in C

programs with the instruction CM1CON0bits.EN = 1.

Short names are generally not useful in assembly programs because the same name may be used by different

peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit

name are appended with an underscore plus the name of the register in which the bit resides to avoid naming

contentions.

DS40002002B-page 16

Datasheet

PIC16(L)F18425/45

Device Overview

1.4.2.2 Long Bit Names

Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to

the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1

prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN.

Important:ꢀ The COG1 peripheral is used as an example. Not all devices have the COG peripheral.

Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be

set with the G1EN = 1instruction. In assembly, this bit can be set with the BSF COG1CON0,G1ENinstruction.

1.4.2.3 Bit Fields

Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention.

For example, the three Least Significant bits of the COG1CON0 register contain the Mode Control bits. The short

name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The

following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode:

COG1CON0bits.MD = 0x5;

Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended

with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name

MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for

setting the COG1 to Push-Pull mode:

Example 1:

MOVLW ~(1<<G1MD1)

ANDWF COG1CON0,F

MOVLW 1<<G1MD2 | 1<<G1MD0

IORWF COG1CON0,F

Example 2:

BSF

BCF

BSF

COG1CON0,G1MD2

COG1CON0,G1MD1

COG1CON0,G1MD0

1.4.3

Register and Bit Naming Exceptions

1.4.3.1 Status, Interrupt, and Mirror Bits

Status, interrupt enables, Interrupt flags, and Mirror bits are contained in registers that span more than one

peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant.

1.4.3.2 Legacy Peripherals

There are some peripherals that do not strictly adhere to these naming conventions. Peripherals that have existed for

many years and are present in almost every device are the exceptions. These exceptions were necessary to limit the

adverse impact of the new conventions on legacy code. Peripherals that do adhere to the new convention will include

a table in the registers section indicating the long name prefix for each peripheral instance. Peripherals that fall into

the exception category will not have this table. These peripherals include, but are not limited to the following:

•

EUSART

MSSP

1.5

Register Legend

The table below describes the conventions for bit types and bit Reset values used in the current data sheet.

DS40002002B-page 17

Datasheet

PIC16(L)F18425/45

Device Overview

Table 1-2.ꢀRegister Legend

Value

Description

RO

W

U

Read-only bit

Writable bit

Unimplemented bit, read as ‘0’

Programmable bit

Bit is set

P

‘1’

‘0’

x

Bit is cleared

Bit is unknown

Bit is unchanged

u

-n/n

q

Value at POR and BOR/Value at all other Resets

Reset Value is determined by hardware

f

Reset Value is determined by fuse setting

Reset Value at POR for PPS re-mappable signals

g

DS40002002B-page 18

Datasheet

PIC16(L)F18425/45

Guidelines for Getting Started with PIC16(L)F18425...

2.

Guidelines for Getting Started with PIC16(L)F18425/45

Microcontrollers

2.1

Basic Connection Requirements

Getting started with the PIC16(L)F18425/45 family of 8-bit microcontrollers requires attention to a minimal set of

device pin connections before proceeding with development.

The following pins must always be connected:

•

All V_DDand V_SSpins (see 2.2 Power Supply Pins)

MCLR pin (see 2.3 Master Clear (MCLR) Pin)

These pins must also be connected if they are being used in the end application:

•

PGC/PGD pins used for In-Circuit Serial Programming^™(ICSP^™) and debugging purposes (see 2.4 In-Circuit

Serial Programming (ICSP) Pins)

•

OSCI and OSCO pins when an external oscillator source is used (see 2.5 External Oscillator Pins)

Additionally, the following may be required:

V_REF+/V_REF- pins are used when external voltage reference for analog modules is implemented

•

The minimum mandatory connections are shown in the figure below.

Figure 2-1.ꢀRecommended Minimum Connections

Rev. 10-000249B

6/27/2017

C2

VDD

R1

R2

MCLR

C1

PIC16(L)Fxxxxx

Vss

Key (all values are recommendations):

C1: 10 nF, 16V ceramic

C2: 0.1 uF, 16V ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

2.2

Power Supply Pins

2.2.1

Decoupling Capacitors

The use of decoupling capacitors on every pair of power supply pins (V_DDand V_SS) is required.

Consider the following criteria when using decoupling capacitors:

•

Value and type of capacitor: A 0.1 μF (100 nF), 10-25V capacitor is recommended. The capacitor should be a

low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are

recommended.

Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as

possible. It is recommended to place the capacitors on the same side of the board as the device. If space is

constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater than 0.25 inch (6 mm).

DS40002002B-page 19

Datasheet

PIC16(L)F18425/45

Guidelines for Getting Started with PIC16(L)F18425...

•

Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a

second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second

capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to each primary

decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as

close to the power and ground pins as possible (e.g., 0.1 μF in parallel with 0.001 μF).

Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to

the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first

in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a

minimum, thereby reducing PCB trace inductance.

2.2.2

Tank Capacitors

On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for

integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should

be determined based on the trace resistance that connects the power supply source to the device, and the maximum

current drawn by the device in the application. In other words, select the tank capacitor that meets the acceptable

voltage sag at the device. Typical values range from 4.7 μF to 47 μF.

2.3

Master Clear (MCLR) Pin

The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If

programming and debugging are not required in the end application, a direct connection to V_DDmay be all that is

required. The addition of other components, to help increase the application’s resistance to spurious Resets from

voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be

implemented, depending on the application’s requirements.

During programming and debugging, the resistance and capacitance that can be added to the pin must be

considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (V_IHand

V_IL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be

adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be

isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The

jumper is replaced for normal run-time operations.

Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin.

Figure 2-2.ꢀExample of MCLR Pin Connections

Rev. 30-000058A

6/23/2017

VDD

R1

R2

MCLR

JP

C1

Note:ꢀ

1. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin V_IHand V_IL

specifications are met.

2. R2 ≤ 470Ω will limit any current flowing into MCLR from the extended capacitor, C1, in the event of MCLR pin

breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin

V_IHand V_ILspecifications are met.

2.4

In-Circuit Serial Programming^™(ICSP^™) Pins

The ICSPCLK and ICSPDAT pins are used for ICSP and debugging purposes. It is recommended to keep the trace

length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is

expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of

Ohms, not to exceed 100Ω.

DS40002002B-page 20

Datasheet

PIC16(L)F18425/45

Guidelines for Getting Started with PIC16(L)F18425...

Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended as they

can interfere with the programmer/debugger communications to the device. If such discrete components are an

application requirement, they should be removed from the circuit during programming and debugging. Alternatively,

refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming

specification for information on capacitive loading limits, and pin input voltage high (V_IH) and input low (V_IL)

requirements.

For device emulation, ensure that the “Communication Channel Select” (i.e., ICSPCLK/ICSPDAT pins), programmed

into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool.

For more information on available Microchip development tools connection requirements, refer to the “Development

Support” section.

Related Links

39. Development Support

2.5

External Oscillator Pins

Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-

frequency secondary oscillator.

The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to

the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The

load capacitors should be placed next to the oscillator itself, on the same side of the board.

Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper

pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground

pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed.

Layout suggestions are shown in the following figure. In-line packages may be handled with a single-sided layout that

completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely

surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer.

In all cases, the guard trace(s) must be returned to ground.

DS40002002B-page 21

Datasheet

PIC16(L)F18425/45

Guidelines for Getting Started with PIC16(L)F18425...

Figure 2-3.ꢀSuggested Placement of the Oscillator Circuit

Rev. 30-000059A

4/6/2017

Single-Sided and In-Line Layouts:

Copper Pour

(tied to ground)

Primary Oscillator

Crystal

DEVICE PINS

Primary

OSC1

Oscillator

C1

C2

`

OSC2

GND

SOSCO

SOSCI

Secondary Oscillator

(SOSC)

`

Crystal

SOSC: C2

SOSC: C1

Fine-Pitch (Dual-Sided) Layouts:

Top Layer Copper Pour

(tied to ground)

Bottom Layer

Copper Pour

(tied to ground)

OSCO

C2

Oscillator

Crystal

GND

C1

OSCI

DEVICE PINS

In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other signals in close

proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise).

For additional information and design guidance on oscillator circuits, refer to these Microchip Application Notes,

available at the corporate website (www.microchip.com):

®

™

•

AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC and PICmicro Devices”

AN849, “Basic PICmicro^®Oscillator Design”

AN943, “Practical PICmicro^®Oscillator Analysis and Design”

AN949, “Making Your Oscillator Work”

Related Links

8. OSC - Oscillator Module

DS40002002B-page 22

Datasheet

PIC16(L)F18425/45

Guidelines for Getting Started with PIC16(L)F18425...

2.6

Unused I/Os

Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10

kΩ resistor to V_SSon unused pins to drive the output to logic low.

DS40002002B-page 23

Datasheet

PIC16(L)F18425/45

Enhanced Mid-Range CPU

3.

Enhanced Mid-Range CPU

This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 50 instructions. Interrupt

capability includes automatic context saving. The hardware stack is 16-levels deep and has Overflow and Underflow

Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs)

provide the ability to read program and data memory.

Figure 3-1.ꢀCore Data Path Diagram

Rev. 10-000055C

11/30/2016

15

Configuration

Data Bus

15

8

Program Counter

Flash

Program

Memory

16-Level Stack

(15-bit)

RAM

14

Program

Bus

12

Program Memory

Read (PMR)

RAM Addr

Addr MUX

Instruction Reg

Indirect

Addr

Direct Addr

7

12

5

12

BSR Reg

15

FSR0 Reg

STATUS Reg

MUX

15

FSR1 Reg

8

3

Power-up

Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Instruction

Decode and

Control

ALU

8

CLKIN

CLKOUT

SOSCI

Timing

Generation

W Reg

SOSCO

VDD

VSS

Internal

Oscillator

Block

3.1

Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the

interrupt. This saves stack space and user code.

Related Links

7.5 Automatic Context Saving

DS40002002B-page 24

Datasheet

PIC16(L)F18425/45

Enhanced Mid-Range CPU

3.2

3.3

16-Level Stack with Overflow and Underflow

These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will

set the appropriate bit (STKOVF or STKUNF) in the PCON0 register, and if enabled, will cause a software Reset.

Related Links

5.5 Stack

10.14.2 PCON0

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which

allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction

cycle in instructions using INDF to allow the data to be fetched. General purpose memory can also be addressed

linearly, providing the ability to access contiguous data larger than 80 bytes.

Related Links

5.6 Indirect Addressing

3.4

Instruction Set

There are 50 instructions for the enhanced mid-range CPU to support the features of the CPU.

Related Links

38. Instruction Set Summary

DS40002002B-page 25

Datasheet

PIC16(L)F18425/45

Device Configuration

4.

Device Configuration

Device configuration consists of the Configuration Words, user ID, device ID, Device Information Area (DIA), and the

Device Configuration Information (DCI) regions.

Related Links

5.12 Device Information Area

5.11 Device Configuration Information

4.1

4.2

Configuration Words

There are five Configuration Words that allow the user to select the device oscillator, reset, and memory protection

options. These are implemented at 8007h through 800Bh.

Note:ꢀ The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including

debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

Code Protection

Code protection allows the device to be protected from unauthorized access. Internal access to the program memory

is unaffected by any code protection setting. A single code protect bit controls the access for both program memory

and data EEPROM memory.

The entire program memory and Data EEPROM space is protected from external reads and writes by the CP bit.

When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can

continue to read program memory, regardless of the protection bit settings. Self-writing the program memory is

dependent upon the write protection setting.

4.3

4.4

Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader

software, can be protected while allowing other regions of the program memory to be modified.

The WRT bits define the size of the program memory block that is protected.

User ID

Four words in the memory space (8000h-8003h) are designated as ID locations where the user can store checksum

or other code identification numbers. These locations are readable and writable during normal execution. See the

“NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and

Configuration Words” section for more information on accessing these memory locations. For more information on

checksum calculation, see the “PIC16(L)F184XX Memory Programming Specification”, (DS40001970A).

Related Links

6.4.7 NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and

Configuration Words

4.5

Device ID and Revision ID

The 14-bit Device ID word is located at 0x8006 and the 14-bit revision ID is located at 0x8005. These locations are

read-only and cannot be erased or modified.

Development tools, such as device programmers and debuggers, may be used to read the Device ID, Revision ID

and Configuration Words. Refer to the “Nonvolatile Memory (NVM) Control” section for more information on

accessing these locations.

DS40002002B-page 26

Datasheet

PIC16(L)F18425/45

Device Configuration

Related Links

6. NVM - Nonvolatile Memory Control

4.6

Register Summary - Configuration Words

Offset

Name

Bit Pos.

7:0

13:8

7:0

RSTOSC[2:0]

FCMEN

FEXTOSC[2:0]

CLKOUTEN

0x8007

0x8008

0x8009

0x800A

0x800B

CONFIG1

CSWEN

BOREN

LPBOREN

DEBUG

PWRTS[1:0]

MCLRE

CONFIG2

CONFIG3

CONFIG4

CONFIG5

13:8

7:0

STVREN

PPS1WAY

ZCDDIS

BORV

WDTE[1:0]

WDTCPS[4:0]

13:8

7:0

WDTCCS[2:0]

SAFEN

WDTCWS[2:0]

BBSIZE[2:0]

WRTC

WRTAPP

BBEN

13:8

7:0

LVP

WRTSAF

WRTD

WRTB

CP

13:8

4.7

Register Definitions: Configuration Words

DS40002002B-page 27

Datasheet

PIC16(L)F18425/45

Device Configuration

4.7.1

CONFIG1

Name:ꢀ

Offset:ꢀ

CONFIG1

0x8007

Configuration Word 1

Oscillators

Bit

15

7

14

13

FCMEN

R/P

12

11

CSWEN

R/P

10

9

8

CLKOUTEN

Access

Reset

U

1

U

1

U

1

R/P

1

Bit

6

5

4

3

2

1

0

RSTOSC[2:0]

FEXTOSC[2:0]

Access

Reset

U

1

R/P

1

R/P

1

R/P

1

U

1

R/P

1

R/P

1

R/P

1

Bit 13 – FCMENꢀFail-Safe Clock Monitor Enable bit

Value

Description

1

0

FSCM timer enabled

FSCM timer disabled

Bit 11 – CSWENꢀClock Switch Enable bit

Value

Description

1

Writing to NOSC and NDIV is allowed

0

The NOSC and NDIV bits cannot be changed by user software

Bit 8 – CLKOUTENꢀClock Out Enable bit

Value

Condition

Description

1

If FEXTOSC = EC (high, mid or low) or Not

Enabled

CLKOUT function is disabled; I/O or oscillator

function on OSC2

0

If FEXTOSC = EC (high, mid or low) or Not

Enabled

CLKOUT function is enabled; F_OSC/4 clock appears

at OSC2

Otherwise

This bit is ignored.

Bits 6:4 – RSTOSC[2:0]ꢀPower-up Default Value for COSC bits

This value is the Reset default value for COSC and selects the oscillator first used by user software. Refer to COSC

operation.

Value

111

Description

EXTOSC operating per FEXTOSC bits

110

HFINTOSC (1 MHz), with OSCFRQ = ‘010’ (4 MHz) and CDIV = ‘0010’ (4:1)

101

100

011

010

001

000

LFINTOSC

SOSC

Reserved

EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits

HFINTOSC with 2x PLL (32 MHz), with OSCFRQ = ‘101’ (16 MHz) and CDIV = ‘0000’ (1:1)

HFINTOSC with OSCFRQ = 32 MHz and CDIV = 1:1

Bits 2:0 – FEXTOSC[2:0]ꢀFEXTOSC External Oscillator Mode Selection bits

Value

111

110

101

100

011

Description

ECH (External Clock) above 8 MHz

ECM (External Clock) for 500 kHz to 8 MHz

ECL (External Clock) below 500 kHz

Oscillator not enabled

Reserved (do not use)

DS40002002B-page 28

Datasheet

PIC16(L)F18425/45

Device Configuration

Value

010

001

Description

HS (Crystal oscillator) above 4 MHz

XT (Crystal oscillator) above 100 kHz, below 4 MHz

LP (Crystal oscillator) optimized for 32.768 kHz

000

Related Links

8.6.7 OSCFRQ

8.6.2 OSCCON2

DS40002002B-page 29

Datasheet

PIC16(L)F18425/45

Device Configuration

4.7.2

CONFIG2

Name:ꢀ

Offset:ꢀ

CONFIG2

0x8008

Configuration Word 2

Supervisor

Bit

15

7

14

13

DEBUG

R/P

12

STVREN

R/P

11

PPS1WAY

R/P

10

ZCD

R/P

1

9

BORV

R/P

1

8

Access

Reset

U

1

Bit

6

5

LPBOREN

R/P

4

3

2

1

0

MCLRE

R/P

BOREN[1:0]

PWRTS[1:0]

Access

Reset

R/P

1

R/P

1

U

1

U

1

R/P

1

R/P

1

Bit 13 – DEBUGꢀ Debugger Enable bit⁽¹⁾

Value

Description

1

0

Background debugger disabled

Background debugger enabled

Bit 12 – STVRENꢀStack Overflow/Underflow Reset Enable bit

Value

Description

1

0

Stack Overflow or Underflow will cause a Reset

Stack Overflow or Underflow will not cause a Reset

Bit 11 – PPS1WAYꢀPPSLOCKED bit One-Way Set Enable bit

Value

Description

1

The PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one

clear/set cycle

0

The PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)

Bit 10 – ZCDꢀZCD Control bit

Value

Description

1

0

ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of the ZCDCON register.

ZCD always enabled, ZCDSEN bit is ignored

Bit 9 – BORVꢀ Brown-out Reset Voltage Selection bit⁽²⁾

Value

Description

1

0

Brown-out Reset voltage (V_BOR) set to lower trip point level

Brown-out Reset voltage (V_BOR) set to higher trip point level

Bits 7:6 – BOREN[1:0]ꢀBrown-out Reset Enable bits

When enabled, Brown-out Reset Voltage (V_BOR) is set by BORV bit

Value

11

10

01

00

Description

Brown-out Reset enabled, SBOREN bit is ignored

Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored

Brown-out Reset enabled according to SBOREN

Brown-out Reset disabled

Bit 5 – LPBORENꢀLow-Power BOR Enable bit

Value

Description

1

0

Low-Power Brown-out Reset is disabled

Low-Power Brown-out Reset is enabled

DS40002002B-page 30

Datasheet

PIC16(L)F18425/45

Device Configuration

Bits 2:1 – PWRTS[1:0]ꢀPower-up Timer Selection bits

Value

11

10

01

00

Description

PWRT disabled

PWRT set at 64 ms

PWRT set at 16 ms

PWRT set at 1 ms

Bit 0 – MCLREꢀ Master Clear (MCLR) Enable bit

Value

Condition

If LVP = 1

If LVP = 0

Description

RE3 pin function is MCLR (it will reset the device when driven low)

MCLR pin is MCLR (it will reset the device when driven low)

MCLR pin function is port defined function

1

0

Note:ꢀ

1. The DEBUG bit in the Configuration Word 2 is managed automatically by device development tools including

debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.

2. See V_BORparameter in the “Electrical Specifications” chapter for specific trip point voltages.

Related Links

40.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset

Specifications

DS40002002B-page 31

Datasheet

PIC16(L)F18425/45

Device Configuration

4.7.3

CONFIG3

Name:ꢀ

Offset:ꢀ

CONFIG3

0x8009

Configuration Word 3

Windowed Watchdog Timer

Bit

15

7

14

6

13

12

11

10

9

8

WDTCCS[2:0]

WDTCWS[2:0]

Access

Reset

R/P

1

R/P

1

R/P

1

R/P

1

R/P

1

R/P

1

Bit

5

4

3

2

1

0

WDTE[1:0]

WDTCPS[4:0]

Access

Reset

U

1

R/P

1

R/P

1

R/P

1

R/P

1

R/P

1

R/P

1

R/P

1

Bits 13:11 – WDTCCS[2:0]ꢀWDT Input Clock Selector bits

Value

111

110 to

011

Description

Software Control

Reserved

010

32 kHz SOSC

001

000

WDT reference clock is the 31.25 kHz HFINTOSC (MFINTOSC) output

WDT reference clock is the 31.0 kHz LFINTOSC

Bits 10:8 – WDTCWS[2:0]ꢀWDT Window Select bits

WDTCON1 [WINDOW] at POR

Window delay Window

Software control Keyed access

WDTCWS

of WINDOW?

required?

Value

Percent of time opening Percent

of time

111

110

101

100

011

010

001

000

111

110

101

100

011

010

001

000

n/a

25

100

75

Yes

No

37.5

50

62.5

50

No

Yes

62.5

75

37.5

25

87.5

12.5

Bits 6:5 – WDTE[1:0]ꢀWDT Operating Mode bits

Value

11

Description

WDT enabled regardless of Sleep; SEN is ignored

10

01

00

WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit is ignored

WDT enabled/disabled by SEN bit

WDT disabled, SEN bit is ignored

DS40002002B-page 32

Datasheet

PIC16(L)F18425/45

Device Configuration

Bits 4:0 – WDTCPS[4:0]ꢀWDT Period Select bits

WDTCON0[WDTPS] at POR

WDTCPS

Software Control of WDTPS?

Typical Time Out

(F_IN= 31 kHz)

Value

Divider Ratio

11111

11110

01011

11110

1:65536

1:32

2¹⁶

2s

Yes

No

2⁵

1 ms

...

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

1:8388608

1:4194304

1:2097152

1:1048576

1:524288

1:262144

1:131072

1:65536

1:32768

1:16384

1:8192

2²³

2²²

2²¹

2²⁰

2¹⁹

2¹⁸

2¹⁷

2¹⁶

2¹⁵

2¹⁴

2¹³

2¹²

2¹¹

2¹⁰

2⁹

256s

128s

64s

32s

16s

8s

4s

2s

1s

512 ms

256 ms

128 ms

64 ms

32 ms

16 ms

8 ms

4 ms

2 ms

1 ms

No

1:4096

1:2048

1:1024

1:512

1:256

2⁸

1:128

2⁷

1:64

2⁶

1:32

2⁵

DS40002002B-page 33

Datasheet

PIC16(L)F18425/45

Device Configuration

4.7.4

CONFIG4

Name:ꢀ

Offset:ꢀ

CONFIG4

0x800A

Configuration Word 4

Memory Write Protection

Bit

15

14

6

13

LVP

R/P

1

12

11

WRTSAF

R/P

10

WRTD

R/P

1

9

WRTC

R/P

1

8

WRTB

R/P

1

Access

Reset

U

1

Bit

7

WRTAPP

R/P

5

4

SAFEN

R/P

3

BBEN

R/P

1

2

1

0

BBSIZE[2:0]

Access

Reset

U

1

U

1

R/P

1

R/P

1

R/P

1

Bit 13 – LVPꢀLow-Voltage Programming Enable bit

The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule

is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating

LVP mode from the Configuration state.

The preconditioned (erased) state for this bit is critical.

Value

Description

1

Low-voltage programming enabled. MCLR/V_PPpin function is MCLR. MCLRE Configuration bit is

ignored.

0

HV on MCLR/V_PPmust be used for programming

Bit 11 – WRTSAFꢀ Storage Area Flash Write Protection bit⁽¹⁾

Value

Description

1

0

SAF NOT write-protected

SAF write-protected

Bit 10 – WRTDꢀ Data EEPROM Write Protection bit⁽¹⁾

Value

Description

1

0

Data EEPROM NOT write-protected

Data EEPROM write-protected

Bit 9 – WRTCꢀ Configuration Register Write Protection bit⁽¹⁾

Value

Description

1

0

Configuration Registers NOT write-protected

Configuration Registers write-protected

Bit 8 – WRTBꢀ Boot Block Write Protection bit⁽¹⁾

Value

Description

1

0

Boot Block NOT write-protected

Boot Block write-protected

Bit 7 – WRTAPPꢀ Application Block Write Protection bit⁽¹⁾

Value

Description

1

0

Application Block NOT write-protected

Application Block write-protected

Bit 4 – SAFENꢀ SAF Enable bit⁽¹⁾

Value

Description

1

SAF disabled

DS40002002B-page 34

Datasheet

PIC16(L)F18425/45

Device Configuration

Value

Description

0

SAF enabled

Bit 3 – BBENꢀ Boot Block Enable bit⁽¹⁾

Value

Description

1

0

Boot Block disabled

Boot Block enabled

Bits 2:0 – BBSIZE[2:0]ꢀ Boot Block Size Selection bits

BBSIZE is used only when BBEN = 0

BBSIZE bits can only be written while BBEN = 1; after BBEN = 0, BBSIZ is write-protected.

Table 4-1.ꢀBoot Block Size Bits

Actual Boot Block Size User

Program Memory Size (words)

Last Boot Block

Memory Access

BBEN

BBSIZE

PIC16(L)F18425/45

1

0

xxx

111

0

—

512

01FFh

03FFh

07FFh

0FFFh

110

1024

2048

4096

101

100-000

Note:ꢀ The maximum boot block size is half the user program memory size. All selections higher than the

maximum are set to half size. For example, all BBSIZE = 000 - 100produce a boot block size of 4 kW on a 8 kW

device.

Note:ꢀ

1. Bits are implemented as sticky bits. Once protection is enabled, it can only be reset through a Bulk Erase.

DS40002002B-page 35

Datasheet

PIC16(L)F18425/45

Device Configuration

4.7.5

CONFIG5

Name:ꢀ

Offset:ꢀ

CONFIG5

0x800B

Configuration Word 5

Code Protection

Bit

15

7

14

13

12

11

10

9

8

Access

Reset

U

1

U

1

U

1

U

1

U

1

U

1

Bit

6

5

4

3

2

1

0

CP

R/P

1

Access

Reset

U

1

U

1

U

1

U

1

U

1

U

1

U

1

Bit 0 – CPꢀProgram Flash Memory Code Protection bit

Value

Description

1

0

Program Flash Memory code protection disabled

Program Flash Memory code protection enabled

4.8

Register Summary - Device and Revision

Offset

Name

Bit Pos.

7:0

13:8

7:0

MJRREV[1:0]

MNRREV[5:0]

0x8005

0x8006

REVISION ID

1

0

MJRREV[5:2]

DEV[11:8]

DEV[7:0]

DEVICE ID

13:8

1

4.9

Register Definitions: Device and Revision

DS40002002B-page 36

Datasheet

PIC16(L)F18425/45

Device Configuration

4.9.1

REVISION ID

Name:ꢀ

Offset:ꢀ

REVISION ID

0x8005

Revision ID Register

15

Bit

14

13

1

12

0

11

R

10

R

9

8

MJRREV[5:2]

Access

Reset

R

1

R

0

R

Bit

7

6

5

4

3

2

1

0

MJRREV[1:0]

R

MNRREV[5:0]

Access

Reset

R

Bit 13 – 1ꢀRead as ‘1’

These bits are fixed with value ‘1’ for all devices in this family.

Bit 12 – 0ꢀRead as ‘0’

These bits are fixed with value ‘0’ for all devices in this family.

Bits 11:6 – MJRREV[5:0]ꢀMajor Revision ID bits

These bits are used to identify a major revision.

Bits 5:0 – MNRREV[5:0]ꢀMinor Revision ID bits

These bits are used to identify a minor revision.

DS40002002B-page 37

Datasheet

PIC16(L)F18425/45

Device Configuration

4.9.2

DEVICE ID

Name:ꢀ

Offset:ꢀ

DEVICE ID

0x8006

Device ID Register

15

Bit

14

13

1

12

1

11

R

10

R

9

8

DEV[11:8]

Access

Reset

R

Bit

7

6

5

4

3

2

1

0

DEV[7:0]

Access

Reset

R

Bit 13 – 1

These bit must be ‘1’ to be distinguishable from the previous Device ID scheme

Bit 12 – 1

These bit must be ‘1’ to be distinguishable from the previous Device ID scheme

Bits 11:0 – DEV[11:0]

Device ID bits

Device

Device ID

30CCh

30CDh

30D0h

PIC16F18425

PIC16LF18425

PIC16F18445

PIC16LF18445

30D1h

DS40002002B-page 38

Datasheet

PIC16(L)F18425/45

Memory Organization

5.

Memory Organization

These devices contain the following types of memory:

•

Program Memory

– Configuration Words

– Device ID

– User ID

– Program Flash Memory

– Device Information Area (DIA)

– Device Configuration Information (DCI)

– Revision ID

•

Data Memory

– Core Registers

– Special Function Registers

– General Purpose RAM

– Common RAM

Data EEPROM

The following features are associated with access and control of program memory and data memory:

•

PCL and PCLATH

Stack

Indirect Addressing

NVMREG access

5.1

Program Memory Organization

The enhanced mid-range core has a 15-bit Program Counter capable of addressing 32K x 14 program memory

space. The table below shows the memory sizes implemented. Accessing a location above these boundaries will

cause a wrap-around within the implemented memory space.

The Reset vector is at 0000h and the interrupt vector is at 0004h. Refer to the “Interrupt Controller” chapter for more

details.

Table 5-1.ꢀDevice Sizes And Addresses

Device

Program Memory Size (Words)

Last Program Memory Address

PIC16(L)F18425

PIC16(L)F18445

8192

0x1FFF

DS40002002B-page 39

Datasheet

PIC16(L)F18425/45

Memory Organization

Figure 5-1.ꢀProgram Memory and Stack

Rev. 10-000040J

3/3/2017

PC[14:0]

CALL, CALLW

RETURN, RETLW

15

Interrupt, RETFIE

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

0000h

Interrupt Vector

0004h

0005h

07FFh

0800h

On-chip

Program

Memory

0FFFh

1000h

17FFh

1800h

Page 0

1FFFh

2000h

3FFFh

4000h

Unimplemented

7FFFh

Related Links

4.7.5 CONFIG5

5.2.5 Memory Violation

5.1.1

Reading Program Memory as Data

There are three methods of accessing constants in program memory. The first method is to use tables of RETLW

instructions. The second method is to set an FSR to point to the program memory. The third method is to use the

NVMREG interface to access the program memory.

Related Links

6.4 NVMREG Access

5.1.1.1 RETLW Instruction

The RETLWinstruction can be used to provide access to tables of constants. The recommended way to create such a

table is shown in the following example.

DS40002002B-page 40

Datasheet

PIC16(L)F18425/45

Memory Organization

Example 5-1.ꢀAccessing table of constants using RETLW instruction

constants

BRW

;Add Index in W to

;program counter to

;select data

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

;Index0 data

;Index1 data

my_function

;… LOTS OF CODE…

MOVLW

DATA_INDEX

call constants

;… THE CONSTANT IS IN W

The BRWinstruction makes this type of table very simple to implement.

5.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by setting bit 7 of an FSRxH register and reading the matching

INDFx register. The MOVIWinstruction will place the lower eight bits of the addressed word in the W register. Writes to

the program memory cannot be performed via the INDFx registers. Instructions that read the program memory via the

FSR require one extra instruction cycle to complete. The following example demonstrates reading the program

memory via an FSR.

The HIGH directive will set bit 7 if a label points to a location in the program memory. This applies to the assembly

code shown below.

Example 5-2.ꢀRead of Program memory using FSR register

constants

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

;Index0 data

;Index1 data

my_function

;… LOTS OF CODE…

MOVLW

MOVWF

MOVLW

MOVWF

MOVIW

LOW constants

FSR1L

HIGH constants

FSR1H

2[FSR1]

;DATA2 IS IN W

5.2

Memory Access Partition (MAP)

User Flash is partitioned into:

•

Application Block

Boot Block

Storage Area Flash (SAF) Block

The user can allocate the memory usage by setting the BBEN bit, selecting the size of the partition defined by

BBSIZE bits and enabling the Storage Area Flash by the SAFEN bit of the Configuration Word 4. Refer to the

following links for the different user Flash memory partitions.

Related Links

4.7.4 CONFIG4

5.2.1

Application Block

Default settings of the Configuration bits (BBEN = 1and SAFEN = 1) assign all memory in the user Flash area to the

application block.

DS40002002B-page 41

Datasheet

PIC16(L)F18425/45

Memory Organization

5.2.2

5.2.3

Boot Block

If BBEN = 1, the boot block is enabled and a specific address range is allotted as the boot block based on the value

of the BBSIZE bits and the sizes provided in Configuration Word 4.

Related Links

4.7.4 CONFIG4

Storage Area Flash

Storage Area Flash (SAF) is enabled by clearing the SAFEN bit of the Configuration Word 4. If enabled, the SAF

block is placed at the end of memory and spans 128 words. If the Storage Area Flash (SAF) is enabled, the SAF area

is not available for program execution.

Related Links

4.7.4 CONFIG4

5.2.4

Memory Write Protection

All the memory blocks have corresponding write protection fuses WRTAPP, WRTB and WRTC bits in the

Configuration Word 4. If write-protected locations are written from NVMCON registers, the memory is not changed

and the WRERR bit defined in NVMCON1 register is set as explained in the “WRERR Bit” section.

Related Links

4.7.4 CONFIG4

6.6.3 NVMCON1

6.4.9 WRERR Bit

5.2.5

Memory Violation

A Memory Execution Violation Reset occurs while executing an instruction that has been fetched from outside a valid

execution area, clearing the MEMV bit. Refer to the “Memory Execution Violation” section for the available valid

program execution areas and the PCON1 register definition for MEMV bit conditions.

Table 5-2.ꢀMemory Access Partition

Partition

BBEN = 1 SAFEN BBEN = 1 SAFEN BBEN = 0 SAFEN BBEN = 0 SAFEN

REG

Address

= 1

= 0

= 1

= 0

00 0000h ... Last

Block Memory

Address

BOOT BLOCK⁽⁴⁾

APPLICATION

BLOCK⁽⁴⁾

Last Boot Block

Memory Address

+ 1⁽¹⁾... Last

Program Memory

Address - 80h

APPLICATION

BLOCK⁽⁴⁾

APPLICATION

BLOCK⁽⁴⁾

PFM

APPLICATION

BLOCK⁽⁴⁾

Last Program

Memory Address -

7Fh⁽²⁾... Last

SAF⁽⁴⁾

Program Memory

Address

Config Memory

Address⁽³⁾

CONFIG

DS40002002B-page 42

Datasheet

PIC16(L)F18425/45

Memory Organization

Note:ꢀ

1. Last Boot Block Memory Address is based on BBSIZE given in “Configuration Word 4”.

2. Last Program Memory Address is the Flash size given in the “Program Memory Organization”.

3. Config Memory Address are the address locations of the Configuration Words given in the “NVMREG Access

to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and Configuration

Words” section.

4. Each memory block has a corresponding write protection fuse defined by the WRTAPP, WRTB and WRTC bits

in the “Configuration Word 4”.

Related Links

10.11 Memory Execution Violation

10.14.3 PCON1

4.7.4 CONFIG4

5.1 Program Memory Organization

6.4.7 NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and

Configuration Words

5.3

Data Memory Organization

The data memory is partitioned into up to 64 memory banks with 128 bytes in each bank. Each bank consists of:

•

12 core registers

Up to 20 Special Function Registers (SFR)

Up to 80 bytes of General Purpose RAM (GPR)

16 bytes of common RAM

DS40002002B-page 43

Datasheet

PIC16(L)F18425/45

Memory Organization

Figure 5-2.ꢀBanked Memory Partition

Rev. 10-000 041C

11/8/201 7

7-bit Bank Offset

Typical Memory Bank

00h

Core Registers

(12 bytes)

0Bh

0Ch

Special Function Registers

(up to 20 bytes maximum)

1Fh

20h

Special Function Registers

or

General Purpose RAM

(80 bytes maximum)

6Fh

70h

Common RAM

(16 bytes)

7Fh

5.3.1

Bank Selection

The active bank is selected by writing the bank number into the Bank Select Register (BSR). All data memory can be

accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers

(FSR). Data memory uses a 13-bit address. The upper six bits of the address define the Bank address and the lower

seven bits select the registers/RAM in that bank.

Related Links

5.6 Indirect Addressing

5.8.7 BSR

5.3.2

Core Registers

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12

addresses of every data memory bank (addresses x00h/x80h through x0Bh/x8Bh). These registers are listed below.

Table 5-3.ꢀCore Registers

Addresses in BANKx

x00h or x80h

Core Registers

INDF0

x01h or x81h

INDF1

DS40002002B-page 44

Datasheet

PIC16(L)F18425/45

Memory Organization

...........continued

Addresses in BANKx

x02h or x82h

x03h or x83h

x04h or x84h

x05h or x85h

x06h or x86h

x07h or x87h

x08h or x88h

x09h or x89h

x0Ah or x8Ah

x0Bh or x8Bh

Core Registers

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

5.3.2.1 STATUS Register

The STATUS register contains:

•

the arithmetic status of the ALU

the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the

destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits

are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the

result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUSwill clear bits [4:3] and [1:0], and set the Z bit. This leaves the STATUS register as

‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPFand MOVWFinstructions are used to alter the STATUS

register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits,

refer to the “Instruction Set Summary” section.

Important:ꢀ The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction.

Related Links

5.8.4 STATUS

5.3.3

5.3.4

Special Function Register

The Special Function Registers (SFR) are registers used by the application to control the desired operation of

peripheral functions in the device. The SFRs occupy the first 20 bytes of the data banks 0-59 and the first 100 bytes

of the data banks 60-63, after the core registers.

The SFRs associated with the operation of the peripherals are described in the appropriate peripheral chapter of this

data sheet.

General Purpose RAM

There are up to 80 bytes of GPR in each data memory bank. The general purpose RAM can be accessed in a non-

banked method via the FSRs. This can simplify access to large memory structures.

Refer to section 5.6.2 Linear Data Memory for details about details about linear memory accessing.

DS40002002B-page 45

Datasheet

PIC16(L)F18425/45

Memory Organization

5.3.5

Common RAM

There are 16 bytes of common RAM accessible from all banks.

5.4

PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and

writable register. The high byte (PC[14:8]) is not directly readable or writable and comes from PCLATH. On any Reset

the PC is cleared. The Figure 5-3 shows the five situations for the loading of the PC.

Figure 5-3.ꢀLoading of PC in Different Situations

Rev. 10-000042A

7/30/2013

PCH

7

14

6

PCL

0

Instruction

with PCL as

Destination

PC

8

0

PCLATH

ALU result

PCH

14

6

PCL

GOTO,

CALL

PC

4

11

OPCODE [10:0]

PCLATH

PCH

7

14

6

PCL

0

PC

CALLW

8

PCLATH

W

14

PCL

0

PCH

PC

BRW

BRA

15

PC + W

15

PC + OPCODE [8:0]

5.4.1

5.4.2

Modifying PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter

PC[14:8] bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the

Program Counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower

eight bits are written to the PCL register, all 15 bits of the Program Counter will change to the values contained in the

PCLATH register and those being written to the PCL register.

Computed GOTO

A computed GOTOis accomplished by adding an offset to the Program Counter (ADDWF PCL). When performing a

table read using a computed GOTOmethod, care should be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556).

DS40002002B-page 46

Datasheet

PIC16(L)F18425/45

Memory Organization

5.4.3

Computed Function Calls

A computed function CALLallows programs to maintain tables of functions and provide another way to execute state

machines or look-up tables. When performing a table read using a computed function CALL, care should be

exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the CALLinstruction, the PCH[2:0] and PCL registers are loaded with the operand of the CALLinstruction.

PCH[6:3] is loaded with PCLATH[6:3].

The CALLWinstruction enables computed calls by combining PCLATH and W to form the destination address. A

computed CALLWis accomplished by loading the W register with the desired address and executing CALLW. The PCL

register is loaded with the value of W and PCH is loaded with PCLATH.

5.4.4

Branching

The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page

boundaries. There are two forms of branching, BRWand BRA. The PC will have incremented to fetch the next

instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.

If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded

with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 + the signed value of the operand of the BRAinstruction.

5.5

Stack

All devices have a 16-level by 15-bit wide hardware stack. The stack space is not part of either program or data

space. The PC is PUSHed onto the stack when CALLor CALLWinstructions are executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN, RETLWor a RETFIEinstruction execution. PCLATH is not

affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN Configuration bit is programmed to ‘0’. This means that after

the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first

PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be

set on an Overflow/Underflow, regardless of whether the Reset is enabled.

If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be Reset if the stack is PUSHed

beyond the sixteenth level or POPed beyond the fist level, setting the appropriate bits (STKOVF or STKUNF,

respectively) in the PCON register.

Important:ꢀ There are no instructions/mnemonics called PUSH or POP. These are actions that occur from

the execution of the CALL, CALLW, RETURN, RETLWand RETFIEinstructions or the vectoring to an

interrupt address.

5.5.1

Accessing the Stack

The stack is accessible through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack

Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into

TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will

position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and

underflow.

Important:ꢀ Care should be taken when modifying the STKPTR while interrupts are enabled.

DS40002002B-page 47

Datasheet

PIC16(L)F18425/45

Memory Organization

During normal program operation, CALL, CALLWand interrupts will increment STKPTR while RETLW, RETURN, and

RETFIEwill decrement STKPTR. STKPTR can be monitored to obtain to value of stack memory left at any given

time. The STKPTR always points at the currently used place on the stack. Therefore, a CALLor CALLWwill increment

the STKPTR and then write the PC, and a return will unload the PC value from the stack and then decrement the

STKPTR.

Reference the following figures for examples of accessing the stack.

Figure 5-4.ꢀAccessing the Stack Example 1

Rev. 10-000043A

7/30/2013

Stack Reset Disabled

(STVREN = 0)

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x1F

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The

empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL register will return ‘0’. If the

Stack Overflow/Underflow Reset is

disabled, the TOSH/TOSL register will

return the contents of stack address

0x0F.

Stack Reset Enabled

STKPTR = 0x1F

TOSH:TOSL

0x0000

(STVREN = 1)

DS40002002B-page 48

Datasheet

PIC16(L)F18425/45

Memory Organization

Figure 5-5.ꢀAccessing the Stack Example 2

Rev. 10-000043B

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

This figure shows the stack configuration

after the first CALL or a single interrupt.

If a RETURNinstruction is executed, the

return address will be placed in the

Program Counter and the Stack Pointer

decremented to the empty state (0x1F).

STKPTR = 0x00

TOSH:TOSL

Return Address

Figure 5-6.ꢀAccessing the Stack Example 3

Rev. 10-000043C

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

After seven CALLs or six CALLs and an

interrupt, the stack looks like the figure on

the left. A series of RETURNinstructions will

repeatedly place the return addresses into

the Program Counter and pop the stack.

STKPTR = 0x06

TOSH:TOSL

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

DS40002002B-page 49

Datasheet

PIC16(L)F18425/45

Memory Organization

Figure 5-7.ꢀAccessing the Stack Example 4

Rev. 10-000043D

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address

When the stack is full, the next CALLor

an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00 so

the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

STKPTR = 0x10

TOSH:TOSL

0x00

Related Links

5.8.11 TOS

5.6

Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the

register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two

INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn

register value is created by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are

divided into three memory regions:

•

Traditional/Banked Data Memory

Linear Data Memory

Program Flash Memory

Data EEPROM

DS40002002B-page 50

Datasheet

PIC16(L)F18425/45

Memory Organization

Figure 5-8.ꢀIndirect Addressing PIC16(L)F18425/45

Rev. 10-000044F

1/13/2017

0x0000

Traditional

Data Memory

0x1FFF

0x2000

Linear

Data Memory

0X2FEF

0X2FF0

Reserved

0x7FFF

0x8000

FSR

Address

Range

PC value = 0x000

Program

Flash Memory

0x87FF

PC value = 0x7FF

Related Links

5.8.5 FSR0

5.6.1

Traditional/Banked Data Memory

The traditional or banked data memory is a region from FSR address 0x000 to FSR address 0x1FFF. The addresses

correspond to the absolute addresses of all SFR, GPR and common registers.

DS40002002B-page 51

Datasheet

PIC16(L)F18425/45

Memory Organization

Figure 5-9.ꢀTraditional/Banked Data Memory Map

Rev. 10-000056B

12/14/2016

Direct Addressing

Indirect Addressing

From Opcode

BSR

5

0

6

0

7

FSRxH

0

7

FSRxL

0

0 0 0

Bank Select Location Select

000000 000001 000010

Bank Select

111111

Location Select

0x00

0x7F

Bank 63

Bank 0 Bank 1 Bank 2

5.6.2

Linear Data Memory

The linear data memory is the region from FSR address 0x2000 to FSR address 0x2FEF. This region is a virtual

region that points back to the 80-byte blocks of GPR memory in all the banks. Refer to the Figure 5-10 for the Linear

Data Memory Map.

Figure 5-10.ꢀLinear Data Memory Map

Rev. 10-000057B

8/24/2016

7

FSRnH

0

7

FSRnL

0

Location Select

0x2000

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Bank 2

0x16F

0x1920

Bank 50

0x196F

0x2FEF

Important:ꢀ The address range 0x2000 to 0x2FEF represents the complete addressable Linear Data

Memory for PIC devices (up to Bank 50). The actual implemented Linear Data Memory will differ from one

device to the other in a family. Refer to General Purpose RAM Distribution for the memory limits of

PIC16(L)F18425/45 devices.

DS40002002B-page 52

Datasheet

PIC16(L)F18425/45

Memory Organization

Table 5-4.ꢀGeneral Purpose RAM Distribution

Bank #

{bank:offset}

0x020-0x06F

0x0A0-0x0EF

0x120-0x16F

0x1A0-0x1EF

0x220-0x26F

0x2A0-0x2EF

0x320-0x36F

0x3A0-0x3EF

0x420-0x46F

0x4A0-0x4EF

0x520-0x56F

0x5A0-0x5EF

0x620-0x64F

0x620-0x66F

Linear address

0x2000-0x204F

0x2050-0x209F

0x20A0-0x20EF

0x20F0-0x213F

0x2140-0x218F

0x2190-0x21DF

0x21E0-0x222F

0x2230-0x227F

0x2280-0x22CF

0x22D0-0x231F

0x2320-0x236F

0x2370-0x23BF

0x23C0-0x23EF

0x23C0-0x240F

PIC16(L)F18425

PIC16(L)F18445

0

1

80

48

80

2

3

4

5

6

7

8

9

10

11

12

80

13

14

15

16

17

18

19

20

21

22

23

24

25

0x6A0-0x6EF

0x720-0x76F

0x7A0-0x7EF

0x820-0x86F

0x8A0-0x8EF

0x920-0x96F

0x9A0-0x9EF

0xA20-0xA6F

0xAA0-0xAEF

0xB20-0xB6F

0xBA0-0xBEF

0xC20-0xC6F

0xCA0-0xCBF

0x2410-0x245F

0x2460-0x24AF

0x24B0-0x24FF

0x2500-0x254F

0x2550-0x259F

0x25A0-0x25EF

0x25F0-0x263F

0x2640-0x268F

0x2690-0x26DF

0x26E0-0x272F

0x2730-0x277F

0x2780-0x27CF

0x27D0-0x27EF

80

32

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80

bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.

5.6.3

Data EEPROM Memory

The EEPROM memory can be read or written through the NVMCON register interface (6.2 Data EEPROM).

However, to make access to the EEPROM easier, read-only access to the EEPROM contents are also available

through indirect addressing via an FSR. When the MSP of the FSR (ex: FSRxH) is set to 0x70, the lower 8-bit

address value (in FSRxL) determines the EEPROM location that may be read via the INDF register). In other words,

the EEPROM address range 0x00-0xFF is mapped into the FSR address space between 0x7000 and 0x70FF.

DS40002002B-page 53

Datasheet

PIC16(L)F18425/45

Memory Organization

Writing to the EEPROM cannot be accomplished via the FSR/INDF interface. Reads from the EEPROM through the

FSR/INDF interface will require one additional instruction cycle to complete.

5.6.4

Program Flash Memory

To make constant data access easier, the entire Program Flash Memory is mapped to the upper half of the FSR

address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be

accessed through INDF. Only the lower eight bits of each memory location are accessible via INDF. Writing to the

Program Flash Memory cannot be accomplished via the FSR/INDF interface. All instructions that access Program

Flash Memory via the FSR/INDF interface will require one additional instruction cycle to complete.

Figure 5-11.ꢀProgram Flash Memory Map

Rev. 10-000058A

7/31/2013

7

1

FSRnH

0

7

FSRnL

0

Location Select

0x8000

0x0000

Program

Flash

Memory

(low 8 bits)

0x7FFF

0xFFFF

5.7

Register Summary - Memory and Status

Offset

Name

Bit Pos.

0x00

0x01

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF[7:0]

PCL[7:0]

0x02

0x03

STATUS

TO

PD

Z

DC

C

0x04

FSRL[7:0]

FSRH[7:0]

FSRL[7:0]

FSRH[7:0]

FSR0

FSR1

0x05

0x06

0x07

0x08

BSR

BSR[5:0]

0x09

WREG

WREG[7:0]

0x0A

0x0B

0x0C

...

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x0FEC

0x0FED

0x0FEE

0x0FEF

STKPTR

TOS

7:0

STKPTR[4:0]

TOSL[7:0]

TOSH[7:0]

15:8

5.8

Register Definitions: Memory and Status

DS40002002B-page 54

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.1

INDF0

Name:ꢀ

Offset:ꢀ

INDF0

0x00 + n*0x80 [n=0..63]

Indirect Data Register. This is a virtual register. The GPR/SFR register addressed by the FSR0 register is the target

for all operations involving the INDF0 register.

Bit

7

6

5

4

3

2

1

0

INDF0[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – INDF0[7:0]

Indirect data pointed to by the FSR0 register

Related Links

5.3.2 Core Registers

DS40002002B-page 55

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.2

INDF1

Name:ꢀ

Offset:ꢀ

INDF1

0x01 + n*0x80 [n=0..63]

Indirect Data Register. This is a virtual register. The GPR/SFR register addressed by the FSR1 register is the target

for all operations involving the INDF1 register.

Bit

7

6

5

4

3

2

1

0

INDF1[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – INDF1[7:0]

Indirect data pointed to by the FSR1 register

Related Links

5.3.2 Core Registers

DS40002002B-page 56

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.3

PCL

Name:ꢀ

Offset:ꢀ

PCL

0x02 + n*0x80 [n=0..63]

Low byte of the Program Counter

Bit

7

6

5

4

3

2

1

0

PCL[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – PCL[7:0]

Provides direct read and write access to the Program Counter

DS40002002B-page 57

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.4

STATUS

Name:ꢀ

Offset:ꢀ

STATUS

0x03 + n*0x80 [n=0..63]

Status Register

7

Bit

6

5

4

TO

RO

1

3

PD

RO

1

2

Z

1

DC

R/W

0

C

Access

Reset

R/W

0

R/W

0

Bit 4 – TOꢀTime-Out bit

Reset States: POR/BOR = 1

All Other Resets = q

Description

Value

1

Set at power-up or by execution of CLRWDTor SLEEPinstruction

0

A WDT time-out occurred

Bit 3 – PDꢀPower-Down bit

Reset States: POR/BOR = 1

All Other Resets = q

Description

Value

1

Set at power-up or by execution of CLRWDTinstruction

0

Cleared by execution of the SLEEPinstruction

Bit 2 – ZꢀZero bit

Reset States: POR/BOR = 0

All Other Resets = u

Description

Value

1

0

The result of an arithmetic or logic operation is zero

The result of an arithmetic or logic operation is not zero

Bit 1 – DCꢀ Digit Carry/Borrow bit⁽¹⁾

ADDWF, ADDLW, SUBLW, SUBWFinstructions

Reset States: POR/BOR = 0

All Other Resets = u

Value

Description

1

0

A carry-out from the 4th low-order bit of the result occurred

No carry-out from the 4th low-order bit of the result

Bit 0 – Cꢀ Carry/Borrow bit⁽¹⁾

ADDWF, ADDLW, SUBLW, SUBWFinstructions

Reset States: POR/BOR = 0

All Other Resets = u

Value

Description

1

0

A carry-out from the Most Significant bit of the result occurred

No carry-out from the Most Significant bit of the result occurred

Note:ꢀ

1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second

operand. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the

Source register.

Related Links

5.3.2 Core Registers

DS40002002B-page 58

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.5

FSR0

Name:ꢀ

Offset:ꢀ

FSR0

0x04 + n*0x80 [n=0..63]

Indirect Address Register

The FSR0 value is the address of the data to which the INDF0 register points.

Bit

15

14

13

12

11

10

9

8

FSR0[15:8]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

FSR0[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 15:0 – FSR0[15:0]

Address of INDF0 data

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

FSR0H: Accesses the high byte FSR0[15:8]

FSR0L: Accesses the low byte FSR0[7:0]

Related Links

5.3.2 Core Registers

DS40002002B-page 59

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.6

FSR1

Name:ꢀ

Offset:ꢀ

FSR1

0x06 + n*0x80 [n=0..63]

Indirect Address Register

The FSR1 value is the address of the data to which the INDF1 register points.

Bit

15

14

13

12

11

10

9

8

FSR1[15:8]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

FSR1[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 15:0 – FSR1[15:0]

Address of INDF1 data

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

FSR1H: Accesses the high byte FSR1[15:8]

FSR1L: Accesses the low byte FSR1[7:0]

DS40002002B-page 60

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.7

BSR

Name:ꢀ

Offset:ꢀ

BSR

0x08 + n*0x80 [n=0..63]

Bank Select Register

The BSR indicates the data memory bank by writing the bank number into the register. All data memory can be

accessed directly via instructions, or indirectly via FSRs.

Bit

7

6

5

4

3

2

1

0

BSR[5:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 5:0 – BSR[5:0]

Six Most Significant bits of the data memory address

Related Links

5.3.2 Core Registers

DS40002002B-page 61

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.8

WREG

Name:ꢀ

Offset:ꢀ

WREG

0x09 + n*0x80 [n=0..63]

Working Data Register

Bit

7

6

5

4

3

2

1

0

WREG[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – WREG[7:0]

Related Links

5.3.2 Core Registers

DS40002002B-page 62

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.9

PCLATH

Name:ꢀ

Offset:ꢀ

PCLATH

0x0A + n*0x80 [n=0..63]

Program Counter Latches.

Write Buffer for the upper 7 bits of the Program Counter

Bit

7

6

5

4

3

2

1

0

PCLATH[6:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 6:0 – PCLATH[6:0]ꢀHigh PC Latch Register

Holding register for Program Counter bits [6:0]

Related Links

5.3.2 Core Registers

DS40002002B-page 63

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.10 INTCON

Name:ꢀ

Offset:ꢀ

INTCON

0x0B + n*0x80 [n=0..63]

Interrupt Control Register

Bit

7

6

5

4

3

2

1

0

INTEDG

R/W

1

GIE

PEIE

Access

Reset

R/W

0

R/W

0

Bit 7 – GIEꢀGlobal Interrupt Enable bit

Value

Description

1

0

Enables all active interrupts

Disables all interrupts

Bit 6 – PEIEꢀPeripheral Interrupt Enable bit

Value

Description

1

0

Enables all active peripheral interrupts

Disables all peripheral interrupts

Bit 0 – INTEDGꢀExternal Interrupt Edge Select bit

Value

Description

1

0

Interrupt on rising edge of INT pin

Interrupt on falling edge of INT pin

Important:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its

corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt

flag bits are clear prior to enabling an interrupt. This feature allows for software polling.

Related Links

5.3.2 Core Registers

DS40002002B-page 64

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.11

TOS

Name:ꢀ

Offset:ꢀ

TOS

0xFEE

Top-of-Stack Registers

Contents of the stack pointed to by the STKPTR register. To access the stack, adjust the value of STKPTR, which will

position TOSH:TOSL, then read/write to TOSH:TOSL.

Bit

15

14

13

12

11

10

9

8

TOS[15:8]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

TOS[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 15:0 – TOS[15:0]ꢀTOS Register Value

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

TOSH: Accesses the high byte TOS[15:8]

TOSL: Accesses the low byte TOS[7:0]

Related Links

5.3.2 Core Registers

DS40002002B-page 65

Datasheet

PIC16(L)F18425/45

Memory Organization

5.8.12 STKPTR

Name:ꢀ

Offset:ꢀ

STKPTR

0xFED

Stack Pointer Register

Bit

7

6

5

4

3

2

1

0

STKPTR[4:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – STKPTR[4:0]ꢀStack Pointer Location bits

DS40002002B-page 66

Datasheet

PIC16(L)F18425/45

Memory Organization

5.9

Register Summary: Shadow Registers

Offset

Name

Bit Pos.

0x00

...

Reserved

0x1FE3

0x1FE4

0x1FE5

0x1FE6

0x1FE7

STATUS_SHAD

WREG_SHAD

BSR_SHAD

7:0

TO

PD

Z

DC

C

WREG[7:0]

7:0

BSR[5:0]

PCLATH[6:0]

PCLATH_SHAD

7:0

FSR0_SHAD[7:0]

0x1FE8

0x1FEA

FSR0_SHAD

FSR1_SHAD

15:8

7:0

FSR1_SHAD[7:0]

15:8

5.10

Register Definitions: Shadow Registers

DS40002002B-page 67

Datasheet

PIC16(L)F18425/45

Memory Organization

5.10.1 STATUS_SHAD

Name:ꢀ

Offset:ꢀ

STATUS_SHAD

0x1FE4

Shadow of Status Register

Bit

7

6

5

4

TO

RO

x

3

PD

RO

x

2

Z

1

DC

R/W

x

0

C

Access

Reset

R/W

x

R/W

x

Bit 4 – TOꢀTime-Out bit

Reset States: POR/BOR = x

All Other Resets = u

Description

Value

1

Set at power-up or by execution of CLRWDTor SLEEPinstruction

0

A WDT Time-out occurred

Bit 3 – PDꢀPower-Down bit

Reset States: POR/BOR = x

All Other Resets = u

Description

Value

1

Set at power-up or by execution of CLRWDTinstruction

0

Cleared by execution of the SLEEPinstruction

Bit 2 – ZꢀZero bit

Reset States: POR/BOR = x

All Other Resets = u

Description

Value

1

0

The result of an arithmetic or logic operation is zero

The result of an arithmetic or logic operation is not zero

Bit 1 – DCꢀ Digit Carry/Borrow bit⁽¹⁾

ADDWF, ADDLW, SUBLW, SUBWFinstructions

Reset States: POR/BOR = x

All Other Resets = u

Value

Description

1

0

A carry-out from the 4th low-order bit of the result occurred

No carry-out from the 4th low-order bit of the result

Bit 0 – Cꢀ Carry/Borrow bit⁽¹⁾

ADDWF, ADDLW, SUBLW, SUBWFinstructions

Reset States: POR/BOR = x

All Other Resets = u

Value

Description

1

0

A carry-out from the Most Significant bit of the result occurred

No carry-out from the Most Significant bit of the result occurred

Note:ꢀ

1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second

operand. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the

Source register.

DS40002002B-page 68

Datasheet

PIC16(L)F18425/45

Memory Organization

5.10.2 WREG_SHAD

Name:ꢀ

Offset:ꢀ

WREG_SHAD

0x1FE5

Shadow of Working Data Register

Bit

7

6

5

4

3

2

1

0

WREG[7:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 7:0 – WREG[7:0]

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

DS40002002B-page 69

Datasheet

PIC16(L)F18425/45

Memory Organization

5.10.3 BSR_SHAD

Name:ꢀ

Offset:ꢀ

BSR_SHAD

0x1FE6

Shadow of Bank Select Register

The BSR indicates the data memory bank by writing the bank number into the register. All data memory can be

accessed directly via instructions, or indirectly via FSRs.

Bit

7

6

5

4

3

2

1

0

BSR[5:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 5:0 – BSR[5:0]

Six Most Significant bits of the data memory address

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

DS40002002B-page 70

Datasheet

PIC16(L)F18425/45

Memory Organization

5.10.4 PCLATH_SHAD

Name:ꢀ

Offset:ꢀ

PCLATH_SHAD

0x1FE7

Shadow of Program Counter Latches.

Write Buffer for the upper 7 bits of the Program Counter

Bit

7

6

5

4

3

2

1

0

PCLATH[6:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 6:0 – PCLATH[6:0]ꢀHigh PC Latch Register

Holding register for Program Counter bits [6:0]

Reset States: POR/BOR = xxxxxxx

All Other Resets = uuuuuuu

DS40002002B-page 71

Datasheet

PIC16(L)F18425/45

Memory Organization

5.10.5 FSR_SHAD

Name:ꢀ

Offset:ꢀ

FSRx_SHAD

0x1FE8,0x1FEA

Shadow of Indirect Address Register. The FSRx_SHAD value is the address of the data to which the INDFx register

points.

Bit

15

7

14

6

13

12

11

10

9

8

Access

Reset

Bit

5

4

3

2

1

0

FSRx_SHAD[7:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 7:0 – FSRx_SHAD[7:0]

Address of INDFx data

Reset States: POR/BOR = xxxxxxxxxxxxxxxx

All Other Resets = uuuuuuuuuuuuuuuu

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

FSRx_SHADH: Accesses the high byte FSRx_SHAD[15:8]

FSRx_SHADL: Accesses the low byte FSRx_SHAD[7:0]

5.11

Device Configuration Information

The Device Configuration Information (DCI) is a dedicated region in the program Flash memory mapped from 8200h

to 821Fh. The data stored in the DCI memory is hard-coded into the device during manufacturing. Refer to the table

below for the complete DCI table address and description. The DCI holds information about the device, which is

useful for programming and bootloader applications. These locations are read-only and cannot be erased or

modified.

Table 5-5.ꢀDevice Configuration Information for PIC16(L)F18425/45 Devices

ADDRESS

8200h

Name

ERSIZ

DESCRIPTION

Erase Row Size

PIC16(L)F18425/45

UNITS

Words

Latches

Rows

32

8201h

WLSIZ

URSIZ

EESIZ

PCNT

Number of Write Latches

Number of User Rows

EE Data Memory Size

Pin Count

8202h

256

8203h

256

Bytes

8204h

14, 16, 20

Pins

5.12

Device Information Area

The Device Information Area (DIA) is a dedicated region in the program memory space; it is a new feature in the

PIC16(L)F184XX family of devices. The DIA contains the calibration data for the internal temperature indicator

module, stores the Microchip Unique Identifier words, and the Fixed Voltage Reference voltage readings measured in

mV. The complete DIA table is shown below, followed by a description of each region and its functionality. The data is

mapped from 8100h to 811Fh in the PIC16(L)F184XX family. These locations are read-only and cannot be erased or

modified. The data is programmed into the device during manufacturing.

DS40002002B-page 72

Datasheet

PIC16(L)F18425/45

Memory Organization

Table 5-6.ꢀDevice Information Area

Address Range

Name of Region

MUI0

Standard Device Information

MUI1

MUI2

MUI3

8100h-8108h

MUI4

Microchip Unique Identifier (9 Words)

MUI5

MUI6

MUI7

MUI8

8109h

MUI9

1 Word Reserved

EUI0

EUI1

EUI2

EUI3

810Ah-8111h

Unassigned (8 Words)

Unassigned (1 Word)

EUI4

EUI5

EUI6

EUI7

8112h

8113h

TSLR1

TSLR2

TSLR3

TSHR1

TSHR2

TSHR3

FVRA1X

FVRA2X

FVRA4X⁽¹⁾

FVRC1X

FVRC2X

FVRC4X⁽¹⁾

Temperature indicator ADC reading at 90°C (low range setting)

Unassigned (1 Word)

8114h

8115h

Unassigned (1 Word)

8116h

Temperature indicator ADC reading at 90°C (high range setting)

Unassigned (1 Word)

8117h

8118h

ADC FVR1 Output voltage for 1x setting (in mV)

ADC FVR1 Output Voltage for 2x setting (in mV)

ADC FVR1 Output Voltage for 4x setting (in mV)

Comparator FVR2 Output Voltage for 1x setting (in mV)

Comparator FVR2 Output Voltage for 2x setting (in mV)

Comparator FVR2 Output Voltage for 4x setting (in mV)

Unassigned (2 Words)

8119h

811Ah

811Bh

811Ch

811Dh

811Eh-811Fh

Note:ꢀ

1. Value not present on LF devices.

DS40002002B-page 73

Datasheet

PIC16(L)F18425/45

Memory Organization

5.12.1 Microchip Unique Identifier (MUI)

The PIC16(L)F184XX devices are individually encoded during final manufacturing with a Microchip Unique Identifier

(MUI). The MUI cannot be erased by a Bulk Erase command or any other user-accessible means. This feature allows

for manufacturing traceability of Microchip Technology devices in applications where this is required. It may also be

used by the application manufacturer for a number of functions that require unverified unique identification, such as:

•

Tracking the device

Unique serial number

The MUI consists of nine program words and one reserved program word. When taken together, these fields form a

unique identifier. The MUI is stored in read-only locations, located between 8100h to 8109h in the DIA space. The

above table lists the addresses of the identifier words.

Important:ꢀ For applications that require verified unique identification, contact your Microchip Technology

sales office to create a serialized quick turn programming option.

5.12.2 External Unique Identifier (EUI)

The EUI data is stored at locations 810Ah to 8111h in the program memory region. This region is an optional space

for placing application specific information. The data is coded per customer requirements during manufacturing. The

EUI cannot be erased by a Bulk Erase command.

Important:ꢀ Data is stored in this address range on receiving a request from the customer. The customer

may contact the local sales representative or Field Applications Engineer, and provide them the unique

identifier information that is required to be stored in this region.

5.12.3 Analog-to-Digital Conversion Data of the Temperature Sensor

The purpose of the temperature indicator module is to provide a temperature-dependent voltage that can be

measured by an analog module. The “Temperature Indicator Module” chapter explains the operation of the

Temperature Indicator module and defines terms such as the low range and high range settings of the sensor. The

DIA table contains the internal ADC measurement values of the temperature sensor for low and high range at fixed

points of reference. The values are measured during test and are unique to each device. The right-justified ADC

readings are stored in the DIA memory region. The calibration data can be used to plot the approximate sensor

output voltage, V_TSENSEvs. Temperature curve.

•

TSLR: Address 8112h to 8114h store the measurements for the low range setting of the temperature sensor at

V_DD= 3V.

•

TSHR: Address 8115h to 8117h store the measurements for the high range setting of the temperature sensor at

V_DD= 3V.

The stored measurements are made by the device ADC using the internal V_REF= 2.048V.

5.12.4 Fixed Voltage Reference Data

The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of V_DD, with 1.024V, 2.048V or

4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the

following:

•

ADC input channel

ADC positive reference

Comparator positive input

Digital-to-Analog Converter

For more information on the FVR, refer to the “Fixed Voltage Reference (FVR)” chapter.

The DIA stores measured FVR voltages for this device in mV for the different buffer settings of 1x, 2x or 4x at

program memory locations 8118h to 811Dh.

DS40002002B-page 74

Datasheet

PIC16(L)F18425/45

Memory Organization

•

FVRA1X stores the value of ADC FVR1 Output Voltage for 1x setting (in mV)

FVRA2X stores the value of ADC FVR1 Output Voltage for 2x setting (in mV)

FVRA4X stores the value of ADC FVR1 Output Voltage for 4x setting (in mV)

FVRC1X stores the value of Comparator FVR2 Output Voltage for 1x setting (in mV)

FVRC2X stores the value of Comparator FVR2 Output Voltage for 2x setting (in mV)

FVRC4X stores the value of Comparator FVR2 Output Voltage for 4x setting (in mV)

Related Links

30. FVR - Fixed Voltage Reference

DS40002002B-page 75

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.

NVM - Nonvolatile Memory Control

Nonvolatile Memory (NVM) is separated into two types: Program Flash Memory (PFM) and Data EEPROM Memory.

NVM is accessible by using both the FSR and INDF registers, or through the NVMREG register interface.

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump

rated to operate over the operating voltage range of the device.

NVM can be protected in two ways, by either code protection or write protection.

Code protection (CP bit in the CONFIG5) disables access, reading and writing to both PFM and Data EEPROM

Memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code

protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all nonvolatile

memory, Configuration bits and User IDs.

Write protection prohibits self-write and erase to a portion or all of the NVM, as defined by the WRTSAF, WRTD,

WRTC, WRTB, and WRTAPP bits of CONFIG4. Write protection does not affect a device programmer’s ability to

read, write, or erase the device.

Related Links

4.7.4 CONFIG4

4.7.5 CONFIG5

6.1

Program Flash Memory

Program Flash memory consists of an array of 14-bit words as user memory, with additional words for user ID

information, Configuration words, and interrupt vectors. Program memory provides storage locations for:

•

User program instructions

User defined data

Program memory data can be read and/or written to through:

•

CPU instruction fetch (read-only)

FSR/INDF indirect access (read-only)

NVMREG access

In-Circuit Serial Programming^™(ICSP^™)

Read operations return a single word of memory. When write and erase operations are done on a row basis, the row

size is defined. Program memory will erase to a logic ‘1’ and program to a logic ‘0’.

It is important to understand the program memory structure for erase and programming operations. Program memory

is arranged in rows. A row consists of 32 14-bit program memory words. A row is the minimum size that can be

erased by user software.

All or a portion of a row can be programmed. Data to be written into the program memory row is written to 14-bit wide

data write latches. These latches are not directly accessible, but may be loaded via sequential writes to the

NVMDATH:NVMDATL register pair.

Important:ꢀ To modify only a portion of a previously programmed row, the contents of the entire row must

be read. Then, the new data and retained data can be written into the write latches to reprogram the row of

program memory. However, any unprogrammed locations can be written without first erasing the row. In

this case, it is not necessary to save and rewrite the other previously programmed locations.

Related Links

6.3 FSR and INDF Access

6.4 NVMREG Access

DS40002002B-page 76

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.1.1

Program Memory Voltages

The program memory is readable and writable during normal operation over the full V_DDrange.

6.1.1.1 Programming Externally

The program memory cell and control logic support write and Bulk Erase operations down to the minimum device

operating voltage. Special BOR operation is enabled during Bulk Erase.

Related Links

10.2.4 BOR is Always OFF

6.1.1.2 Self-Programming

The program memory cell and control logic will support write and row erase operations across the entire V_DDrange.

Bulk Erase is not available when self-programming.

6.2

Data EEPROM

Data EEPROM consists of 256 bytes of user data memory. The EEPROM provides storage locations for 8-bit user

defined data.

EEPROM can be read and/or written through:

•

NVMREG access

External device programmer

Additionally, read-only access to the EEPROM contents are also available through indirect addressing via FSR/INDF

registers.

Unlike Program Flash Memory, which must be written to by row, EEPROM can be written to byte by byte.

Related Links

6.3 FSR and INDF Access

6.4 NVMREG Access

6.3

FSR and INDF Access

The FSR and INDF registers allow indirect access to the program memory or EEPROM.

Related Links

5.8.5 FSR0

6.3.1

FSR Read

With the intended address loaded into an FSR register a MOVIWinstruction or read of INDF will read data from the

program memory or EEPROM.

Reading from NVM requires one instruction cycle. The CPU operation is suspended during the read, and resumes

immediately after. Read operations return a single byte of memory.

6.3.2

FSR Write

Writing/erasing the NVM through the FSR registers (ex. MOVWIinstruction) is not supported in the PIC16(L)F184XX

devices.

DS40002002B-page 77

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.4

NVMREG Access

The NVMREG interface allows read/write access to all the locations accessible by FSRs, and also read/write access

to the User ID locations and EEPROM, and read-only access to the device identification, revision, and configuration

data.

Writing or erasing of NVM via the NVMREG interface is prevented when the device is write-protected.

6.4.1

NVMREG Read Operation

To read a NVM location using the NVMREG interface, the user must:

1. Clear the NVMREGS bit of the NVMCON1 register if the user intends to access program memory locations, or

set NMVREGS if the user intends to access User ID, EEPROM, or configuration locations.

2. Write the desired address into the NVMADRH:NVMADRL register pair.

3. Set the RD bit of the NVMCON1 register to initiate the read.

Once the read control bit is set, the CPU operation is suspended during the read, and resumes immediately after.

The data is available in the very next cycle, in the NVMDATH:NVMDATL register pair; therefore, it can be read as two

bytes in the following instructions.

NVMDATH:NVMDATL register pair will hold this value until another read or until it is written to by the user.

Upon completion, the RD bit is cleared by hardware.

Figure 6-1.ꢀFlash Program Memory Read Flowchart

Rev. 10-000046E

5/17/2017

Start

Read Operation

Select Memory:

Program Memory, DIA, DCI,

Config Words, User ID (NVMREGS)

Select

Word Address

(NVMADRH:NVMADRL)

Data read now in

NVMDATH:NVMDATL

End

Read Operation

Example 6-1.ꢀProgram Memory read

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO

data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

*

BANKSEL

MOVLW

MOVWF

MOVLW

NVMADRL

; Select Bank for NVMCON registers

PROG_ADDR_LO

NVMADRL

;

; Store LSB of address

;

PROG_ADDR_HI

DS40002002B-page 78

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

MOVWF

NVMADRH

; Store MSB of address

BCF

BSF

NVMCON1,NVMREGS

NVMCON1,RD

; Do not select Configuration Space

; Initiate read

MOVF

NVMDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

NVMDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

Related Links

6.6.1 NVMADR

6.6.2 NVMDAT

6.6.3 NVMCON1

6.4.2

NVM Unlock Sequence

The unlock sequence is a mechanism that protects the NVM from unintended self-write programming or erasing. The

sequence must be executed and completed without interruption to successfully complete any of the following

operations:

•

Program Flash Memory Row Erase

Load of Program Flash Memory write latches

Write of Program Flash Memory write latches to program memory

Write of Program Flash Memory write latches to User IDs

Write to EEPROM

The unlock sequence consists of the following steps and must be completed in order:

•

Write 0x55to NVMCON2

Write 0xAAto NMVCON2

Set the WR bit of NVMCON1

Once the WR bit is set, the processor will stall internal operations until the operation is complete and then resume

with the next instruction.

Important:ꢀ The two NOPinstructions after setting the WR bit, that were required in previous devices, are

not required for PIC16(L)F184XX devices. See Figure 6-2 for an example of the Unlock sequence.

Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence

and re-enabled after the unlock sequence is completed.

DS40002002B-page 79

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

Figure 6-2.ꢀNVM Unlock Sequence Flowchart

Rev. 10-000047B

8/24/2015

Start

Unlock Sequence

Write 0x55 to

NVMCON2

Write 0xAA to

NVMCON2

Initiate

Write or Erase operation

(WR = 1)

End

Unlock Sequence

Example 6-2.ꢀNVM Unlock Sequence

BCF

INTCON, GIE

; Recommended so sequence is not interrupted

;

BANKSEL NVMCON1

BSF

NVMCON1, WREN

55h

NVMCON2

AAh

NVMCON2

NVMCON1, WR

INTCON, GIE

; Enable write/erase

MOVLW

MOVWF

MOVLW

MOVWF

BSF

; Load 55h

; Step 1: Load 55h into NVMCON2

; Step 2: Load W with AAh

; Step 3: Load AAH into NVMCON2

; Step 4: Set WR bit to begin write/erase

; Re-enable interrupts

BSF

Note:ꢀ

1. Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate

order shown.

2. Opcodes shown are illustrative; any instruction that has the indicated effect may be used.

6.4.3

NVMREG Write to EEPROM

Writing to the EEPROM is accomplished by the following steps:

1. Set the NVMREGS and WREN bits of the NVMCON1 register.

2. Write the desired address (address 0x7000) into the NVMADRH:NVMADRL register pair.

3. Perform the unlock sequence as described in the 6.4.2 NVM Unlock Sequence section.

A single EEPROM byte is written through NVMDATA register. The operation includes an implicit erase cycle for that

byte (it is not necessary to set the FREE bit in NVMCON1 register), and will require multiple instruction cycles to

finish. CPU execution continues in parallel and, when complete, WR bit in NVMCON1 register is cleared by

hardware, NVMIF flag in PIR7 register is set, and an interrupt will occur if NVMIE in PIE7 is also set. Software must

poll the WR bit to determine when writing is complete, or wait for the interrupt to occur. WREN will remain

unchanged. Once the EEPROM write operation begins, clearing the WR bit will have no effect; the operation will run

to completion.

Related Links

DS40002002B-page 80

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.4.2 NVM Unlock Sequence

6.4.4 NVMREG Erase of Program Memory

6.4.4

NVMREG Erase of Program Memory

Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program

memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write to program

memory. To erase a program memory row:

1. Clear the NVMREGS bit of the NVMCON1 register to erase program memory locations, or set the NMVREGS

bit to erase User ID locations.

2. Write the desired address into the NVMADRH:NVMADRL register pair.

3. Set the FREE and WREN bits of the NVMCON1 register.

4. Perform the unlock sequence as described in the “NVM Unlock Sequence” section.

If the program memory address is write-protected, the WR bit will be cleared and the erase operation will not take

place.

While erasing program memory, CPU operation is suspended, and resumes when the operation is complete. Upon

completion, the NVMIF is set, and an interrupt will occur if the NVMIE bit is also set.

Write latch data is not affected by erase operations, and WREN will remain unchanged.

DS40002002B-page 81

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

Figure 6-3.ꢀNVM Erase Flowchart

Rev. 10-000048B

8/24/2015

Start

Erase Operation

Select Memory:

PFM, Config Words, User ID

(NVMREGS)

Select Word Address

(NVMADRH:NVMADRL)

Select Erase Operation

(FREE=1)

Enable Write/Erase Operation

(WREN=1)

Disable Interrupts

(GIE=0)

Unlock Sequence

(See Note 1)

CPU stalls while

Erase operation completes

(2 ms typical)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

Note:ꢀ See previous figure.

DS40002002B-page 82

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

Example 6-3.ꢀErasing One Row of Program Flash Memory

; This sample row erase routine assumes the following:

; 1.A valid address within the erase row is loaded in variables ADDRH:ADDRL

; 2.ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

BCF

NVMADRL

ADDRL,W

NVMADRL

; Load lower 8 bits of erase address boundary

ADDRH,W

NVMADRH

; Load upper 6 bits of erase address boundary

; Choose PFM memory area

; Specify an erase operation

; Enable writes

; Disable interrupts during unlock sequence

NVMCON1,NVMREGS

NVMCON1,FREE

NVMCON1,WREN

INTCON,GIE

BSF

BCF

; ---------------------REQUIRED UNLOCK SEQUENCE:--------------------

MOVLW

MOVWF

MOVLW

MOVWF

BSF

0x55

NVMCON2

0xAA

NVMCON2

NVMCON1,WR

; Load 0x55 to get ready for unlock sequence

; First step is to load 0x55 into NVMCON2

; Second step is to load 0xAA into W

; Third step is to load 0xAA into NVMCON2

; Final step is to set WR bit

; ------------------------------------------------------------------

BSF

BCF

INTCON,GIE

NVMCON1,WREN

; Re-enable interrupts, erase is complete

; Disable writes

Table 6-1.ꢀNVM Organization and Access Information

Master Values

NVMREG Access

FSR Access

FSR

™

Memory

Function

Memory

Type

Program

ICSP

NVMREGS bit

Allowed

Operations

FSR

NVMADR[14:0]

Programming

Access

Counter (PC) Address (NVMCON1)

Address

RESET

VECTOR

0

0x0000

0x8000

0x0001

0x0003

0x0001

0x0003

0x0001

0x0003

0x8001

0x8003

USER

MEMORY

Program

Flash

Memory

READ/WRITE

READ ONLY

INT

VECTOR

0x0004

0x8004

0x0005

0x7FFF⁽¹⁾

0x0005

0x7FFF⁽¹⁾

0x8000

0x0005

0x7FFF⁽¹⁾

0x0000

0x8005

0xFFFF

USER

MEMORY

Program

Flash

Memory

1

USER ID

READ/WRITE

0x8003

0x0003

Reserved

REV ID

—

1

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x0100

0x02FF

0x7000

0x70FF

—

0x8005

0x8006

0x8007

0x8008

0x8009

0x800A

0x800B

0x8100

0x82FF

0xF000

0xF0FF

HC

READ

DEVICE ID

CONFIG1

CONFIG2

CONFIG3

CONFIG4

CONFIG5

NO ACCESS

NO PC

ACCESS

FUSE

READ/WRITE

DIA and DCI

PFM

READ

0x7000

0x70FF

USER

MEMORY

1

EEPROM

READ/WRITE

READ ONLY

DS40002002B-page 83

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

Note:ꢀ

1. The maximum Program Flash Memory address for the PIC16(L)F184XX family is 0x7FFF.

Related Links

5. Memory Organization

6.4.5

NVMREG Write to Program Memory

Program memory is programmed using the following steps:

1. Load the address of the row to be programmed into NVMADRH:NVMADRL.

2. Load each write latch with data.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program

memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at a time. The maximum number of words written at one time is

equal to the number of write latches. See Figure 6-4 for more details.

The write latches are aligned to the Flash row address boundary defined by the upper ten bits of

NVMADRH:NVMADRL, (NVMADRH[6:0]:NVMADRL[7:5]) with the lower five bits of NVMADRL, (NVMADRL[4:0])

determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a

program memory write operation, the data in the write latches is reset to contain 0x7FFF.

The following steps should be completed to load the write latches and program a row of program memory. These

steps are divided into two parts. First, each write latch is loaded with data from the NVMDATH:NVMDATL using the

unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is

cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash

program memory.

Important:ꢀ The special unlock sequence is required to load a write latch with data or initiate a Flash

programming operation. If the unlock sequence is interrupted, writing to the latches or program memory

will not be initiated.

1. Set the WREN bit of the NVMCON1 register.

2. Clear the NVMREGS bit of the NVMCON1 register.

3. Set the LWLO bit of the NVMCON1 register. When the LWLO bit of the NVMCON1 register is ‘1’, the write

sequence will only load the write latches and will not initiate the write to Flash program memory.

4. Load the NVMADRH:NVMADRL register pair with the address of the location to be written.

5. Load the NVMDATH:NVMDATL register pair with the program memory data to be written.

6. Execute the unlock sequence. The write latch is now loaded.

7. Increment the NVMADRH:NVMADRL register pair to point to the next location.

8. Repeat steps 5 through 7 until all but the last write latch has been loaded.

9. Clear the LWLO bit of the NVMCON1 register. When the LWLO bit of the NVMCON1 register is ‘0’, the write

sequence will initiate the write to Flash program memory.

10. Load the NVMDATH:NVMDATL register pair with the program memory data to be written.

11. Execute the unlock sequence. The entire program memory latch content is now written to Flash program

memory.

Important:ꢀ The program memory write latches are reset to the blank state (0x7FFF) at the completion of

every write or erase operation. As a result, it is not necessary to load all the program memory write

latches. Unloaded latches will remain in the blank state.

DS40002002B-page 84

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

An example of the complete write sequence is shown in Writing to Program Flash Memory. The initial address is

loaded into the NVMADRH:NVMADRL register pair; the data is loaded using indirect addressing.

Figure 6-4.ꢀNVMREG Writes to Program Flash Memory With 32 Write Latches

Rev. 10-000004F

8/15/2016

7

6

0

7

5

4

0

7

-

5

0

7

0

-

NVMADRH

NVMADRL

NVMDATH

6

NVMDATL

8

-

r9

r8

r7

r6

r5

r4

r3

r2

r1

r0

c4

c3

c2

c1

c0

14

Program Memory Write Latches

14 14

10

5

14

Write Latch #0 Write Latch #1

00h 01h

Write Latch #30

1Eh

Write Latch #31

1Fh

NVMADRL[4:0]

14

Addr

Row

000h

001h

002h

Addr

0000h

0010h

0020h

0001h

0011h

0021h

001Eh

003Eh

005Eh

001Fh

003Fh

005Fh

NVMREGS=0

End

Addr

Row

Address

Decode

End Addr

NVMADRH[6:0]

NVMADRL[7:5]

Flash Program Memory

Configuration Memory

User ID, Device ID, Revision ID, Configuration Words, DIA, DCI

NVMREGS = 1

DS40002002B-page 85

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

Figure 6-5.ꢀProgram Flash Memory Flowchart

Rev. 10-000049C

8/24/2015

Start

Write Operation

Determine number of

words to be written into

PFM. The number of

words cannot exceed the

number of words per row

(word_cnt)

Load the value to write

TABLAT

Update the word counter

(word_cnt--)

Write Latches to PFM

Disable Interrupts

Select access to PFM

locations using

NVMREG[1:0] bits

(GIE = 0)

Last word to

write ?

Yes

Select Row Address

TBLPTR

No

Unlock Sequence

(See Note 1)

Disable Interrupts

Select Write Operation

(GIE = 0)

(FREE = 0)

CPU stalls while Write

operation completes

(2 ms typical)

Unlock Sequence

Load Write Latches Only

(See Note 1)

Enable Write/Erase

Operation (WREN = 1)

Re-enable Interrupts

No delay when writing to

PFM Latches

(GIE = 1)

Disable Write/Erase

Operation (WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Write Operation

Increment Address

TBLPTR++

Note:ꢀ

1. See Figure 6-2 for an example of the Unlock sequence.

Example 6-4.ꢀWriting to Program Flash Memory

; This write routine assumes the following:

; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in

DS40002002B-page 86

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the least significant bits = 00000) is

loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

; 5. NVM interrupts are not taken into account

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

NVMADRH

ADDRH,W

NVMADRH

; Load initial address

ADDRL,W

NVMADRL

LOW DATA_ADDR

FSR0L

; Load initial data address

HIGH DATA_ADDR

FSR0H

NVMCON1,NVMREGS ; Set Program Flash Memory as write location

NVMCON1,WREN

NVMCON1,LWLO

BSF

; Enable writes

; Load only write latches

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

FSR0++

NVMDATL

FSR0++

NVMDATH

; Load first data byte

; Load second data byte

MOVF

NVMADRL,W

0x1F

XORLW

ANDLW

BTFSC

GOTO

; Check if lower bits of address are 00000

; and if on last of 32 addresses

; Last of 32 words?

0x1F

STATUS,Z

START_WRITE

; If so, go write latches into memory

CALL

INCF

GOTO

UNLOCK_SEQ

NVMADRL,F

LOOP

; If not, go load latch

; Increment address

START_WRITE

BCF

CALL

BCF

NVMCON1,LWLO

UNLOCK_SEQ

NVMCON1,WREN

; Latch writes complete, now write memory

; Perform required unlock sequence

; Disable writes

UNLOCK_SEQ

MOVLW

BCF

55h

INTCON,GIE

NVMCON2

AAh

; Disable interrupts

MOVWF

MOVLW

MOVWF

BSF

; Begin unlock sequence

NVMCON2

NVMCON1,WR

INTCON,GIE

BSF

; Unlock sequence complete, re-enable

interrupts

return

6.4.6

Modifying Flash Program Memory

When modifying existing data in a program memory, data within the memory row must be read and saved in a RAM

image. Program memory is modified using the following steps:

1. Load the starting address of the row to be modified.

2. Read the existing data from the row into a RAM image.

3. Modify the RAM image to contain the new data to be written into program memory.

4. Load the starting address of the row to be rewritten.

5. Erase the program memory row.

6. Load the write latches with data from the RAM image.

7. Initiate a programming operation.

DS40002002B-page 87

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

Figure 6-6.ꢀFlash Program Memory Modify Flowchart

Rev. 10-000050B

8/21/2015

Start

Modify Operation

Read Operation

(See Note 1)

An image of the entire row

read must be stored in RAM

Modify Image

The words to be modified are

changed in the RAM image

Erase Operation

(See Note 2)

Write Operation

Use RAM image

(See Note 3)

End

Modify Operation

Note:ꢀ

1. See Flash Program Memory Read Flowchart.

2. See NVM Erase Flowchart.

3. See Program Flash Memory Flowchart.

6.4.7

NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID,

EEPROM, and Configuration Words

NVMREGS can be used to access the following memory regions:

•

Device Information Area (DIA)

Device Configuration Information (DCI)

User ID region

Device ID and Revision ID

Configuration Words

EEPROM

The value of NVMREGS is set to ‘1’ in the NVMCON1 register to access these regions. The memory regions listed

above would be pointed to by PC[15] = 1, but not all addresses reference valid data. Different access may exist for

reads and writes. Refer to the table below. When read access is initiated on an address outside the parameters listed

in the following table, the NVMDATH: NVMDATL register pair is cleared, reading back ‘0’s.

DS40002002B-page 88

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

Table 6-2.ꢀNVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID,

EEPROM, and Configuration Words (NVMREGS = 1)

Address

Function

User IDs

Read Access

Write Access

0x8000 - 0x8003

0x8005 - 0x8006

0x8007 - 0x800B

0x8100 - 0x82FF

0xF000 - 0xF0FF

Yes

No

Device ID/Revision ID

Configuration Words 1-5

DIA and DCI

Yes

No

EEPROM

Yes

Example 6-5.ꢀDevice ID Access

; This write routine assumes the following:

; 1. A full row of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in

DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the least significant bits = 00000) is

loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

; 5. NVM interrupts are not taken into account

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

NVMADRH

ADDRH,W

NVMADRH

; Load initial address

ADDRL,W

NVMADRL

LOW DATA_ADDR

FSR0L

; Load initial data address

HIGH DATA_ADDR

FSR0H

NVMCON1,NVMREGS

NVMCON1,WREN

NVMCON1,LWLO

; Set PFM as write location

; Enable writes

; Load only write latches

BSF

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

CALL

FSR0++

NVMDATL

FSR0++

NVMDATH

UNLOCK_SEQ

NVMADRL,F

NVMADRL,W

0x1F

; Load first data byte

; Load second data byte

; If not, go load latch

; Increment address

INCF

MOVF

XORLW

ANDLW

BTFSC

GOTO

; Check if lower bits of address are 00000

; and if on last of 32 addresses

; Last of 32 words?

0x1F

STATUS,Z

START_WRITE

; If so, go write latches into memory

GOTO

LOOP

START_WRITE

BCF

CALL

BCF

NVMCON1,LWLO

UNLOCK_SEQ

NVMCON1,LWLO

; Latch writes complete, now write memory

; Perform required unlock sequence

; Disable writes

UNLOCK_SEQ

MOVLW

BCF

0x55

INTCON,GIE

NVMCON2

0xAA

; Disable interrupts

MOVWF

MOVLW

MOVWF

BSF

; Begin unlock sequence

NVMCON2

NVMCON1,WR

INTCON,GIE

BSF

; Unlock sequence complete, re-enable

DS40002002B-page 89

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

interrupts

RETURN

6.4.8

Write Verify

It is considered good programming practice to verify that program memory writes agree with the intended value.

Since program memory is stored as a full row then the stored program memory contents are compared with the

intended data stored in RAM after the last write is complete.

Figure 6-7.ꢀFlash Program Memory Verify Flowchart

Rev. 10-000051B

12/4/2015

Start

Verify Operation

This routine assumes that the last

row of data written was from an

image saved on RAM. This image

will be used to verify the data

currently stored in PFM

Read Operation⁽¹⁾

NVMDAT =

No

RAM image ?

Yes

Fail

Verify Operation

No

Last word ?

Yes

End

Verify Operation

Note:ꢀ

1. See Flash Program Memory Read Flowchart.

6.4.9

WRERR Bit

The WRERR bit in the NVMCON1 register can be used to determine if a write error occurred. WRERR will be set if

one of the following conditions occurs:

•

If WR is set while the NVMADRH:NMVADRL points to a write-protected address

A Reset occurs while a self-write operation was in progress

An unlock sequence was interrupted

DS40002002B-page 90

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

The WRERR bit is normally set by hardware, but can be set by the user for test purposes. Once set, WRERR must

be cleared in software.

Table 6-3.ꢀActions for PFM When WR = 1

Actions for PFM when WR = 1

Free LWLO

Comments

•

If WP is enabled, WR is cleared and WRERR is set

All 32 words are erased

Erase the 32-word row of

NVMADRH:NVMADRL location.

1

0

x

1

0

NVMDATH:NVMDATL is ignored

•

Write protection is ignored

No memory access occurs

Copy NVMDATH:NVMDATL to the write

latch corresponding to NVMADR LSBs.

•

If WP is enabled, WR is cleared and WRERR is set

Write latches are reset to 0x03FF

Write the write-latch data to PFM row.

NVMDATH:NVMDATL is ignored

Related Links

6.4.4 NVMREG Erase of Program Memory

DS40002002B-page 91

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.5

Register Summary: NVM Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x0819

7:0

15:8

7:0

NVMADR[7:0]

NVMADR[14:8]

NVMDAT[7:0]

0x081A

0x081C

NVMADR

NVMDAT

15:8

7:0

NVMDAT[13:8]

WRERR WREN

NVMCON2[7:0]

0x081E

0x081F

NVMCON1

NVMCON2

NVMREGS

LWLO

FREE

WR

RD

7:0

6.6

Register Definitions: Nonvolatile Memory

DS40002002B-page 92

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.6.1

NVMADR

Name:ꢀ

Offset:ꢀ

NVMADR

0x81A

Nonvolatile Memory Address Register

Bit

15

14

13

12

11

10

9

8

NVMADR[14:8]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

NVMADR[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 14:0 – NVMADR[14:0]ꢀNVM Address Bits

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

NVMADRH: Accesses the high byte NVMADR[15:8]

NVMADRL: Accesses the low byte NVMADR[7:0]

Note:ꢀ Bit [15] is undefined while WR = 1

DS40002002B-page 93

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.6.2

NVMDAT

Name:ꢀ

Offset:ꢀ

NVMDAT

0x81C

Nonvolatile Memory Data Register

Bit

15

14

13

12

11

10

9

8

NVMDAT[13:8]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bit

7

6

5

4

3

2

1

0

NVMDAT[7:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 13:0 – NVMDAT[13:0]ꢀNVM Data bits

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

NVMDATH: Accesses the high byte NVMDAT[13:8]

NVMDATL: Accesses the low byte NVMDAT[7:0]

Reset States: POR/BOR = xxxxxxxxxxxxxx

All Other Resets = uuuuuuuuuuuuuu

DS40002002B-page 94

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.6.3

NVMCON1

Name:ꢀ

Offset:ꢀ

NVMCON1

0x81E

Nonvolatile Memory Control 1 Register

Bit

7

6

NVMREGS

R/W

5

LWLO

R/W

0

4

FREE

R/S/HC

0

3

2

WREN

R/W

0

1

WR

0

RD

WRERR

R/W/HS

x

Access

Reset

R/S/HC

0

R/S/HC

0

Bit 6 – NVMREGSꢀNVM Region Selection bit

Value

Description

1

0

Access EEPROM, DIA, DCI, Configuration, User ID and Device ID Registers

Access Program Flash Memory

Bit 5 – LWLOꢀLoad Write Latches Only bit

Value

Condition

Description

1

When FREE = 0 The next WR command updates the write latch for this word within the row; no

memory operation is initiated.

0

-

When FREE = 0 The next WR command writes data or erases

Otherwise:

This bit is ignored.

Bit 4 – FREEꢀProgram Flash Memory Erase Enable bit

Value

Description

1

Performs an erase operation with the next WR command; the 32-word pseudo-row containing the

indicated address is erased (to all 1s) to prepare for writing.

The next WR command writes without erasing.

0

Bit 3 – WRERR

Write-Reset Error Flag bit^(1,2,3)

Reset States: POR/BOR = x

All Other Resets = q

Value

Description

1

A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one

while NVMADR points to a write-protected address.

All write operations have completed normally.

0

Bit 2 – WRENꢀProgram/Erase Enable bit

Value

Description

1

0

Allows program/erase cycles

Inhibits programming/erasing of program Flash

Bit 1 – WRꢀ Write Control bit^(4,5,6)

Value

Condition

Description

1

When NVMREG:NVMADR points to a Program

Flash Memory location:

Initiates the operation indicated by table in

“WRERR Bit” section.

0

1

0

When NVMREG:NVMADR points to a Program

Flash Memory location:

When NVMREG:NVMADR points to a EEPROM

location:

When NVMREG:NVMADR points to a EEPROM

location:

NVM program/erase operation is complete and

inactive.

Initiates an erase/program cycle at the

corresponding EEPROM location.

NVM program/erase operation is complete and

inactive.

Bit 0 – RDꢀ Read Control bit⁽⁷⁾

DS40002002B-page 95

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

Value

Description

1

Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction cycle

and the bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.

NVM read operation is complete and inactive

0

Note:ꢀ

1. Bit is undefined while WR = 1(during the EEPROM write operation it may be ‘0’ or ‘1’).

2. Bit must be cleared by software; hardware will not clear this bit.

3. Bit may be written to ‘1’ by the user in order to implement test sequences.

4. This bit can only be set by following the sequence described in the “NVM Unlock Sequence” section.

5. Operations are self-timed and the WR bit is cleared by hardware when complete.

6. Once a write operation is initiated, setting this bit to zero will have no effect.

7. Reading from EEPROM loads only NVMDATL.

Related Links

6.4.2 NVM Unlock Sequence

6.4.9 WRERR Bit

DS40002002B-page 96

Datasheet

PIC16(L)F18425/45

NVM - Nonvolatile Memory Control

6.6.4

NVMCON2

Name:ꢀ

Offset:ꢀ

NVMCON2

0x81F

Nonvolatile Memory Control 2 Register

Bit

7

6

5

4

3

2

1

0

NVMCON2[7:0]

Access

Reset

WO

0

WO

0

WO

0

WO

0

WO

0

WO

0

WO

0

WO

0

Bits 7:0 – NVMCON2[7:0]ꢀFlash Memory Unlock Pattern bits

Note:ꢀ To unlock writes, a 0x55 must be written first followed by an 0xAA before setting the WR bit of the NVMCON1

register. The value written to this register is used to unlock the writes.

DS40002002B-page 97

Datasheet

PIC16(L)F18425/45

Interrupts

7.

Interrupts

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the

source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.

Many peripherals can produce interrupts. Refer to the corresponding chapters for details.

A block diagram of the interrupt logic is shown in Figure 7-1.

Figure 7-1.ꢀInterrupt Logic

Rev. 10-000010C

10/12/2016

TMR0IF

TMR0IE

Wake-up

(If in Sleep mode)

INTF

INTE

Peripheral Interrupts

(ADIF) PIR1 [0]

(ADIE) PIE1 [0]

IOCIF

IOCIE

Interrupt

to CPU

PEIE

GIE

PIRn

PIEn

7.1

Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

•

GIE bit of the INTCON register

Interrupt Enable bit(s) for the specific interrupt event(s)

PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx

registers)

The PIR registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the

status of the GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:

•

Current prefetched instruction is flushed

GIE bit is cleared

Current Program Counter (PC) is pushed onto the stack

Critical registers are automatically saved to the shadow registers (see “Automatic Context Saving”)

PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the

interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because

the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but

will not cause the processor to redirect to the interrupt vector.

The RETFIEinstruction exits the ISR by popping the previous address from the stack, restoring the saved context

from the shadow registers and setting the GIE bit.

For additional information on a specific interrupts operation, refer to its peripheral chapter.

DS40002002B-page 98

Datasheet

PIC16(L)F18425/45

Interrupts

Important:ꢀ

1. Individual interrupt flag bits are set, regardless of the state of any other enable bits.

2. All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is

clear will be serviced when the GIE bit is set again.

Related Links

7.5 Automatic Context Saving

7.2

Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the

interrupt vector begins. The interrupt is sampled during Q1 of the instruction cycle. The actual interrupt latency then

depends on the instruction that is executing at the time the interrupt is detected. See the following figures for more

details.

Figure 7-2.ꢀInterrupt Latency

Rev. 10-000269E

8/31/2016

OSC1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKOUT

INT

Valid Interrupt

window⁽¹⁾

1 Cycle Instruction at PC

PC = 0x0004

NOP

PC - 1

PC - 2

PC

PC + 1

PC

PC = 0x0005 PC = 0x0006

PC = 0x0004 PC = 0x0005

Fetch

PC - 1

NOP

Execute

Indeterminate

Latency⁽²⁾

Latency

Note:ꢀ

1. An interrupt may occur at any time during the interrupt window.

2. Since an interrupt may occur any time during the interrupt window, the actual latency can vary.

DS40002002B-page 99

Datasheet

PIC16(L)F18425/45

Interrupts

Figure 7-3.ꢀINT Pin Interrupt Timing

Rev. 30-000150A

6/27/2017

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(4)

INT pin

INTF

(1)

(2)

(5)

Interrupt Latency

GIE

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (0004h)

Inst (PC + 1)

Inst (0005h)

Inst (0004h)

Instruction

Executed

For ced NOP

Inst (PC)

Inst (PC – 1)

Note:ꢀ

1. INTF flag is sampled here (every Q1).

2. Asynchronous interrupt latency = 3-5 T_CY. Synchronous latency = 3-4 T_CY, where T_CY= instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3. For minimum width of INT pulse, refer to AC specifications in the “Electrical Specifications” section.

4. INTF may be set any time during the Q4-Q1 cycles.

7.3

Interrupts During Sleep

Interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the

system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the

processor will continue executing instructions after the SLEEPinstruction. The instruction directly after the SLEEP

instruction will always be executed before branching to the ISR.

Related Links

12. Power-Saving Operation Modes

7.4

7.5

INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting

the INTE bit of the PIE0 register. The INTEDG bit of the INTCON register determines on which edge the interrupt will

occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling

edge will cause the interrupt. The INTF bit of the PIR0 register will be set when a valid edge appears on the INT pin.

If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.

Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are

automatically saved in the shadow registers:

DS40002002B-page 100

Datasheet

PIC16(L)F18425/45

Interrupts

•

W register

STATUS register (except for TO and PD)

BSR register

FSR registers

PCLATH register

Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these

registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow

register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in

Bank 63 and are readable and writable. Depending on the user’s application, other registers may also need to be

saved.

Related Links

5.10 Register Definitions: Shadow Registers

DS40002002B-page 101

Datasheet

PIC16(L)F18425/45

Interrupts

7.6

Register Summary - Interrupt Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x070B

0x070C

0x070D

0x070E

0x070F

0x0710

0x0711

0x0712

0x0713

0x0714

0x0715

0x0716

0x0717

0x0718

0x0719

0x071A

0x071B

0x071C

0x071D

0x071E

PIR0

PIR1

PIR2

PIR3

PIR4

PIR5

PIR6

PIR7

PIR8

Reserved

PIE0

PIE1

PIE2

PIE3

PIE4

PIE5

PIE6

PIE7

PIE8

7:0

TMR0IF

IOCIF

INTF

OSFIF

CSWIF

ZCDIF

ADTIF

C2IF

ADIF

C1IF

RC1IF

TMR6IF

CL24IF

TX1IF

TMR5IF

CLC1IF

BCL2IF

TMR4IF

SSP2IF

TMR3IF

TMR5GIF

CCP3IF

BCL1IF

TMR2IF

TMR3GIF

CCP2IF

CWG2IF

SSP1IF

TMR1IF

TMR1GIF

CCP1IF

CWG1IF

SMT1IF

CLC4IF

CLC3IF

CCP4IF

NVMIF

NCO1IF

IOCIE

SMT1PWAIF SMT1PRAIF

7:0

TMR0IE

INTE

ADIE

OSFIE

CSWIE

ZCDIE

ADTIE

C2IE

C1IE

RC1IE

TMR6IE

CLC2IE

TX1IE

TMR5IE

CLC1IE

BCL2IE

TMR4IE

SSP2IE

TMR3IE

TMR5GIE

CCP3IE

BCL1IE

TMR2IE

TMR3GIE

CCP2IE

CWG2IE

SSP1IE

TMR1IE

TMR1GIE

CCP1IE

CWG1IE

SMT1IE

CLC4IE

CLC3IE

CCP4IE

NVMIE

NCO1IE

SMT1PWAIE SMT1PRAIE

7.7

Register Definitions: Interrupt Control

DS40002002B-page 102

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.1

INTCON

Name:ꢀ

Offset:ꢀ

INTCON

0x00B

Interrupt Control Register

Bit

7

GIE

R/W

0

6

PEIE

R/W

0

5

4

3

2

1

0

INTEDG

R/W

1

Access

Reset

Bit 7 – GIEꢀGlobal Interrupt Enable bit

Value

Description

1

0

Enables all active interrupts

Disables all interrupts

Bit 6 – PEIEꢀPeripheral Interrupt Enable bit

Value

Description

1

0

Enables all active peripheral interrupts

Disables all peripheral interrupts

Bit 0 – INTEDGꢀExternal Interrupt Edge Select bit

Value

Description

1

0

Interrupt on rising edge of INT pin

Interrupt on falling edge of INT pin

Important:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its

corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt

flag bits are clear prior to enabling an interrupt. This feature allows for software polling.

DS40002002B-page 103

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.2

PIE0

Name:ꢀ

Offset:ꢀ

PIE0

0x716

Peripheral Interrupt Enable Register 0

Bit

7

6

5

TMR0IE

R/W

0

4

IOCIE

R/W

0

3

2

1

0

INTE

R/W

0

Access

Reset

Bit 5 – TMR0IEꢀ Timer0 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 4 – IOCIEꢀ Interrupt-on-Change Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 0 – INTEꢀ External Interrupt Enable bit⁽¹⁾

Value

1

Description

Enabled

0

Disabled

Note:ꢀ

1. The External Interrupt INT pin is selected by INTPPS.

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by PIE1-PIE8.

Interrupt sources controlled by the PIE0 register do not require PEIE to be set in order to allow interrupt vectoring

(when GIE is set).

Related Links

16.9.2 xxxPPS

DS40002002B-page 104

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.3

PIE1

Name:ꢀ

Offset:ꢀ

PIE1

0x717

Peripheral Interrupt Enable Register 1

Bit

7

OSFIE

R/W

0

6

CSWIE

R/W

0

5

4

3

2

1

ADTIE

R/W

0

ADIE

R/W

0

Access

Reset

Bit 7 – OSFIEꢀOscillator Fail Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 6 – CSWIEꢀClock-Switch Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 1 – ADTIEꢀADC Threshold Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 0 – ADIEꢀADC Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-

PIE8.

DS40002002B-page 105

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.4

PIE2

Name:ꢀ

Offset:ꢀ

PIE2

0x718

Peripheral Interrupt Enable Register 2

Bit

7

6

ZCDIE

R/W

0

5

4

3

2

1

C2IE

R/W

0

C1IE

R/W

0

Access

Reset

Bit 6 – ZCDIEꢀZero-Cross Detect Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bits 0, 1 – CnIEꢀComparator ‘n’ Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-

PIE8.

DS40002002B-page 106

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.5

PIE3

Name:ꢀ

Offset:ꢀ

PIE3

0x719

Peripheral Interrupt Enable Register 3

Bit

7

6

5

RC1IE

R/W

0

4

TX1IE

R/W

0

3

BCL2IE

R/W

0

2

SSP2IE

R/W

0

1

BCL1IE

R/W

0

SSP1IE

R/W

0

Access

Reset

Bit 5 – RCnIEꢀEUSARTn Receive Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 4 – TXnIEꢀEUSARTn Transmit Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bits 1, 3 – BCLnIEꢀMSSPn Bus Collision Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bits 0, 2 – SSPnIEꢀSynchronous Serial Port ‘n’ Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-

PIE8.

DS40002002B-page 107

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.6

PIE4

Name:ꢀ

Offset:ꢀ

PIE4

0x71A

Peripheral Interrupt Enable Register 4

Bit

7

6

5

TMR6IE

R/W

0

4

TMR5IE

R/W

0

3

TMR4IE

R/W

0

2

TMR3IE

R/W

0

1

TMR2IE

R/W

0

TMR1IE

R/W

0

Access

Reset

Bit 5 – TMR6IEꢀTMR6 to PR6 Match Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 4 – TMR5IEꢀTMR5 Overflow Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 3 – TMR4IEꢀTMR4 to PR4 Match Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 2 – TMR3IEꢀTMR3 Overflow Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 1 – TMR2IEꢀTMR2 to PR2 Match Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 0 – TMR1IEꢀTMR1 Overflow Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-

PIE8.

DS40002002B-page 108

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.7

PIE5

Name:ꢀ

Offset:ꢀ

PIE5

0x71B

Peripheral Interrupt Enable Register 5

Bit

7

CLC4IE

R/W

0

6

CLC3IE

R/W

0

5

CLC2IE

R/W

0

4

CLC1IE

R/W

0

3

2

TMR5GIE

R/W

1

TMR3GIE

R/W

0

TMR1GIE

R/W

Access

Reset

0

Bit 7 – CLC4IEꢀCLC4 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 6 – CLC3IEꢀCLC3 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 5 – CLC2IEꢀCLC2 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 4 – CLC1IEꢀCLC1 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 2 – TMR5GIEꢀTMR5 Gate Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 1 – TMR3GIEꢀTMR3 Gate Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 0 – TMR1GIEꢀTMR1 Gate Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-

PIE8.

DS40002002B-page 109

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.8

PIE6

Name:ꢀ

Offset:ꢀ

PIE6

0x71C

Peripheral Interrupt Enable Register 6

Bit

7

6

5

4

3

CCP4IE

R/W

0

2

CCP3IE

R/W

0

1

CCP2IE

R/W

0

CCP1IE

R/W

0

Access

Reset

Bit 3 – CCP4IEꢀCCP4 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 2 – CCP3IEꢀCCP3 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 1 – CCP2IEꢀCCP2 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 0 – CCP1IEꢀCCP1 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-

PIE8.

DS40002002B-page 110

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.9

PIE7

Name:ꢀ

Offset:ꢀ

PIE7

0x71D

Peripheral Interrupt Enable Register 7

Bit

7

6

5

NVMIE

R/W

0

4

NCO1IE

R/W

0

3

2

1

CWG2IE

R/W

0

CWG1IE

R/W

Access

Reset

0

Bit 5 – NVMIEꢀNVM Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 4 – NCO1IEꢀNCO Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 1 – CWG2IEꢀCWG2 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 0 – CWG1IEꢀCWG1 Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-

PIE8.

DS40002002B-page 111

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.10 PIE8

Name:ꢀ

Offset:ꢀ

PIE8

0x71E

Peripheral Interrupt Enable Register 8

Bit

7

6

5

4

3

2

1

0

SMT1IE

R/W

0

SMT1PWAIE

SMT1PRAIE

Access

Reset

R/W

0

R/W

0

Bit 2 – SMT1PWAIEꢀSMT1 Pulse-width Acquisition Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 1 – SMT1PRAIEꢀSMT1 Period Acquisition Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Bit 0 – SMT1IEꢀSMT1 Counter Overflow Interrupt Enable bit

Value

1

Description

Enabled

0

Disabled

Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-

PIE8.

DS40002002B-page 112

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.11

PIR0

Name:ꢀ

Offset:ꢀ

PIR0

0x70C

Peripheral Interrupt Request (Flag) Register 0

Bit

7

6

5

4

IOCIF

RO

0

3

2

1

0

INTF

R/W/HS

0

TMR0IF

R/W/HS

0

Access

Reset

Bit 5 – TMR0IFꢀ Timer0 Interrupt Flag bit

Value

Description

1

0

TMR0 register has overflowed (must be cleared by software)

TMR0 register has not overflowed

Bit 4 – IOCIFꢀ Interrupt-on-Change Flag bit⁽²⁾

Value

Description

1

One or more of the IOCAF-IOCEF register bits are currently set, indicating an enabled edge was

detected by the IOC module.

0

None of the IOCAF-IOCEF register bits are currently set

Bit 0 – INTFꢀ External Interrupt Flag bit⁽¹⁾

Value

Description

1

0

External Interrupt has occurred

External Interrupt has not occurred

Note:ꢀ

1. The External Interrupt INT pin is selected by INTPPS.

2. The IOCIF bit is the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag, application

firmware must clear all of the lower level IOCAF-IOCEF register bits.

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

Related Links

16.9.2 xxxPPS

DS40002002B-page 113

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.12 PIR1

Name:ꢀ

Offset:ꢀ

PIR1

0x70D

Peripheral Interrupt Request (Flag) Register 1

Bit

7

6

5

4

3

2

1

ADTIF

R/W/HS

0

ADIF

R/W/HS

0

OSFIF

R/W/HS

0

CSWIF

R/W/HS

0

Access

Reset

Bit 7 – OSFIFꢀOscillator Fail Interrupt Flag bit

Value

Description

1

0

Oscillator fail-safe interrupt has occurred (must be cleared in software)

No oscillator fail-safe interrupt

Bit 6 – CSWIFꢀ Clock-Switch Complete Interrupt Flag bit

Value

Description

1

The clock switch module indicates an interrupt condition and is ready to complete the clock switch

operation (must be cleared in software)

0

The clock switch does not indicate an interrupt condition

Bit 1 – ADTIFꢀADC Threshold Interrupt Flag bit

Value

Description

1

0

An A/D conversion or complex operation has completed (must be cleared in software)

An A/D conversion or complex operation is not complete

Bit 0 – ADIFꢀADC Interrupt Flag bit

Value

Description

1

0

An A/D conversion or complex operation has completed (must be cleared in software)

An A/D conversion or complex operation is not complete

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

DS40002002B-page 114

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.13 PIR2

Name:ꢀ

Offset:ꢀ

PIR2

0x70E

Peripheral Interrupt Request (Flag) Register 2

Bit

7

6

5

4

3

2

1

C2IF

R/W/HS

0

C1IF

R/W/HS

0

ZCDIF

R/W/HS

0

Access

Reset

Bit 6 – ZCDIFꢀZero-Cross Detect Interrupt Flag bit

Value

Description

1

0

An enabled rising and/or falling ZCD1 event has been detected (must be cleared in software)

No ZCD1 event has occurred

Bits 0, 1 – CnIFꢀComparator ‘n’ Interrupt Flag bit

Value

Description

1

0

Comparator Cn interrupt asserted (must be cleared in software)

Comparator Cn interrupt not asserted

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

DS40002002B-page 115

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.14 PIR3

Name:ꢀ

Offset:ꢀ

PIR3

0x70F

Peripheral Interrupt Request (Flag) Register 3

Bit

7

6

5

4

3

2

1

0

RC1IF

RO/HS

0

TX1IF

RO/HS

0

BCL2IF

R/W/HS

0

SSP2IF

R/W/HS

0

BCL1IF

R/W/HS

0

SSP1IF

R/W/HS

0

Access

Reset

Bit 5 – RCnIFꢀ EUSARTn Receive Interrupt Flag bit⁽¹⁾

Value

Description

1

0

The EUSARTn receive buffer is not empty (contains at least one byte)

The EUSARTn receive buffer is empty

Bit 4 – TXnIFꢀ EUSARTn Transmit Interrupt Flag bit⁽²⁾

Value

Description

1

The EUSARTn transmit buffer contains at least one unoccupied space

0

The EUSARTn transmit buffer is currently full. The application firmware should not write to TXnREG

again, until more room becomes available in the transmit buffer.

Bits 1, 3 – BCLnIFꢀMSSPn Bus Collision Interrupt Flag bit

Value

Description

1

0

A bus collision was detected (must be cleared in software)

No bus collision was detected

Bits 0, 2 – SSPnIFꢀSynchronous Serial Port ‘n’ Interrupt Flag bit

Value

Description

1

0

The Transmission/Reception/Bus Condition is complete (must be cleared in software)

Waiting for the Transmission/Reception/Bus Condition in progress

Note:ꢀ

1. The RCnIF flag is a read-only bit. To clear the RCnIF flag, the firmware must read from RCnREG enough

times to remove all bytes from the receive buffer.

2. The TXnIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TXnIF flag, the

firmware must write enough data to TXnREG to completely fill all available bytes in the buffer. The TXnIF flag

does not indicate transmit completion (use TRMT for this purpose instead).

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

DS40002002B-page 116

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.15 PIR4

Name:ꢀ

Offset:ꢀ

PIR4

0x710

Peripheral Interrupt Request (Flag) Register 4

Bit

7

6

5

4

3

2

1

0

TMR6IF

R/W/HS

0

TMR5IF

R/W/HS

0

TMR4IF

R/W/HS

0

TMR3IF

R/W/HS

0

TMR2IF

R/W/HS

0

TMR1IF

R/W/HS

0

Access

Reset

Bit 5 – TMR6IFꢀTMR6 to PR6 Match Interrupt Flag bit

Value

Description

1

The TMR6 postscaler overflowed, or in 1:1 mode, a TMR6 to PR6 match occurred (must be cleared in

software)

0

No TMR6 event has occurred

Bit 4 – TMR5IFꢀTMR5 Overflow Interrupt Flag bit

Value

Description

1

0

TMR5 register overflowed (must be cleared in software)

TMR5 register did not overflow

Bit 3 – TMR4IFꢀTMR4 to PR4 Match Interrupt Flag bit

Value

Description

1

The TMR4 postscaler overflowed, or in 1:1 mode, a TMR4 to PR4 match occurred (must be cleared in

software)

0

No TMR4 event has occurred

Bit 2 – TMR3IFꢀTMR3 Overflow Interrupt Flag bit

Value

Description

1

0

TMR3 register overflowed (must be cleared in software)

TMR3 register did not overflow

Bit 1 – TMR2IFꢀTMR2 to PR2 Match Interrupt Flag bit

Value

Description

1

The TMR2 postscaler overflowed, or in 1:1 mode, a TMR2 to PR2 match occurred (must be cleared in

software)

0

No TMR2 event has occurred

Bit 0 – TMR1IFꢀTMR1 Overflow Interrupt Flag bit

Value

Description

1

0

TMR1 register overflowed (must be cleared in software)

TMR1 register did not overflow

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

DS40002002B-page 117

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.16 PIR5

Name:ꢀ

Offset:ꢀ

PIR5

0x711

Peripheral Interrupt Request (Flag) Register 5

Bit

7

6

5

4

3

2

1

0

CLC4IF

R/W/HS

0

CLC3IF

R/W/HS

0

CL24IF

R/W/HS

0

CLC1IF

R/W/HS

0

TMR5GIF

R/W/HS

0

TMR3GIF

R/W/HS

0

TMR1GIF

R/W/HS

0

Access

Reset

Bit 7 – CLC4IFꢀCLC4 Interrupt Flag bit

Value

Description

1

0

A CLC4OUT interrupt condition has occurred (must be cleared in software)

No CLC4 interrupt event has occurred

Bit 6 – CLC3IFꢀCLC3 Interrupt Flag bit

Value

Description

1

0

A CLC3OUT interrupt condition has occurred (must be cleared in software)

No CLC3 interrupt event has occurred

Bit 5 – CL24IFꢀCLC2 Interrupt Flag bit

Value

Description

1

0

A CLC2OUT interrupt condition has occurred (must be cleared in software)

No CLC2 interrupt event has occurred

Bit 4 – CLC1IFꢀCLC1 Interrupt Flag bit

Value

Description

1

0

A CLC1OUT interrupt condition has occurred (must be cleared in software)

No CLC1 interrupt event has occurred

Bit 2 – TMR5GIFꢀTMR5 Gate Interrupt Flag bit

Value

Description

1

0

The Timer5 Gate has gone inactive (the acquisition is complete)

The Timer5 Gate has not gone inactive

Bit 1 – TMR3GIFꢀTMR3 Gate Interrupt Flag bit

Value

Description

1

0

The Timer3 Gate has gone inactive (the acquisition is complete)

The Timer3 Gate has not gone inactive

Bit 0 – TMR1GIFꢀTMR1 Gate Interrupt Flag bit

Value

Description

1

0

The Timer1 Gate has gone inactive (the acquisition is complete)

The Timer1 Gate has not gone inactive

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

DS40002002B-page 118

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.17 PIR6

Name:ꢀ

Offset:ꢀ

PIR6

0x712

PIR6 Peripheral Interrupt Request (Flag) Register 6

Bit

7

6

5

4

3

2

1

0

CCP4IF

R/W/HS

0

CCP3IF

R/W/HS

0

CCP2IF

R/W/HS

0

CCP1IF

R/W/HS

0

Access

Reset

Bit 3 – CCP4IFꢀCCP4 Interrupt Flag bit

Value

Condition

Description

1

0

1

0

1

0

Capture mode

Compare mode

PWM mode

Capture occurred (must be cleared in software)

Capture did not occur

Compare match occurred (must be cleared in software)

Compare match did not occur

Output trailing edge occurred (must be cleared in software)

Output trailing edge did not occur

PWM mode

Bit 2 – CCP3IFꢀCCP3 Interrupt Flag bit

Value

Condition

Description

1

0

1

0

1

0

Capture mode

Compare mode

PWM mode

Capture occurred (must be cleared in software)

Capture did not occur

Compare match occurred (must be cleared in software)

Compare match did not occur

Output trailing edge occurred (must be cleared in software)

Output trailing edge did not occur

PWM mode

Bit 1 – CCP2IFꢀCCP2 Interrupt Flag bit

Value

Condition

Description

1

0

1

0

1

0

Capture mode

Compare mode

PWM mode

Capture occurred (must be cleared in software)

Capture did not occur

Compare match occurred (must be cleared in software)

Compare match did not occur

Output trailing edge occurred (must be cleared in software)

Output trailing edge did not occur

PWM mode

Bit 0 – CCP1IFꢀCCP1 Interrupt Flag bit

Value

Condition

Description

1

0

1

0

1

0

Capture mode

Compare mode

PWM mode

Capture occurred (must be cleared in software)

Capture did not occur

Compare match occurred (must be cleared in software)

Compare match did not occur

Output trailing edge occurred (must be cleared in software)

Output trailing edge did not occur

PWM mode

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

DS40002002B-page 119

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.18 PIR7

Name:ꢀ

Offset:ꢀ

PIR7

0x713

Peripheral Interrupt Request (Flag) Register 7

Bit

7

6

5

4

3

2

1

0

NVMIF

R/W/HS

0

NCO1IF

R/W/HS

0

CWG2IF

R/W/HS

0

CWG1IF

R/W/HS

0

Access

Reset

Bit 5 – NVMIFꢀNVM Interrupt Flag bit

Value

Description

1

0

The requested NVM operation has completed

NVM interrupt not asserted

Bit 4 – NCO1IFꢀNumerically Controlled Oscillator (NCO) Interrupt Flag bit

Value

Description

1

0

The NCO has rolled over

No NCO interrupt event has occurred

Bit 1 – CWG2IFꢀCWG2 Interrupt Flag bit

Value

Description

1

0

CWG2 has gone into shutdown

CWG2 is operating normally, or interrupt cleared

Bit 0 – CWG1IFꢀCWG1 Interrupt Flag bit

Value

Description

1

0

CWG1 has gone into shutdown

CWG1 is operating normally, or interrupt cleared

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

DS40002002B-page 120

Datasheet

PIC16(L)F18425/45

Interrupts

7.7.19 PIR8

Name:ꢀ

Offset:ꢀ

PIR8

0x714

Peripheral Interrupt Request (Flag) Register 8

Bit

7

6

5

4

3

2

SMT1PWAIF

R/W/HS

0

1

SMT1PRAIF

R/W/HS

0

SMT1IF

R/W/HS

0

Access

Reset

Bit 2 – SMT1PWAIFꢀSMT1 Pulse-Width Acquisition Interrupt Flag bit

Value

Description

1

0

Interrupt has occurred (must be cleared by software)

Interrupt event has not occurred

Bit 1 – SMT1PRAIFꢀSMT1 Period Acquisition Interrupt Flag bit

Value

Description

1

0

Interrupt has occurred (must be cleared by software)

Interrupt event has not occurred

Bit 0 – SMT1IFꢀSMT1 Interrupt Flag bit

Value

Description

1

0

Interrupt has occurred (must be cleared by software)

Interrupt event has not occurred

Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Enable bit, GIE, of the INTCON appropriate interrupt flag bits are clear prior to enabling an

interrupt.

DS40002002B-page 121

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.

OSC - Oscillator Module

8.1

Overview

The oscillator module has multiple clock sources and selection features that allow it to be used in a wide range of

applications while maximizing performance and minimizing power consumption. The following figure illustrates a

block diagram of the oscillator module.

Clock sources can be supplied from external oscillators, quartz-crystal resonators and ceramic resonators. In

addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice

of speeds selectable via software. Additional clock features include:

•

Selectable system clock source between external or internal sources via software.

Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH,

ECM, ECL) and switch automatically to the internal oscillator.

•

Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources.

The RSTOSC bits of Configuration Word 1 determine the type of oscillator that will be used when the device runs

after Reset, including when it is first powered up.

The internal clock modes, LFINTOSC, HFINTOSC (set at 1 MHz), or HFINTOSC (set at 32 MHz) can be set through

the RSTOSC bits.

If an external clock source is selected, the FEXTOSC bits of Configuration Word 1 must be used in conjunction with

the RSTOSC bits to select the External Clock mode.

The external oscillator module can be configured in one of the following clock modes, by setting the FEXTOSC bits of

Configuration Word 1:

1. ECL – External Clock Low-Power mode

(≤ 500 kHz)

2. ECM – External Clock Medium-Power mode

(≤ 8 MHz)

3. ECH – External Clock High-Power mode

(≤ 32 MHz)

4. LP – 32 kHz Low-Power Crystal mode

5. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (between 100 kHz and 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator mode (above 4 MHz)

The ECH, ECM, and ECL Clock modes rely on an external logic level signal as the device clock source. The LP, XT,

and HS Clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized

for a different frequency range. The internal oscillator block produces low and high-frequency clock sources,

designated LFINTOSC and HFINTOSC. Multiple device clock frequencies may be derived from these clock sources.

DS40002002B-page 122

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

Figure 8-1.ꢀSimplified PIC^®MCU Clock Source Block Diagram

Rev. 10-000208M

5/17/2017

CLKIN/ OSC1

External

Oscillator

(EXTOSC)

CLKOUT/ OSC2

CDIV[3:0]

4x PLL Mode

COSC[2:0]

SOSCIN/SOSCI

Secondary

Oscillator

(SOSC)

512

PLL Block

1001

256

128

64

32

16

8

111

001

010

100

101

110

000

011

1000

Sleep

2x PLL Mode

0111

System Clock

SOSCO

LFINTOSC

0110

0101

31kHz

Oscillator

0100

SYSCMD

Peripheral Clock

0011

4

0010 Sleep

2

0001

0000

Idle

1

HFINTOSC

HFFRQ[2:0]

1 – 32 MHz

Oscillator

FSCM

To Peripherals

Related Links

4.7.1 CONFIG1

8.2

Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function. Examples include: oscillator modules

(ECH, ECM, ECL mode) and quartz crystal resonators or ceramic resonators (LP, XT and HS modes).

There is also a secondary oscillator block which is optimized for a 32.768 kHz external clock source, which can be

used as an alternate clock source.

There are two internal oscillator blocks:

•

HFINTOSC

LFINTOSC

The HFINTOSC can produce clock frequencies from 1-32 MHz, and is responsible for generating the two MFINTOSC

frequencies (500 kHz and 32 kHz) that can be used by some peripherals. The LFINTOSC generates a 31 kHz clock

frequency.

There is a 4x PLL that can be used by the external oscillator. Additionally, there is a 2x PLL that can be used by the

HFINTOSC at certain frequencies.

Related Links

8.2.1.4 4x PLL

8.2.2.3 2x PLL

8.2.1

External Clock Sources

An external clock source can be used as the device system clock by performing one of the following actions:

DS40002002B-page 123

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

•

Program the RSTOSC bits in the Configuration Word 1 to select an external clock source that will be used as the

default system clock upon a device Reset.

Write the NOSC and NDIV bits to switch the system clock source.

Related Links

8.3 Clock Switching

8.2.1.1 EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When

operating in this mode, an external clock source is connected to the CLKIN/OSC1 input. OSC2/CLKOUT is available

for general purpose I/O or CLKOUT. The Figure 8-2 shows the pin connections for EC mode.

EC mode has three power modes to select from through Configuration Words:

•

ECH – High power, ≤ 32 MHz

ECM – Medium power, ≤ 8 MHz

ECL – Low power, ≤ 0.1 MHz

The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation

after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC^®MCU design is fully static, stopping the

external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external

clock, the device will resume operation as if no time had elapsed.

Figure 8-2.ꢀExternal Clock (EC) Mode Operation

Rev. 30-000060A

4/6/2017

OSC1/CLKIN

PIC^®MCU

Clock from

Ext. System

OSC2/CLKOUT

(1)

FOSC/4 or

I/O

Note:ꢀ

1. Output depends upon CLKOUTEN bit of the Configuration Word 1 (CONFIG1).

8.2.1.2 LP, XT, HS Modes

The LP, XT, and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1

and OSC2 (Figure 8-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to

support various resonator types and speed.

LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is

the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch

crystals). but can operate up to 100 kHz.

XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current

consumption is the medium of the three modes. This mode is best suited to drive crystals and resonators with a

frequency range up to 4 MHz.

HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is

the highest of the three modes. This mode is best suited for resonators that require operating frequencies up to 20

MHz.

Figure 8-3 and Figure 8-4 show typical circuits for quartz crystal and ceramic resonators, respectively.

DS40002002B-page 124

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

Figure 8-3.ꢀQuartz Crystal Operation (LP, XT or HS Mode)

Rev. 10-000059A

7/30/2013

PIC^®MCU

OSC1/CLKIN

C1

To Internal

Logic

Quartz

Crystal

(2)

Sleep

RF

OSC2/CLKOUT

(1)

C2

RS

Note:ꢀ

1. Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the

manufacturer data sheets for specifications and recommended application.

2. Always verify oscillator performance over the V_DDand temperature range that is expected for the application.

3. For oscillator design assistance, reference the following Microchip Application Notes:

– AN826, “Crystal Oscillator Basics and Crystal Selection for PIC^®and PIC^®Devices” (DS00826)

– AN849, “Basic PIC^®Oscillator Design” (DS00849)

– AN943, “Practical PIC^®Oscillator Analysis and Design” (DS00943)

– AN949, “Making Your Oscillator Work” (DS00949)

Figure 8-4.ꢀCeramic Resonator Operation

(XT or HS Mode)

Rev. 30-000062A

4/6/2017

PIC^®MCU

OSC1/CLKIN

C1

To Internal

Logic

(3)

(2)

RP

RF

Sleep

OSC2/CLKOUT

(1)

C2

RS

Ceramic

Resonator

Note:ꢀ

1. Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the

manufacturer data sheets for specifications and recommended application.

2. Always verify oscillator performance over the V_DDand temperature range that is expected for the application.

3. For oscillator design assistance, reference the following Microchip Application Notes:

®

–

AN826, Crystal Oscillator Basics andCrystal Selection for rfPIC and PIC Devices (DS00826)

®

AN849, Basic PIC Oscillator Design (DS00849)

®

AN943, Practical PIC Oscillator Analysis and Design (DS00943)

AN949, Making Your Oscillator Work (DS00949)

8.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024

oscillations from OSC1. This occurs following a Power-on Reset (POR), or a wake-up from Sleep. The OST ensures

that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable

system clock to the oscillator module.

DS40002002B-page 125

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.2.1.4 4x PLL

The oscillator module contains a 4x PLL that can be used with the external clock sources to provide a system clock

source. The input frequency for the PLL must fall within specifications.

The PLL can be enabled for use by one of two methods:

1. Program the RSTOSC bits in the Configuration Word 1 to ‘010’ (enable EXTOSC with 4x PLL).

2. Write the NOSC bits to ‘010’ (enable EXTOSC with 4x PLL).

Related Links

8.6.1 OSCCON1

40.4.3 PLL Specifications

8.2.1.5 Secondary Oscillator

The secondary oscillator is a separate oscillator block that can be used as an alternate system clock source. The

secondary oscillator is optimized for 32.768 kHz, and can be used with an external crystal oscillator connected to the

SOSCI and SOSCO device pins, or an external clock source connected to the SOSCIN pin. The secondary oscillator

can be selected during run-time using clock switching.

Figure 8-5.ꢀQuartz Crystal Operation (Secondary Oscillator)

Rev. 30-000063A

4/6/2017

PIC^®MCU

SOSCI

C1

To Internal

Logic

32.768 kHz

Quartz

Crystal

SOSCO

C2

Related Links

8.3 Clock Switching

8.2.2

Internal Clock Sources

The device may be configured to use the internal oscillator block as the system clock by performing one of the

following actions:

•

Program the RSTOSC bits in Configuration Word 1 to select the INTOSC clock source, which will be used as the

default system clock upon a device Reset.

•

Write the NOSC bits to switch the system clock source to the internal oscillator during run-time.

The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Word 1.

The internal oscillator block has two independent oscillators that can produce two internal system clock sources.

1. The HFINTOSC (High-Frequency Internal Oscillator) is factory-calibrated and operates up to 32 MHz.

2. The LFINTOSC (Low-Frequency Internal Oscillator) is factory-calibrated and operates at 31 kHz.

Related Links

8.3 Clock Switching

8.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a precision digitally-controlled internal clock source that

produces a stable clock up to 32 MHz. The HFINTOSC can be enabled through one of the following methods:

•

Programming the RSTOSC bits in Configuration Word 1 to ‘110’ (F_OSC= 1 MHz) or ‘000’ (F_OSC= 32 MHz) to set

the oscillator upon device Power-up or Reset.

DS40002002B-page 126

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

•

Write to the NOSC bits during run-time.

The HFINTOSC frequency can be selected by setting the HFFRQ bits.

The NDIV bits allow for division of the output of the selected clock source by a range between 1:1 and 1:512.

Related Links

8.3 Clock Switching

8.6.1 OSCCON1

8.6.7 OSCFRQ

8.2.2.2 MFINTOSC

The module provides two (500 kHz and 31.25 kHz) constant clock outputs. These clocks are digital divisors of the

HFINTOSC clock. Dynamic divider logic is used to provide constant MFINTOSC clock rates for all settings of

HFINTOSC.

The MFINTOSC cannot be used to drive the system but it is used to clock certain modules such as the Timers and

WWDT.

8.2.2.3 2x PLL

The oscillator module contains a PLL that can be used with the HFINTOSC clock source to provide a system clock

source. The input frequency to the PLL is limited to 8, 12, or 16 MHz, which will yield a system clock source of 16, 24,

or 32 MHz, respectively.

The PLL may be enabled for use by one of two methods:

1. Program the RSTOSC bits in the Configuration Word 1 to ‘001’ to enable the HFINTOSC (32 MHz). This

setting configures the HFFRQ bits to ‘101’ (16 MHz) and activates the 2x PLL.

2. Write ‘001’ the NOSC bits to enable the 2x PLL, and write the correct value into the HFFRQ to select the

desired system clock frequency.

Related Links

8.6.1 OSCCON1

8.6.7 OSCFRQ

8.2.2.4 Internal Oscillator Frequency Adjustment

The internal oscillator is factory-calibrated. This internal oscillator can be adjusted in software by writing to the

OSCTUNE register.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock

source frequency, such as the Power-up Timer (PWRT), WWDT, Fail-Safe Clock Monitor (FSCM) and peripherals,

are not affected by the change in frequency.

The default value of the OSCTUNE register is 00h. The value is a 6-bit two’s complement number. A value of 1Fh will

provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum

frequency.

When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code

execution continues during this shift. There is no indication that the shift has occurred.

Related Links

8.6.6 OSCTUNE

8.2.2.5 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is a factory-calibrated 31 kHz internal clock source.

The LFINTOSC is the frequency for the Power-up Timer (PWRT), Windowed Watchdog Timer (WWDT) and Fail-Safe

Clock Monitor (FSCM).

The LFINTOSC is enabled through one of the following methods:

•

Programming the RSTOSC bits of Configuration Word 1 to enable LFINTOSC.

Write to the NOSC bits during run-time.

DS40002002B-page 127

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

Related Links

8.3 Clock Switching

4.7.1 CONFIG1

8.6.1 OSCCON1

8.2.2.6 Oscillator Status and Manual Enable

The ‘ready’ status of each oscillator is displayed in the OSCSTAT register. The oscillators can also be manually

enabled through the OSCEN register. Manual enabling makes it possible to verify the operation of the EXTOSC or

SOSC crystal oscillators. This can be achieved by enabling the selected oscillator, then watching the corresponding

‘ready’ state of the oscillator in the OSCSTAT register.

Related Links

8.6.4 OSCSTAT

8.6.5 OSCEN

8.2.2.7 HFOR and MFOR Bits

The HFOR and MFOR bits indicate that the HFINTOSC and MFINTOSC is ready. These clocks are always valid for

use at all times, but only accurate after they are ready.

When a new value is loaded into the OSCFRQ register, the HFOR and MFOR bits will clear, and set again when the

oscillator is ready. During pending OSCFRQ changes the MFINTOSC clock will stall at a high or a low state, until the

HFINTOSC resumes operation.

8.3

Clock Switching

The system clock source can be switched between external and internal clock sources via software using the New

Oscillator Source (NOSC) and New Divider selection request (NDIV) bits. The following clock sources can be

selected:

•

External Oscillator (EXTOSC)

High-Frequency Internal Oscillator (HFINTOSC)

Low-Frequency Internal Oscillator (LFINTOSC)

Secondary Oscillator (SOSC)

EXTOSC with 4x PLL

HFINTOSC with 2x PLL

8.3.1

New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits

The New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) bits select the system clock source

and frequency that are used for the CPU and peripherals.

When new values of NOSC and NDIV are written to OSCCON1, the current oscillator selection will continue to

operate while waiting for the new clock source to indicate that it is stable and ready. In some cases, the newly

requested source may already be in use, and is ready immediately. In the case of a divider-only change, the new and

old sources are the same, so the old source will be ready immediately. The device may enter Sleep while waiting for

the switch, as described in 8.3.3 Clock Switch and Sleep.

When the new oscillator is ready, the New Oscillator Ready (NOSCR) bit of OSCCON3 is set and also the Clock

Switch Interrupt Flag (CSWIF) bit of PIR1 is set. If Clock Switch Interrupts are enabled (CSWIE = 1), an interrupt will

be generated at that time. The Oscillator Ready (ORDY) bit of OSCCON3 can also be polled to determine when the

oscillator is ready in lieu of an interrupt.

If the Clock Switch Hold (CSWHOLD) bit is clear, the oscillator switch will occur when the New Oscillator is READY

bit (NOSCR) is set, and the interrupt (if enabled) will be serviced at the new oscillator setting.

If CSWHOLD is set, the oscillator switch is suspended, while execution continues using the current (old) clock

source. When the NOSCR bit is set, software should:

•

Set CSWHOLD = 0so the switch can complete, or

Copy COSC into NOSC to abandon the switch.

DS40002002B-page 128

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

If Doze is in effect, the switch occurs on the next clock cycle, whether or not the CPU is operating during that cycle.

Changing the clock post-divider without changing the clock source (i.e., changing F_OSCfrom 1 MHz to 2 MHz) is

handled in the same manner as a clock source change, as described previously. The clock source will already be

active, so the switch is relatively quick. CSWHOLD must be clear (CSWHOLD = 0) for the switch to complete.

The current COSC and CDIV are indicated in the OSCCON2 register up to the moment when the switch actually

occurs, at which time OSCCON2 is updated and ORDY is set. NOSCR is cleared by hardware to indicate that the

switch is complete.

Related Links

8.3.3 Clock Switch and Sleep

8.6.1 OSCCON1

8.6.2 OSCCON2

8.6.3 OSCCON3

8.3.2

PLL Input Switch

Switching between the PLL and any non-PLL source is managed as described above. The input to the PLL is

established when NOSC selects the PLL, and maintained by the COSC setting.

When NOSC and COSC select the PLL with different input sources, the system continues to run using the COSC

setting, and the new source is enabled per NOSC. When the new oscillator is ready (and CSWHOLD = 0), system

operation is suspended while the PLL input is switched and the PLL acquires lock. This provides a truly glitch-free

clock switch operation.

Important:ꢀ If the PLL fails to lock, the FSCM will trigger.

8.3.3

Clock Switch and Sleep

If OSCCON1 is written with a new value and the device is put to Sleep before the switch completes, the switch will

not take place and the device will enter Sleep mode.

When the device wakes from Sleep and the CSWHOLD bit is clear, the device will wake with the ‘new’ clock active,

and the Clock Switch Interrupt Flag bit (CSWIF) will be set.

When the device wakes from Sleep and the CSWHOLD bit is set, the device will wake with the ‘old’ clock active and

the new clock will be requested again.

Figure 8-6.ꢀClock Switch (CSWHOLD = 0)

Rev. 30-000064A

4/7/2016

OSCCON1

WRITTEN

OSC #1

OSC #2

ORDY

NOTE 2

NOSCR

NOTE 1

CSWIF

USER

CLEAR

CSWHOLD

DS40002002B-page 129

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

Note:ꢀ

1. CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.

2. The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.

Figure 8-7.ꢀClock Switch (CSWHOLD = 1)

Rev. 30-000065A

4/6/2017

OSCCON1

WRITTEN

OSC #1

OSC #2

ORDY

NOSCR

NOTE 1

CSWIF

USER

CLEAR

CSWHOLD

Note:ꢀ

1. CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.

Figure 8-8.ꢀClock Switch Abandoned

Rev. 30-000066A

4/6/2017

OSCCON1

WRITTEN

OSCCON1

WRITTEN

OSC #1

ORDY

NOTE 2

NOSCR

NOTE 1

CSWIF

CSWHOLD

Note:ꢀ

1. CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.

2. ORDY = 0if OSCCON1 does not match OSCCON2; a new switch will begin.

8.4

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The

FSCM is enabled by setting the FCMEN bit in the Configuration Word 1. The FSCM is applicable to all external

Oscillator modes (LP, XT, HS, ECL/M/H and Secondary Oscillator).

DS40002002B-page 130

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

Figure 8-9.ꢀFSCM Block Diagram

Rev. 30-000067A

4/6/2017

ꢏꢇꢟꢠꢗ ꢡꢟꢅꢢꢂꢟꢄ

ꢈꢆꢂꢠꢣ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢏꢇꢟꢠꢗ

ꢎ

ꢔ

ꢈꢉꢊꢋꢌꢍꢎꢏ

ꢍꢜꢠꢢꢇꢇꢆꢂꢟꢄ

ꢐ ꢑꢒ

ꢓ

ꢔ

ꢕꢖ ꢗꢘꢙ

ꢒꢝꢝ ꢘꢙ

Dꢚꢛ ꢞꢜd

Dꢚꢕꢛ uꢜd

ꢎꢆꢞꢧꢇꢃ ꢏꢇꢟꢠꢗ

ꢏꢇꢟꢠꢗ

ꢉꢆꢢꢇꢤꢄꢃ

ꢥꢃꢂꢃꢠꢂꢃꢦ

8.4.1

8.4.2

Fail-Safe Detection

The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The

sample clock is generated by dividing the LFINTOSC by 64. See Figure 8-9. Inside the fail detector block is a latch.

The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each

rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the

external clock goes low.

Fail-Safe Operation

When the external clock fails, the FSCM switches the device clock to the HFINTOSC at 1 MHz clock frequency and

sets the OSFIF bit flag of the PIR3 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE3

register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed

clock. The system clock will continue to be sourced from the internal clock source until the device firmware

successfully restarts the external oscillator and switches back to external operation, by writing to the NOSC and NDIV

bits of the OSCCON1 register.

8.4.3

8.4.4

Fail-Safe Condition Clearing

The Fail-Safe condition is cleared after a Reset, executing a SLEEPinstruction or changing the NOSC and NDIV bits

of the OSCCON1 register. When switching to the external oscillator or external oscillator with PLL, the OST is

restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON1. When

the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The

OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the

OSFIF flag will again be set by hardware.

Reset or Wake-up from Sleep

The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST

is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC Clock modes so

that the FSCM will be active as soon as the Reset or wake-up has completed. Therefore, the device will always be

executing code while the OST is operating when using one of the EC modes.

DS40002002B-page 131

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

Figure 8-10.ꢀFSCM Timing Diagram

Rev. 30-000068A

4/6/2017

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSCFIF

Test

Note:ꢀ The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

DS40002002B-page 132

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.5

Register Summary - OSC

Offset

Name

Bit Pos.

0x00

...

Reserved

0x088C

0x088D

0x088E

0x088F

0x0890

0x0891

0x0892

0x0893

OSCCON1

OSCCON2

OSCCON3

OSCSTAT

OSCEN

7:0

NOSC[2:0]

COSC[2:0]

NDIV[3:0]

CDIV[3:0]

CSWHOLD SOSCPWR

ORDY

LFOR

NOSCR

SOR

EXTOR

HFOR

MFOR

ADOR

PLLR

EXTOEN

HFOEN

MFOEN

LFOEN

SOSCEN

ADOEN

OSCTUNE

OSCFRQ

HFTUN[5:0]

HFFRQ[2:0]

8.6

Register Definitions: Oscillator Control

DS40002002B-page 133

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.6.1

OSCCON1

Name:ꢀ

Offset:ꢀ

OSCCON1

0x88D

Oscillator Control Register1

Bit

7

6

5

4

3

2

1

0

NOSC[2:0]

NDIV[3:0]

Access

Reset

R/W

f

R/W

f

R/W

f

R/W

q

R/W

q

R/W

q

R/W

q

Bits 6:4 – NOSC[2:0]ꢀ New Oscillator Source Request bits^(1,2,3)

The setting requests a source oscillator and PLL combination per Table 8-1.

Table 8-1.ꢀNOSC Bit Settings

NOSC[2:0]

111

Clock Source

EXTOSC⁽⁵⁾

HFINTOSC⁽⁶⁾

LFINTOSC

110

101

100

SOSC

011

Reserved

EXTOSC + 4x PLL⁽⁵⁾

HFINTOSC + 2x PLL⁽⁶⁾

Reserved

010

001

000

Bits 3:0 – NDIV[3:0]ꢀ New Divider Selection Request bits^(2,3,4)

The setting determines the new postscaler division ratio per Table 8-2.

Table 8-2.ꢀNDIV Bit Settings

NDIV[3:0]

1111-1010

1001

Clock Divider

Reserved

512

256

128

64

32

16

8

1000

0111

0110

0101

0100

0011

0010

4

0001

2

0000

1

DS40002002B-page 134

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

Note:ꢀ

1. The default value (f) is determined by the CONFIG1[RSTOSC] Configuration bits.

2. If NOSC is written with a reserved value, the operation is ignored and NOSC is not written.

3. When CONFIG1[CSWEN] = 0, this register is read-only and cannot be changed from the POR value.

4. When NOSC = 110(HFINTOSC 1 MHz), the NDIV bits will default to ‘0010’ upon Reset; for all other NOSC

settings the NDIV bits will default to ‘0000’ upon Reset.

5. EXTOSC configured by CONFIG1[FEXTOSC].

6. HFINTOSC frequency is set with the FRQ bits of the OSCFRQ register.

Related Links

4.7.1 CONFIG1

40.4.3 PLL Specifications

DS40002002B-page 135

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.6.2

OSCCON2

Name:ꢀ

Offset:ꢀ

OSCCON2

0x88E

Oscillator Control Register 2

Bit

7

6

5

4

3

2

1

0

COSC[2:0]

CDIV[3:0]

Access

Reset

RO

n

RO

n

RO

n

RO

n

RO

n

RO

n

RO

n

Bits 6:4 – COSC[2:0]ꢀ Current Oscillator Source Select bits (read-only)^(1,2)

Indicates the current source oscillator and PLL combination, as shown in the following table.

Table 8-3.ꢀCOSC Bit Settings

COSC/NOSC

111

Clock Source

EXTOSC⁽³⁾

HFINTOSC⁽⁴⁾

LFINTOSC

110

101

100

SOSC

011

Reserved

EXTOSC + 4x PLL⁽³⁾

HFINTOSC + 2x PLL⁽⁴⁾

Reserved

010

001

000

Bits 3:0 – CDIV[3:0]ꢀ Current Divider Select bits (read-only)^(1,2)

Indicates the current postscaler division ratio, as shown in the following table.

Table 8-4.ꢀCDIV Bit Settings

CDIV/NDIV

1111-1010

1001

Clock Divider

Reserved

512

256

128

64

32

16

8

1000

0111

0110

0101

0100

0011

0010

4

0001

2

0000

1

DS40002002B-page 136

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

Note:ꢀ

1. The POR value is the value present when user code execution begins.

2. The Reset value (n) is the same as the OSCCON1[NOSC/NDIV] bits.

3. EXTOSC configured by the CONFIG1[FEXTOSC] bits.

4. HFINTOSC frequency is configured with the FRQ bits of the OSCFRQ register.

Related Links

4.7.1 CONFIG1

40.4.3 PLL Specifications

DS40002002B-page 137

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.6.3

OSCCON3

Name:ꢀ

Offset:ꢀ

OSCCON3

0x88F

Oscillator Control Register 3

Bit

7

CSWHOLD

R/W/HC

0

6

SOSCPWR

R/W

5

4

ORDY

RO

3

NOSCR

RO

2

1

0

Access

Reset

0

Bit 7 – CSWHOLDꢀClock Switch Hold bit

Value

1

Description

Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready

0

Clock switch may proceed when the oscillator selected by NOSC is ready; when NOSCR becomes ‘1’,

the switch will occur

Bit 6 – SOSCPWRꢀSecondary Oscillator Power Mode Select bit

Value

Description

1

0

Secondary oscillator operating in High-Power mode

Secondary oscillator operating in Low-Power mode

Bit 4 – ORDYꢀOscillator Ready bit (read-only)

Value

Description

1

0

OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC

A clock switch is in progress

Bit 3 – NOSCRꢀ New Oscillator is Ready bit (read-only)⁽¹⁾

Value

Description

1

0

A clock switch is in progress and the oscillator selected by NOSC indicates a ready condition

A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready

Note:ꢀ

1. If CSWHOLD = 0, the user may not see this bit set because the bit is set for less than one instruction cycle.

DS40002002B-page 138

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.6.4

OSCSTAT

Name:ꢀ

Offset:ꢀ

OSCSTAT

0x890

Oscillator Status Register 1

Bit

7

EXTOR

RO

6

HFOR

RO

q

5

MFOR

RO

4

LFOR

RO

q

3

SOR

RO

q

2

ADOR

RO

1

0

PLLR

RO

q

Access

Reset

q

Bit 7 – EXTORꢀEXTOSC (external) Oscillator Ready bit

Value

Description

1

The oscillator is ready to be used

0

The oscillator is not enabled, or is not yet ready to be used

Bit 6 – HFORꢀHFINTOSC Oscillator Ready bit

Value

Description

1

0

The oscillator is ready to be used

The oscillator is not enabled, or is not yet ready to be used

Bit 5 – MFORꢀMFINTOSC Oscillator Ready bit

Value

Description

1

0

The oscillator is ready to be used

The oscillator is not enabled, or is not yet ready to be used

Bit 4 – LFORꢀLFINTOSC Oscillator Ready bit

Value

Description

1

0

The oscillator is ready to be used

The oscillator is not enabled, or is not yet ready to be used

Bit 3 – SORꢀSecondary (Timer1) Oscillator Ready bit

Value

Description

1

0

The oscillator is ready to be used

The oscillator is not enabled, or is not yet ready to be used

Bit 2 – ADORꢀADC Oscillator Ready bit

Value

Description

1

0

The oscillator is ready to be used

The oscillator is not enabled, or is not yet ready to be used

Bit 0 – PLLRꢀPLL Ready bit

Value

Description

1

The PLL is ready to be used

0

The PLL is not enabled, the required input source is not ready, or the PLL is not locked

DS40002002B-page 139

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.6.5

OSCEN

Name:ꢀ

Offset:ꢀ

OSCEN

0x891

Oscillator Manual Enable Register

Bit

7

EXTOEN

R/W

6

HFOEN

R/W

0

5

MFOEN

R/W

0

4

LFOEN

R/W

0

3

SOSCEN

R/W

2

ADOEN

R/W

0

1

0

Access

Reset

0

Bit 7 – EXTOENꢀExternal Oscillator Manual Request Enable bit

Value

Description

1

0

EXTOSC is explicitly enabled, operating as specified by CONFIG1[FEXTOSC]

EXTOSC is only enabled if requested by a peripheral

Bit 6 – HFOENꢀHFINTOSC Oscillator Manual Request Enable bit

Value

Description

1

0

HFINTOSC is explicitly enabled, operating as specified by OSCFRQ

HFINTOSC is only enabled if requested by a peripheral

Bit 5 – MFOENꢀMFINTOSC (500 kHz/31.25 kHz) Oscillator Manual Request Enable bit (Derived from HFINTOSC)

Value

Description

1

0

MFINTOSC is explicitly enabled

MFINTOSC is only enabled if requested by a peripheral

Bit 4 – LFOENꢀLFINTOSC (31 kHz) Oscillator Manual Request Enable bit

Value

Description

1

0

LFINTOSC is explicitly enabled

LFINTOSC is only enabled if requested by a peripheral

Bit 3 – SOSCENꢀSecondary Oscillator Manual Request Enable bit

Value

Description

1

0

Secondary Oscillator is explicitly enabled, operating as specified by SOSCPWR

Secondary Oscillator is only enabled if requested by a peripheral

Bit 2 – ADOENꢀADC Oscillator Manual Request Enable bit

Value

Description

1

0

ADC oscillator is explicitly enabled

ADC oscillator is only enabled if requested by a peripheral

Related Links

4.7.1 CONFIG1

DS40002002B-page 140

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.6.6

OSCTUNE

Name:ꢀ

Offset:ꢀ

OSCTUNE

0x892

HFINTOSC Tuning Register

Bit

7

6

5

4

3

2

1

0

HFTUN[5:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 5:0 – HFTUN[5:0]ꢀHFINTOSC Frequency Tuning bits

Value

Description

01 1111

00 0000

10 0000

Maximum frequency

Center frequency. Oscillator module is running at the calibrated frequency (default value).

Minimum frequency

DS40002002B-page 141

Datasheet

PIC16(L)F18425/45

OSC - Oscillator Module

8.6.7

OSCFRQ

Name:ꢀ

Offset:ꢀ

OSCFRQ

0x893

HFINTOSC Frequency Selection Register

Bit

7

6

5

4

3

2

1

0

HFFRQ[2:0]

Access

Reset

R/W

q

R/W

q

R/W

q

Bits 2:0 – HFFRQ[2:0]ꢀHFINTOSC Frequency Selection bits

Nominal Frequency

2x PLL Frequency

(MHz)

FRQ[2:0]

(NOSC = 110)

(NOSC = 001)

111

110

101

100

011

010

001

000

Reserved

32

16

12

8

32

24

16

4

2

Reserved

1

Note:ꢀ

1. When RSTOSC = 110(HFINTOSC 1 MHz), the FRQ bits will default to ‘010’ upon Reset; when RSTOSC =

001(HFINTOSC 32 MHz), the FRQ bits will default to ‘101’ upon Reset.

DS40002002B-page 142

Datasheet

PIC16(L)F18425/45

REFCLK - Reference Clock Output Module

9.

REFCLK - Reference Clock Output Module

The reference clock output (REFCLK) module provides the ability to send a clock signal to the clock reference output

pin (CLKR). The reference clock output can also be routed internally as a signal for other peripherals, such as the

Data Signal Modulator (DSM), memory scanner, and timer module.

The reference clock output module has the following features:

•

Selectable Clock Source Using the CLKRCLK Register

Programmable Clock Divider

Selectable Duty Cycle

Figure 9-1.ꢀClock Reference Block Diagram

Rev. 10-000261B

1/23/2019

DIV

Counter Reset

EN

128

111

110

101

100

011

010

001

000

See

DC

RxyPPS

64

32

16

8

CLKRCLK

Register

CLKR

Duty Cycle

PPS

4

2

To Peripherals

EN

CLK

Figure 9-2.ꢀClock Reference Timing

Rev. 10-000264B

1/23/2019

P1

P2

CLKRCLK

EN

CLKR Output

DIV = 001

DC = 10

Duty Cycle

(50%)

CLKR Output

CLKRCLK/2

DIV = 001

DC = 01

Duty Cycle

(25%)

9.1

Clock Source

The clock source of the reference clock peripheral is selected with the CLK bits in the CLKRCLK register. The

available clock sources are listed below:

•

CLCs

DS40002002B-page 143

Datasheet

PIC16(L)F18425/45

REFCLK - Reference Clock Output Module

•

NCO

Secondary oscillator

MFINTOSC

LFINTOSC

F_OSC

9.1.1

Clock Synchronization

The CLKR output signal is ensured to be glitch-free when the EN bit in the CLKRCON register is set to start the

module and enable the CLKR output.

When the reference clock output is disabled, the output signal will be disabled immediately.

Clock dividers and clock duty cycles can be changed while the module is enabled but doing so may cause glitches to

occur on the output. To avoid possible glitches, clock dividers and clock duty cycles should be changed only when the

EN bit is clear.

9.2

Programmable Clock Divider

The module takes the clock input and divides it based on the value of the DIV bits.

The following configurations are available:

•

Base F_OSCvalue

F_OSCdivided by 2

F_OSCdivided by 4

F_OSCdivided by 8

F_OSCdivided by 16

F_OSCdivided by 32

F_OSCdivided by 64

F_OSCdivided by 128

The clock divider values can be changed while the module is enabled. However, in order to prevent glitches on the

output, the DIV bits should only be changed when the module is disabled (EN = 0).

9.3

Selectable Duty Cycle

The DC bits in the CLKRCON register are used to modify the duty cycle of the output clock. A duty cycle of 0%, 25%,

50%, or 75% can be selected for all clock rates when the DIV value is not 000. When DIV = 000the duty cycle

defaults to 50% for all values of DC except 00, in which case the duty cycle is 0% (constant low output).

Important:ꢀ The DC value at Reset is 10. This makes the default duty cycle 50% and not 0%.

Important:ꢀ Clock dividers and clock duty cycles can be changed while the module is enabled but doing

so may cause glitches to occur on the output. To avoid possible glitches, clock dividers and clock duty

cycles should be changed only when the module is disabled (EN = 0).

9.4

Operation in Sleep Mode

The reference clock module continues to operate and provide a signal output in Sleep for all clock source selections

except F_OSC(CLK=0).

DS40002002B-page 144

Datasheet

PIC16(L)F18425/45

REFCLK - Reference Clock Output Module

9.5

Register Summary: Reference CLK

Offset

Name

Bit Pos.

0x00

...

Reserved

0x0894

0x0895

0x0896

CLKRCON

CLKRCLK

7:0

EN

DC[1:0]

DIV[2:0]

CLK[3:0]

9.6

Register Definitions: Reference Clock

Related Links

1.4.2.2 Long Bit Names

DS40002002B-page 145

Datasheet

PIC16(L)F18425/45

REFCLK - Reference Clock Output Module

9.6.1

CLKRCON

Name:ꢀ

Offset:ꢀ

CLKRCON

0x895

Reference Clock Control Register

Bit

7

EN

R/W

0

6

5

4

3

2

1

DIV[2:0]

R/W

0

DC[1:0]

Access

Reset

R/W

1

R/W

0

R/W

0

R/W

0

Bit 7 – EN

Reference Clock Module Enable bit

Value

Description

1

0

Reference clock module enabled

Reference clock module is disabled

Bits 4:3 – DC[1:0]

Reference Clock Duty Cycle bits⁽¹⁾

Value

11

10

01

00

Description

Clock outputs duty cycle of 75%

Clock outputs duty cycle of 50%

Clock outputs duty cycle of 25%

Clock outputs duty cycle of 0%

Bits 2:0 – DIV[2:0]

Reference Clock Divider bits

Value

111

110

101

100

011

010

001

000

Description

Base clock value divided by 128

Base clock value divided by 64

Base clock value divided by 32

Base clock value divided by 16

Base clock value divided by 8

Base clock value divided by 4

Base clock value divided by 2

Base clock value

Note:ꢀ

1. Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.

DS40002002B-page 146

Datasheet

PIC16(L)F18425/45

REFCLK - Reference Clock Output Module

9.6.2

CLKRCLK

Name:ꢀ

Offset:ꢀ

CLKRCLK

0x896

Clock Reference Clock Selection MUX

Bit

7

6

5

4

3

2

1

0

CLK[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 3:0 – CLK[3:0]ꢀCLKR Clock Selection bits

Table 9-1.ꢀCLKR Clock Sources

CLK

1111-1011

1010

Clock Source

Reserved

CLC4 OUT

1001

CLC3 OUT

1000

CLC2 OUT

0111

CLC1 OUT

0110

NCO1 OUT

0101

SOSC

0100

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

LFINTOSC

0011

0010

0001

HFINTOSC (32 MHz)

F_OSC

0000

DS40002002B-page 147

Datasheet

PIC16(L)F18425/45

Resets

10.

Resets

There are multiple ways to reset this device:

•

Power-on Reset (POR)

Brown-out Reset (BOR)

Low-Power Brown-out Reset (LPBOR)

MCLR Reset

WDT Reset

RESETinstruction

Stack Overflow

Stack Underflow

Programming mode exit

To allow V_DDto stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR

event.

A simplified block diagram of the On-Chip Reset Circuit is shown in the block diagram below.

Figure 10-1.ꢀSimplified Block Diagram of On-Chip Reset Circuit

Rev. 10-000006G

4/6/2017

ICSP™ Programming Mode Exit

RESET Instruction

Memory Violation

Stack Underflow

Stack Overflow

VPP/MCLR

MCLRE

WWDT Time-out/

Window violation

Device

Reset

Power-on

Reset

VDD

Brown-out

Reset

Power-up

Timer

LFINTOSC

PWRTS[1:0]

2

LPBOR

Reset

Note:ꢀ See “BOR Operating Conditions” table for BOR active conditions.

Related Links

10.2.3 BOR Controlled by Software

DS40002002B-page 148

Datasheet

PIC16(L)F18425/45

Resets

10.1

10.2

Power-on Reset (POR)

The POR circuit holds the device in Reset until V_DDhas reached an acceptable level for minimum operation. Slow

rising V_DD, fast operating speeds or analog performance may require greater than minimum V_DD. The PWRT, BOR or

MCLR features can be used to extend the start-up period until all device operation conditions have been met.

Related Links

10.2.3 BOR Controlled by Software

Brown-out Reset (BOR)

The BOR circuit holds the device in Reset when V_DDreaches a selectable minimum level. Between the POR and

BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN[1:0] bits in Configuration Word 2.

The four operating modes are:

•

BOR is always ON

BOR is OFF when in Sleep

BOR is controlled by software

BOR is always OFF

Refer to BOR Operating Conditions for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV[1:0] bits in Configuration Word 2.

A V_DDnoise rejection filter prevents the BOR from triggering on small events. If V_DDfalls below V_BORfor a duration

greater than parameter T_BORDC, the device will reset and the BOR bit in the PCON0 register will be cleared,

indicating the Brown-out Reset condition occurred. See Figure 10-2.

10.2.1 BOR is Always ON

When the BOREN bits of Configuration Word 2 are programmed to ‘11’, the BOR is always ON. The device start-up

will be delayed until the BOR is ready and V_DDis higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

10.2.2 BOR is OFF in Sleep

When the BOREN bits of Configuration Word 2 are programmed to ‘10’, the BOR is on, except in Sleep. BOR

protection is not active during Sleep, but device wake-up will be delayed until the BOR can determine that V_DDis

higher than the BOR threshold. The device wake-up will be delayed until the BOR is ready.

10.2.3 BOR Controlled by Software

When the BOREN bits of Configuration Word 2 are programmed to ‘01’, the BOR is controlled by the SBOREN bit.

The device wake from Sleep is not delayed by the BOR ready condition or the V_DDlevel only when the SBOREN bit

is cleared in software and the device is starting up from a non POR/BOR Reset event.

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY

bit.

BOR protection is unchanged by Sleep.

Table 10-1.ꢀBOR Operating Conditions

Instruction Execution upon: Release of POR or Wake-up

BOREN[1:0] SBOREN Device Mode BOR Mode

from Sleep

Waits for release of BOR⁽¹⁾(BORRDY = 1)

11

X

Active

Awake

Sleep

Waits for release of BOR (BORRDY = 1) Waits for BOR

Reset release

10

X

Disabled

DS40002002B-page 149

Datasheet

PIC16(L)F18425/45

Resets

...........continued

Instruction Execution upon: Release of POR or Wake-up

from Sleep

BOREN[1:0] SBOREN Device Mode BOR Mode

1

Waits for BOR Reset release (BORRDY = 1)

X

Active

01

00

0

X

Disabled

Begins immediately (BORRDY = x)

Figure 10-2.ꢀBrown-out Situations

Rev. 30-000092A

4/12/2017

VDD

VBOR

Internal

Reset

(1)

TPWRT

VDD

VBOR

Internal

Reset

< TPWRT

(1)

TPWRT

VDD

VBOR

Internal

Reset

(1)

TPWRT

Note:ꢀ T_PWRTdelay only if PWRTS bit field is programmed to a value different from ‘11’.

10.2.4 BOR is Always OFF

When the BOREN bits of the Configuration Word 2 are programmed to ‘00’, the BOR is always disabled. In the

configuration, setting the SWBOREN bit will have no affect on BOR operations.

10.3

Low-Power Brown-out Reset (LPBOR)

The Low-Power Brown-Out Reset (LPBOR) circuit provides alternative protection against Brown-out conditions.

When V_DDfalls below the LPBOR threshold, the device is held in Reset. When this occurs, the BOR bit of the

PCON0 register is cleared to indicate that a Brown-out Reset occurred. The BOR bit will be cleared when either the

BOR or the LPBOR circuitry detects a BOR condition. The LPBOR feature can be used with or without BOR enabled.

When used while BOR is enabled, the LPBOR can be used as a secondary protection circuit in case the BOR circuit

fails to detect the BOR condition. Additionally, when BOR is enabled except while in Sleep (BOREN[1:0] = 10), the

LPBOR circuit will hold the device in Reset while VDD is lower than the LPBOR threshold, and will also re-arm the

POR. (see 40.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-

Out Reset Specifications for LPBOR Reset voltage levels).

When used without BOR enabled, the LPBOR circuit provides a single Reset trip point with the benefit of reduced

current consumption.

DS40002002B-page 150

Datasheet

PIC16(L)F18425/45

Resets

Figure 10-3.ꢀLPBOR, BOR, POR Relationship

Rev. 30-000091B

6/21/2017

Any Reset

BOR

BOR Event

REARM POR

Event

To PCON

indicator bit

POR

LPBOR

POR Event

LPBOR Event

Reset

logic

10.3.1 Enabling LPBOR

The LPBOR is controlled by the LPBOREN bit of Configuration Word 2. When the device is erased, the LPBOR

module defaults to disabled.

Related Links

4.7.2 CONFIG2

10.3.2 LPBOR Module Output

The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d

together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON0

register and to the power control block.

10.4

MCLR Reset

The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit

of Configuration Word 2 and the LVP bit of Configuration Word 4 (see table below). The RMCLR bit in the PCON0

register will be set to ‘0’ if a MCLR has occurred.

Table 10-2.ꢀMCLR Configuration

MCLRE

LVP

1

MCLR

Enabled

Disabled

x

1

0

10.4.1 MCLR Enabled

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to V_DD

through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.

DS40002002B-page 151

Datasheet

PIC16(L)F18425/45

Resets

Important:ꢀ An internal Reset event (RESETinstruction, BOR, WWDT, POR, STKOVF, STKUNF) does not

drive the MCLR pin low.

Related Links

2.3 Master Clear (MCLR) Pin

10.4.2 MCLR Disabled

When MCLR is disabled, the MCLR becomes input-only and pin functions such as internal weak pull-ups are under

software control.

Related Links

14.3 I/O Priorities

10.5

Windowed Watchdog Timer (WWDT) Reset

The Windowed Watchdog Timer generates a Reset if the firmware does not issue a CLRWDTinstruction within the

time-out period or window set. The TO and PD bits in the STATUS register and the RWDT bit are changed to indicate

a WDT Reset. The WDTWV bit indicates if the WDT Reset has occurred due to a time-out or a window violation.

Related Links

5.8.4 STATUS

11. WWDT - Windowed Watchdog Timer

10.6

10.7

RESET Instruction

A RESETinstruction will cause a device Reset. The RI bit will be set to ‘0’. See Reset Status Bits and Their

Significance for default conditions after a RESETinstruction has occurred.

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits in PCON0 register

indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word 2.

Related Links

4.7.2 CONFIG2

10.8

10.9

Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

Power-up Timer (PWRT)

The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as

long as PWRT is active. The PWRT delay allows additional time for the V_DDto rise to an acceptable level.

The Power-up Timer is controlled by the PWRTS bit field of the Configuration Word 2.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00000607).

DS40002002B-page 152

Datasheet

PIC16(L)F18425/45

Resets

10.10 Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if required for selected oscillator source).

3. MCLR must be released (if enabled).

The total time-out will vary based on oscillator configuration and Power-up Timer configuration.

The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long

enough, the Power-up Timer and oscillator Start-up Timer will expire. Upon bringing MCLR high, the device will begin

execution after ten F_OSCcycles (see Figure 10-4). This is useful for testing purposes or for synchronizing more than

one device operating in parallel.

Figure 10-4.ꢀReset Start-up Sequence

Rev. 30-000093A

4/12/2017

VDD

Internal POR

TPWRT

Power-up Timer

MCLR

TMCLR

Internal RESET

Oscillator Modes

External Crystal

TOST

Oscillator Start-up Timer

Oscillator

FOSC

Internal Oscillator

Oscillator

FOSC

External Clock (EC)

CLKIN

FOSC

Related Links

8. OSC - Oscillator Module

10.11 Memory Execution Violation

A Memory Execution Violation Reset occurs if executing an instruction being fetched from outside the valid execution

area. The different valid execution areas are defined as follows:

DS40002002B-page 153

Datasheet

PIC16(L)F18425/45

Resets

•

Flash Memory: The “Device Sizes and Addresses” table shows the addresses available on the

PIC16(L)F18425/45 devices based on user Flash size. Execution outside this region generates a memory

execution violation.

Storage Area Flash (SAF): If Storage Area Flash (SAF) is enabled , the SAF area is not a valid execution area.

Prefetched instructions that are not executed do not cause memory execution violations. For example, a GOTO

instruction in the last memory location will prefetch from an invalid location; this is not an error. If an instruction from

an invalid location tries to execute, the memory violation is generated immediately, and any concurrent interrupt

requests are ignored. When a memory execution violation is generated, the device is reset and flag MEMV is cleared

in PCON1 to signal the cause. The flag needs to be set in code after a memory execution violation.

Related Links

5.1 Program Memory Organization

5.2.3 Storage Area Flash

5.2.5 Memory Violation

10.12 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of the Reset.

The following tables show the Reset conditions of these registers.

Table 10-3.ꢀReset Status Bits and Their Significance

STOVF STKUNF RWDT RMCLR RI POR BOR TO PD MEMV

Condition

Power-on Reset

0

u

1

u

0

u

1

u

1

u

0

u

1

u

0

u

1

u

0

u

0

u

x

0

u

1

0

x

1

0

1

u

1

u

1

x

0

1

u

0

u

0

u

1

u

1

u

0

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WWDT Reset

WWDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

Memory violation Reset

Table 10-4.ꢀReset Condition for Special Registers

Condition

STATUS

Register

PCON0

Register

PCON1

Register

Program

Counter

0

---1 1000

-uuu uuuu

---1 0uuu

---0 uuuu

0011 110x

0011 11u0

uuuu 0uuu

uuu0 uuuu

---- --1-

---- --u-

---- --1-

---- --u-

Power-on Reset

Brown-out Reset

MCLR Reset during normal operation

MCLR Reset during Sleep

WWDT Time-out Reset

DS40002002B-page 154

Datasheet

PIC16(L)F18425/45

Resets

...........continued

STATUS

Register

PCON0

Register

PCON1

Register

Program

Counter

Condition

---0 0uuu

---u uuuu

---1 0uuu

---u uuuu

-uuu uuuu

uuuu uuuu

uu0u uuuu

uuuu uuuu

uuuu u0uu

1uuu uuuu

u1uu uuuu

uuuu uuuu

---- --u-

---- --0-

WWDT Wake-up from Sleep

PC + 1

0

WWDT Window Violation Reset

Interrupt Wake-up from Sleep

PC + 1⁽¹⁾

0

RESET Instruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

Memory Violation Reset (MEMV = 0)

Legend: u= unchanged, x= unknown, — = unimplemented bit, reads as ‘0’.

Note:ꢀ

1. When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

Related Links

5.8.4 STATUS

DS40002002B-page 155

Datasheet

PIC16(L)F18425/45

Resets

10.13 Register Summary - BOR Control and Power Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x0810

0x0811

0x0812

0x0813

0x0814

BORCON

Reserved

PCON0

7:0

SBOREN

STKOVF

BORRDY

7:0

STKUNF

WDTWV

RWDT

RMCLR

RI

POR

BOR

PCON1

MEMV

10.14 Register Definitions: Power Control

DS40002002B-page 156

Datasheet

PIC16(L)F18425/45

Resets

10.14.1 BORCON

Name:ꢀ

Offset:ꢀ

BORCON

0x811

Brown-out Reset Control Register

Bit

7

SBOREN

R/W

6

5

4

3

2

1

0

BORRDY

Access

Reset

R

q

1

Bit 7 – SBORENꢀSoftware Brown-out Reset Enable bit

Reset States: POR/BOR = 1

All Other Resets = u

Value

Condition

Description

—

1

0

If BOREN≠ 01

If BOREN= 01

SBOREN is read/write, but has no effect on the BOR.

BOR Enabled

BOR Disabled

Bit 0 – BORRDYꢀBrown-out Reset Circuit Ready Status bit

Reset States: POR/BOR = q

All Other Resets = u

Value

Description

1

0

The Brown-out Reset Circuit is active and armed

The Brown-out Reset Circuit is disabled or is warming up

Related Links

4.7.2 CONFIG2

DS40002002B-page 157

Datasheet

PIC16(L)F18425/45

Resets

10.14.2 PCON0

Name:ꢀ

Offset:ꢀ

PCON0

0x813

Power Control Register 0

Bit

7

6

5

4

3

2

1

POR

R/W/HC

0

BOR

R/W/HC

q

STKOVF

R/W/HS

0

STKUNF

R/W/HS

0

WDTWV

R/W/HC

1

RWDT

R/W/HC

1

RMCLR

R/W/HC

1

RI

R/W/HC

1

Access

Reset

Bit 7 – STKOVFꢀStack Overflow Flag bit

Reset States: POR/BOR = 0

All Other Resets = q

Value

Description

1

A Stack Overflow occurred (more CALLs than fit on the stack)

0

A Stack Overflow has not occurred or set to ‘0’ by firmware

Bit 6 – STKUNFꢀStack Underflow Flag bit

Reset States: POR/BOR = 0

All Other Resets = q

Value

Description

1

A Stack Underflow occurred (more RETURNs than CALLs)

0

A Stack Underflow has not occurred or set to ‘0’ by firmware

Bit 5 – WDTWVꢀWatchdog Window Violation Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value

1

Description

A WDT window violation has not occurred or set to ‘1’ by firmware

0

A CLRWDTinstruction was issued when the WDT Reset window was closed (set to ‘0’ in hardware

when a WDT window violation Reset occurs)

Bit 4 – RWDTꢀWDT Reset Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value

Description

1

A WDT overflow/time-out Reset has not occurred or set to ‘1’ by firmware

0

A WDT overflow/time-out Reset has occurred (set to ‘0’ in hardware when a WDT Reset occurs)

Bit 3 – RMCLRꢀ MCLR Reset Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value

Description

1

A MCLR Reset has not occurred or set to ‘1’ by firmware

0

A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)

Bit 2 – RIꢀ RESETInstruction Flag bit

Reset States: POR/BOR = 1

All Other Resets = q

Value

Description

1

A RESETinstruction has not been executed or set to ‘1’ by firmware

0

A RESETinstruction has been executed (set to ‘0’ in hardware upon executing a RESETinstruction)

Bit 1 – PORꢀPower-on Reset Status bit

DS40002002B-page 158

Datasheet

PIC16(L)F18425/45

Resets

Reset States: POR/BOR = 0

All Other Resets = u

Description

No Power-on Reset occurred or set to ‘1’ by firmware

A Power-on Reset occurred (set to ‘0’ in hardware when a Power-on Reset occurs)

Value

1

0

Bit 0 – BORꢀBrown-out Reset Status bit

Reset States: POR/BOR = q

All Other Resets = u

Value

Description

1

No Brown-out Reset occurred or set to ‘1’ by firmware

0

A Brown-out Reset occurred (set to ‘0’ in hardware when a Brown-out Reset occurs)

DS40002002B-page 159

Datasheet

PIC16(L)F18425/45

Resets

10.14.3 PCON1

Name:ꢀ

Offset:ꢀ

PCON1

0x814

Power Control Register 1

Bit

7

6

5

4

3

2

1

0

MEMV

R/W/HC

1

Access

Reset

Bit 1 – MEMVꢀMemory Violation Flag bit

Reset States: POR/BOR = 1

All Other Resets = u

Value

1

0

Description

No Memory Violation Reset occurred or set to ‘1’ by firmware.

A Memory Violation Reset occurred (set to ‘0’ in hardware when a Memory Violation occurs)

DS40002002B-page 160

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

11.

WWDT - Windowed Watchdog Timer

The Watchdog Timer (WDT) is a system timer that generates a Reset if the firmware does not issue a CLRWDT

instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected

events. The Windowed Watchdog Timer (WWDT) differs in that CLRWDTinstructions are only accepted when they are

performed within a specific window during the time-out period.

The WWDT has the following features:

•

Selectable Clock Source

Multiple Operating Modes

– WWDT is always on

– WWDT is off when in Sleep

– WWDT is controlled by software

– WWDT is always off

•

Configurable Time-out Period is from 1 ms to 256s (Nominal)

Configurable Window Size from 12.5% to 100% of the Time-out Period

Multiple Reset Conditions

DS40002002B-page 161

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

Figure 11-1.ꢀWindowed Watchdog Timer Block Diagram

Rev. 10-000 162A

1/2/201 4

WWDT

Armed

WDT

Window

Violation

Window Closed

Comparator

Window

Sizes

CLRWDT

WINDOW

RESET

Reserved

111

110

101

100

011

010

001

000

Reserved

R

Reserved

18-bit Prescale

Counter

E

Reserved

SOSC

MFINTOSC/16

LFINTOSC

CS

PS

R

5-bit

WDT Counter

Overflow

Latch

WDT Time-out

WDTE[1:0] = 01

SEN

WDTE[1:0] = 11

WDTE[1:0] = 10

Sleep

11.1

Independent Clock Source

The WWDT can derive its time base from either the 31 kHz LFINTOSC or 31.25 kHz MFINTOSC internal oscillators,

depending on the value of WDTE bits in the CONFIG3.

If WDTE = 'b1x, then the clock source will be enabled depending on the WDTCCS bits in the CONFIG3.

If WDTE = 'b01, the SEN bit in the WDTCON0 register should be set by software to enable WWDT, and the clock

source is enabled by the WDTCS bits in the WDTCON1 register.

DS40002002B-page 162

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

Time intervals in this chapter are based on a minimum nominal interval of 1 ms. See 40.4.2 Internal Oscillator

Parameters(1) section for LFINTOSC and MFINTOSC tolerances.

Related Links

4.7.3 CONFIG3

40.4.2 Internal Oscillator Parameters(1)

40. Electrical Specifications

11.2

WWDT Operating Modes

The Windowed Watchdog Timer module has four operating modes controlled by the WDTE bits in the CONFIG3. See

Table 11-1.

Table 11-1.ꢀWWDT Operating Modes

WDTE[1:0]

SEN

Device Mode

WWDT Mode

Active

11

X

x

Awake

Active

10

X

Sleep

Disabled

Active

1

0

X

x

01

00

Disabled

11.3

11.4

Time-out Period

If the WDTCPS bits in CONFIG3 are set to 0’b11111, then the WDTPS bits set the time-out period from 1 ms to 256

seconds (nominal). If any value other than the default value is assigned to WDTCPS Configuration bits, then the

timer period will be based on the WDTCPS bits in the CONFIG3 register. After a Reset, the default time-out period is

2s.

Related Links

4.7.3 CONFIG3

Watchdog Window

The Windowed Watchdog Timer has an optional Windowed mode that is controlled by the WDTCWS bits in

Configuration Word 3 and WINDOW bits in the WDTCON1 register. In the Windowed mode, the CLRWDTinstruction

must occur within the allowed window of the WDT period. Any CLRWDTinstruction that occurs outside of this window

will trigger a window violation and will cause a WWDT Reset, similar to a WWDT time-out. See Figure 11-2 for an

example.

The window size is controlled by the Watchdog Timer Window Select (WINDOW) bits in WDTCON1, if WDTCWS bits

in Configuration Word 3 are set to 111.

The WDTTMR bits in the WDTTMR register are used to determine whether the window is open, as defined by the

WINDOW bits.

In the event of a window violation, a Reset will be generated and the WDTWV bit of the PCON0 register will be

cleared. This bit is set by a POR or can be set in firmware.

Related Links

10.14.2 PCON0

DS40002002B-page 163

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

11.5

Clearing the WWDT

The WWDT is cleared when any of the following conditions occur:

•

Any Reset

Valid CLRWDTinstruction is executed

Device enters Sleep

Exit Sleep by Interrupt

WWDT is disabled

Oscillator Start-up Timer (OST) is running

Any write to the WDTCON0 or 11.8.2 WDTCON1 registers

11.5.1

CLRWDT Considerations (Windowed Mode)

When in Windowed mode, the WWDT must be armed before a CLRWDTinstruction will clear the timer. This is

performed by reading the WDTCON0 register. Executing a CLRWDTinstruction without performing such an arming

action will trigger a window violation regardless of whether the window is open or not.

See Table 11-2 for more information.

11.6

Operation During Sleep

When the device enters Sleep, the WWDT is cleared. If the WWDT is enabled during Sleep, the WWDT resumes

counting. When the device exits Sleep, the WWDT is cleared again.

The WWDT remains clear until the Oscillator Start-up Timer (OST) completes, if enabled.

When a WWDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up

and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. The RWDT

bit in the PCON0 register can also be used.

Table 11-2.ꢀWWDT Clearing Conditions

Conditions

WWDT

WDTE = 00

WDTE = 01and SEN = 0

WDTE = 10and enter Sleep

CLRWDT Command

Oscillator Fail Detected

Cleared

Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

Unaffected

Change INTOSC divider (IRCF bits)

DS40002002B-page 164

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

Figure 11-2.ꢀWindow Period and Delay

Rev. 10-000163A

8/15/2016

CLRWDTInstruction

(or other WDT Reset)

Window Period

Window Closed

Window Open

Time-out Event

Window Delay

(window violation can occur)

Related Links

8.2.1.3 Oscillator Start-up Timer (OST)

5.8.4 STATUS

10.14.2 PCON0

5. Memory Organization

DS40002002B-page 165

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

11.7

Register Summary - WDT Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x080B

0x080C

0x080D

0x080E

0x080F

0x0810

WDTCON0

WDTCON1

WDTPSL

7:0

WDTPS[4:0]

SEN

WDTCS[2:0]

WINDOW[2:0]

PSCNTL[7:0]

PSCNTH[7:0]

WDTPSH

WDTTMR

WDTTMR[4:0]

STATE

PSCNT[1:0]

11.8

Register Definitions: Windowed Watchdog Timer Control

DS40002002B-page 166

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

11.8.1

WDTCON0

Name:ꢀ

Offset:ꢀ

WDTCON0

0x80C

Watchdog Timer Control Register 0

Bit

7

6

5

4

3

2

1

0

WDTPS[4:0]

SEN

R/W

0

Access

Reset

R/W

q

R/W

q

R/W

q

R/W

q

R/W

q

Bits 5:1 – WDTPS[4:0]ꢀ Watchdog Timer Prescale Select bits⁽¹⁾

Bit Value = Prescale Rate

Value

Description

11111 to

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

Reserved. Results in minimum interval (1 ms)

1:8388608 (2²³) (Interval 256s nominal)

1:4194304 (2²²) (Interval 128s nominal)

1:2097152 (2²¹) (Interval 64s nominal)

1:1048576 (2²⁰) (Interval 32s nominal)

1:524288 (2¹⁹) (Interval 16s nominal)

1:262144 (2¹⁸) (Interval 8s nominal)

1:131072 (2¹⁷) (Interval 4s nominal)

1:65536 (Interval 2s nominal) (Reset value)

1:32768 (Interval 1s nominal)

1:16384 (Interval 512 ms nominal)

1:8192 (Interval 256 ms nominal)

1:4096 (Interval 128 ms nominal)

1:2048 (Interval 64 ms nominal)

1:1024 (Interval 32 ms nominal)

1:512 (Interval 16 ms nominal)

1:256 (Interval 8 ms nominal)

1:128 (Interval 4 ms nominal)

1:64 (Interval 2 ms nominal)

1:32 (Interval 1 ms nominal)

Bit 0 – SENꢀSoftware Enable/Disable for Watchdog Timer bit

Value

Condition

Description

—

If WDTE = 1x

If WDTE = 01

If WDTE = 00

This bit is ignored

WDT is turned on

WDT is turned off

This bit is ignored

1

0

—

Note:ꢀ

1. Times are approximate. WDT time is based on 31 kHz LFINTOSC.

2. When WDTCPS in CONFIG3 = 11111, the Reset value (q) of WDTPS is ‘01011’. Otherwise, the Reset value

of WDTPS is equal to WDTCPS in CONFIG3.

3. When WDTCPS in CONFIG3L ≠ 11111, these bits are read-only.

DS40002002B-page 167

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

11.8.2

WDTCON1

Name:ꢀ

Offset:ꢀ

WDTCON1

0x80D

Watchdog Timer Control Register 1

Bit

7

6

5

4

3

2

1

0

WDTCS[2:0]

WINDOW[2:0]

Access

Reset

R/W

q

R/W

q

R/W

q

R/W

q

R/W

q

R/W

q

Bits 6:4 – WDTCS[2:0]ꢀWatchdog Timer Clock Select bits

Value

111 to

010

Description

Reserved

001

000

MFINTOSC 31.25 kHz

LFINTOSC 31 kHz

Bits 2:0 – WINDOW[2:0]ꢀWatchdog Timer Window Select bits

WINDOW

111

Window delay Percent of time

Window opening Percent of time

N/A

12.5

25

100

87.5

75

110

101

100

37.5

50

62.5

50

011

010

62.5

75

37.5

25

001

000

87.5

12.5

Note:ꢀ

1. If WDTCCS in CONFIG3 = 111, the Reset value of WDTCS is ‘000’.

2. The Reset value (q) of WINDOW is determined by the value of WDTCWS in the CONFIG3 register.

3. If WDTCCS in CONFIG3 ≠ 111, these bits are read-only.

4. If WDTCWS in CONFIG3 ≠ 111, these bits are read-only.

DS40002002B-page 168

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

11.8.3

WDTPSL

Name:ꢀ

Offset:ꢀ

WDTPSL

0x80E

WWDT Prescale Select Low Register (Read-Only)

Bit

7

6

5

4

3

2

1

0

PSCNTL[7:0]

Access

Reset

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

Bits 7:0 – PSCNTL[7:0]ꢀ Prescale Select Low Byte bits⁽¹⁾

Note:ꢀ

1. The 18-bit WDT prescale value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower two bits of the

WDTTMR registers. PSCNT[17:0] is intended for debug operations and should be read during normal

operation.

DS40002002B-page 169

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

11.8.4

WDTPSH

Name:ꢀ

Offset:ꢀ

WDTPSH

0x80F

WWDT Prescale Select High Register (Read-Only)

Bit

7

6

5

4

3

2

1

0

PSCNTH[7:0]

Access

Reset

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

Bits 7:0 – PSCNTH[7:0]ꢀ Prescale Select High Byte bits⁽¹⁾

Note:ꢀ

1. The 18-bit WDT prescale value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower bits of the

WDTTMR registers. PSCNT[17:0] is intended for debug operations and should be read during normal

operation.

DS40002002B-page 170

Datasheet

PIC16(L)F18425/45

WWDT - Windowed Watchdog Timer

11.8.5

WDTTMR

Name:ꢀ

Offset:ꢀ

WDTTMR

0x810

WDT Timer Register (Read-Only)

Bit

7

6

5

4

3

2

STATE

RO

1

0

WDTTMR[4:0]

PSCNT[1:0]

Access

Reset

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

Bits 7:3 – WDTTMR[4:0]ꢀWatchdog Window Value bits

WINDOW

WDT Window State

Open Percent

Closed

Open

111

110

101

100

011

010

001

000

00000-11111

00100-11111

01000-11111

01100-11111

10000-11111

10100-11111

11000-11111

11100-11111

N/A

100

87.5

75

00000-00011

00000-00111

00000-01011

00000-01111

00000-10011

00000-10111

00000-11011

62.5

50

37.5

25

12.5

Bit 2 – STATEꢀWDT Armed Status bit

Value

Description

1

0

WDT is armed

WDT is not armed

Bits 1:0 – PSCNT[1:0]ꢀ Prescale Select Upper bits⁽¹⁾

Note:ꢀ

1. The 18-bit WDT prescale value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower two bits of the

WDTTMR registers. PSCNT[17:0] is intended for debug operations and should be read during normal

operation.

DS40002002B-page 171

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

12.

Power-Saving Operation Modes

The purpose of the Power-Down modes is to reduce power consumption. There are three Power-Down modes:

•

Doze mode

Idle mode

Sleep mode

12.1

Doze Mode

Doze mode allows for power saving by reducing CPU operation and program memory (PFM) access, without

affecting peripheral operation. Doze mode differs from Sleep mode because the bandgap and system oscillators

continue to operate, while only the CPU and PFM are affected. The reduced execution saves power by eliminating

unnecessary operations within the CPU and memory.

When the Doze Enable bit is set (DOZEN = 1), the CPU executes only one instruction cycle out of every N cycles as

defined by the DOZE bits. For example, if DOZE = 100, the instruction cycle ratio is 1:32. The CPU and memory

execute for one instruction cycle and then lay Idle for 31 instruction cycles. During the unused cycles, the peripherals

continue to operate at the system clock speed.

Related Links

12.5.2 CPUDOZE

12.1.1 Doze Operation

The Doze operation is illustrated in Figure 12-1. For this example:

•

Doze enabled (DOZEN = 1)

DOZE = 001(1:4) ratio

Recover-on-Interrupt enabled (ROI = 1)

As with normal operation, the program memory fetches for the next instruction cycle. The instruction clocks to the

peripherals continue throughout.

DS40002002B-page 172

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

Figure 12-1.ꢀDoze Mode Operation Example

System

Clock

1

2

3

4

1

2

3

4

1

2

3

4

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

CPU Clock

PFM Op’s

Fetch

Exec

Fetch

Exec

Push

0004h

NOP

Fetch

Exec

Fetch

Exec

Exec^(1,2)

Exec

CPU Op’s

Interrupt

Here

(ROI = 1)

Note:ꢀ

1. Multicycle instructions are executed to completion before fetching 0004h.

2. If the prefetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will

resume execution at full speed.

12.1.2 Interrupts During Doze

System behavior if an interrupt occurs during DOZE can be configured using the Recover-on-Interrupt (ROI) bit and

the Doze-on-Exit (DOE) bit. Refer to the table below for details about system behavior in all cases for a transition

from Main to ISR back to Main.

DS40002002B-page 173

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

Table 12-1.ꢀInterrupts During DOZE

Code Flow

DOZEN ROI

Main

ISR⁽¹⁾

Return to Main

Normal operation and

DOE = DOZEN (in

hardware) DOZEN = 0

(unchanged)

Normal

Operation

0

1

0

1

0

1

Normal operation and

DOE = DOZEN (in

hardware) DOZEN = 0

(unchanged)

Normal

Operation

If DOE = 1when return

from interrupt: DOZE

operation and DOZEN = 1

(in hardware)

If DOE = 0when return

from interrupt: Normal

operation and DOZEN = 0

(in hardware)

DOZE operation and

DOE = DOZEN (in

hardware) DOZEN = 1

(unchanged)

DOZE

operation

Normal operation and

DOE = DOZEN (in

hardware) DOZEN = 0

(unchanged)

DOZE

operation

1

Note:ꢀ

1. User software can change DOE bit in the ISR.

12.2

Sleep Mode

Sleep mode is entered by executing the SLEEPinstruction, while the Idle Enable (IDLEN) bit of the CPUDOZE

register is cleared (IDLEN = 0). If the SLEEPinstruction is executed while the IDLEN bit is set (IDLEN = 1), the CPU

will enter the Idle mode.

Upon entering Sleep mode, the following conditions exist:

1. Resets other than WDT are not affected by Sleep mode; WDT will be cleared but keeps running if enabled for

operation during Sleep.

2. The PD bit of the STATUS register is cleared.

3. The TO bit of the STATUS register is set.

4. The CPU and the System clocks are disabled.

5. 31 kHz LFINTOSC, HFINTOSC and SOSC will remain enabled if any peripheral has requested them as a

clock source or if the HFOEN, LFOEN, or SOSCEN bits of the OSCEN register are set.

6. ADC is unaffected if the FRC oscillator is selected. When the ADC clock is something other than FRC, a

SLEEPinstruction causes the present conversion to be aborted and the ADC module is turned off, although

the ADON bit remains active.

7. I/O ports maintain the status they had before SLEEPwas executed (driving high, low, or high-impedance) only

if no peripheral connected to the I/O port is active.

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

•

I/O pins should not be floating

External circuitry sinking current from I/O pins

Internal circuitry sourcing current from I/O pins

Current draw from pins with internal weak pull-ups

Modules using any oscillator

DS40002002B-page 174

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

I/O pins that are high-impedance inputs should be pulled to V_DDor V_SSexternally to avoid switching currents caused

by floating inputs.

Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules.

Related Links

12.2.3 Low-Power Sleep Mode

5.8.4 STATUS

30. FVR - Fixed Voltage Reference

33. DAC - 5-Bit Digital-to-Analog Converter

12.2.1 Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

1. External Reset input on MCLR pin, if enabled.

2. BOR Reset, if enabled.

3. POR Reset.

4. Windowed Watchdog Timer, if enabled.

5. Any external interrupt.

6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information).

The first three events will cause a device Reset. The last three events are considered a continuation of program

execution. To determine whether a device Reset or wake-up event occurred, refer to the “Determining the cause of a

Reset” section.

When the SLEEPinstruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up

through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of

the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP

instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEPinstruction, the device will

then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEPis not

desirable, the user should have a NOPafter the SLEEPinstruction.

The WDT is cleared when the device wakes-up from Sleep, regardless of the source of wake-up.

Related Links

10.12 Determining the Cause of a Reset

12.2.2 Wake-up Using Interrupts

When global interrupts are disabled (GIE cleared) and any interrupt source, with the exception of the clock switch

interrupt, has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:

•

If the interrupt occurs before the execution of a SLEEPinstruction

SLEEPinstruction will execute as a NOP

–

– WDT and WDT prescaler will not be cleared

– TO bit of the STATUS register will not be set

– PD bit of the STATUS register will not be cleared

If the interrupt occurs during or after the execution of a SLEEPinstruction

–

SLEEPinstruction will be completely executed

– Device will immediately wake-up from Sleep

– WDT and WDT prescaler will be cleared

– TO bit of the STATUS register will be set

– PD bit of the STATUS register will be cleared

Even if the flag bits were checked before executing a SLEEPinstruction, it may be possible for flag bits to become set

before the SLEEPinstruction completes. To determine whether a SLEEPinstruction executed, test the PD bit. If the

PD bit is set, the SLEEPinstruction was executed as a NOP.

DS40002002B-page 175

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

Figure 12-2.ꢀWake-Up From Sleep Through Interrupt

Rev. 3000090A

4/12/2017

CLKIN⁽¹⁾

(3)

CLKOUT⁽²⁾

TOST

Interrupt Latency⁽⁴⁾

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Forced NOP

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note:ꢀ

1. External clock. High, Medium, Low mode assumed.

2. CLKOUT is shown here for timing reference.

3. T_OST= 1024 T_OSC. This delay does not apply to EC and INTOSC Oscillator modes.

4. GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will

continue in-line.

12.2.3 Low-Power Sleep Mode

The PIC16(L)F18425/45 devices contain an internal Low Dropout (LDO) voltage regulator, which allows the device

I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its

associated reference circuitry must remain active when the device is in Sleep mode.

The PIC16(L)F18425/45 devices allow the user to optimize the operating current in Sleep, depending on the

application requirements.

Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. Depending on the

configuration of these bits, the LDO and reference circuitry are placed in a low-power state when the device is in

Sleep.

12.2.3.1 Sleep Current vs. Wake-up Time

In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The

device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking-up

from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize.

The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The

Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.

12.2.3.2 Peripheral Usage in Sleep

Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected.

The Low-Power Sleep mode is intended for use with these peripherals:

•

Brown-out Reset (BOR)

Windowed Watchdog Timer (WWDT)

External interrupt pin/Interrupt-On-Change pins

Timer1 (with external clock source)

It is the responsibility of the end user to determine what is acceptable for their application when setting the VREGPM

settings in order to ensure operation in Sleep.

Important:ꢀ The LF devices do not have a configurable Low-Power Sleep mode. LFs are unregulated

devices and are always in the lowest power state when in Sleep, with no wake-up time penalty. These

devices have a lower maximum V_DDand I/O voltage than the F devices.

DS40002002B-page 176

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

Related Links

40. Electrical Specifications

12.3

Idle Mode

When the Idle Enable (IDLEN) bit is clear (IDLEN = 0), the SLEEPinstruction will put the device into full Sleep mode.

When IDLEN is set (IDLEN = 1), the SLEEPinstruction will put the device into Idle mode. In Idle mode, the CPU and

memory operations are halted, but the peripheral clocks continue to run. This mode is similar to Doze mode, except

that in Idle both the CPU and program memory are shut off.

Important:ꢀ Peripherals using F_OSCwill continue running while in Idle (but not in Sleep). Peripherals using

HFINTOSC:LFINTOSC will continue running in both Idle and Sleep.

Important:ꢀ If CLKOUTEN is enabled (CLKOUTEN = 0, Configuration Word 1), the output will continue

operating while in Idle.

12.3.1 Idle and Interrupts

Idle mode ends when an interrupt occurs (even if GIE = 0), but IDLEN is not changed. The device can re-enter Idle

by executing the SLEEPinstruction.

If Recover-on-Interrupt is enabled (ROI = 1), the interrupt that brings the device out of Idle also restores full-speed

CPU execution when Doze is also enabled.

12.3.2 Idle and WWDT

When in Idle, the WWDT Reset is blocked and will instead wake the device. The WWDT wake-up is not an interrupt,

therefore ROI does not apply.

Important:ꢀ The WWDT can bring the device out of Idle, in the same way it brings the device out of Sleep.

The DOZEN bit is not affected.

DS40002002B-page 177

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

12.4

Register Summary - Power Savings Control

Offset

Name

Bit Pos.

0x00

...

Reserved

VREGCON

Reserved

0x0811

0x0812

0x0813

...

7:0

VREGPM

DOZE[2:0]

0x088B

0x088C

CPUDOZE

IDLEN

DOZEN

ROI

DOE

12.5

Register Definitions: Power Savings Control

DS40002002B-page 178

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

12.5.1 VREGCON

Name:ꢀ

Offset:ꢀ

VREGCON

0x812

Voltage Regulator Control Register

Bit

7

6

5

4

3

2

1

VREGPM

R/W

0

Access

Reset

0

Bit 1 – VREGPMꢀVoltage Regulator Power Mode Selection bit

This register is available only for F devices.

Value

Description

1

0

Low-Power Sleep mode enabled in Sleep. Draws lowest current in Sleep, slower wake-up

Normal Power mode enabled in Sleep. Draws higher current in Sleep, faster wake-up

DS40002002B-page 179

Datasheet

PIC16(L)F18425/45

Power-Saving Operation Modes

12.5.2 CPUDOZE

Name:ꢀ

Offset:ꢀ

CPUDOZE

0x88C

Doze and Idle Register

Bit

7

IDLEN

R/W

0

6

DOZEN

R/W/HC/HS

0

5

4

DOE

3

2

1

DOZE[2:0]

R/W

0

ROI

R/W

0

Access

Reset

R/W/HC/HS

0

R/W

0

R/W

0

Bit 7 – IDLENꢀIdle Enable bit

Value

1

0

Description

A SLEEPinstruction places device into Idle mode

A SLEEPinstruction places the device into Sleep mode

Bit 6 – DOZENꢀ Doze Enable bit⁽¹⁾

Value

Description

1

0

Places devices into DOZE setting

Places devices into Normal mode

Bit 5 – ROIꢀ Recover-on-Interrupt bit⁽¹⁾

Value

Description

1

Entering the Interrupt Service Routine (ISR) makes DOZEN = 0

0

Entering the Interrupt Service Routine (ISR) does not change DOZEN

Bit 4 – DOEꢀ Doze-on-Exit bit⁽¹⁾

Value

Description

1

Executing the ISR makes DOZEN = 1

0

Exiting the ISR does not change DOZEN

Bits 2:0 – DOZE[2:0]ꢀRatio of CPU Instruction Cycles to Peripheral Instruction Cycles

Value

111

110

101

100

011

010

001

000

Description

1:256

1:128

1:64

1:32

1:16

1:8

1:4

1:2

Note:ꢀ

1. See the link below for more details.

Related Links

12.1.2 Interrupts During Doze

DS40002002B-page 180

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.

PMD - Peripheral Module Disable

The PIC16(L)F18425/45 devices provide the ability to disable selected modules, placing them into the lowest

possible Power mode.

Important:ꢀ For legacy reasons, all modules are ON by default following any Reset.

13.1

Disabling a Module

A peripheral can be disabled by setting the corresponding peripheral disable bit in the PMDx register. Disabling a

module has the following effects:

•

All clock and control inputs to the module are suspended; there are no logic transitions, and the module will not

function.

•

The module is held in Reset.

– Writing to the SFRs is disabled.

– Reading returns 0x00

•

Analog outputs are disabled; digital outputs read ‘0’

Related Links

16.9.2 xxxPPS

16.9.1 PPSLOCK

13.2

Enabling a Module

When the register bit is cleared, the module is re-enabled and will be in its Reset state; SFR data will reflect the POR

Reset values. Depending on the module, it may take up to one full instruction cycle for the module to become active.

Important:ꢀ There should be no interaction with the module (e.g., writing to registers) for at least one

instruction after it has been re-enabled.

13.3

System Clock Disable

Setting the SYSCMD bit in the 13.5.1 PMD0 register disables the system clock F_OSCdistribution network to the

peripherals. Not all peripherals make use of SYSCLK, so not all peripherals are affected. Refer to the specific

peripheral description to see if it will be affected by this bit or not.

Related Links

13.5.1 PMD0

DS40002002B-page 181

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.4

Register Summary - PMD

Offset

Name

Bit Pos.

0x00

...

Reserved

0x0795

0x0796

0x0797

0x0798

0x0799

0x079A

0x079B

0x079C

0x079D

PMD0

PMD1

PMD2

PMD3

PMD4

PMD5

PMD6

PMD7

7:0

SYSCMD

NCO1MD

FVRMD

NVMMD

CLKRMD

TMR1MD

IOCMD

TMR6MD

TMR5MD

TMR4MD

TMR3MD

CCP4MD

CLC3MD

TMR2MD

TMR0MD

DAC1MD

PWM7MD

CWG2MD

ADCMD

PWM6MD

CWG1MD

C2MD

C1MD

ZCDMD

CCP3MD

CCP2MD

CCP1MD

UART1MD

CLC4MD

MSSP2MD

CLC1MD

MSSP1MD

DSM1MD

SMT1MD

CLC2MD

13.5

Register Definitions: Peripheral Module Disable

DS40002002B-page 182

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.5.1 PMD0

Name:ꢀ

Offset:ꢀ

PMD0

0x796

PMD Control Register 0

Bit

7

SYSCMD

R/W

6

FVRMD

R/W

0

5

4

3

2

NVMMD

R/W

0

1

CLKRMD

R/W

0

IOCMD

R/W

0

Access

Reset

0

Bit 7 – SYSCMDꢀDisable Peripheral System Clock Network bit

Disables the System clock network

Value

Description

1

System clock network disabled (F_OSC

)

0

System clock network enabled

Bit 6 – FVRMDꢀDisable Fixed Voltage Reference bit

Value

Description

1

0

FVR module disabled

FVR module enabled

Bit 2 – NVMMDꢀ NVM Module Disable bit⁽¹⁾

Disables the NVM module

Value

Description

1

All Memory reading and writing is disabled; NVMCON registers cannot be written; FSR access to these

locations returns zero.

NVM module enabled

0

Bit 1 – CLKRMDꢀDisable Clock Reference bit

Value

Description

1

0

CLKR module disabled

CLKR module enabled

Bit 0 – IOCMDꢀDisable Interrupt-on-Change bit, All Ports

Value

Description

1

0

IOC module(s) disabled

IOC module(s) enabled

Note:ꢀ

1. When enabling NVM, a delay of up to 1 μs may be required before accessing data.

Related Links

13.3 System Clock Disable

DS40002002B-page 183

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.5.2 PMD1

Name:ꢀ

Offset:ꢀ

PMD1

0x797

PMD Control Register 1

Bit

7

6

TMR6MD

R/W

5

TMR5MD

R/W

4

TMR4MD

R/W

3

TMR3MD

R/W

2

TMR2MD

R/W

1

TMR1MD

R/W

0

TMR0MD

R/W

Access

Reset

0

Bits 0, 1, 2, 3, 4, 5, 6 – TMRnMDꢀDisable Timer n bit

Value

Description

1

0

TMRn module disabled

TMRn module enabled

DS40002002B-page 184

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.5.3 PMD2

Name:ꢀ

Offset:ꢀ

PMD2

0x798

PMD Control Register 2

Bit

7

NCO1MD

R/W

6

5

4

3

2

1

0

Access

Reset

0

Bit 7 – NCO1MDꢀDisable Numerically Control Oscillator bit

Value

Description

1

0

NCO1 module disabled

NCO1 module enabled

DS40002002B-page 185

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.5.4 PMD3

Name:ꢀ

Offset:ꢀ

PMD3

0x799

PMD Control Register 3

Bit

7

6

DAC1MD

R/W

5

ADCMD

R/W

0

4

3

2

C2MD

R/W

0

1

C1MD

R/W

0

ZCDMD

R/W

0

Access

Reset

0

Bit 6 – DAC1MDꢀDisable DAC1 bit

Value

Description

1

0

DAC module disabled

DAC module enabled

Bit 5 – ADCMDꢀDisable ADC bit

Value

Description

1

0

ADC module disabled

ADC module enabled

Bit 2 – C2MDꢀDisable Comparator C2 bit

Value

Description

1

0

C2 module disabled

C2 module enabled

Bit 1 – C1MDꢀDisable Comparator C1 bit

Value

Description

1

0

C1 module disabled

C1 module enabled

Bit 0 – ZCDMDꢀ Disable Zero-Cross Detect module bit

Value

Description

1

0

ZCD module disabled

ZCD module enabled

DS40002002B-page 186

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.5.5 PMD4

Name:ꢀ

Offset:ꢀ

PMD4

0x79A

PMD Control Register 4

Bit

7

6

PWM7MD

R/W

5

PWM6MD

R/W

4

3

CCP4MD

R/W

2

CCP3MD

R/W

1

CCP2MD

R/W

0

CCP1MD

R/W

Access

Reset

0

Bit 6 – PWM7MDꢀDisable Pulse-Width Modulator PWM7 bit

Value

Description

1

0

PWM7 module disabled

PWM7 module enabled

Bit 5 – PWM6MDꢀDisable Pulse-Width Modulator PWM6 bit

Value

Description

1

0

PWM6 module disabled

PWM6 module enabled

Bit 3 – CCP4MDꢀDisable Pulse-Width Modulator CCP4 bit

Value

Description

1

0

CCP4 module disabled

CCP4 module enabled

Bit 2 – CCP3MDꢀDisable Pulse-Width Modulator CCP3 bit

Value

Description

1

0

CCP3 module disabled

CCP3 module enabled

Bit 1 – CCP2MDꢀDisable Pulse-Width Modulator CCP2 bit

Value

Description

1

0

CCP2 module disabled

CCP2 module enabled

Bit 0 – CCP1MDꢀDisable Pulse-Width Modulator CCP1 bit

Value

Description

1

0

CCP1 module disabled

CCP1 module enabled

DS40002002B-page 187

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.5.6 PMD5

Name:ꢀ

Offset:ꢀ

PMD5

0x79B

PMD Control Register 5

Bit

7

6

CWG2MD

R/W

5

CWG1MD

R/W

4

3

2

1

0

Access

Reset

0

Bit 6 – CWG2MDꢀDisable CWG2 bit

Value

Description

1

0

CWG2 module disabled

CWG2 module enabled

Bit 5 – CWG1MDꢀDisable CWG1 bit

Value

Description

1

0

CWG1 module disabled

CWG1 module enabled

DS40002002B-page 188

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.5.7 PMD6

Name:ꢀ

Offset:ꢀ

PMD6

0x79C

PMD Control Register 6

Bit

7

6

5

4

UART1MD

R/W

3

2

1

MSSP2MD

R/W

0

MSSP1MD

R/W

Access

Reset

0

Bit 4 – UART1MDꢀDisable EUSART1 bit

Value

Description

1

0

EUSART1 module disabled

EUSART1 module enabled

Bit 1 – MSSP2MDꢀDisable MSSP2 bit

Value

Description

1

0

MSSP2 module disabled

MSSP2 module enabled

Bit 0 – MSSP1MDꢀDisable MSSP1 bit

Value

Description

1

0

MSSP1 module disabled

MSSP1 module enabled

DS40002002B-page 189

Datasheet

PIC16(L)F18425/45

PMD - Peripheral Module Disable

13.5.8 PMD7

Name:ꢀ

Offset:ꢀ

PMD7

0x79D

PMD Control Register 7

Bit

7

6

5

SMT1MD

R/W

4

CLC4MD

R/W

3

CLC3MD

R/W

2

CLC2MD

R/W

1

CLC1MD

R/W

0

DSM1MD

R/W

Access

Reset

0

Bit 5 – SMT1MDꢀDisable Signal Measurement Timer1 bit

Value

Description

1

0

SMT1 module disabled

SMT1 module enabled

Bits 1, 2, 3, 4 – CLCnMDꢀDisable CLCn bit

Value

Description

1

0

CLCn module disabled

CLCn module enabled

Bit 0 – DSM1MDꢀDisable Data Signal Modulator 1 bit

Value

Description

1

0

DSM1 module disabled

DSM1 module enabled

DS40002002B-page 190

Datasheet

PIC16(L)F18425/45

I/O Ports

14.

I/O Ports

14.1

PORT Availability

Table 14-1.ꢀPORT Availability Per Device

PORTs

PORTA

PORTB

PORTC

PORT Description

PIC16(L)F18425

PIC16(L)F18445

6-bit wide, bidirectional port.

4-bit wide, bidirectional port.

6/8-bit wide, bidirectional port.

•

14.2

I/O Ports Description

Each port has standard registers for its operation. These registers are:

•

PORTx registers (reads the levels on the pins of the device)

LATx registers (output latch)

TRISx registers (data direction)

ANSELx registers (analog select)

WPUx registers (weak pull-up)

INLVLx (input level control)

SLRCONx registers (slew rate control)

ODCONx registers (open-drain control)

Most PORT pins share functions with device peripherals, both analog and digital. In general, when a peripheral is

enabled on a PORT pin, that pin cannot be used as a general purpose output; however, the pin can still be read.

The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving.

A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of

the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the

actual I/O pin value.

Ports that support analog inputs have an associated ANSELx register. When an ANSELx bit is set, the digital input

buffer associated with that bit is disabled.

Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing

excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other

peripherals, is shown in the following figure:

DS40002002B-page 191

Datasheet

PIC16(L)F18425/45

I/O Ports

Figure 14-1.ꢀGeneric I/O Port Operation

Rev. 10-000052A

7/30/2013

Read LATx

TRISx

D

Q

Write LATx

Write PORTx

VDD

CK

Data Register

Data bus

I/O pin

Read PORTx

To digital peripherals

ANSELx

To analog peripherals

VSS

14.3

I/O Priorities

Each pin defaults to the PORT data latch after Reset. Other functions are selected with the peripheral pin select logic.

See “Peripheral Pin Select (PPS) Module” for more information.

Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These

inputs are active when the I/O pin is set for Analog mode using the ANSELx register. Digital output functions may

continue to control the pin when it is in Analog mode.

Analog outputs, when enabled, take priority over digital outputs and force the digital output driver into a high-

impedance state.

The pin function priorities are as follows:

1. Configuration bits

2. Analog outputs (disable the input buffers)

3. Analog inputs

4. Port inputs and outputs from PPS

Related Links

16. PPS - Peripheral Pin Select Module

14.4

PORTx Registers

In this section the generic names such as PORTx, LATx, TRISx, etc. can be associated with PORTA, PORTB,

PORTC, etc, depending on availability per device (see related link below).

Related Links

14.1 PORT Availability

DS40002002B-page 192

Datasheet

PIC16(L)F18425/45

I/O Ports

14.4.1 Data Register

PORTx is a bidirectional port, and its corresponding data direction register is TRISx. Setting a TRISx bit (‘1’) will

make the corresponding PORTx pin an input (i.e., disable the output driver). Clearing a TRISx bit (‘0’) will make the

corresponding PORTx pin an output (i.e., it enables output driver and puts the contents of the output latch on the

selected pin). The example below shows how to initialize PORTA.

Reading the PORTx register reads the status of the pins, whereas writing to it will write to the PORT latch. All write

operations are read-modify-write operations. Therefore, a write to a port implies that the PORT pins are read, this

value is modified and then written to the PORT data latch (LATx).

The PORT data latch LATx holds the output port data and contains the latest value of a LATx or PORTx write. The

examples below show how to initialize PORTA.

Example 14-1.ꢀInitializing PORTA in assembly

; This code example illustrates initializing the PORTA register.

; The other ports are initialized in the same manner.

BANKSEL

CLRF

BANKSEL

CLRF

BANKSEL

CLRF

BANKSEL

MOVLW

MOVWF

PORTA

LATA

;

;Init PORTA

;Data Latch

;

;digital I/O

;

LATA

ANSELA

TRISA

B'00111000' ;Set RA[5:3] as inputs

TRISA ;and set RA[2:0] as outputs

Example 14-2.ꢀInitializing PORTA in C

// This code example illustrates initializing the PORTA register.

// The other ports are initialized in the same manner.

PORTA = 0x00;

LATA = 0x00;

ANSELA = 0x00;

TRISA = 0x38;

// Clear PORTA

// Clear Data Latch

// Enable digital drivers

// Set RA[5:3] as inputs and set others as outputs

Related Links

14.6.1 PORTA

14.6.4 TRISA

14.6.7 LATA

14.4.2 Direction Control

The TRISx register controls the PORTx pin output drivers, even when they are being used as analog inputs. The user

should ensure the bits in the TRISx register are maintained set when using them as analog inputs. I/O pins

configured as analog inputs always read ‘0’.

14.4.3 Open-Drain Control

The ODCONx register controls the open-drain feature of the port. Open-drain operation is independently selected for

each pin. When an ODCONx bit is set, the corresponding port output becomes an open-drain driver capable of

sinking current only. When an ODCONx bit is cleared, the corresponding port output pin is the standard push-pull

drive capable of sourcing and sinking current.

Important:ꢀ It is not necessary to set open-drain control when using the pin for I²C; the I²C module

controls the pin and makes the pin open-drain.

DS40002002B-page 193

Datasheet

PIC16(L)F18425/45

I/O Ports

14.4.4 Slew Rate Control

The SLRCONx register controls the slew rate option for each PORT pin. Slew rate for each port pin can be controlled

independently. When an SLRCONx bit is set, the corresponding PORT pin drive is slew rate limited. When an

SLRCONx bit is cleared, The corresponding PORT pin drive slews at the maximum rate possible.

14.4.5 Input Threshold Control

The INLVLx register controls the input voltage threshold for each of the available PORTx input pins. A selection

between the Schmitt Trigger CMOS or the TTL compatible thresholds is available. The input threshold is important in

determining the value of a read of the PORTx register and also the level at which an interrupt-on-change occurs, if

that feature is enabled.

Important:ꢀ Changing the input threshold selection should be performed while all peripheral modules are

disabled. Changing the threshold level during the time a module is active may inadvertently generate a

transition associated with an input pin, regardless of the actual voltage level on that pin.

14.4.6 Analog Control

The ANSELx register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELx bit

high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly.

The state of the ANSELx bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still

operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing

READ-MODIFY-WRITEinstructions on the affected port.

Important:ꢀ The ANSELx bits default to the Analog mode after Reset. To use any pins as digital general

purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software.

14.4.7 Weak Pull-up Control

The WPUx register controls the individual weak pull-ups for each PORT pin.

14.4.8 PORTx Functions and Output Priorities

Each PORTx pin is multiplexed with other functions.

Each pin defaults to the PORT latch data after Reset. Other output functions are selected with the peripheral pin

select logic, or by enabling an analog output, such as the DAC. See the link below for more information.

Analog input functions, such as ADC and comparator inputs are not shown in the peripheral pin select lists. Digital

output functions may continue to control the pin when it is in Analog mode.

Related Links

16. PPS - Peripheral Pin Select Module

14.4.9 MCLR/V_PPPin

The MCLR/V_PPpin is an input-only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as

a PORT pin (MCLRE = 0), it functions as a digital input-only pin; as such, it does not have TRISx and LATx bits

associated with its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, the

MCLR/V_PPpin also functions as the programming voltage input pin during high voltage programming.

The MCLR/V_PPpin is a read-only bit and will read ‘1’ when MCLRE = 1(i.e., Master Clear enabled).

DS40002002B-page 194

Datasheet

PIC16(L)F18425/45

I/O Ports

Important:ꢀ On a Power-on Reset, the MCLR/V_PPpin is enabled as a digital input-only if Master Clear

functionality is disabled.

The MCLR/V_PPpin has an individually controlled internal weak pull-up. When set, the corresponding WPU bit

enables the pull-up. When the MCLR/V_PPpin is configured as MCLR, (MCLRE = 1and, LVP = 0in the Configuration

Words), or configured for Low-Voltage Programming, (MCLRE = x and LVP = 1), the pull-up is always enabled and

the WPU bit has no effect.

DS40002002B-page 195

Datasheet

PIC16(L)F18425/45

I/O Ports

14.5

Register Summary - Input/Output

Offset

Name

Bit Pos.

0x00

...

Reserved

0x0B

0x0C

PORTA

PORTB

PORTC

7:0

RA5

RB5

RC5

RA4

RB4

RC4

RA3

RC3

RA2

RC2

RA1

RC1

RA0

RC0

0x0D

RB7

RC7

RB6

RC6

0x0E

0x0F

...

Reserved

0x11

0x12

TRISA

TRISB

TRISC

7:0

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

0x13

TRISB7

TRISC7

TRISB6

TRISC6

0x14

TRISC3

LATC3

0x15

...

Reserved

0x17

0x18

LATA

LATB

LATC

7:0

LATA5

LATB5

LATC5

LATA4

LATB4

LATC4

LATA2

LATC2

LATA1

LATC1

LATA0

LATC0

0x19

LATB7

LATC7

LATB6

LATC6

0x1A

0x1B

...

Reserved

0x1F37

0x1F38

0x1F39

0x1F3A

0x1F3B

0x1F3C

0x1F3D

...

ANSELA

WPUA

7:0

ANSELA5

WPUA5

ODCA5

SLRA5

ANSELA4

WPUA4

ODCA4

SLRA4

ANSELA2

WPUA2

ODCA2

SLRA2

ANSELA1

WPUA1

ODCA1

SLRA1

ANSELA0

WPUA0

ODCA0

SLRA0

WPUA3

ODCONA

SLRCONA

INLVLA

INLVLA5

INLVLA4

INLVLA3

INLVLA2

INLVLA1

INLVLA0

Reserved

0x1F42

0x1F43

0x1F44

0x1F45

0x1F46

0x1F47

0x1F48

...

ANSELB

WPUB

7:0

ANSELB7

WPUB7

ODCB7

SLRB7

ANSELB6

WPUB6

ODCB6

SLRB6

ANSELB5

WPUB5

ODCB5

SLRB5

ANSELB4

WPUB4

ODCB4

SLRB4

ODCONB

SLRCONB

INLVLB

INLVLB7

INLVLB6

INLVLB5

INLVLB4

Reserved

0x1F4D

0x1F4E

0x1F4F

0x1F50

0x1F51

0x1F52

ANSELC

WPUC

7:0

ANSELC7

WPUC7

ODCC7

SLRC7

ANSELC6

WPUC6

ODCC6

SLRC6

ANSELC5

WPUC5

ODCC5

SLRC5

ANSELC4

WPUC4

ODCC4

SLRC4

ANSELC3

WPUC3

ODCC3

SLRC3

ANSELC2

WPUC2

ODCC2

SLRC2

ANSELC1

WPUC1

ODCC1

SLRC1

ANSELC0

WPUC0

ODCC0

SLRC0

ODCONC

SLRCONC

INLVLC

INLVLC7

INLVLC6

INLVLC5

INLVLC4

INLVLC3

INLVLC2

INLVLC1

INLVLC0

14.6

Register Definitions: Port Control

DS40002002B-page 196

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.1 PORTA

Name:ꢀ

Offset:ꢀ

PORTA

0x00C

PORTA Register

Bit

7

6

5

4

3

2

1

0

RA5

R/W

x

RA4

R/W

x

RA3

R/W

x

RA2

R/W

x

RA1

R/W

x

RA0

R/W

x

Access

Reset

Bits 0, 1, 2, 3, 4, 5 – RAnꢀPort I/O Value

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value

Description

1

0

PORT pin is ≥ V_IH

PORT pin is ≤ V_IL

Note:ꢀ

•

Writes to PORTA are actually written to the corresponding LATA register.

Reads from PORTA register return actual I/O pin values.

•

Bits RA0, RA1 and RA3 are read-only when DEBUG is enabled, and will read ‘0’.

Bit RA3 will read ‘1’ when MCLRE = 1(master clear enabled) and ‘0’ when DEBUG is enabled.

DS40002002B-page 197

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.2 PORTB

Name:ꢀ

Offset:ꢀ

PORTB

0x00D

PORTB Register

Bit

7

6

5

4

3

2

1

0

RB7

R/W

x

RB6

R/W

x

RB5

R/W

x

RB4

R/W

x

Access

Reset

Bits 4, 5, 6, 7 – RBnꢀPort I/O Value bits

Reset States: POR/BOR = xxxx

All Other Resets = uuuu

Value

Description

1

0

PORT pin is ≥ V_IH

PORT pin is ≤ V_IL

Note:ꢀ Writes to PORTB are actually written to the corresponding LATB register.

Reads from PORTB register return actual I/O pin values.

DS40002002B-page 198

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.3 PORTC

Name:ꢀ

Offset:ꢀ

PORTC

0x00E

PORTC Register

Bit

7

6

5

4

3

2

1

0

RC7

R/W

x

RC6

R/W

x

RC5

R/W

x

RC4

R/W

x

RC3

R/W

x

RC2

R/W

x

RC1

R/W

x

RC0

R/W

x

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – RCnꢀPort I/O Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Value

Description

1

0

PORT pin is ≥ V_IH

PORT pin is ≤ V_IL

Note:ꢀ

1. Writes to PORTC are actually written to the corresponding LATC register.

Reads from PORTC register return actual I/O pin values.

2. Bits RC6 and RC7 available on 20-pin or higher pin count devices only; Bits unimplemented for lower pin

count devices.

DS40002002B-page 199

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.4 TRISA

Name:ꢀ

Offset:ꢀ

TRISA

0x012

Tri-State Control Register

Bit

7

6

5

TRISA5

R/W

1

4

TRISA4

R/W

1

3

2

TRISA2

R/W

1

TRISA1

R/W

1

0

TRISA0

R/W

1

Access

Reset

RO

1

Bits 4, 5 – TRISAxꢀTRISA Port I/O Tri-state Control bits

Value

Description

1

0

PORTA pin configured as an input (tri-stated)

PORTA pin configured as an output

Bits 0, 1, 2 – TRISAnꢀTRISA Port I/O Tri-state Control bits

Value

Description

1

0

PORTA pin configured as an input (tri-stated)

PORTA pin configured as an output

Note:ꢀ Bits TRISA0 and TRISA1 are read-only when DEBUG is enabled, and will read ‘1’.

DS40002002B-page 200

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.5 TRISB

Name:ꢀ

Offset:ꢀ

TRISB

0x013

Tri-State Control Register

Bit

7

TRISB7

R/W

1

6

TRISB6

R/W

1

5

TRISB5

R/W

1

4

TRISB4

R/W

1

3

2

1

0

Access

Reset

Bits 4, 5, 6, 7 – TRISBnꢀTRISB Port I/O Tri-state Control bits

Value

Description

1

0

PORTB pin configured as an input (tri-stated)

PORTB pin configured as an output

DS40002002B-page 201

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.6 TRISC

Name:ꢀ

Offset:ꢀ

TRISC

0x014

Tri-State Control Register

Bit

7

TRISC7

R/W

1

6

TRISC6

R/W

1

5

TRISC5

R/W

1

4

TRISC4

R/W

1

3

TRISC3

R/W

1

2

TRISC2

R/W

1

TRISC1

R/W

1

0

TRISC0

R/W

1

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISCnꢀTRISC Port I/O Tri-state Control bits

Value

Description

1

0

PORTC pin configured as an input (tri-stated)

PORTC pin configured as an output

Note:ꢀ Bits TRISC6 and TRISC7 available on 20-pin or higher pin count devices only; Bits unimplemented for lower

pin count devices.

DS40002002B-page 202

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.7 LATA

Name:ꢀ

Offset:ꢀ

LATA

0x018

Output Latch Register

Bit

7

6

5

LATA5

R/W

x

4

LATA4

R/W

x

3

2

LATA2

R/W

x

1

LATA1

R/W

x

0

LATA0

R/W

x

Access

Reset

RO

1

Bits 4, 5 – LATAnꢀOutput Latch A Value bits

Reset States: POR/BOR = xx

All Other Resets = uu

Bits 0, 1, 2 – LATAnꢀOutput Latch A Value bits

Reset States: POR/BOR = xxx

All Other Resets = uuu

Note:ꢀ Writes to LATA are equivalent with writes to the corresponding PORTA register. Reads from LATA register

return register values, not I/O pin values.

DS40002002B-page 203

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.8 LATB

Name:ꢀ

Offset:ꢀ

LATB

0x019

Output Latch Register

Bit

7

LATB7

R/W

x

6

5

LATB5

R/W

x

4

LATB4

R/W

x

3

2

1

0

LATB6

R/W

x

Access

Reset

Bits 4, 5, 6, 7 – LATBnꢀOutput Latch B Value bits

Reset States: POR/BOR = xxxx

All Other Resets = uuuuu

Note:ꢀ Writes to LATB are equivalent with writes to the corresponding PORTB register. Reads from LATB register

return register values, not I/O pin values.

DS40002002B-page 204

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.9 LATC

Name:ꢀ

Offset:ꢀ

LATC

0x01A

Output Latch Register

Bit

7

LATC7

R/W

x

6

5

LATC5

R/W

x

4

LATC4

R/W

x

3

LATC3

R/W

x

2

LATC2

R/W

x

1

LATC1

R/W

x

0

LATC0

R/W

x

LATC6

R/W

x

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – LATCnꢀOutput Latch C Value bits

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuuu

Note:ꢀ

1. Writes to LATC are equivalent with writes to the corresponding PORTC register. Reads from LATC register

return register values, not I/O pin values.

2. Bits LATC6 and LATC7 available on 20-pin or higher pin count devices only; Bits unimplemented for lower pin

count devices.

DS40002002B-page 205

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.10 ANSELA

Name:ꢀ

Offset:ꢀ

ANSELA

0x1F38

Analog Select Register

Bit

7

6

5

ANSELA5

R/W

4

ANSELA4

R/W

3

2

ANSELA2

R/W

1

ANSELA1

R/W

0

ANSELA0

R/W

Access

Reset

1

Bits 4, 5 – ANSELAnꢀAnalog Select on RA Pins

Value

Description

1

0

Analog input. Pin is assigned as analog input. Digital input buffer disabled.

Digital I/O. Pin is assigned to port or digital special function.

Bits 0, 1, 2 – ANSELAnꢀAnalog Select on RA Pins

Value

Description

1

0

Analog input. Pin is assigned as analog input. Digital input buffer disabled.

Digital I/O. Pin is assigned to port or digital special function.

Note:ꢀ When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

DS40002002B-page 206

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.11 ANSELB

Name:ꢀ

Offset:ꢀ

ANSELB

0x1F43

Analog Select Register

Bit

7

ANSELB7

R/W

6

ANSELB6

R/W

5

ANSELB5

R/W

4

ANSELB4

R/W

3

2

1

0

Access

Reset

1

Bits 4, 5, 6, 7 – ANSELBnꢀAnalog Select on RB Pins

Value

Description

1

0

Analog input. Pin is assigned as analog input. Digital input buffer disabled.

Digital I/O. Pin is assigned to port or digital special function.

Note:ꢀ When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

DS40002002B-page 207

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.12 ANSELC

Name:ꢀ

Offset:ꢀ

ANSELC

0x1F4E

Analog Select Register

Bit

7

ANSELC7

R/W

6

ANSELC6

R/W

5

ANSELC5

R/W

4

ANSELC4

R/W

3

ANSELC3

R/W

2

ANSELC2

R/W

1

ANSELC1

R/W

0

ANSELC0

R/W

Access

Reset

1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ANSELCnꢀAnalog Select on RC Pins

Value

Description

1

0

Analog input. Pin is assigned as analog input. Digital input buffer disabled.

Digital I/O. Pin is assigned to port or digital special function.

Note:ꢀ

1. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

2. Bits ANSC6 and ANSC7 available on 20-pin or higher pin count devices only; Bits unimplemented for lower pin

count devices.

DS40002002B-page 208

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.13 WPUA

Name:ꢀ

Offset:ꢀ

WPUA

0x1F39

Weak Pull-up Register

Bit

7

6

5

WPUA5

R/W

0

4

WPUA4

R/W

0

3

WPUA3

R/W

0

2

WPUA2

R/W

0

1

WPUA1

R/W

0

WPUA0

R/W

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5 – WPUAnꢀWeak Pull-up PORTA Control

Value

Description

1

0

Weak Pull-up enabled

Weak Pull-up disabled

Note:ꢀ

1. If MCLRE = 1, the weak pull-up in RA3 is always enabled; bit WPUA3 will read as ‘1’.

2. The weak pull-up device is automatically disabled if the pin is configured as an output.

DS40002002B-page 209

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.14 WPUB

Name:ꢀ

Offset:ꢀ

WPUB

0x1F44

Weak Pull-up Register

Bit

7

WPUB7

R/W

0

6

WPUB6

R/W

0

5

WPUB5

R/W

0

4

WPUB4

R/W

0

3

2

1

0

Access

Reset

Bits 4, 5, 6, 7 – WPUBnꢀWeak Pull-up PORTB Control bits

Value

Description

1

0

Weak Pull-up enabled

Weak Pull-up disabled

DS40002002B-page 210

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.15 WPUC

Name:ꢀ

Offset:ꢀ

WPUC

0x1F4F

Weak Pull-up Register

Bit

7

WPUC7

R/W

0

6

WPUC6

R/W

0

5

WPUC5

R/W

0

4

WPUC4

R/W

0

3

WPUC3

R/W

0

2

WPUC2

R/W

0

1

WPUC1

R/W

0

WPUC0

R/W

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – WPUCnꢀWeak Pull-up PORTC Control bits

Value

Description

1

0

Weak Pull-up enabled

Weak Pull-up disabled

Note:ꢀ Bits WPUC6 and WPUC7 available on 20-pin or higher pin count devices only; Bits unimplemented for lower

pin count devices.

DS40002002B-page 211

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.16 ODCONA

Name:ꢀ

Offset:ꢀ

ODCONA

0x1F3A

Open-Drain Control Register

Bit

7

6

5

ODCA5

R/W

0

4

ODCA4

R/W

0

3

2

ODCA2

R/W

0

1

ODCA1

R/W

0

ODCA0

R/W

0

Access

Reset

Bits 4, 5 – ODCAnꢀOpen-Drain Configuration on RA Pins

Value

1

0

Description

PORT pin operates as open-drain drive (sink current only)

PORT pin operates as standard push-pull drive (source and sink current)

Bits 0, 1, 2 – ODCAnꢀOpen-Drain Configuration on RA Pins

Value

Description

1

0

PORT pin operates as open-drain drive (sink current only)

PORT pin operates as standard push-pull drive (source and sink current)

DS40002002B-page 212

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.17 ODCONB

Name:ꢀ

Offset:ꢀ

ODCONB

0x1F45

Open-Drain Control Register

Bit

7

ODCB7

R/W

0

6

ODCB6

R/W

0

5

ODCB5

R/W

0

4

ODCB4

R/W

0

3

2

1

0

Access

Reset

Bits 4, 5, 6, 7 – ODCBnꢀOpen-Drain Configuration on RB Pins

Value

1

0

Description

PORT pin operates as open-drain drive (sink current only)

PORT pin operates as standard push-pull drive (source and sink current)

DS40002002B-page 213

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.18 ODCONC

Name:ꢀ

Offset:ꢀ

ODCONC

0x1F50

Open-Drain Control Register

Bit

7

ODCC7

R/W

0

6

ODCC6

R/W

0

5

ODCC5

R/W

0

4

ODCC4

R/W

0

3

ODCC3

R/W

0

2

ODCC2

R/W

0

1

ODCC1

R/W

0

ODCC0

R/W

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – ODCCnꢀOpen-Drain Configuration on RC Pins

Value

Description

1

PORT pin operates as open-drain drive (sink current only)

0

PORT pin operates as standard push-pull drive (source and sink current)

Note:ꢀ Bits ODCC6 and ODCC7 available on 20-pin or higher pin count devices only; Bits unimplemented for lower

pin count devices.

DS40002002B-page 214

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.19 SLRCONA

Name:ꢀ

Offset:ꢀ

SLRCONA

0x1F3B

Slew Rate Control Register

Bit

7

6

5

SLRA5

R/W

1

4

SLRA4

R/W

1

3

2

SLRA2

R/W

1

SLRA1

R/W

1

0

SLRA0

R/W

1

Access

Reset

Bits 4, 5 – SLRAnꢀSlew Rate Control on RA Pins

Value

Description

1

0

PORT pin slew rate is limited

PORT pin slews at maximum rate

Bits 0, 1, 2 – SLRAnꢀSlew Rate Control on RA Pins

Value

Description

1

0

PORT pin slew rate is limited

PORT pin slews at maximum rate

DS40002002B-page 215

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.20 SLRCONB

Name:ꢀ

Offset:ꢀ

SLRCONB

0x1F46

Slew Rate Control Register

Bit

7

SLRB7

R/W

1

6

SLRB6

R/W

1

5

SLRB5

R/W

1

4

SLRB4

R/W

1

3

2

1

0

Access

Reset

Bits 4, 5, 6, 7 – SLRBnꢀSlew Rate Control on RB Pins

Value

Description

1

0

PORT pin slew rate is limited

PORT pin slews at maximum rate

DS40002002B-page 216

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.21 SLRCONC

Name:ꢀ

Offset:ꢀ

SLRCONC

0x1F51

Slew Rate Control Register

Bit

7

SLRC7

R/W

1

6

SLRC6

R/W

1

5

SLRC5

R/W

1

4

SLRC4

R/W

1

3

SLRC3

R/W

1

2

SLRC2

R/W

1

SLRC1

R/W

1

0

SLRC0

R/W

1

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRCnꢀSlew Rate Control on RC Pins

Value

Description

1

0

PORT pin slew rate is limited

PORT pin slews at maximum rate

Note:ꢀ Bits SLRC6 and SLRC7 available on 20-pin or higher pin count devices only; Bits unimplemented for lower

pin count devices.

DS40002002B-page 217

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.22 INLVLA

Name:ꢀ

Offset:ꢀ

INLVLA

0x1F3C

Input Level Control Register

Bit

7

6

5

INLVLA5

R/W

4

INLVLA4

R/W

3

INLVLA3

R/W

2

INLVLA2

R/W

1

INLVLA1

R/W

0

INLVLA0

R/W

Access

Reset

1

Bits 0, 1, 2, 3, 4, 5 – INLVLAnꢀInput Level Select on RA Pins

Value

Description

1

0

ST input used for port reads and interrupt-on-change

TTL input used for port reads and interrupt-on-change

DS40002002B-page 218

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.23 INLVLB

Name:ꢀ

Offset:ꢀ

INLVLB

0x1F47

Input Level Control Register

Bit

7

INLVLB7

R/W

6

INLVLB6

R/W

5

INLVLB5

R/W

4

INLVLB4

R/W

3

2

1

0

Access

Reset

1

Bits 4, 5, 6, 7 – INLVLBnꢀInput Level Select on RB Pins

Value

Description

1

0

ST input used for port reads and interrupt-on-change

TTL input used for port reads and interrupt-on-change

DS40002002B-page 219

Datasheet

PIC16(L)F18425/45

I/O Ports

14.6.24 INLVLC

Name:ꢀ

Offset:ꢀ

INLVLC

0x1F52

Input Level Control Register

Bit

7

INLVLC7

R/W

6

INLVLC6

R/W

5

INLVLC5

R/W

4

INLVLC4

R/W

3

INLVLC3

R/W

2

INLVLC2

R/W

1

INLVLC1

R/W

0

INLVLC0

R/W

Access

Reset

1

Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLCnꢀInput Level Select on RC Pins

Value

Description

1

0

ST input used for port reads and interrupt-on-change

TTL input used for port reads and interrupt-on-change

Note:ꢀ Bits INLVLC6 and INLVLC7 available on 20-pin or higher pin count devices only; Bits unimplemented for lower

pin count devices.

DS40002002B-page 220

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.

IOC - Interrupt-On-Change

All pins on all ports can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated

by detecting a signal that has either a rising edge or a falling edge. Any individual pin, or combination of pins, can be

configured to generate an interrupt. The interrupt-on-change module has the following features:

•

Interrupt-on-Change enable

Individual pin configuration

Rising and falling edge detection

Individual pin interrupt flags

Figure 15-1 is a block diagram of the IOC module.

Figure 15-1.ꢀInterrupt-on-Change Block Diagram (PORTA Example)

Rev. 10-000 037A

6/2/201 4

D

Q

IOCANx

R

Q4Q1

edge

detect

RAx

to data bus

IOCAFx

S

data bus =

0 or 1

D

Q

D

Q

IOCAPx

write IOCAFx

R

IOCIE

Q2

IOC interrupt

to CPU core

from all other

IOCnFx individual

pin detectors

15.1

15.2

Enabling the Module

To allow individual port pins to generate an interrupt, the IOCIE bit of the PIE0 register must be set. If the IOCIE bit is

disabled, the edge detection on the pin will still occur, but an interrupt will not be generated.

Related Links

7.7.2 PIE0

Individual Pin Configuration

For each PORT pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising

edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the

IOCxN register is set.

A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP

and IOCxN registers, respectively.

DS40002002B-page 221

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.3

Interrupt Flags

The bits located in the IOCxF registers are status flags that correspond to the interrupt-on-change pins of each port. If

an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an

interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the PIR0 register reflects the status of all IOCxF

bits.

Related Links

7.7.11 PIR0

15.3.1 Clearing Interrupt Flags

The individual status flags, (IOCxF register bits), can be cleared by resetting them to zero. If another edge is detected

during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the

value actually being written.

In order to ensure that no detected edge is lost while clearing flags, only ANDoperations masking out known changed

bits should be performed. The following sequence is an example of what should be performed.

Example 15-1.ꢀClearing Interrupt Flags

(PORTA Example)

MOVLW

XORWF

ANDWF

0xFF

IOCAF, W

IOCAF, F

15.4

Operation in Sleep

The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed

out of Sleep.

DS40002002B-page 222

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.5

Register Summary - Interrupt-on-Change

Note:ꢀ PORTB associated registers as well as IOCCx6 and IOCCx7 bits are available for 20-pin or higher pin count

devices only .

Offset

Name

Bit Pos.

0x00

...

Reserved

0x1F3C

0x1F3D

0x1F3E

0x1F3F

0x1F40

...

IOCAP

IOCAN

IOCAF

7:0

IOCAP5

IOCAN5

IOCAF5

IOCAP4

IOCAN4

IOCAF4

IOCAP3

IOCAN3

IOCAF3

IOCAP2

IOCAN2

IOCAF2

IOCAP1

IOCAN1

IOCAF1

IOCAP0

IOCAN0

IOCAF0

Reserved

0x1F47

0x1F48

0x1F49

0x1F4A

0x1F4B

...

IOCBP

IOCBN

IOCBF

7:0

IOCBP7

IOCBN7

IOCBF7

IOCBP6

IOCBN6

IOCBF6

IOCBP5

IOCBN5

IOCBF5

IOCBP4

IOCBN4

IOCBF4

Reserved

0x1F52

0x1F53

0x1F54

0x1F55

IOCCP

IOCCN

IOCCF

7:0

IOCCP7

IOCCN7

IOCCF7

IOCCP6

IOCCN6

IOCCF6

IOCCP5

IOCCN5

IOCCF5

IOCCP4

IOCCN4

IOCCF4

IOCCP3

IOCCN3

IOCCF3

IOCCP2

IOCCN2

IOCCF2

IOCCP1

IOCCN1

IOCCF1

IOCCP0

IOCCN0

IOCCF0

15.6

Register Definitions: Interrupt-on-Change Control

DS40002002B-page 223

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.1 IOCAP

Name:ꢀ

Offset:ꢀ

IOCAP

0x1F3D

Interrupt-on-Change Positive Edge Register

Bit

7

6

5

IOCAP5

R/W

0

4

IOCAP4

R/W

0

3

IOCAP3

R/W

0

2

IOCAP2

R/W

0

1

IOCAP1

R/W

0

IOCAP0

R/W

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5 – IOCAPnꢀInterrupt-on-Change Positive Edge Enable bits

Value

Description

1

Interrupt-on-Change enabled on the IOCA pin for a positive-going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0

Interrupt-on-Change disabled for the associated pin.

Note:ꢀ

1. IOCAP0 and IOCAP1 are not available for use if the debugger is enabled.

2. If MCLRE = 1or LVP = 1, port functionality is disabled and IOCAP3 is not available.

DS40002002B-page 224

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.2 IOCAN

Name:ꢀ

Offset:ꢀ

IOCAN

0x1F3E

Interrupt-on-Change Negative Edge Register

Bit

7

6

5

IOCAN5

R/W

0

4

IOCAN4

R/W

0

3

IOCAN3

R/W

0

2

IOCAN2

R/W

0

1

IOCAN1

R/W

0

IOCAN0

R/W

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5 – IOCANnꢀInterrupt-on-Change Negative Edge Enable bits

Value

Description

1

Interrupt-on-Change enabled on the IOCA pin for a negative-going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0

Interrupt-on-Change disabled for the associated pin

Note:ꢀ

1. IOCAN0 and IOCAN1 are not available for use if the debugger is enabled.

2. If MCLRE = 1or LVP = 1, port functionality is disabled and IOCAN3 is not available.

DS40002002B-page 225

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.3 IOCAF

Name:ꢀ

Offset:ꢀ

IOCAF

0x1F3F

PORTA Interrupt-on-Change Flag Register

Bit

7

6

5

4

3

2

1

0

IOCAF5

R/W/HS

0

IOCAF4

R/W/HS

0

IOCAF3

R/W/HS

0

IOCAF2

R/W/HS

0

IOCAF1

R/W/HS

0

IOCAF0

R/W/HS

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5 – IOCAFnꢀInterrupt-on-Change Flag bits

Value

Condition

Description

1

IOCAP[n]=1

A positive edge was detected on the RA[n] pin

1

0

IOCAN[n]=1

IOCAP[n]=xand IOCAN[n]=x

A negative edge was detected on the RA[n] pin

No change was detected, or the user cleared the detected change

Note:ꢀ

1. IOCAF0 and IOCAF1 are not available for use if the debugger is enabled.

2. If MCLRE = 1or LVP = 1, port functionality is disabled and IOCAF3 is not available.

DS40002002B-page 226

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.4 IOCBP

Name:ꢀ

Offset:ꢀ

IOCBP

0x1F48

Interrupt-on-Change Positive Edge Register

Bit

7

IOCBP7

R/W

0

6

IOCBP6

R/W

0

5

IOCBP5

R/W

0

4

IOCBP4

R/W

0

3

2

1

0

Access

Reset

Bits 4, 5, 6, 7 – IOCBPnꢀInterrupt-on-Change Positive Edge Enable bits

Value

Description

1

Interrupt-on-Change enabled on the IOCB pin for a positive-going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0

Interrupt-on-Change disabled for the associated pin.

Note:ꢀ PORTB associated registers are available on 20-pin or higher pin count devices only.

DS40002002B-page 227

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.5 IOCBN

Name:ꢀ

Offset:ꢀ

IOCBN

0x1F49

Interrupt-on-Change Negative Edge Register

Bit

7

IOCBN7

R/W

0

6

IOCBN6

R/W

0

5

IOCBN5

R/W

0

4

IOCBN4

R/W

0

3

2

1

0

Access

Reset

Bits 4, 5, 6, 7 – IOCBNnꢀInterrupt-on-Change Negative Edge Enable bits

Value

Description

1

Interrupt-on-Change enabled on the IOCB pin for a negative-going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0

Interrupt-on-Change disabled for the associated pin

Note:ꢀ PORTB associated registers are available on 20-pin or higher pin count devices only.

DS40002002B-page 228

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.6 IOCBF

Name:ꢀ

Offset:ꢀ

IOCBF

0x1F4A

PORTB Interrupt-on-Change Flag Register

Bit

7

6

5

4

3

2

1

0

IOCBF7

R/W/HS

0

IOCBF6

R/W/HS

0

IOCBF5

R/W/HS

0

IOCBF4

R/W/HS

0

Access

Reset

Bits 4, 5, 6, 7 – IOCBFnꢀInterrupt-on-Change Flag bits

Value

Condition

Description

1

IOCBP[n]=1

A positive edge was detected on the RB[n] pin

1

0

IOCBN[n]=1

IOCBP[n]=xand IOCBN[n]=x

A negative edge was detected on the RB[n] pin

No change was detected, or the user cleared the detected change

Note:ꢀ PORTB associated registers are available on 20-pin or higher pin count devices only.

DS40002002B-page 229

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.7 IOCCP

Name:ꢀ

Offset:ꢀ

IOCCP

0x1F53

Interrupt-on-Change Positive Edge Register

Bit

7

IOCCP7

R/W

0

6

IOCCP6

R/W

0

5

IOCCP5

R/W

0

4

IOCCP4

R/W

0

3

IOCCP3

R/W

0

2

IOCCP2

R/W

0

1

IOCCP1

R/W

0

IOCCP0

R/W

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCCPnꢀInterrupt-on-Change Positive Edge Enable bits

Value

Description

1

Interrupt-on-Change enabled on the IOCC pin for a positive-going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0

Interrupt-on-Change disabled for the associated pin.

Note:ꢀ IOCCP6 and IOCCP7 are available on 20-pin or higher pin count devices only.

DS40002002B-page 230

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.8 IOCCN

Name:ꢀ

Offset:ꢀ

IOCCN

0x1F54

Interrupt-on-Change Negative Edge Register

Bit

7

IOCCN7

R/W

0

6

IOCCN6

R/W

0

5

IOCCN5

R/W

0

4

IOCCN4

R/W

0

3

IOCCN3

R/W

0

2

IOCCN2

R/W

0

1

IOCCN1

R/W

0

IOCCN0

R/W

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCCNnꢀInterrupt-on-Change Negative Edge Enable bits

Value

Description

1

Interrupt-on-Change enabled on the IOCC pin for a negative-going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0

Interrupt-on-Change disabled for the associated pin

Note:ꢀ IOCCN6 and IOCCN7 are available on 20-pin or higher pin count devices only.

DS40002002B-page 231

Datasheet

PIC16(L)F18425/45

IOC - Interrupt-On-Change

15.6.9 IOCCF

Name:ꢀ

Offset:ꢀ

IOCCF

0x1F55

PORTC Interrupt-on-Change Flag Register

Bit

7

6

5

4

3

2

1

0

IOCCF7

R/W/HS

0

IOCCF6

R/W/HS

0

IOCCF5

R/W/HS

0

IOCCF4

R/W/HS

0

IOCCF3

R/W/HS

0

IOCCF2

R/W/HS

0

IOCCF1

R/W/HS

0

IOCCF0

R/W/HS

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCCFnꢀInterrupt-on-Change Flag bits

Value

Condition

Description

1

IOCCP[n]=1

A positive edge was detected on the RC[n] pin

1

0

IOCCN[n]=1

IOCCP[n]=xand IOCCN[n]=x

A negative edge was detected on the RC[n] pin

No change was detected, or the user cleared the detected change

Note:ꢀ IOCCF6 and IOCCF7 are available on 20-pin or higher pin count devices only.

DS40002002B-page 232

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

16.

PPS - Peripheral Pin Select Module

The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital

signals are included in the selections.

All analog inputs and outputs remain fixed to their assigned pins. Input and output selections are independent as

shown in the Figure 16-1.

Figure 16-1.ꢀSimplified PPS Block Diagram

Rev. 10-000 262B

2/22/201 7

RA0PPS

abcPPS

RA0

Peripheral abc

RxyPPS

Rxy

Peripheral xyz

RC7PPS

RC7

xyzPPS

RC7

16.1

PPS Inputs

Each peripheral has an PPS register with which the input pin to the peripheral is selected. Although every peripheral

has its own PPS input selection register, the selections are identical for every peripheral as shown in 16.9.2 xxxPPS

register

Not all ports are available for input as shown in PPS Input Signal Routing Options.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level

regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must

be cleared to enable the digital input buffer.

Important:ꢀ The notation “xxx” in the generic register name is a place holder for the peripheral identifier.

For example, xxx = INT for the INTPPS register.

Table 16-1.ꢀPPS Input Signal Routing Options

Default

Location at

POR

(14/16-pin

devices)

Default

Location at

POR (20-

Reset Value

(xxxPPS[4:0])

14/16-pin

Reset Value

(xxxPPS[4:0])

20-pin devices

PORT From

Which Input Is

Available

Input Signal Input Register

Name

devices

devices)

00010

INT

INTPPS

RA2

A

B

—

DS40002002B-page 233

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

...........continued

Default

Location at

POR

(14/16-pin

devices)

Default

Reset Value

(xxxPPS[4:0])

14/16-pin

Location at

POR (20-

Reset Value

(xxxPPS[4:0])

20-pin devices

PORT From

Which Input Is

Available

Input Signal Input Register

Name

devices

devices)

00010

00101

00100

00101

10101

10100

10001

10000

10011

10010

10101

00001

10101

10011

00010

00100

00010

10011

10100

10001

00101

10010

10000

10001

10011

10100

10101

00000

10101

10100

00010

00101

00100

00101

10101

10100

10001

10000

10011

10010

10101

00001

10101

10011

00010

00100

00010

10011

01100

01101

10010

01110

01100

10110

01111

01101

00001

01101

01111

T0CKI

T1CKI

T0CKIPPS

T1CKIPPS

T1GPPS

RA2

RA5

RA4

RA5

RC5

RC4

RC1

RC0

RC3

RC2

RC5

RA1

RC5

RC3

RA2

RA4

RA2

RC3

RC4

RC1

RA5

RC2

RC0⁽¹⁾

RC1⁽¹⁾

RC3

RC4⁽¹⁾

RC5⁽¹⁾

RA0

RC5

RC4

RA2

RA5

RA4

RA5

RC5

RC4

RC1

RC0

RC3

RC2

RC5

RA1

RC5

RC3

RA2

RA4

RA2

RC3

RB4

RB5

RC2

RB6⁽¹⁾

RB4⁽¹⁾

RC6

RB7⁽¹⁾

RB5⁽¹⁾

RA1

RB5

RB7

A

B

—

B

—

C

T1G

—

A

T2IN

T2INPPS

—

B

T3CKI

T3CKIPPS

T3GPPS

—

A

T3G

—

B

T4IN

T4INPPS

—

A

T5CKI

T5CKIPPS

T5GPPS

—

B

T5G

—

A

T6IN

T6INPPS

B

MDCARL

MDCARH

MDSRC

CCP1IN

CCP2IN

CCP3IN

CCP4IN

CWG1IN

CWG2IN

CLCIN0

CLCIN1

CLCIN2

CLCIN3

ADACT

MDCARLPPS

MDCARHPPS

MDSRCPPS

CCP1INPPS

CCP2INPPS

CCP3INPPS

CCP4INPPS

CWG1INPPS

CWG2INPPS

CLCIN0PPS

CLCIN1PPS

CLCIN2PPS

CLCIN3PPS

ADACTPPS

—

B

A

—

A

B

—

B

A

—

A

B

SCL1/SCK1 SSP1CLKPPS

B

SDA1/SDI1

SS1

SSP1DATPPS

SS1PPS

B

—

B

SCL2/SCK2 SSP2CLKPPS

—

SDA2/SDI2

SS2

SSP2DATPPS

SS2PPS

B

RX1/DT1

TX1/CK1

RX1PPS

B

CK1PPS

B

DS40002002B-page 234

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

...........continued

Default

Location at

POR

(14/16-pin

devices)

Default

Reset Value

(xxxPPS[4:0])

14/16-pin

Location at

POR (20-

Reset Value

(xxxPPS[4:0])

20-pin devices

PORT From

Which Input Is

Available

Input Signal Input Register

Name

devices

devices)

10000

00101

10000

00101

SMT1SIG

SMT1WIN

SMT1SIGPPS

SMT1WINPPS

RC0

RA5

RC0

RA5

—

B

C

Note:ꢀ

1. Some pads are configured for I²C logic levels; clock and data signals may be assigned to any of these pins.

Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the

INLVL register.

Table 16-2.ꢀPPS Input Register Values

Desired Input Pin

RC7

Value to Write to Register

01 0111

01 0110

01 0101

01 0100

01 0011

01 0010

01 0001

01 0000

00 1111

00 1110

00 1101

00 1100

00 0101

00 0100

00 0011

00 0010

00 0001

00 0000

RC6

RC5

RC4

RC3

RC2

RC1

RC0

RB7

RB6

RB5

RB4

RA5

RA4

RA3

RA2

RA1

RA0

16.2

PPS Outputs

Each I/O pin has a PPS register with which the pin output source is selected. With few exceptions, the port TRIS

control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver

as part of the peripheral operation will override the TRIS control as needed. These peripherals include:

•

EUSART (synchronous operation)

MSSP (I²C)

Although every pin has its own PPS peripheral selection register, the selections are identical for every pin as shown

in the 16.9.3 RxyPPS register.

DS40002002B-page 235

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

Important:ꢀ The notation “Rxy” is a place holder for the pin identifier. The ‘x’ holds the place of the PORT

letter and the ‘y’ holds the place of the bit number. For example, Rxy = RA0 for the RA0PPS register.

Table 16-3 shows detailed output routing options for each peripheral.

Table 16-3.ꢀPPS Output Signal Routing Options

RxyPPS Register Value Output Signal Name

Remappable to any PORT

(14-pin devices)

Remappable to any PORT (20-

pin devices

10 0000

01 1111

01 1110

01 1101

01 1100

01 1011

01 1010

01 1001

01 1000

01 0111

01 0110

01 0101

01 0100

01 0011

01 0010

01 0001

01 0000

00 1111

00 1110

00 1101

00 1100

00 1011

00 1010

00 1001

00 1000

00 0111

00 0110

00 0101

00 0100

00 0011

ADCGRDB

ADCGRDA

CWG2D

X

CWG2C

CWG2B

CWG2A

DSM1OUT

CLKR

NCO1OUT

TMR0OUT

SDO2/SDA2

SCK2/SCL2

SDO1/SDA1

SCK1/SCL1

C2OUT

X

C1OUT

DT1

CK1/TX1

PWM7OUT

PWM6OUT

CCP4OUT

CCP3OUT

CCP2OUT

CCP1OUT

CWG1D

CWG1C

CWG1B

CWG1A

CLC4OUT

CLC3OUT

DS40002002B-page 236

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

...........continued

RxyPPS Register Value Output Signal Name

Remappable to any PORT

Remappable to any PORT (20-

pin devices

(14-pin devices)

00 0010

00 0001

CLC2OUT

CLC1OUT

X

16.3

Bidirectional Pins

PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS

output select the same pin. Peripherals that have bidirectional signals include:

•

EUSART (DT/RXxPPS and TX/CKxPPS pins for synchronous operation)

MSSP (I²C SDA/SSPxDATPPS and SCL/SSPxCLKPPS)

Important:ꢀ The I²C default inputs, and a limited number of other alternate pins, are I²C and SMBus

compatible. Clock and data signals can be routed to any pin, however pins without I²C compatibility will

operate at standard TTL/ST logic levels as selected by the INLVL register. See the INLVL register for each

port to determine which pins are I²C and SMBus compatible.

16.4

PPS Lock

The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent changes. PPS

selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting and clearing this bit requires a

special sequence as an extra precaution against inadvertent changes. Examples of setting and clearing the

PPSLOCKED bit are shown in the following examples.

Example 16-1.ꢀPPS Lock Sequence

; suspend interrupts

BCF

INTCON,GIE

BANKSEL PPSLOCK ; set bank

; required sequence, next 5 instructions

MOVLW

MOVWF

MOVLW

MOVWF

0x55

PPSLOCK

0xAA

PPSLOCK

; Set PPSLOCKED bit to disable writes or

BSF

; restore interrupts

BSF INTCON,GIE

PPSLOCK,PPSLOCKED

Example 16-2.ꢀPPS Unlock Sequence

; suspend interrupts

BCF

INTCON,GIE

BANKSEL PPSLOCK ; set bank

; required sequence, next 5 instructions

MOVLW

MOVWF

MOVLW

MOVWF

0x55

PPSLOCK

0xAA

PPSLOCK

; Clear PPSLOCKED bit to enable writes

BCF

PPSLOCK,PPSLOCKED

DS40002002B-page 237

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

; restore interrupts

BSF INTCON,GIE

Note:ꢀ

1. The PPSLOCK bit can only be set or cleared after the unlock sequence shown above.

2. If PPS1WAY = 1, the PPSLOCK bit cannot be cleared after it has been set.

16.5

PPS1WAY Bit

The PPS can be locked by setting the PPS1WAY bit of Configuration Word 2. When the PPS1WAY bit is set, the

PPSLOCKED bit of the PPSLOCK register can be cleared and set only one time after a device Reset. Once the PPS

registers are configured, user software sets the PPSLOCKED bit, preventing any further writes to the PPS registers.

the PPS registers can be read at any time, regardless of the PPS1WAY or PPSLOCKED settings.

When the PPS1WAY bit is clear, the PPSLOCKED bit of the PPSLOCK register can be cleared and set multiple times

during code execution, but requires the PPS lock/unlock sequence to be performed each time modifications to the

PPS registers are made.

Related Links

16.9.1 PPSLOCK

16.6

16.7

Operation During Sleep

PPS input and output selections are unaffected by Sleep.

Effects of a Reset

A device Power-on-Reset (POR) clears all PPS input and output selections to their default values. All other Resets

leave the selections unchanged. Default input selections are shown in Table 16-1. The PPS1WAY is also removed.

DS40002002B-page 238

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

16.8

Register Summary - PPS

Note:ꢀ PORTB associated RxyPPS register as well as RC6PPS and RC7PPS registers are only available for 20-pin

or higher pin count devices.

Offset

Name

Bit Pos.

0x00

...

Reserved

0x1E8E

0x1E8F

0x1E90

0x1E91

0x1E92

0x1E93

0x1E94

0x1E95

0x1E96

0x1E97

0x1E98

...

PPSLOCK

INTPPS

7:0

PPSLOCKED

PORT[1:0]

PIN[2:0]

T0CKIPPS

T1CKIPPS

T1GPPS

T3CKIPPS

T3GPPS

T5CKIPPS

T5GPPS

Reserved

0x1E9B

0x1E9C

0x1E9D

0x1E9E

0x1E9F

...

T2INPPS

T4INPPS

T6INPPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EA0

0x1EA1

0x1EA2

0x1EA3

0x1EA4

0x1EA5

...

CCP1PPS

CCP2PPS

CCP3PPS

CCP4PPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EA8

0x1EA9

0x1EAA

0x1EAB

...

SMT1WINPPS

SMT1SIGPPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EB0

0x1EB1

0x1EB2

0x1EB3

...

CWG1PPS

CWG2PPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EB7

0x1EB8

0x1EB9

0x1EBA

0x1EBB

0x1EBC

0x1EBD

0x1EBE

0x1EBF

...

MDCARLPPS

MDCARHPPS

MDSRCPPS

CLCIN1PPS

CLCIN2PPS

CLCIN3PPS

CLCIN4PPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EC2

0x1EC3

0x1EC4

0x1EC5

0x1EC6

0x1EC7

0x1EC8

ADACTPPS

Reserved

7:0

PORT[1:0]

PIN[2:0]

SSP1CLKPPS

SSP1DATPPS

SSP1SSPPS

SSP2CLKPPS

7:0

PORT[1:0]

PIN[2:0]

DS40002002B-page 239

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

...........continued

Offset

Name

Bit Pos.

0x1EC9

0x1ECA

0x1ECB

0x1ECC

0x1ECD

...

SSP2DATPPS

SSP2SSPPS

RX1PPS

7:0

PORT[1:0]

PIN[2:0]

CK1PPS

Reserved

0x1F0F

0x1F10

0x1F11

0x1F12

0x1F13

0x1F14

0x1F15

0x1F16

...

RA0PPS

RA1PPS

RA2PPS

Reserved

RA4PPS

RA5PPS

7:0

PPS[5:0]

7:0

PPS[5:0]

Reserved

0x1F1B

0x1F1C

0x1F1D

0x1F1E

0x1F1F

0x1F20

0x1F21

0x1F22

0x1F23

0x1F24

0x1F25

0x1F26

0x1F27

RB4PPS

RB5PPS

RB6PPS

RB7PPS

RC0PPS

RC1PPS

RC2PPS

RC3PPS

RC4PPS

RC5PPS

RC6PPS

RC7PPS

7:0

PPS[5:0]

16.9

Register Definitions: PPS Input and Output Selection

DS40002002B-page 240

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

16.9.1 PPS Lock Register

Name:ꢀ

Offset:ꢀ

PPSLOCK

0x1E8F

Bit

7

6

5

4

3

2

1

0

PPSLOCKED

Access

Reset

R/W

0

Bit 0 – PPSLOCKEDꢀPPS Locked bit

Value

Description

1

0

PPS is locked. PPS selections can not be changed.

PPS is not locked. PPS selections can be changed.

DS40002002B-page 241

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

16.9.2 Peripheral xxx Input Selection

Name:ꢀ

xxxPPS

Bit

7

6

5

4

3

2

1

PIN[2:0]

R/W

g

0

PORT[1:0]

Access

Reset

R/W

x

R/W

x

R/W

g

R/W

g

Bits 4:3 – PORT[1:0]ꢀPeripheral xxx Input PORT Selection bits

See the Table 16-1 for a list of available ports and default pin locations.

Value

10

Description

PORTC

01

PORTB

00

PORTA

Bits 2:0 – PIN[2:0]ꢀPeripheral xxx Input Pin Selection bits

Value

111

110

101

100

011

010

001

000

Description

Peripheral input is from PORTx Pin 7 (Rx7)

Peripheral input is from PORTx Pin 6 (Rx6)

Peripheral input is from PORTx Pin 5 (Rx5)

Peripheral input is from PORTx Pin 4 (Rx4)

Peripheral input is from PORTx Pin 3 (Rx3)

Peripheral input is from PORTx Pin 2 (Rx2)

Peripheral input is from PORTx Pin 1 (Rx1)

Peripheral input is from PORTx Pin 0 (Rx0)

Important:ꢀ

PORTB is available only for 20-pin or higher pin count devices.

Related Links

16.1 PPS Inputs

DS40002002B-page 242

Datasheet

PIC16(L)F18425/45

PPS - Peripheral Pin Select Module

16.9.3 Pin Rxy Output Source Selection Register

Name:ꢀ

RxyPPS

Important:ꢀ See 16.8 Register Summary - PPS for the address offset of each individual register.

Bit

7

6

5

4

3

2

1

0

RxyPPS[5:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 5:0 – RxyPPS[5:0]ꢀPin Rxy Output Source Selection bits

See Table 16-3 for details about source selection.

Related Links

16.2 PPS Outputs

DS40002002B-page 243

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.

CLC - Configurable Logic Cell

The Configurable Logic Cell (CLC) module provides programmable logic that operates outside the speed limitations

of software execution. The logic cell takes up to 64 input signals and, through the use of configurable gates, reduces

the 64 inputs to four logic lines that drive one of eight selectable single-output logic functions.

Input sources are a combination of the following:

•

I/O pins

Internal clocks

Peripherals

Register bits

The output can be directed internally to peripherals and to an output pin.

Important:ꢀ There are several CLC instances on this device. Throughout this section, the lower case ‘x’ in

register names is a generic reference to the CLC instance number. For example, the first instance of the

control register is CLC1CON and is generically described in this chapter as CLCxCON.

The following figure is a simplified diagram showing signal flow through the CLC. Possible configurations include:

•

Combinatorial Logic:

– AND

– NAND

– AND-OR

– AND-OR-INVERT

– OR-XOR

– OR-XNOR

•

Latches:

– S-R

– Clocked D with Set and Reset

– Transparent D with Set and Reset

– Clocked J-K with Reset

DS40002002B-page 244

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

Figure 17-1.ꢀCLC Simplified Block Diagram

Rev. 10-000025H

11/9/2016

OUT

CLCxOUT

D

Q

Q1

LCx_in[0]

LCx_in[1]

LCx_in[2]

CLCx_out

to Peripherals

EN

.

lcxg1

CLCxPPS

PPS

lcxg2

Logic

lcxq

Function

CLCx

lcxg3

lcxg4

(2)

.

POL

TRIS

MODE[2:0]

Interrupt

det

LCx_in[n-2]

LCx_in[n-1]

LCx_in[n]

INTP

INTN

set bit

CLCxIF

Interrupt

det

Note:ꢀ

1. See Figure 17-2 for input data selection and gating.

2. See Figure 17-3 for programmable logic functions.

17.1

CLC Setup

Programming the CLC module is performed by configuring the four stages in the logic signal flow. The four stages

are:

•

Data selection

Data gating

Logic function selection

Output polarity

Each stage is setup at run time by writing to the corresponding CLC Special Function Registers. This has the added

advantage of permitting logic reconfiguration on-the-fly during program execution.

17.1.1 Data Selection

There are 64 signals available as inputs to the configurable logic. Four 64-input multiplexers are used to select the

inputs to pass on to the next stage.

Data selection is through four multiplexers as indicated on the left side of the following diagram. Data inputs in the

figure are identified by a generic numbered input name.

DS40002002B-page 245

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

Figure 17-2.ꢀInput Data Selection and Gating

Data Selection

Rev. 30-000149A

6/12/2017

LCx_in[0]

000000

Data GATE 1

d1T

d1N

G

1 D1 T

1 D1 N

1 D2 T

1 D2N

1 D3 T

1 D3 N

1 D4 T

1 D4 N

111111

LCx_in[n]

LCx_in[0]

D1S[5:0]

lcxg1

000000

G1POL

d2T

d2N

111111

000000

LCx_in[n]

LCx_in[0]

D2S[5:0]

Data GATE 2

lcxg2

d3T

d3N

(Same as Data GATE 1)

Data GATE 3

111111

000000

LCx_in[n]

LCx_in[0]

lcxg3

lcxg4

D3S[5:0]

(Same as Data GATE 1)

Data GATE 4

(Same as Data GATE 1)

d4T

d4N

111111

LCx_in[n]

D4S[5:0]

Note:

All controls are undefined at power-up.

The CLCxSEL0, CLCxSEL1, CLCxSEL2, and CLCxSEL3 Data Input Source registers correlate the generic input

name to the actual signal for each CLC module. The column labeled ‘DyS Value’ indicates the MUX selection code

for the selected data input. DyS is an abbreviation for the MUX select input codes: D1S through D4S where ‘y’ is the

gate number.

DS40002002B-page 246

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

Important:ꢀ Data selections are undefined at power-up.

17.1.2 Data Gating

Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage.

Each data gate can direct any combination of the four selected inputs.

The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or

non-inverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before

going on to the logic function stage.

The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is

inverted, the gate is an AND of all enabled data inputs. When the inputs and output are not inverted, the gate is an

OR or all enabled inputs.

The following table summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The

table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are

selected, the output will be zero or one, depending on the gate output polarity bit.

Table 17-1.ꢀData Gating Logic

CLCxGLSy

0x55

GyPOL

Gate Logic

AND

1

0

1

0

1

0x55

NAND

NOR

0xAA

OR

0x00

Logic 0

Logic 1

0x00

It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the

gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output

of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity

bit to set the desired level.

Data gating is configured with the logic gate select registers as follows:

•

Gate 1: CLCxGLS0

Gate 2: CLCxGLS1

Gate 3: CLCxGLS2

Gate 4: CLCxGLS3

Register number suffixes are different than the gate numbers because other variations of this module have multiple

gate selections in the same register.

Data gating is indicated in the right side of Figure 17-2. Only one gate is shown in detail. The remaining three gates

are configured identically with the exception that the data enables correspond to the enables for that gate.

17.1.3 Logic Function

There are eight available logic functions including:

•

AND-OR

OR-XOR

AND

S-R Latch

D Flip-Flop with Set and Reset

DS40002002B-page 247

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

•

D Flip-Flop with Reset

J-K Flip-Flop with Reset

Transparent Latch with Set and Reset

Logic functions are shown in the following diagram. Each logic function has four inputs and one output. The four

inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to

other peripherals, an output pin, and back to the CLC itself.

Figure 17-3.ꢀProgrammable Logic Functions

Rev. 10-000122B

9/13/2016

AND OR

OR XOR

lcxg1

lcxg2

lcxg1

lcxg2

lcxq

lcxg3

lcxg4

lcxg3

lcxg4

MODE

MODE[2 :0] = 000

[2 :0] = 001

4 input AND

S R Latch

lcxg1

lcxq

S

Q

lcxg2

lcxg3

lcxq

lcxg3

lcxg4

R

lcxg4

MODE

[2 :0] = 011

[2 :0] = 010

1 Input D Flip Flop with S and R

2 Input D Flip Flop with R

lcxg4

lcxg2

S

D

Q

D

Q

lcxg2

lcxq

lcxg1

lcxg3

lcxg1

R

lcxg3

[2 :0] = 100

MODE[2 :0] = 101

MODE

J K Flip Flop with R

1 Input Transparent Latch with S and R

lcxg4

J

Q

lcxg2

lcxq

S

D

Q

lcxg2

lcxq

lcxg1

lcxg4

K

R

LE

lcxg3

lcxg1

R

lcxg3

[2 :0] = 110

MODE[2 :0] = 111

MODE

17.1.4 Output Polarity

The last stage in the CLC is the output polarity. Setting the POL bit in the CLCxPOL register inverts the output signal

from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting

output transition.

DS40002002B-page 248

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.2

CLC Interrupts

An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables

are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose.

The CLCxIF bit of the associated PIR register will be set when either edge detector is triggered and its associated

enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts.

To fully enable the interrupt, set the following bits:

•

CLCxIE bit of the respective PIE register

INTP bit (for a rising edge detection)

INTN bit (for a falling edge detection)

If priority interrupts are not used

– Clear the IPEN bit of the INTCON register

– Set the GIE bit of the INTCON register

– Set the PEIE bit of the INTCON register

If the CLC is a high-priority interrupt

•

– Set the IPEN bit of the INTCON register

– Set the CLCxIP bit of the respective IPR register

– Set the GIEH bit of the INTCON register

If the CLC is a low-priority interrupt

– Set the IPEN bit of the INTCON register

– Clear the CLCxIP bit of the respective IPR register

– Set the GIEL bit of the INTCON register

The CLCxIF bit of the respective PIR register, must be cleared in software as part of the interrupt service. If another

edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.

Related Links

5.8.10 INTCON

7.7.7 PIE5

7.7.16 PIR5

17.3

Output Mirror Copies

Mirror copies of all CLCxOUT bits are contained in the CLCDATA register. Reading this register reads the outputs of

all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the OUT bits in the

individual CLCxCON registers.

17.4

17.5

Effects of a Reset

The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain

unchanged.

Operation During Sleep

The CLC module operates independently from the system clock and will continue to run during Sleep, provided that

the input sources selected remain active.

The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an

input source, regardless of the system clock source selected.

In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when

the CLC is enabled, the CPU will go Idle during Sleep, but the CLC will continue to operate and the HFINTOSC will

remain active.

DS40002002B-page 249

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

This will have a direct effect on the Sleep mode current.

17.6

CLC Setup Steps

The following steps should be followed when setting up the CLC:

•

Disable CLC by clearing the EN bit.

Select desired inputs using the CLCxSEL0 through CLCxSEL3 registers.

Clear any associated ANSEL bits.

Set all TRIS bits associated with inputs.

Enable the chosen inputs through the four gates using the CLCxGLS0 through CLCxGLS3 registers.

Select the gate output polarities with the GyPOL bits

Select the desired logic function with the MODE bits

Select the desired polarity of the logic output with the POL bit. (This step may be combined with the previous

gate output polarity step).

•

If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit corresponding to that

output.

•

Configure the interrupts (optional). See 17.2 CLC Interrupts

Enable the CLC by setting the EN bit.

DS40002002B-page 250

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.7

Register Summary - CLC Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x1E0E

0x1E0F

0x1E10

0x1E11

0x1E12

0x1E13

0x1E14

0x1E15

0x1E16

0x1E17

0x1E18

0x1E19

0x1E1A

0x1E1B

0x1E1C

0x1E1D

0x1E1E

0x1E1F

0x1E20

0x1E21

0x1E22

0x1E23

0x1E24

0x1E25

0x1E26

0x1E27

0x1E28

0x1E29

0x1E2A

0x1E2B

0x1E2C

0x1E2D

0x1E2E

0x1E2F

0x1E30

0x1E31

0x1E32

0x1E33

0x1E34

0x1E35

0x1E36

0x1E37

CLCDATA

CLC1CON

CLC1POL

CLC1SEL0

CLC1SEL1

CLC1SEL2

CLC1SEL3

CLC1GLS0

CLC1GLS1

CLC1GLS2

CLC1GLS3

CLC2CON

CLC2POL

CLC2SEL0

CLC2SEL1

CLC2SEL2

CLC2SEL3

CLC2GLS0

CLC2GLS1

CLC2GLS2

CLC2GLS3

CLC3CON

CLC3POL

CLC3SEL0

CLC3SEL1

CLC3SEL2

CLC3SEL3

CLC3GLS0

CLC3GLS1

CLC3GLS2

CLC3GLS3

CLC4CON

CLC4POL

CLC4SEL0

CLC4SEL1

CLC4SEL2

CLC4SEL3

CLC4GLS0

CLC4GLS1

CLC4GLS2

CLC4GLS3

7:0

MLC4OUT

INTN

MLC3OUT

G3POL

MLC2OUT

MODE[2:0]

G2POL

MLC1OUT

G1POL

EN

OUT

INTP

POL

G4POL

D1S[5:0]

D2S[5:0]

D3S[5:0]

D4S[5:0]

G1D4T

G2D4T

G3D4T

G4D4T

EN

G1D4N

G2D4N

G3D4N

G4D4N

G1D3T

G2D3T

G3D3T

G4D3T

OUT

G1D3N

G2D3N

G3D3N

G4D3N

INTP

G1D2T

G1D2N

G2D2N

G3D2N

G4D2N

G1D1T

G2D1T

G1D1N

G2D1N

G3D1N

G4D1N

G2D2T

G3D2T

G4D2T

INTN

G3D1T

G4D1T

MODE[2:0]

G2POL

POL

G4POL

G3POL

G1POL

D1S[5:0]

D2S[5:0]

D3S[5:0]

D4S[5:0]

G1D4T

G2D4T

G3D4T

G4D4T

EN

G1D4N

G2D4N

G3D4N

G4D4N

G1D3T

G2D3T

G3D3T

G4D3T

OUT

G1D3N

G2D3N

G3D3N

G4D3N

INTP

G1D2T

G1D2N

G2D2N

G3D2N

G4D2N

G1D1T

G2D1T

G1D1N

G2D1N

G3D1N

G4D1N

G2D2T

G3D2T

G4D2T

INTN

G3D1T

G4D1T

MODE[2:0]

G2POL

POL

G4POL

G3POL

G1POL

D1S[5:0]

D2S[5:0]

D3S[5:0]

D4S[5:0]

G1D4T

G2D4T

G3D4T

G4D4T

EN

G1D4N

G2D4N

G3D4N

G4D4N

G1D3T

G2D3T

G3D3T

G4D3T

OUT

G1D3N

G2D3N

G3D3N

G4D3N

INTP

G1D2T

G1D2N

G2D2N

G3D2N

G4D2N

G1D1T

G2D1T

G1D1N

G2D1N

G3D1N

G4D1N

G2D2T

G3D2T

G4D2T

INTN

G3D1T

G4D1T

MODE[2:0]

G2POL

POL

G4POL

G3POL

G1POL

D1S[5:0]

D2S[5:0]

D3S[5:0]

D4S[5:0]

G1D4T

G2D4T

G3D4T

G4D4T

G1D4N

G2D4N

G3D4N

G4D4N

G1D3T

G2D3T

G3D3T

G4D3T

G1D3N

G2D3N

G3D3N

G4D3N

G1D2T

G1D2N

G2D2N

G3D2N

G4D2N

G1D1T

G2D1T

G3D1T

G4D1T

G1D1N

G2D1N

G3D1N

G4D1N

G2D2T

G3D2T

G4D2T

17.8

Register Definitions: Configurable Logic Cell

DS40002002B-page 251

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.1 CLCDATA

Name:ꢀ

Offset:ꢀ

CLCDATA

0x1E0F

CLC Data Ouput Register

Mirror copy of

Bit

7

6

5

4

3

MLC4OUT

R/W

2

MLC3OUT

R/W

1

MLC2OUT

R/W

0

MLC1OUT

R/W

Access

Reset

0

Bits 0, 1, 2, 3 – MLCxOUT

Mirror copy of CLCx_out bit

Value

1

0

Description

CLCx_out is 1

CLCx_out is 0

DS40002002B-page 252

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.2 CLCxCON

Name:ꢀ

Offset:ꢀ

CLCxCON

0x1E10,0x1E1A,0x1E24,0x1E2E

Configurable Logic Cell Control Register

Bit

7

EN

R/W

0

6

5

OUT

RO

0

4

INTP

R/W

0

3

INTN

R/W

0

2

1

MODE[2:0]

R/W

0

Access

Reset

R/W

0

R/W

0

Bit 7 – EN

CLC Enable bit

Value

Description

1

Configurable logic cell is enabled and mixing signals

0

Configurable logic cell is disabled and has logic zero output

Bit 5 – OUT

Logic cell output data, after LCPOL. Sampled from CLCxOUT

Bit 4 – INTP

Configurable Logic Cell Positive Edge Going Interrupt Enable bit

Value

Description

1

0

CLCxIF will be set when a rising edge occurs on CLCxOUT

Rising edges on CLCxOUT have no effect on CLCxIF

Bit 3 – INTN

Configurable Logic Cell Negative Edge Going Interrupt Enable bit

Value

Description

1

0

CLCxIF will be set when a falling edge occurs on CLCxOUT

Falling edges on CLCxOUT have no effect on CLCxIF

Bits 2:0 – MODE[2:0]

Configurable Logic Cell Functional Mode Selection bits

Value

111

110

101

100

011

010

001

000

Description

Cell is 1-input transparent latch with Set and Reset

Cell is J-K flip-flop with Reset

Cell is 2-input D flip-flop with Reset

Cell is 1-input D flip-flop with Set and Reset

Cell is S-R latch

Cell is 4-input AND

Cell is OR-XOR

Cell is AND-OR

DS40002002B-page 253

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.3 CLCxPOL

Name:ꢀ

Offset:ꢀ

CLCxPOL

0x1E11,0x1E1B,0x1E25,0x1E2F

Signal Polarity Control Register

Bit

7

6

5

4

3

G4POL

R/W

x

2

G3POL

R/W

x

1

G2POL

R/W

x

0

G1POL

R/W

x

POL

R/W

0

Access

Reset

Bit 7 – POL

CLCxOUT Output Polarity Control bit

Value

Description

1

The output of the logic cell is inverted

0

The output of the logic cell is not inverted

Bits 0, 1, 2, 3 – GyPOL

Gate Output Polarity Control bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

The gate output is inverted when applied to the logic cell

The output of the gate is not inverted

DS40002002B-page 254

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.4 CLCxSEL0

Name:ꢀ

Offset:ꢀ

CLCxSEL0

0x1E12,0x1E1C,0x1E26,0x1E30

Generic CLCx Data 1 Select Register

Bit

7

6

5

4

3

2

1

0

D1S[5:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 5:0 – D1S[5:0]ꢀCLCx Data 1 Input Selection bits

Table 17-2.ꢀCLC Data Input Sources

D1S Value

111111[63]

111110[62]

111101[61]

111100[60]

111011[59]

111010[58]

111001[57]

111000[56]

110111[55]

110110[54]

110101[53]

110100[52]

110011[51]

110010[50]

110001[49]

110000[48]

101111[47]

101110[46]

101101[45]

101100[44]

101011[43]

101010[42]

101001[41]

101000[40]

100111[39]

CLC Input Source

Reserved

D1S Value

CLC Input Source

DSM1_out

011111[31]

011110[30]

011101[29]

011100[28]

011011[27]

011010[26]

011001[25]

011000[24]

010111[23]

010110[22]

010101[21]

010100[20]

010011[19]

010010[18]

010001[17]

010000[16]

001111[15]

001110[14]

001101[13]

001100[12]

001011[11]

001010[10]

001001[9]

001000[8]

000111[7]

Reserved

IOC_flag

Reserved

ZCD_out

Reserved

C2_out

Reserved

C1_out

Reserved

NCO1_out

Reserved

PWM7_out

PWM6 _out

CCP4_out

Reserved

CCP3_out

Reserved

CCP2_out

Reserved

CCP1_out

Reserved

SMT1_overflow

TMR6 _out

TMR5 _overflow

TMR4_out

Reserved

TMR3 _overflow

TMR2_out

Reserved

CWG2B_out test

CWG2A_out

CWG1B_out

CWG1A_out

MSSP2_clk_out

MSSP2_data_out

MSSP1_clk_out

TMR1_overflow

TMR0_overflow

CLKR_out

FRC

SOSC

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

DS40002002B-page 255

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

...........continued

D1S Value

CLC Input Source

MSSP1_data_out

EUSART1_CK_out

EUSART1_DT_out

CLC4_out

D1S Value

CLC Input Source

LFINTOSC

100110[38]

100101[37]

100100[36]

100011[35]

100010[34]

100001[33]

100000[32]

000110[6]

000101[5]

000100[4]

000011[3]

000010[2]

000001[1]

000000[0]

HFINTOSC (32 MHz)

F_OSC

CLCIN3PPS

CLCIN2PPS

CLCIN1PPS

CLCIN0PPS

CLC3_out

CLC2_out

CLC1_out

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

DS40002002B-page 256

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.5 CLCxSEL1

Name:ꢀ

Offset:ꢀ

CLCxSEL1

0x1E13,0x1E1D,0x1E27,0x1E31

Generic CLCx Data 2 Select Register

Bit

7

6

5

4

3

2

1

0

D2S[5:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 5:0 – D2S[5:0]ꢀCLCx Data 2 Input Selection bits

Table 17-3.ꢀCLC Data Input Sources

D2S Value

111111[63]

111110[62]

111101[61]

111100[60]

111011[59]

111010[58]

111001[57]

111000[56]

110111[55]

110110[54]

110101[53]

110100[52]

110011[51]

110010[50]

110001[49]

110000[48]

101111[47]

101110[46]

101101[45]

101100[44]

101011[43]

101010[42]

101001[41]

101000[40]

100111[39]

CLC Input Source

Reserved

D2S Value

CLC Input Source

DSM1_out

011111[31]

011110[30]

011101[29]

011100[28]

011011[27]

011010[26]

011001[25]

011000[24]

010111[23]

010110[22]

010101[21]

010100[20]

010011[19]

010010[18]

010001[17]

010000[16]

001111[15]

001110[14]

001101[13]

001100[12]

001011[11]

001010[10]

001001[9]

001000[8]

000111[7]

Reserved

IOC_flag

Reserved

ZCD_out

Reserved

C2_out

Reserved

C1_out

Reserved

NCO1_out

Reserved

PWM7_out

PWM6 _out

CCP4_out

Reserved

CCP3_out

Reserved

CCP2_out

Reserved

CCP1_out

Reserved

SMT1_overflow

TMR6 _out

TMR5 _overflow

TMR4_out

Reserved

TMR3 _overflow

TMR2_out

Reserved

CWG2B_out test

CWG2A_out

CWG1B_out

CWG1A_out

MSSP2_clk_out

MSSP2_data_out

MSSP1_clk_out

TMR1_overflow

TMR0_overflow

CLKR_out

FRC

SOSC

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

DS40002002B-page 257

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

...........continued

D2S Value

CLC Input Source

MSSP1_data_out

EUSART1_CK_out

EUSART1_DT_out

CLC4_out

D2S Value

CLC Input Source

LFINTOSC

100110[38]

100101[37]

100100[36]

100011[35]

100010[34]

100001[33]

100000[32]

000110[6]

000101[5]

000100[4]

000011[3]

000010[2]

000001[1]

000000[0]

HFINTOSC (32 MHz)

F_OSC

CLCIN3PPS

CLCIN2PPS

CLCIN1PPS

CLCIN0PPS

CLC3_out

CLC2_out

CLC1_out

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

DS40002002B-page 258

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.6 CLCxSEL2

Name:ꢀ

Offset:ꢀ

CLCxSEL2

0x1E14,0x1E1E,0x1E28,0x1E32

Generic CLCx Data 3 Select Register

Bit

7

6

5

4

3

2

1

0

D3S[5:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 5:0 – D3S[5:0]ꢀCLCx Data 3 Input Selection bits

Table 17-4.ꢀCLC Data Input Sources

D3S Value

111111[63]

111110[62]

111101[61]

111100[60]

111011[59]

111010[58]

111001[57]

111000[56]

110111[55]

110110[54]

110101[53]

110100[52]

110011[51]

110010[50]

110001[49]

110000[48]

101111[47]

101110[46]

101101[45]

101100[44]

101011[43]

101010[42]

101001[41]

101000[40]

100111[39]

CLC Input Source

Reserved

D3S Value

CLC Input Source

DSM1_out

011111[31]

011110[30]

011101[29]

011100[28]

011011[27]

011010[26]

011001[25]

011000[24]

010111[23]

010110[22]

010101[21]

010100[20]

010011[19]

010010[18]

010001[17]

010000[16]

001111[15]

001110[14]

001101[13]

001100[12]

001011[11]

001010[10]

001001[9]

001000[8]

000111[7]

Reserved

IOC_flag

Reserved

ZCD_out

Reserved

C2_out

Reserved

C1_out

Reserved

NCO1_out

Reserved

PWM7_out

PWM6 _out

CCP4_out

Reserved

CCP3_out

Reserved

CCP2_out

Reserved

CCP1_out

Reserved

SMT1_overflow

TMR6 _out

TMR5 _overflow

TMR4_out

Reserved

TMR3 _overflow

TMR2_out

Reserved

CWG2B_out test

CWG2A_out

CWG1B_out

CWG1A_out

MSSP2_clk_out

MSSP2_data_out

MSSP1_clk_out

TMR1_overflow

TMR0_overflow

CLKR_out

FRC

SOSC

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

DS40002002B-page 259

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

...........continued

D3S Value

CLC Input Source

MSSP1_data_out

EUSART1_CK_out

EUSART1_DT_out

CLC4_out

D3S Value

CLC Input Source

LFINTOSC

100110[38]

100101[37]

100100[36]

100011[35]

100010[34]

100001[33]

100000[32]

000110[6]

000101[5]

000100[4]

000011[3]

000010[2]

000001[1]

000000[0]

HFINTOSC (32 MHz)

F_OSC

CLCIN3PPS

CLCIN2PPS

CLCIN1PPS

CLCIN0PPS

CLC3_out

CLC2_out

CLC1_out

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

DS40002002B-page 260

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.7 CLCxSEL3

Name:ꢀ

Offset:ꢀ

CLCxSEL3

0x1E15,0x1E1F,0x1E29,0x1E33

Generic CLCx Data 4 Select Register

Bit

7

6

5

4

3

2

1

0

D4S[5:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 5:0 – D4S[5:0]ꢀCLCx Data 4 Input Selection bits

Table 17-5.ꢀCLC Data Input Sources

D4S Value

111111[63]

111110[62]

111101[61]

111100[60]

111011[59]

111010[58]

111001[57]

111000[56]

110111[55]

110110[54]

110101[53]

110100[52]

110011[51]

110010[50]

110001[49]

110000[48]

101111[47]

101110[46]

101101[45]

101100[44]

101011[43]

101010[42]

101001[41]

101000[40]

100111[39]

CLC Input Source

Reserved

D4S Value

CLC Input Source

DSM1_out

011111[31]

011110[30]

011101[29]

011100[28]

011011[27]

011010[26]

011001[25]

011000[24]

010111[23]

010110[22]

010101[21]

010100[20]

010011[19]

010010[18]

010001[17]

010000[16]

001111[15]

001110[14]

001101[13]

001100[12]

001011[11]

001010[10]

001001[9]

001000[8]

000111[7]

Reserved

IOC_flag

Reserved

ZCD_out

Reserved

C2_out

Reserved

C1_out

Reserved

NCO1_out

Reserved

PWM7_out

PWM6 _out

CCP4_out

Reserved

CCP3_out

Reserved

CCP2_out

Reserved

CCP1_out

Reserved

SMT1_overflow

TMR6 _out

TMR5 _overflow

TMR4_out

Reserved

TMR3 _overflow

TMR2_out

Reserved

CWG2B_out test

CWG2A_out

CWG1B_out

CWG1A_out

MSSP2_clk_out

MSSP2_data_out

MSSP1_clk_out

TMR1_overflow

TMR0_overflow

CLKR_out

FRC

SOSC

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

DS40002002B-page 261

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

...........continued

D4S Value

CLC Input Source

MSSP1_data_out

EUSART1_CK_out

EUSART1_DT_out

CLC4_out

D4S Value

CLC Input Source

LFINTOSC

100110[38]

100101[37]

100100[36]

100011[35]

100010[34]

100001[33]

100000[32]

000110[6]

000101[5]

000100[4]

000011[3]

000010[2]

000001[1]

000000[0]

HFINTOSC (32 MHz)

F_OSC

CLCIN3PPS

CLCIN2PPS

CLCIN1PPS

CLCIN0PPS

CLC3_out

CLC2_out

CLC1_out

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

DS40002002B-page 262

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.8 CLCxGLS0

Name:ꢀ

Offset:ꢀ

CLCxGLS0

0x1E16,0x1E20,0x1E2A,0x1E34

CLCx Gate1 Logic Select Register

Bit

7

6

5

4

G1D3N

R/W

x

3

G1D2T

R/W

x

2

G1D2N

R/W

x

1

G1D1T

R/W

x

0

G1D1N

R/W

x

G1D4T

G1D4N

G1D3T

R/W

x

Access

Reset

R/W

x

R/W

x

Bits 1, 3, 5, 7 – G1DyT

dyT: Gate1 Data ‘y’ True (non-inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

dyT is gated into g1

dyT is not gated into g1

Bits 0, 2, 4, 6 – G1DyN

dyN: Gate1 Data ‘y’ Negated (inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

dyN is gated into g1

dyN is not gated into g1

DS40002002B-page 263

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.9 CLCxGLS1

Name:ꢀ

Offset:ꢀ

CLCxGLS1

0x1E17,0x1E21,0x1E2B,0x1E35

CLCx Gate2 Logic Select Register

Bit

7

6

5

4

G2D3N

R/W

x

3

G2D2T

R/W

x

2

G2D2N

R/W

x

1

G2D1T

R/W

x

0

G2D1N

R/W

x

G2D4T

G2D4N

G2D3T

R/W

x

Access

Reset

R/W

x

R/W

x

Bits 1, 3, 5, 7 – G2DyT

dyT: Gate2 Data ‘y’ True (non-inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

dyT is gated into g2

dyT is not gated into g2

Bits 0, 2, 4, 6 – G2DyN

dyN: Gate2 Data ‘y’ Negated (inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

dyN is gated into g2

dyN is not gated into g2

DS40002002B-page 264

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.10 CLCxGLS2

Name:ꢀ

Offset:ꢀ

CLCxGLS2

0x1E18,0x1E22,0x1E2C,0x1E36

CLCx Gate3 Logic Select Register

Bit

7

6

5

4

G3D3N

R/W

x

3

G3D2T

R/W

x

2

G3D2N

R/W

x

1

G3D1T

R/W

x

0

G3D1N

R/W

x

G3D4T

G3D4N

G3D3T

R/W

x

Access

Reset

R/W

x

R/W

x

Bits 1, 3, 5, 7 – G3DyT

dyT: Gate3 Data ‘y’ True (non-inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

dyT is gated into g3

dyT is not gated into g3

Bits 0, 2, 4, 6 – G3DyN

dyN: Gate3 Data ‘y’ Negated (inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

dyN is gated into g3

dyN is not gated into g3

DS40002002B-page 265

Datasheet

PIC16(L)F18425/45

CLC - Configurable Logic Cell

17.8.11 CLCxGLS3

Name:ꢀ

Offset:ꢀ

CLCxGLS3

0x1E19,0x1E23,0x1E2D,0x1E37

CLCx Gate4 Logic Select Register

Bit

7

6

5

4

G4D3N

R/W

x

3

G4D2T

R/W

x

2

G4D2N

R/W

x

1

G4D1T

R/W

x

0

G4D1N

R/W

x

G4D4T

G4D4N

G4D3T

R/W

x

Access

Reset

R/W

x

R/W

x

Bits 1, 3, 5, 7 – G4DyT

dyT: Gate4 Data ‘y’ True (non-inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

dyT is gated into g4

dyT is not gated into g4

Bits 0, 2, 4, 6 – G4DyN

dyN: Gate4 Data ‘y’ Negated (inverted) bit

Reset States: Default = xxxx

POR/BOR = x

All Other Resets = u

Value

Description

1

0

dyN is gated into g4

dyN is not gated into g4

DS40002002B-page 266

Datasheet

PIC16(L)F18425/45

TMR0 - Timer0 Module

18.

TMR0 - Timer0 Module

Timer0 module has the following features:

•

8-Bit Timer with Programmable Period

16-Bit Timer

Selectable Clock Sources

Synchronous and Asynchronous Operation

Programmable Prescaler and Postscaler

Interrupt on Match or Overflow

Output on I/O Pin (via PPS) or to Other Peripherals

Operation During Sleep

Figure 18-1.ꢀTimer0 Block Diagram

Rev. 10-000017I

2/8/2018

Peripherals

See T0CON1

TMR0

body

T0CKPS

T0OUTPS

Register

T0IF

1

0

Prescaler

IN

OUT

T0_out

Postscaler

SYNC

TMR0

FOSC/4

T016BIT

PPS

T0ASYNC

Q

D

PPS

RxyPPS

T0CKIPPS

CK

T0CS

16-bit TMR0 Body Diagram (T016BIT = 1)

8-bit TMR0 Body Diagram (T016BIT = 0)

Clear

IN

TMR0 High

Byte

OUT

IN

R

TMR0L

8

Read TMR0L

Write TMR0L

COMPARATOR

OUT

T0_match

8

TMR0H

TMR0 High

Byte

Latch

8

Enable

TMR0H

8

Internal Data Bus

DS40002002B-page 267

Datasheet

PIC16(L)F18425/45

TMR0 - Timer0 Module

18.1

Timer0 Operation

Timer0 can operate as either an 8-bit or 16-bit timer. The mode is selected with the T016BIT bit.

18.1.1 8-bit Mode

In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives

several prescale options (see prescaler control bits, T0CKPS).

In this mode as shown in Figure 18-1, a buffered version of TMR0H is maintained. This is compared with the value of

TMR0L on each cycle of the selected clock source. When the two values match, the following events occur:

•

TMR0L is reset

The contents of TMR0H are copied to the TMR0H buffer for next comparison

18.1.2 16-Bit Mode

In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives

several prescale options (see prescaler control bits, T0CKPS).

In this mode TMR0H:TMR0L form the 16-bit timer value. As shown in Figure 18-1, read and write of the TMR0H

register are buffered. TMR0H register is updated with the contents of the high byte of Timer0 during a read of TMR0L

register. Similarly, a write to the high byte of Timer0 takes place through the TMR0H buffer register. The high byte is

updated with the contents of TMR0H register when a write occurs to TMR0L register. This allows all 16 bits of Timer0

to be read and written at the same time.

Timer0 rolls over to 0x0000 on incrementing past 0xFFFF. This makes the timer free-running. TMR0L/H registers

cannot be reloaded in this mode once started.

18.2

Clock Selection

Timer0 has several options for clock source selections, option to operate synchronously/asynchronously and a

programmable prescaler.

18.2.1 Clock Source Selection

The T0CS bits in T0CON1 register are used to select the clock source for Timer0. Refer to Timer0 Clock Source

Selections table for possible clock sources.

18.2.2 Synchronous Mode

When the T0ASYNC bit is clear, Timer0 clock is synchronized to the system clock (F_OSC/4). When operating in

Synchronous mode, Timer0 clock frequency cannot exceed F_OSC/4. During Sleep mode system clock is not available

and Timer0 cannot operate.

18.2.3 Asynchronous Mode

When the T0ASYNC bit is set, Timer0 increments with each rising edge of the input source (or output of the

prescaler, if used). Asynchronous mode allows Timer0 to continue operation during Sleep mode provided the

selected clock source is available.

18.2.4 Programmable Prescaler

Timer0 has 16 programmable input prescaler options ranging from 1:1 to 1:32768. The prescaler values are selected

using the T0CKPS bits.

The prescaler counter is not directly readable or writable. The prescaler counter is cleared on the following events:

•

A write to the TMR0L register

A write to either the T0CON0 or T0CON1 registers

Any device Reset

Related Links

10. Resets

DS40002002B-page 268

Datasheet

PIC16(L)F18425/45

TMR0 - Timer0 Module

18.3

Timer0 Output and Interrupt

18.3.1 Programmable Postscaler

Timer0 has 16 programmable output postscaler options ranging from 1:1 to 1:16. The postscaler values are selected

using the T0OUTPS bits. The postscaler divides the output of Timer0 by the selected ratio.

The postscaler counter is not directly readable or writable. The postscaler counter is cleared on the following events:

•

A write to the TMR0L register

A write to either the T0CON0 or T0CON1 registers

Any device Reset

18.3.2 Timer0 Output

TMR0_out is the output of the postscaler. TMR0_out toggles on every match between TMR0L and TMR0H in 8-bit

mode, or when TMR0H:TMR0L rolls over in 16-bit mode. If the output postscaler is used, the output is scaled by the

ratio selected.

The Timer0 output can be routed to an I/O pin via the RxyPPS output selection register. The Timer0 output can be

monitored through software via the T0OUT output bit.

Related Links

16.2 PPS Outputs

18.3.3 Timer0 Interrupt

The Timer0 Interrupt Flag bit (TMR0IF) is set when the TMR0_out toggles. If the Timer0 interrupt is enabled

(TMR0IE), the CPU will be interrupted when the TMR0IF bit is set.

When the postscaler bits (T0OUTPS) are set to 1:1 operation (no division), the T0IF flag bit will be set with every

TMR0 match or rollover. In general, the TMR0IF flag bit will be set every T0OUTPS +1 matches or rollovers.

18.3.4 Timer0 Example

Timer0 Configuration:

•

Timer0 mode = 16-bit

Clock Source = F_OSC/4 (250 kHz)

Synchronous operation

Prescaler = 1:1

Postscaler = 1:2 (T0OUTPS = 1)

In this case the TMR0_out toggles every two rollovers of TMR0H:TMR0L. i.e.,

(0xFFFF)*2*(1/250kHz) = 524.28 ms

18.4

Operation During Sleep

When operating synchronously, Timer0 will halt when the device enters Sleep mode.

When operating asynchronously and selected clock source is active, Timer0 will continue to increment and wake the

device from Sleep mode if Timer0 interrupt is enabled.

DS40002002B-page 269

Datasheet

PIC16(L)F18425/45

TMR0 - Timer0 Module

18.5

Register Summary - Timer0

Offset

Name

Bit Pos.

0x00

...

Reserved

0x059B

0x059C

0x059D

0x059E

0x059F

TMR0L

TMR0H

T0CON0

T0CON1

7:0

TMR0L[7:0]

TMR0H[7:0]

T0EN

T0OUT

T016BIT

T0OUTPS[3:0]

T0CKPS[3:0]

T0CS[2:0]

T0ASYNC

18.6

Register Definitions: Timer0 Control

DS40002002B-page 270

Datasheet

PIC16(L)F18425/45

TMR0 - Timer0 Module

18.6.1 TMR0L

Name:ꢀ

Offset:ꢀ

TMR0L

0x59C

Timer0 Period/Count Low Register

Bit

7

6

5

4

3

2

1

0

TMR0L[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – TMR0L[7:0]ꢀTMR0 Least Significant Counter

Value

Condition

Description

11111111

T016BIT = 0

8-bit Timer0 Counter bits

to

00000000

11111111

to

T016BIT = 1

16-bit Timer0 Least Significant Byte

00000000

DS40002002B-page 271

Datasheet

PIC16(L)F18425/45

TMR0 - Timer0 Module

18.6.2 TMR0H

Name:ꢀ

Offset:ꢀ

TMR0H

0x59D

Timer0 Period/Count High Register

Bit

7

6

5

4

3

2

1

0

TMR0H[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – TMR0H[7:0]ꢀTMR0 Most Significant Counter

Value

Condition

Description

11111111

T016BIT = 0 8-bit Timer0 Period Value. TMR0L continues counting from 0 when this value is reached.

to

00000000

11111111

to

T016BIT = 1 16-bit Timer0 Most Significant Byte

00000000

DS40002002B-page 272

Datasheet

PIC16(L)F18425/45

TMR0 - Timer0 Module

18.6.3 T0CON0

Name:ꢀ

Offset:ꢀ

T0CON0

0x59E

Timer0 Control Register 0

Bit

7

T0EN

R/W

0

6

5

4

T016BIT

R/W

0

3

2

1

0

T0OUT

T0OUTPS[3:0]

Access

Reset

R

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7 – T0ENꢀTMR0 Enable

Value

Description

1

0

The module is enabled and operating

The module is disabled

Bit 5 – T0OUTꢀTMR0 Output

Bit 4 – T016BITꢀTMR0 Operating as 16-Bit Timer Select

Value

Description

1

0

TMR0 is a 16-bit timer

TMR0 is an 8-bit timer

Bits 3:0 – T0OUTPS[3:0]ꢀTMR0 Output Postscaler (Divider) Select

Value

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Description

1:16 Postscaler

1:15 Postscaler

1:14 Postscaler

1:13 Postscaler

1:12 Postscaler

1:11 Postscaler

1:10 Postscaler

1:9 Postscaler

1:8 Postscaler

1:7 Postscaler

1:6 Postscaler

1:5 Postscaler

1:4 Postscaler

1:3 Postscaler

1:2 Postscaler

1:1 Postscaler

DS40002002B-page 273

Datasheet

PIC16(L)F18425/45

TMR0 - Timer0 Module

18.6.4 T0CON1

Name:ꢀ

Offset:ꢀ

T0CON1

0x59F

Timer0 Control Register 1

Bit

7

6

T0CS[2:0]

R/W

5

4

T0ASYNC

R/W

3

2

1

0

T0CKPS[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:5 – T0CS[2:0]ꢀTimer0 Clock Source Select

Table 18-1.ꢀTimer0 Clock Source Selections

T0CS

111

110

101

100

011

010

001

Clock Source

CLC1_out

SOSC

MFINTOSC(500 kHz)

LFINTOSC

HFINTOSC

F_OSC/4

Pin selected by T0CKIPPS (Inverted)

000

Pin selected by T0CKIPPS (Noninverted)

Bit 4 – T0ASYNCꢀTMR0 Input Asynchronization Enable

Value

Description

1

0

The input to the TMR0 counter is not synchronized to system clocks

The input to the TMR0 counter is synchronized to F_OSC/4

Bits 3:0 – T0CKPS[3:0]ꢀPrescaler Rate Select

Value

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Description

1:32768

1:16384

1:8192

1:4096

1:2048

1:1024

1:512

1:256

1:128

1:64

1:32

1:16

1:8

1:4

1:2

1:1

DS40002002B-page 274

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.

TMR1 - Timer1 Module with Gate Control

Timer1 module is a 16-bit timer/counter with the following features:

•

16-Bit Timer/Counter Register Pair (TMRxH:TMRxL)

Programmable Internal or External Clock Source

2-Bit Prescaler

Optionally Synchronized Comparator Out

Multiple Timer1 Gate (Count Enable) Sources

Interrupt-on-Overflow

Wake-Up on Overflow (External Clock, Asynchronous Mode Only)

16-Bit Read/Write Operation

Time Base for the Capture/Compare Function with the CCP Modules

Special Event Trigger (with CCP)

Selectable Gate Source Polarity

Gate Toggle Mode

Gate Single Pulse Mode

Gate Value Status

Gate Event Interrupt

Important:ꢀ References to module Timer1 apply to all the odd numbered timers on this device.

DS40002002B-page 275

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

Figure 19-1.ꢀTimer1 Block Diagram

TxGATE

4

TxGPPS

GSPM

0000

PPS

1

D

Q

GVAL

0

1

Single Pulse

Acq. Control

NOTE (5)

0

1111

Q1

D

Q

GPOL

ON

GGO/DONE

CK

R

Interrupt

det

set bit

TMRxGIF

GTM

GE

set flag bit

TMRxIF

ON

EN

D

To Comparators (6)

Synchronized Clock Input

TMRx⁽²⁾

Tx_overflow

Q

TMRxH

TMRxL

0

1

TxCLK

SYNC

TxCLK

4

TxCKIPPS

PPS

(1)

0000

Prescaler

1,2,4,8

Synchronize⁽³⁾

det

Note ⁽⁴⁾

1111

2

Fosc/2

Internal

Clock

CKPS

Sleep

Input

Note:ꢀ

1. This signal comes from the pin seleted by TxCKIPPS.

2. TMRx register increments on rising edge.

3. Synchronize does not operate while in Sleep.

4. See TMRxCLK for clock source selections.

5. See TMRxGATE for gate source selection.

6. Synchronized comparator output should not be used in conjunction with synchronized input clock.

19.1

Timer1 Operation

The Timer1 module is a 16-bit incrementing counter that is accessed through the TMRxH:TMRxL register pair. Writes

to TMRxH or TMRxL directly update the counter.

When used with an internal clock source, the module is a timer and increments on every instruction cycle. When

used with an external clock source, the module can be used as either a timer or counter and increments on every

selected edge of the external source.

Timer1 is enabled by configuring the ON and GE bits in the TxCON and TxGCON registers, respectively. The table

below displays the Timer1 enable selections.

DS40002002B-page 276

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

Table 19-1.ꢀTimer1 Enable Selections

ON

1

GE

1

Timer1 Operation

Count Enabled

Always On

Off

1

0

1

0

Off

19.2

Clock Source Selection

The CS bits select the clock source for Timer1. These bits allow the selection of several possible synchronous and

asynchronous clock sources. The possible clock source are listed in 19.14.5 TMRxCLK register.

19.2.1 Internal Clock Source

When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of F_OSCas

determined by the Timer1 prescaler.

When the F_OSCinternal clock source is selected, the Timer1 register value will increment by four counts every

instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To

utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input.

Important:ꢀ In Counter mode, a falling edge must be registered by the counter prior to the first

incrementing rising edge after any one or more of the following conditions:

•

Timer1 enabled after POR

Write to TMRxH or TMRxL

Timer1 is disabled

Timer1 is disabled (TMRxON = 0) when TxCKI is high then Timer1 is enabled (TMRxON = 1) when

TxCKI is low. Refer to the figure below.

Figure 19-2.ꢀTimer1 Incrementing Edge

Rev. 30-000136A

5/24/2017

TxCKI = 1

when TMRx

Enabled

TxCKI = 0

when TMRx

Enabled

Note:ꢀ

1. Arrows indicate counter increments.

2. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of

the clock.

19.2.2 External Clock Source

When the external clock source is selected, the Timer1 module may work as a timer or a counter.

When enabled to count, Timer1 is incremented on the rising edge of the external clock input of the TxCKIPPS pin.

This external clock source can be synchronized to the system clock or it can run asynchronously.

DS40002002B-page 277

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.3

19.4

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits control the prescale

counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a

write to TMRxH or TMRxL.

Secondary Oscillator

A secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier

output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The secondary oscillator

is not dedicated only to Timer1; it can also be used by other modules.

The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register. This can be used as one of the

Timer1 clock sources selected with the CS bits. The oscillator will continue to run during Sleep.

Important:ꢀ The oscillator requires a start-up and stabilization time before use. Thus, the SOSCEN bit of

the OSCEN register should be set and a suitable delay observed prior to enabling Timer1. A software

check can be performed to confirm if the secondary oscillator is enabled and ready to use. This is done by

polling the SOR bit of the OSCSTAT register.

Related Links

8.2.1.5 Secondary Oscillator

19.5

Timer1 Operation in Asynchronous Counter Mode

When the SYNC control bit is set, the external clock input is not synchronized. The timer increments asynchronously

to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and

can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software

are needed to read/write the timer (see 19.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode).

Important:ꢀ When switching from synchronous to asynchronous operation, it is possible to skip an

increment. When switching from asynchronous to synchronous operation, it is possible to produce an

additional increment.

19.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode

Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read

(taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values

itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that

the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer

registers, while the register is incrementing. This may produce an unpredictable value in the TMRxH:TMRxL register

pair.

19.6

Timer1 16-Bit Read/Write Mode

Timer1 can be configured to read and write all 16 bits of data, to and from, the 8-bit TMRxL and TMRxH registers,

simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit.

To accomplish this function, the TMRxH register value is mapped to a buffer register called the TMRxH buffer

register. While in 16-Bit mode, the TMRxH register is not directly readable or writable and all read and write

operations take place through the use of this TMRxH buffer register.

When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the

TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH

DS40002002B-page 278

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1 value from a

single instance in time. Refer the figure below for more details.

In contrast, when not in 16-Bit mode, the user must read each register separately and determine if the values have

become invalid due to a rollover that may have occurred between the read operations.

When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with

the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to

the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the

TMRxL:TMRxH register pair at the same time.

Any requests to write to the TMRxH directly does not clear the Timer1 prescaler value. The prescaler value is only

cleared through write requests to the TMRxL register.

Figure 19-3.ꢀTimer1 16-Bit Read/Write Mode Block Diagram

Rev. 30-000135A

5/24/2017

From

Timer1

Circuitry

Set

TMR1

High Byte

TMR1L

TMR1IF

on Overflow

8

Read TMR1L

Write TMR1L

8

TMR1H

8

Internal Data Bus

19.7

Timer1 Gate

Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is

also referred to as Timer1 gate enable.

Timer1 gate can also be driven by multiple selectable sources.

19.7.1 Timer1 Gate Enable

The Timer1 Gate Enable mode is enabled by setting the GE bit. The polarity of the Timer1 Gate Enable mode is

configured using the GPOL bit.

When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source.

When Timer1 Gate signal is inactive, the timer will not increment and hold the current count. Enable mode is

disabled, no incrementing will occur and Timer1 will hold the current count. See figure below for timing details.

Table 19-2.ꢀTimer1 Gate Enable Selections

TMRxCLK

GPOL

TxG

1

Timer1 Operation

Counts

1

0

↑

0

Holds Count

Counts

1

0

DS40002002B-page 279

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

Figure 19-4.ꢀTimer1 Gate Enable Mode

Rev. 30-000137A

5/24/2017

TMRxGE

TxGPOL

TxG_IN

TxCKI

TxGVAL

Timer1/3/5/7

N

N + 1

N + 2

N + 3

N + 4

19.7.2 Timer1 Gate Source Selection

The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by

the GPOL bit. The following gate source are available:

•

Signal Measurement Timers

Configurable Logic Cells

Comparators

PWM

NCO

T1CLKIN

For all options for gate source selection refer to the 19.14.4 TMRxGATE.

Related Links

34.4.1 Comparator Output Synchronization

19.7.3 Timer1 Gate Toggle Mode

When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as

opposed to the duration of a single level pulse.

The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See

figure below for timing details.

Timer1 Gate Toggle mode is enabled by setting the GTM bit. When the GTM bit is cleared, the flip-flop is cleared and

held clear. This is necessary in order to control which edge is measured.

Important:ꢀ Enabling Toggle mode at the same time as changing the gate polarity may result in

indeterminate operation.

DS40002002B-page 280

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

Figure 19-5.ꢀTimer1 Gate Toggle Mode

Rev. 30-000138A

5/25/2017

TMRxGE

TxGPOL

TxGTM

TxTxG_IN

TxCKI

TxGVAL

TIMER1/3/5/7

N

N + 1 N + 2 N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

19.7.4 Timer1 Gate Single Pulse Mode

When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate

Single Pulse mode is first enabled by setting the GSPM bit in the TxGCON register. Next, the GGO/DONE bit in the

TxGCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing

edge of the pulse, the GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment

Timer1 until the GGO/DONE bit is once again set in software.

Clearing the GSPM bit will also clear the GGO/DONE bit. See figure below for timing details.

Enabling the Toggle mode and the Single Pulse mode simultaneously will permit both sections to work together. This

allows the cycle times on the Timer1 gate source to be measured. See figure below for timing details.

DS40002002B-page 281

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

Figure 19-6.ꢀTimer1 Gate Single Pulse Mode

Rev. 30-000139A

5/25/2017

TMRxGE

TxGPOL

TxGSPM

Cleared by hardware on

falling edge of TxGVAL

TxGGO/

DONE

Set by software

Counting enabled on

rising edge of TxG

TxG_IN

TxCKI

TxGVAL

TIMER1/3/5/7

TMRxGIF

N

N + 1

N + 2

Cleared by

software

Set by hardware on

falling edge of TxGVAL

Cleared by software

DS40002002B-page 282

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

Figure 19-7.ꢀTimer1 Gate Single Pulse and Toggle Combined Mode

Rev. 30-000140A

5/25/2017

TMRxGE

TxGPOL

TxGSPM

TxGTM

Cleared by hardware on

falling edge of TxGVAL

TxGGO/

DONE

Set by software

Counting enabled on

rising edge of TxG

TxG_IN

TxCKI

TxGVAL

TIMER1/3/5/7

TMRxGIF

N + 4

N + 2 N + 3

N

N + 1

Set by hardware on

falling edge of TxGVAL

Cleared by

software

Cleared by software

19.7.5 Timer1 Gate Value Status

When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The

value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the Timer1 gate is not

enabled (GE bit is cleared).

19.7.6 Timer1 Gate Event Interrupt

When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate

event. When the falling edge of GVAL occurs, the TMRxGIF flag bit in the PIR5 register will be set. If the TMRxGIE

bit in the PIE5 register is set, then an interrupt will be recognized.

The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (GE bit is cleared).

For more information on selecting high or low priority status for the Timer1 gate event interrupt see the Interrupts

chapter.

19.8

Timer1 Interrupt

The Timer1 register pair (TMRxH:TMRxL) increments to 0xFFFF and rolls over to 0x0000. When Timer1 rolls over,

the Timer1 Interrupt Flag (TMR1IF) bit of the PIR4 register is set. To enable the interrupt-on-rollover, the following bits

must be set:

•

TMRxON bit of the TxCON register

TMRxIE bits of the PIE4 register

DS40002002B-page 283

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

•

PEIE/GIEL bit of the INTCON register

GIE/GIEH bit of the INTCON register

The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine.

For more information on selecting high or low priority status for the Timer1 overflow interrupt, see the Interrupts

chapter.

Important:ꢀ The TMRxH:TMRxL register pair and the TMRxIF bit should be cleared before enabling

interrupts.

19.9

Timer1 Operation During Sleep

Timer1 can only operate during Sleep when configured for Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the counter. To set up the timer to wake the device:

•

TMRxON bit of the TxCON register must be set

TMRxIE bit of the PIEx register must be set

PEIE/GIEL bit of the INTCON register must be set

TxSYNC bit of the TxCON register must be set

Configure the TMRxCLK register for using secondary oscillator as the clock source

Enable the SOSCEN bit of the OSCEN register

The device will wake-up on an overflow and execute the next instruction. If the GIE/GIEH bit of the INTCON register

is set, the device will call the Interrupt Service Routine.

The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting.

19.10 CCP Capture/Compare Time Base

The CCP modules use the TMRxH:TMRxL register pair as the time base when operating in Capture or Compare

mode.

In Capture mode, the value in the TMRxH:TMRxL register pair is copied into the CCPRxH:CCPRxL register pair on a

configured event.

In Compare mode, an event is triggered when the value in the CCPRxH:CCPRxL register pair matches the value in

the TMRxH:TMRxL register pair. This event can be a Special Event Trigger.

For more information, see Capture/Compare/PWM Module(CCP) chapter.

Related Links

22. Capture/Compare/PWM Module

19.11 CCP Special Event Trigger

When any of the CCPs are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL register pair.

This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP

interrupt.

In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1.

Timer1 should be synchronized and F_OSC/4 should be selected as the clock source in order to utilize the Special

Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed.

In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take

precedence.

DS40002002B-page 284

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.12 Peripheral Module Disable

When a peripheral is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD

registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in

Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD) are in the PMD1

register. See Peripheral Module Disable (PMD) chapter for more information.

Related Links

13.4 Register Summary - PMD

DS40002002B-page 285

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.13 Register Summary - Timer1

Offset

Name

Bit Pos.

0x00

...

Reserved

0x020B

7:0

15:8

7:0

15:8

7:0

15:8

7:0

TMRx[7:0]

0x020C

TMR1

TMRx[15:8]

0x020E

0x020F

0x0210

0x0211

T1CON

T1GCON

CKPS[1:0]

GTM GSPM

SYNC

GVAL

RD16

ON

GE

GPOL

GGO/DONE

TMR1GATE

TMR1CLK

GSS[4:0]

CS[4:0]

TMRx[7:0]

TMRx[15:8]

0x0212

TMR3

0x0214

0x0215

0x0216

0x0217

T3CON

T3GCON

CKPS[1:0]

GTM GSPM

SYNC

GVAL

GGO/DONE

TMR3GATE

TMR3CLK

GSS[4:0]

CS[4:0]

TMRx[7:0]

0x0218

TMR5

TMRx[15:8]

0x021A

0x021B

0x021C

0x021D

T5CON

T5GCON

CKPS[1:0]

GTM GSPM

SYNC

GVAL

GGO/DONE

TMR5GATE

TMR5CLK

GSS[4:0]

CS[4:0]

19.14 Register Definitions: Timer1

DS40002002B-page 286

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.14.1 Timer Register

Name:ꢀ

Offset:ꢀ

TMRx

0x20C,0x212,0x218

Bit

15

14

13

12

11

10

9

8

TMRx[15:8]

TMRx[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 15:0 – TMRx[15:0]ꢀTimer Register Value

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

TMRxH: Accesses the high byte TMRx[15:8]

TMRxL: Accesses the low byte TMRx[7:0]

Reset States: POR/BOR = 0000000000000000

All Other Resets = uuuuuuuuuuuuuuuu

DS40002002B-page 287

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.14.2 TxCON

Name:ꢀ

Offset:ꢀ

TxCON

0x20E,0x214,0x21A

Timer Control Register

Bit

7

6

5

4

3

2

SYNC

R/W

0

1

RD16

R/W

0

ON

R/W

0

CKPS[1:0]

Access

Reset

R/W

0

R/W

0

Bits 5:4 – CKPS[1:0]ꢀTimer Input Clock Prescale Select bits

Reset States: POR/BOR = 00

All Other Resets = uu

Value

11

10

01

00

Description

1:8 Prescale value

1:4 Prescale value

1:2 Prescale value

1:1 Prescale value

Bit 2 – SYNCꢀTimer External Clock Input Synchronization Control bit

Reset States: POR/BOR = 0

All Other Resets = u

Value

Condition

Description

X

1

0

CS = F_OSC/4 or F_OSC

Else

This bit is ignored. Timer uses the incoming clock as is.

Do not synchronize external clock input

Synchronize external clock input with system clock

Bit 1 – RD16ꢀ16-Bit Read/Write Mode Enable bit

Reset States: POR/BOR = 0

All Other Resets = u

Value

Description

1

0

Enables register read/write of Timer in one 16-bit operation

Enables register read/write of Timer in two 8-bit operations

Bit 0 – ONꢀTimer On bit

Reset States: POR/BOR = 0

All Other Resets = u

Description

Value

1

0

Enables Timer

Disables Timer

DS40002002B-page 288

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.14.3 TxGCON

Name:ꢀ

Offset:ꢀ

TxGCON

0x20F,0x215,0x21B

Timer Gate Control Register

Bit

7

GE

R/W

0

6

GPOL

R/W

0

5

GTM

R/W

0

4

GSPM

R/W

0

3

2

GVAL

RO

x

1

0

GGO/DONE

Access

Reset

R/W

0

Bit 7 – GEꢀTimer Gate Enable bit

Reset States: POR/BOR = 0

All Other Resets = u

Value

1

Condition

ON = 1

Description

Timer counting is controlled by the Timer gate function

0

X

ON = 1

ON = 0

Timer is always counting

This bit is ignored

Bit 6 – GPOLꢀTimer Gate Polarity bit

Reset States: POR/BOR = 0

All Other Resets = u

Value

Description

1

0

Timer gate is active-high (Timer counts when gate is high)

Timer gate is active-low (Timer counts when gate is low)

Bit 5 – GTMꢀTimer Gate Toggle Mode bit

Timer Gate Flip-Flop Toggles on every rising edge when Toggle mode is enabled.

Reset States: POR/BOR = 0

All Other Resets = u

Value

Description

1

0

Timer Gate Toggle mode is enabled

Timer Gate Toggle mode is disabled and Toggle flip-flop is cleared

Bit 4 – GSPMꢀTimer Gate Single Pulse Mode bit

Reset States: POR/BOR = 0

All Other Resets = u

Value

Description

1

0

Timer Gate Single Pulse mode is enabled and is controlling Timer gate)

Timer Gate Single Pulse mode is disabled

Bit 3 – GGO/DONEꢀTimer Gate Single Pulse Acquisition Status bit

This bit is automatically cleared when TxGSPM is cleared.

Reset States: POR/BOR = 0

All Other Resets = u

Value

Description

1

0

Timer Gate Single Pulse Acquisition is ready, waiting for an edge

Timer Gate Single Pulse Acquisition has completed or has not been started.

Bit 2 – GVALꢀTimer Gate Current State bit

Indicates the current state of the timer gate that could be provided to TMRxH:TMRxL

Unaffected by Timer Gate Enable (TMRxGE)

DS40002002B-page 289

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.14.4 TMRxGATE

Name:ꢀ

Offset:ꢀ

TMRxGATE

0x210,0x216,0x21C

Timer Gate Source Selection Register

Bit

7

6

5

4

3

2

GSS[4:0]

R/W

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – GSS[4:0]ꢀTimer Gate Source Selection bits

Table 19-3.ꢀTimer Gate Sources

Gate Source

Timer3

GSS

Timer1

Timer5

11111-11001

10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

Reserved

CLC4_out

Reserved

CLC4_out

CLC3_out

CLC2_out

CLC1_out

ZCD1_output

C2OUT_sync

C1OUT_sync

NCO1_out

PWM7_out

PWM6_out

CCP4_out

CCP3_out

CCP2_out

CCP1_out

CLC4_out

CLC3_out

CLC2_out

CLC1_out

ZCD1_output

C2OUT_sync

C1OUT_sync

NCO1_out

ZCD1_output

C2OUT_sync

C1OUT_sync

NCO1_out

PWM7_out

PWM6_out

CCP4_out

CCP3_out

CCP2_out

CCP1_out

SMT1_overflow

PWM7_out

PWM6_out

CCP4_out

CCP3_out

CCP2_out

CCP1_out

SMT1_overflow

TMR6_postscaled output

Timer5 overflow output

TMR4_postscaled output

Timer3 overflow output

TMR2_postscaled output

Reserved

SMT1_overflow

TMR6_postscaled output

Reserved

TMR6_postscaled output

Timer5 overflow output

TMR4_postscaled output

Reserved

TMR4_postscaled output

Timer3 overflow output

TMR2_postscaled output

Timer1 overflow output

Timer0 overflow output

T5GPPS

TMR2_postscaled output

Timer1 overflow output

Timer0 overflow output

T3GPPS

Timer0 overflow output

T1GPPS

Reset States: POR/BOR = 00000

DS40002002B-page 290

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

All Other Resets = uuuuu

DS40002002B-page 291

Datasheet

PIC16(L)F18425/45

TMR1 - Timer1 Module with Gate Control

19.14.5 TMRxCLK

Name:ꢀ

Offset:ꢀ

TMRxCLK

0x211,0x217,0x21D

Timer Clock Source Selection Register

Bit

7

6

5

4

3

2

CS[4:0]

R/W

0

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – CS[4:0]ꢀTimer Clock Source Selection bits

Table 19-4.ꢀTimer Clock Sources

Clock Source

Timer3

CS

Timer1

Timer5

11111-10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

Reserved

CLC4_out

Reserved

CLC4_out

CLC3_out

CLC2_out

CLC1_out

Reserved

CLC4_out

CLC3_out

CLC2_out

CLC1_out

Reserved

CLC3_out

CLC2_out

CLC1_out

Timer5 overflow output

Timer3 overflow output

Reserved

Timer5 overflow output

Reserved

Timer3 overflow output

Timer1 overflow output

Timer0 overflow output

CLKR output

Timer1 overflow output

Timer0 overflow output

CLKR output

Timer0 overflow output

CLKR output

SOSC

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

LFINTOSC

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

LFINTOSC

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

LFINTOSC

HFINTOSC

F_OSC

F_OSC/4

T1CKIPPS

T3CKIPPS

T5CKIPPS

Reset States: POR/BOR = 00000

All Other Resets = uuuuu

DS40002002B-page 292

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.

TMR2 - Timer2 Module

The Timer2 module is a 8-bit timer that incorporates the following features:

•

8-Bit Timer and Period Registers

Readable and Writable

Software Programmable Prescaler (1:1 to 1:128)

Software Programmable Postscaler (1:1 to 1:16)

Interrupt on T2TMR Match with T2PR

One-Shot Operation

Full Asynchronous Operation

Includes Hardware Limit Timer (HLT)

Alternate Clock Sources

External Timer Reset Signal Sources

Configurable Timer Reset Operation

See Figure 20-1 for a block diagram of Timer2.

Important:ꢀ References to module Timer2 apply to all the even numbered timers on this device. (Timer2,

Timer4, etc.)

Figure 20-1.ꢀTimer2 with Hardware Limit Timer (HLT) Block Diagram

RSEL

Rev. 10-000168D

TxINPPS

4/29/2019

TxIN

PPS

MODE

MODE[3]

External

Reset

TMRx_ers

reset

Edge Detector

Level Detector

Mode Control

(2 clock Sync)

CCP_pset⁽¹⁾

Sources⁽²⁾

MODE[4:3]=’b01

enable

CKPOL

CS

Clear ON

D

Q

MODE[4:1]=’b1011

TMRx_clk

TxINPPS

TxIN

PPS

Prescaler

CKPS

0

R

TxTMR

Set flag bit

TMRxIF

Sync

Fosc/4

1

See

TxCLKCON

register⁽³⁾

PSYNC

TMRx_postscaled

Comparator

TxPR

Postscaler

Sync

(2 Clocks)

1

0

OUTPS

ON

CSYNC

Note:ꢀ

1. Signal to the CCP to trigger the PWM pulse.

2. See TxRST for external Reset sources.

3. See Clock Source Selection table for clock source selection.

DS40002002B-page 293

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.1

Timer2 Operation

Timer2 operates in three major modes:

•

Free Running Period

One-shot

Monostable

Within each mode there are several options for starting, stopping, and reset. Table 20-1 lists the options.

In all modes, the T2TMR count register is incremented on the rising edge of the clock signal from the programmable

prescaler. When T2TMR equals T2PR, a high level is output to the postscaler counter. T2TMR is cleared on the next

clock input.

An external signal from hardware can also be configured to gate the timer operation or force a T2TMR count Reset.

In Gate modes the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes

the T2TMR count is reset on either the level or edge from the external source.

The T2TMR and T2PR registers are both directly readable and writable. The T2TMR register is cleared and the

T2PR register initializes to FFh on any device Reset. Both the prescaler and postscaler counters are cleared on the

following events:

•

A write to the T2TMR register

A write to the T2CON register

Any device Reset

External Reset Source event that resets the timer.

Important:ꢀ T2TMR is not cleared when T2CON is written.

20.1.1 Free-Running Period Mode

The value of T2TMR is compared to that of the Period register, T2PR, on each clock cycle. When the two values

match, the comparator resets the value of T2TMR to 00h on the next cycle and increments the output postscaler

counter. When the postscaler count equals the value in the OUTPS bits of the T2CON register then a one clock

period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared.

20.1.2 One-Shot Mode

The One-Shot mode is identical to the Free-Running Period mode except that the ON bit is cleared and the timer is

stopped when T2TMR matches T2PR and will not restart until the ON bit is cycled off and on. Postscaler (OUTPS)

values other than zero are ignored in this mode because the timer is stopped at the first period event and the

postscaler is reset when the timer is restarted.

20.1.3 Monostable Mode

Monostable modes are similar to One-Shot modes except that the ON bit is not cleared and the timer can be

restarted by an external Reset event.

20.2

Timer2 Output

The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each

match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is incremented each time

the T2TMR value matches the T2PR value. This signal can be selected as an input to several other input modules:

•

The ADC module, as an auto-conversion trigger

CWG, as an auto-shutdown source

The CRC memory scanner, as a trigger for triggered mode

DS40002002B-page 294

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

•

Gate source for odd numbered timers (Timer1, Timer3, etc.)

Alternate SPI clock

Reset signals for other instances of even numbered timers (Timer2, Timer4, etc.)

In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See “PWM Overview”

and “Pulse-width Modulation” sections for more details on setting up Timer2 for use with the CCP and PWM modules.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.3

20.4

External Reset Sources

In addition to the clock source, the Timer2 also takes in an external Reset source. This external Reset source is

selected for each timer with the corresponding TxRST register. This source can control starting and stopping of the

timer, as well as resetting the timer, depending on which mode the timer is in. Reset source selections are shown in

the following table.

Refer to the External Reset Sources table for further information.

Timer2 Interrupt

Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches with the

selected postscaler value (OUTPS bits of T2CON register). The interrupt is enabled by setting the TMR2IE interrupt

enable bit. Interrupt timing is illustrated in the figure below.

Figure 20-2.ꢀTimer2 Prescaler, Postscaler, and Interrupt Timing Diagram

Rev. 10-000205A

4/7/2016

CKPS

PRx

0b010

1

OUTPS

0b0001

TMRx_clk

TMRx

0

1

0

1

0

1

0

TMRx_postscaled

(1)

(2)

(1)

TMRxIF

Note:ꢀ

1. Setting the interrupt flag is synchronized with the instruction clock.

2. Cleared by software.

20.5

20.6

PSYNC bit

Setting the PSYNC bit synchronizes the prescaler output to F_OSC/4. Setting this bit is required for reading the Timer2

counter register while the selected Timer clock is asynchronous to F_OSC/4.

Note:ꢀ Setting PSYNC requires that the output of the prescaler is slower than F_OSC/4. Setting PSYNC when the

output of the prescaler is greater than or equal to F_OSC/4 may cause unexpected results.

CSYNC bit

All bits in the Timer2 SFRs are synchronized to F_OSC/4 by default, not the Timer2 input clock. As such, if the Timer2

input clock is not synchronized to F_OSC/4, it is possible for the Timer2 input clock to transition at the same time as the

DS40002002B-page 295

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

ON bit is set in software, which may cause undesirable behavior and glitches in the counter. Setting the CSYNC bit

remedies this problem by synchronizing the ON bit to the Timer2 input clock instead of F_OSC/4. However, as this

synchronization uses an edge of the TMR2 input clock, up to one input clock cycle will be consumed and not counted

by the Timer2 when CSYNC is set. Conversely, clearing the CSYNC bit synchronizes the ON bit to F_OSC/4, which

does not consume any clock edges, but has the previously stated risk of glitches.

20.7

Operating Modes

The mode of the timer is controlled by the MODE bits of the T2HLT register. Edge-Triggered modes require six Timer

clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer

clock periods long. External triggers are ignored while in Debug mode.

Table 20-1.ꢀOperating Modes Table

MODE[4:0]

[4:3] [2:0]

000

Timer Control

Output

Operation

Mode

Operation

Start

Reset

—

Stop

Software gate (Figure 20-3)

ON = 1

ON = 0

ON = 1and

TMRx_ers = 1

—

ON = 0or

TMRx_ers = 0

Hardware gate, active-high

(Figure 20-4)

001

010

Period Pulse

ON = 1and

TMRx_ers = 0

—

ON = 0or

TMRx_ers = 1

Hardware gate, active-low

011

00

Rising or falling edge Reset

Rising edge Reset (Figure 20-5)

Falling edge Reset

TMRx_ers ↕

TMRx_ers ↑

TMRx_ers ↓

Free-

Running Period

100

ON = 0

Period

Pulse

101

with

Hardware

Reset

ON = 1

ON = 0or

TMRx_ers = 0

110

TMRx_ers = 0

Low level Reset

High level Reset (Figure 20-6)

ON = 0or

TMRx_ers = 1

111

000

001

TMRx_ers = 1

One-shot

Software start (Figure 20-7)

—

ON = 1and

TMRx_ers ↑

Rising edge start (Figure 20-8)

Edge-

Triggered Start

ON = 1and

TMRx_ers ↓

010

011

Falling edge start

Any edge start

—

(Note 1)

ON = 0

ON = 1and

TMRx_ers ↕

—

or

Next clock after

TMRx = PRx

(Note 2)

01

One-shot

ON = 1and

TMRx_ers ↑

Rising edge start and

Rising edge Reset (Figure 20-9)

100

TMRx_ers ↑

TMRx_ers ↓

TMRx_ers = 0

TMRx_ers = 1

Edge-

Triggered Start

ON = 1and

TMRx_ers ↓

Falling edge start and

Falling edge Reset

101

110

111

and

ON = 1and

TMRx_ers ↑

Rising edge start and

Low level Reset (Figure 20-10)

Hardware Reset

(Note 1)

ON = 1and

TMRx_ers ↓

Falling edge start and

High level Reset

DS40002002B-page 296

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

...........continued

Mode

MODE[4:0]

[4:3] [2:0]

000

Timer Control

Output

Operation

Start

Reset

Stop

Reserved

ON = 1and

TMRx_ers ↑

Rising edge start

(Figure 20-11)

001

010

011

—

ON = 0

Edge-

Triggered

or

Mono-stable

ON = 1and

TMRx_ers ↓

Next clock after

TMRx = PRx

(Note 3)

Falling edge start

Any edge start

Start

(Note 1)

ON = 1and

TMRx_ers ↕

10

100

Reserved

ON = 1and

101

Level

Triggered

High level start and

110

TMRx_ers = 0

TMRx_ers = 1

Low level Reset (Figure 20-12) TMRx_ers = 1

ON = 0or

Held in Reset

Start

and

One-shot

ON = 1and

TMRx_ers = 0

Low level start and

High level Reset

(Note 2)

111

Hardware Reset

11

Reserved

xxx

Reserved

Note:ꢀ

1. If ON = 0then an edge is required to restart the timer after ON = 1.

2. When T2TMR = T2PR then the next clock clears ON and stops T2TMR at 0x00.

3. When T2TMR = T2PR then the next clock stops T2TMR at 0x00 but does not clear ON.

20.8

Operation Examples

Unless otherwise specified, the following notes apply to the following timing diagrams:

•

Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the T2CON register are

cleared).

•

The diagrams illustrate any clock except F_OSC/4 and show clock-sync delays of at least two full cycles for both

ON and Timer2_ers. When using F_OSC/4, the clock-sync delay is at least one instruction period for Timer2_ers;

ON applies in the next instruction period.

•

ON and Timer2_ers are somewhat generalized, and clock-sync delays may produce results that are slightly

different than illustrated.

The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of

the CCP module as described in the “PWM Overview” section. The signals are not a part of the Timer2 module.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.1 Software Gate Mode

This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1and

does not increment when ON = 0. When the TMRx count equals the PRx period count the timer resets on the next

clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 20-3. With

PRx = 5, the counter advances until TMRx = 5, and goes to zero with the next clock.

DS40002002B-page 297

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-3.ꢀSoftware Gate Mode Timing Diagram (MODE = 00000)

Rev. 10-000195B

5/30/2014

MODE

TMRx_clk

Instruction⁽¹⁾

ON

0b00000

BSF

BCF

BSF

PRx

5

TMRx

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

0

1

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note:ꢀ

1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.2 Hardware Gate Mode

The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can

also gate the timer. When used with the CCP, the gating extends the PWM period. If the timer is stopped when the

PWM output is high, then the duty cycle is also extended.

When MODE[4:0] = 00001then the timer is stopped when the external signal is high. When MODE[4:0] = 00010,

then the timer is stopped when the external signal is low.

Figure 20-4 illustrates the Hardware Gating mode for MODE[4:0] = 00001in which a high input level starts the

counter.

DS40002002B-page 298

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-4.ꢀHardware Gate Mode Timing Diagram (MODE = 00001)

Rev. 10-000 196B

5/30/201 4

MODE

TMRx_clk

TMRx_ers

PRx

0b00001

5

TMRx

0

1

2

3

4

5

0

1

2

3

4

5

0

1

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.3 Edge-Triggered Hardware Limit Mode

In Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches the period

count. Three types of Resets are possible:

•

Reset on rising or falling edge (MODE[4:0] = 00011)

Reset on rising edge (MODE[4:0] = 00100)

Reset on falling edge (MODE[4:0] = 00101)

When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and

restarts the PWM pulse after a two clock delay. Refer to Figure 20-5.

DS40002002B-page 299

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-5.ꢀEdge-Triggered Hardware Limit Mode Timing Diagram

(MODE = 00100)

Rev. 10-000 197B

5/30/201 4

MODE

TMRx_clk

PRx

0b00100

5

Instruction⁽¹⁾

ON

BSF

BCF BSF

TMRx_ers

TMRx

0

1

2

0

1

2

3

4

3

5

0

1

2

3

4

5

0

1

TMRx_postscaled

PWM Duty

Cycle

PWM Output

Note:ꢀ

1. BSFand BCFrepresent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.4 Level-Triggered Hardware Limit Mode

In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal

TMRx_ers, as shown in Figure 20-6. Selecting MODE[4:0] = 00110will cause the timer to reset on a low level

external signal. Selecting MODE[4:0] = 00111will cause the timer to reset on a high level external signal. In the

example, the counter is reset while TMRx_ers = 1. ON is controlled by BSFand BCFinstructions. When ON = 0the

external signal is ignored.

When the CCP uses the timer as the PWM time base then the PWM output will be set high when the timer starts

counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the

timer count matches the PRx value or two clock periods after the external Reset signal goes true and stays true.

The timer starts counting, and the PWM output is set high, on either the clock following the PRx match or two clocks

after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to

match the CCPRx pulse width value. If the external Reset signal goes true while the PWM output is high then the

PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx

value.

DS40002002B-page 300

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-6.ꢀLevel-Triggered Hardware Limit Mode Timing Diagram

(MODE = 00111)

Rev. 10-000198B

5/30/2014

MODE

TMRx_clk

PRx

0b00111

5

Instruction⁽¹⁾

ON

BSF

BCF

BSF

TMRx_ers

TMRx

0

1

2

0

1

2

3

4

5

0

1

2

3

4

5

0

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note:ꢀ

1. BSFand BCFrepresent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.5 Software Start One-Shot Mode

In One-Shot mode the timer resets and the ON bit is cleared when the timer value matches the PRx period value.

The ON bit must be set by software to start another timer cycle. Setting MODE[4:0] = 01000selects One-Shot mode

which is illustrated in Figure 20-7. In the example, ON is controlled by BSFand BCFinstructions. In the first case, a

BSFinstruction sets ON and the counter runs to completion and clears ON. In the second case, a BSFinstruction

starts the cycle, BCF/BSFinstructions turn the counter off and on during the cycle, and then it runs to completion.

When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts concurrent

with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive

will terminate when the timer value matches the CCPRx pulse width value. The PWM drive will remain off until

software sets the ON bit to start another cycle. If the software clears the ON bit after the CCPRx match but before the

PRx match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing

cycle can only be initiated by setting the ON bit after it has been cleared by a PRx period count match.

DS40002002B-page 301

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-7.ꢀSoftware Start One-Shot Mode Timing Diagram (MODE = 01000)

Rev. 10-000199B

4/7/2016

MODE

TMRx_clk

PRx

0b01000

5

Instruction⁽¹⁾

ON

BSF

BCF

BSF

TMRx

0

1

2

3

4

5

0

1

2

3

4

5

0

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note:ꢀ

1. BSFand BCFrepresent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.6 Edge-Triggered One-Shot Mode

The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set,

and clear the ON bit when the timer matches the PRx period value. The following edges will start the timer:

•

Rising edge (MODE[4:0] = 01001)

Falling edge (MODE[4:0] = 01010)

Rising or Falling edge (MODE[4:0] = 01011)

If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume

counting. Figure 20-8 illustrates operation in the rising edge One-Shot mode.

When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will activate the

PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay

deactivated when the timer halts at the PRx period count match.

DS40002002B-page 302

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-8.ꢀEdge-Triggered One-Shot Mode Timing Diagram (MODE = 01001)

Rev. 10-000200B

5/19/2016

MODE

TMRx_clk

PRx

0b01001

5

Instruction⁽¹⁾

ON

BSF

BCF

TMRx_ers

TMRx

0

1

2

3

4

5

0

1

2

CCP_pset

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note:ꢀ

1. BSFand BCFrepresent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.7 Edge-Triggered Hardware Limit One-Shot Mode

In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit

is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The

counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are

as follows:

•

Rising edge start and Reset (MODE[4:0] = 01100)

Falling edge start and Reset (MODE[4:0] = 01101)

The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will

have no effect until after software sets the ON bit. Figure 20-9 illustrates the rising edge hardware limit one-shot

operation.

When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset

edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width

value and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the

timer before the match occurs.

DS40002002B-page 303

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-9.ꢀEdge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01100)

Rev. 10-000201B

4/7/2016

MODE

TMRx_clk

PRx

0b01100

5

Instruction⁽¹⁾

ON

BSF

TMRx_ers

TMRx

0

1

2

3

4

5

0

1

2

0

1

2

3

4

5

0

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note:ꢀ

1. BSFand BCFrepresent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.8 Level Reset, Edge-Triggered Hardware Limit One-Shot Modes

In Level -Triggered One-Shot mode the timer count is reset on the external signal level and starts counting on the

rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are

selected as follows:

•

Low Reset level (MODE[4:0] = 01110)

High Reset level (MODE[4:0] = 01111)

When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is

cleared by either a PRx match or by software control, a new external signal edge is required after the ON bit is set to

start the counter.

When Level-Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation, the PWM drive

goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count

equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the PRx

period count match.

DS40002002B-page 304

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-10.ꢀLow Level Reset, Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE =

01110)

Rev. 10-000202B

4/7/2016

MODE

TMRx_clk

PRx

0b01110

5

Instruction⁽¹⁾

ON

BSF

TMRx_ers

TMRx

0

1

2

3

4

5

0

1

0

1

2

3

4

5

0

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note:ꢀ

1. BSFand BCFrepresent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.9 Edge-Triggered Monostable Modes

The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON

bit is set, and stop incrementing the timer when the timer matches the PRx period value. The following edges will

start the timer:

•

Rising edge (MODE[4:0] = 10001)

Falling edge (MODE[4:0] = 10010)

Rising or Falling edge (MODE[4:0] = 10011)

When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation, the PWM drive

goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches the

PRx value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP

PWM.

DS40002002B-page 305

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-11.ꢀRising Edge-Triggered Monostable Mode Timing Diagram (MODE = 10001)

Rev. 10-000203A

4/7/2016

MODE

TMRx_clk

PRx

0b10001

5

Instruction⁽¹⁾

ON

BSF

BCF

BSF

BCF

BSF

TMRx_ers

TMRx

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

0

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note:ꢀ

1. BSFand BCFrepresent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.8.10 Level-Triggered Hardware Limit One-Shot Modes

The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset on an external Reset level and start

counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external

signal is not in Reset or the ON bit is set, then the other signal being set/made active will start the timer. Reset levels

are selected as follows:

•

Low Reset level (MODE[4:0] = 10110)

High Reset level (MODE[4:0] = 10111)

When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is

cleared by either a PRx match or by software control, the timer will stay in Reset until both the ON bit is set and the

external signal is not at the Reset level.

When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM operation, the

PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts

the timer.

DS40002002B-page 306

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

Figure 20-12.ꢀLevel-Triggered Hardware Limit one-Shot Mode Timing Diagram (MODE = 10110)

Rev. 10-000204A

4/7/2016

MODE

TMR2_clk

PRx

0b10110

5

Instruction⁽¹⁾

ON

BSF

BCF

BSF

TMR2_ers

TMRx

0

1

2

3

4

5

0

1

2

3

0

1

2

3

4

5

0

TMR2_postscaled

PWM Duty

Cycle

‘D3

PWM Output

Note:ꢀ

1. BSFand BCFrepresent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON

bit of TxCON. CPU execution is asynchronous to the timer clock input.

Related Links

22.4 PWM Overview

24. PWM - Pulse-Width Modulation

20.9

Timer2 Operation During Sleep

When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the T2TMR and

T2PR registers will remain unchanged while processor is in Sleep mode.

When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. If any

internal oscillator is selected as the clock source, it will stay active during Sleep mode.

DS40002002B-page 307

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.10 Register Summary - Timer2

Offset

Name

Bit Pos.

0x00

...

Reserved

0x028B

0x028C

0x028D

0x028E

0x028F

0x0290

0x0291

0x0292

0x0293

0x0294

0x0295

0x0296

0x0297

0x0298

0x0299

0x029A

0x029B

0x029C

0x029D

T2TMR

T2PR

7:0

TxTMR[7:0]

TxPR[7:0]

T2CON

T2HLT

ON

CKPS[2:0]

CSYNC

OUTPS[3:0]

MODE[4:0]

CS[3:0]

PSYNC

CPOL

T2CLKCON

T2RST

RSEL[3:0]

T4TMR

T4PR

TxTMR[7:0]

TxPR[7:0]

T4CON

T4HLT

ON

CKPS[2:0]

CSYNC

OUTPS[3:0]

MODE[4:0]

CS[3:0]

PSYNC

T4CLKCON

T4RST

RSEL[3:0]

T6TMR

T6PR

TxTMR[7:0]

TxPR[7:0]

T6CON

T6HLT

ON

CKPS[2:0]

CSYNC

OUTPS[3:0]

MODE[4:0]

CS[3:0]

PSYNC

T6CLKCON

T6RST

RSEL[3:0]

20.11 Register Definitions: Timer2 Control

Notice:ꢀ References to module Timer2 apply to all the even numbered timers on this device. (Timer2,

Timer4, etc.)

Related Links

1.4.2.2 Long Bit Names

DS40002002B-page 308

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.11.1 TxTMR

Name:ꢀ

Offset:ꢀ

TxTMR

0x28C,0x292,0x298

Timer Counter Register

Bit

7

6

5

4

3

2

1

0

TxTMR[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – TxTMR[7:0]ꢀTimerx Counter bits

DS40002002B-page 309

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.11.2 TxPR

Name:ꢀ

Offset:ꢀ

TxPR

0x28D,0x293,0x299

Timer Period Register

Bit

7

6

5

4

3

2

1

0

TxPR[7:0]

Access

Reset

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Bits 7:0 – TxPR[7:0]ꢀTimer Period Register bits

Value

1111

Description

The timer restarts at ‘0’ when TxTMR reaches TxPR value

1111 -

0000

DS40002002B-page 310

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.11.3 TxCON

Name:ꢀ

Offset:ꢀ

TxCON

0x28E,0x294,0x29A

Timerx Control Register

Bit

7

ON

6

5

CKPS[2:0]

R/W

4

3

2

1

0

OUTPS[3:0]

Access

Reset

R/W/HC

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7 – ON

Timer On bit⁽¹⁾

Value

Description

1

Timer is on

0

Timer is off: all counters and state machines are reset

Bits 6:4 – CKPS[2:0]ꢀTimer Clock Prescale Select bits

Value

111

110

101

100

011

010

001

000

Description

1:128 Prescaler

1:64 Prescaler

1:32 Prescaler

1:16 Prescaler

1:8 Prescaler

1:4 Prescaler

1:2 Prescaler

1:1 Prescaler

Bits 3:0 – OUTPS[3:0]ꢀTimer Output Postscaler Select bits

Value

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Description

1:16 Postscaler

1:15 Postscaler

1:14 Postscaler

1:13 Postscaler

1:12 Postscaler

1:11 Postscaler

1:10 Postscaler

1:9 Postscaler

1:8 Postscaler

1:7 Postscaler

1:6 Postscaler

1:5 Postscaler

1:4 Postscaler

1:3 Postscaler

1:2 Postscaler

1:1 Postscaler

Note:ꢀ

1. In certain modes, the ON bit will be auto-cleared by hardware. See Table 20-1.

DS40002002B-page 311

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.11.4 TxHLT

Name:ꢀ

Offset:ꢀ

TxHLT

0x28F,0x295,0x29B

Timer Hardware Limit Control Register

Bit

7

PSYNC

R/W

0

6

CPOL

R/W

0

5

CSYNC

R/W

0

4

3

2

MODE[4:0]

R/W

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7 – PSYNC

Timer Prescaler Synchronization Enable bit^{(1, 2)}

Value

1

0

Description

Timer Prescaler Output is synchronized to F_OSC/4

Timer Prescaler Output is not synchronized to F_OSC/4

Bit 6 – CPOL

Timer Clock Polarity Selection bit⁽³⁾

Value

Description

1

0

Falling edge of input clock clocks timer/prescaler

Rising edge of input clock clocks timer/prescaler

Bit 5 – CSYNC

Timer Clock Synchronization Enable bit^{(4, 5)}

Value

Description

1

0

ON bit is synchronized to timer clock input

ON bit is not synchronized to timer clock input

Bits 4:0 – MODE[4:0]

Timer Control Mode Selection bits^{(6, 7)}

Value

Description

00000 to

See Table 20-1

11111

Note:ꢀ

1. Setting this bit ensures that reading TxTMR will return a valid data value.

2. When this bit is ‘1’, Timer cannot operate in Sleep mode.

3. CKPOL should not be changed while ON = 1.

4. Setting this bit ensures glitch-free operation when the ON is enabled or disabled.

5. When this bit is set then the timer operation will be delayed by two input clocks after the ON bit is set.

6. Unless otherwise indicated, all modes start upon ON = 1and stop upon ON = 0(stops occur without affecting

the value of TxTMR).

7. When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode.

DS40002002B-page 312

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.11.5 TxCLKCON

Name:ꢀ

Offset:ꢀ

TxCLKCON

0x290,0x296,0x29C

Timer Clock Source Selection Register

Bit

7

6

5

4

3

2

1

0

CS[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 3:0 – CS[3:0]ꢀTimer Clock Source Selection bits

Table 20-2.ꢀClock Source Selection

Clock Source

Timer4

CS[3:0]

Timer2

Timer6

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Reserved

CLC4_out

Reserved

CLC4_out

CLC3_out

CLC2_out

CLC1_out

ZCD1_output

NCO1_out

CLKR

CLC4_out

CLC3_out

CLC2_out

CLC1_out

ZCD1_output

NCO1_out

ZCD1_output

NCO1_out

CLKR

SOSC

MFINTOSC(31.25 kHz)

MFINTOSC(500 kHz)

LFINTOSC

HFINTOSC(32 MHz)

F_OSC

MFINTOSC(31.25 kHz)

MFINTOSC(500 kHz)

LFINTOSC

HFINTOSC(32 MHz)

F_OSC

MFINTOSC(31.25 kHz)

MFINTOSC(500 kHz)

LFINTOSC

HFINTOSC(32 MHz)

F_OSC

F_OSC/4

T2CKIPPS

T4CKIPPS

T6CKIPPS

Value

n

Description

See Clock Source Selection table.

DS40002002B-page 313

Datasheet

PIC16(L)F18425/45

TMR2 - Timer2 Module

20.11.6 TxRST

Name:ꢀ

Offset:ꢀ

TxRST

0x291,0x297,0x29D

Timer External Reset Signal Selection Register

Bit

7

6

5

4

3

2

1

0

RSEL[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 3:0 – RSEL[3:0]

External Reset Source Selection Bits

Table 20-3.ꢀExternal Reset Sources

Reset Source

TMR4

RSEL[3:0]

TMR2

TMR6

1111

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Reserved

CLC4_out

CLC3_out

CLC2_out

CLC1_out

ZCD1_output

C2OUT_sync

C1OUT_sync

PWM7_out

PWM6_out

CCP4_out

CCP3_out

CCP2_out

CCP1_out

T2INPPS

Reserved

CLC4_out

CLC3_out

CLC2_out

CLC1_out

ZCD1_output

C2OUT_sync

C1OUT_sync

PWM7_out

PWM6_out

CCP4_out

CCP3_out

CCP2_out

CCP1_out

T4INPPS

CLC4_out

CLC3_out

CLC2_out

CLC1_out

ZCD1_output

C2OUT_sync

C1OUT_sync

PWM7_out

PWM6_out

CCP4_out

CCP3_out

CCP2_out

CCP1_out

T6INPPS

Value

n

Description

See External Reset Sources table

DS40002002B-page 314

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.

SMT - Signal Measurement Timer

The SMT is a 24-bit counter with advanced clock and gating logic, which can be configured for measuring a variety of

digital signal parameters such as pulse width, frequency and duty cycle, and the time difference between edges on

two signals.

Features of the SMT include:

•

24-bit timer/counter

Two 24-bit measurement capture registers

One 24-bit period match register

Multi-mode operation, including relative timing measurement

Interrupt on period match and acquisition complete

Multiple clock, signal and window sources

Below is the block diagram for the SMT module.

Figure 21-1.ꢀSignal Measurement Timer Block Diagram

Rev. 10-000161E

11/13/2018

Period Latch

SMTxPR

Set SMTxPRAIF

SMT

Clock

Sync

SMT_window

Circuit

Control

Logic

Set SMTxIF

Comparator

SMT

Clock

Sync

SMT_signal

Circuit

24-bit

Buffer

SMTxCPR

SMTxCPW

Reset

SMTxTMR

24-bit

Buffer

Enable

SMT

Clock

Window Latch

Set SMTxPWAIF

Prescaler

Sources

CSEL

21.1

SMT Operation

21.1.1 Clock Source Selection

The SMT clock source is selected by configuring the CSEL bits in the SMTxCLK register. The clock source can be

prescaled using the PS bits of the SMTxCON0 register. The prescaled clock source is used to clock both the counter

and any synchronization logic used by the module. Refer the table below for possible clock source options.

The polarity of the clock source can be selected using the CPOL bit in the SMTxCON0 register.

21.1.2 Signal and Window Source Selection

The SMT signal and window sources are selected by configuring the SSEL bits in the SMTxSIG register and the

WSEL bits in the SMTxWIN register. Refer the tables below for the possible selections.

DS40002002B-page 315

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

The polarity of the signal and window sources can be selected using the SPOL and WPOL bits in the SMTxCON0

register.

21.1.3 Time Base

The SMTxTMR is the 24-bit counter/timer used for measurement in each of the modes of the SMT. It can be reset to

0x000000 by setting the RST bit of the SMTxSTAT register. It can be written to and read by software. It is not guarded

for atomic access, therefore reads and writes to the SMTxTMR should be made when the GO = 0.

The counter can be prevented from a rollover using the STP bit in the SMTxCON0 register. When STP = 1,

SMTxTMR will remain equal to SMTxPR. When STP = 0, SMTxTMR resets to 0x000000.

21.1.4 Capture Pulse Width and Period Registers

The SMTxCPW and SMTxCPR registers are used to latch in the value of the SMTxTMR based on the mode of SMT

operation. These registers can also be updated with the current value of the SMTxTMR value by setting the CPWUP

and CPRUP bits of the SMTxSTAT register, respectively.

21.1.5 Status Information

The SMT provides input status information for the user without requiring the need to deal with the polarity of the

incoming signals.

Go Status: Timer run status is determined by the TS bit of the SMTxSTAT register, and will be delayed in time by

synchronizer delays in non-Counter modes.

Signal Status:Signal status is determined by the AS bit of the SMTxSTAT register. This bit is used in all modes

except Window Measure, Time of Flight and Capture modes, and is only valid when TS = 1, and will be delayed in

time by synchronizer delays in non-Counter modes.

Window Status: Window status is determined by the WS bit of the SMTxSTAT register. This bit is only used in

Windowed Measure, Gated Counter and Gated Window Measure modes, and is only valid when TS = 1, and will be

delayed in time by synchronizer delays in non-Counter modes.

21.1.6 Modes of Operation

The mode of operation is selected by configuring MODE bits in SMTxCON1 register. The following sections provide

descriptions and examples of how the modes can be used. Note that all waveforms assume WPOL/SPOL/CPOL = 0.

For all modes, the REPEAT bit controls whether the acquisition is repeated or single. When REPEAT = 0(Single

Acquisition mode), the timer will stop incrementing and the SMTxGO bit will be reset upon the completion of an

acquisition. Otherwise, the timer will continue and allow for continued acquisitions to overwrite the previous ones until

the timer is stopped in software.

21.1.6.1 Timer Mode

Timer mode is the basic mode of operation where the SMTxTMR is used as a 24-bit timer. No data acquisition takes

place in this mode. The timer increments as long as the SMTxGO bit has been set by software. No SMT window or

SMT signal events affect the SMTxGO bit. Everything is synchronized to the SMT clock source. When the timer

experiences a period match (SMTxTMR = SMTxPR), SMTxTMR is reset and the period match interrupt trips. See

figure below.

DS40002002B-page 316

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-2.ꢀTimer Mode Timing Diagram

Rev. 10-000 174A

12/19/201 3

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxPR

11

SMTxTMR

SMTxIF

0

1

2

3

4

5

6

7

8

9

10 11

0

1

2

3

4

5

6

7

8

9

21.1.6.2 Gated Timer Mode

Gated Timer mode uses the signal input (SSEL) to control whether or not the SMTxTMR will increment. Upon a

falling edge of the signal, the SMTxCPW register will update to the current value of the SMTxTMR. Example

waveforms for both repeated and single acquisitions are provided in figures below.

Figure 21-3.ꢀGated Timer Mode, Repeat Acquisition Timing Diagram

Rev. 10-000 176A

12/19/201 3

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxPR

SMTxTMR

0xFFFFFF

0

1

2

3

4

5

6

7

SMTxCPW

SMTxPWAIF

5

7

DS40002002B-page 317

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-4.ꢀGated Timer Mode, Single Acquisition Timing Diagram

Rev. 10-000 175A

12/19/201 3

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxPR

SMTxTMR

0xFFFFFF

0

1

2

3

4

5

SMTxCPW

SMTxPWAIF

5

21.1.6.3 Period and Duty Cycle Measurement Mode

In this mode, either the duty cycle or period (depending on polarity) of the input signal can be acquired relative to the

SMT clock. The CPW register is updated on a falling edge of the signal, and the CPR register is updated on a rising

edge of the signal, along with the SMTxTMR resetting to 0x000001. In addition, the SMTxGO bit is reset on a rising

edge when the SMT is in single acquisition mode. See figures below.

Figure 21-5.ꢀPeriod and Duty-Cycle, Repeat Acquisition Mode Timing Diagram

Rev. 10-000 177A

12/19/201 3

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

SMTxCPW

SMTxCPR

0

1

2

3

4

5

6

7

8

9

5

10 11

1

2

3

4

5

2

11

SMTxPWAIF

SMTxPRAIF

DS40002002B-page 318

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-6.ꢀPeriod and Duty-Cycle, Single Acquisition Mode Timing Diagram

Rev. 10-000 178A

12/19/201 3

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

0

1

2

3

4

5

6

7

8

9 10 11

SMTxCPW

5

SMTxCPR

11

SMTxPWAIF

SMTxPRAIF

21.1.6.4 High and Low Measurement Mode

This mode measures the high and low pulse time of the signal relative to the SMT clock. It begins incrementing the

SMTxTMR on a rising edge on the input signal, then updates the SMTxCPW register with the value and resets the

SMTxTMR on a falling edge, starting to increment again. Upon observing another rising edge, it updates the

SMTxCPR register with its current value and once again resets the SMTxTMR value and begins incrementing again.

See the figures below.

Figure 21-7.ꢀHigh and Low Measurement Mode, Repeat Acquisition Timing Diagram

Rev. 10-000 180A

12/19/201 3

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

SMTxCPW

SMTxCPR

0

1

2

3

4

5

1

2

3

4

5

6

1

2

1

2

3

2

6

SMTxPWAIF

SMTxPRAIF

DS40002002B-page 319

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-8.ꢀHigh and Low Measurement Mode, Single Acquisition Timing Diagram

Rev. 10-000 179A

12/19/201 3

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

0

1

2

3

4

5

1

2

3

4

5

6

SMTxCPW

5

SMTxCPR

6

SMTxPWAIF

SMTxPRAIF

21.1.6.5 Windowed Measurement Mode

This mode measures the duration of the window input (WSEL) to the SMT. It begins incrementing the timer on a

rising edge of the window input and updates the SMTxCPR register with the value of the timer and resets the timer

on a second rising edge. See figures below.

Figure 21-9.ꢀWindowed Measurement Mode, Repeat Acquisition Timing Diagram

Rev. 10-000 182A

12/19/201 3

SMTxWIN

SMTxWIN_sync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

0

1

2

3

4

5

6

7

8

9

10 11 12

1

2

3

4

5

6

7

8

1

2

3

4

SMTxCPR

12

8

SMTxPRAIF

DS40002002B-page 320

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-10.ꢀWindowed Measurement Mode, Single Acquisition Timing Diagram

Rev. 10-000 181A

12/19/201 3

SMTxWIN

SMTxWIN_sync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

0

1

2

3

4

5

6

7

8

9 10 11 12

SMTxCPR

12

SMTxPRAIF

21.1.6.6 Gated Window Measurement Mode

This mode measures the duty cycle of the signal input over a known input window. It does so by incrementing the

timer on each pulse of the clock signal while the signal input is high, updating the SMTxCPR register and resetting

the timer on every rising edge of the window input after the first. See figures below.

Figure 21-11.ꢀGated Windowed Measurement Mode, Repeat Acquisition Timing Diagram

Rev. 10-000 184A

12/19/201 3

SMTxWIN

SMTxWIN_sync

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

0

1

2

3

4

5

6

0

1

2

3

0

SMTxCPR

6

3

SMTxPRAIF

DS40002002B-page 321

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-12.ꢀGated Windowed Measurement Mode, Single Acquisition Timing Diagram

Rev. 10-000 183A

12/19/201 3

SMTxWIN

SMTxWIN_sync

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

0

1

2

3

4

5

6

SMTxCPR

6

SMTxPRAIF

21.1.6.7 Time of Flight Measurement Mode

This mode measures the time interval between a rising edge on the window input and a rising edge on the signal

input, beginning to increment the timer upon observing a rising edge on the window input, while updating the

SMTxCPR register and resetting the timer upon observing a rising edge on the signal input. In the event of two rising

edges of the window signal without a signal rising edge, it will update the SMTxCPW register with the current value of

the timer and reset the timer value. See figures below.

Figure 21-13.ꢀTime of Flight Mode, Repeat Acquisition Timing Diagram

Rev. 10-000186A

4/22/2016

SMTxWIN

SMTxWIN_sync

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

SMTxCPW

SMTxCPR

0

1

2

3

4

5

1

2

3

4

5

6

7

8

9

10 11 12 13

1

2

13

4

SMTxPWAIF

SMTxPRAIF

DS40002002B-page 322

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-14.ꢀTime of Flight Mode, Single Acquisition Timing Diagram

Rev. 10-000185A

4/26/2016

SMTxWIN

SMTxWIN_sync

SMTx_signal

SMTx_signalsync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

0

1

2

3

4

5

SMTxCPW

SMTxCPR

4

SMTxPWAIF

SMTxPRAIF

21.1.6.8 Capture Mode

This mode captures the timer value based on a rising or falling edge on the window input and triggers an interrupt.

This mimics the capture feature of a CCP module. The timer begins incrementing upon the SMTxGO bit being set,

and updates the value of the SMTxCPR register on each rising edge of window signal, and updates the value of the

SMTxCPW register on each falling edge of the window signal. The timer is not reset by any hardware conditions in

this mode and must be reset by software, if desired. See figures below.

Figure 21-15.ꢀCapture Mode, Repeat Acquisition Timing Diagram

Rev. 10-000 188A

12/19/201 3

SMTxWIN

SMTxWIN_sync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

SMTxCPW

SMTxCPR

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

19

3

32

31

2

18

SMTxPWAIF

SMTxPRAIF

DS40002002B-page 323

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-16.ꢀCapture Mode, Single Acquisition Timing Diagram

Rev. 10-000 187A

12/19/201 3

SMTxWIN

SMTxWIN_sync

SMTx Clock

SMTxEN

SMTxGO

SMTxGO_sync

SMTxTMR

SMTxCPW

SMTxCPR

0

1

2

3

2

SMTxPWAIF

SMTxPRAIF

21.1.6.9 Counter Mode

This mode increments the timer on each pulse of the signal input. This mode is asynchronous to the SMT clock and

uses the signal input as a time source. The SMTxCPW register will be updated with the current SMTxTMR value on

the falling edge of the window input. See figure below.

Figure 21-17.ꢀCounter Mode Timing Diagram

Rev. 10-000189A

4/12/2016

SMTxWIN

SMTx_signal

SMTxEN

SMTxGO

SMTxTMR

SMTxCPW

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

12

27

25

21.1.6.10 Gated Counter Mode

This mode counts pulses on the signal input, gated by the window input. It begins incrementing the timer upon seeing

a rising edge of the window input and updates the SMTxCPW register upon a falling edge on the window input. See

figures below.

DS40002002B-page 324

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-18.ꢀGated Counter Mode, Repeat Acquisition Timing Diagram

Rev. 10-000190A

12/18/2013

SMTxWIN

SMTx_signal

SMTxEN

SMTxGO

SMTxTMR

SMTxCPW

SMTxPWAIF

0

1

2

3

4

5

6

7

8

9

10 11 12

13

8

Figure 21-19.ꢀGated Counter Mode, Single Acquisition Timing Diagram

Rev. 10-000191A

12/18/2013

SMTxWIN

SMTx_signal

SMTxEN

SMTxGO

SMTxTMR

SMTxCPW

0

1

2

3

4

5

6

7

8

SMTxPWAIF

21.1.6.11 Windowed Counter Mode

This mode counts pulses on the signal input, within a window dictated by the window input. It begins counting upon

seeing a rising edge of the window input, updates the SMTxCPW register on a falling edge of the window input, and

updates the SMTxCPR register on each rising edge of the window input after the first. See figures below.

Figure 21-20.ꢀWindowed Counter Mode, Repeat Acquisition Timing Diagram

Rev. 10-000192A

12/18/2013

SMTxWIN

SMTx_signal

SMTxEN

SMTxGO

SMTxTMR

SMTxCPW

SMTxCPR

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

9

1

2

3

4

5

16

SMTxPWAIF

SMTxPRAIF

DS40002002B-page 325

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

Figure 21-21.ꢀWindowed Counter Mode, Single Acquisition Timing Diagram

Rev. 10-000193A

12/18/2013

SMTxWIN

SMTx_signal

SMTxEN

SMTxGO

SMTxTMR

SMTxCPW

SMTxCPR

SMTxPWAIF

SMTxPRAIF

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

9

16

21.1.7 Interrupts

The SMT has three interrupts:

•

Pulse Width Acquisition Interrupt (SMTxPWAIF): Interrupt triggers when SMTxCPW is updated

Period Acquisition Interrupt (SMTxPRAIF): Interrupt triggers when SMTxCPR is updated

Counter Period Match Interrupt (SMTxIF): Interrupt triggers when SMTxTMR equals SMTxPR

Each of the above interrupts can be enabled/disabled using the corresponding bits in the PIEx register.

21.1.8 Operation During Sleep

The SMT can operate during Sleep, Idle, and Doze modes; provided that the clock and signal sources continue to

function. System clock sources, like F_OSCand F_OSC/4, are disabled in Sleep.

DS40002002B-page 326

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.2

Register Summary - SMT Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x048B

7:0

15:8

23:16

7:0

TMR[7:0]

0x048C

0x048F

0x0492

0x0495

SMT1TMR

SMT1CPR

SMT1CPW

SMT1PR

TMR[15:8]

TMR[23:16]

CPR[7:0]

15:8

23:16

7:0

CPR[15:8]

CPR[23:16]

CPW[7:0]

CPW[15:8]

CPW[23:16]

PR[7:0]

15:8

23:16

7:0

15:8

23:16

7:0

PR[15:8]

PR[23:16]

0x0498

0x0499

0x049A

0x049B

0x049C

0x049D

SMT1CON0

SMT1CON1

SMT1STAT

SMT1CLK

SMT1SIG

EN

GO

STP

WPOL

SPOL

CPOL

MODE[3:0]

PS[1:0]

7:0

REPEAT

CPWUP

7:0

CPRUP

RST

TS

WS

CSEL[2:0]

AS

7:0

SSEL[4:0]

WSEL[4:0]

SMT1WIN

7:0

21.3

Register Definitions: SMT Control

DS40002002B-page 327

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.1 SMTxTMR

Name:ꢀ

Offset:ꢀ

SMTxTMR

0x048C

SMT Timer Register

Bit

23

22

21

20

19

18

17

16

TMR[23:16]

TMR[15:8]

TMR[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

15

14

13

12

11

10

9

8

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 23:0 – TMR[23:0]ꢀSMT timer value

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

SMTxTMRU: Accesses the upper byte TMR[23:16]

SMTxTMRH: Accesses the high byte TMR[15:8]

SMTxTMRL: Accesses the low byte TMR[7:0]

DS40002002B-page 328

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.2 SMTxCPR

Name:ꢀ

Offset:ꢀ

SMTxCPR

0x048F

SMT Captured Period Register

Bit

23

22

21

20

19

18

17

16

CPR[23:16]

CPR[15:8]

CPR[7:0]

Access

Reset

R

x

R

x

R

x

R

x

R

x

R

x

R

x

R

x

Bit

15

14

13

12

11

10

9

8

Access

Reset

R

x

R

x

R

x

R

x

R

x

R

x

R

x

R

x

Bit

7

6

5

4

3

2

1

0

Access

Reset

R

x

R

x

R

x

R

x

R

x

R

x

R

x

R

x

Bits 23:0 – CPR[23:0]ꢀSMTxTMR value at time of period capture event

Reset States: POR/BOR = xxxxxxxxxxxxxxxxxxxxxxxx

All Other Resets = uuuuuuuuuuuuuuuuuuuuuuuu

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

SMTxCPRU: Accesses the upper byte CPR[23:16]

SMTxCPRH: Accesses the high byte CPR[15:8]

SMTxCPRL: Accesses the low byte CPR[7:0]

DS40002002B-page 329

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.3 SMTxCPW

Name:ꢀ

Offset:ꢀ

SMTxCPW

0x0492

SMT Captured Pulse Width Register

Bit

23

22

21

20

19

18

17

16

CPW[23:16]

CPW[15:8]

CPW[7:0]

Access

Reset

R

x

R

x

R

x

R

x

R

x

R

x

R

x

R

x

Bit

15

14

13

12

11

10

9

8

Access

Reset

R

x

R

x

R

x

R

x

R

x

R

x

R

x

R

x

Bit

7

6

5

4

3

2

1

0

Access

Reset

R

x

R

x

R

x

R

x

R

x

R

x

R

x

R

x

Bits 23:0 – CPW[23:0]ꢀSMTxTMR value at time of capture event

Reset States: POR/BOR = xxxxxxxxxxxxxxxxxxxxxxxx

All Other Resets = uuuuuuuuuuuuuuuuuuuuuuuu

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

SMTxCPWU: Accesses the upper byte CPW[23:16]

SMTxCPWH: Accesses the high byte CPW[15:8]

SMTxCPWL: Accesses the low byte CPW[7:0]

DS40002002B-page 330

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.4 SMTxPR

Name:ꢀ

Offset:ꢀ

SMTxPR

0x0495

SMT Period Register

23

Bit

22

21

20

19

18

17

16

PR[23:16]

PR[15:8]

PR[7:0]

Access

Reset

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Bit

15

14

13

12

11

10

9

8

Access

Reset

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Bit

7

6

5

4

3

2

1

0

Access

Reset

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Bits 23:0 – PR[23:0]ꢀThe SMTxTMR value at which the SMTxTMR resets to zero

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

SMTxPRU: Accesses the upper byte PR[23:16]

SMTxPRH: Accesses the high byte PR[15:8]

SMTxPRL: Accesses the low byte PR[7:0]

DS40002002B-page 331

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.5 SMTxCON0

Name:ꢀ

Offset:ꢀ

SMTxCON0

0x0498

SMT Control Register 0

Bit

7

EN

R/W

0

6

5

4

WPOL

R/W

0

3

SPOL

R/W

0

2

CPOL

R/W

0

1

0

STP

R/W

0

PS[1:0]

Access

Reset

R/W

0

R/W

0

Bit 7 – ENꢀSMT Enable bit

Value

Description

1

SMT is enabled

0

SMT is disabled; internal states are reset, clock requests are disabled

Bit 5 – STPꢀSMT Counter Halt Enable bit

Value

Condition

Description

1

0

When SMTxTMR = SMTxPR Counter remains SMTxPR; period match interrupt occurs when clocked

When SMTxTMR = SMTxPR Counter resets to 0x000000; period match interrupt occurs when

clocked

Bit 4 – WPOLꢀSMTxWIN Input Polarity Control bit

Value

Description

1

0

Window signal is active-low/falling edge enabled

Window signal is active-high/rising edge enabled

Bit 3 – SPOLꢀSMTxSIG Input Polarity Control bit

Value

Description

1

0

SMT Signal is active-low/falling edge enabled

SMT Signal is active-high/rising edge enabled

Bit 2 – CPOLꢀSMT Clock Input Polarity Control bit

Value

Description

1

0

SMTxTMR increments on the falling edge of the selected clock signal

SMTxTMR increments on the rising edge of the selected clock signal

Bits 1:0 – PS[1:0]ꢀSMT Prescale Select bits

Value

11

10

01

00

Description

Prescaler = 1:8

Prescaler = 1:4

Prescaler = 1:2

Prescaler = 1:1

DS40002002B-page 332

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.6 SMTxCON1

Name:ꢀ

Offset:ꢀ

SMTxCON1

0x0499

SMT Control Register 1

Bit

7

GO

R/W

0

6

REPEAT

R/W

5

4

3

2

1

0

MODE[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7 – GOꢀ SMT GO Data Acquisition bit

Value

Description

1

0

Incrementing, acquiring data is enabled

Incrementing, acquiring data is disabled

Bit 6 – REPEATꢀSMT Repeat Acquisition Enable bit

Value

Description

1

0

Repeat Data Acquisition mode is enabled

Single Acquisition mode is enabled

Bits 3:0 – MODE[3:0]ꢀSMT Operation Mode Select bits

Value

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Description

Reserved

Windowed counter

Gated counter

Counter

Capture

Time of flight

Gated windowed measurement

Windowed measurement

High and low time measurement

Period and Duty-Cycle Acquisition

Gated Timer

Timer

DS40002002B-page 333

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.7 SMTxSTAT

Name:ꢀ

Offset:ꢀ

SMTxSTAT

0x049A

SMT Status Register

Bit

7

6

5

4

3

2

TS

RO

0

1

WS

RO

0

AS

RO

0

CPRUP

R/W/HC

0

CPWUP

R/W/HC

0

RST

R/W

0

Access

Reset

Bit 7 – CPRUPꢀ SMT Manual Period Buffer Update bit

Value

Description

1

0

Request update to SMTxCPR registers

SMTxCPR registers update is complete

Bit 6 – CPWUPꢀSMT Manual Pulse Width Buffer Update bit

Value

Description

1

0

Request update to SMTxCPW registers

SMTxCPW registers update is complete

Bit 4 – RSTꢀSMT Manual Timer Reset bit

Value

Description

1

0

Request Reset to SMTxTMR registers

SMTxTMR registers update is complete

Bit 2 – TSꢀSMT GO Value Status bit

Value

Description

1

0

SMTxTMR is incrementing

SMTxTMR is not incrementing

Bit 1 – WSꢀSMT Window Status bit

Value

Description

1

0

SMT window is open

SMT window is closed

Bit 0 – ASꢀSMT Signal Value Status bit

Value

Description

1

0

SMT acquisition is in progress

SMT acquisition is not in progress

DS40002002B-page 334

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.8 SMTxCLK

Name:ꢀ

Offset:ꢀ

SMTxCLK

0x049B

SMT Clock Selection Register

Bit

7

6

5

4

3

2

1

CSEL[2:0]

R/W

0

Access

Reset

R/W

0

R/W

0

Bits 2:0 – CSEL[2:0]ꢀSMT Clock Selection bits

Table 21-1.ꢀSMT Clock Source Selection

CSEL[2:0]

111

Clock Source

CLKREF output

SOSC

110

101

MFINTOSC (31.25kHz)

MFINTOSC (500kHz)

LFINTOSC

100

011

010

HFINTOSC

001

F_OSC

000

F_OSC/4

DS40002002B-page 335

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.9 SMTxSIG

Name:ꢀ

Offset:ꢀ

SMTxSIG

0x049C

SMT Signal Selection bits

Bit

7

6

5

4

3

2

SSEL[4:0]

R/W

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – SSEL[4:0]ꢀSMT Signal Selection bits

Table 21-2.ꢀSMT Signal Selection

SSEL[4:0]

11111-10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

SMT1 Signal Source

Reserved

CLC4OUT

CLC3OUT

CLC2OUT

CLC1OUT

ZCDOUT

C2OUT

C1OUT

NCO1OUT

PWM7OUT

PWM6OUT

CCP4OUT

CCP3OUT

CCP2OUT

CCP1OUT

TMR6 postscaled output

TMR5 overflow

TMR4 postscaled output

TMR3 overflow

TMR2 postscaled output

TMR1 overflow

TMR0 overflow

Pin Selected by SMT1SIGPPS

DS40002002B-page 336

Datasheet

PIC16(L)F18425/45

SMT - Signal Measurement Timer

21.3.10 SMTxWIN

Name:ꢀ

Offset:ꢀ

SMTxWIN

0x049D

SMT Window Input Select Register

Bit

7

6

5

4

3

2

WSEL[4:0]

R/W

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – WSEL[4:0]ꢀSMT Window Selection bits

Table 21-3.ꢀSMT Window Selection

WSEL[4:0]

11111-11000

10111

10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

SMT1 Window Source

Reserved

NCO1OUT

Reserved

CLKREFOUT

CLC4OUT

CLC3OUT

CLC2OUT

CLC1OUT

ZCDOUT

C2OUT

C1OUT

PWM7OUT

PWM6OUT

CCP4OUT

CCP3OUT

CCP2OUT

CCP1OUT

TMR6_postscaled_out

TMR4_postscaled_out

TMR2_postscaled_out

TMR0_overflow

SOSC

MFINTOSC (31.25kHz)

LFINTOSC (31.25kHz)

Pin Selected by SMT1WINPPS

DS40002002B-page 337

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

22.

Capture/Compare/PWM Module

The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to

generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of

an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has

expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.

This family of devices contains four standard Capture/Compare/PWM modules (CCP1, CCP2, CCP3, and CCP4). It

should be noted that the Capture/Compare mode operation is described with respect to TMR1 and the PWM mode

operation is described with respect to T2TMR in the following sections.

The Capture and Compare functions are identical for all CCP modules.

Important:ꢀ

1. In devices with more than one CCP module, it is very important to pay close attention to the register

names used. A number placed after the module acronym is used to distinguish between separate

modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two

completely different CCP modules.

2. Throughout this section, generic references to a CCP module in any of its operating modes may be

interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins,

and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a

particular module, when required.

22.1

CCP Module Configuration

Each Capture/Compare/PWM module is associated with a control register (CCPxCON), a capture input selection

register (CCPxCAP) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers:

CCPRxL (low byte) and CCPRxH (high byte).

22.1.1 CCP Modules and Timer Resources

The CCP modules utilize Timers 1 through 6 that vary with the selected mode. Various timers are available to the

CCP modules in Capture, Compare or PWM modes, as shown in the table below.

Table 22-1.ꢀCCP Mode - Timer Resources

CCP Mode

Capture

Compare

PWM

Timer Resource

Timer1, Timer3 or Timer5

Timer2, Timer4 or Timer6

The assignment of a particular timer to a module is determined by the timer to CCP enable bits in the CCPTMRS0

and/or CCPTMRS1 registers. All of the modules may be active at once and may share the same timer resource if

they are configured to operate in the same mode (Capture/Compare or PWM) at the same time.

22.1.2 Open-Drain Output Option

When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally

configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level

through an external pull-up resistor and allows the output to communicate with external circuits without the need for

additional level shifters.

DS40002002B-page 338

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

22.2

Capture Mode

Capture mode makes use of the 16-bit odd numbered timer resources (Timer1, Timer3, etc.). When an event occurs

on the capture source, the 16-bit CCPRx register captures and stores the 16-bit value of the TMRx register. An event

is defined as one of the following and is configured by the MODE bits:

•

Every falling edge of CCPx input

Every rising edge of CCPx input

Every 4^thrising edge of CCPx input

Every 16^thrising edge of CCPx input

Every edge of CCPx input (rising or falling)

When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIR6 register is set. The interrupt flag must be

cleared in software. If another capture occurs before the value in the CCPRx register is read, the old captured value

is overwritten by the new captured value.

Important:ꢀ If an event occurs during a 2-byte read, the high and low-byte data will be from different

events. It is recommended while reading the CCPRxH:CCPRxL register pair to either disable the module

or read the register pair twice for data integrity.

The following figure shows a simplified diagram of the capture operation.

Figure 22-1.ꢀCapture Mode Operation Block Diagram

Rev. 10-000158E

6/26/2017

RxyPPS

CCPx

PPS

CTS

TRIS Control

CCPRxH CCPRxL

16

Capture Trigger Sources

See CCPxCAP register

set CCPxIF

Prescaler

1,4,16

and

Edge Detect

16

CCPx

PPS

MODE [3:0]

TMR1H

TMR1L

CCPxPPS

22.2.1 Capture Sources

In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit.

Important:ꢀ If the CCPx pin is configured as an output, a write to the port can cause a capture condition.

The capture source is selected by configuring the CTS bits as shown in the following table:

Table 22-2.ꢀCapture Trigger Sources

CTS

Source

111

CLC4_out

DS40002002B-page 339

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

...........continued

CTS

Source

110

101

100

011

010

001

000

CLC3_out

CLC2_out

CLC1_out

IOC_interrupt

C2_out

C1_out

Pin selected by CCPxPPS

22.2.2 Timer1 Mode Resource

Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture operation may not work.

See section “Timer1 Module with Gate Control” for more information on configuring Timer1.

Related Links

19. TMR1 - Timer1 Module with Gate Control

22.2.3 Software Interrupt Mode

When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE

Interrupt Priority bit of the PIE6 register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF

Interrupt Flag bit of the PIR6 register following any change in Operating mode.

Important:ꢀ Clocking Timer1 from the system clock (F_OSC) should not be used in Capture mode. In order

for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the

instruction clock (F_OSC/4) or from an external clock source.

22.2.4 CCP Prescaler

There are four prescaler settings specified by the MODE bits. Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the

prescaler. The example below demonstrates the code to perform this function.

Example 22-1.ꢀChanging Between Capture Prescalers

BANKSEL CCP1CON

;(only needed when CCP1CON is not in ACCESS space)

;Turn CCP module off

CLRF

CCP1CON

MOVLW

MOVWF

NEW_CAPT_PS

CCP1CON

;CCP ON and Prescaler select → W

;Load CCP1CON with this value

22.2.5 Capture During Sleep

Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1

module in Capture mode. It can be driven by the instruction clock (F_OSC/4), or by an external clock source.

When Timer1 is clocked by F_OSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep,

Timer1 will continue from its previous state.

Capture mode will operate during Sleep when Timer1 is clocked by an external clock source.

DS40002002B-page 340

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

22.3

Compare Mode

The Compare mode function described in this section is available and identical for all CCP modules.

Compare mode makes use of the 16-bit odd numbered Timer resources (Timer1, Timer3, etc.). The 16-bit value of

the CCPRx register is constantly compared against the 16-bit value of the TMRx register. When a match occurs, one

of the following events can occur:

•

Toggle the CCPx output and clear TMRx

Toggle the CCPx output without clearing TMRx

Set the CCPx output

Clear the CCPx output

Pulse output

Pulse output and clear TMRx

The action on the pin is based on the value of the MODE control bits. At the same time, the interrupt flag CCPxIF bit

is set, and an ADC conversion can be triggered, if selected.

All Compare modes can generate an interrupt and trigger an ADC conversion. When MODE = '0001'or '1011',

the CCP resets the TMRx register.

The following figure shows a simplified diagram of the compare operation.

Figure 22-2.ꢀCompare Mode Operation Block Diagram

Rev. 30-000133A

6/27/2017

MODE

Auto-conversion Trigger

4

CCPRxH CCPRxL

CCPx

PPS

Q

S

R

Output

Logic

Comparator

RxyPPS

TMR1H TMR1L

TRIS

Set CCPxIF Interrupt Flag

22.3.1 CCPx Pin Configuration

The software must configure the CCPx pin as an output by clearing the associated TRIS bit and defining the

appropriate output pin through the RxyPPS registers. See section “Peripheral Pin Select (PPS) Module” for more

details.

The CCP output can also be used as an input for other peripherals.

Important:ꢀ Clearing the CCPxCON register will force the CCPx compare output latch to the default low

level. This is not the PORT I/O data latch.

Related Links

16. PPS - Peripheral Pin Select Module

22.3.2 Timer1 Mode Resource

In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare

operation may not work in Asynchronous Counter mode.

See Section "Timer1 Module with Gate Control" for more information on configuring Timer1.

DS40002002B-page 341

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

Important:ꢀ Clocking Timer1 from the system clock (F_OSC) should not be used in Compare mode. In order

for Compare mode to generate the trigger event on the CCPx pin, Timer1 must be clocked from the

instruction clock (F_OSC/4) or from an external clock source.

22.3.3 Auto-Conversion Trigger

All CCPx modes set the CCP Interrupt Flag (CCPxIF). When this flag is set and a match occurs, an auto-conversion

trigger can take place if the CCP module is selected as the conversion trigger source.

Refer to Section “Auto-Conversion Trigger” for more information.

Important:ꢀ Removing the match condition by changing the contents of the CCPRxH and CCPRxL

register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that

generates the Timer1 Reset, will preclude the Reset from occurring.

Related Links

32.2.6 Auto-Conversion Trigger

22.3.4 Compare During Sleep

Since F_OSCis shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the

timer is running. The device will wake on interrupt (if enabled).

22.4

PWM Overview

Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully ON and

fully OFF states. The PWM signal resembles a square wave where the high portion of the signal is considered the

ON state and the low portion of the signal is considered the OFF state. The high portion, also known as the pulse

width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width,

also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies

less power. The PWM period is defined as the duration of one complete cycle or the total amount of ON and OFF

time combined.

PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher

resolution allows for more precise control of the pulse-width time and in turn the power that is applied to the load.

The term duty cycle describes the proportion of the ON time to the OFF time and is expressed in percentages, where

0% is fully OFF and 100% is fully ON. A lower duty cycle corresponds to less power applied and a higher duty cycle

corresponds to more power applied.

The figure below shows a typical waveform of the PWM signal.

Figure 22-3.ꢀCCP PWM Output Signal

Rev. 30-000134A

5/9/2017

Period

Pulse Width

TMR2 = PR2

TMR2 = CCPRxH:CCPRxL

TMR2 = 0

22.4.1 Standard PWM Operation

The standard PWM function described in this section is available and identical for all CCP modules.

The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of

resolution. The period, duty cycle, and resolution are controlled by the following registers:

DS40002002B-page 342

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

•

Even numbered TxPR registers (T2PR, T4PR, etc)

Even numbered TxCON registers (T2CON, T4CON, etc)

16-bit CCPRx registers

CCPxCON registers

It is required to have F_OSC/4 as the clock input to TxTMR for correct PWM operation. The following figure shows a

simplified block diagram of PWM operation.

Figure 22-4.ꢀSimplified PWM Block Diagram

Rev. 10-000 157C

9/5/201 4

Duty cycle registers

CCPRxH

CCPRxL

CCPx_out

To Peripherals

set CCPIF

10-bit Latch⁽²⁾

(Not accessible by user)

R

S

Q

Comparator

PPS

CCPx

RxyPPS

TRIS Control

TMR2 Module

TMR2

R

(1)

ERS logic

CCPx_pset

Comparator

PR2

Note:ꢀ

1. 8-bit timer is concatenated with two bits generated by F_OSCor two bits of the internal prescaler to create 10-bit

time base.

2. The alignment of the 10 bits from the CCPRx register is determined by the CCPxFMT bit.

Important:ꢀ The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin.

22.4.2 Setup for PWM Operation

The following steps should be taken when configuring the CCP module for standard PWM operation:

1. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin output

driver by setting the associated TRIS bit.

2. Load the T2PR register with the PWM period value.

3. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values.

4. Load the CCPRx register with the PWM duty cycle value and configure the FMT bit to set the proper register

alignment.

5. Configure and start Timer2:

– Clear the TMR2IF interrupt flag bit of the PIR4 register. See Note below.

– Select the timer clock source to be as F_OSC/4 using the TxCLKCON register. This is required for correct

operation of the PWM module.

DS40002002B-page 343

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

– Configure the T2CKPS bits of the T2CON register with the timer prescale value.

– Enable the timer by setting the T2ON bit.

6. Enable PWM output pin:

– Wait until the timer overflows and the TMR2IF bit of the PIR4 register is set. See Note below.

– Enable the CCPx pin output driver by clearing the associated TRIS bit.

Important:ꢀ In order to send a complete duty cycle and period on the first PWM output, the

above steps must be included in the setup sequence. If it is not critical to start with a complete

PWM signal on the first output, then step 6 may be ignored.

Related Links

20.11.3 TxCON

22.4.3 Timer2 Timer Resource

The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period.

22.4.4 PWM Period

The PWM period is specified by the T2PR register of Timer2. The PWM period can be calculated using the formula in

the equation below.

Equation 22-1.ꢀPWM Period

ꢀꢁꢂꢀꢃꢄꢅꢆꢇ = ꢈ2ꢀꢉ + 1 • 4 • ꢈ

• ꢈꢂꢉ2Prꢃꢍꢎꢏꢐꢃꢑꢏꢐꢒꢃ

ꢊꢋꢌ

where T_OSC= 1/F_OSC

When T2TMR is equal to T2PR, the following three events occur on the next increment cycle:

•

T2TMR is cleared

The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.)

The PWM duty cycle is transferred from the CCPRx register into a 10-bit buffer.

Important:ꢀ The Timer postscaler (see “Timer2 Interrupt”) is not used in the determination of the PWM

frequency.

Related Links

20.4 Timer2 Interrupt

22.4.5 PWM Duty Cycle

The PWM duty cycle is specified by writing a 10-bit value to the CCPRx register. The alignment of the 10-bit value is

determined by the FMT bit (see Figure 22-5). The CCPRx register can be written to at any time. However, the duty

cycle value is not latched into the 10-bit buffer until after a match between T2PR and T2TMR.

The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio.

DS40002002B-page 344

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

Figure 22-5.ꢀPWM 10-Bit Alignment

Rev. 10-000 160A

12/9/201 3

CCPRxH

7 6 5 4 3 2 1 0

CCPRxL

7 6 5 4 3 2 1 0

FMT = 0

CCPRxH

7 6 5 4 3 2 1 0

CCPRxL

7 6 5 4 3 2 1 0

FMT = 1

10-bit Duty Cycle

9 8 7 6 5 4 3 2 1 0

Equation 22-2.ꢀPulse Width

ꢀꢒꢐꢍꢃ ꢁꢅꢇꢓℎ = ꢌꢌꢀꢉꢔꢕ:ꢌꢌꢀꢉꢔꢖ ꢄꢃꢗꢅꢍꢓꢃꢄ ꢘꢏꢐꢒꢃ • ꢈ

• ꢈꢂꢉ2 Prꢃꢍꢎꢏꢐꢃ ꢑꢏꢐꢒꢃ

ꢊꢋꢌ

Equation 22-3.ꢀDuty Cycle

ꢌꢌꢀꢉꢔꢕ:ꢌꢌꢀꢉꢔꢖ ꢄꢃꢗꢅꢍꢓꢃꢄ ꢘꢏꢐꢒꢃ

ꢙꢒꢓꢚꢌꢚꢎꢐꢃꢉꢏꢓꢅꢆ =

4 ꢈ2ꢀꢉ + 1

The CCPRx register is used to double buffer the PWM duty cycle. This double buffering is essential for glitchless

PWM operation.

The 8-bit timer T2TMR register is concatenated with either the 2-bit internal system clock (F_OSC), or two bits of the

prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.

When the 10-bit time base matches the CCPRx register, then the CCPx pin is cleared (see Figure 22-4).

22.4.6 PWM Resolution

The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will

result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles.

The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR register value

as shown below.

Equation 22-4.ꢀPWM Resolution

log 4 ꢈ2ꢀꢉ + 1

Reꢍꢆꢐꢒꢓꢅꢆꢛ =

ꢜꢅꢓꢍ

log 2

Important:ꢀ If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain

unchanged.

Table 22-3.ꢀExample PWM Frequencies and Resolutions (F_OSC= 20 MHz)

PWM Frequency

Timer Prescale

1.22 kHz

16

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

4

1

0x3F

8

1

0x1F

7

1

T2PR Value

0xFF

10

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

Table 22-4.ꢀExample PWM Frequencies and Resolutions (F_OSC= 8 MHz)

PWM Frequency

Timer Prescale

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz

200.0 kHz

16

4

1

DS40002002B-page 345

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

...........continued

PWM Frequency

1.22 kHz

0x65

8

4.90 kHz

0x65

8

19.61 kHz

76.92 kHz

153.85 kHz

200.0 kHz

T2PR Value

0x65

8

0x19

6

0x0C

5

0x09

5

Maximum Resolution (bits)

22.4.7 Operation in Sleep Mode

In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the CCPx pin is

driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from the previous

state.

22.4.8 Changes in System Clock Frequency

The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will

result in changes to the PWM frequency. See the “Oscillator Module (with Fail-Safe Clock Monitor)” section for

additional details.

Related Links

8. OSC - Oscillator Module

22.4.9 Effects of Reset

Any Reset will force all ports to Input mode and the CCP registers to their Reset states.

DS40002002B-page 346

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

22.5

Register Summary - CCP Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x030B

7:0

15:8

7:0

CCPR[7:0]

CCPR[15:8]

FMT

0x030C

CCPR1

0x030E

0x030F

CCP1CON

CCP1CAP

EN

OUT

MODE[3:0]

CTS[2:0]

7:0

CCPR[7:0]

0x0310

CCPR2

15:8

7:0

CCPR[15:8]

0x0312

0x0313

CCP2CON

CCP2CAP

FMT

MODE[3:0]

CTS[2:0]

7:0

CCPR[7:0]

0x0314

CCPR3

15:8

7:0

CCPR[15:8]

0x0316

0x0317

CCP3CON

CCP3CAP

FMT

MODE[3:0]

CTS[2:0]

7:0

CCPR[7:0]

0x0318

CCPR4

15:8

7:0

CCPR[15:8]

0x031A

0x031B

CCP4CON

CCP4CAP

FMT

MODE[3:0]

CTS[2:0]

7:0

22.6

Register Definitions: CCP Control

Long bit name prefixes for the CCP peripherals are shown in the following table. Refer to the “Long Bit Names”

section for more information.

Table 22-5.ꢀCCP Long Bit Name Prefixes

Peripheral

CCP1

Bit Name Prefix

CCP1

CCP2

CCP3

CCP4

Related Links

1.4.2.2 Long Bit Names

DS40002002B-page 347

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

22.6.1 CCPxCON

Name:ꢀ

Offset:ꢀ

CCPxCON

0x30E,0x312,0x316,0x31A

CCP Control Register

Bit

7

6

5

OUT

RO

x

4

3

2

1

0

EN

R/W

0

FMT

R/W

0

MODE[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7 – ENꢀCCP Module Enable bit

Value

Description

1

0

CCP is enabled

CCP is disabled

Bit 5 – OUTꢀCCP Output Data bit (read-only)

Bit 4 – FMTꢀCCPW (pulse-width) Value Alignment bit

Value

Condition

Description

Not used

Left-aligned format

Right-aligned format

x

1

0

Capture mode

Compare mode

PWM mode

Bits 3:0 – MODE[3:0]ꢀCCP Mode Select bits

Table 22-6.ꢀCCPx Mode Select Bits

MODE

11xx

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Operating Mode

PWM

Operation

Set CCPxIF

PWM Operation

Yes

—

Compare

Pulse output; clear TMR1⁽²⁾

Pulse output

Clear output⁽¹⁾

Set output⁽¹⁾

Capture

Every 16^thrising edge of CCPx input

Every 4^thrising edge of CCPx input

Every rising edge of CCPx input

Every falling edge of CCPx input

Every edge of CCPx input

Toggle output

Compare

Disabled

Toggle output; clear TMR1⁽²⁾

Note:ꢀ

1. The set and clear operations of the Compare mode are Reset by setting MODE = '0000'.

2. When MODE = '0001'or '1011', then the timer associated with the CCP module is cleared. TMR1 is the

default selection for the CCP module, so it is used for indication purpose only.

DS40002002B-page 348

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

22.6.2 CCPxCAP

Name:ꢀ

Offset:ꢀ

CCPxCAP

0x30F,0x313,0x317,0x31B

Capture Trigger Input Selection Register

Bit

7

6

5

4

3

2

1

CTS[2:0]

R/W

0

Access

Reset

R/W

0

R/W

0

Bits 2:0 – CTS[2:0]ꢀCapture Trigger Input Selection bits

Table 22-7.ꢀCapture Trigger Sources

CTS

Source

111

110

101

100

011

010

001

000

CLC4_out

CLC3_out

CLC2_out

CLC1_out

IOC_interrupt

C2_out

C1_out

Pin selected by CCPxPPS

DS40002002B-page 349

Datasheet

PIC16(L)F18425/45

Capture/Compare/PWM Module

22.6.3 CCPRx

Name:ꢀ

Offset:ꢀ

CCPRx

0x30C,0x310,0x314,0x318

Capture/Compare/Pulse Width Register

Bit

15

14

13

12

11

10

9

8

CCPR[15:8]

CCPR[7:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bit

7

6

5

4

3

2

1

0

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 15:0 – CCPR[15:0]ꢀCapture/Compare/Pulse Width

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

When MODE = Capture or Compare

– CCPRxH: Accesses the high byte CCPR[15:8]

– CCPRxL: Accesses the low byte CCPR[7:0]

When MODE = PWM and FMT=0

•

– CCPRxH[7:2]: Not used

– CCPRxH[1:0]: Accesses the two Most Significant bits CCPR[9:8]

– CCPRxL: Accesses the eight Least Significant bits CCPR[7:0]

When MODE = PWM and FMT=1

•

– CCPRxH: Accesses the eight Most Significant bits CCPR[9:2]

– CCPRxL[7:6]: Accesses the two Least Significant bits CCPR[1:0]

– CCPRxL[5:0]: Not used

DS40002002B-page 350

Datasheet

PIC16(L)F18425/45

CCP/PWM Timer Resource Selection

23.

CCP/PWM Timer Resource Selection

Each CCP/PWM module has an independent timer selection which can be accessed using the CxTSEL or PxTSEL

bits in the CCPTMRS0 and/or CCPTMRS1 registers. The default timer selection is Timer1 when using Capture/

Compare mode and Timer2 when using PWM mode in the CCPx module. The default timer selection for the PWM

module is always Timer2.

DS40002002B-page 351

Datasheet

PIC16(L)F18425/45

CCP/PWM Timer Resource Selection

23.1

Register Summary - Timer Selection Registers for CCP/PWM

Offset

Name

Bit Pos.

0x00

...

Reserved

0x021D

0x021E

0x021F

CCPTMRS0

CCPTMRS1

7:0

C4TSEL[1:0]

C3TSEL[1:0]

P7TSEL[1:0]

C2TSEL[1:0]

P6TSEL[1:0]

C1TSEL[1:0]

23.2

Register Definitions: CCP/PWM Timer Selection

DS40002002B-page 352

Datasheet

PIC16(L)F18425/45

CCP/PWM Timer Resource Selection

23.2.1 CCPTMRS0

Name:ꢀ

Offset:ꢀ

CCPTMRS0

0x21E

CCP Timers Selection Register0

Bit

7

6

5

4

3

2

1

0

C4TSEL[1:0]

C3TSEL[1:0]

C2TSEL[1:0]

C1TSEL[1:0]

Access

Reset

R/W

0

R/W

1

R/W

0

R/W

1

R/W

0

R/W

1

R/W

0

R/W

1

Bits 0:1, 2:3, 4:5, 6:7 – CxTSELꢀCCPx Timer Selection bits

Value

11

10

01

00

Description

CCPx is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode

CCPx is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode

CCPx is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode

Reserved

DS40002002B-page 353

Datasheet

PIC16(L)F18425/45

CCP/PWM Timer Resource Selection

23.2.2 CCPTMRS1

Name:ꢀ

Offset:ꢀ

CCPTMRS1

0x21F

CCP Timers Control Register

Bit

7

6

5

4

3

2

1

0

P7TSEL[1:0]

P6TSEL[1:0]

Access

Reset

R/W

0

R/W

1

R/W

0

R/W

1

Bits 2:3, 4:5 – PxTSELꢀPWMx Timer Selection bits

Value

11

10

01

00

Description

PWMx based on TMR6

PWMx based on TMR4

PWMx based on TMR2

Reserved

DS40002002B-page 354

Datasheet

PIC16(L)F18425/45

PWM - Pulse-Width Modulation

24.

PWM - Pulse-Width Modulation

The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution

that are configured by the following registers:

•

TxPR

TxCON

PWMxDC

PWMxCON

Important:ꢀ The corresponding TRIS bit must be cleared to enable the PWM output on the PWMx pin.

Each PWM module can select the timer source that controls the module. Note that the PWM mode operation is

described with respect to TMR2 in the following sections.

Figure 24-1 shows a simplified block diagram of PWM operation.

Figure 24-2 shows a typical waveform of the PWM signal.

Figure 24-1.ꢀSimplified PWM Block Diagram

Rev. 10-000022B

9/24/2014

PWMxDCL[7:6]

Duty cycle registers

PWMxDCH

PWMx_out

To Peripherals

10-bit Latch

(Not visible to user)

R

S

Q

Comparator

0

1

PPS

PWMx

TMR2 Module

RxyPPS

TRIS Control

R

PWMxPOL

(1)

TMR2

Comparator

PR2

T2_match

Note:ꢀ

1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit

time base.

DS40002002B-page 355

Datasheet

PIC16(L)F18425/45

PWM - Pulse-Width Modulation

Figure 24-2.ꢀPWM Output

Rev. 30-000129A

5/17/2017

Period

Pulse Width

TMR2 = PR2

TMR2 =

PWMxDCH[7:0]:PWMx DCL[7:6]

TMR2 = 0

For a step-by-step procedure on how to set up this module for PWM operation, refer to 24.9 Setup for PWM

Operation using PWMx Output Pins.

24.1

Fundamental Operation

The PWM module produces a 10-bit resolution output. The PWM timer can be selected using the PxTSEL bits in the

CCPTMRS register. The default selection for PWMx is TMR2. Note that the PWM module operation in the following

sections is described with respect to TMR2. Timer2 and T2PR set the period of the PWM. The PWMxDCL and

PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is

independently controlled.

Important:ꢀ The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler

could be used to have a servo update rate at a different frequency than the PWM output.

All PWM outputs associated with Timer2 are set when T2TMR is cleared. Each PWMx is cleared when TxTMR is

equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL[7:6] (2 LSb) registers. When

the value is greater than or equal to T2PR, the PWM output is never cleared (100% duty cycle).

Important:ꢀ The PWMxDCH and PWMxDCL registers are double-buffered. The buffers are updated when

T2TMR matches T2PR. Care should be taken to update both registers before the timer match occurs.

24.2

24.3

PWM Output Polarity

The output polarity is inverted by setting the POL bit in the PWMxCON register.

PWM Period

The PWM period is specified by the TxPR register The PWM period can be calculated using the formula of Equation

24-1. It is required to have F_OSC/4 as the selected clock input to the timer for correct PWM operation.

Equation 24-1.ꢀPWM Period

ꢀꢁꢂꢀꢃꢄꢅꢆꢇ = ꢈ2ꢀꢉ + 1 • 4 • ꢈꢆꢍꢎ • ꢈꢂꢉ2 Prꢃꢍꢎꢏꢐꢃꢑꢏꢐꢒꢃ

Note:ꢀ T_OSC= 1/F_OSC

When T2TMR is equal to T2PR, the following three events occur on the next increment cycle:

•

T2TMR is cleared

The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.)

The PWMxDCH and PWMxDCL register values are latched into the buffers.

DS40002002B-page 356

Datasheet

PIC16(L)F18425/45

PWM - Pulse-Width Modulation

Important:ꢀ The Timer2 postscaler has no effect on the PWM operation.

24.4

PWM Duty Cycle

The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The

PWMxDCH register contains the eight MSbs and the PWMxDCL[7:6], the two LSbs. The PWMxDCH and PWMxDCL

registers can be written to at any time.

The formulas below are used to calculate the PWM pulse width and the PWM duty cycle ratio.

Equation 24-2.ꢀPulse Width

ꢀꢒꢐꢍꢃꢁꢅꢇꢓℎ = ꢀꢁꢂꢔꢙꢌꢕ:ꢀꢁꢂꢔꢙꢌꢖ 7:6 • ꢈꢆꢍꢎ • ꢈꢂꢉ2Prꢃꢍꢎꢏꢐꢃꢑꢏꢐꢒꢃ

Note:ꢀ T_OSC= 1/F_OSC

Equation 24-3.ꢀDuty Cycle Ratio

ꢀꢁꢂꢔꢙꢌꢕ:ꢀꢁꢂꢔꢙꢌꢖ 7:6

ꢙꢒꢓꢚꢌꢚꢎꢐꢃꢉꢏꢓꢅꢆ =

4 ꢈ2ꢀꢉ + 1

The 8-bit timer T2TMR register is concatenated with the two Least Significant bits of 1/F_OSC, adjusted by the Timer2

prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.

24.5

PWM Resolution

The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will

result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles.

The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR register value

as shown below.

Equation 24-4.ꢀPWM Resolution

log 4 ꢈ2ꢀꢉ + 1

Reꢍꢆꢐꢒꢓꢅꢆꢛ =

ꢜꢅꢓꢍ

log 2

Important:ꢀ If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain

unchanged.

Table 24-1.ꢀExample PWM Frequencies and Resolutions (F_OSC= 20 MHz)

PWM Frequency

Timer Prescale

0.31 kHz

64

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

4

1

0x3F

8

1

0x1F

7

1

T2PR Value

0xFF

10

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

Table 24-2.ꢀExample PWM Frequencies and Resolutions (F_OSC= 8 MHz)

PWM Frequency

Timer Prescale

0.31 kHz

64

4.90 kHz

4

19.61 kHz

76.92 kHz

153.85 kHz

200.0 kHz

1

T2PR Value

0x65

0x19

0x0C

0x09

DS40002002B-page 357

Datasheet

PIC16(L)F18425/45

PWM - Pulse-Width Modulation

...........continued

PWM Frequency

0.31 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz

200.0 kHz

Maximum Resolution (bits)

8

6

5

24.6

24.7

Operation in Sleep Mode

In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the PWMx pin is

driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from its previous

state.

Changes in System Clock Frequency

The PWM frequency is derived from the system clock frequency (F_OSC). Any changes in the system clock frequency

will result in changes to the PWM frequency.

Related Links

8. OSC - Oscillator Module

24.8

24.9

Effects of Reset

Any Reset will force all ports to Input mode and the PWM registers to their Reset states.

Setup for PWM Operation using PWMx Output Pins

The following steps should be taken when configuring the module for PWM operation using the PWMx pins:

1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s).

2. Clear the PWMxCON register.

3. Load the T2PR register with the PWM period value.

4. Load the PWMxDCH register and bits [7:6] of the PWMxDCL register with the PWM duty cycle value.

5. Configure and start Timer2:

– Clear the TMR2IF interrupt flag bit of the PIR4 register.⁽¹⁾

– Select the timer clock source to be as F_OSC/4 using the TxCLKCON register. This is required for correct

operation of the PWM module.

– Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value.

– Enable Timer2 by setting the T2ON bit of the T2CON register.

6. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIR4 register is set.⁽²⁾

7. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the desired pin PPS

control bits.

8. Configure the PWM module by loading the PWMxCON register with the appropriate values.

Note:ꢀ

1. In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed

in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4.

2. For operation with other peripherals only, disable PWMx pin outputs.

24.9.1 PWMx Pin Configuration

All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing

the associated TRIS bits.

DS40002002B-page 358

Datasheet

PIC16(L)F18425/45

PWM - Pulse-Width Modulation

24.10 Setup for PWM Operation to Other Device Peripherals

The following steps should be taken when configuring the module for PWM operation to be used by other device

peripherals:

1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s).

2. Clear the PWMxCON register.

3. Load the T2PR register with the PWM period value.

4. Load the PWMxDCH register and bits [7:6] of the PWMxDCL register with the PWM duty cycle value.

5. Configure and start Timer2:

– Clear the TMR2IF interrupt flag bit of the PIR4 register.⁽¹⁾

– Select the timer clock source to be as F_OSC/4 using the TxCLKCON register. This is required for correct

operation of the PWM module.

– Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value.

– Enable Timer2 by setting the T2ON bit of the T2CON register.

6. Wait until Timer2 overflows, TMR2IF bit of the PIR4 register is set.⁽¹⁾

7. Configure the PWM module by loading the PWMxCON register with the appropriate values.

Note:ꢀ

1. In order to send a complete duty cycle and period on the first PWM output, the above steps must be included

in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6

may be ignored.

DS40002002B-page 359

Datasheet

PIC16(L)F18425/45

PWM - Pulse-Width Modulation

24.11 Register Summary - Registers Associated with PWM

Offset

Name

Bit Pos.

0x00

...

Reserved

0x038B

7:0

15:8

7:0

DCL[1:0]

0x038C

PWM6DC

DCH[7:0]

0x038E

0x038F

PWM6CON

Reserved

EN

OUT

POL

7:0

15:8

7:0

0x0390

0x0392

PWM7DC

DCH[7:0]

PWM7CON

24.12 Register Definitions: PWM Control

DS40002002B-page 360

Datasheet

PIC16(L)F18425/45

PWM - Pulse-Width Modulation

24.12.1 PWMxDC

Name:ꢀ

Offset:ꢀ

PWMxDC

0x38C,0x390

PWM Duty Cycle Register

Bit

15

14

13

12

11

10

9

8

DCH[7:0]

Access

Reset

x

Bit

7

6

5

4

3

2

1

0

DCL[1:0]

Access

Reset

x

Bits 15:8 – DCH[7:0]ꢀPWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle.

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Bits 7:6 – DCL[1:0]ꢀPWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle.

Reset States: POR/BOR = xx

All Other Resets = uu

DS40002002B-page 361

Datasheet

PIC16(L)F18425/45

PWM - Pulse-Width Modulation

24.12.2 PWMxCON

Name:ꢀ

Offset:ꢀ

PWMxCON

0x38E,0x392

PWM Control Register

Bit

7

EN

R/W

0

6

5

OUT

RO

0

4

3

2

1

0

POL

R/W

0

Access

Reset

Bit 7 – ENꢀPWM Module Enable bit

Value

Description

1

0

PWM module is enabled

PWM module is disabled

Bit 5 – OUTꢀPWM Module Output Level When Bit is Read

Bit 4 – POLꢀPWM Output Polarity Select bit

Value

Description

1

0

PWM output is inverted

PWM output is normal

DS40002002B-page 362

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.

CWG - Complementary Waveform Generator

The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms.

It is backwards compatible with previous CCP functions. The PIC16(L)F18425/45 family has 2 instance(s) of the

CWG module.

The CWG has the following features:

•

Six Operating Modes:

– Synchronous Steering mode

– Asynchronous Steering mode

– Full-Bridge mode, Forward

– Full-Bridge mode, Reverse

– Half-Bridge mode

– Push-Pull mode

•

Output Polarity Control

Output Steering

Independent 6-Bit Rising and Falling Event Dead-Band Timers:

– Clocked dead band

– Independent rising and falling dead-band enables

Auto-Shutdown Control With:

– Selectable shutdown sources

– Auto-restart option

•

– Auto-shutdown pin override control

25.1

Fundamental Operation

The CWG generates two output waveforms from the selected input source.

The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby,

creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in

section 25.7 Dead-Band Control.

It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all.

In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as

auto-shutdown and is covered in section 25.11 Auto-Shutdown.

25.2

Operating Modes

The CWG module can operate in six different modes, as specified by the MODE bits:

•

Half-Bridge mode

Push-Pull mode

Asynchronous Steering mode

Synchronous Steering mode

Full-Bridge mode, Forward

Full-Bridge mode, Reverse

All modes accept a single pulse data input, and provide up to four outputs as described in the following sections.

All modes include auto-shutdown control as described in 25.11 Auto-Shutdown.

DS40002002B-page 363

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

Important:ꢀ Except as noted for Full-Bridge mode (25.2.3 Full-Bridge Modes), mode changes should only

be performed while EN = 0.

25.2.1 Half-Bridge Mode

In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in

Figure 25-1. A non-overlap (dead-band) time is inserted between the two outputs to prevent shoot-through current in

various power supply applications. Dead-band control is described in 25.7 Dead-Band Control. The output steering

feature cannot be used in this mode. A basic block diagram of this mode is shown in Figure 25-2.

The unused outputs CWGxC and CWGxD drive similar signals, with polarity independently controlled by the POLC

and POLD bits, respectively.

Figure 25-1.ꢀCWG Half-Bridge Mode Operation

Rev. 30-000097A

4/14/2017

CWGx_clock

CWGxA

CWGxC

Rising Event Dead Band

Falling Event Dead Band

Rising Event D

Falling Event Dead Band

CWGxB

CWGxD

CWGx_data

Note:ꢀ CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out

DS40002002B-page 364

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

Figure 25-2.ꢀSimplified CWG Block Diagram (Half-Bridge Mode, MODE[2:0] = 100)

LSAC[1:0]

Rev. 10-000209D

2/2/2016

00

01

10

11

‘1’

‘0’

High-Z

Rising Dead-Band Block

clock

CWG Clock

CWG Data

1

0

CWG Data A

data out

data in

CWGxA

POLA

POLB

POLC

POLD

LSBD[1:0]

‘1’

‘0’

00

01

10

11

Falling Dead-Band Block

clock

CWG Data B

data out

High-Z

data in

1

0

CWG

Data

CWG Data Input

CWGxB

CWGxC

CWGxD

Q

D

E

LSAC[1:0]

00

01

10

11

‘1’

‘0’

EN

High-Z

1

0

Auto-shutdown source

(CWGxAS1 register)

S

R

Q

LSBD[1:0]

00

01

10

11

‘1’

‘0’

REN

SHUTDOWN = 0

High-Z

1

0

SHUTDOWN

FREEZE

D

Q

CWG Data

DS40002002B-page 365

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.2.2 Push-Pull Mode

In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 25-3. This

alternation creates the push-pull effect required for driving some transformer-based power supply designs. Steering

modes are not used in Push-Pull mode. A basic block diagram for the Push-Pull mode is shown in Figure 25-4.

The push-pull sequencer is reset whenever EN = 0or if an auto-shutdown event occurs. The sequencer is clocked by

the first input pulse, and the first output appears on CWG1A.

The unused outputs CWGxC and CWGxD drive copies of CWGxA and CWGxB, respectively, but with polarity

controlled by the POLC and POLD bits of the CWGxCON1 register, respectively.

Figure 25-3.ꢀCWG Push-Pull Mode Operation

Rev. 30-000098A

4/14/2017

CWGx

clock

Input

source

CWGxA

CWGxB

DS40002002B-page 366

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

Figure 25-4.ꢀSimplified CWG Block Diagram (Push-Pull Mode, MODE[2:0] = 101)

LSAC[1:0]

Rev. 10-000210D

2/2/2016

00

01

10

11

‘1’

‘0’

High-Z

1

0

CWG Data A

CWG Data

CWGxA

CWGxB

CWGxC

CWGxD

POLA

POLB

POLC

LSBD[1:0]

D

Q

‘1’

‘0’

00

01

10

11

High-Z

CWG Data B

1

0

CWG Data Input

CWG

Data

Q

D

E

LSAC[1:0]

00

01

10

11

‘1’

‘0’

EN

High-Z

1

0

Auto-shutdown source

(CWGxAS1 register)

S

R

Q

LSBD[1:0]

REN

00

01

10

11

‘1’

‘0’

SHUTDOWN = 0

High-Z

1

0

POLD

SHUTDOWN

FREEZE

D

Q

CWG Data

DS40002002B-page 367

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.2.3 Full-Bridge Modes

In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the

input data signal. The mode selection may be toggled between forward and reverse by toggling the MODE[0] bit of

the CWGxCON0 while keeping MODE[2:1] static, without disabling the CWG module. When connected, as shown in

Figure 25-5, the outputs are appropriate for a full-bridge motor driver. Each CWG output signal has independent

polarity control, so the circuit can be adapted to high-active and low-active drivers. A simplified block diagram for the

Full-Bridge modes is shown in Figure 25-6.

Figure 25-5.ꢀExample of Full-Bridge Application

Rev. 10-000263A

12/8/2015

VDD

FET

Driver

FET

Driver

QA

QC

CWGxA

CWGxB

CWGxC

CWGxD

LOAD

FET

Driver

FET

Driver

QB

QD

DS40002002B-page 368

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

Figure 25-6.ꢀSimplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes)

Rev. 10-000212D

2/2/2016

MODE[2:0] = 010: Forward

MODE[2:0] = 011: Reverse

LSAC[1:0]

00

01

10

11

‘1’

Rising Dead-Band Block

clock

‘0’

CWG Clock

High-Z

signal out

signal in

1

CWG

Data

CWG Data A

POLA

CWGxA

MODE[2:0]

0

D

Q

CWG

Data

LSBD[1:0]

cwg data

‘1’

‘0’

00

01

10

11

signal in

signal out

CWG Clock

High-Z

clock

Falling Dead-Band Block

1

0

CWG Data B

POLB

CWG Data Input

CWG Data

CWGxB

CWGxC

CWGxD

Q

D

E

LSAC[1:0]

00

01

10

11

‘1’

‘0’

EN

High-Z

1

0

CWG Data C

POLC

Auto-shutdown source

(CWGxAS1 register)

S

R

Q

LSBD[1:0]

REN

00

01

10

11

‘1’

‘0’

SHUTDOWN = 0

High-Z

1

0

CWG Data D

POLD

SHUTDOWN

FREEZE

D

Q

CWG Data

In Forward Full-Bridge mode (MODE = 010), CWGxA is driven to its Active state, CWGxB and CWGxC are driven to

their Inactive state, and CWGxD is modulated by the input signal, as shown in Figure 25-7.

DS40002002B-page 369

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

In Reverse Full-Bridge mode (MODE = 011), CWGxC is driven to its Active state, CWGxA and CWGxD are driven to

their Inactive states, and CWGxB is modulated by the input signal, as shown in Figure 25-7.

In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or vice versa. This

dead-band control is described in 25.7 Dead-Band Control, with additional details in 25.8 Rising Edge and Reverse

Dead Band and 25.9 Falling Edge and Forward Dead Band. Steering modes are not used with either of the Full-

Bridge modes. The mode selection may be toggled between forward and reverse toggling the MODE[0] bit of the

CWGxCON0 while keeping MODE[2:1] static, without disabling the CWG module.

Figure 25-7.ꢀExample of Full-Bridge Output

Rev. 30-000099A

4/14/2017

Forward

Mode

Period

CWGxA⁽²⁾

CWGxB⁽²⁾

CWGxC⁽²⁾

Pulse Width

CWGxD⁽²⁾

(1)

Reverse

Mode

Period

CWGxA⁽²⁾

Pulse Width

CWGxB⁽²⁾

CWGxC⁽²⁾

CWGxD⁽²⁾

(1)

Note:ꢀ

1. A rising CWG data input creates a rising event on the modulated output.

2. Output signals shown as active-high; all POL bits are clear.

25.2.3.1 Direction Change in Full-Bridge Mode

In Full-Bridge mode, changing MODE controls the forward/reverse direction. Direction changes occur on the next

rising edge of the modulated input.

A direction change is initiated in software by changing the MODE bits. The sequence is illustrated in Figure 25-8.

•

The associated active output CWGxA and the inactive output CWGxC are switched to drive in the opposite

direction.

The previously modulated output CWGxD is switched to the Inactive state, and the previously inactive output

CWGxB begins to modulate.

CWG modulation resumes after the direction-switch dead band has elapsed.

DS40002002B-page 370

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.2.3.2 Dead-Band Delay in Full-Bridge Mode

Dead-band delay is important when either of the following conditions is true:

1. The direction of the CWG output changes when the duty cycle of the data input is at or near 100%, or

2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on

time.

The dead-band delay is inserted only when changing directions, and only the modulated output is affected. The

statically-configured outputs (CWGxA and CWGxC) are not afforded dead band, and switch essentially

simultaneously.

The following figure shows an example of the CWG outputs changing directions from forward to reverse, at near

100% duty cycle. In this example, at time t1, the output of CWGxA and CWGxD become inactive, while output

CWGxC becomes active. Since the turn-off time of the power devices is longer than the turn-on time, a shoot-through

current will flow through power devices QC and QD for the duration of ‘t’. The same phenomenon will occur to power

devices QA and QB for the CWG direction change from reverse to forward.

When changing the CWG direction at high duty cycle is required for an application, two possible solutions for

eliminating the shoot-through current are:

1. Reduce the CWG duty cycle for one period before changing directions.

2. Use switch drivers that can drive the switches off faster than they can drive them on.

Figure 25-8.ꢀExample of PWM Direction Change at Near 100% Duty Cycle

Rev. 30-000100A

4/14/2017

t1

Forward Period

Reverse Period

CWGxA

CWGxB

Pulse Width

CWGxC

CWGxD

Pulse Width

T

ON

External Switch C

External Switch D

T_OFF

Potential Shoot-

Through Current

T = T_OFF- T_ON

25.2.4 Steering Modes

In both Synchronous and Asynchronous Steering modes, the modulated input signal can be steered to any

combination of four CWG outputs. A fixed-value will be presented on all the outputs not used for the PWM output.

Each output has independent polarity, steering, and shutdown options. Dead-band control is not used in either

steering mode.

DS40002002B-page 371

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

Figure 25-9.ꢀSimplified CWG Block Diagram (Output Steering Modes)

Rev. 10-000211D

5/30/2017

MODE[2:0] = 000: Asynchronous

MODE[2:0] = 001: Synchronous

LSAC[1:0]

00

01

10

11

‘1’

‘0’

High-Z

CWG Data A

POLA

1

0

1

0

CWGxA

CWGxB

CWGxC

CWGxD

OVRA

STRA

LSBD[1:0]

‘1’

‘0’

00

01

10

11

CWG

Data

CWG Data

Input

High-Z

Q

D

E

CWG Data B

POLB

1

0

1

0

OVRB

STRB

EN

LSAC[1:0]

00

01

10

11

‘1’

‘0’

High-Z

CWG Data C

POLC

1

0

Auto-shutdown source

(CWGxAS1 register)

1

0

S

R

Q

OVRC

STRC

LSBD[1:0]

REN

SHUTDOWN = 0

00

01

10

11

‘1’

‘0’

High-Z

CWG Data D

POLD

1

0

1

0

OVRD

SHUTDOWN

FREEZE

STRD

D

Q

CWG Data

DS40002002B-page 372

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

For example, when STRA = 0then the corresponding pin is held at the level defined by OVRA. When STRA = 1,

then the pin is driven by the modulated input signal.

The POLy bits control the signal polarity only when STRy = 1.

The CWG auto-shutdown operation also applies in Steering modes as described in “25.11 Auto-Shutdown”. An auto-

shutdown event will only affect pins that have STRy = 1.

25.2.4.1 Synchronous Steering Mode

In Synchronous Steering mode (MODE = 001), changes to steering selection registers take effect on the next rising

edge of the modulated data input (see figure below). In Synchronous Steering mode, the output will always produce a

complete waveform.

Important:ꢀ Only the STRx bits are synchronized; the OVRx bits are not synchronized.

Figure 25-10.ꢀExample of Synchronous Steering (MODE = 001)

Rev. 30-000101A

4/14/2017

CWGx

clock

Input

source

CWGxA

CWGxB

25.2.4.2 Asynchronous Steering Mode

In Asynchronous mode (MODE = 000), steering takes effect at the end of the instruction cycle that writes to STRx. In

Asynchronous Steering mode, the output signal may be an incomplete waveform (see figure below). This operation

may be useful when the user firmware needs to immediately remove a signal from the output pin.

Figure 25-11.ꢀExample of Asynchronous Steering (MODE = 000)

Rev. 30-000102A

4/14/2017

CWGx

INPUT

End of Instruction Cycle

STRA

CWGxA

CWGxA Follows CWGx data input

25.3

Start-up Considerations

The application hardware must use the proper external pull-up and/or pull-down resistors on the CWG output pins.

This is required because all I/O pins are forced to high-impedance at Reset.

The polarity control bits (POLy) allow the user to choose whether the output signals are active-high or active-low.

DS40002002B-page 373

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.4

Clock Source

The clock source is used to drive the dead-band timing circuits. The CWG module allows the following clock sources

to be selected:

•

F_OSC(system clock)

HFINTOSC

When the HFINTOSC is selected, the HFINTOSC will be kept running during Sleep. Therefore, CWG modes

requiring dead band can operate in Sleep, provided that the CWG data input is also active during Sleep. The clock

sources are selected using the CS bit. The system clock F_OSCis disabled in Sleep and thus dead-band control

cannot be used.

25.5

Selectable Input Sources

The CWG generates the output waveforms having the following input sources:

•

Analog Comparators output

Data Signal Modulator

CLCs

NCO

PWM

CCP

Pin selected by CWGxINPPS

The input sources are selected using the ISM bits in the CWGxISM register.

25.6

Output Control

25.6.1 CWG Outputs

Each CWG output can be routed to a Peripheral Pin Select (PPS) output via the RxyPPS register.

Related Links

16. PPS - Peripheral Pin Select Module

25.6.2 Polarity Control

The polarity of each CWG output can be selected independently. When the output polarity bit is set, the

corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low.

However, polarity does not affect the override levels. Output polarity is selected with the POLy bits. Auto-shutdown

and steering options are unaffected by polarity.

25.7

Dead-Band Control

The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in PWM switches.

Dead-band operation is employed for Half-Bridge and Full-Bridge modes. The CWG contains two 6-bit dead-band

counters. One is used for the rising edge of the input source control in Half-Bridge mode or for reverse dead-band

Full-Bridge mode. The other is used for the falling edge of the input source control in Half-Bridge mode or for forward

dead band in Full-Bridge mode.

Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling dead-band

counter registers.

25.7.1 Dead-Band Functionality in Half-Bridge mode

In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the

rising edge of the inverted output. This can be seen in Figure 25-1.

DS40002002B-page 374

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.7.2 Dead-Band Functionality in Full-Bridge mode

In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE[0] bit can be

set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWGxA and

CWGxC signals will change immediately upon the first rising input edge following a direction change, but the

modulated signals (CWGxB or CWGxD, depending on the direction of the change) will experience a delay dictated by

the dead-band counters.

25.8

Rising Edge and Reverse Dead Band

In Half-Bridge mode, the rising edge dead band delays the turn-on of the CWGxA output after the rising edge of the

CWG data input. In Full-Bridge mode, the reverse dead-band delay is only inserted when changing directions from

Forward mode to Reverse mode, and only the modulated output CWGxB is affected.

The 25.15.3 CWGxDBR register determines the duration of the dead-band interval on the rising edge of the input

source signal. This duration is from 0 to 64 periods of the CWG clock.

Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is

present.

If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on

the respective output.

The CWGxDBR register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBR is written.

When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input, after

the LD bit is set. Refer to the following figure for an example.

Figure 25-12.ꢀDead-Band Operation, CWGxDBR = 0x01, CWGxDBF = 0x02

Rev. 30-000103A

4/14/2017

cwg_clock

Input Source

CWGxA

CWGxB

25.9

Falling Edge and Forward Dead Band

In Half-Bridge mode, the falling edge dead band delays the turn-on of the CWGxB output at the falling edge of the

CWG data input. In Full-Bridge mode, the forward dead-band delay is only inserted when changing directions from

Reverse mode to Forward mode, and only the modulated output CWGxD is affected.

The 25.15.4 CWGxDBF register determines the duration of the dead-band interval on the falling edge of the input

source signal. This duration is from zero to 64 periods of CWG clock.

Dead-band delay is always initiated on the edge of the input source signal. A count of zero indicates that no dead

band is present.

If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on

the respective output.

The CWGxDBF register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBF is written.

When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input after the

LD is set. Refer to the following figure for an example.

DS40002002B-page 375

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

Figure 25-13.ꢀDead-Band Operation, CWGxDBR = 0x03, CWGxDBF = 0x06, Source Shorter Than Dead Band

Rev. 30-000104A

4/14/2017

cwg_clock

Input Source

CWGxA

CWGxB

source shorter than dead band

25.10 Dead-Band Jitter

When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates jitter in the dead-

band time delay. The maximum jitter is equal to one CWG clock period. Refer to the equations below for more details.

Equation 25-1.ꢀDead-Band Delay Time Calculation

1

ꢈ

=

• ꢙꢟꢔ < 5:0 >

ꢙꢝꢞꢙ − ꢟꢞꢠꢙ_ꢂꢡꢠ

ꢢ

ꢌꢁꢣ_ꢌꢖꢊꢌꢤ

1

ꢈ

=

• ꢙꢟꢔ < 5:0 > + 1

ꢙꢝꢞꢙ − ꢟꢞꢠꢙ_ꢂꢡꢠ

ꢙꢝꢞꢙ − ꢟꢞꢠꢙ_ꢂꢞꢥ

ꢢ

ꢌꢁꢣ_ꢌꢖꢊꢌꢤ

ꢈ

= ꢈ

− ꢈ

ꢦꢡꢈꢈꢝꢉ

ꢙꢝꢞꢙ − ꢟꢞꢠꢙ_ꢂꢞꢥ

1

=

ꢢ

ꢌꢁꢣ_ꢌꢖꢊꢌꢤ

ꢈ

= ꢈ

+ ꢈ

ꢙꢝꢞꢙ − ꢟꢞꢠꢙ_ꢂꢞꢥ

ꢙꢝꢞꢙ − ꢟꢞꢠꢙ_ꢂꢡꢠ ꢦꢡꢈꢈꢝꢉ

Equation 25-2.ꢀDead-Band Delay Example Calculation

ꢙꢟꢔ < 5:0 > = 0ꢔ0ꢞ = 10

ꢢ

= 8 ꢂꢕꢧ

ꢌꢁꢣ_ꢌꢖꢊꢌꢤ

1

ꢈ

=

= 125ꢛꢍ

ꢦꢡꢈꢈꢝꢉ

8 ꢂꢕꢧ

ꢈ

= 125ꢛꢍ • 10 = 125ꢨꢍ

ꢙꢝꢞꢙ − ꢟꢞꢠꢙ_ꢂꢡꢠ

ꢈ

= 1.25ꢨꢍ + 0.125 ꢨꢍ = 1.37ꢨꢍ

ꢙꢝꢞꢙ − ꢟꢞꢠꢙ_ꢂꢞꢥ

25.11 Auto-Shutdown

Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe

shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. The

auto-shutdown circuit is illustrated in the following figure.

DS40002002B-page 376

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

Figure 25-14.ꢀCWG Shutdown Block Diagram

Rev. 10-000172C

8/7/2015

Write ‘1’ to

SHUTDOWN bit

PPS

AS0E

CWGxINPPS

C1OUT_sync

AS4E

C2OUT_sync

AS5E

SHUTDOWN

TMR2_postscaled

AS1E

S

R

Q

D

Q

CWG_shutdown

REN

FREEZE

TMR4_postscaled

Write ‘0’ to

SHUTDOWN bit

AS2E

CK

CWG_data

TMR6_postscaled

AS3E

25.11.1 Shutdown

The shutdown state can be entered by either of the following two methods:

•

Software Generated

External Input

25.11.1.1 Software Generated Shutdown

Setting the SHUTDOWN bit will force the CWG into the shutdown state.

When the auto-restart is disabled, the shutdown state will persist as long as the SHUTDOWN bit is set.

When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising

edge event. The SHUTDOWN bit indicates when a shutdown condition exists. The bit may be set or cleared in

software or by hardware.

25.11.1.2 External Input Source

External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition.

When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override

levels without software delay. The override levels are selected by the LSBD and LSAC bits in CWGxAS0 register.

The following input sources can be selected to cause a shutdown condition:

•

CLC2_out/CLC3_out (low causes shutdown)

CMP2_out (low causes shutdown)

CMP1_out (low causes shutdown)

TMR6_postscaled (high causes shutdown)

TMR4_postscaled (high causes shutdown)

TMR2_postscaled (high causes shutdown)

Pin selected by CWGxPPS (low causes shutdown)

The shutdown input sources are individually enabled by the ASyE bits in CWGxAS1 register.

Important:ꢀ Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be

cleared, except by disabling auto-shutdown, as long as the shutdown input level persists.

25.11.1.3 Pin Override Levels

The levels driven to the CWG outputs during an auto-shutdown event are controlled by the LSBD and LSAC bits. The

LSBD bits control CWGxB/D output levels, while the LSAC bits control the CWGxA/C output levels.

25.11.1.4 Auto-Shutdown Interrupts

When an auto-shutdown event occurs, either by software or hardware setting SHUTDOWN, the CWGxIF flag bit of

the PIR7 register is set.

Related Links

7.7.18 PIR7

DS40002002B-page 377

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.11.2 Auto-Shutdown Restart

After an auto-shutdown event has occurred, there are two ways to resume operation:

Software controlled

Auto-restart

•

In either case, the shutdown source must be cleared before the restart can take place. That is, either the shutdown

condition must be removed, or the corresponding ASyE bit must be cleared.

25.11.2.1 Software-Controlled Restart

When the REN bit is clear (REN = 0), the CWG module must be restarted after an auto-shutdown event through

software.

Once all auto-shutdown sources are removed, the software must clear SHUTDOWN. Once SHUTDOWN is cleared,

the CWG module will resume operation upon the first rising edge of the CWG data input.

Important:ꢀ The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still

present.

Figure 25-15.ꢀShutdown Functionality, Auto-Restart Disabled (REN = 0, LSAC = 01, LSBD = 01)

Rev. 30-000105A

4/14/2017

REN Cleared by Software

Shutdown Event Ceases

CWG Input

Source

Shutdown Source

SHUTDOWN

Tri-State (No Pulse)

CWGxA

CWGxC

CWGxB

CWGxD

No Shutdown

Output Resumes

Shutdown

25.11.2.2 Auto-Restart

When the REN bit is set (REN = 1), the CWG module will restart from the shutdown state automatically.

Once all auto-shutdown conditions are removed, the hardware will automatically clear SHUTDOWN. Once

SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input.

Important:ꢀ The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still

present.

DS40002002B-page 378

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

Figure 25-16.ꢀShutdown Functionality, Auto-Restart Enabled (REN = 1, LSAC = 01, LSBD = 01)

Rev. 30-000106A

4/14/2017

Shutdown Event Ceases

REN auto-cleared by hardware

CWG Input

Source

Shutdown Source

SHUTDOWN

Tri-State (No Pulse)

CWGxA

CWGxB

CWGxC

CWGxD

Tri-State (No Pulse)

Shutdown

No Shutdown

Output Resumes

25.12 Operation During Sleep

The CWG module operates independently from the system clock and will continue to run during Sleep, provided that

the clock and input sources selected remain active.

The HFINTOSC remains active during Sleep when all the following conditions are met:

•

CWG module is enabled

Input source is active

HFINTOSC is selected as the clock source, regardless of the system clock source selected.

In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when

the CWG is enabled and the input source is active, then the CPU will go idle during Sleep, but the HFINTOSC will

remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current.

25.13 Configuring the CWG

1. Ensure that the TRIS control bits corresponding to CWG outputs are set so that all are configured as inputs,

ensuring that the outputs are inactive during setup. External hardware should ensure that pin levels are held to

safe levels.

2. Clear the EN bit, if not already cleared.

3. Configure the MODE bits to set the output operating mode.

4. Configure the POLy bits to set the output polarities.

5. Configure the ISM bits to select the data input source.

6. If a steering mode is selected, configure the STRy bits to select the desired output on the CWG outputs.

7. Configure the LSBD and LSAC bits to select the auto-shutdown output override states (this is necessary even

if not using auto-shutdown because start-up will be from a shutdown state).

8. If auto-restart is desired, set the REN bit.

9. If auto-shutdown is desired, configure the ASyE bits to select the shutdown source.

10. Set the desired rising and falling dead-band times with the CWGxDBR and CWGxDBF registers.

11. Select the clock source with the CS bits.

12. Set the EN bit to enable the module.

13. Clear the TRIS bits that correspond to the CWG outputs to set them as outputs.

If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear

the SHUTDOWN bit in software to start the CWG.

DS40002002B-page 379

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.14 Register Summary - CWG Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x060B

0x060C

0x060D

0x060E

0x060F

0x0610

0x0611

0x0612

0x0613

0x0614

0x0615

0x0616

0x0617

0x0618

0x0619

0x061A

0x061B

0x061C

0x061D

0x061E

CWG1CLK

CWG1ISM

CWG1DBR

CWG1DBF

CWG1CON0

CWG1CON1

CWG1AS0

CWG1AS1

CWG1STR

Reserved

7:0

CS

ISM[3:0]

DBR[5:0]

DBF[5:0]

EN

LD

MODE[2:0]

IN

POLD

POLC

POLB

POLA

SHUTDOWN

OVRD

REN

LSBD[1:0]

LSAC[1:0]

AS5E

AS4E

AS3E

STRD

AS2E

STRC

AS1E

STRB

AS0E

STRA

OVRC

OVRB

OVRA

CWG2CLK

CWG2ISM

CWG2DBR

CWG2DBF

CWG2CON0

CWG2CON1

CWG2AS0

CWG2AS1

CWG2STR

7:0

CS

ISM[3:0]

DBR[5:0]

DBF[5:0]

EN

LD

MODE[2:0]

POLB

IN

POLD

POLC

POLA

SHUTDOWN

OVRD

REN

LSBD[1:0]

LSAC[1:0]

AS5E

AS4E

AS3E

STRD

AS2E

STRC

AS1E

STRB

AS0E

STRA

OVRC

OVRB

OVRA

25.15 Register Definitions: CWG Control

Long bit name prefixes for the CWG peripherals are shown in the table below. Refer to the “Long Bit Names Section”

for more information.

Table 25-1.ꢀCWG Bit Name Prefixes

Peripheral

CWG1

Bit Name Prefix

CWG1

CWG2

DS40002002B-page 380

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.1 CWGxCLK

Name:ꢀ

Offset:ꢀ

CWGxCLK

0x60C,0x616

CWGx Clock Input Selection Register

Bit

7

6

5

4

3

2

1

0

CS

R/W

0

Access

Reset

Bit 0 – CSꢀClock Source

CWG Clock Source Selection Select bits

Value

Description

1

0

HFINTOSC (remains operating during Sleep)

F_OSC

DS40002002B-page 381

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.2 CWGxISM

Name:ꢀ

Offset:ꢀ

CWGxISM

0x60D,0x617

CWGx Input Selection Register

Bit

7

6

5

4

3

2

1

0

ISM[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 3:0 – ISM[3:0]ꢀCWG Data Input Source Select bits

Table 25-2.ꢀCWG Data Input Sources

ISM

Data Source

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Reserved

CLC4_out

CLC3_out

CLC2_out

CLC1_out

DSM1_out

C2_out

C1_out

NCO1_out

PWM7_out

PWM6_out

CCP4_out

CCP3_out

CCP2_out

CCP1_out

Pin selected by CWGxINPPS

DS40002002B-page 382

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.3 CWGxDBR

Name:ꢀ

Offset:ꢀ

CWGxDBR

0x60E,0x618

CWG Rising Dead-Band Count Register

Bit

7

6

5

4

3

2

1

0

DBR[5:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 5:0 – DBR[5:0]ꢀCWG Rising Edge-Triggered Dead-Band Count bits

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value

Description

n

0

Dead band is active no less than n, and no more than n+1, CWG clock periods after the rising edge

0 CWG clock periods. Dead-band generation is bypassed

DS40002002B-page 383

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.4 CWGxDBF

Name:ꢀ

Offset:ꢀ

CWGxDBF

0x60F,0x619

CWG Falling Dead-Band Count Register

Bit

7

6

5

4

3

2

1

0

DBF[5:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 5:0 – DBF[5:0]ꢀCWG Falling Edge-Triggered Dead-Band Count bits

Reset States: POR/BOR = xxxxxx

All Other Resets = uuuuuu

Value

Description

n

0

Dead band is active no less than n, and no more than n+1, CWG clock periods after the falling edge

0 CWG clock periods. Dead-band generation is bypassed

DS40002002B-page 384

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.5 CWGxCON0

Name:ꢀ

Offset:ꢀ

CWGxCON0

0x610,0x61A

CWG Control Register 0

Bit

7

EN

R/W

0

6

LD

5

4

3

2

1

MODE[2:0]

R/W

0

Access

Reset

R/W/HC

0

R/W

0

R/W

0

Bit 7 – ENꢀCWG1 Enable bit

Value

Description

1

0

Module is enabled

Module is disabled

Bit 6 – LDꢀ CWG1 Load Buffers bit⁽¹⁾

Value

Description

1

Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit

is set

0

Buffers remain unchanged

Bits 2:0 – MODE[2:0]ꢀCWG1 Mode bits

Value

111

110

101

100

011

010

001

000

Description

Reserved

CWG outputs operate in Push-Pull mode

CWG outputs operate in Half-Bridge mode

CWG outputs operate in Reverse Full-Bridge mode

CWG outputs operate in Forward Full-Bridge mode

CWG outputs operate in Synchronous Steering mode

CWG outputs operate in Asynchronous Steering mode

Note:ꢀ

1. This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.

DS40002002B-page 385

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.6 CWGxCON1

Name:ꢀ

Offset:ꢀ

CWGxCON1

0x611,0x61B

CWG Control Register 1

Bit

7

6

5

IN

RO

x

4

3

POLD

R/W

0

2

POLC

R/W

0

1

POLB

R/W

0

POLA

R/W

0

Access

Reset

Bit 5 – INꢀCWG Input Value bit (read-only)

Value

Description

1

0

CWG input is a logic 1

CWG input is a logic 0

Bits 0, 1, 2, 3 – POLyꢀCWG Output ‘y’ Polarity bit

Value

Description

1

0

Signal output is inverted polarity

Signal output is normal polarity

DS40002002B-page 386

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.7 CWGxAS0

Name:ꢀ

Offset:ꢀ

CWGxAS0

0x612,0x61C

CWG Auto-Shutdown Control Register 0

Bit

7

6

5

4

3

2

1

0

SHUTDOWN

R/W/HS/HC

0

REN

R/W

0

LSBD[1:0]

LSAC[1:0]

Access

Reset

R/W

0

R/W

1

R/W

0

R/W

1

Bit 7 – SHUTDOWNꢀ Auto-Shutdown Event Status bit^(1,2)

Value

Description

1

0

An auto-shutdown state is in effect

No auto-shutdown event has occurred

Bit 6 – RENꢀAuto-Restart Enable bit

Value

Description

1

0

Auto-restart is enabled

Auto-restart is disabled

Bits 5:4 – LSBD[1:0]ꢀCWGxB and CWGxD Auto-Shutdown State Control bits

Value

Description

11

A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event occurs.

A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event occurs.

Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs.

The Inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band

interval when an auto-shutdown event occurs.

10

01

00

Bits 3:2 – LSAC[1:0]ꢀCWGxA and CWGxC Auto-Shutdown State Control bits

Value

Description

11

A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event occurs.

A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event occurs.

Pin is tri-stated on CWGxA/C when an auto-shutdown event occurs.

The Inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band

interval when an auto-shutdown event occurs.

10

01

00

Note:ꢀ

1. This bit may be written while EN = 0(25.15.5 CWGxCON0), to place the outputs into the shutdown

configuration.

2. The outputs will remain in Auto-shutdown state until the next rising edge of the CWG data input after this bit is

cleared.

DS40002002B-page 387

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.8 CWGxAS1

Name:ꢀ

Offset:ꢀ

CWGxAS1

0x613,0x61D

CWG Auto-Shutdown Control Register 1

Bit

7

6

5

AS5E

R/W

0

4

AS4E

R/W

0

3

AS3E

R/W

0

2

AS2E

R/W

0

1

AS1E

R/W

0

AS0E

R/W

0

Access

Reset

Bits 0, 1, 2, 3, 4, 5 – ASyEꢀCWG Auto-shutdown Source ASyE Enable bit(1)

Table 25-3.ꢀShutdown Sources

ASyE

AS6E

AS5E

AS4E

AS3E

AS2E

AS1E

AS0E

Source

CLC2_out/CLC3_out (low causes shutdown)

CMP2_out (low causes shutdown)

CMP1_out (low causes shutdown)

TMR6_postscaled (high causes shutdown)

TMR4_postscaled (high causes shutdown)

TMR2_postscaled (high causes shutdown)

Pin selected by CWGxPPS (low causes shutdown)

Value

Description

1

0

Auto-shutdown for source ASyE is enabled

Auto-shutdown for source ASyE is disabled

Note:ꢀ 1. This bit may be written while EN = 0(25.15.5 CWGxCON0), to place the outputs into the shutdown

configuration.

The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this bit is

cleared.

DS40002002B-page 388

Datasheet

PIC16(L)F18425/45

CWG - Complementary Waveform Generator

25.15.9 CWGxSTR

Name:ꢀ

Offset:ꢀ

CWGxSTR

0x614,0x61E

CWG Steering Control Register ⁽¹⁾

Bit

7

OVRD

R/W

0

6

OVRC

R/W

0

5

OVRB

R/W

0

4

OVRA

R/W

0

3

STRD

R/W

0

2

STRC

R/W

0

1

STRB

R/W

0

STRA

R/W

0

Access

Reset

Bits 4, 5, 6, 7 – OVRyꢀSteering Data OVR'y' bit

Value

Condition

Description

x

STRy = 1

CWGx'y' output has the CWG data input waveform with polarity control from

POLy bit

1

0

STRy = 0and POLy = x CWGx'y' output is high

STRy = 0and POLy = x CWGx'y' output is low

Bits 0, 1, 2, 3 – STRyꢀ STR'y' Steering Enable bit⁽²⁾

Value

Description

1

0

CWGx'y' output has the CWG data input waveform with polarity control from POLy bit

CWGx'y' output is assigned to value of OVRy bit

Note:ꢀ

1. The bits in this register apply only when MODE = '00x'(25.15.5 CWGxCON0, Steering modes).

2. This bit is double-buffered when MODE = '001'.

DS40002002B-page 389

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.

NCO - Numerically Controlled Oscillator

The Numerically Controlled Oscillator (NCO) module is a timer that uses overflow from the addition of an increment

value to divide the input frequency. The advantage of the addition method over simple counter driven timer is that the

output frequency resolution does not vary with the divider value. The NCO is most useful for application that requires

frequency accuracy and fine resolution at a fixed duty cycle.

Features of the NCO include:

•

20-bit Increment Function

Fixed Duty Cycle mode (FDC) Mode

Pulse Frequency (PF) Mode

Output Pulse Width Control

Multiple Clock Input Sources

Output polarity Control

Interrupt Capability

Figure 26-1 is a simplified block diagram of the NCO module.

Figure 26-1.ꢀNumerically Controlled Oscillator Module Simplified Block Diagram

NCOxINC

Rev. 10-000028E

1/16/2019

20

(1)

INCxBUF

20

1111

NCO_overflow

Adder

20

NCOx Clock

Sources

NCOx_clk

NCOxACC

20

See

NCOxCLK

Register

NCO_interrupt

Set NCOxIF

0000

Fixed Duty

Cycle Mode

Circuitry

TRIS control

CKS[3:0]

D

Q

D

Q

0

1

4

PPS

_

Q

NCOxOUT

RxyPPS

PFM

POL

To Peripherals

OUT

NCOx_out

S

Q

EN

D

Q

_

Q

Ripple

Counter

R

Q1

Pulse

R

Frequency

Mode Circuitry

3

PWS[2:0]

Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling

the NCO module. The full increment value is loaded into the buffer registers on the second rising edge of the

NCOx_clk signal that occurs immediately after a write to the NCOxINCL register. The buffers are not user-

accessible and are shown here for reference.

DS40002002B-page 390

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.1

NCO Operation

The NCO operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate. The

accumulator will overflow with a carry periodically, which is the raw NCO output (NCO_overflow). This effectively

reduces the input clock by the ratio of the addition value to the maximum accumulator value. Refer to Equation 26-1

for details.

The NCO output can be further modified by stretching the pulse or toggling a flip-flop. The modified NCO output is

then distributed internally to other peripherals and can optionally be output to a pin. The accumulator overflow also

generates an interrupt (NCO_interrupt). The NCO period changes in discrete steps to create an average frequency.

Equation 26-1.ꢀNCO Overflow Frequency

ꢠꢌꢊ ꢌꢐꢆꢎꢩ ꢢꢄꢃꢪꢒꢃꢛꢎꢚ × ꢡꢛꢎꢄꢃꢫꢃꢛꢓ ꢑꢏꢐꢒꢃ

ꢢ

=

ꢊꢑꢝꢉꢢꢖꢊꢁ

20

2

26.1.1 NCO Clock Sources

Clock sources available to the NCO include:

•

HFINTOSC

FOSC

LC1_out

The NCO clock source is selected by configuring the CKS bits in the NCOxCLK register.

Related Links

26.9.4 NCOxCLK

26.1.2 Accumulator

The accumulator is a 20-bit register. Read and write access to the accumulator is available through three registers:

•

NCOxACCL

NCOxACCH

NCOxACCU

Related Links

26.9.1 NCOxACC

26.1.3 Adder

The NCO Adder is a full adder, which operates independently from the system clock. The addition of the previous

result and the increment value replaces the accumulator value on the rising edge of each input clock.

26.1.4 Increment Registers

The increment value is stored in three registers making up a 20-bit incrementer. In order of LSB to MSB they are:

•

NCOxINCL

NCOxINCH

NCOxINCU

When the NCO module is enabled, the NCOxINCU and NCOxINCH registers should be written first, then the

NCOxINCL register. Writing to the NCOxINCL register initiates the increment buffer registers to be loaded

simultaneously on the second rising edge of the NCO_clk signal.

The registers are readable and writable. The increment registers are double-buffered to allow value changes to be

made without first disabling the NCO module.

When the NCO module is disabled, the increment buffers are loaded immediately after a write to the increment

registers.

DS40002002B-page 391

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

Important:ꢀ The increment buffer registers are not user-accessible.

Related Links

26.9.2 NCOxINC

26.2

Fixed Duty Cycle Mode

In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows (NCO_overflow), the output is toggled. This

provides a 50% duty cycle with a constant frequency, provided that the increment value remains constant.

The FDC frequency can be calculated using Equation 26-2. The FDC frequency is half of the overflow frequency

since it takes two overflow events to generate one FDC clock period. For more information, refer to Figure 26-2.

Equation 26-2.ꢀFDC Frequency

ꢢ

= ꢢ

/2

ꢬꢇꢎ

ꢆꢘꢃꢄꢬꢐꢆꢭ

Figure 26-2.ꢀFDC Output Mode Operation Diagram

Rev. 10-000029A

11/7/2013

NCOx

Clock

Source

NCOx

Increment

Value

4000h

NCOx

Accumulator

Value

00000h 04000h 08000h

FC000h 00000h 04000h 08000h

NCO_overflow

NCO_interrupt

NCOx Output

FDC Mode

NCOx Output

PF Mode

NCOxPWS =

000

NCOx Output

PF Mode

NCOxPWS =

001

Related Links

26.9.3 NCOxCON

DS40002002B-page 392

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.3

Pulse Frequency Mode

In Pulse Frequency (PF) mode, every time the Accumulator overflows, the output becomes active for one or more

clock periods. Once the clock period expires, the output returns to an inactive state. This provides a pulsed output.

The output becomes active on the rising clock edge immediately following the overflow event. For more information,

refer to Figure 26-2.

The value of the active and inactive states depends on the POL bit in the NCOxCON register.

The PF mode is selected by setting the PFM bit in the NCOxCON register.

Related Links

26.9.3 NCOxCON

26.3.1 Output Pulse Width Control

When operating in PF mode, the active state of the output can vary in width by multiple clock periods. Various pulse

widths are selected with the PWS bits.

When the selected pulse width is greater than the Accumulator overflow time frame, then NCO output does not

toggle.

Related Links

26.9.4 NCOxCLK

26.4

Output Polarity Control

The last stage in the NCO module is the output polarity. The POL bit in the NCOxCON register selects the output

polarity. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output

transition.

The NCO output can be used internally by source code or other peripherals. Accomplish this by reading the NxOUT

(read-only) bit of the NCOxCON register. The NCO output signal (NCOx_out) is available to the following peripherals:

•

CLC

CWG

Timer1

Timer2

CLKR

26.5

Interrupts

When the accumulator overflows (NCO_overflow), the NCO Interrupt Flag bit, NCO1IF, of the PIR7 register is set. To

enable the interrupt event (NCO_interrupt), the following bits must be set:

•

EN bit

NCO1IE bit of the PIE7 register

PEIE bit of the INTCON register

GIE bit of the INTCON register

The interrupt must be cleared by software by clearing the NCO1IF bit in the Interrupt Service Routine.

Related Links

26.9.3 NCOxCON

5.8.10 INTCON

7.7.18 PIR7

7.7.9 PIE7

DS40002002B-page 393

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.6

26.7

Effects of a Reset

All of the NCO registers are cleared to zero as the result of a Reset.

Operation in Sleep

The NCO module operates independently from the system clock and will continue to run during Sleep, provided that

the clock source selected remains active.

The HFINTOSC remains active during Sleep when the NCO module is enabled and the HFINTOSC is selected as the

clock source, regardless of the system clock source selected.

In other words, if the HFINTOSC is simultaneously selected as the system clock and the NCO clock source, when the

NCO is enabled, the CPU will go Idle during Sleep, but the NCO will continue to operate and the HFINTOSC will

remain active.

This will have a direct effect on the Sleep mode current.

DS40002002B-page 394

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.8

Register Summary - NCO

Offset

Name

Bit Pos.

0x00

...

Reserved

0x058B

7:0

15:8

23:16

7:0

ACC[7:0]

ACC[15:8]

ACC[23:16]

INC[7:0]

0x058C

0x058F

NCO1ACC

NCO1INC

15:8

23:16

7:0

INC[15:8]

INC[19:16]

0x0592

0x0593

NCO1CON

NCO1CLK

EN

OUT

POL

PFM

7:0

PWS[2:0]

CKS[3:0]

26.9

Register Definitions: NCO

DS40002002B-page 395

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.9.1 NCOxACC

Name:ꢀ

Offset:ꢀ

NCOxACC

0x058C

NCO Accumulator Register

Bit

23

22

21

20

19

18

17

16

ACC[23:16]

ACC[15:8]

ACC[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

15

14

13

12

11

10

9

8

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 23:0 – ACC[23:0]ꢀAccumulated sum of NCO additions

Note:ꢀ

1. The individual bytes in this multi-byte register can be accessed with the following register names:

– NCOxACCU: Accesses the upper byte ACC[23:16]

– NCOxACCH: Accesses the high byte ACC[15:8]

– NCOxACCL: Accesses the low byte ACC[7:0]

2. The accumulator spans registers NCOxACCU:NCOxACCH:NCOxACCL. The 24 bits are reserved but not all

are used. This register updates in real-time, asynchronously to the CPU; there is no provision to ensure atomic

access to this 24-bit space using an 8-bit bus. Writing to this register while the module is operating will

produce undefined results.

DS40002002B-page 396

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.9.2 NCOxINC

Name:ꢀ

Offset:ꢀ

NCOxINC

0x058F

NCO Increment Register

Bit

23

22

21

13

20

12

19

18

17

16

INC[19:16]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bit

15

14

11

10

9

8

INC[15:8]

INC[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 19:0 – INC[19:0]ꢀ Value by which the NCOxACC is increased by each NCO clock^(1,2)

Note:ꢀ

1. The individual bytes in this multi-byte register can be accessed with the following register names:

– NCOxINCU: Accesses the upper byte INC[19:16]

– NCOxINCH: Accesses the high byte INC[15:8]

– NCOxINCL: Accesses the low byte INC[7:0]

2. The logical increment spans NCOxINCU:NCOxINCH:NCOxINCL.

3. NCOxINC is double-buffered as INCBUF

– INCBUF is updated on the next falling edge of NCOxCLK after writing to NCOxINCL

– NCOxINCU and NCOxINCH should be written prior to writing NCOxINCL

DS40002002B-page 397

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.9.3 NCOxCON

Name:ꢀ

Offset:ꢀ

NCOxCON

0x0592

NCO Control Register

Bit

7

EN

R/W

0

6

5

OUT

RO

0

4

3

2

1

0

POL

R/W

0

PFM

R/W

0

Access

Reset

Bit 7 – ENꢀNCO Enable bit

Value

Description

1

0

NCO module is enabled

NCO module is disabled

Bit 5 – OUTꢀNCO Output bit

Displays the current output value of the NCO module.

Bit 4 – POLꢀNCO Polarity bit

Value

Description

1

0

NCO output signal is inverted

NCO output signal is not inverted

Bit 0 – PFMꢀNCO Pulse Frequency Mode bit

Value

Description

1

NCO operates in Pulse Frequency mode

0

NCO operates in Fixed Duty Cycle mode, divide by 2

DS40002002B-page 398

Datasheet

PIC16(L)F18425/45

NCO - Numerically Controlled Oscillator

26.9.4 NCOxCLK

Name:ꢀ

Offset:ꢀ

NCOxCLK

0x0593

NCO Input Clock Control Register

Bit

7

6

PWS[2:0]

R/W

5

4

3

2

1

0

CKS[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:5 – PWS[2:0]ꢀNCO Output Pulse Width Select bits(1)

Value

111

110

101

100

011

010

001

000

Description

NCO output is active for 128 input clock periods

NCO output is active for 64 input clock periods

NCO output is active for 32 input clock periods

NCO output is active for 16 input clock periods

NCO output is active for 8 input clock periods

NCO output is active for 4 input clock periods

NCO output is active for 2 input clock periods

NCO output is active for 1 input clock periods

Bits 3:0 – CKS[3:0]ꢀNCO Clock Source Select bits

Description

Table 26-1.ꢀNCO Clock Sources

CKS

1111-1011

1010

Clock Source

Reserved

CLC4_out

1001

CLC3_out

1000

CLC2_out

0111

CLC1_out

0110

CLKR

0101

SOSC

0100

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

LFINTOSC

HFINTOSC

F_OSC

0011

0010

0001

0000

Note:ꢀ

1. PWS applies only when operating in Pulse Frequency mode.

DS40002002B-page 399

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

27.

DSM - Data Signal Modulator Module

The Data Signal Modulator (DSM) is a peripheral that allows the user to mix a data stream, also known as a

modulator signal, with a carrier signal to produce a modulated output.

Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a

peripheral, or externally through an input pin.

The modulated output signal is generated by performing a logical “AND” operation of both the carrier and modulator

signals and then provided to the MDOUT pin.

The carrier signal is comprised of two distinct and separate signals. A Carrier High (CARH) signal and a Carrier Low

(CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the

CARH signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the CARL

signal with the modulator signal.

Using this method, the DSM can generate the following types of key modulation schemes:

•

Frequency-Shift Keying (FSK)

Phase-Shift Keying (PSK)

On-Off Keying (OOK)

Additionally, the following features are provided within the DSM module:

•

Carrier Synchronization

Carrier Source Polarity Select

Programmable Modulator Data

Modulated Output Polarity Select

Peripheral Module Disable, which provides the ability to place the DSM module in the lowest power consumption

mode

The figure below shows a simplified block diagram of the data signal modulator peripheral.

DS40002002B-page 400

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

Figure 27-1.ꢀSimplified Block Diagram of the Data Signal Modulator

Rev. 10-000248F

1/19/2016

MDCHS[3:0]

Data Signal Modulator

0000

See

MDCARH

Register

CARH

D

MDCHPOL

1111

SYNC

Q

1

0

MDSRCS[4:0]

00000

MDCHSYNC

RxyPPS

See

MDSRC

Register

MOD

PPS

MDOPOL

11111

MDCLS[3:0]

D

SYNC

Q

0000

1

0

See

MDCARL

Register

CARL

MDCLSYNC

MDCLPOL

1111

27.1

27.2

DSM Operation

The DSM module can be enabled by setting the EN bit in the MDCON0 register. Clearing the EN bit, disables the

output of the module but retain the carrier and source signal selections. The module will resume operation when the

EN bit is set again. The output of the DSM module can be rerouted to several pins using the RxyPPS register. When

the EN bit is cleared the output pin is held low.

Modulator Signal Sources

The modulator signal can be supplied from the following sources:

•

EUSART

DS40002002B-page 401

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

•

MSSP

CLC

NCO

CCP/PWM

NCO

internal MDBIT

I/O pin

The sources are selected using the SRCS bits in the MDxSRC register.

27.3

Carrier Signal Sources

The carrier high signal and carrier low signal can be supplied from the following sources:

•

CCPs

CLCs

PWMs

NCO

Reference clocks

System clocks

I/O pin

The carrier high signal is selected by using the CHS bits in the MDxCARH register.

The carrier low signal is selected by using the CLS bits in the MDxCARL register.

27.4

Carrier Synchronization

During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the

modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the

modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition

is allowed to transition low before the DSM switches over to the next carrier source.

Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the

carrier high signal is enabled by setting the CHSYNC bit. Synchronization for the carrier low signal is enabled by

setting the CLSYNC bit.

The figures below show the timing diagrams of using various synchronization methods.

Figure 27-2.ꢀOn Off Keying (OOK) Synchronization

Rev. 30-000144A

5/26/2017

carrier_low

carrier_high

modulator

MDCHSYNC = 1

MDCLSYNC = 0

MDCHSYNC = 1

MDCLSYNC = 1

MDCHSYNC = 0

MDCLSYNC = 0

MDCHSYNC = 0

MDCLSYNC = 1

DS40002002B-page 402

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

Figure 27-3.ꢀNo Synchronization (MDCHSYNC = 0, MDCLSYNC = 0)

Rev. 30-000145A

5/26/2017

carrier_high

carrier_low

modulator

MDCHSYNC = 0

MDCLSYNC = 0

carrier_high

carrier_low

carrier_high

carrier_low

Active Carrier

State

Figure 27-4.ꢀCarrier High Synchronization (MDCHSYNC = 1, MDCLSYNC = 0)

Rev. 30-000146A

5/26/2017

carrier_high

carrier_low

modulator

MDCHSYNC = 1

MDCLSYNC = 0

Active Carrier

carrier_high

carrier_low

both

State

Figure 27-5.ꢀCarrier Low Synchronization (MDCHSYNC = 0, MDCLSYNC = 1)

Rev. 30-000147A

5/26/2017

carrier_high

carrier_low

modulator

MDCHSYNC = 0

MDCLSYNC = 1

Active Carrier

carrier_high

carrier_low

carrier_high

carrier_low

State

Figure 27-6.ꢀFull Synchronization (MDCHSYNC = 1, MDCLSYNC = 1)

Rev. 30-000148A

5/26/2017

carrier_high

carrier_low

modulator

Falling edges

used to sync

MDCHSYNC = 1

MDCLSYNC = 1

Active Carrier

State

carrier_high

carrier_low

CL

DS40002002B-page 403

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

27.5

Carrier Source Polarity Select

The signal provided from any selected input source for the carrier high and carrier low signals can be inverted.

Inverting the signal for the carrier high and low source is enabled by setting the CHPOL bit and the CLPOL bit,

respectively.

27.6

27.7

27.8

Programmable Modulator Data

The BIT control bit can be selected as the modulation source. This gives the user the ability to provide software

driven modulation.

Modulated Output Polarity

The modulated output signal provided on the DSM pin can also be inverted. Inverting the modulated output signal is

enabled by setting the OPOL bit.

Operation in Sleep Mode

The DSM can still operate during Sleep, if the carrier and modulator input sources are also still operable during

Sleep. Refer to “Power-Saving Operation Modes” for more details.

Related Links

12. Power-Saving Operation Modes

27.9

Effects of a Reset

Upon any device Reset, the DSM module is disabled. The user’s firmware is responsible for initializing the module

before enabling the output. All the registers are reset to their default values.

27.10 Peripheral Module Disable

The DSM module can be completely disabled using the PMD module to achieve maximum power saving. When the

DSM1MD bit of PMD7 register is set, the DSM module is completely disabled. This puts the module in its lowest

Power Consumption state. When enabled again all the registers of the DSM module default to POR status.

Related Links

13.5 Register Definitions: Peripheral Module Disable

DS40002002B-page 404

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

27.11 Register Summary - DSM

Offset

Name

Bit Pos.

0x00

...

Reserved

0x0896

0x0897

0x0898

0x0899

0x089A

0x089B

MD1CON0

MD1CON1

MD1SRC

7:0

EN

OUT

OPOL

CHSYNC

BIT

CHPOL

CLPOL

CLSYNC

SRCS[4:0]

CLS[3:0]

CHS[3:0]

MD1CARL

MD1CARH

27.12 Register Definitions: Modulation Control

DS40002002B-page 405

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

27.12.1 MDxCON0

Name:ꢀ

Offset:ꢀ

MDxCON0

0x0897

Modulation Control Register 0

Bit

7

EN

R/W

0

6

5

4

OPOL

R/W

0

3

2

1

0

BIT

R/W

0

OUT

R/W

0

Access

Reset

Bit 7 – ENꢀModulator Module Enable bit

Value

Description

1

0

Modulator module is enabled and mixing input signals

Modulator module is disabled and has no output

Bit 5 – OUTꢀModulator Output bit

Displays the current output value of the modulator module.

Bit 4 – OPOLꢀModulator Output Polarity Select bit

Value

Description

1

0

Modulator output signal is inverted; idle high output

Modulator output signal is not inverted; idle low output

Bit 0 – BITꢀModulation Source Select Input bit

Allows software to manually set modulation source input to module

Note:ꢀ

1. The modulated output frequency can be greater and asynchronous from the clock that updates this register bit,

the bit value may not be valid for higher speed modulator or carrier signals.

2. MDBIT must be selected as the modulation source in the MDxSRC register for this operation.

DS40002002B-page 406

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

27.12.2 MDxCON1

Name:ꢀ

Offset:ꢀ

MDxCON1

0x0898

Modulation Control Register 1

Bit

7

6

5

CHPOL

R/W

0

4

CHSYNC

R/W

3

2

1

CLPOL

R/W

0

CLSYNC

R/W

Access

Reset

0

Bit 5 – CHPOLꢀModulator High Carrier Polarity Select bit

Value

Description

1

0

Selected high carrier signal is inverted

Selected high carrier signal is not inverted

Bit 4 – CHSYNCꢀModulator High Carrier Synchronization Enable bit

Value

Description

1

Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low

time carrier

0

Modulator output is not synchronized to the high time carrier signal

Bit 1 – CLPOLꢀModulator Low Carrier Polarity Select bit

Value

Description

1

0

Selected low carrier signal is inverted

Selected low carrier signal is not inverted

Bit 0 – CLSYNCꢀModulator Low Carrier Synchronization Enable bit

Value

Description

1

Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high

time carrier

0

Modulator output is not synchronized to the low time carrier signal

Note:ꢀ

1. Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

DS40002002B-page 407

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

27.12.3 MDxSRC

Name:ꢀ

Offset:ꢀ

MDxSRC

0x0899

Modulation Source Control Register

Bit

7

6

5

4

3

2

SRCS[4:0]

R/W

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – SRCS[4:0]ꢀModulator Source Selection bits

Table 27-1.ꢀMDSRC Selection MUX Connections

SRCS[4:0]

11111-10010

10001

Connection

Reserved

MSSP2 - SDO

MSSP1 - SDO

10000

01111

EUSART1 TX (TX/CK output)

CLC4 OUT

01110

01101

CLC3 OUT

01100

CLC2 OUT

01011

CLC1 OUT

01010

C2 OUT

01001

C1 OUT

01000

NCO1 OUT

00111

PWM7 OUT

PWM6 OUT

CCP4 OUT

00110

00101

00100

CCP3 OUT

00011

CCP2 OUT

00010

CCP1 OUT

00001

MDBIT

00000

Pin selected by MDSRCPPS

DS40002002B-page 408

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

27.12.4 MDxCARL

Name:ꢀ

Offset:ꢀ

MDxCARL

0x089A

Modulation Low Carrier Control Register

Bit

7

6

5

4

3

2

1

0

CLS[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 3:0 – CLS[3:0]ꢀModulator Carrier Low Input Selection bits

Table 27-2.ꢀMDCARL Source Selections

MDCARL

CLS[3:0]

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

Connection

Reserved

CLC4 OUT

CLC3 OUT

CLC2 OUT

CLC1 OUT

NCO1 OUT

PWM7 OUT

PWM6 OUT

CCP4 OUT

CCP3 OUT

CCP2 OUT

CCP1 OUT

CLKREF output

HFINTOSC

F_OSC(system clock)

0000

Pin selected by MDCARLPPS

DS40002002B-page 409

Datasheet

PIC16(L)F18425/45

DSM - Data Signal Modulator Module

27.12.5 MDxCARH

Name:ꢀ

Offset:ꢀ

MDxCARH

0x089B

Modulation High Carrier Control Register

Bit

7

6

5

4

3

2

1

0

CHS[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 3:0 – CHS[3:0]ꢀModulator Carrier High Selection bits

Table 27-3.ꢀMDCARH Source Selections

MDCARH

CHS[3:0]

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Connection

Reserved

CLC4 OUT

CLC3 OUT

CLC2 OUT

CLC1 OUT

NCO1 OUT

PWM7 OUT

PWM6 OUT

CCP4 OUT

CCP3 OUT

CCP2 OUT

CCP1 OUT

CLKREF output

HFINTOSC

F_OSC(system clock)

Pin selected by MDCARHPPS

DS40002002B-page 410

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.

EUSART - Enhanced Universal Synchronous Asynchronous Receiver

Transmitter

The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform

an input or output serial data transfer independent of device program execution. The EUSART, also known as a

Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex

synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals

and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices,

such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not

have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous

device.

The EUSART module includes the following capabilities:

•

Full-Duplex Asynchronous Transmit and Receive

Two-Character Input Buffer

One-Character Output Buffer

Programmable 8-Bit or 9-Bit Character Length

Address Detection in 9-bit Mode

Input Buffer Overrun Error Detection

Received Character Framing Error Detection

Half-Duplex Synchronous Master

Half-Duplex Synchronous Slave

Programmable Clock Polarity in Synchronous Modes

Sleep Operation

The EUSART module implements the following additional features, making it ideally suited for use in Local

Interconnect Network (LIN) bus systems:

•

Automatic detection and calibration of the baud rate

Wake-up on Break reception

13-bit Break character transmit

Block diagrams of the EUSART transmitter and receiver are shown in Figure 28-1 and Figure 28-2.

The operation of the EUSART module consists of six registers:

•

Transmit Status and Control (28.6.5 TXxSTA)

Receive Status and Control (28.6.4 RCxSTA)

Baud Rate Control (28.6.6 BAUDxCON)

Baud Rate Value (28.6.3 SPxBRG)

Receive Data Register (28.6.1 RCxREG)

Transmit Data Register (28.6.2 TXxREG)

The RXx/DTx and TXx/CKx input pins are selected with the RXxPPS and TXxPPS registers, respectively. TXx, CKx,

and DTx output pins are selected with each pin’s RxyPPS register. Since the RX input is coupled with the DT output

in Synchronous mode, it is the user’s responsibility to select the same pin for both of these functions when operating

in Synchronous mode. The EUSART control logic will control the data direction drivers automatically.

DS40002002B-page 411

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

Figure 28-1.ꢀEUSART Transmit Block Diagram

Rev. 10-000 113C

2/15/201 7

Data bus

8

TXIE

TXIF

Interrupt

TXREG register

8

SYNC

CSRC

RxyPPS⁽¹⁾

RXx/DTx Pin

TXEN

CKx Pin

MSb

(8)

LSb

0

Pin Buffer

and Control

PPS

1

0

PPS

Transmit Shift Register (TSR)

CKPPS⁽²⁾

TX_out

TRMT

Baud Rate Generator

BRG16

FOSC

÷ n

TX9

n

TXx/CKx Pin

TX9D

0

1

+ 1

Multiplier

SYNC

x4

x16

x64

PPS

1

x

1

0

1

0

RxyPPS⁽²⁾

BRGH

x

1

0

SPBRGH SPBRGL

SYNC

CSRC

BRG16

Note 1: In Synchronous mode, the DT output and RX input PPS

selections should enable the same pin.

2: In Master Synchronous mode the TX output and CK input

PPS selections should enable the same pin.

DS40002002B-page 412

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

Figure 28-2.ꢀEUSART Receive Block Diagram

Rev. 10-000 114B

2/15/201 7

CREN

OERR

RCIDL

SPEN

RXPPS⁽¹⁾

PPS

RSR Register

MSb

LSb

RXx/DTx pin

Pin Buffer

and Control

Data

Recovery

Stop (8)

7

1

0

Start

SYNC

CSRC

RX9

PPS

1

0

CKx Pin

CKPPS⁽²⁾

Baud Rate Generator

BRG16

FIFO

FOSC

÷ n

FERR

RX9D

RCREG Register

8

n

Data Bus

+ 1

Multiplier

x4

x16

x64

SYNC

BRGH

BRG16

1

x

1

0

1

0

1

0

RCxIF

RCxIE

Interrupt

SPBRGH SPBRGL

Note 1: In Synchronous mode, the DT output and RX input PPS

selections should enable the same pin.

2: In Master Synchronous mode the TX output and CK input

PPS selections should enable the same pin.

28.1

EUSART Asynchronous Mode

The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented

with two levels: a V_OHMark state which represents a ‘1’ data bit, and a V_OLSpace state which represents a ‘0’ data

bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit

without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state.

Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by

one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data

format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud

Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 28-2 for

examples of baud rate configurations.

The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be

implemented in software and stored as the ninth data bit.

28.1.1 EUSART Asynchronous Transmitter

Figure 28-1 is a simplified representation of the transmitter. The heart of the transmitter is the serial Transmit Shift

Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which

is the TXxREG register.

28.1.1.1 Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits:

•

TXEN bit in the TXxSTA register is set to ‘1’ to enable the transmitter circuitry of the EUSART

SYNC bit in the TXxSTA register is set to ‘0’ to configure the EUSART for asynchronous operation

SPEN bit in the RCxSTA register is set to ‘1’ to enable the EUSART interface and to enable automatically the

output drivers for the RxyPPS selected as the TXx/CKx output

DS40002002B-page 413

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

All other EUSART control bits are assumed to be in their default state.

If the TXx/CKx pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the

corresponding ANSEL bit.

Important:ꢀ The TXxIF Transmitter Interrupt flag in the PIR3 register is set when the TXEN enable bit in

the PIE3 register is set and the Transmit Shift register (TSR) is Idle.

28.1.1.2 Transmitting Data

A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous

character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR

register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until

the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred

to the TSR in one T_CYimmediately following the Stop bit transmission. The transmission of the Start bit, data bits and

Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG.

28.1.1.3 Transmit Data Polarity

The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of

this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the transmit data

resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In

Synchronous mode, the SCKP bit has a different function. See the 28.3.1.2 Clock Polarity section for more details.

28.1.1.4 Transmit Interrupt Flag

The TXxIF interrupt flag bit of the PIR3 register is set whenever the EUSART transmitter is enabled and no character

is being held for transmission in the TXxREG. In other words, the TXxIF bit is only cleared when the TSR is busy with

a character and a new character has been queued for transmission in the TXxREG. The TXxIF flag bit is not cleared

immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle following the write execution.

Polling TXxIF immediately following the TXxREG write will return invalid results. The TXxIF bit is read-only, it cannot

be set or cleared by software.

The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIE3 register. However, the TXxIF

flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE enable bit.

To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE

interrupt enable bit upon writing the last character of the transmission to the TXxREG.

28.1.1.5 TSR Status

The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is

set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the

TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied

to this bit, so the user needs to poll this bit to determine the TSR status.

Important:ꢀ The TSR register is not mapped in data memory, so it is not available to the user.

28.1.1.6 Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the EUSART

will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most

Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least

Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the

TXxREG is written.

A special 9-bit Address mode is available for use with multiple receivers. See the 28.1.2.7 Address Detection section

for more information on the Address mode.

DS40002002B-page 414

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.1.1.7 Asynchronous Transmission Setup

1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud

rate (see section 28.2 EUSART Baud Rate Generator (BRG)).

2. Select the transmit output pin by writing the appropriate value to the RxyPPS register.

3. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit.

4. If 9-bit transmission is desired, set the TX9 control bit in the TXxSTA register. That will indicate that the eight

Least Significant data bits are an address when the receiver is set for address detection.

5. Set SCKP bit if inverted transmit is desired.

6. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set.

7. If interrupts are desired, set the TXxIE interrupt enable bit of the PIE3 register.

8. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set.

9. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit.

10. Load 8-bit data into the TXxREG register. This will start the transmission.

Figure 28-3.ꢀAsynchronous Transmission

Rev. 10-000 115A

2/7/201 7

Word 1

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXxIF bit

(Transmit Buffer

Reg Empty Flag)

1 TCY

TRMT bit

(Transmit Shift

Reg Empty Flag)

Figure 28-4.ꢀAsynchronous Transmission (Back-to-Back)

Rev. 10-000 116A

2/7/201 7

Word 1

Word 2

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

Start bit

bit 0

Word 2

TXxIF bit

(Transmit Buffer

Reg Empty Flag)

1 TCY

TRMT bit

(Transmit Shift

Reg Empty Flag)

28.1.2 EUSART Asynchronous Receiver

The Asynchronous mode is typically used in RS-232 systems. A simplified representation of the receiver is shown in

the Figure 28-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery

block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register

(RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately

transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete

characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and

RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register.

DS40002002B-page 415

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.1.2.1 Enabling the Receiver

The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits:

•

CREN bit in the RCxSTA register is set to ‘1’ to enables the receiver circuitry of the EUSART

SYNC bit in the TXxSTA register is set to ‘0’ to configure the EUSART for asynchronous operation

SPEN bit in the RCxSTA register is set to ‘1’ to enable the EUSART interface

All other EUSART control bits are assumed to be in their default state.

The user must set the RXxPPS register to select the RXx/DTx I/O pin and set the corresponding TRIS bit to configure

the pin as an input.

Important:ꢀ If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for

the receiver to function.

28.1.2.2 Receiving Data

The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also

known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit

and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception,

without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification

succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a

majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been

sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is

always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this character. See the 28.1.2.4 Receive Framing Error section

for more information on framing errors.

Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the

EUSART receive FIFO and the RCxIF interrupt flag bit of the PIR3 register is set. The top character in the FIFO is

transferred out of the FIFO by reading the RCxREG register.

Important:ꢀ If the receive FIFO is overrun, no additional characters will be received until the overrun

condition is cleared. See the 28.1.2.5 Receive Overrun Error section for more information.

28.1.2.3 Receive Interrupts

The RCxIF interrupt flag bit of the PIR3 register is set whenever the EUSART receiver is enabled and there is an

unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by

software.

RCxIF interrupts are enabled by setting all of the following bits:

•

RCxIE, Interrupt Enable bit of the PIE3 register

PEIE, Peripheral Interrupt Enable bit of the INTCON register

GIE, Global Interrupt Enable bit of the INTCON register

The RCxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of

interrupt enable bits.

28.1.2.4 Receive Framing Error

Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that

a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA

register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit

must be read before reading the RCxREG.

DS40002002B-page 416

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR =

1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next

character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART.

Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not

generate an interrupt.

Important:ꢀ If all receive characters in the receive FIFO have framing errors, repeated reads of the

RCxREG will not clear the FERR bit.

28.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety,

is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The

characters already in the FIFO buffer can be read but no additional characters will be received until the error is

cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the

EUSART by clearing the SPEN bit of the RCxSTA register.

28.1.2.6 Receiving 9-Bit Characters

The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will

shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most

Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO

buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG.

28.1.2.7 Address Detection

A special Address Detection mode is available for use when multiple receivers share the same transmission line,

such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register.

Address detection requires 9-bit character reception. When address detection is enabled, only characters with the

ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt bit. All other

characters will be ignored.

Upon receiving an address character, user software determines if the address matches its own. Upon address match,

user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user

software detects the end of the message, determined by the message protocol used, software places the receiver

back into the Address Detection mode by setting the ADDEN bit.

28.1.2.8 Asynchronous Reception Setup

1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud

rate (see the 28.2 EUSART Baud Rate Generator (BRG) section).

2. Set the RXxPPS register to select the RXx/DTx input pin.

3. Clear the ANSEL bit for the RXx pin (if applicable).

4. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation.

5. If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON

register.

6. If 9-bit reception is desired, set the RX9 bit.

7. Enable reception by setting the CREN bit.

8. The RCxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An

interrupt will be generated if the RCxIE interrupt enable bit was also set.

9. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit.

10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register.

11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.

28.1.2.9 9-Bit Address Detection Mode Setup

This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect

Enable follow these steps:

DS40002002B-page 417

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud

rate (see the 28.2 EUSART Baud Rate Generator (BRG) section).

2. Set the RXxPPS register to select the RXx input pin.

3. Clear the ANSEL bit for the RXx pin (if applicable).

4. Enable the serial port by setting the SPEN bit. The SYNC bit must be cleared for asynchronous operation.

5. If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON

register.

6. Enable 9-bit reception by setting the RX9 bit.

7. Enable address detection by setting the ADDEN bit.

8. Enable reception by setting the CREN bit.

9. The RCxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to

the receive buffer. An interrupt will be generated if the RCxIE Interrupt Enable bit is also set.

10. Read the RCxSTA register to get the error flags. The ninth data bit will always be set.

11. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register.

Software determines if this is the device’s address.

12. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.

13. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and

generate interrupts.

Figure 28-5.ꢀAsynchronous Reception

Rev. 10-000 117A

2/8/201 7

Start

bit

Start

bit

Start

bit

Stop

bit

Stop

bit

Stop

bit

RXx/DTx

bit 0

Word 1

bit 7/8

bit 0

Word 2

bit 7/8

bit 0

Word 3

bit 7/8

Rcv Shift Reg

Rcv Buffer Reg

Word 1

Word 2

RCxREG

RCIDL

Read

RCxREG

RCxIF

(Interrupt flag)

OERR Flag

CREN

(software clear)

Note: This timing diagram shows three bytes appearing on the RXx input. The OERR flag is set because the

RCxREG is not read before the third word is received.

28.1.3 Clock Accuracy with Asynchronous Operation

The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as

V_DDor temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to

adjust the baud rate clock, but both require a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the

OSCTUNE register allows for fine resolution changes to the system clock source.

The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud

Detect feature (see 28.2.1 Auto-Baud Detect). There may not be fine enough resolution when adjusting the Baud

Rate Generator to compensate for a gradual change in the peripheral clock frequency.

DS40002002B-page 418

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.2

EUSART Baud Rate Generator (BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous

and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the

BAUDxCON register selects 16-bit mode.

The SPxBRGH, SPxBRGL register pair determines the period of the free-running baud rate timer. In Asynchronous

mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the

BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored.

Table 28-1 contains the formulas for determining the baud rate. Equation 28-1 provides a sample calculation for

determining the baud rate and baud rate error.

Typical baud rates and error values for various asynchronous modes have been computed and are shown in Table

28-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the

baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. The BRGH

bit is used to achieve very high baud rates.

Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow before outputting the new baud rate.

If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid

this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the

system clock.

Equation 28-1.ꢀCalculating Baud Rate Error

For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

ꢢ

ꢊꢋꢌ

ꢙꢃꢍꢅꢄꢃꢇꢟꢏꢒꢇꢄꢏꢓꢃ =

64 × ꢋꢀꢔꢟꢉꢣ + 1

Solving for SPxBRG:

ꢢ

ꢊꢋꢌ

ꢋꢀꢔꢟꢉꢣ =

− 1

64 × ꢙꢃꢍꢅꢄꢃꢇꢟꢏꢒꢇꢄꢏꢓꢃ

16000000

− 1

ꢋꢀꢔꢟꢉꢣ =

64 × 9600

ꢋꢀꢔꢟꢉꢣ = 25.042 ≃ 25

ꢌꢏꢐꢎꢒꢐꢏꢓꢃꢇꢟꢏꢒꢇꢄꢏꢓꢃ =

16000000

64 × 25 + 1

ꢌꢏꢐꢎꢒꢐꢏꢓꢃꢇꢟꢏꢒꢇꢄꢏꢓꢃ = 9615

ꢌꢏꢐꢎꢒꢐꢏꢓꢃꢇꢟꢏꢒꢇꢄꢏꢓꢃ − ꢙꢃꢍꢅꢄꢃꢇꢟꢏꢒꢇꢄꢏꢓꢃ

ꢝꢄꢄꢆꢄ =

ꢙꢃꢍꢅꢄꢃꢇꢟꢏꢒꢇꢄꢏꢓꢃ

9615 − 9600

9600

ꢝꢄꢄꢆꢄ = 0.16 %

Table 28-1.ꢀBaud Rate Formulas

Configuration Bits

BRG/EUSART Mode

Baud Rate Formula

F_OSC/[64 (n+1)]

SYNC

BRG16

BRGH

0

1

0

1

0

8-bit/Asynchronous

16-bit/Asynchronous

F_OSC/[16 (n+1)]

DS40002002B-page 419

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

...........continued

Configuration Bits

BRG/EUSART Mode

Baud Rate Formula

SYNC

BRG16

BRGH

0

1

0

1

x

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

F_OSC/[4 (n+1)]

Note: x = Don’t care, n = value of SPxBRGH:SPxBRGL register pair.

Table 28-2.ꢀSample Baud Rates for Asynchronous Modes

SYNC = 0, BRGH = 0, BRG16 = 0

F_OSC= 20.000 MHz F_OSC= 18.432 MHz

SPBRG Actual SPBRG Actual

F_OSC= 32.000 MHz

F_OSC= 11.0592 MHz

BAUD

RATE

Actual

%

SPBRG Actual

%

SPBRG

value

Rate Error

value

Rate Error

value

Rate Error

value

Rate Error

(decimal)

300

—

239

119

29

27

14

7

—

143

71

17

16

8

1200

2400

9600

1221 1.73

2404 0.16

9470 -1.36

10417 0.00

19.53k 1.73

255

129

32

1200 0.00

2400 0.00

9600 0.00

10286 -1.26

19.20k 0.00

57.60k 0.00

1200 0.00

2400 0.00

9600 0.00

10165 -2.42

19.20k 0.00

57.60k 0.00

2404 0.16

9615 0.16

207

51

47

25

3

10417 10417 0.00

19.2k 19.23k 0.16

57.6k 55.55k -3.55

29

15

—

2

115.2k

—

SYNC = 0, BRGH = 0, BRG16 = 0

Fosc = 4.000 MHz Fosc = 3.6864 MHz

SPBRG Actual SPBRG Actual SPBRG Actual

Fosc = 8.000 MHz

Actual

Fosc = 1.000 MHz

BAUD

RATE

%

SPBRG

Rate Error

value

Rate Error

value

Rate Error

value

Rate Error

value

(decimal)

300

—

103

51

12

11

300

0.16

207

51

25

—

5

300

0.00

191

47

23

5

300

0.16

51

12

—

1200

2400

9600

1202 0.16

2404 0.16

9615 0.16

1202 0.16

2404 0.16

1200 0.00

2400 0.00

9600 0.00

1202 0.16

—

10417 10417 0.00

10417 0.00

—

2

19.2k

57.6k

115.2k

—

19.20k 0.00

57.60k 0.00

—

0

—

DS40002002B-page 420

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

SYNC = 0, BRGH = 1, BRG16 = 0

Fosc = 32.000 MHz

Fosc = 20.000 MHz

Fosc = 18.432 MHz

Fosc = 11.0592 MHz

BAUD

RATE

Actual

%

SPBRG Actual

%

SPBRG Actual

%

SPBRG Actual

%

SPBRG

value

Rate

Error

value

Rate

Error

value

Rate Error

value

Rate Error

(decimal)

300

—

71

65

35

11

5

1200

2400

9600

—

9615

0.16

207

191

103

34

9615

0.16

129

119

64

9600 0.00

10378 -0.37

19.20k 0.00

57.60k 0.00

115.2k 0.00

119

110

59

19

9

9600 0.00

10473 0.53

19.20k 0.00

57.60k 0.00

115.2k 0.00

10417 10417 0.00

19.2k 19.23k 0.16

57.6k 57.14k -0.79

115.2k 117.64k 2.12

10417 0.00

19.23k 0.16

56.82k -1.36

113.64k -1.36

21

16

10

SYNC = 0, BRGH = 1, BRG16 = 0

Fosc = 4.000 MHz Fosc = 3.6864 MHz

SPBRG Actual SPBRG Actual SPBRG Actual

Fosc = 8.000 MHz

Actual

Fosc = 1.000 MHz

BAUD

RATE

%

SPBRG

value

Rate Error

value

Rate Error

value

Rate Error

value

Rate Error

(decimal)

300

—

207

103

25

—

191

95

23

21

11

3

300

0.16

207

51

25

—

5

1200

2400

9600

1202 0.16

2404 0.16

9615 0.16

10417 0.00

19.23k 0.16

1200 0.00

2400 0.00

9600 0.00

10473 0.53

19.2k 0.00

57.60k 0.00

115.2k 0.00

1202 0.16

2404 0.16

9615 0.16

207

51

47

25

8

—

10417 10417 0.00

19.2k 19231 0.16

57.6k 55556 -3.55

23

10417 0.00

12

—

115.2k

—

1

SYNC = 0, BRGH = 0, BRG16 = 1

Fosc = 20.000 MHz Fosc = 18.432 MHz

SPBRG Actual SPBRG Actual

Fosc = 32.000 MHz

Fosc = 11.0592 MHz

BAUD

RATE

Actual

%

SPBRG

value

Actual

Rate

%

SPBRG

value

Rate Error

Error

value

Rate Error

value

Rate Error

(decimal)

300

300.0 0.00

1200 -0.02

2401 -0.04

9615 0.16

6666

3332

832

300.0 -0.01

1200 -0.03

2399 -0.03

4166

1041

520

129

119

64

300.0 0.00

1200 0.00

2400 0.00

9600 0.00

10378 -0.37

19.20k 0.00

3839

959

479

119

110

59

300.0 0.00

1200 0.00

2400 0.00

9600 0.00

10473 0.53

19.20k 0.00

2303

575

287

71

1200

2400

9600

207

9615

0.16

10417 10417 0.00

19.2k 19.23k 0.16

191

10417 0.00

19.23k 0.16

65

103

35

DS40002002B-page 421

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

57.6k 57.14k -0.79

115.2k 117.6k 2.12

34

16

56.818 -1.36

113.636 -1.36

21

10

57.60k 0.00

115.2k 0.00

19

9

57.60k 0.00

115.2k 0.00

11

5

SYNC = 0, BRGH = 0, BRG16 = 1

Fosc = 4.000 MHz Fosc = 3.6864 MHz

Fosc = 8.000 MHz

Fosc = 1.000 MHz

BAUD

RATE

Actual

%

SPBRG Actual

%

SPBRG Actual

%

SPBRG Actual

%

SPBRG

Rate Error

value

Rate Error

value

Rate Error

value

Rate Error

value

(decimal)

300

299.9 -0.02

1199 -0.08

2404 0.16

9615 0.16

1666

416

207

51

300.1 0.04

1202 0.16

2404 0.16

9615 0.16

10417 0.00

19.23k 0.16

832

207

103

25

300.0 0.00

1200 0.00

2400 0.00

9600 0.00

10473 0.53

19.20k 0.00

57.60k 0.00

115.2k 0.00

767

191

95

23

21

11

3

300.5 0.16

1202 0.16

2404 0.16

207

51

25

—

5

1200

2400

9600

—

10417 10417 0.00

19.2k 19.23k 0.16

57.6k 55556 -3.55

47

23

10417 0.00

25

12

—

8

—

115.2k

—

1

SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1

Fosc = 20.000 MHz Fosc = 18.432 MHz

Fosc = 32.000 MHz

Fosc = 11.0592 MHz

BAUD

RATE

Actual

%

SPBRG Actual

%

SPBRG Actual

%

SPBRG Actual

%

SPBRG

value

Rate Error

value

Rate Error

value

Rate Error

value

Rate Error

(decimal)

300

300.0 0.00

1200 0.00

2400 0.01

9604 0.04

26666

6666

3332

832

300.0 0.00

1200 -0.01

2400 0.02

9597 -0.03

10417 0.00

19.23k 0.16

57.47k -0.22

116.3k 0.94

16665

4166

2082

520

479

259

86

300.0 0.00

1200 0.00

2400 0.00

9600 0.00

10425 0.08

19.20k 0.00

57.60k 0.00

115.2k 0.00

15359

3839

1919

479

441

239

79

300.0 0.00

1200 0.00

2400 0.00

9600 0.00

10433 0.16

19.20k 0.00

57.60k 0.00

115.2k 0.00

9215

2303

1151

287

264

143

47

1200

2400

9600

10417 10417 0.00

19.2k 19.18k -0.08

57.6k 57.55k -0.08

115.2k 115.9k 0.64

767

416

138

68

42

39

23

SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1

Fosc = 4.000 MHz Fosc = 3.6864 MHz

Fosc = 8.000 MHz

Actual SPBRG Actual

Fosc = 1.000 MHz

BAUD

RATE

%

SPBRG Actual

%

SPBRG Actual

%

SPBRG

value

Rate Error

value

Rate Error

value

Rate Error

value

Rate Error

(decimal)

300

1200

2400

300.0 0.00

1200 -0.02

2401 0.04

6666

1666

832

300.0 0.01

1200 0.04

2398 0.08

3332

832

300.0 0.00

1200 0.00

2400 0.00

3071

767

300.1 0.04

1202 0.16

2404 0.16

832

207

103

416

383

DS40002002B-page 422

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

9600

9615 0.16

207

191

103

34

9615 0.16

10417 0.00

19.23k 0.16

58.82k 2.12

111.1k -3.55

103

95

51

16

8

9600 0.00

10473 0.53

19.20k 0.00

57.60k 0.00

115.2k 0.00

95

87

47

15

7

9615 0.16

10417 0.00

19.23k 0.16

25

23

12

—

10417 10417

0

19.2k 19.23k 0.16

57.6k 57.14k -0.79

115.2k 117.6k 2.12

—

16

28.2.1 Auto-Baud Detect

The EUSART module supports automatic detection and calibration of the baud rate.

In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming

RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h

(ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising

edges including the Stop bit edge.

Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the ABD

sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the

Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 28-6. The fifth rising edge

will occur on the RXx pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper

BRG period is left in the SPxBRGH, SPxBRGL register pair, the ABDEN bit is automatically cleared and the RCxIF

interrupt flag is set. The value in the RCxREG needs to be read to clear the RCxIF interrupt. RCxREG content should

be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the

SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register.

The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 28-3. During ABD, both the

SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While

calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are clocked at 1/8^ththe BRG base clock rate.

The resulting byte measurement is the average bit time when clocked at full speed.

Note:ꢀ

1. If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break

character (see 28.2.3 Auto-Wake-up on Break).

2. It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG

clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible.

3. During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-

baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair.

Table 28-3.ꢀBRG Counter Clock Rates

BRG16

BRGH

BRG Base Clock

F_OSC/4

BRG ABD Clock

F_OSC/32

1

0

1

0

1

0

F_OSC/16

F_OSC/128

F_OSC/16

F_OSC/128

F_OSC/64

F_OSC/512

Note:ꢀ During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter,

independent of the BRG16 setting.

DS40002002B-page 423

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

Figure 28-6.ꢀAutomatic Baud Rate Calibration

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28.2.2 Auto-Baud Overflow

During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate

counter overflows before the fifth rising edge is detected on the RXx pin. The ABDOVF bit indicates that the counter

has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the

ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RXx pin. Upon

detecting the fifth RX edge, the hardware will set the RCxIF interrupt flag and clear the ABDEN bit of the BAUDxCON

register. The RCxIF flag can be subsequently cleared by reading the RCxREG register. The ABDOVF flag of the

BAUDxCON register can be cleared by software directly.

To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of

the BAUDxCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first.

28.2.3 Auto-Wake-up on Break

During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive

and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up

due to activity on the RX/DT line. This feature is available only in Asynchronous mode.

The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal

receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event

independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This

coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.)

The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated

synchronously to the Q clocks in normal CPU operating modes as shown in Figure 28-7, and asynchronously if the

device is in Sleep mode, as shown in Figure 28-8. The interrupt condition is cleared by reading the RCxREG register.

The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals

to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next

character.

28.2.3.1 Special Considerations

Break Character

To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros.

When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is

set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted

as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent

characters can result in framing or overrun errors.

DS40002002B-page 424

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13-bit times

recommended for LIN bus, or any number of bit times for standard RS-232 devices.

Oscillator Start-up Time

Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals

(i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be

followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper

initialization of the EUSART.

WUE Bit

The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared in hardware by a

rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and

discarding its contents.

To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before

setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the

Sleep mode.

Figure 28-7.ꢀAuto-Wake-up Bit (WUE) Timing During Normal Operation

Rev. 10-000 326A

2/13/201 7

q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4

FOSC

Bit set by user

Auto cleared

WUE bit

RXx/DTx

line

RCxIF

Cleared due to user read of RCxREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

Figure 28-8.ꢀAuto-Wake-up Bit (WUE) Timings During Sleep

Rev. 10-000 327A

2/13/201 7

q1 q2 q3 q4 q1 q2 q3 q4

q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4

q1

FOSC

Bit set by user

Auto cleared

WUE bit

RXx/DTx

line

RCxIF

Cleared due to user read of RCxREG

Sleep command executed

Sleep ends

Note 1: The EUSART remains in Idle while the WUE bit is set.

28.2.4 Break Character Sequence

The EUSART module has the capability of sending the special Break character sequences that are required by the

LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit.

To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission

is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all ‘0’s will be

transmitted.

DS40002002B-page 425

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EUSART - Enhanced Universal Synchronous Asyn...

The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to

preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in

the LIN specification).

The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it does during

normal transmission. See Figure 28-9 for more details.

28.2.4.1 Break and Sync Transmit Sequence

The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte.

This sequence is typical of a LIN bus master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the Break sequence.

3. Load the TXxREG with a dummy character to initiate transmission (the value is ignored).

4. Write ‘55h’ to TXxREG to load the Sync character into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted.

When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG.

28.2.5 Receiving a Break Character

The EUSART module can receive a Break character in two ways.

The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received data as

indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate.

A Break character has been received when all three of the following conditions are true:

•

RCxIF bit is set

FERR bit is set

RCxREG = 00h

The second method uses the Auto-Wake-up feature described in 28.2.3 Auto-Wake-up on Break. By enabling this

feature, the EUSART will sample the next two transitions on RX/DT, cause an RCxIF interrupt, and receive the next

data byte followed by another interrupt.

Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both

methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode.

Figure 28-9.ꢀSend Break Character Sequence

Dummy

Rev. 10-000 118A

2/13/201 7

Write

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

Start bit

bit 0

bit 1

Break

bit 11

Stop bit

TXxIF bit

(Transmit Buffer

Reg Empty Flag)

TRMT bit

(Transmit Shift

Reg Empty Flag)

SENDB

(send break

control bit)

Auto cleared

SENDB sampled here

DS40002002B-page 426

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.3

EUSART Synchronous Mode

Synchronous serial communications are typically used in systems with a single master and one or more slaves. The

master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the

system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry.

There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. The slaves use the

external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift

registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact

that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate

as either a master or slave device.

Start and Stop bits are not used in synchronous transmissions.

28.3.1 Synchronous Master Mode

The following bits are used to configure the EUSART for synchronous master operation:

•

SYNC bit in the TXxSTA register is set to ‘1’ to configure the EUSART for synchronous operation

CSRC bit in the TXxSTA register is set to ‘1’ to configure the EUSART as the master

SREN bit in the RCxSTA register is set to ‘0’ for transmit; SREN = 1for receive (recommended setting to receive

1 byte)

•

CREN bit in the RCxSTA register is set to ‘0’ for transmit; CREN = 1to receive continuously

SPEN bit in the RCxSTA register is set to ‘1’ to enable the EUSART interface

Important:ꢀ Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the

Transmit mode, otherwise the device will be configured to receive.

28.3.1.1 Master Clock

Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a

master transmits the clock on the TX/CK line. The TXx/CKx pin output driver is automatically enabled when the

EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to

ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many

clock cycles are generated as there are data bits.

28.3.1.2 Clock Polarity

A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the

BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data

changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is

cleared, the data changes on the rising edge of each clock.

28.3.1.3 Synchronous Master Transmission

Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers are

automatically enabled when the EUSART is configured for synchronous master transmit operation.

A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a

previous character the new character data is held in the TXxREG until the last bit of the previous character has been

transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data

in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately

following the transfer of the data to the TSR from the TXxREG.

Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock

edge.

Note:ꢀ The TSR register is not mapped in data memory, so it is not available to the user.

28.3.1.4 Synchronous Master Transmission Setup

1. Initialize the SPxBRGH, SPxBRGL register pair and the BRG16 bit to achieve the desired baud rate (see

section 28.2 EUSART Baud Rate Generator (BRG)).

DS40002002B-page 427

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EUSART - Enhanced Universal Synchronous Asyn...

2. Select the transmit output pin by writing the appropriate values to the RxyPPS register and RXxPPS register.

Both selections should enable the same pin.

3. Select the clock output pin by writing the appropriate values to the RxyPPS register and CKxPPS register.

Both selections should enable the same pin.

4. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC.

5. Disable Receive mode by clearing the SREN and CREN bits.

6. Enable Transmit mode by setting the TXEN bit.

7. If 9-bit transmission is desired, set the TX9 bit.

8. If interrupts are desired, set the TXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON

register.

9. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit.

10. Start transmission by loading data to the TXxREG register.

Figure 28-10.ꢀSynchronous Transmission

Rev. 10-000 115A

2/7/201 7

Word 1

Write to TXxREG

BRG Output

(Shift Clock)

TXx/CKx pin

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXxIF bit

(Transmit Buffer

Reg Empty Flag)

1 TCY

TRMT bit

(Transmit Shift

Reg Empty Flag)

28.3.1.5 Synchronous Master Reception

Data is received at the RXx/DTx pin. The RXx/DTx pin output driver is automatically disabled when the EUSART is

configured for synchronous master receive operation.

In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA

register) or the Continuous Receive Enable bit (CREN of the RCxSTA register).

When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single

character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are

continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops

immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the

completion of the first character and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge of the TX/CK

clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR,

the RCxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least

Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RCxIF bit remains set as

long as there are unread characters in the receive FIFO.

Note:ꢀ If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to

function.

28.3.1.6 Receive Overrun Error

The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety,

is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is

set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no

additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the

overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared

by reading RCxREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either

clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART.

DS40002002B-page 428

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.3.1.7 Receiving 9-Bit Characters

The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will

shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth, and Most

Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO

buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG.

28.3.1.8 Synchronous Master Reception Setup

1. Initialize the SPxBRGH:SPxBRGL register pair and set or clear the BRG16 bit, as required, to achieve the

desired baud rate.

2. Select the receive input pin by writing the appropriate values to the RxyPPS register and RXxPPS register.

Both selections should enable the same pin.

3. Select the clock output pin by writing the appropriate values to the RxyPPS register and CKxPPS register.

Both selections should enable the same pin.

4. Clear the ANSEL bit for the RXx pin (if applicable).

5. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC.

6. Ensure that CREN and SREN bits are cleared.

7. If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON

register.

8. If 9-bit reception is desired, set bit RX9.

9. Start reception by setting the SREN bit or for continuous reception, set the CREN bit.

10. Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be generated if

the enable bit RCxIE was set.

11. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.

12. Read the 8-bit received data by reading the RCxREG register.

13. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing

the SPEN bit which resets the EUSART.

Figure 28-11.ꢀSynchronous Reception (Master Mode, SREN)

Rev. 10-000 121A

2/13/201 7

RXx/DTx pin

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TXx/CKx pin

SCKP = 0

TXx/CKx pin

SCKP = 1

Write to SREN

SREN bit

CREN bit

‘0’

RCxIF

(Interrupt)

Read

RCxREG

28.3.2 Synchronous Slave Mode

The following bits are used to configure the EUSART for synchronous slave operation:

•

SYNC = 1(configures the EUSART for synchronous operation.)

CSRC = 0(configures the EUSART as a slave)

DS40002002B-page 429

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EUSART - Enhanced Universal Synchronous Asyn...

•

SREN = 0(for transmit); SREN = 1(for single byte receive)

CREN = 0(for transmit); CREN = 1(recommended setting for continuous receive)

SPEN = 1(enables the EUSART)

Important:ꢀ Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the

Transmit mode, otherwise the device will be configured to receive.

28.3.2.1 Slave Clock

Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a

slave receives the clock on the TX/CK line. The TXx/CKx pin output driver is automatically disabled when the device

is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to

ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many

clock cycles should be received as there are data bits.

Important:ꢀ If the device is configured as a slave and the TX/CK function is on an analog pin, the

corresponding ANSEL bit must be cleared.

28.3.2.2 EUSART Synchronous Slave Transmit

The operation of the Synchronous Master and Slave modes are identical (see 28.3.1.3 Synchronous Master

Transmission), except in the case of the Sleep mode.

If two words are written to the TXxREG and then the SLEEPinstruction is executed, the following will occur:

1. The first character will immediately transfer to the TSR register and transmit.

2. The second word will remain in the TXxREG register.

3. The TXxIF bit will not be set.

4. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to

the TSR and the TXxIF bit will now be set.

5. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next

instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.

28.3.2.3 Synchronous Slave Transmission Setup

1. Set the SYNC and SPEN bits and clear the CSRC bit.

2. Select the transmit output pin by writing the appropriate values to the RxyPPS register and RXxPPS register.

Both selections should enable the same pin.

3. Select the clock input pin by writing the appropriate value to the CKxPPS register.

4. Clear the ANSEL bit for the CKx pin (if applicable).

5. Clear the CREN and SREN bits.

6. If interrupts are desired, set the TXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON

register.

7. If 9-bit transmission is desired, set the TX9 bit.

8. Enable transmission by setting the TXEN bit.

9. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit.

10. Prepare for transmission by writing the Least Significant eight bits to the TXxREG register. The word will be

transmitted in response to the Master clocks at the CKx pin.

28.3.2.4 EUSART Synchronous Slave Reception

The operation of the Synchronous Master and Slave modes is identical (see 28.3.1.5 Synchronous Master

Reception), with the following exceptions:

•

Sleep

DS40002002B-page 430

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EUSART - Enhanced Universal Synchronous Asyn...

•

CREN bit is always set, therefore the receiver is never Idle

SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is

received, the RSR register will transfer the data to the RCxREG register. If the RCxIE enable bit is set, the interrupt

generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will

branch to the interrupt vector.

28.3.2.5 Synchronous Slave Reception Setup:

1. Set the SYNC and SPEN bits and clear the CSRC bit.

2. Select the receive input pin by writing the appropriate value to the RXxPPS register.

3. Select the clock input pin by writing the appropriate values to the CKxPPS register.

4. Clear the ANSEL bit for both the TXx/CKx and RXx/DTx pins (if applicable).

5. If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON

register.

6. If 9-bit reception is desired, set the RX9 bit.

7. Set the CREN bit to enable reception.

8. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set.

9. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register.

10. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register.

11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing

the SPEN bit which resets the EUSART.

28.4

EUSART Operation During Sleep

The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers

during Sleep.

Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers.

28.4.1 Synchronous Receive During Sleep

To receive during Sleep, all the following conditions must be met before entering Sleep mode:

•

RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see 28.3.2.5

Synchronous Slave Reception Setup:).

If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON

register.

The RCxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive

buffer.

Upon entering Sleep mode, the device will be ready to accept data and clocks on the RXx/DTx and TXx/CKx pins,

respectively. When the data word has been completely clocked in by the external device, the RCxIF interrupt flag bit

of the PIR3 register will be set. Thereby, waking the processor from Sleep.

Upon waking from Sleep, the instruction following the SLEEPinstruction will be executed. If the Global Interrupt

Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 0x0004 will be

called.

28.4.2 Synchronous Transmit During Sleep

To transmit during Sleep, all the following conditions must be met before entering Sleep mode:

•

The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission (see

28.3.2.3 Synchronous Slave Transmission Setup).

The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and

transmit buffer.

The TXxIE interrupt enable bits of the PIE3 register and PEIE of the INTCON register must be written to ‘1’.

DS40002002B-page 431

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

•

If interrupts are desired, set the GIE bit of the INTCON register.

Upon entering Sleep mode, the device will be ready to accept clocks on the TXx/CKx pin and transmit data on the

RXx/DTx pin. When the data word in the TSR register has been completely clocked out by the external device, the

pending byte in the TXxREG will transfer to the TSR and the TXxIF flag will be set. Thereby, waking the processor

from Sleep. At this point, the TXxREG is available to accept another character for transmission. Writing TXxREG will

clear the TXxIF flag.

Upon waking from Sleep, the instruction following the SLEEPinstruction will be executed. If the Global Interrupt

Enable (GIE) bit is also set then the Interrupt Service Routine at address 0x0004 will be called.

DS40002002B-page 432

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.5

Register Summary - EUSART

Offset

Name

Bit Pos.

0x00

...

Reserved

0x0118

0x0119

0x011A

RC1REG

TX1REG

7:0

15:8

7:0

RCREG[7:0]

TXREG[7:0]

SPBRG[7:0]

SPBRG[15:8]

0x011B

SP1BRG

0x011D

0x011E

0x011F

RC1STA

TX1STA

SPEN

CSRC

RX9

TX9

SREN

TXEN

CREN

SYNC

SCKP

ADDEN

SENDB

BRG16

FERR

BRGH

OERR

TRMT

WUE

RX9D

TX9D

BAUD1CON

ABDOVF

RCIDL

ABDEN

28.6

Register Definitions: EUSART Control

DS40002002B-page 433

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.6.1 RCxREG

Name:ꢀ

Offset:ꢀ

RCxREG

0x0119

Receive Data Register

Bit

7

6

5

4

3

2

1

0

RCREG[7:0]

Access

Reset

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

Bits 7:0 – RCREG[7:0]ꢀReceive data

DS40002002B-page 434

Datasheet

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EUSART - Enhanced Universal Synchronous Asyn...

28.6.2 TXxREG

Name:ꢀ

Offset:ꢀ

TXxREG

0x011A

Transmit Data Register

Bit

7

6

5

4

3

2

1

0

TXREG[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – TXREG[7:0]ꢀTransmit Data

DS40002002B-page 435

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.6.3 SPxBRG

Name:ꢀ

Offset:ꢀ

SPxBRG

0x011B

UART BAUD Rate Generator

Bit

15

14

13

12

11

10

9

8

SPBRG[15:8]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

SPBRG[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 15:0 – SPBRG[15:0]ꢀBaud Rate Register

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

SPxBRGH: Accesses the high byte SPBRG[15:8]

SPxBRGL: Accesses the low byte SPBRG[7:0]

DS40002002B-page 436

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.6.4 RCxSTA

Name:ꢀ

Offset:ꢀ

RCxSTA

0x011D

Receive Status and Control Register

Bit

7

SPEN

R/W

0

6

5

SREN

R/W

0

4

CREN

R/W

0

3

ADDEN

R/W

0

2

FERR

RO

0

1

0

RX9

R/W

0

OERR

R/HC

0

RX9D

R/HC

0

Access

Reset

Bit 7 – SPENꢀSerial Port Enable bit

Value

Description

1

Serial port enabled

0

Serial port disabled (held in Reset)

Bit 6 – RX9ꢀ9-Bit Receive Enable bit

Value

Description

1

0

Selects 9-bit reception

Selects 8-bit reception

Bit 5 – SRENꢀSingle Receive Enable bit

Controls reception. This bit is cleared by hardware when reception is complete

Value

Condition

Description

1

0

X

SYNC = 1AND CSRC = 1

SYNC = 0OR CSRC = 0

Start single receive

Single receive is complete

Don’t care

Bit 4 – CRENꢀContinuous Receive Enable bit

Value

Condition Description

1

SYNC = 1 Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0

1

0

SYNC = 1 Disables continuous receive

SYNC = 0 Enables receiver

SYNC = 0 Disables receiver

Bit 3 – ADDENꢀAddress Detect Enable bit

Value

Condition

Description

1

SYNC = 0AND RX9 = 1 The receive buffer is loaded and the interrupt occurs only when the ninth

received bit is set

0

X

SYNC = 0AND RX9 = 1 All bytes are received and interrupt always occurs. Ninth bit can be used as

parity bit

RX9 = 0OR SYNC = 1 Don't care

Bit 2 – FERRꢀFraming Error bit

Value

Description

1

0

Unread byte in 28.6.1 RCxREG has a framing error

Unread byte in 28.6.1 RCxREG does not have a framing error

Bit 1 – OERRꢀOverrun Error bit

Value

Description

1

0

Overrun error (can be cleared by clearing either SPEN or CREN bit)

No overrun error

Bit 0 – RX9DꢀNinth bit of Received Data

This can be address/data bit or a parity bit which is determined by user firmware.

DS40002002B-page 437

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.6.5 TXxSTA

Name:ꢀ

Offset:ꢀ

TXxSTA

0x011E

Transmit Status and Control Register

Bit

7

CSRC

R/W

0

6

5

TXEN

R/W

0

4

SYNC

R/W

0

3

SENDB

R/W

0

2

BRGH

R/W

0

1

TRMT

RO

1

0

TX9D

R/W

0

TX9

R/W

0

Access

Reset

Bit 7 – CSRCꢀClock Source Select bit

Value

1

0

X

Condition

SYNC = 1

SYNC = 0

Description

Master mode (clock generated internally from BRG)

Slave mode (clock from external source)

Don’t care

Bit 6 – TX9ꢀ9-bit Transmit Enable bit

Value

Description

1

0

Selects 9-bit transmission

Selects 8-bit transmission

Bit 5 – TXENꢀTransmit Enable bit

Enables transmitter⁽¹⁾

Value

Description

1

0

Transmit enabled

Transmit disabled

Bit 4 – SYNCꢀEUSART Mode Select bit

Value

Description

1

0

Synchronous mode

Asynchronous mode

Bit 3 – SENDBꢀSend Break Character bit

Value

Condition Description

1

0

X

SYNC = 0

SYNC = 1

Send Sync Break on next transmission (cleared by hardware upon completion)

Sync Break transmission disabled or completed

Don’t care

Bit 2 – BRGHꢀHigh Baud Rate Select bit

Value

1

0

X

Condition

SYNC = 0

SYNC = 1

Description

High speed, if BRG16 = 1, baud rate is baudclk/4; else baudclk/16

Low speed

Don’t care

Bit 1 – TRMTꢀTransmit Shift Register (TSR) Status bit

Value

Description

1

0

TSR is empty

TSR is not empty

Bit 0 – TX9DꢀNinth bit of Transmit Data

Can be address/data bit or a parity bit.

DS40002002B-page 438

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

Note:ꢀ

1. SREN and CREN bits override TXEN in Sync mode.

DS40002002B-page 439

Datasheet

PIC16(L)F18425/45

EUSART - Enhanced Universal Synchronous Asyn...

28.6.6 BAUDxCON

Name:ꢀ

Offset:ꢀ

BAUDxCON

0x011F

Baud Rate Control Register

Bit

7

ABDOVF

RO

6

RCIDL

RO

5

4

SCKP

RW

0

3

BRG16

RW

2

1

WUE

RW

0

ABDEN

RW

Access

Reset

0

Bit 7 – ABDOVFꢀAuto-Baud Detect Overflow bit

Value

1

0

X

Condition

SYNC = 0

SYNC = 1

Description

Auto-baud timer overflowed

Auto-baud timer did not overflow

Don’t care

Bit 6 – RCIDLꢀReceive Idle Flag bit

Value

1

0

X

Condition

SYNC = 0

SYNC = 1

Description

Receiver is Idle

Start bit has been received and the receiver is receiving

Don’t care

Bit 4 – SCKPꢀSynchronous Clock Polarity Select bit

Value

1

0

1

0

Condition

SYNC = 0

SYNC = 1

Description

Idle state for transmit (TX) is a low level (transmit data inverted)

Idle state for transmit (TX) is a high level (transmit data is non-inverted)

Data is clocked on rising edge of the clock

Data is clocked on falling edge of the clock

Bit 3 – BRG16ꢀ16-bit Baud Rate Generator Select bit

Value

Description

1

0

16-bit Baud Rate Generator is used

8-bit Baud Rate Generator is used

Bit 1 – WUEꢀWake-up Enable bit

Value

Condition Description

1

SYNC = 0 Receiver is waiting for a falling edge. Upon falling edge no character will be received and

flag RCxIF will be set. WUE will automatically clear after RCxIF is set.

SYNC = 0 Receiver is operating normally

0

X

SYNC = 1 Don’t care

Bit 0 – ABDENꢀAuto-Baud Detect Enable bit

Value

1

0

X

Condition

SYNC = 0

SYNC = 1

Description

Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

Auto-Baud Detect is complete or mode is disabled

Don’t care

DS40002002B-page 440

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

29.

MSSP - Master Synchronous Serial Port Module

The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, Shift registers, display

drivers, A/D converters, etc. The MSSP module can operate in one of two modes:

•

Serial Peripheral Interface (SPI)

Inter-Integrated Circuit (I²C)

The SPI interface can operate in Master or Slave mode and supports the following features:

•

Selectable Clock Parity

Slave Select Synchronization (Slave Mode Only)

Daisy-Chain Connection of Slave Devices

The I²C interface can operate in Master or Slave mode and supports the following modes and features:

•

Byte NACKing (Slave Mode)

Limited Multi-Master Support

7-Bit and 10-Bit Addressing

Start and Stop Interrupts

Interrupt Masking

Clock Stretching

Bus Collision Detection

General Call Address Matching

Address Masking

Address Hold and Data Hold Modes

Selectable SDA Hold Times

29.1

SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-

Duplex mode. Devices communicate in a master/slave environment where the master device initiates the

communication. A slave device is controlled through a Chip Select known as Slave Select.

The SPI bus specifies four signal connections:

•

Serial Clock (SCK)

Serial Data Out (SDO)

Serial Data In (SDI)

Slave Select (SS)

Figure 29-1 shows the block diagram of the MSSP module when operating in SPI mode.

DS40002002B-page 441

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Figure 29-1.ꢀMSSP Block Diagram (SPI mode)

Rev. 30-000011A

3/31/2017

Data Bus

Read

Write

SSPxBUF Reg

SSPSR Reg

SSPxDATPPS

SDI

PPS

Shift

Clock

bit 0

SDO

PPS

RxyPPS

SS

Control

Enable

SS

2 (CKP, CKE)

Clock Select

PPS

Edge

Select

SSPxSSPPS

SSPxCLKPPS⁽²⁾

PPS

SSPM<3:0>

4

T2_match

SCK

(

)

2

TOSC

Prescaler

4, 16, 64

Edge

Select

PPS

RxyPPS⁽¹⁾

Baud Rate

Generator

(SSPxADD)

TRIS bit

Note 1: Output selection for Master mode

2: Input selection for Slave and Master mode

The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are

used, an independent Slave Select connection is required from the master device to each slave device.

Figure 29-2 shows a typical connection between a master device and multiple slave devices.

The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears

disconnected from the bus when they are not selected.

DS40002002B-page 442

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Figure 29-2.ꢀSPI Master and Multiple Slave Connection

Rev. 30-000012A

3/31/2017

SCK

SDO

SCK

SDI

SDO

SS

SPI Master

SPI Slave

#1

SDI

General I/O

SCK

SDI

SDO

SS

SPI Slave

#2

SCK

SDI

SDO

SS

SPI Slave

#3

29.1.1 SPI Mode Registers

The MSSP module has five registers for SPI mode operation. These are:

•

MSSP STATUS register (SSPxSTAT)

MSSP Control register 1 (SSPxCON1)

MSSP Control register 3 (SSPxCON3)

MSSP Data Buffer register (SSPxBUF)

MSSP Address register (SSPxADD)

MSSP Shift register (SSPSR)

(Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and STATUS registers for SPI mode operation. The SSPxCON1 register

is readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are

read/write.

One of the five SPI Master modes uses the SSPxADD value to determine the Baud Rate Generator clock frequency.

More information on the Baud Rate Generator is available in 29.7 Baud Rate Generator.

SSPSR is the Shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR

register. SSPxBUF is the Buffer register to which data bytes are written, and from which data bytes are read.

In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete

byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR.

29.2

SPI Mode Operation

Transmissions involve two Shift registers, eight bits in size, one in the master and one in the slave. With either the

master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out

first. At the same time, a new Least Significant bit (LSb) is shifted into the same register.

The following figure shows a typical connection between two processors configured as master and slave devices.

DS40002002B-page 443

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Figure 29-3.ꢀSPI Master/Slave Connection

Rev/ 30-000013A

3/31/2017

SPI Slave SSPM[3:0] =

SPI Master SSPM[3:0] =

010x

00xx

= 1010

SDO

SDI

Serial Input Buffer

(BUF)

Serial Input Buffer

(SSPxBUF)

SDO

SDI

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

Serial Clock

SCK

Slave Select

SS

General I/O

(optional)

Processor 2

Processor 1

Data is shifted out of both Shift registers on the programmed clock edge and latched on the opposite edge of the

clock.

The master device transmits information out on its SDO output pin, which is connected to and received by the slave’s

SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to and received

by the master’s SDI input pin.

To begin communication the master device first sends out the clock signal. Both the master and the slave devices

should be configured for the same clock polarity.

The master device starts a transmission by sending out the MSb from its Shift register. The slave device reads this bit

from that same line and saves it into the LSb position of its Shift register.

During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is

sending out the MSb from its Shift register (on its SDO pin) and the slave device is reading this bit and saving it as

the LSb of its Shift register, the slave device is also sending out the MSb from its Shift register (on its SDO pin) and

the master device is reading this bit and saving it as the LSb of its Shift register.

After eight bits have been shifted out, the master and slave have exchanged register values.

If there is more data to exchange, the Shift registers are loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three

scenarios for data transmission:

•

Master sends useful data and slave sends dummy data.

Master sends useful data and slave sends useful data.

Master sends dummy data and slave sends useful data.

Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master

stops sending the clock signal and it deselects the slave.

Every slave device connected to the bus that has not been selected through its slave select line must disregard the

clock and transmission signals and must not transmit out any data of its own.

When initializing the SPI several options need to be specified. This is done by programming the appropriate control

bits (SSPxCON1[5:0] and SSPxSTAT[7:6]). These control bits allow the following to be specified:

•

Master mode (SCK is the clock output)

Slave mode (SCK is the clock input)

Clock Polarity (Idle state of SCK)

DS40002002B-page 444

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

•

Data Input Sample Phase (middle or end of data output time)

Clock Edge (output data on rising/falling edge of SCK)

Clock Rate (Master mode only)

Slave Select mode (Slave mode only)

To enable the serial port the SSP Enable bit, SSPEN, must be set. To reset or reconfigure SPI mode, clear the

SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. The SDI, SDO, SCK and SS serial port

pins are selected with the PPS controls. For the pins to behave as the serial port function, some must have their data

direction bits (in the TRIS register) appropriately programmed as follows:

•

SDI must have corresponding TRIS bit set

SDO must have corresponding TRIS bit cleared

SCK (Master mode) must have corresponding TRIS bit cleared

SCK (Slave mode) must have corresponding TRIS bit set

The RxyPPS and SSPxCLKPPS controls must select the same pin

SS must have corresponding TRIS bit set

Any serial port function that is not desired may be overridden by programming the corresponding data direction

(TRIS) register to the opposite value.

The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts

the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the

received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register.

Then, the Buffer Full Detect bit, BF, and the Interrupt Flag bit, SSPxIF, are set. This double-buffering of the received

data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to

the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL,

will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to

complete successfully.

When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte

of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF, indicates when SSPxBUF has been loaded with

the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be

irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/

reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure

that a write collision does not occur.

The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register.

Additionally, the SSPxSTAT register indicates the various Status conditions.

29.2.1 SPI Master Mode

The master can initiate the data transfer at any time because it controls the SCK line. The master determines when

the slave (Processor 2, Figure 29-3) is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only

going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to

shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into

the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set).

The clock polarity is selected by appropriately programming the CKP bit and the CKE bit. This then, would give

waveforms for SPI communication as shown in Figure 29-4, Figure 29-6, Figure 29-7 and Figure 29-8, where the

MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following:

•

F_OSC/4 (or T_CY

)

F_OSC/16 (or 4 * T_CY

)

F_OSC/64 (or 16 * T_CY

Timer2 output/2

)

F_OSC/(4 * (SSPxADD + 1))

Figure 29-4 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample

is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown.

DS40002002B-page 445

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Important:ꢀ In Master mode the clock signal output to the SCK pin is also the clock signal input to the

peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral

input with the SSPxCLKPPS register. The pin that is selected using the SSPxCLKPPS register should also

be made a digital I/O. This is done by clearing the corresponding ANSEL bit.

Figure 29-4.ꢀSPI Mode Waveform (Master Mode)

Rev. 30-000014A

3/13/2017

Write to

SSPxBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

(CKE = 0)

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPxIF

SSPSR to

SSPxBUF

29.2.2 SPI Slave Mode

In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is

latched, the SSPxIF Interrupt Flag bit is set.

Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be

observed by reading the SCK pin. The Idle state is determined by the CKP bit.

While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock

must meet the minimum high and low times as specified in the “Electrical Specifications” chapter.

While in Sleep mode, the slave can transmit/receive data. The Shift register is clocked from the SCK pin input and

when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep.

DS40002002B-page 446

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

29.2.3 Daisy-Chain Configuration

The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the

second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is

connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what

was received during the first group of clock pulses. The whole chain acts as one large communication shift register.

The daisy-chain feature only requires a single Slave Select line from the master device.

The following figure shows the block diagram of a typical daisy-chain connection when operating in SPI mode.

Figure 29-5.ꢀSPI Daisy-Chain Connection

Rev. 30-000015A

3/31/2017

SCK

SDO

SCK

SDI

SDO

SS

SPI Master

SPI Slave

#1

SDI

General I/O

SCK

SDI

SDO

SS

SPI Slave

#2

SCK

SDI

SDO

SS

SPI Slave

#3

In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit will

enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to

ignore data that may not apply to it.

29.2.4 Slave Select Synchronization

The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master

device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is

starting.

If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave

Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is

pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync

with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select

line allows the slave and master to align themselves at the beginning of each transmission.

The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPM =

0100).

When the SS pin is low, transmission and reception are enabled and the SDO pin is driven.

When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes

a floating output. External pull-up/pull-down resistors may be desirable depending on the application.

Note:ꢀ

1. When the SPI is in Slave mode with SS pin control enabled (SSPM = 0100), the SPI module will reset if the

SS pin is set to V_DD

.

2. When the SPI is used in Slave mode with CKE set; the user must enable SS pin control.

3. While operated in SPI Slave mode the SMP bit must remain clear.

DS40002002B-page 447

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MSSP - Master Synchronous Serial Port Module

When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high

level or clearing the SSPEN bit.

Figure 29-6.ꢀSlave Select Synchronous Waveform

Rev. 30-000016A

4/10/2017

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPxBUF

Shift register SSPSR

and bit count are reset

SSPxBUF to

SSPSR

bit 6

bit 7

bit 0

SDO

SDI

bit 7

bit 0

bit 7

Input

Sample

SSPxIF

Interrupt

Flag

SSPSR to

SSPxBUF

DS40002002B-page 448

Datasheet

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MSSP - Master Synchronous Serial Port Module

Figure 29-7.ꢀSPI Mode Waveform (Slave Mode with CKE = 0)

Rev. 30-000017A

4/3/2017

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPxBUF

Valid

bit 6

bit 2

bit 5

bit 4

bit 3

bit 1

bit 0

SDO

bit 7

SDI

bit 0

bit 7

Input

Sample

SSPxIF

Interrupt

Flag

SSPSR to

SSPxBUF

Write Collision

detection active

Figure 29-8.ꢀSPI Mode Waveform (Slave Mode with CKE = 1)

Rev. 30-000018A

4/1/2017

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPxBUF

Valid

bit 6

bit 3

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

SDI

bit 0

Input

Sample

SSPxIF

Interrupt

Flag

SSPSR to

SSPxBUF

Write Collision

detection active

DS40002002B-page 449

Datasheet

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MSSP - Master Synchronous Serial Port Module

29.2.5 SPI Operation in Sleep Mode

In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case

of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the MSSP clock is much faster than the system clock.

In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will

wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSP interrupts should be disabled.

In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception

will remain in that state until the device wakes. After the device returns to Run mode, the module will resume

transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the

device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight

bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device.

29.3

I²C Mode Overview

The Inter-Integrated Circuit (I²C) bus is a multimaster serial data communication bus. Devices communicate in a

master/slave environment where the master devices initiate the communication. A slave device is controlled through

addressing. The following two diagrams show block diagrams of the I²C Master and Slave modes, respectively.

Figure 29-9.ꢀMSSP Block Diagram (I²C Master mode)

Rev. 30-000019A

4/3/2017

Internal

data bus

[SSPM[3:0]]

SSPxDATPPS⁽¹⁾

Read

Write

SDA

SDA in

PPS

SSPxBUF

SSPSR

Generator

(SSPxADD)

Shift

Clock

RxyPPS⁽¹⁾

PPS

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate (SSPxCON2)

SSPxCLKPPS⁽²⁾

PPS

SCL

PPS

Start bit detect,

Stop bit detect

RxyPPS⁽²⁾

Write collision detect

Clock arbitration

State counter for

Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV

Reset SEN, PEN (SSPxCON2)

Set SSP1IF, BCL1IF

SCL in

end of XMIT/RCV

Address Match detect

Bus Collision

Note 1: SDA pin selections must be the same for input and output

2: SCL pin selections must be the same for input and output

DS40002002B-page 450

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Figure 29-10.ꢀMSSP Block Diagram (I²C Slave mode)

Rev. 30-000020A

4/3/2017

Internal

Data Bus

Read

Write

SSPxCLKPPS⁽²⁾

SSPxBUF Reg

SSPSR Reg

SCL

PPS

Shift

Clock

Stretching

MSb

LSb

RxyPPS⁽²⁾

SSPxMSK Reg

Match Detect

SSPxADD Reg

SSPxDATPPS⁽¹⁾

SDA

Addr Match

PPS

Set, Reset

S, P bits

(SSPxSTAT Reg)

Start and

Stop bit Detect

RxyPPS⁽¹⁾

Note 1: SDA pin selections must be the same for input and output

2: SCL pin selections must be the same for input and output

The I²C bus specifies two signal connections:

•

Serial Clock (SCL)

Serial Data (SDA)

Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply

voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one.

The following diagram shows a typical connection between two processors configured as master and slave devices.

Figure 29-11.ꢀI²C Master/Slave Connection

Rev. 30-000021A

4/3/2017

VDD

SCL

SDA

SCL

SDA

VDD

Master

Slave

The I²C bus can operate with one or more master devices and one or more slave devices.

There are four potential modes of operation for a given device:

•

Master Transmit mode

(master is transmitting data to a slave)

Master Receive mode

(master is receiving data from a slave)

Slave Transmit mode

(slave is transmitting data to a master)

DS40002002B-page 451

Datasheet

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MSSP - Master Synchronous Serial Port Module

•

Slave Receive mode

(slave is receiving data from the master)

To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start

bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write

bit, which determines whether the master intends to transmit to or receive data from the slave device.

If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The

master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in

Receive mode or Transmit mode, respectively.

A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data

bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master

intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave.

The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the

slave device has received the transmitted data and is ready to receive more.

The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL

line is held high are used to indicate Start and Stop bits.

If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after

each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave

Receive mode.

If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds

after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is in

Slave Transmit mode.

On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the

master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-

high transition of the SDA line while the SCL line is held high.

In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the

master device may send another Start bit in place of the Stop bit or last ACK bit when it is in Receive mode.

The I²C bus specifies three message protocols:

•

Single message where a master writes data to a slave.

Single message where a master reads data from a slave.

Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes

and reads, to one or more slaves.

When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical

zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on

the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data.

When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master

device communicating at any single time.

29.3.1 Register Definitions: I²C Mode

The MSSPx module has seven registers for I²C operation.

These are:

•

MSSP Status register (SSPxSTAT)

MSSP Control register 1 (SSPxCON1)

MSSP Control register 2 (SSPxCON2)

MSSP Control register 3 (SSPxCON3)

Serial Receive/Transmit Buffer register (SSPxBUF)

MSSP Address register (SSPxADD)

I²C Slave Address Mask register (SSPxMSK)

MSSP Shift register (SSPSR) – not directly accessible

DS40002002B-page 452

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

SSPxCON1, SSPxCON2, SSPxCON3 and SSPxSTAT are the Control and STATUS registers in I²C mode operation.

The SSPxCON1, SSPxCON2, and SSPxCON3 registers are readable and writable. The lower six bits of the

SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPSR is the Shift register used for

shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. SSPxADD

contains the slave device address when the MSSP is configured in I²C Slave mode. When the MSSP is configured in

Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload value.

SSPxMSK holds the slave address mask value when the module is configured for 7-Bit Address Masking mode.

While it is a separate register, it shares the same SFR address as SSPxADD; it is only accessible when the

SSPM[3:0] bits are specifically set to permit access. In receive operations, SSPSR and SSPxBUF together, create a

double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF

interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both

SSPxBUF and SSPSR.

29.4

I²C Mode Operation

All MSSP I²C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags

interface the module with the PIC^®microcontroller and user software. Two pins, SDA and SCL, are exercised by the

module to communicate with other external I²C devices.

29.4.1 Clock Stretching

When a slave device has not completed processing data, it can delay the transfer of more data through the process

of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit,

indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the

SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the

SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue

communicating.

Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data.

29.4.2 Arbitration

Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot

begin a new message until the bus returns to an Idle state.

However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the

process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that

it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop

transmitting on the SDA line.

For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a

logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of

the line is different than expected and concludes that another transmitter is communicating.

The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this

transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop

condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any

difference between the expected and actual levels on the SDA line continues with its original transmission. It can do

so without any complications, because so far, the transmission appears exactly as expected with no other transmitter

disturbing the message.

Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common.

If two master devices are sending a message to two different slave devices at the address stage, the master sending

the lower slave address always wins arbitration. When two master devices send messages to the same slave

address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data

stage.

Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.

DS40002002B-page 453

Datasheet

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MSSP - Master Synchronous Serial Port Module

29.4.3 Byte Format

All communication in I²C is done in 9-bit segments. A byte is sent from a master to a slave or vice versa, followed by

an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA

changes that pin to an input and reads in an acknowledge value on the next clock pulse.

The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on

the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus,

explained below.

29.4.4 Definition of I²C Terminology

There is language and terminology in the description of I²C communication that have definitions specific to I²C. That

word usage is defined below and may be used in the rest of this document without explanation. This table was

adapted from the Philips I²C specification.

TERM

Transmitter

Receiver

Master

Description

The device that shifts data out onto the bus.

The device that shifts data in from the bus.

The device that initiates a transfer, generates clock signals and terminates a transfer.

The device addressed by the master.

Slave

Multi-master

Arbitration

A bus with more than one device that can initiate data transfers.

Procedure to ensure that only one master at a time controls the bus. Winning arbitration

ensures that the message is not corrupted.

Synchronization

Idle

Procedure to synchronize the clocks of two or more devices on the bus.

No master is controlling the bus, and both SDA and SCL lines are high.

Any time one or more master devices are controlling the bus.

Active

Addressed Slave Slave device that has received a matching address and is actively being clocked by a master.

Matching Address Address byte that is clocked into a slave that matches the value stored in SSPxADD.

Write Request

Read Request

Slave receives a matching address with R/W bit clear, and is ready to clock in data.

Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of

the Slave. This data is the next and all following bytes until a Restart or Stop.

Clock Stretching When a device on the bus hold SCL low to stall communication.

Bus Collision

Any time the SDA line is sampled low by the module while it is outputting and expected high

state.

29.4.5 SDA and SCL Pins

Selection of any I²C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should

be set by the user to inputs by setting the appropriate TRIS bits.

Note:ꢀ

1. SDA is tied to output zero when an I²C mode is enabled.

2. Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are

bidirectional. The SDA input is selected with the SSPxDATPPS registers. The SCL input is selected with the

SSPxCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user’s responsibility to make

the selections so that both the input and the output for each function is on the same pin.

29.4.6 SDA Hold Time

The hold time of the SDA pin is selected by the SDAHT bit. Hold time is the time SDA is held valid after the falling

edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large

capacitance.

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MSSP - Master Synchronous Serial Port Module

29.4.7 Start Condition

The I²C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high.

A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active

state. Figure 29-12 shows wave forms for Start and Stop conditions.

A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This

does not conform to the I²C Specification that states no bus collision can occur on a Start.

29.4.8 Stop Condition

A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high.

Important:ꢀ At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes

low then high again while the SCL line stays high, only the Start condition is detected.

Figure 29-12.ꢀI²C Start and Stop Conditions

Rev. 30-000022A

4/3/2017

SDA

SCL

S

P

Change of

Data Allowed

Start

Stop

Condition

29.4.9 Restart Condition

A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after

terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic

and preparing it to clock in an address. The master may want to address the same or another slave. Figure 29-13

shows the wave form for a Restart condition.

In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a

slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the

high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data.

After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high

address with R/W clear, or high address match fails.

DS40002002B-page 455

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PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Figure 29-13.ꢀI²C Restart Condition

Rev. 30-000023A

4/3/2017

Sr

Change of

Data Allowed

Restart

Condition

29.4.10 Start/Stop Condition Interrupt Masking

The SCIE and PCIE bits can enable the generation of an interrupt in Slave modes that do not typically support this

function. These bits will have no effect in Slave modes where interrupt on Start and Stop detect are already enabled.

29.4.11 Acknowledge Sequence

The ninth SCL pulse for any transferred byte in I²C is dedicated as an Acknowledge. It allows receiving devices to

respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this

time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the

transmitter that the device has received the transmitted data and is ready to receive more.

The result of an ACK is placed in the ACKSTAT bit in the SSPxCON2 register.

The slave software, when the AHEN and DHEN bits in the SSPxCON3 register are set, allows the user to set the

ACK value sent back to the transmitter. The ACKDT bit in the SSPxCON2 register is set/cleared to determine the

response.

The slave hardware will generate an ACK response if both the AHEN and DHEN bits are clear. However, if the BF bit

in the SSPxSTAT register or the SSPOV bit in the SSPxCON1 register are set when a byte is received then the ACK

will not be sent by the slave.

When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit in the SSPxCON3

register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only

active when either the AHEN bit or DHEN bit is enabled.

29.5

I²C Slave Mode Operation

The MSSP Slave mode operates in one of four modes selected by the SSPM bits. The modes can be divided into 7-

bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead

for handling the larger addresses.

Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally getting set

upon detection of a Start, Restart, or Stop condition.

29.5.1 Slave Mode Addresses

The SSPxADD register contains the Slave mode address. The first byte received after a Start or Restart condition is

compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register

and an interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the

software that anything happened.

The SSPxMSK register affects the address matching process. See 29.5.9 SSP Mask Register for more information.

29.5.1.1 I²C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address

match.

DS40002002B-page 456

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MSSP - Master Synchronous Serial Port Module

29.5.1.2 I²C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8

are the two MSbs of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register.

After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the

low address. The low address byte is clocked in and all eight bits are compared to the low address value in

SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL is held low until SSPxADD is

updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is

ready to receive the high address byte on the next communication.

A high and low address match as a write request is required at the start of all 10-bit addressing communication. A

transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with

the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is

only valid for a slave after it has received a complete high and low address byte match.

29.5.2 Slave Reception

When the R/W bit of a matching received address byte is clear, the R/W bit is cleared. The received address is

loaded into the SSPxBUF register and acknowledged.

When the overflow condition exists for a received address, then Not Acknowledge (NACK) is given. An overflow

condition is defined as either the BF bit is set, or the SSPOV bit is set. The BOEN bit modifies this operation. For

more information see SSPxCON3.

An MSSP interrupt is generated for each transferred data byte. The SSPxIF flag bit must be cleared by software.

When the SEN bit is set, SCL will be held low (clock stretch) following each received byte. The clock must be

released by setting the CKP bit, except sometimes in 10-bit mode. See 29.5.6.2 10-bit Addressing Mode for more

details.

29.5.2.1 7-bit Addressing Reception

This section describes a standard sequence of events for the MSSP module configured as an I²C slave in 7-bit

Addressing mode. Figure 29-14 and Figure 29-15 are used as a visual reference for this description.

This is a step by step process of what typically must be done to accomplish I²C communication.

1. Start bit detected.

2. S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

3. Matching address with R/W bit clear is received.

4. The slave pulls SDA low sending an ACK to the master, and sets SSPxIF bit.

5. Software clears the SSPxIF bit.

6. Software reads received address from SSPxBUF clearing the BF flag.

7. If SEN = 1; Slave software sets CKP bit to release the SCL line.

8. The master clocks out a data byte.

9. Slave drives SDA low sending an ACK to the master, and sets SSPxIF bit.

10. Software clears SSPxIF.

11. Software reads the received byte from SSPxBUF clearing BF.

12. Steps 8-12 are repeated for all received bytes from the master.

13. Master sends Stop condition, setting P bit, and the bus goes Idle.

29.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and

clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to

decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds

™

support for PMBus that was not present on previous versions of this module.

This list describes the steps that need to be taken by slave software to use these options for I²C communication.

Figure 29-16 displays a module using both address and data holding. Figure 29-17 includes the operation with the

SEN bit of the SSPxCON2 register set.

1. S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

DS40002002B-page 457

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MSSP - Master Synchronous Serial Port Module

2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling edge

of SCL.

3. Slave clears the SSPxIF.

4. Slave can look at the ACKTIM bit to determine if the SSPxIF was after or before the ACK.

5. Slave reads the address value from SSPxBUF, clearing the BF flag.

6. Slave sets ACK value clocked out to the master by setting ACKDT.

7. Slave releases the clock by setting CKP.

8. SSPxIF is set after an ACK, not after a NACK.

9. If SEN = 1, the slave hardware will stretch the clock after the ACK.

10. Slave clears SSPxIF.

Important:ꢀ SSPxIF is still set after the ninth falling edge of SCL even if there is no clock stretching

and BF has been cleared. Only if NACK is sent to master is SSPxIF not set

11. SSPxIF set and CKP cleared after eighth falling edge of SCL for a received data byte.

12. Slave looks at ACKTIM bit to determine the source of the interrupt.

13. Slave reads the received data from SSPxBUF clearing BF.

14. Steps 7-14 are the same for each received data byte.

15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a

Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit.

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PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

29.5.3 Slave Transmission

When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit is set. The received

address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit.

Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see 29.5.6 Clock Stretching for

more details). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done

preparing the transmit data.

The transmit data must be loaded into the SSPxBUF register, which also loads the SSPSR register. Then the SCL pin

should be released by setting the CKP bit. The eight data bits are shifted out on the falling edge of the SCL input.

This ensures that the SDA signal is valid during the SCL high time.

The ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is

copied to the ACKSTAT bit. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the

not ACK is latched by the slave, the slave goes Idle and waits for another occurrence of the Start bit. If the SDA line

was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be

released by setting bit CKP.

An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the

SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth

clock pulse.

29.5.3.1 Slave Mode Bus Collision

A slave receives a read request and begins shifting data out on the SDA line. If a bus collision is detected and the

SBCDE bit is set, the BCLxIF bit of the PIR3 register is set. Once a bus collision is detected, the slave goes Idle and

waits to be addressed again. User software can use the BCLxIF bit to handle a slave bus collision.

29.5.3.2 7-bit Transmission

A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines

what software for a slave will need to do to accomplish a standard transmission. Figure 29-18 can be used as a

reference to this list.

1. Master sends a Start condition on SDA and SCL.

2. S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

3. Matching address with R/W bit set is received by the Slave setting SSPxIF bit.

4. Slave hardware generates an ACK and sets SSPxIF.

5. SSPxIF bit is cleared by user.

6. Software reads the received address from SSPxBUF, clearing BF.

7. R/W is set so CKP was automatically cleared after the ACK.

8. The slave software loads the transmit data into SSPxBUF.

9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave.

10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register.

11. SSPxIF bit is cleared.

12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data.

Important:ꢀ

1.

2.

If the master ACKs then the clock will be stretched.

ACKSTAT is the only bit updated on the rising edge of the ninth SCL clock instead of the

falling edge.

13. Steps 9-13 are repeated for each transmitted byte.

14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

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MSSP - Master Synchronous Serial Port Module

29.5.3.3 7-bit Transmission with Address Hold Enabled

Setting the AHEN bit enables additional clock stretching and interrupt generation after the eighth falling edge of a

received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt

is set.

Figure 29-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled.

1. Bus starts Idle.

2. Master sends Start condition; the S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is

cleared and SSPxIF interrupt is generated.

4. Slave software clears SSPxIF.

5. Slave software reads the ACKTIM, R/W and D/A bits to determine the source of the interrupt.

6. Slave reads the address value from the SSPxBUF register clearing the BF bit.

7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit

accordingly.

8. Slave sets the CKP bit releasing SCL.

9. Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set.

11. Slave software clears SSPxIF.

12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit.

Important:ꢀ SSPxBUF cannot be loaded until after the ACK.

13. Slave sets the CKP bit releasing the clock.

14. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse.

15. Slave hardware copies the ACK value into the ACKSTAT bit.

16. Steps 10-15 are repeated for each byte transmitted to the master from the slave.

17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the

communication.

Important:ꢀ Master must send a not ACK on the last byte to ensure that the slave releases the SCL

line to receive a Stop.

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PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

29.5.4 Slave Mode 10-bit Address Reception

This section describes a standard sequence of events for the MSSP module configured as an I²C slave in 10-bit

Addressing mode.

Figure 29-20 is used as a visual reference for this description.

This is a step-by-step process of what must be done by the slave software to accomplish I²C communication.

1. Bus starts Idle.

2. Master sends Start condition; S bit is set; SSPxIF is set if interrupt on Start detect is enabled.

3. Master sends matching high address with R/W bit clear; UA bit is set.

4. Slave sends ACK and SSPxIF is set.

5. Software clears the SSPxIF bit.

6. Software reads received address from SSPxBUF clearing the BF flag.

7. Slave loads low address into SSPxADD, releasing SCL.

8. Master sends matching low address byte to the slave; UA bit is set.

Important:ꢀ Updates to the SSPxADD register are not allowed until after the ACK sequence.

9. Slave sends ACK and SSPxIF is set.

Important:ꢀ If the low address does not match, SSPxIF and UA are still set so that the slave

software can set SSPxADD back to the high address. BF is not set because there is no match. CKP

is unaffected.

10. Slave clears SSPxIF.

11. Slave reads the received matching address from SSPxBUF clearing BF.

12. Slave loads high address into SSPxADD.

13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPxIF is set.

14. If SEN bit is set, CKP is cleared by hardware and the clock is stretched.

15. Slave clears SSPxIF.

16. Slave reads the received byte from SSPxBUF clearing BF.

17. If SEN is set the slave sets CKP to release the SCL.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

29.5.5 10-bit Addressing with Address or Data Hold

Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is

the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared

and SCL line is held low are the same. Figure 29-21 can be used as a reference of a slave in 10-bit addressing with

AHEN set.

Figure 29-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode.

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MSSP - Master Synchronous Serial Port Module

29.5.6 Clock Stretching

Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The

slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master

device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any

stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL.

The CKP bit is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL

line to go low and then hold it. Setting CKP will release SCL and allow more communication.

29.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit is set, a read request, the slave hardware will clear CKP. This allows the slave time

to update SSPxBUF with data to transfer to the master. If the SEN bit is set, the slave hardware will always stretch

the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes.

Important:ꢀ

1. The BF bit has no effect on whether or not the clock will be stretched. This is different than previous

versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the

ninth falling edge of SCL.

2. Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded

before the ninth falling edge of SCL. It is now always cleared for read requests.

29.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is

stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD.

Important:ꢀ Previous versions of the module did not stretch the clock if the second address byte did not

match.

29.5.6.3 Byte NACKing

When the AHEN bit is set, CKP is cleared by hardware after the eighth falling edge of SCL for a received matching

address byte. When the DHEN bit is set, CKP is cleared after the eighth falling edge of SCL for received data.

Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it

wants to ACK the received data.

29.5.7 Clock Synchronization and the CKP bit

Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the

CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not

assert the SCL line until an external I²C master device has already asserted the SCL line. The SCL output will remain

low until the CKP bit is set and all other devices on the I²C bus have released SCL. This ensures that a write to the

CKP bit will not violate the minimum high time requirement for SCL (see the following figure).

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MSSP - Master Synchronous Serial Port Module

Figure 29-23.ꢀClock Synchronization Timing

Rev. 30-000033A

4/3/2017

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX ‚ – 1

Master device

asserts clock

CKP

Master device

releases clock

WR

SSPxCON1

29.5.8 General Call Address Support

The addressing procedure for the I²C bus is such that the first byte after the Start condition usually determines which

device will be the slave addressed by the master device. The exception is the general call address that can address

all devices. When this address is used, all devices should, in theory, respond with an acknowledge.

The general call address is a reserved address in the I²C protocol, defined as address 0x00. When the GCEN bit is

set, the slave module will automatically ACK the reception of this address regardless of the value stored in

SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave

software can read SSPxBUF and respond. The following figure shows a general call reception sequence.

Figure 29-24.ꢀSlave Mode General Call Address Sequence

Rev. 30-000034A

4/3/2017

Address is compared to General Call Address

after ACK, set interrupt

0

Receiving Data

D5 D4 D3 D2 D1

ACK

R/W =

General Call Address

ACK

9

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

9

S

SSPxIF

BF (SSPxSTAT<0>)

Cleared by software

SSPxBUF is read

GCEN (SSPxCON2<7>)

’1’

In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare

to receive the second byte as data, just as it would in 7-bit mode.

If the AHEN bit is set, just as with any other address reception, the slave hardware will stretch the clock after the

eighth falling edge of SCL. The slave must then set its ACKEN value and release the clock with communication

progressing as it would normally.

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MSSP - Master Synchronous Serial Port Module

29.5.9 SSP Mask Register

An SSP Mask register (SSPxMSK) is available in I²C Slave mode as a mask for the value held in the SSPSR register

during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making the

corresponding bit of the received address a “don’t care”.

This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until

written with a mask value.

The SSP Mask register is active during:

•

7-bit Address mode: address compare of A[7:1].

10-bit Address mode: address compare of A[7:0] only. The SSP mask has no effect during the reception of the

first (high) byte of the address.

29.6

I²C Master Mode

Master mode is enabled by setting and clearing the appropriate SSPM bits and setting the SSPEN bit. In Master

mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output

driver TRIS controls when necessary to drive the pins low.

Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The

Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I²C bus

may be taken when the P bit is set, or the bus is Idle.

In Firmware Controlled Master mode, user code conducts all I²C bus operations based on Start and Stop bit

condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other

communication is done by the user software directly manipulating the SDA and SCL lines.

The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (SSP interrupt, if enabled):

•

Start condition detected

Stop condition detected

Data transfer byte transmitted/received

Acknowledge transmitted/received

Repeated Start generated

Important:ꢀ

1. The MSSP module, when configured in I²C Master mode, does not allow queuing of events. For

instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF

register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF

will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not

occur.

2. Master mode suspends Start/Stop detection when sending the Start/Stop condition by means of the

SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware

clears the control bit.

29.6.1 I²C Master Mode Operation

The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with

a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the

next serial transfer, the I²C bus will not be released.

In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte

transmitted contains the slave address of the receiving device (7 bits) and the R/W bit. In this case, the R/W bit will

be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is

received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer.

In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and

the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed

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MSSP - Master Synchronous Serial Port Module

by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is

received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions

indicate the beginning and end of transmission.

A Baud Rate Generator is used to set the clock frequency output on SCL. See 29.7 Baud Rate Generator for more

details.

29.6.2 Clock Arbitration

Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the

SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is

suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud

Rate Generator is reloaded with the contents of 29.9.2 SSPxADD and begins counting. This ensures that the SCL

high time will always be at least one BRG rollover count in the event that the clock is held low by an external device

as shown in the following figure.

Figure 29-25.ꢀBaud Rate Generator Timing with Clock Arbitration

Rev. 30-000035A

4/3/2017

SDA

SCL

DX

DX ‚ – 1

SCL deasserted but slave holds

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count

BRG

Reload

29.6.3 WCOL Status Flag

If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL

bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it

indicates that an action on SSPxBUF was attempted while the module was not Idle.

Important:ꢀ Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is

disabled until the Start condition is complete.

29.6.4 I²C Master Mode Start Condition Timing

To initiate a Start condition (Figure 29-26), the user sets the SEN Start Enable bit. If the SDA and SCL pins are

sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and starts its count. If SCL and

SDA are both sampled high when the Baud Rate Generator times out (T_BRG), the SDA pin is driven low. The action of

the SDA being driven low while SCL is high is the Start condition and causes the S bit to be set. Following this, the

Baud Rate Generator is reloaded with the contents of SSPxADD and resumes its count. When the Baud Rate

Generator times out (T_BRG), the SEN bit will be automatically cleared by hardware; the Baud Rate Generator is

suspended, leaving the SDA line held low and the Start condition is complete.

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MSSP - Master Synchronous Serial Port Module

Important:ꢀ

1. If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if

during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus

collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and

the I²C module is reset into its Idle state.

2. The Philips I²C specification states that a bus collision cannot occur on a Start.

Figure 29-26.ꢀFirst Start Bit Timing

Rev. 30-000036A

4/3/2017

Set S bit (SSPxSTAT<3>)

Write to SEN bit occurs here

At completion of Start bit,

hardware clears SEN bit

and sets SSPxIF bit

SDA = 1,

SCL = 1

TBRG

Write to SSPxBUF occurs here

2nd bit

SDA

SCL

1st bit

TBRG

S

TBRG

29.6.5 I²C Master Mode Repeated Start Condition Timing

A Repeated Start condition (Figure 29-27) occurs when the RSEN bit is programmed high and the master state

machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled

low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud

Rate Generator count (T_BRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be

deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting.

SDA and SCL must be sampled high for one T_BRG. This action is then followed by assertion of the SDA pin (SDA = 0)

for one T_BRGwhile SCL is high. SCL is asserted low. Following this, the RSEN bit will be automatically cleared and

the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected

on the SDA and SCL pins, the S bit will be set. The SSPxIF bit will not be set until the Baud Rate Generator has

timed out.

Important:ꢀ

1. If RSEN is programmed while any other event is in progress, it will not take effect.

2. A bus collision during the Repeated Start condition occurs if:

– SDA is sampled low when SCL goes from low-to-high.

– SCL goes low before SDA is asserted low. This may indicate that another master is attempting

to transmit a data ‘1’.

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PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Figure 29-27.ꢀRepeated Start Condition Waveform

Rev. 30-000037A

4/10/2017

S bit set by hardware

Write to SSPxCON2

occurs here

SDA = 1,

At completion of Start bit,

hardware clears the RSEN bit

and sets SSPxIF

SDA = 1,

SCL = 1

SCL (no change)

TBRG

1st bit

SDA

SCL

Write to SSPxBUF occurs here

TBRG

Sr

Repeated Start

TBRG

29.6.6 I²C Master Mode Transmission

Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a

value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to

begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the

falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (T_BRG). Data should be

valid before SCL is released high. When the SCL pin is released high, it is held that way for T_BRG. The data on the

SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows

the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred,

or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth

clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set.

After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next

data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 29-28).

After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven

address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA

pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample

the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT

Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the

SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF

takes place, holding SCL low and allowing SDA to float.

29.6.6.1 BF Status Flag

In Transmit mode, the BF bit is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted

out.

29.6.6.2 WCOL Status Flag

If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte),

the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).

The WCOL bit must be cleared by software before the next transmission.

29.6.6.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when

the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address

(including a general call), or when the slave has properly received its data.

29.6.6.4 Typical Transmit Sequence:

1. The user generates a Start condition by setting the SEN bit.

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MSSP - Master Synchronous Serial Port Module

2. SSPxIF is set by hardware on completion of the Start.

3. SSPxIF is cleared by software.

4. The MSSP module will wait the required start time before any other operation takes place.

5. The user loads the SSPxBUF with the slave address to transmit.

6. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as

SSPxBUF is written to.

7. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit.

8. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit.

9. The user loads the SSPxBUF with eight bits of data.

10. Data is shifted out the SDA pin until all eight bits are transmitted.

11. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit.

12. Steps 8-11 are repeated for all transmitted data bytes.

13. The user generates a Stop or Restart condition by setting the PEN or RSEN bits. Interrupt is generated once

the Stop/Restart condition is complete.

Figure 29-28.ꢀI²C Master Mode Waveform (Transmission, 7 or 10-bit Address)

Rev. 30-000038A

4/3/2017

ACKSTAT in

Write SSPxCON2<0> SEN = 1

SSPxCON2 = 1

Start condition begins

From slave, clear ACKSTAT bit SSPxCON2<6>

Transmitting Data or Second Half

SEN = 0

R/W = 0

ACK = 0

Transmit Address to Slave

A7 A6 A5 A4 A3 A2 A1

ACK

of 10-bit Address

SDA

SCL

D7 D6 D5 D4 D3 D2 D1 D0

SSPxBUF written with 7-bit address and R/W

start transmit

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

P

S

SCL held low

while CPU

responds to SSPxIF

SSPxIF

Cleared by software service routine

from SSP interrupt

Cleared by software

BF (SSPxSTAT<0>)

SEN

SSPxBUF is written by software

SSPxBUF written

After Start condition, SEN cleared by hardware

PEN

R/W

29.6.7 I²C Master Mode Reception

Master mode reception (Figure 29-29) is enabled by programming the RCEN Receive Enable bit.

Important:ꢀ The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be

disregarded.

The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-

high) and data is shifted into the SSPSR. After the falling edge of the eighth clock all the following events occur:

•

The receive enable flag is automatically cleared

The contents of the SSPSR are loaded into the SSPxBUF

DS40002002B-page 477

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MSSP - Master Synchronous Serial Port Module

•

The BF flag bit is set

The SSPxIF flag bit is set

The Baud Rate Generator is suspended from counting

The SCL pin is held low

The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is

automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the

Acknowledge Sequence Enable, ACKEN bit.

29.6.7.1 BF Status Flag

In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is

cleared when the SSPxBUF register is read.

29.6.7.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR while the BF flag bit is already

set from a previous reception.

29.6.7.3 WCOL Status Flag

If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the

WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).

29.6.7.4 Typical Receive Sequence:

1. The user generates a Start condition by setting the SEN bit.

2. SSPxIF is set by hardware on completion of the Start.

3. SSPxIF is cleared by software.

4. User writes SSPxBUF with the slave address to transmit and the R/W bit set.

5. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as

SSPxBUF is written to.

6. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit.

7. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit.

8. User sets the RCEN bit and the master clocks in a byte from the slave.

9. After the eighth falling edge of SCL, SSPxIF and BF are set.

10. Master clears SSPxIF and reads the received byte from SSPUF which clears BF.

11. Master sets the ACK value to be sent to slave in the ACKDT bit and initiates the ACK by setting the ACKEN

bit.

12. Master’s ACK is clocked out to the slave and SSPxIF is set.

13. User clears SSPxIF.

14. Steps 8-13 are repeated for each received byte from the slave.

15. Master sends a not ACK or Stop to end communication.

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MSSP - Master Synchronous Serial Port Module

29.6.8 Acknowledge Sequence Timing

An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable ACKEN bit. When this bit is set,

the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user

wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (T_BRG) and

the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate

Generator counts for T_BRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the

Baud Rate Generator is turned off and the MSSP module then goes into Idle mode.

Figure 29-30.ꢀAcknowledge Sequence Waveform

Rev. 30-000040A

4/3/2017

Acknowledge sequence starts here,

ACKEN automatically cleared

write to SSPxCON2

ACKEN = 1, ACKDT = 0

TBRG

9

TBRG

SDA

SCL

D0

ACK

8

SSPxIF

Cleared in

software

SSPxIF set at the end

of Acknowledge sequence

SSPxIF set at

the end of receive

Cleared in

software

Note: TBRG = one Baud Rate Generator period.

29.6.8.1 Acknowledge Write Collision

If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write does not occur).

29.6.9 Stop Condition Timing

A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable PEN bit.

At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is

set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded

and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one T_BRG

(Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while

SCL is high, the P bit is set. One T_BRGlater, the PEN bit is cleared and the SSPxIF bit is set.

Figure 29-31.ꢀStop Condition in Receive or Transmit Mode

Rev. 30-000041A

4/3/2017

SCL = 1for TBRG, followed by SDA = 1for TBRG

after SDA sampled high. P bit (SSPxSTAT<4>) is set.

Write to SSPxCON2,

set PEN

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

Falling edge of

9th clock

TBRG

SCL

SDA

ACK

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

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MSSP - Master Synchronous Serial Port Module

29.6.9.1 Write Collision on Stop

If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of

the buffer are unchanged (the write does not occur).

29.6.10 Sleep Operation

While in Sleep mode, the I²C slave module can receive addresses or data and when an address match or complete

byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled).

29.6.11 Effects of a Reset

A Reset disables the MSSP module and terminates the current transfer.

29.6.12 Multi-Master Mode

In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP

module is disabled. Control of the I²C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P

bits cleared. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition

occurs.

In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected

output level. This check is performed by hardware with the result placed in the BCLxIF bit.

The states where arbitration can be lost are:

•

Address Transfer

Data Transfer

A Start Condition

A Repeated Start Condition

An Acknowledge Condition

29.6.13 Multi-Master Communication, Bus Collision and Bus Arbitration

Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA

pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master

asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data

sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt

Flag, BCLxIF and reset the I²C port to its Idle state (Figure 29-32).

If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the

SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision

Interrupt Service Routine and if the I²C bus is free, the user can resume communication by asserting a Start

condition.

If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the

condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2 register

are cleared. When the user services the bus collision Interrupt Service Routine and if the I²C bus is free, the user can

resume communication by asserting a Start condition.

The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will be set.

A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left

off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination

of when the bus is free. Control of the I²C bus can be taken when the P bit is set, or the bus is Idle and the S and P

bits are cleared.

DS40002002B-page 481

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MSSP - Master Synchronous Serial Port Module

Figure 29-32.ꢀBus Collision Timing for Transmit and Acknowledge

Rev. 30-000042A

4/3/2017

Sample SDA. While SCL is high,

data does not match what is driven

by the master.

Data changes

while SCL = 0

SDA line pulled low

by another source

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCLxIF)

BCLxIF

29.6.13.1 Bus Collision During a Start Condition

During a Start condition, a bus collision occurs if:

1. SDA or SCL are sampled low at the beginning of the Start condition (Figure 29-33).

2. SCL is sampled low before SDA is asserted low (Figure 29-34).

During a Start condition, both the SDA and the SCL pins are monitored.

If the SDA pin is already low, or the SCL pin is already low, then all of the following occur:

•

the Start condition is aborted,

the BCLxIF flag is set and

the MSSP module is reset to its Idle state (Figure 29-33).

DS40002002B-page 482

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MSSP - Master Synchronous Serial Port Module

Figure 29-33.ꢀBus Collision During Start Condition (SDA Only)

Rev. 30-000043A

4/3/2017

SDA goes low before the SEN bit is set.

Set BCLxIF,

S bit and SSPxIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.

SSPx module reset into Idle state.

SDA sampled low before

Start condition. Set BCLxIF.

S bit and SSPxIF set because

SDA = 0, SCL = 1.

BCLxIF

SSPxIF and BCLxIF are

cleared by software

S

SSPxIF

SSPxIF and BCLxIF are

cleared by software

The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud

Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs

because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition.

Figure 29-34.ꢀBus Collision During Start Condition (SCL = 0)

Rev. 30-000044A

4/3/2017

SDA = 0, SCL = 1

TBRG

SDA

SCL

SEN

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

SCL = 0before SDA = 0,

bus collision occurs. Set BCLxIF.

SCL = 0before BRG time-out,

bus collision occurs. Set BCLxIF.

BCLxIF

Interrupt cleared

by software

S

’0’

SSPxIF

If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 29-35). If,

however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate

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MSSP - Master Synchronous Serial Port Module

Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision

does not occur. At the end of the BRG count, the SCL pin is asserted low.

Figure 29-35.ꢀBRG Reset Due to SDA Arbitration During Start Condition

Rev. 30-000045A

4/10/2017

0

SDA = , SCL = 1

Set S

Set SSPxIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

time out

-

SEN

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

’0’

BCLxIF

S

SSPxIF

Interrupts cleared

by software

SDA = 0, SCL = 1,

set SSPxIF

Important:ꢀ The reason that bus collision is not a factor during a Start condition is that no two bus masters

can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before

the other. This condition does not cause a bus collision because the two masters must be allowed to

arbitrate the first address following the Start condition. If the address is the same, arbitration must be

allowed to continue into the data portion, Repeated Start or Stop conditions.

29.6.13.2 Bus Collision During a Repeated Start Condition

During a Repeated Start condition, a bus collision occurs if:

1. A low level is sampled on SDA when SCL goes from low level to high level (Case 1).

2. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’

(Case 2).

When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down

to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 29-36). If

SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times

out, no bus collision occurs because no two masters can assert SDA at exactly the same time.

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MSSP - Master Synchronous Serial Port Module

Figure 29-36.ꢀBus Collision During a Repeated Start Condition (Case 1)

Rev. 30-000046A

4/3/2017

SDA

SCL

Sample SDA when SCL goes high.

0

If SDA = , set BCLxIF and release SDA and SCL.

RSEN

BCLxIF

Cleared by software

’0’

S

’0’

SSPxIF

If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see

Figure 29-37.

If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven

low and the Repeated Start condition is complete.

Figure 29-37.ꢀBus Collision During Repeated Start Condition (Case 2)

Rev. 30-000047A

4/3/2017

TBRG

SDA

SCL

SCL goes low before SDA,

set BCLxIF. Release SDA and SCL.

BCLxIF

RSEN

Interrupt cleared

by software

’0’

S

SSPxIF

29.6.13.3 Bus Collision During a Stop Condition

Bus collision occurs during a Stop condition if:

1. After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed

out (Case 1).

2. After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2).

The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When

the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to

zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to

another master attempting to drive a data ‘0’ (Figure 29-38). If the SCL pin is sampled low before SDA is allowed to

float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 29-39).

DS40002002B-page 485

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Figure 29-38.ꢀBus Collision During a Stop Condition (Case 1)

Rev. 30-000048A

4/3/2017

SDA sampled

TBRG

low after TBRG,

set BCLxIF

SDA

SDA asserted low

SCL

PEN

BCLxIF

P

’0’

SSPxIF

Figure 29-39.ꢀBus Collision During a Stop Condition (Case 2)

Rev. 30-000049A

4/3/2017

TBRG

SDA

SCL goes low before SDA goes high,

set BCLxIF

Assert SDA

SCL

PEN

BCLxIF

P

’0’

SSPxIF

29.7

Baud Rate Generator

The MSSP module has a Baud Rate Generator available for clock generation in both I²C and SPI Master modes. The

Baud Rate Generator (BRG) reload value is placed in the SSPxADD register. When a write occurs to SSPxBUF, the

Baud Rate Generator will automatically begin counting down.

Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain

in its last state.

An internal signal “Reload”, shown in Figure 29-40, triggers the value from SSPxADD to be loaded into the BRG

counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is

asserted depends on the mode in which the MSSP is being operated.

Table 29-1 illustrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD.

Example 29-1.ꢀMSSP Baud Rate Generator Frequency Equation

ꢢ

ꢊꢋꢌ

ꢢ

=

ꢌꢖꢊꢌꢤ

4 × ꢋꢋꢀꢔꢞꢙꢙ + 1

DS40002002B-page 486

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Figure 29-40.ꢀBaud Rate Generator Block Diagram

Rev. 30-000050A

4/3/2017

SSPM[3:0]

SSPxADD[7:0]

SSPM[3:0]

SCL

Reload

Control

Reload

BRG Down Counter

SSPCLK

FOSC/2

Important:ꢀ Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate

Generator for I²C. This is an implementation limitation.

Table 29-1.ꢀMSSP Clock Rate w/BRG

Fclock

(2 Rollovers of BRG)

F_OSC

F_CY

BRG Value

32 MHz

16 MHz

4 MHz

8 MHz

4 MHz

1 MHz

13h

19h

4Fh

09h

0Ch

27h

09h

400 kHz

308 kHz

100 kHz

400 kHz

308 kHz

100 kHz

Note:ꢀ Refer to the I/O port electrical specifications in the “Electrical Specifications” section, Internal Oscillator

Parameters, to ensure the system is designed to support all requirements.

DS40002002B-page 487

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MSSP - Master Synchronous Serial Port Module

29.8

Register Summary: MSSP Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x018B

0x018C

0x018D

0x018E

0x018F

0x0190

0x0191

0x0192

0x0193

...

SSP1BUF

SSP1ADD

SSP1MSK

SSP1STAT

SSP1CON1

SSP1CON2

SSP1CON3

7:0

BUF[7:0]

ADD[7:0]

MSK[6:0]

P

MSK0

BF

SMP

WCOL

GCEN

ACKTIM

CKE

SSPOV

ACKSTAT

PCIE

D/A

S

R/W

SSPM[3:0]

UA

SSPEN

ACKDT

SCIE

CKP

ACKEN

BOEN

RCEN

PEN

RSEN

AHEN

SEN

SDAHT

SBCDE

DHEN

Reserved

0x0195

0x0196

0x0197

0x0198

0x0199

0x019A

0x019B

0x019C

SSP2BUF

SSP2ADD

SSP2MSK

SSP2STAT

SSP2CON1

SSP2CON2

SSP2CON3

7:0

BUF[7:0]

ADD[7:0]

MSK[6:0]

MSK0

BF

SMP

WCOL

GCEN

ACKTIM

CKE

SSPOV

ACKSTAT

PCIE

D/A

P

S

R/W

UA

SSPEN

ACKDT

SCIE

CKP

SSPM[3:0]

ACKEN

BOEN

RCEN

PEN

RSEN

AHEN

SEN

SDAHT

SBCDE

DHEN

29.9

Register Definitions: MSSP Control

DS40002002B-page 488

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MSSP - Master Synchronous Serial Port Module

29.9.1 SSPxBUF

Name:ꢀ

Offset:ꢀ

SSPxBUF

0x18C,0x196

MSSP Data Buffer Register

Bit

7

6

5

4

3

2

1

0

BUF[7:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 7:0 – BUF[7:0]ꢀMSSP Input and Output Data Buffer bits

DS40002002B-page 489

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MSSP - Master Synchronous Serial Port Module

29.9.2 SSPxADD

Name:ꢀ

Offset:ꢀ

SSPxADD

0x18D,0x197

MSSP Baud Rate Divider and Address Register

Bit

7

6

5

4

3

2

1

0

ADD[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – ADD[7:0]

•

SPI and I²C Master: Baud rate divider

I²C Slave: Address bits

Value

Mode

SPI and I²C Master

Description

11111111

-0000001

1

Baud rate divider. SCK/SCL pin clock period = ((n + 1) *4)/F_OSC. Values

less than 3 are not valid.

I²C 10-bit Slave MS

Address

Bits 7-3 and Bit 0 are not used and are don’t care. Bits 2:1 are bits 9:8 of

the 10-bit Slave Most Significant Address

xxxxx11x

-

xxxxx00x

11111111

-0000000

0

1111111x

-0000000

x

I²C 10-bit Slave LS

Address

Bits 7:0 of 10-Bit Slave Least Significant Address

I²C 7-bit Slave

Bit 0 is not used and is don’t care. Bits 7:1 are the 7-bit Slave Address

DS40002002B-page 490

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MSSP - Master Synchronous Serial Port Module

29.9.3 SSPxMSK

Name:ꢀ

Offset:ꢀ

SSPxMSK

0x18E,0x198

MSSP Address Mask Register

Bit

7

6

5

4

MSK[6:0]

R/W

3

2

1

0

MSK0

R/W

1

Access

Reset

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Bits 7:1 – MSK[6:0]ꢀMask bits

Value

1

0

Mode

Description

I²C Slave The received address bit n is compared to SSPxADD bit n to detect I²C address match

I²C Slave The received address bit n is not used to detect I²C address match

Bit 0 – MSK0

Mask bit for I²C 10-bit Slave mode

Value

1

Mode

Description

I²C 10-bit Slave The received address bit 0 is compared to SSPxADD bit 0 to detect I²C address

match

I²C 10-bit Slave The received address bit 0 is not used to detect I²C address match

SPI or I²C 7-bit Don’t care

0

x

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MSSP - Master Synchronous Serial Port Module

29.9.4 SSPxSTAT

Name:ꢀ

Offset:ꢀ

SSPxSTAT

0x18F,0x199

MSSP Status Register

Bit

7

6

5

D/A

RO

0

4

P

3

S

2

R/W

RO

0

1

UA

RO

0

BF

RO

0

SMP

R/W

0

CKE

R/W

0

Access

Reset

RO

0

RO

0

Bit 7 – SMPꢀSlew Rate Control bit

Value

Mode

Description

1

0

1

0

SPI Master

SPI Slave

I²C

Input data is sampled at the end of data output time

Input data is sampled at the middle of data output time

Keep this bit cleared in SPI Slave mode

Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz)

Slew rate control is enabled for High-Speed mode (400 kHz)

I²C

Bit 6 – CKE

SPI: Clock select bit⁽⁴⁾I²C: SMBus Select bit

Value

Mode

SPI

I²C

Description

1

0

1

0

Transmit occurs on the transition from active to Idle clock state

Transmit occurs on the transition from Idle to active clock state

Enables SMBus-specific inputs

I²C

Disables SMBus-specific inputs

Bit 5 – D/A

Data/Address bit

Value

Mode

Description

Reserved

SPI or I²C Master

x

1

0

I²C Slave

Indicates that the last byte received or transmitted was data

Indicates that the last byte received or transmitted was address

Bit 4 – P

Stop bit⁽¹⁾

Value

Mode

SPI

I²C

Description

Reserved

Stop bit was detected last

Stop bit was not detected last

x

1

0

Bit 3 – S

Start bit⁽¹⁾

Value

Mode

SPI

I²C

Description

Reserved

Start bit was detected last

Start bit was not detected last

x

1

0

Bit 2 – R/W

Read/Write Information bit^(2,3)

Value

Mode

SPI

I²C Slave

Description

Reserved

Read

x

1

0

Write

DS40002002B-page 492

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Value

1

0

Mode

I²C Master

Description

Transmit is in progress

Transmit is not in progress

Bit 1 – UAꢀUpdate Address bit (10-Bit Slave mode only)

Value

Mode

Description

x

1

0

All other modes Reserved

I²C 10-bit Slave Indicates that the user needs to update the address in the SSPxADD register

I²C 10-bit Slave Address does not need to be updated

Bit 0 – BF

Buffer Full Status bit⁽⁵⁾

Value

Mode

Description

I²C Transmit

Character written to SSPxBUF has not been sent

SSPxBUF is ready for next character

Received character in SSPxBUF has not been read

Received character in SSPxBUF has been read

1

0

1

0

I²C Transmit

SPI and I²C Receive

Note:ꢀ

1. This bit is cleared on Reset and when SSPEN is cleared.

2. In I²C Slave mode this bit holds the R/W bit information following the last address match. This bit is only valid

from the address match to the next Start bit, Stop bit or not ACK bit.

3. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

4. Polarity of clock state is set by the CKP bit.

5. I²C receive status does not include ACK and Stop bits.

DS40002002B-page 493

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

29.9.5 SSPxCON1

Name:ꢀ

Offset:ꢀ

SSPxCON1

0x190,0x19A

MSSP Control Register 1

Bit

7

6

5

SSPEN

R/W

0

4

3

2

1

0

WCOL

R/W/HS

0

SSPOV

R/W/HS

0

CKP

R/W

0

SSPM[3:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7 – WCOL

Write Collision Detect bit

Value

Mode

Description

1

SPI

A write to the SSPxBUF register was attempted while the previous byte was

still transmitting (must be cleared by software)

I²C Master transmit

I²C Slave transmit

A write to the SSPxBUF register was attempted while the I²C conditions

were not valid for a transmission to be started (must be cleared by software)

The SSPxBUF register is written while it is still transmitting the previous

word (must be cleared in software)

1

0

x

SPI or I²C Master or

Slave transmit

Master or Slave receive Don’t care

No collision

Bit 6 – SSPOV

Receive Overflow Indicator bit⁽¹⁾

Value

Mode

Description

1

SPI Slave

A byte is received while the SSPxBUF register is still holding the previous

byte. The user must read SSPxBUF, even if only transmitting data, to avoid

setting overflow. (must be cleared in software)

A byte is received while the SSPxBUF register is still holding the previous

byte (must be cleared in software)

I²C Receive

1

SPI Slave or I²C Receive No overflow

SPI Master or I²C Master Don’t care

transmit

0

x

Bit 5 – SSPEN

Master Synchronous Serial Port Enable bit.⁽²⁾

Value

Mode Description

1

SPI

Enables the serial port. The SCKx, SDOx, SDIx, and SSx pin selections must be made with the

PPS controls. Each signal must be configured with the corresponding TRIS control to the

direction appropriate for the mode selected.

Enables the serial port. The SDAx and SCLx pin selections must be made with the PPS

controls. Since both signals are bidirectional the PPS input pin and PPS output pin selections

must be made that specify the same pin. Both pins must be configured as inputs with the

corresponding TRIS controls.

I²C

1

0

All

Disables serial port and configures these pins as I/O PORT pins

Bit 4 – CKP

SCK Release Control bit

Value

Mode

Description

1

0

1

0

x

SPI

I²C Slave

I²C Master

Idle state for the clock is a high level

Idle state for the clock is a low level

Releases clock

Holds clock low (clock stretch), used to ensure data setup time

Unused in this mode

DS40002002B-page 494

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Bits 3:0 – SSPM[3:0]

Master Synchronous Serial Port Mode Select bits⁽⁴⁾

Value

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Description

I²C Slave mode: 10-bit address with Start and Stop bit interrupts enabled

I²C Slave mode: 7-bit address with Start and Stop bit interrupts enabled

Reserved - do not use

I²C Firmware Controlled Master mode (slave Idle)

SPI Master mode: Clock = F_OSC/(4*(SSPxADD+1)). SSPxADD must be greater than 0.⁽³⁾

Reserved - do not use

I²C Master mode: Clock = F_OSC/(4 * (SSPxADD + 1))

I²C Slave mode: 10-bit address

I²C Slave mode: 7-bit address

SPI Slave mode: Clock = SCKx pin. SSx pin control is disabled

SPI Slave mode: Clock = SCKx pin. SSx pin control is enabled

SPI Master mode: Clock = TMR2 output/2

SPI Master mode: Clock = Fosc/64

SPI Master mode: Clock = Fosc/16

SPI Master mode: Clock = Fosc/4

Note:ꢀ

1. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to

the SSPxBUF register.

2. When enabled, these pins must be properly configured as inputs or outputs.

3. SSPxADD = 0is not supported.

4. Bit combinations not specifically listed here are either reserved or implemented in I²C mode only.

DS40002002B-page 495

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

29.9.6 SSPxCON2

Name:ꢀ

Offset:ꢀ

SSPxCON2

0x191,0x19B

Control Register for I²C Operation Only

MSSP Control Register 2

Bit

7

GCEN

R/W

0

6

5

ACKDT

R/W

0

4

ACKEN

R/W

0

3

RCEN

R/W

0

2

1

RSEN

R/W

0

ACKSTAT

R/W/HC

0

PEN

R/W

0

SEN

R/W

0

Access

Reset

Bit 7 – GCEN

General Call Enable bit (Slave mode only)

Value

Mode

Description

x

1

0

Master mode

Slave mode

Don’t care

General call is enabled

General call is not enabled

Bit 6 – ACKSTATꢀAcknowledge Status bit (Master Transmit mode only)

Value

Description

1

0

Acknowledge was not received from slave

Acknowledge was received from slave

Bit 5 – ACKDT

Acknowledge Data bit (Master Receive mode only)⁽¹⁾

Value

Description

1

0

Not Acknowledge

Acknowledge

Bit 4 – ACKEN

Acknowledge Sequence Enable bit⁽²⁾

Value

Description

1

Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;

automatically cleared by hardware

0

Acknowledge sequence is Idle

Bit 3 – RCEN

Receive Enable bit (Master Receive mode only)⁽²⁾

Value

1

0

Description

Enables Receive mode for I²C

Receive is Idle

Bit 2 – PEN

Stop Condition Enable bit (Master mode only)⁽²⁾

Value

Description

1

0

Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware

Stop condition is Idle

Bit 1 – RSEN

Repeated Start Condition Enable bit (Master mode only)⁽²⁾

Value

Description

1

0

Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware

Repeated Start condition is Idle

DS40002002B-page 496

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Bit 0 – SEN

Start Condition Enable bit (Master mode only)⁽²⁾

Value

Description

1

0

Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware

Start condition is Idle

Note:ꢀ

1. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

2. If the I²C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or

writes to the SSPxBUF are disabled).

DS40002002B-page 497

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

29.9.7 SSPxCON3

Name:ꢀ

Offset:ꢀ

SSPxCON3

0x192,0x19C

MSSP Control Register 3

Bit

7

6

PCIE

R/W

0

5

SCIE

R/W

0

4

BOEN

R/W

0

3

SDAHT

R/W

0

2

SBCDE

R/W

0

1

AHEN

R/W

0

DHEN

R/W

0

ACKTIM

R/HS/HC

0

Access

Reset

Bit 7 – ACKTIMꢀAcknowledge Time Status bit

Unused in Master mode.

Value

x

1

Mode

Description

This bit is not used

SPI or I²C Master

I²C Slave and AHEN = 1or DHEN = Eighth falling edge of SCL has occurred and the ACK/NACK

1

state is active

I²C Slave

ACK/NACK state is not active. Transitions low on ninth rising

edge of SCL.

0

Bit 6 – PCIE

Stop Condition Interrupt Enable bit⁽¹⁾

Value

Mode

Description

x

1

0

SPI or SSPM = 1111or 0111

SSPM ≠ 1111and SSPM ≠ 0111

Don’t care

Enable interrupt on detection of Stop condition

Stop detection interrupts are disabled

Bit 5 – SCIEꢀStart Condition Interrupt Enable bit

Value

Mode

Description

x

1

0

SPI or SSPM = 1111or 0111

SSPM ≠ 1111and SSPM ≠ 0111

Don’t care

Enable interrupt on detection of Start condition

Start detection interrupts are disabled

Bit 4 – BOEN

Buffer Overwrite Enable bit⁽²⁾

Value

Mode Description

1

0

1

SPI

I²C

SSPxBUF is updated every time a new data byte is available, ignoring the BF bit

If a new byte is receive with BF set then SSPOV is set and SSPxBUF is not updated

SSPxBUF is updated every time a new data byte is available, ignoring the SSPOV effect on

updating the buffer

I²C

SSPxBUF is only updated when SSPOV is clear

0

Bit 3 – SDAHTꢀSDA Hold Time Selection bit

Value

Mode

SPI

I²C

Description

Not used in SPI mode

Minimum of 300 ns hold time on SDA after the falling edge of SCL

Minimum of 100 ns hold time on SDA after the falling edge of SCL

x

1

0

Bit 2 – SBCDEꢀSlave Mode Bus Collision Detect Enable bit

Unused in Master mode.

Value

Mode

Description

Don’t care

Collision detection is enabled

Collision detection is not enabled

SPI or I²C Master

I²C Slave

x

1

0

I²C Slave

DS40002002B-page 498

Datasheet

PIC16(L)F18425/45

MSSP - Master Synchronous Serial Port Module

Bit 1 – AHENꢀAddress Hold Enable bit

Value

x

Mode

Description

SPI or I²C Master Don’t care

I²C Slave

Address hold is enabled. As a result CKP is cleared after the eighth falling SCL

edge of an address byte reception. Software must set the CKP bit to resume

operation.

1

0

Address hold is not enabled

Bit 0 – DHENꢀData Hold Enable bit

Value

x

Mode

Description

SPI or I²C Master Don’t care

I²C Slave

Data hold is enabled. As a result CKP is cleared after the eighth falling SCL edge of

a data byte reception. Software must set the CKP bit to resume operation.

Data hold is not enabled

1

0

Note:ꢀ

1. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

2. For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set

when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.

DS40002002B-page 499

Datasheet

PIC16(L)F18425/45

FVR - Fixed Voltage Reference

30.

FVR - Fixed Voltage Reference

The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of V_DD, with the following selectable

output levels:

•

1.024V

2.048V

4.096V

The output of the FVR can be configured to supply a reference voltage to the following:

•

ADC input channel

ADC positive reference

Comparator input

Digital-to-Analog Converter (DAC)

The FVR can be enabled by setting the FVREN bit of the FVRCON register.

Important:ꢀ Fixed Voltage Reference output cannot exceed V_DD

.

Related Links

30.4.1 FVRCON

30.1

Independent Gain Amplifiers

The output of the FVR, which is connected to the ADC, Comparators, and DAC, is routed through two independent

programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three

possible voltage levels.

The ADFVR[1:0] bits of the FVRCON register are used to enable and configure the gain amplifier settings for the

reference supplied to the ADC module.

The CDAFVR[1:0] bits of the FVRCON register are used to enable and configure the gain amplifier settings for the

reference supplied to the DAC and comparator module.

Related Links

32. ADC2 - Analog-to-Digital Converter

34. CMP - Comparator Module

33. DAC - 5-Bit Digital-to-Analog Converter

30.2

FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to

stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set.

DS40002002B-page 500

Datasheet

PIC16(L)F18425/45

FVR - Fixed Voltage Reference

Figure 30-1.ꢀVoltage Reference Block Diagram

Rev. 10-000 053C

12/9/201 3

2

ADFVR[1:0]

1x

2x

4x

FVR_buffer1

(To ADC Module)

2

CDAFVR[1:0]

FVR_buffer2

(To Comparators

and DAC)

1x

2x

4x

FVREN

+

_

FVRRDY (Note 1)

Note 1

Note:ꢀ

1. Any peripheral requiring the fixed reference.

DS40002002B-page 501

Datasheet

PIC16(L)F18425/45

FVR - Fixed Voltage Reference

30.3

Register Summary - FVR

Offset

Name

Bit Pos.

0x00

...

Reserved

FVRCON

0x090B

0x090C

7:0

FVREN

FVRRDY

TSEN

TSRNG

CDAFVR[1:0]

ADFVR[1:0]

30.4

Register Definitions: FVR Control

DS40002002B-page 502

Datasheet

PIC16(L)F18425/45

FVR - Fixed Voltage Reference

30.4.1 FVRCON

Name:ꢀ

Offset:ꢀ

FVRCON

0x90C

Fixed Voltage Reference Control Register

Bit

7

FVREN

R/W

0

6

5

TSEN

R/W

0

4

TSRNG

R/W

0

3

2

1

0

FVRRDY

CDAFVR[1:0]

ADFVR[1:0]

Access

Reset

R

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7 – FVRENꢀFixed Voltage Reference Enable bit

Value

Description

1

0

Fixed Voltage Reference is enabled

Fixed Voltage Reference is disabled

Bit 6 – FVRRDYꢀFixed Voltage Reference Ready Flag bit (3)

Value

Description

1

Fixed Voltage Reference output is ready for use

0

Fixed Voltage Reference output is not ready or not enabled

Bit 5 – TSENꢀ Temperature Indicator Enable bit(2)

Value

Description

1

0

Temperature Indicator is enabled

Temperature Indicator is disabled

Bit 4 – TSRNGꢀTemperature Indicator Range Selection bit(2)

Value

Description

1

0

V_OUT= V_DD- 4 V_T(High Range)

V_OUT= V_DD- 2 V_T(Low Range)

Bits 3:2 – CDAFVR[1:0]ꢀComparator FVR Buffer Gain Selection bits

Value

11

10

01

00

Description

Comparator FVR Buffer Gain is 4x, (4.096V)⁽¹⁾

Comparator FVR Buffer Gain is 2x, (2.048V)⁽¹⁾

Comparator FVR Buffer Gain is 1x, (1.024V)

Comparator FVR Buffer is off

Bits 1:0 – ADFVR[1:0]ꢀADC FVR Buffer Gain Selection bit

Value

11

10

01

00

Description

ADC FVR Buffer Gain is 4x, (4.096V)⁽¹⁾

ADC FVR Buffer Gain is 2x, (2.048V)⁽¹⁾

ADC FVR Buffer Gain is 1x, (1.024V)

ADC FVR Buffer is off

Note:ꢀ

1. Fixed Voltage Reference output cannot exceed V_DD

.

2. See “Temperature Indicator Module” section for additional information.

3. FVRRDY is always ‘1’.

Related Links

31. Temperature Indicator Module

DS40002002B-page 503

Datasheet

PIC16(L)F18425/45

Temperature Indicator Module

31.

Temperature Indicator Module

This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the

silicon die.

The circuit’s range of operating temperature falls between -40°C and +125°C. The output is a voltage that is

proportional to the device temperature. The output of the temperature indicator is internally connected to the device

ADC.

The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on

the level of calibration performed. A one point calibration allows the circuit to indicate a temperature closely

surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more

accurately.

Reference Application Note AN2092, “Using the Temperature Indicator Module” (DS00002092) for more details

regarding the calibration process.

31.1

Module Operation

The figure below shows a simplified block diagram of the temperature circuit. The proportional voltage output is

achieved by measuring the forward voltage drop across multiple silicon junctions.

The following equation describes the output characteristics of the temperature indicator.

Equation 31-1.ꢀV_OUTRanges

ꢕꢅꢗℎ ꢉꢏꢛꢗꢃ: ꢑ

= ꢑ − 4ꢑ

ꢙꢙ ꢈ

ꢊꢮꢈ

ꢖꢆꢭ ꢉꢏꢛꢗꢃ:ꢑ

= ꢑ − 2ꢑ

ꢙꢙ ꢈ

ꢊꢮꢈ

The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See “Fixed Voltage

Reference (FVR)” section for more information.

The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current.

The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON

register, provides a wider output voltage. This provides more resolution over the temperature range. This range

requires a higher bias voltage to operate and thus, a higher V_DDis needed.

The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower

voltage drop and thus, a lower V_DDvoltage is needed to operate the circuit. The low range is provided for low voltage

operation.

DS40002002B-page 504

Datasheet

PIC16(L)F18425/45

Temperature Indicator Module

Figure 31-1.ꢀTemperature Circuit Block Diagram

VDD

TSEN

TSRNG

VOUT

To ADC

Temp. Indicator

Related Links

30. FVR - Fixed Voltage Reference

31.3 Temperature Indicator Range

32. ADC2 - Analog-to-Digital Converter

31.2

Minimum Operating V_DD

When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is

within specifications. When the temperature circuit is operated in high range, the device operating voltage, V_DD, must

be high enough to ensure that the temperature circuit is correctly biased.

The following table shows the recommended minimum V_DDvs. range setting.

Table 31-1.ꢀRecommended V_DDvs. Range

Min. V_DD, TSRNG = 1 (High Range)

Min. V_DD, TSRNG = 0 (Low Range)

≥3.6V

≥1.8V

31.3

Temperature Indicator Range

The temperature indicator circuit operates in either High or Low range. The High range, selected by setting the

TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the

temperature range. High range requires a higher-bias voltage to operate and thus, a higher V_DDis needed. The Low

range is selected by clearing the TSRNG bit of the FVRCON register. The Low range generates a lower sensor

voltage and thus, a lower V_DDvoltage is needed to operate the circuit.

The output voltage of the sensor is the highest value at -40°C and the lowest value at +125°C.

•

High Range: The High range is used in applications with the reference for the ADC, V_REF= 2.048V. This range

may not be suitable for battery-powered applications. The ADC reading (in counts) at 90°C for the high range

setting is stored in the DIA Table as parameter TSHR2.

•

Low Range: This mode is useful in applications in which the V_DDis too low for high-range operation. The V_DDin

this mode can be as low as 1.8V. V_DDmust, however, be at least 0.5V higher than the maximum sensor voltage

depending on the expected low operating temperature. The ADC reading (in counts) at 90°C for the low range

setting is stored in the DIA Table as parameter TSLR2.

DS40002002B-page 505

Datasheet

PIC16(L)F18425/45

Temperature Indicator Module

31.4

Estimation of Temperature

This section describes the steps involved in estimating the die temperature, T_MEAS

1. Obtain the ADC count value of the measured analog voltage: The analog output voltage, V_MEASis converted to

a digital count value by the Analog-to-Digital Converter (ADC) and is referred to as ADC_MEAS

:

.

2. Obtain the ADC count value, ADC_DIAat 90°C, from the DIA Table. This parameter is TSLR2 for the low range

setting or TSHR2 for the high range setting of the temperature indicator module.

3. Obtain the output analog voltage (in mV) value of the Fixed Reference Voltage (FVR) for 2x setting, from the

DIA table. This parameter is referred to as FVRA2X in the DIA Table.

4. Obtain the value of the temperature indicator voltage sensitivity, parameter Mv, from the “Electrical

Specifications” section.

The following equation provides an estimate of the die temperature based on the above parameters:

Equation 31-2.ꢀSensor Temperature

ꢞꢙꢌ

− ꢞꢙꢌ

× ꢢꢑꢉꢞ2ꢥ

ꢙꢡꢞ

ꢂꢝꢞꢋ

ꢈ

= 90 +

ꢂꢝꢞꢋ

ꢠ

2

− 1 × ꢂꢘ

Note:ꢀ Where:

ADC_MEAS= ADC reading at temperature being estimated

ADC_DIA= ADC reading stored in the DIA

FVRA2X = FVR value stored in the DIA for 2x setting

N = Resolution of the ADC

Mv = Temperature Indicator voltage sensitivity (mV/°C)

Note:ꢀ It is recommended to take the average of ten measurements of ADC_MEASto reduce noise and improve

accuracy.

Related Links

40.4.6 Temperature Indicator Requirements

31.4.1 Calibration

31.4.1.1 Higher-Order Calibration

If the application requires more precise temperature measurement, additional calibrations steps will be necessary.

For these applications, two-point or three-point calibration is recommended. An Application Note will be released in

future that demonstrates higher-order calibration process. An Application Note that demonstrates higher-order

calibration process will be released in the future.

31.4.2 Temperature Resolution

The resolution of the ADC reading, Ma (°C/count), depends on both the ADC resolution N and the reference voltage

used for conversion, as shown in the equation below. It is recommended to use the smallest V_REFvalue, such as the

ADC FVR1 Output Voltage for 2x setting (FVRA2X) value from the DIA Table.

Related Links

40.4.11 Fixed Voltage Reference (FVR) Specifications

31.5

ADC Acquisition Time

To ensure accurate temperature measurements, the user must wait at least 200 ms after the ADC input multiplexer is

connected to the temperature indicator output before the conversion is performed.

DS40002002B-page 506

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.

ADC²- Analog-to-Digital Converter

The Analog-to-Digital Converter with Computation (ADC²) allows conversion of an analog input signal to a 12-bit

binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a

12-bit binary result via successive approximation and stores the conversion result into the ADC result registers

(ADRESH:ADRESL register pair).

Additionally, the following features are provided within the ADC module:

•

13-bit Acquisition Timer

Hardware Capacitive Voltage Divider (CVD) Support:

– 13-bit precharge timer

– Adjustable sample and hold capacitor array

– Guard ring digital output drive

Automatic Repeat and Sequencing:

– Automated double sample conversion for CVD

– Two sets of result registers (Result and Previous result)

– Auto-conversion trigger

•

– Internal retrigger

Computation Features:

– Averaging and low-pass filter functions

– Reference comparison

– 2-level threshold comparison

– Selectable interrupts

The figure below shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of a conversion and upon threshold comparison. These

interrupts can be used to wake-up the device from Sleep.

DS40002002B-page 507

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

Figure 32-1.ꢀADC²Block Diagram

PREF[1:0]

Rev. 10-000034D

11/2/2016

FVR_buffer1

11

10

01

00

Positive

Reference

Select

VREF+ pin

Reserved

NREF

VDD

VREF- pin

VSS

1

0

CS

AN0

ANa

Vref- Vref+

External

Channel

Inputs

.

Fosc

Divider

FOSC/n

FOSC

FRC

ADC

Clock

Select

ADC_clk

ANz

sampled

input

FRC

VSS

Temp Indicator

DACx_output

FVR_buffer

Internal

Channel

Inputs

ADC CLOCK SOURCE

ADC

Sample Circuit

PCH[5:0]

ADFM

set bit ADIF

12

complete

start

12-bit Result

16

Write to bit

GO/DONE

ADRESH

ADRESL

Enable

Trigger Select

ACT[4:0]

ADON

. . .

VSS

Trigger Sources

AUTO CONVERSION

TRIGGER

32.1

ADC Configuration

When configuring and using the ADC the following functions must be considered:

•

Port Configuration

Channel Selection

ADC Voltage Reference Selection

ADC Conversion Clock Source

Interrupt Control

Result Formatting

Conversion Trigger Selection

DS40002002B-page 508

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

•

ADC Acquisition Time

ADC Precharge Time

Additional Sample-and-Hold Capacitor

Single/Double Sample Conversion

Guard Ring Outputs

32.1.1 Port Configuration

The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should

be configured for analog by setting the associated TRIS and ANSEL bits. Refer to the “I/O Ports” section for more

information.

Important:ꢀ Analog voltages on any pin that is defined as a digital input may cause the input buffer to

conduct excess current.

Related Links

14. I/O Ports

32.1.2 Channel Selection

The ADPCH register determines which channel is connected to the sample and hold circuit for conversion. When

changing channels, a delay is required before starting the next conversion. Refer to the 32.2 ADC Operation section

for more information.

The channel selections available using PCH bits in ADPCH register.

Related Links

32.2 ADC Operation

30. FVR - Fixed Voltage Reference

31. Temperature Indicator Module

33. DAC - 5-Bit Digital-to-Analog Converter

32.1.3 ADC Voltage Reference

The PREF bits provide control of the positive voltage reference. The positive voltage reference can be:

•

V_REF+ pin

V_DD

FVR 1.024V

FVR 2.048V

FVR 4.096V

The NREF bit provides control of the negative voltage reference. The negative voltage reference can be:

•

V_REF- pin

V_SS

Related Links

30. FVR - Fixed Voltage Reference

32.8.20 ADREF

32.1.4 Conversion Clock

The source of the conversion clock is software selectable using CS bit in the ADCON0 register. If F_OSCis selected as

the ADC clock (CS = 0), a prescaler can be used to divide the input clock in order to meet the ADC clock period

specification. The prescaler options are available via ADCLK register.

The available ADC clock source options are the following:

•

CS = 0: F_OSC/2*(n+1) , where ‘n’ is from 0 to 127

DS40002002B-page 509

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

•

CS = 1: F_RC(dedicated RC oscillator)

The time to complete one bit conversion is defined as the T_AD. The following figure shows the complete timing details

of the ADC conversion.

Figure 32-2.ꢀAnalog-to-Digital Conversion T_ADCycles

Rev. 10-000035C

11/2/2016

Precharge

Time

1-8191 TCY

(TPRE)

Acquisition/

Sharing Time

1-8191 TCY

(TACQ)

Conversion Time

(Traditional Timing of ADC Conversion)

TCY TCY-TAD

TAD1

TAD3

TAD5

TAD7

TAD11TAD12TAD13 2TCY

TAD8 TAD9 TAD10

TAD2

TAD4

TAD6

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2

b1 b0

TAD11

Conversion starts

External and Internal External and Internal

Channels are Channels share

charged/discharged charge

Holding capacitor CHOLD is disconnected from analog input (typically 100ns)

If ADPRE = 0

If ADPRE ≠ 0

If ADACQ ≠ 0

If ADACQ = 0

(Traditional Operation Start)

On the following cycle:

ADRESH:ADRESL is loaded,

GO bit is cleared,

Set GO bit

ADIF bit is set,

For correct conversion, the appropriate T_ADspecification must be met. Access the “ADC Timing Specifications”

section for more information. The following table below gives examples of appropriate ADC clock selections.

Important:ꢀ

1. Unless using the F_RC, any changes in the system clock frequency will change the ADC clock

frequency, which may adversely affect the ADC result.

2. The internal control logic of the ADC runs off of the clock selected by the CS bit. What this can

mean is when the CS is set to ‘1’ (ADC runs on FRC), there may be unexpected delays in operation

when setting ADC control bits.

Table 32-1.ꢀADC Clock Period (T_AD) Vs. Device Operating Frequencies^(1,4)

ADC Clock Period (T

)

Device Frequency (F

)

OSC

AD

ADC

Clock

Source

ADCLK

64 MHz

32 MHz

20 MHz

16 MHz

8 MHz

4 MHz

1 MHz

F

CS(ADCON0[4]) = 1

1.0-6.0 μs

4.0 μs

...

1.0-6.0 μs

6.4 μs

...

1.0-6.0 μs

8.0 μs

...

1.0-6.0 μs

RC

(3)

128.0 μs

111111

/128

2.0 μs

...

16.0 μs

32.0 μs

OSC

...

(2)

(3)

000100

000011

000010

000001

000000

F

/10

/8

250 ns

500 ns

800 ns

1.0 μs

500 ns

2.0 μs

1.0 μs

750 ns

500 ns

4.0 μs

2.0 μs

1.5 μs

1.0 μs

500 ns

16.0 μs

8.0 μs

6.0 μs

4.0 μs

2.0 μs

OSC

(2)

125 ns

250 ns

400 ns

(2)

/6

93.75 ns

187.5 ns

300 ns

375 ns

(2)

/4

62.5 ns

125 ns

200 ns

250 ns

(2)

/2

31.25 ns

62.5 ns

100 ns

125 ns

250 ns

DS40002002B-page 510

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

...........continued

ADC Clock Period (T

)

Device Frequency (F

)

OSC

AD

ADC

Clock

Source

ADCLK

64 MHz

32 MHz

20 MHz

16 MHz

8 MHz

4 MHz

1 MHz

Note:ꢀ

1.

2.

3.

4.

See T

parameter in the “Electrical Specifications” section for F

source typical T

value.

AD

RC

These values violate the required T

time.

AD

time.

Outside the recommended T

AD

The ADC clock period (T ) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock

AD

oscillator source must be used when conversions are to be performed with the device in Sleep mode.

F

. However, the F

OSC

RC

Related Links

32.8.15 ADCON0

40.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications

40. Electrical Specifications

32.1.5 Interrupts

The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion.

The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1

register. The ADIF bit must be cleared in software.

Important:ꢀ

1. The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC

interrupt is enabled.

2. The ADC operates during Sleep only when the FRC oscillator is selected.

This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt

will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEPinstruction is always

executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the ADIE bit and the

PEIE bit of the INTCON register must both be set and the GIE bit of the INTCON register must be cleared. If all three

of these bits are set, the execution will switch to the Interrupt Service Routine.

32.1.6 Result Formatting

The 12-bit ADC conversion result can be supplied in two formats, left justified or right justified. The FRM bit controls

the output format.

The figure below shows the two output formats.

Writes to the ADRES register pair are always right justified regardless of the selected format mode. Therefore, data

read after writing to ADRES when FRM = 0will be shifted left four places.

DS40002002B-page 511

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

Figure 32-3.ꢀ12-Bit ADC Conversion Result Format

Rev. 30-000116B

6/27/2017

ADRESH

ADRESL

(ADFRM = 0)

MSB

bit 7

bit 0

bit 7

LSB

bit 0

12-bit ADC Result

Unimplemented:

Read as ‘0’

(ADFRM = 1)

MSB

LSB

bit 0

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

12-bit ADC Result

32.2

ADC Operation

32.2.1 Starting a Conversion

To enable the ADC module, the ON bit in the ADCON0 register must be set to a ‘1’. A conversion may be started by

any of the following:

•

Software setting the GO bit to ‘1’

An external trigger (source selected by 32.8.21 ADACT)

A continuous-mode retrigger (see “Continuous Sampling mode” section.)

.

Important:ꢀ The GO bit should not be set in the same instruction that turns on the ADC.

Related Links

32.2.7 ADC Conversion Procedure (Basic Mode)

32.6.8 Continuous Sampling Mode

32.8.15 ADCON0

32.8.17 ADCON2

32.2.2 Completion of a Conversion

When any individual conversion is complete, the value already in ADRES is written into ADPREV (if PSIS = 1) and

the new conversion result appears in ADRES. When the conversion completes, the ADC module will:

•

Clear the GO bit (unless the CONT bit is set)

Set the ADIF Interrupt Flag bit

Set the MATH bit in the ADSTAT register

Update ADACC

When DSEN = 0then after every conversion, or when DSEN = 1then after every other conversion, the following

events occur:

•

ADERR is calculated

ADTIF interrupt is set if ADERR calculation meets threshold comparison

Importantly, filter and threshold computations occur after the conversion itself is complete. As such, interrupt handlers

responding to ADIF should check ADTIF before reading filter and threshold results.

DS40002002B-page 512

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ADC2 - Analog-to-Digital Converter

32.2.3 Terminating a Conversion

If a conversion must be terminated before completion, the GO bit can be cleared in software. The ADRESH and

ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits

will match the last bit converted. In this case, filter and/or threshold occur.

Important:ꢀ A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off

and any pending conversion is terminated.

32.2.4 ADC Operation During Sleep

The ADC module can operate during Sleep. This requires the ADC clock source to be set to internal RC oscillator

(CS bit in the ADCON0 register is set to ‘1’). When the F_RCis selected as ADC clock source, the ADC waits one

additional instruction before starting the conversion. This allows the SLEEPinstruction to be executed, which can

reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when

the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion

completes, although the ON bit remains set.

32.2.5 External Trigger During Sleep

If the external trigger is received during Sleep while the ADC clock source is set to the FRC, the ADC module will

perform the conversion and set the ADIF bit upon completion.

If an external trigger is received when the ADC clock source is something other than FRC, the trigger will be

recorded, but the conversion will not begin until the device exits Sleep.

32.2.6 Auto-Conversion Trigger

The auto-conversion trigger allows periodic ADC measurements without software intervention. When a rising edge of

the selected source occurs, the GO bit is set by hardware.

The auto-conversion trigger source is selected by the ACT bits in the ADACT register.

Using the Auto-conversion Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the

ADC timing requirements are met. See ADC Auto-Conversion Trigger Sources table for auto-conversion sources.

32.2.7 ADC Conversion Procedure (Basic Mode)

This is an example procedure for using the ADC to perform an Analog-to-Digital conversion:

1. Configure Port:

1.1.

1.2.

Disable pin output driver (Refer to the TRISx register)

Configure pin as analog (Refer to the ANSELx register)

2. Configure the ADC module:

2.1.

2.2.

2.3.

2.4.

Select ADC conversion clock

Configure voltage reference

Select ADC input channel (precharge+acquisition)

Turn on ADC module

3. Configure ADC interrupt (optional):

3.1.

3.2.

3.3.

3.4.

Clear ADC interrupt flag

Enable ADC interrupt

Enable peripheral interrupt (PIE bit)

Enable global interrupt (GIE bit) (see Note 1 below)

4. If ADACQ = 0, software must wait the required acquisition time (see Note 2 below).

5. Start conversion by setting the GO bit.

6. Wait for ADC conversion to complete by one of the following:

6.1.

Polling the GO bit

DS40002002B-page 513

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ADC2 - Analog-to-Digital Converter

6.2.

6.3.

Polling the ADIF bit

Waiting for the ADC interrupt (interrupts enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt is enabled).

Important:ꢀ

1. The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-

line code execution.

2. Refer to the “ADC Acquisition Requirements” section.

Example 32-1.ꢀADC Conversion (assembly)

; This code block configures the ADC for polling, V_DDand V_SSreferences,

; F_RCoscillator, and AN0 input.

; Conversion start & polling for completion are included.

;

BANKSEL ADCON1

;

movlw

movwf

B’11110000’ ;Right justify, FRC oscillator

ADCON1

;Vdd and Vss Vref

BANKSEL TRISA

;

bsf

TRISA,0

;Set RA0 to input

BANKSEL ANSEL

;

bsf

ANSEL,0

;Set RA0 to analog

;

BANKSEL ADCON0

movlw

movwf

call

bsf

btfsc

goto

BANKSEL ADRESH

movf

movwf

movf

movwf

B’00000001’ ;Select channel AN0

ADCON0 ;Turn ADC On

SampleTime ;Acquisiton delay

ADCON0,ADGO ;Start conversion

ADCON0,ADGO ;Is conversion done?

$-1

;No, test again

;

ADRESH,W

RESULTHI

ADRESL,W

RESULTLO

;Read upper 2 bits

;store in GPR space

;Read lower 8 bits

;Store in GPR space

Example 32-2.ꢀADC Conversion (C)

/*This code block configures the ADC for polling, V_DDand V_SSreferences,F_RC

oscillator and AN0 input.

Conversion start & polling for completion are included.

*/

void main() {

//System Initialize

initializeSystem();

//Setup ADC

ADCON0bits.FM = 1;

ADCON0bits.CS = 1;

ADPCH = 0x00;

//right justify

//FRC Clock

//RA0 is Analog channel

//Set RA0 to input

TRISAbits.TRISA0 = 1;

ANSELAbits.ANSELA0 = 1; //Set RA0 to analog

ADCON0bits.ON = 1;

//Turn ADC On

while (1) {

ADCON0bits.GO = 1;

//Start conversion

while (ADCON0bits.GO); //Wait for conversion done

resultHigh = ADRESH;

resultLow = ADRESL;

//Read result

}

Related Links

DS40002002B-page 514

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.3 ADC Acquisition Requirements

32.3

ADC Acquisition Requirements

For the ADC to meet its specified accuracy, the charge holding capacitor (C_HOLD) must be allowed to fully charge to

the input channel voltage level. The Analog Input model is shown in the following figure. The source impedance (R_S)

and the internal sampling switch (R_SS) impedance directly affect the time required to charge the capacitor C_HOLD. The

sampling switch (R_SS) impedance varies over the device voltage (V_DD), refer to the following figure.

Figure 32-4.ꢀAnalog Input Model

Rev. 30-000114B

6/27/2017

VDD

Analog

Input

Sampling

Switch

VT  0.6V

SS

RIC  1k

Rss

Rs

(1)

CPIN

5 pF

VA

I LEAKAGE

C^HOLD= 28 pF

Ref-

V^T 0.6V

6V

5V

RSS

V^DD4V

3V

Legend:

C^HOLD

CPIN

= Sample/Hold Capacitance

= Input Capacitance

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

5 6 7 8 9 1011

Sampling Switch

RIC

RSS

SS

VT

= Interconnect Resistance

= Resistance of Sampling Switch

= Sampling Switch

(kOhm)

= Threshold Voltage

Note:ꢀ

1. Refer to “I/O Ports Electrical Specifications”.

Important:ꢀ The maximum recommended impedance for analog sources is 10 kΩ.

If the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is

selected (or changed), an ADC acquisition must be completed before the conversion can be started. To calculate the

minimum acquisition time, the following equation may be used. This equation assumes that 1/2 LSb error is used

(4,096 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified

resolution.

Equation 32-1.ꢀAcquisition Time Example

Assumptions: Temperature = 50°C and external impedance pf 10 kΩ 5.0V V_DD

T_ACQ= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= T_AMP+ T_C+ T_COFF

= 2 μs + T_C+ [(Temperature - 25°C)(0.05 μs/°C)]

The value for T_Ccan be approximated with the following equations:

1

ꢛ + 1

ꢑ

1 −

= ꢑꢌꢕꢊꢖꢙ

;[1]ꢑ

charged to within 1/2 lsb

ꢞꢀꢀꢖꢡꢝꢙ

ꢌꢕꢊꢖꢙ

2

− 1

DS40002002B-page 515

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

−ꢈ

ꢌ

ꢑ

1 − ꢃ

= ꢑꢌꢕꢊꢖꢙ

;[2]ꢑ

charge response toꢑ

ꢉ

ꢞꢀꢀꢖꢡꢝꢙ

ꢌꢕꢊꢖꢙ ꢞꢀꢀꢖꢡꢝꢙ

ꢌ

−ꢈ

ꢌ

1

ꢑ

= ꢑꢞꢀꢀꢖꢡꢝꢙ 1 −

;combining [1] and [2]

ꢉ

ꢞꢀꢀꢖꢡꢝꢙ

ꢌ

ꢛ + 1

2

− 1

Note:ꢀ Where n = number of bits of the ADC.

Solving for T_C:

ꢈ = − ꢌ

ꢉ

+ ꢉ + ꢉ ln 1/8191

ꢌ

ꢕꢊꢖꢙ ꢡꢌ ꢋꢋ ꢋ

ꢈ = − 28ꢯꢢ 1ꢩΩ + 7ꢩΩ + 10ꢩΩ ln 0.0001221

ꢌ

ꢈ = 4.54ꢒꢍ

ꢌ

Therefore:

ꢈ

= 2ꢒꢍ + 4.54ꢒꢍ + 50°ꢌ − 25°ꢌ 0.05ꢒꢍ/°ꢌ

= 7.79ꢒꢍ

ꢞꢌꢰ

ꢈ

ꢞꢌꢰ

Note:ꢀ

1. The reference voltage (V_REF) has no effect on the equation, since it cancels itself out.

2. The charge holding capacitor (C_HOLD) is not discharged after each conversion.

3. The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage

specification.

Figure 32-5.ꢀADC Transfer Function

Rev. 30-000115B

6/27/2017

Full-Scale Range

FFFh

FFEh

FFDh

FFCh

FFBh

03h

02h

01h

00h

Analog Input Voltage

0.5 LSB

1.5 LSB

Zero-Scale

REF-

Full-Scale

Transition

REF+

Related Links

40.4.4 I/O and CLKOUT Timing Specifications

DS40002002B-page 516

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.4

ADC Charge Pump

The ADC module has a dedicated charge pump that can be controlled through the ADCPCON0 register. The primary

purpose of the charge pump is to supply a constant voltage to the gates of transistor devices in the A/D converter,

signal and reference input pass-gates, to prevent degradation of transistor performance at low operating voltage.

The charge pump can be enabled by setting the CPON bit. Once enabled, the pump will undergo a start-up time to

stabilize the charge pump output. Once the output stabilizes and is ready for use, the CPRDY bit will be set.

Related Links

32.8.23 ADCPCON0

32.5

Capacitive Voltage Divider (CVD) Features

The ADC module contains several features that allow the user to perform a relative capacitance measurement on any

ADC channel using the internal ADC sample and hold capacitance as a reference. This relative capacitance

measurement can be used to implement capacitive touch or proximity sensing applications. The following figure

shows the basic block diagram of the CVD portion of the ADC module.

Figure 32-6.ꢀHardware Capacitive Voltage Divider Block Diagram

Rev. 10-000322B

10/4/2017

VDD

ADPPOL & Precharge

ADC

Precharge

ANx

ADPPOL & Precharge

ANx

Multiplexer

ADCAP

Additional

Sample

Capacitors

32.5.1 CVD Operation

A CVD operation begins with the ADC’s internal Sample-and-Hold capacitor (C_HOLD) being disconnected from the

path which connects it to the external capacitive sensor node. While disconnected, C_HOLDis precharged to V_DDor

V_SSthe sensor node is also charged to V_SSor V_DD, respectively to the level opposite that of C_HOLD. When the

precharge phase is complete, the V_DD/V_SSbias paths for the two nodes are shut off and the paths between C_HOLD

and the external sensor node is reconnected, at which time the acquisition phase of the CVD operation begins.

During acquisition, a capacitive voltage divider is formed between the precharged C_HOLDand sensor nodes, which

results in a final voltage level setting on C_HOLDwhich is determined by the capacitances and precharge levels of the

two nodes. After acquisition, the ADC converts the voltage level on C_HOLD. This process is then repeated with the

selected precharge levels inverted for both the C_HOLDand the sensor nodes. The waveform for two CVD

measurements, which is known as differential CVD measurement, is shown in the following figure.

DS40002002B-page 517

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

Figure 32-7.ꢀDifferential CVD Measurement Waveform

Rev. 10-000335A

10/2/2017

Precharge

Acquire

Convert

Precharge

Acquire

Convert

VDD

VSS

Second Sample

First Sample

Time

32.5.2 Precharge Control

The Precharge stage is an optional period of time that brings the external channel and internal sample and hold

capacitor to known voltage levels. Precharge is enabled by writing a non-zero value to the ADPRE register. This

stage is initiated when an ADC conversion begins, either from setting the GO bit, a special event trigger, or a

conversion restart from the computation functionality. If the ADPRE register is cleared when an ADC conversion

begins, this stage is skipped.

During the precharge time, C_HOLDis disconnected from the outer portion of the sample path that leads to the external

capacitive sensor and is connected to either V_DDor V_SS, depending on the value of the PPOL bit. At the same time,

the port pin logic of the selected analog channel is overridden to drive a digital high or low out, in order to precharge

the outer portion of the ADC’s sample path, which includes the external sensor. The output polarity of this override is

also determined by the PPOL bit. The amount of time that this charging needs is controlled by the ADPRE register.

Important:ꢀ The external charging overrides the TRIS setting of the respective I/O pin. If there is a device

attached to this pin, Precharge should not be used.

Related Links

32.8.16 ADCON1

32.8.14 ADPRE

32.5.3 Acquisition Control for CVD

The Acquisition stage allows time for the voltage on the internal sample and hold capacitor to charge or discharge

from the selected analog channel. This acquisition time is controlled by the ADACQ register. If ADPRE = 0,

DS40002002B-page 518

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

acquisition starts at the beginning of conversion. When ADPRE ≠ 0, the acquisition stage begins when precharge

ends.

At the start of the acquisition stage, the port pin logic of the selected analog channel is overridden to turn off the

digital high/low output drivers so they do not affect the final result of the charge averaging. Also, the selected ADC

channel is connected to C_HOLD. This allows charge averaging to proceed between the precharged channel and the

C_HOLDcapacitor.

Important:ꢀ When ADPRE ≠ 0setting ADACQ to ‘0’ will set a maximum acquisition time (8191 ADC clock

cycles). When ADPRE = 0, setting ADACQ to ‘0’ will disable hardware acquisition time control.

32.5.4 Guard Ring Outputs

The following figure shows a typical guard ring circuit. C_GUARDrepresents the capacitance of the guard ring trace

placed on the PCB board. The user selects values for R_Aand R_Bthat will create a voltage profile on C_GUARD, which

will match the selected acquisition channel.

The purpose of the guard ring is to generate a signal in phase with the CVD sensing signal to minimize the effects of

the parasitic capacitance on sensing electrodes. It also can be used as a mutual drive for mutual capacitive sensing.

For more information about active guard and mutual drive, see Application Note AN1478, “mTouch^TMSensing

Solution Acquisition Methods Capacitive Voltage Divider”.

The ADC has two guard ring drive outputs, ADGRDA and ADGRDB. These outputs can be routed through PPS

controls to I/O pins (see “Peripheral Pin Select (PPS) Module” for details) and the polarity of these outputs are

controlled by the GPOL and IPEN bits.

At the start of the first precharge stage, both outputs are set to match the GPOL bit. Once the acquisition stage

begins, ADGRDA changes polarity, while ADGRDB remains unchanged. When performing a double sample

conversion, setting the IPEN bit causes both guard ring outputs to transition to the opposite polarity of GPOL at the

start of the second precharge stage, and ADGRDA toggles again for the second acquisition. For more information on

the timing of the guard ring output, refer to the two following figures.

DS40002002B-page 519

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

Figure 32-8.ꢀDifferential CVD with Guard Ring Output Waveform

Rev. 10-000336A

10/2/2017

Precharge

Acquire

Convert

Precharge

Acquire

Convert

VDD

VSS

Second Sample

First Sample

Time

ADGRDA

ADGRDB

Related Links

32.8.16 ADCON1

16. PPS - Peripheral Pin Select Module

32.5.5 Additional Sample and Hold Capacitance

Additional capacitance can be added in parallel with the internal sample and hold capacitor (C_HOLD) by using the

ADCAP register. This register selects a digitally programmable capacitance, which is added to the ADC conversion

bus, increasing the effective internal capacitance of the sample and hold capacitor in the ADC module. This is used

to improve the match between internal and external capacitance for a better sensing performance. The additional

capacitance does not affect analog performance of the ADC because it is not connected during conversion.

Related Links

32.6 Computation Operation

32.8.13 ADCAP

32.6

Computation Operation

The ADC module hardware is equipped with post conversion computation features. These features provide data

post-processing functions that can be applied to the ADC conversion result, including digital filtering/averaging and

threshold comparison functions.

DS40002002B-page 520

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

Figure 32-9.ꢀComputational Features Simplified Block Diagram

Rev. 10-000260B

8/4/2015

ADCALC[2:0]

ADMD[2:0]

ADRES

ADFILT

Set

Threshold

Error

Interrupt

Calculation

Average/

Logic

ADERR

Flag

1

Filter

ADPREV

0

ADSTPT

ADUTHR

ADLTHR

ADPSIS

The operation of the ADC computational features is controlled by MD bits.

The module can be operated in one of five modes:

•

Basic: This is a legacy mode. In this mode, ADC conversion occurs on single (DSEN = 0) or double (DSEN = 1)

samples. ADIF is set after all the conversions are complete.

Accumulate: With each trigger, the ADC conversion result is added to accumulator and ADCNT increments.

ADIF is set after each conversion. ADTIF is set according to the calculation mode.

Average: With each trigger, the ADC conversion result is added to the accumulator. When the ADRPT number

of samples have been accumulated, a threshold test is performed. Upon the next trigger, the accumulator is

cleared. For the subsequent tests, additional ADRPT samples are required to be accumulated.

•

Burst Average: At the trigger, the accumulator is cleared. The ADC conversion results are then collected

repetitively until ADRPT samples are accumulated and finally the threshold is tested.

Low-Pass Filter (LPF): With each trigger, the ADC conversion result is sent through a filter. When ADRPT

samples have occurred, a threshold test is performed. Every trigger after that, the ADC conversion result is sent

through the filter and another threshold test is performed.

The five modes are summarized in following table.

DS40002002B-page 521

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.6.1 Digital Filter/Average

The digital filter/average module consists of an accumulator with data feedback options, and control logic to

determine when threshold tests need to be applied. The accumulator is a 16-bit wide register that can be accessed

through the ADACCH:ADACCL register pair.

Upon each trigger event (the GO bit set or external event trigger), the ADC conversion result is added to the

accumulator. If the accumulated result exceeds 2^{(accumulator_width)}-1, the OV Accumulator Overflow bit is set.

The number of samples to be accumulated is determined by the ADRPT (A/D Repeat Setting) register. Each time a

sample is added to the accumulator, the ADCNT register is incremented. Once ADRPT samples are accumulated

(ADCNT = ADRPT), an accumulator clear command can be issued by the software by setting the ACLR bit. Setting

the ACLR bit will also clear the OV bit, as well as the ADCNT register. The ACLR bit is cleared by the hardware when

accumulator clearing action is complete.

Important:ꢀ When ADC is operating from FRC, five FRC clock cycles are required to execute the ADACC

clearing operation.

The CRS bits control the data shift on the accumulator result, which effectively divides the value in accumulator

(ADACCU:ADACCH:ADACCL) register pair. For the Accumulate mode of the digital filter, the shift provides a simple

scaling operation. For the Average/Burst Average mode, the Shift bits are used to determine the number of logical

right shifts to be performed on the accumulated result. For the Low-pass Filter mode, the shift is an integral part of

the filter, and determines the cut-off frequency of the filter. The table below shows the -3 dB cut-off frequency in ωT

(radians) and the highest signal attenuation obtained by this filter at nyquist frequency (ωT = π).

Table 32-3.ꢀLow-pass Filter -3 dB Cut-off Frequency

CRS

ωT (radians) @ -3 dB Frequency

dB @ F_nyquist=1/(2T)

1

2

3

4

5

6

7

0.72

0.284

0.134

0.065

0.032

0.016

0.0078

-9.5

-16.9

-23.5

-29.8

-36.0

-42.0

-48.1

32.6.2 Basic Mode

Basic mode (MD = 000) disables all additional computation features. In this mode, no accumulation occurs but

threshold error comparison is performed. Double sampling, Continuous mode, and all CVD features are still available,

but no features involving the digital filter/average features are used.

32.6.3 Accumulate Mode

In Accumulate mode (MD = 001), after every conversion, the ADC result is added to the ADACC register. The

ADACC register is right-shifted by the value of the CRS bits. This right-shifted value is copied into the ADFLT register.

The Formatting mode does not affect the right-justification of the ADFLT value. Upon each sample, ADCNT is also

incremented, incrementing the number of samples accumulated. After each sample and accumulation, the ADACC

value has a threshold comparison performed on it and the ADTIF interrupt may trigger.

Related Links

32.6.7 Threshold Comparison

32.6.4 Average Mode

In Average Mode (MD = 010), the ADACC registers accumulate with each ADC sample, much as in Accumulate

mode, and the ADCNT register increments with each sample. The ADFLT register is also updated with the right-

DS40002002B-page 523

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

shifted value of the ADACC register. The value of the CRS bits govern the number of right shifts. However, in

Average mode, the threshold comparison is performed upon ADCNT being greater than or equal to a user-defined

ADRPT value. In this mode when ADCNT = 2^ADCRS, then the final accumulated value will be divided by number of

samples, allowing for a threshold comparison operation on the average of all gathered samples.

32.6.5 Burst Average Mode

The Burst Average mode (MD = 011) acts the same as the Average mode in most respects. The one way it differs is

that it continuously retriggers ADC sampling until the ADCNT value is greater than or equal to ADRPT, even if

Continuous Sampling mode is not enabled. This allows for a threshold comparison on the average of a short burst of

ADC samples.

Related Links

32.6.8 Continuous Sampling Mode

32.6.6 Low-pass Filter Mode

The Low-pass Filter mode (MD = 100) acts similarly to the Average mode in how it handles samples (accumulates

samples until ADCNT value greater than or equal to ADRPT, then triggers threshold comparison), but instead of a

simple average, it performs a low-pass filter operation on all of the samples, reducing the effect of high-frequency

noise on the average, then performs a threshold comparison on the results. In this mode, the CRS bits determine the

cut-off frequency of the low-pass filter.

Related Links

32.6.1 Digital Filter/Average

32.6 Computation Operation

32.6.7 Threshold Comparison

At the end of each computation:

•

The conversion results are latched and held stable at the end-of-conversion.

The error (ADERR) is calculated based on a difference calculation which is selected by the CALC bits in the

ADCON3 register. The value can be one of the following calculations:

– The first derivative of single measurements

– The CVD result in CVD mode

– The current result vs. a setpoint

– The current result vs. the filtered/average result

– The first derivative of the filtered/average value

– Filtered/average value vs. a setpoint

•

The result of the calculation (ADERR) is compared to the upper and lower thresholds, ADUTH[UTHH:UTHL] and

ADLTH[LTHH:LTHL] registers, to set the UTHR and LTHR flag bits. The threshold logic is selected by TMD bits.

The threshold trigger option can be one of the following:

– Never interrupt

– Error is less than lower threshold

– Error is greater than or equal to lower threshold

– Error is between thresholds (inclusive)

– Error is outside of thresholds

– Error is less than or equal to upper threshold

– Error is greater than upper threshold

– Always interrupt regardless of threshold test results

– If the threshold condition is met, the threshold interrupt flag ADTIF is set.

Note:ꢀ

1. The threshold tests are signed operations.

2. If OV is set, a threshold interrupt is signaled. It is good practice for threshold interrupt handlers to verify the

validity of the threshold by checking ADAOV.

See ADC Error Calculation Mode table for further details.

DS40002002B-page 524

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.6.8 Continuous Sampling Mode

Setting the CONT bit automatically retriggers a new conversion cycle after updating the ADACC register. The GO bit

remains set and retriggering occurs automatically.

If SOI = 1, a threshold interrupt condition will clear GO and the conversions will stop.

32.6.9 Double Sample Conversion

Double sampling is enabled by setting the DSEN bit. When this bit is set, two conversions are required before the

module will calculate threshold error (each conversion must still be triggered separately). The first conversion will set

the MATH bit and update ADACC, but will not calculate ADERR or trigger ADTIF. When the second conversion

completes, the first value is transferred to ADPREV (depending on the setting of PSIS) and the value of the second

conversion is placed into ADRES. Only upon the completion of the second conversion is ADERR calculated and

ADTIF triggered (depending on the value of CALC).

DS40002002B-page 525

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.7

Register Summary - ADC Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x8B

7:0

15:8

7:0

LTH[7:0]

LTH[15:8]

UTH[7:0]

0x8C

0x8E

0x90

0x92

0x94

ADLTH

ADUTH

ADERR

ADSTPT

ADFLTR

15:8

7:0

UTH[15:8]

ERR[7:0]

ERR[15:8]

STPT[7:0]

STPT[15:8]

FLTR[7:0]

FLTR[15:8]

ACC[7:0]

ACC[15:8]

ACC[17:16]

CNT[7:0]

15:8

7:0

15:8

7:0

15:8

7:0

0x96

ADACC

15:8

23:16

7:0

0x99

0x9A

ADCNT

ADRPT

7:0

RPT[7:0]

7:0

PREV[7:0]

PREV[15:8]

RES[7:0]

0x9B

0x9D

ADPREV

15:8

7:0

ADRES

ADPCH

15:8

7:0

RES[15:8]

PCH[5:0]

0x9F

0xA0

...

Reserved

0x010B

7:0

15:8

7:0

15:8

7:0

ACQ[7:0]

ACQ[12:8]

CAP[4:0]

PRE[7:0]

PRE[12:8]

0x010C

0x010E

0x010F

ADACQ

ADCAP

ADPRE

0x0111

0x0112

0x0113

0x0114

0x0115

0x0116

0x0117

0x0118

0x0119

...

ADCON0

ADCON1

ADCON2

ADCON3

ADSTAT

ADREF

ON

CONT

IPEN

CS

FRM

GO

PPOL

PSIS

GPOL

CRS[2:0]

CALC[2:0]

LTHR

DSEN

ACLR

SOI

MD[2:0]

TMD[2:0]

STAT[2:0]

OV

UTHR

MATH

NREF

PREF[1:0]

ADACT

ACT[4:0]

ADCLK

CS[5:0]

Reserved

0x029E

0x029F

ADCPCON0

7:0

CPON

CPRDY

32.8

Register Definitions: ADC Control

DS40002002B-page 526

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.1 ADLTH

Name:ꢀ

Offset:ꢀ

ADLTH

0x08C

ADC Lower Threshold Register

ADLTH and ADUTH are compared with ADERR to set the UTHR and LTHR bits. Depending on the setting of TMD,

an interrupt may be triggered by the results of this comparison.

Bit

15

14

13

12

11

10

9

8

LTH[15:8]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

LTH[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 15:0 – LTH[15:0]ꢀADC Lower Threshold - Signed 2’s complement

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

ADLTHH: Accesses the high byte ADLTH[15:8]

ADLTHL: Accesses the low byte ADLTH[7:0]

DS40002002B-page 527

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.2 ADUTH

Name:ꢀ

Offset:ꢀ

ADUTH

0x08E

ADC Upper Threshold Register

ADLTH and ADUTH are compared with ADERR to set the UTHR and LTHR bits. Depending on the setting of TMD,

an interrupt may be triggered by the results of this comparison.

Bit

15

14

13

12

11

10

9

8

UTH[15:8]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

UTH[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 15:0 – UTH[15:0]ꢀADC Upper Threshold - Signed 2’s complement

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

ADUTHH: Accesses the high byte ADUTH[15:8]

ADUTHL: Accesses the low byte ADUTH[7:0]

DS40002002B-page 528

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.3 ADERR

Name:ꢀ

Offset:ꢀ

ADERR

0x090

ADC Setpoint Error Register

ADC Setpoint Error calculation is determined by the CALC bits.

Bit

15

14

13

12

11

10

9

8

ERR[15:8]

Access

Reset

R

x

R

x

R

x

R

x

R

x

R

x

R

x

R

x

Bit

7

6

5

4

3

2

1

0

ERR[7:0]

Access

Reset

R

x

R

x

R

x

R

x

R

x

R

x

R

x

R

x

Bits 15:0 – ERR[15:0]ꢀADC Setpoint Error - Signed 2’s complement

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

ADERRH: Accesses the high byte ADERR[15:8]

ADERRL: Accesses the low byte ADERR[7:0]

DS40002002B-page 529

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ADC2 - Analog-to-Digital Converter

32.8.4 ADSTPT

Name:ꢀ

Offset:ꢀ

ADSTPT

0x092

ADC Threshold Setpoint Register

Depending on the CALC bits, it may be used to determine ADERR. See ADC Error Calculation Mode table for more

details.

Bit

15

14

13

12

11

10

9

8

STPT[15:8]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

STPT[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 15:0 – STPT[15:0]ꢀADC Threshold Setpoint - Signed 2’s complement

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

ADSTPTH: Accesses the high byte ADSTPT[15:8]

ADSTPTH: Accesses the low byte ADSTPT[7:0]

DS40002002B-page 530

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ADC2 - Analog-to-Digital Converter

32.8.5 ADFLTR

Name:ꢀ

Offset:ꢀ

ADFLTR

0x094

ADC Filter Register

Bit

15

14

13

12

11

10

9

8

FLTR[15:8]

FLTR[7:0]

Access

Reset

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

Bit

7

6

5

4

3

2

1

0

Access

Reset

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

Bits 15:0 – FLTR[15:0]ꢀADC Filter Output - Signed 2’s complement

In Accumulate, Average, and Burst Average mode, this is equal to ADACC register right shifted by the CRS bits. In

LPF mode, this is the output of the low-pass filter.

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

ADFLTRH: Accesses the high byte ADFLTR[15:8]

ADFLTRL: Accesses the low byte ADFLTR[7:0]

DS40002002B-page 531

Datasheet

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ADC2 - Analog-to-Digital Converter

32.8.6 ADACC

Name:ꢀ

Offset:ꢀ

ADACC

0x096

ADC Accumulator Register

See Computation Modes for more details.

Important:ꢀ This register contains signed 2’s complement accumulator value and the upper unused bits

contain copies of the sign bit.

Bit

23

15

22

21

20

19

18

17

16

ACC[17:16]

Access

Reset

R/W

x

R/W

x

Bit

14

13

12

11

10

9

8

ACC[15:8]

ACC[7:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bit

7

6

5

4

3

2

1

0

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 17:0 – ACC[17:0]ꢀADC Accumulator - Signed 2’s complement

Note:ꢀ

1. This register can only be written when GO = 0.

2. The individual bytes in this multi-byte register can be accessed with the following register names:

– ADACCU: Accesses the upper byte ADACC[17:16]

– ADACCH: Accesses the high byte ADACC[15:8]

– ADACCL: Accesses the low byte ADACC[7:0]

DS40002002B-page 532

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ADC2 - Analog-to-Digital Converter

32.8.7 ADCNT

Name:ꢀ

Offset:ꢀ

ADCNT

0x099

ADC Repeat Counter Register

Bit

7

6

5

4

3

2

1

0

CNT[7:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 7:0 – CNT[7:0]ꢀADC Repeat Count bits

Counts the number of times that the ADC is triggered before the threshold is checked. When this value reaches

ADPRT then the threshold is checked. Used when the computation mode is Low-pass Filter, Burst Average, or

Average. See Computation Modes for more details.

Reset States: POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

DS40002002B-page 533

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.8 ADRPT

Name:ꢀ

Offset:ꢀ

ADRPT

0x09A

ADC Repeat Setting Register

Bit

7

6

5

4

3

2

1

0

RPT[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 7:0 – RPT[7:0]ꢀADC Repeat Threshold bits

Determines the number of times that the ADC is triggered for a threshold check. When ADCNT reaches this value the

error threshold is checked. Used when the computation mode is Low-pass Filter, Burst Average, or Average. See

Computation Modes for more details.

DS40002002B-page 534

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ADC2 - Analog-to-Digital Converter

32.8.9 ADPREV

Name:ꢀ

Offset:ꢀ

ADPREV

0x09B

ADC Previous Result Register

Bit

15

14

13

12

11

10

9

8

PREV[15:8]

PREV[7:0]

Access

Reset

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

RO

0

Bit

7

6

5

4

3

2

1

0

Access

Reset

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

RO

x

Bits 15:0 – PREV[15:0]ꢀPrevious ADC Result

Value

n

Condition

PSIS = 1

PSIS = 0

Description

n = ADFLTR value at the start of current ADC conversion

n = ADRES at the start of current ADC conversion⁽¹⁾

Note:ꢀ

1. If PSIS = 0, PREVH and PREVL are formatted the same way as ADRES is, depending on the FRM bit.

2. The individual bytes in this multi-byte register can be accessed with the following register names:

– ADPREVH: Accesses ADPREV[15:8]

– ADPREVL: Accesses ADPREV[7:0]

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ADC2 - Analog-to-Digital Converter

32.8.10 ADRES

Name:ꢀ

Offset:ꢀ

ADRES

0x09D

ADC Result Register

15

Bit

14

13

12

11

10

9

8

RES[15:8]

RES[7:0]

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bit

7

6

5

4

3

2

1

0

Access

Reset

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

Bits 15:0 – RES[15:0]ꢀADC Sample Result

Reset States: POR/BOR = xxxxxxxxxxxxxxxx

All Other Resets = uuuuuuuuuuuuuuuu

Value

0x0FFF

to

Condition

FRM = 1

Description

Right-aligned result

0x0000

0xFFFx

to

FRM = 0

Left-aligned result

0x000x

Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:

•

ADRESH: Accesses the high byte ADRES[15:18]

ADRESL: Accesses the low byte ADRES[7:0]

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ADC2 - Analog-to-Digital Converter

32.8.11 ADPCH

Name:ꢀ

Offset:ꢀ

ADPCH

0x09F

ADC Positive Channel Selection Register

Bit

7

6

5

4

3

2

1

0

PCH[5:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 5:0 – PCH[5:0]ꢀADC Positive Input Channel Selection bits

Table 32-4.ꢀADC Positive Input Channel Selections

PCH

111111

ADC Positive Channel Input

Observations

Fixed Voltage Reference (FVR) 2

Fixed Voltage Reference (FVR) 1

DAC1 output

111110

111101

111100

Temperature Indicator

AV_SS(Analog Ground)

Reserved. No channel connected.

RC7/ANC7

111011

111010-011000

010111

Only for 20-pin devices

010110

RC6/ANC6

010101

RC5/ ANC5

010100

RC4/ ANC4

010011

RC3/ANC3

010010

RC2/ANC2

010001

RC1/ ANC1

010000

RC0/ANC0

001111

RB7/ANB7

Only for 20-pin devices

001110

RB6/ANB6

001101

RB5/ANB5

001100

RB4/ ANB4

001011-000110

000101

Reserved. No channel connected.

RA5/ANA5

000100

RA4/ANA4

000011

Reserved. No channel connected.

RA2/ ANA2

000010

000001

RA1/ ANA1

000000

RA0/ANA0

DS40002002B-page 537

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PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.12 ADACQ

Name:ꢀ

Offset:ꢀ

ADACQ

0x10C

ADC Acquisition Time Control Register

Bit

15

14

13

12

11

10

ACQ[12:8]

R/W

9

8

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bit

7

6

5

4

3

2

1

0

ACQ[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 12:0 – ACQ[12:0]ꢀAcquisition (charge share time) Select

Value

Description

11111111

11111-00

00000000

001

00000000

00000

Number of ADC clock periods in the acquisition time

Acquisition time is not included in the data conversion cycle⁽¹⁾

Note:ꢀ

1. If ADPRE is not equal to ‘0’, then ADACQ = 0b0_0000_0000_0000means Acquisition time is 8192 clocks of

the selected ADC clock.

2. The individual bytes in this multi-byte register can be accessed with the following register names:

– ADACQH: Accesses the high byte ADACQ[12:8]

– ADACQL: Accesses the low byte ADACQ[7:0]

DS40002002B-page 538

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.13 ADCAP

Name:ꢀ

Offset:ꢀ

ADCAP

0x10E

ADC Additional Sample Capacitor Selection Register

Bit

7

6

5

4

3

2

CAP[4:0]

R/W

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – CAP[4:0]ꢀADC Additional Sample Capacitor Selection bits

Value

11111-00

001

Description

Number of pF in the additional capacitance

0

No additional capacitance

DS40002002B-page 539

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.14 ADPRE

Name:ꢀ

Offset:ꢀ

ADPRE

0x10F

ADC Precharge Time Control Register

The individual bytes in this multi-byte register can be accessed with the following register names:

•

ADPREH: Accesses the high byte PRE[12:8]

ADPREL: Accesses the low byte PRE[7:0]

Bit

15

7

14

6

13

5

12

11

10

PRE[12:8]

R/W

9

8

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bit

4

3

2

1

0

PRE[7:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 12:0 – PRE[12:0]ꢀPrecharge Time Select

Value

0x1FFF-0

x0001

0

Description

Number of ADC clocks in the precharge time

Precharge time is not included in the data conversion cycle

Note:ꢀ If ADPRE is not equal to ‘0’, then ADACQ = b’00000000means Acquisition time is 256 clocks of the

selected ADC clock.

DS40002002B-page 540

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.15 ADCON0

Name:ꢀ

Offset:ꢀ

ADCON0

0x111

ADC Control Register 0

Bit

7

ON

R/W

0

6

CONT

R/W

0

5

4

CS

R/W

0

3

2

1

0

GO

FRM

R/W

0

Access

Reset

R/W/HC

0

Bit 7 – ONꢀADC Enable bit

Value

Description

1

0

ADC is enabled

ADC is disabled

Bit 6 – CONTꢀADC Continuous Operation Enable bit

Value

Description

1

GO is retriggered upon completion of each conversion trigger until TIF is set (if SOI is set) or until GO

is cleared (regardless of the value of SOI)

0

GO is cleared upon completion of each conversion trigger

Bit 4 – CSꢀADC Clock Selection bit

Value

Description

1

0

Clock supplied from FRC dedicated oscillator

Clock supplied by F_OSC, divided according to ADCLK register

Bit 2 – FRMꢀADC Results Format/Alignment Selection

Value

Description

1

0

ADRES and ADPREV data are right-justified

ADRES and ADPREV data are left-justified, zero-filled

Bit 0 – GOꢀ ADC Conversion Status bit^(1,2)

Value

Description

1

ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by

hardware as determined by the CONT bit

0

ADC conversion completed/not in progress

Note:ꢀ

1. This bit requires ON bit to be set.

2. If cleared by software while a conversion is in progress, the results of the conversion up to this point will be

transferred to ADRES and the state machine will be reset, but the ADIF interrupt flag bit will not be set; filter

and threshold operations will not be performed.

DS40002002B-page 541

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.16 ADCON1

Name:ꢀ

Offset:ꢀ

ADCON1

0x112

ADC Control Register 1

Bit

7

PPOL

R/W

0

6

IPEN

R/W

0

5

GPOL

R/W

0

4

3

2

1

0

DSEN

R/W

0

Access

Reset

Bit 7 – PPOLꢀPrecharge Polarity bit

Action During 1^stPrecharge Stage

Value

Condition

Description

x

PRE=0

Bit has no effect

Pin shorted to AV_DD

Pin shorted to V_SS

C_HOLDShorted to AV_DD

C_HOLDShorted to V_SS

1

0

1

0

PRE>0& ADC input is I/O pin

PRE>0& ADC input is internal

Bit 6 – IPENꢀA/D Inverted Precharge Enable bit

Value

Condition Description

x

DSEN = 0 Bit has no effect

1

DSEN = 1 The precharge and guard signals in the second conversion cycle are the opposite polarity

of the first cycle

0

DSEN = 1 Both Conversion cycles use the precharge and guards specified by PPOL and GPOL

Bit 5 – GPOLꢀGuard Ring Polarity Selection bit

Value

Description

1

0

ADC guard Ring outputs start as digital high during Precharge stage

ADC guard Ring outputs start as digital low during Precharge stage

Bit 0 – DSENꢀDouble-Sample Enable bit

Value

Description

1

0

Two conversions are performed on each trigger. Data from the first conversion appears in PREV

One conversion is performed for each trigger

DS40002002B-page 542

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.17 ADCON2

Name:ꢀ

Offset:ꢀ

ADCON2

0x113

ADC Control Register 2

Bit

7

PSIS

R/W

0

6

5

CRS[2:0]

R/W

4

3

ACLR

R/W/HC

0

2

1

MD[2:0]

R/W

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bit 7 – PSISꢀADC Previous Sample Input Select bits

Value

Description

1

0

FLTR is transferred to PREV at start-of-conversion

ADRES is transferred to PREV at start-of-conversion

Bits 6:4 – CRS[2:0]ꢀADC Accumulated Calculation Right Shift Select bits

Value

111-000

xxx

Condition

MD = b'100'

MD = b'011' to b'001'

MD = b'000'to b'001'

Description

Low-pass filter time constant is 2^CRS, filter gain is 1:1

The accumulated value is right-shifted by CRS (divided by 2^{CRS (1,2)}

These bits are ignored

)

Bit 3 – ACLRꢀ A/D Accumulator Clear Command bit⁽³⁾

Value

Description

1

0

ACC, OV and CNT bits are cleared

Clearing action is complete (or not started)

Bits 2:0 – MD[2:0]ꢀ ADC Operating Mode Selection bits⁽⁴⁾

Value

111-101

100

011

010

Description

Reserved

Low-pass Filter mode

Burst Average mode

Average mode

001

000

Accumulate mode

Basic (Legacy) mode

Note:ꢀ

1. To correctly calculate an average, the number of samples (set in RPT) must be 2^CRS

.

2. CRS = 3'b111is a reserved option.

3. This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator

selections, the delay may be many instructions.

4. See Computation Modes for full mode descriptions.

DS40002002B-page 543

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.18 ADCON3

Name:ꢀ

Offset:ꢀ

ADCON3

0x114

ADC Control Register 3

Bit

7

6

5

CALC[2:0]

R/W

4

3

SOI

2

1

TMD[2:0]

R/W

0

Access

Reset

R/W

0

R/W

0

R/W/HC

0

R/W

0

R/W

0

Bits 6:4 – CALC[2:0]ꢀADC Error Calculation Mode Select bits

See table below for selection details.

Table 32-5.ꢀADC Error Calculation Mode

Action During 1st Precharge Stage

CALC

Application

DSEN = 0 Single-Sample

DSEN = 1 CVD Double-Sample

Mode

Mode⁽¹⁾

000

ADRES-ADPREV

First derivative of single measurement⁽²⁾

Actual CVD result in CVD mode⁽²⁾

Actual result vs. setpoint

001

010

011

100

ADRES-ADSTPT

ADRES-ADFLTR

Reserved

(ADRES-ADPREV)-ADSTPT

(ADRES-ADPREV)-ADFLTR

Reserved

Actual result vs. averaged/filtered value

Reserved

ADPREV-ADFLTR

First derivative of filtered value⁽³⁾

(negative)

101

110

ADLFTR-ADSTPT

Reserved

ADFLTR-ADSTPT

Reserved

Average/filtered value vs. setpoint

Reserved

111

Reserved

Note:ꢀ

1. When PSIS = 0, the value of ADRES-ADPREV) is the value of (S2-S1) from Computation Modes.

2. When PSIS = 0

3. When PSIS = 1.

Bit 3 – SOIꢀADC Stop-on-Interrupt bit

Value

Condition Description

1

CONT = 1 GO is cleared when the threshold conditions are met, otherwise the conversion is

retriggered

0

x

CONT = 1 GO is not cleared by hardware, must be cleared by software to stop retriggers

CONT = 0 This bit is not used

Bits 2:0 – TMD[2:0]ꢀThreshold Interrupt Mode Select bits

Value

111

110

101

100

011

010

Description

Interrupt regardless of threshold test results

Interrupt if ERR>UTH

Interrupt if ERR≤UTH

Interrupt if ERR<LTH or ERR>UTH

Interrupt if ERR>LTH and ERR<UTH

Interrupt if ERR≥LTH

DS40002002B-page 544

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

Value

001

000

Description

Interrupt if ERR<LTH

Never interrupt

DS40002002B-page 545

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.19 ADSTAT

Name:ꢀ

Offset:ꢀ

ADSTAT

0x115

ADC Status Register

Bit

7

6

5

LTHR

RO

0

4

MATH

R/HS/HC

0

3

2

1

STAT[2:0]

RO

0

OV

RO

0

UTHR

RO

0

Access

Reset

RO

0

RO

0

Bit 7 – OVꢀADC Accumulator Overflow bit

Value

Description

1

ADC accumulator or ERR calculation have overflowed

0

ADC accumulator and ERR calculation have not overflowed

Bit 6 – UTHRꢀADC Module Greater-than Upper Threshold Flag bit

Value

1

0

Description

ERR >UTH

ERR≤UTH

Bit 5 – LTHRꢀADC Module Less-than Lower Threshold Flag bit

Value

1

0

Description

ERR<LTH

ERR≥LTH

Bit 4 – MATHꢀADC Module Computation Status bit

Value

Description

1

0

Registers ADACC, ADFLTR, ADUTH, ADLTH and the OV bit are updating or have already updated

Associated registers/bits have not changed since this bit was last cleared

Bits 2:0 – STAT[2:0]ꢀ ADC Module Cycle Multistage Status bits⁽¹⁾

Value

111

110

101

100

011

010

001

000

Description

ADC module is in 2^ndconversion stage

ADC module is in 2^ndacquisition stage

ADC module is in 2^ndprecharge stage

Not used

ADC module is in 1^stconversion stage

ADC module is in 1^stacquisition stage

ADC module is in 1^stprecharge stage

ADC module is not converting

Note:ꢀ

1. If CS = 1, and F_OSC<FRC, these bits may be invalid.

DS40002002B-page 546

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.20 ADREF

Name:ꢀ

Offset:ꢀ

ADREF

0x116

ADC Reference Selection Register

Bit

7

6

5

4

NREF

R/W

0

3

2

1

0

PREF[1:0]

Access

Reset

R/W

0

R/W

0

Bit 4 – NREFꢀADC Negative Voltage Reference Selection bit

Value

Description

1

0

V_REF- is connected to external V_REF

V_REF- is connected to AV_SS

-

Bits 1:0 – PREF[1:0]ꢀADC Positive Voltage Reference Selection bits

Value

11

Description

V_REF+ is connected to internal Fixed Voltage Reference (FVR) module

10

01

V_REF+ is connected to external V_REF

Reserved

+

00

V_REF+ is connected to V_DD

DS40002002B-page 547

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.21 ADACT

Name:ꢀ

Offset:ꢀ

ADACT

0x117

ADC AUTO Conversion Trigger Source Selection Register

Bit

7

6

5

4

3

2

ACT[4:0]

R/W

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – ACT[4:0]ꢀAuto-Conversion Trigger Select Bits

Table 32-6.ꢀ ADC Auto-Conversion Trigger Sources

ACT

11111

Auto-conversion Trigger Source

Software write to ADPCH

Reserved, do not use

Software read of ADRESH

Software read of ADERRH

Reserved, do not use

CLC4_out

11110

11101

11100

11011 to 11000

10111

10110

CLC3_out

10101

CLC2_out

10100

CLC1_out

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

Logical ORof all Interrupt-on-change Interrupt Flags

C2_out

C1_out

NCO1_out

PWM7_out

PWM6_out

CCP4_trigger

CCP3_trigger

CCP2_trigger

CCP1_trigger

SMT1_trigger

TMR6_postscaled

TMR5_overflow

TMR4_postscaled

TMR3_overflow

TMR2_postscaled

TMR1_overflow

DS40002002B-page 548

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

...........continued

ACT

Auto-conversion Trigger Source

00010

00001

00000

TMR0_overflow

Pin selected by ADACTPPS

External Trigger Disabled

DS40002002B-page 549

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.22 ADCLK

Name:ꢀ

Offset:ꢀ

ADCLK

0x118

ADC Clock Selection Register

Bit

7

6

5

4

3

2

1

0

CS[5:0]

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 5:0 – CS[5:0]ꢀADC Conversion Clock Select bits

Value

Description

11 1111

ADC Clock frequency = F_OSC/(2*(CS+1))

- 00

0000

DS40002002B-page 550

Datasheet

PIC16(L)F18425/45

ADC2 - Analog-to-Digital Converter

32.8.23 ADCPCON0

Name:ꢀ

Offset:ꢀ

ADCPCON0

0x29F

ADC Charge Pump Control Register 0

Bit

7

CPON

R/W

0

6

5

4

3

2

1

0

CPRDY

RO

Access

Reset

0

Bit 7 – CPONꢀCharge Pump On Control bit

Value

Description

1

0

Charge Pump On when requested by the ADC

Charge Pump Off

Bit 0 – CPRDYꢀCharge Pump Ready Status bit

Value

Description

1

Charge Pump is ready

0

Charge Pump is not ready (or never started)

DS40002002B-page 551

Datasheet

PIC16(L)F18425/45

DAC - 5-Bit Digital-to-Analog Converter

33.

DAC - 5-Bit Digital-to-Analog Converter

The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32

selectable output levels.

The positive input source (V_SOURCE+) of the DAC can be connected to:

•

FVR Buffer

External V_REF+ pin

V_DDsupply voltage

The negative input source (V_SOURCE-) of the DAC can be connected to:

•

External V_REF- pin

V_SS

The output of the DAC (DACx_output) can be selected as a reference voltage to the following:

•

Comparator positive input

ADC input channel

DACxOUT1 pin

The Digital-to-Analog Converter (DAC) can be enabled by setting the EN bit.

DS40002002B-page 552

Datasheet

PIC16(L)F18425/45

DAC - 5-Bit Digital-to-Analog Converter

Figure 33-1.ꢀDigital-to-Analog Converter Block Diagram

Rev. 10-000 026J

2/26/201 9

VSOURCE+

Positive

DACR

Reference

Sources

R

PSS

R

2ⁿ

Steps

DACx_output

To Peripherals

EN

R

DACxOUTn

R

OEn⁽¹⁾

Negative

VSOURCE-

Reference

Sources

NSS

Note

1:

The output enable bits are configured so that they act as a one-hotꢀꢁsystem, meaning only one DAC

output can be enabled at a time.

33.1

Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels are set with the DAC1R bits.

The DAC output voltage can be determined by using the following equation.

Equation 33-1.ꢀDAC Output Voltage

ꢙꢞꢌꢉ 4:0

ꢙꢞꢌꢔ_ꢆꢒꢓꢯꢒꢓ =

ꢑ

− ꢑ

ꢔ

+ ꢑ

ꢋꢊꢮꢉꢌꢝ −

ꢋꢊꢮꢉꢌꢝ +

ꢋꢊꢮꢉꢌꢝ −

32

Note:ꢀ See the DAC1CON0 register for the available V_SOURCE+ and V_SOURCE- selections.

33.2

Ratiometric Output Level

The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative

voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the

DAC output value.

DS40002002B-page 553

Datasheet

PIC16(L)F18425/45

DAC - 5-Bit Digital-to-Analog Converter

The value of the individual resistors within the ladder can be found in the “5-Bit DAC Specifications” table from the

“Electrical Specifications” chapter.

Related Links

40.4.10 5-Bit DAC Specifications

33.3

DAC Voltage Reference Output

The DAC voltage can be output to the DAC1OUT pin by setting the DAC1OE bit of the DAC1CON0 register.

Selecting the DAC reference voltage for output on the DAC1OUT pin automatically overrides the digital output buffer

and digital input threshold detector functions, it disables the weak pull-up and the constant-current drive function of

that pin. Reading the DAC1OUT pin when it has been configured for DAC reference voltage output will always return

a ‘0’.

Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external

connections to the DAC1OUT pin. Figure 33-2 below shows an example buffering technique.

Figure 33-2.ꢀVoltage Reference Output Buffer Example

PIC^®MCU

DAC

Module

R

+

–

Buffered DAC Output

DAC1OUT

Voltage

Reference

Output

Impedance

33.4

33.5

Operation During Sleep

The DAC continues to function during Sleep. When the device wakes up from Sleep through an interrupt or a

Watchdog Timer time-out, the contents of the DAC1CON0 register are not affected.

Effects of a Reset

A device Reset affects the following:

•

DACx is disabled.

DACx output voltage is removed from the DACxOUTn pin(s).

The DAC1R range select bits are cleared.

DS40002002B-page 554

Datasheet

PIC16(L)F18425/45

DAC - 5-Bit Digital-to-Analog Converter

33.6

Register Summary - DAC Control

Offset

Name

Bit Pos.

0x00

...

Reserved

0x090D

0x090E

0x090F

DAC1CON0

DAC1CON1

7:0

EN

OE1

PSS[1:0]

DAC1R[4:0]

NSS

33.7

Register Definitions: DAC Control

DS40002002B-page 555

Datasheet

PIC16(L)F18425/45

DAC - 5-Bit Digital-to-Analog Converter

33.7.1 DAC1CON0

Name:ꢀ

Offset:ꢀ

DAC1CON0

0x90E

DAC Control Register

Bit

7

EN

R/W

0

6

5

4

3

2

1

0

OE1

R/W

0

PSS[1:0]

NSS

R/W

0

Access

Reset

R/W

0

R/W

0

Bit 7 – ENꢀDAC Enable bit

Value

Description

1

0

DAC is enabled

DAC is disabled

Bit 5 – OE1ꢀDAC Voltage Output Enable bit

Value

1

0

Description

DAC voltage level is output on the DAC1OUT1 pin

DAC voltage level is disconnected from the DAC1OUT1 pin

Bits 3:2 – PSS[1:0]ꢀDAC Positive Source Select bit

Value

11

Description

Reserved

10

FVR buffer

01

V_REF

+

00

AV_DD

Bit 0 – NSSꢀDAC Negative Source Select bit

Value

1

0

Description

V_REF

AV_SS

-

DS40002002B-page 556

Datasheet

PIC16(L)F18425/45

DAC - 5-Bit Digital-to-Analog Converter

33.7.2 DAC1CON1

Name:ꢀ

Offset:ꢀ

DAC1CON1

0x90F

DAC Data Register

Bit

7

6

5

4

3

2

DAC1R[4:0]

R/W

1

0

Access

Reset

R/W

0

R/W

0

R/W

0

R/W

0

Bits 4:0 – DAC1R[4:0]ꢀData Input Register for DAC bits

DS40002002B-page 557

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

34.

CMP - Comparator Module

Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing

a digital indication of their relative magnitudes. Comparators are very useful mixed-signal building blocks because

they provide analog functionality independent of program execution. The PIC16(L)F18425/45 devices have 2

comparators (C1/C2).

The analog comparator module includes the following features:

•

Programmable Input Selection

Programmable Output Polarity

Rising/Falling Output Edge Interrupts

Wake-up from Sleep

CWG Auto-Shutdown Source

Selectable Voltage Reference

ADC Auto-Trigger

Odd Numbered Timers (Timer1, Timer3, etc.) Gate

Even Numbered Timers (Timer2, Timer4, etc.) Reset

CCP Capture Mode Input

DSM Modulator Source

Input and Window Signal-to-Signal Measurement Timer

34.1

Comparator Overview

A single comparator is shown in Figure 34-1 along with the relationship between the analog input levels and the

digital output. When the analog voltage at V_IN+ is less than the analog voltage at V_IN-, the output of the comparator is

a digital low level. When the analog voltage at V_IN+ is greater than the analog voltage at V_IN-, the output of the

comparator is a digital high level.

Table 34-1.ꢀAvailable Comparators

Device

C1

●

C2

●

PIC16(L)F18425

PIC16(L)F18445

●

Figure 34-1.ꢀSingle Comparator

Rev. 30-000125A

5/17/2017

VIN+

VIN-

+

–

Output

VIN-

VIN+

Output

Note:ꢀ

1. The black areas of the output of the comparator represent the uncertainty due to input offsets and response

time.

DS40002002B-page 558

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

Figure 34-2.ꢀComparator Module Simplified Block Diagram

Re v. 10 -00 00 27R

2/11 /20 19

INTP

Interrupt

Rising

Edge

set bit

CxIF

NCH

EN⁽¹⁾

INTN

Interrupt

Falling

Edge

EN⁽¹⁾

CxVP

CxVN

See CMxNCH

Register

-

Comparator Output

Cx

+

HYS

POL

CxOUT_sync

To Other

See CMxPCH

Register

Peripherals

SYNC

Q

TRIS bit

0

1

CxOUT

PPS

D

PCH

EN⁽¹⁾

RxyPPS

(From Timer1 Module) T1CLK

Note 1:

When EN = 0, all multiplexer inputs are disconnected and the Comparator will produce a 0ꢀꢁat the output.

Related Links

34.15.4 CMxNCH

34.15.5 CMxPCH

34.2

Comparator Control

Each comparator has two control registers: CMxCON0 and CMxCON1.

The CMxCON0 register contains Control and Status bits for the following:

•

Enable

Output

Output Polarity

Hysteresis Enable

Timer1 Output Synchronization

The CMxCON1 register contains Control bits for the following:

•

Interrupt on Positive/Negative Edge Enables

Positive Input Channel Selection

Negative Input Channel Selection

34.2.1 Comparator Enable

Setting the EN bit enables the comparator for operation. Clearing the CxEN bit disables the comparator, resulting in

minimum current consumption.

DS40002002B-page 559

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

34.2.2 Comparator Output

The output of the comparator can be monitored by reading either the CxOUT bit or the MCxOUT bit.

The comparator output can also be routed to an external pin through the RxyPPS register. The corresponding TRIS

bit must be clear to enable the pin as an output.

Note:ꢀ

1. The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified,

external outputs are not latched.

Related Links

16.9.3 RxyPPS

34.2.3 Comparator Output Polarity

Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the

comparator output can be inverted by setting the CxPOL bit. Clearing the CxPOL bit results in a non-inverted output.

Table 34-2 shows the output state versus input conditions, including polarity control.

Table 34-2.ꢀComparator Output State vs. Input Conditions

Input Condition

CxVn > CxVp

CxVn < CxVp

CxVn > CxVp

CxVn < CxVp

CxPOL

CxOUT

0

1

0

1

0

34.3

34.4

Comparator Hysteresis

A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis

function to the overall operation. Hysteresis is enabled by setting the CxHYS bit.

See Comparator Specifications for more information.

Related Links

40.4.9 Comparator Specifications

Operation With Timer1 Gate

The output resulting from a comparator operation can be used as a source for gate control of the odd numbered

timers (Timer1, Timer3, etc.). See 19.7 Timer1 Gate section for more information. This feature is useful for timing the

duration or interval of an analog event.

It is recommended that the comparator output be synchronized to the timer by setting the SYNC bit in the CMxCON0

register. This ensures that the timer does not increment while a change in the comparator is occurring. However,

synchronization is only possible with the Timer1 clock source. Synchronization with the other odd numbered timers is

only possible when they use the same clock source as Timer1.

Related Links

19.7 Timer1 Gate

34.4.1 Comparator Output Synchronization

The output from a comparator can be synchronized with Timer1 by setting the SYNC bit.

Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used

with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge

DS40002002B-page 560

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

of its clock source. See the Figure 34-2 Comparator Block Diagram and the Timer1 Block Diagram for more

information.

Related Links

19. TMR1 - Timer1 Module with Gate Control

34.5

Comparator Interrupt

An interrupt can be generated when either the rising edge or falling edge detector detects a change in the output

value of each comparator.

When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits), the

Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set.

To enable the interrupt, the following bits must be set:

•

EN and POL bits

CxIE bit of the PIE2 register

INTP bit (for a rising edge detection)

INTN bit (for a falling edge detection)

PEIE and GIE bits of the INTCON register

The associated Interrupt Flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is

detected while this flag is being cleared, the flag will still be set at the end of the sequence.

Important:ꢀ Although a comparator is disabled, an interrupt can be generated by changing the output

polarity with the CxPOL bit, or by switching the comparator on or off with the CxEN bit.

34.6

Comparator Positive Input Selection

Configuring the PCH bits in the CMxPCH register direct an internal voltage reference or an analog pin to the non-

inverting input of the comparator:

•

CxINy+ analog pin

DAC output

Fixed Voltage Reference (FVR)

Important:ꢀ To use CxINy+ pins as analog input, the appropriate bits must be set in the ANSEL register

and the corresponding TRIS bits must also be set to disable the output drivers.

Any time the comparator is disabled (CxEN = 0), all comparator inputs are disabled.

Related Links

30. FVR - Fixed Voltage Reference

33. DAC - 5-Bit Digital-to-Analog Converter

34.7

Comparator Negative Input Selection

The NCH bits in the CMxNCH register direct an analog input pin and internal reference voltage or analog ground to

the inverting input of the comparator:

•

CxINy- analog pin

Fixed Voltage Reference (FVR)

DS40002002B-page 561

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

Important:ꢀ To use CxINy- pins as analog input, the appropriate bits must be set in the ANSEL register

and the corresponding TRIS bits must also be set to disable the output drivers.

34.8

Comparator Response Time

The comparator output is indeterminate for a period of time after the change of an input source or the selection of a

new reference voltage. This period is referred to as the response time. The response time of the comparator differs

from the settling time of the voltage reference. Therefore, both of these times must be considered when determining

the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in

Comparator Specifications and Fixed Voltage Reference (FVR) Specifications for more details.

Related Links

40.4.9 Comparator Specifications

40.4.11 Fixed Voltage Reference (FVR) Specifications

34.9

Analog Input Connection Considerations

A simplified circuit for an analog input is shown in Figure 34-3. Since the analog input pins share their connection with

a digital input, they have reverse biased ESD protection diodes to V_DDand V_SS. The analog input, therefore, must be

between V_SSand V_DD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur.

A maximum source impedance of 10 kΩ is recommended for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

Figure 34-3.ꢀAnalog Input Model

Rev. 10-000071A

8/2/2013

VDD

Analog

VT ≈ 0.6V

Input pin

RS < 10K

RIC

To Comparator

(1)

ILEAKAGE

CPIN

5pF

VA

VT ≈ 0.6V

VSS

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

VT

= Interconnect Resistance

= Source Impedance

= Analog Voltage

= Threshold Voltage

Related Links

40. Electrical Specifications

34.10 CWG1 Auto-Shutdown Source

The output of the comparator module can be used as an auto-shutdown source for the CWG1 module. When the

output of the comparator is active and the corresponding WGASxE is enabled, the CWG operation will be suspended

immediately.

DS40002002B-page 562

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

Related Links

25.11.1.2 External Input Source

34.11 ADC Auto-Trigger Source

The output of the comparator module can be used to trigger an ADC conversion. When the ADACT register is set to

trigger on a comparator output, an ADC conversion will trigger when the comparator output goes high.

34.12 Even Numbered Timers Reset

The output of the comparator module can be used to reset the even numbered timers (Timer2, Timer4, etc.). When

the TxERS register is appropriately set, the timer will reset when the comparator output goes high.

34.13 Operation in Sleep Mode

The comparator module can operate during Sleep. The comparator clock source is based on the Timer1 clock

source. If the Timer1 clock source is either the system clock (F_OSC) or the instruction clock (F_OSC/4), Timer1 will not

operate during Sleep, and synchronized comparator outputs will not operate.

A comparator interrupt will wake the device from Sleep. The CxIE bits of the PIE2 register must be set to enable

comparator interrupts.

DS40002002B-page 563

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

34.14 Register Summary - Comparator

Offset

Name

Bit Pos.

0x00

...

Reserved

0x098E

0x098F

0x0990

0x0991

0x0992

0x0993

0x0994

0x0995

0x0996

0x0997

CMOUT

CM1CON0

CM1CON1

CM1NCH

CM1PCH

CM2CON0

CM2CON1

CM2NCH

CM2PCH

7:0

MC2OUT

HYS

MC1OUT

SYNC

EN

OUT

POL

INTP

INTN

NCH[2:0]

PCH[2:0]

HYS

SYNC

INTN

INTP

NCH[2:0]

PCH[2:0]

34.15 Register Definitions: Comparator Control

DS40002002B-page 564

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

34.15.1 CMOUT

Name:ꢀ

Offset:ꢀ

CMOUT

0x98F

Comparator Output Register

Bit

7

6

5

4

3

2

1

MC2OUT

RO

0

MC1OUT

RO

Access

Reset

0

Bits 0, 1 – MCxOUTꢀMirror copy of CxOUT bit

DS40002002B-page 565

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

34.15.2 CMxCON0

Name:ꢀ

Offset:ꢀ

CMxCON0

0x990,0x994

Comparator x Control Register 0

Bit

7

EN

R/W

0

6

OUT

RO

0

5

4

3

2

1

0

SYNC

R/W

0

POL

R/W

0

HYS

R/W

0

Access

Reset

Bit 7 – ENꢀComparator Enable bit

Value

1

0

Description

Comparator is enabled

Comparator is disabled and consumes no active power

Bit 6 – OUTꢀComparator Output bit

Value

Condition

Description

1

If POL = 0(non-inverted polarity):

If POL = 1(inverted polarity):

CxVP > CxVN

CxVP < CxVN

CxVP > CxVN

0

1

0

Bit 4 – POLꢀComparator Output Polarity Select bit

Value

Description

1

0

Comparator output is inverted

Comparator output is not inverted

Bit 1 – HYSꢀComparator Hysteresis Enable bit

Value

Description

1

0

Comparator hysteresis enabled

Comparator hysteresis disabled

Bit 0 – SYNCꢀComparator Output Synchronous Mode bit

Output updated on the falling edge of prescaled Timer1 clock.

Value

Description

1

0

Comparator output to Timer1 and I/O pin is synchronous to changes on the prescaled Timer1 clock.

Comparator output to Timer1 and I/O pin is asynchronous

DS40002002B-page 566

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

34.15.3 CMxCON1

Name:ꢀ

Offset:ꢀ

CMxCON1

0x991,0x995

Comparator x Control Register 1

Bit

7

6

5

4

3

2

1

INTP

R/W

0

INTN

R/W

0

Access

Reset

Bit 1 – INTPꢀComparator Interrupt on Positive-Going Edge Enable bit

Value

Description

1

0

The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit

No interrupt flag will be set on a positive-going edge of the CxOUT bit

Bit 0 – INTNꢀComparator Interrupt on Negative-Going Edge Enable bit

Value

Description

1

0

The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit

No interrupt flag will be set on a negative-going edge of the CxOUT bit

DS40002002B-page 567

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

34.15.4 CMxNCH

Name:ꢀ

Offset:ꢀ

CMxNCH

0x992,0x996

Comparator x Inverting Channel Select Register

Bit

7

6

5

4

3

2

1

NCH[2:0]

R/W

0

Access

Reset

R/W

0

R/W

0

Bits 2:0 – NCH[2:0]ꢀComparator Inverting Input Channel Select bits

NCH

111

110

101

100

011

010

001

000

Negative Input Sources

CxV_Nconnects to AV_SS

CxV_Nconnects to FVR Buffer 2

CxV_Nnot connected

CxV_Nconnects to CxIN3- pin

CxV_Nconnects to CxIN2- pin

CxV_Nconnects to CxIN1- pin

CxV_Nconnects to CxIN0- pin

DS40002002B-page 568

Datasheet

PIC16(L)F18425/45

CMP - Comparator Module

34.15.5 CMxPCH

Name:ꢀ

Offset:ꢀ

CMxPCH

0x993,0x997

Comparator x Non-Inverting Channel Select Register

Bit

7

6

5

4

3

2

1

PCH[2:0]

R/W

0

Access

Reset

R/W

0

R/W

0

Bits 2:0 – PCH[2:0]ꢀComparator Non-Inverting Input Channel Select bits

PCH

111

110

101

100

011

010

001

000

Positive Input Source

CxV_Pconnects to V_SS

CxV_Pconnects to FVR Buffer 2

CxV_Pconnects to DAC1 output

CxV_Pnot connected

CxV_Pconnects to CxIN0+ pin

DS40002002B-page 569

Datasheet

PIC16(L)F18425/45

ZCD - Zero-Cross Detection Module

35.

ZCD - Zero-Cross Detection Module

The Zero-Cross Detection (ZCD) module detects when an A/C signal crosses through the ground potential. The

actual zero crossing threshold is the zero crossing reference voltage, Z_CPINV, which is typically 0.75V above ground.

The connection to the signal to be detected is through a series current-limiting resistor. The module applies a current

source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from

forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the

module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The

current source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD

module is shown in the following simplified block diagram.

Figure 35-1.ꢀSimplified ZCD Block Diagram

Rev. 10-000194B

5/14/2014

VPULLUP

optional

VDD

RPULLUP

-

ZCDxIN

RSERIES

External

voltage

source

RPULLDOWN

Zcpinv

+

optional

ZCDx_output

ZCDxOUT bit

D

Q

ZCDxPOL

Q1

Interrupt

det

Set

ZCDIF

flag

ZCDxINTP

ZCDxINTN

Interrupt

det

The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes:

•

A/C period measurement

Accurate long term time measurement

Dimmer phase delayed drive

Low EMI cycle switching

DS40002002B-page 570

Datasheet

PIC16(L)F18425/45

ZCD - Zero-Cross Detection Module

35.1

External Resistor Selection

The ZCD module requires a current-limiting resistor in series with the external voltage source. The impedance and

rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the

peak voltage when the current through the resistor is nominally 300 μA. Make sure that the ZCD I/O pin internal weak

pull-up is disabled so it does not interfere with the current source and sink.

Equation 35-1.ꢀExternal Resistor

ꢑ

ꢀꢝꢞꢤ

−4

ꢉ

=

ꢋꢝꢉꢡꢝꢋ

3 × 10

Figure 35-2.ꢀExternal Voltage Source

Rev. 30-000001A

7/18/2017

VMAXPEAK

VMINPEAK

VPEAK

ZCPINV

35.2

ZCD Logic Output

The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active.

The OUT bit is set when the current sink is active, and cleared when the current source is active. The OUT bit is

affected by the polarity bit.

The OUT signal can also be used as input to other modules. This is controlled by the registers of the corresponding

module. OUT can be used as follows:

•

Gate source for TMR1/3/5

Clock source for TMR2/4/6

Reset source for TMR2/4/6

35.3

35.4

ZCD Logic Polarity

The POL bit inverts the OUT bit relative to the current source and sink output. When the POL bit is set, a OUT high

indicates that the current source is active, and a low output indicates that the current sink is active.

The POL bit affects the ZCD interrupts.

ZCD Interrupts

An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set.

A rising edge detector and a falling edge detector are present in the ZCD for this purpose.

The ZCDIF bit of the PIR2 register will be set when either edge detector is triggered and its associated enable bit is

set. The INTP bit in the ZCDxCON register enables rising edge interrupts and the INTN bit in the ZCDxCON register

enables falling edge interrupts.

To fully enable the interrupt, the following bits must be set:

•

ZCDIE bit of the PIE2 register

INTP bit for rising edge detection

INTN bit for falling edge detection

DS40002002B-page 571

Datasheet

PIC16(L)F18425/45

ZCD - Zero-Cross Detection Module

•

PEIE and GIE bits of the INTCON register

Changing the POL bit will cause an interrupt, regardless of the level of the SEN bit.

The ZCDIF bit of the PIR2 register must be cleared in software as part of the interrupt service. If another edge is

detected while this flag is being cleared, the flag will still be set at the end of the sequence.

Related Links

5.8.10 INTCON

7.7.13 PIR2

35.5

Correction for Z_CPINVOffset

The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD op amp.

For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross

event to occur either too early or too late.

35.5.1 Correction by AC Coupling

When the external voltage source is sinusoidal, the effects of the Z_CPINVoffset can be eliminated by isolating the

external voltage source from the ZCD pin with a capacitor, in addition to the voltage reducing resistor. The capacitor

will cause a phase shift resulting in the ZCD output switch in advance of the actual zero crossing event. The phase

shift will be the same for both rising and falling zero crossings, which can be compensated for by either delaying the

CPU response to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the

phase shift is negligible.

To determine the series resistor and capacitor values for this configuration, start by computing the impedance, Z, to

obtain a peak current of 300 μA. Next, arbitrarily select a suitably large non-polar capacitor and compute its

reactance, X_C, at the external voltage source frequency. Finally, compute the series resistor, capacitor peak voltage,

and phase shift by the formulas shown below.

When this technique is used and the input signal is not present, the ZCD will tend to oscillate. To avoid this

oscillation, connect the ZCD pin to V_DDor GND with a high-impedance resistor such as 200K.

Equation 35-2.ꢀR-C Equations

V_PEAK= external voltage source peak voltage

f = external voltage source frequency

C = series capacitor

R = series resistor

V_C= Peak capacitor voltage

Φ = Capacitor induced zero crossing phase advance in radians

T_Φ= Time ZC event occurs before actual zero crossing

ꢑ

ꢀꢝꢞꢤ

ꢱ =

−4

3 × 10

1

ꢥ =

ꢌ

2ꢲꢬꢌ

2

ꢌ

ꢉ = ꢱ − ꢥ

−4

ꢑ = ꢥ 3 × 10

ꢌ

ꢥ

ꢌ

−1

Φ = tan

ꢳ

ꢉ

Φ

2ꢲꢬ

ꢈ

=

Φ

DS40002002B-page 572

Datasheet

PIC16(L)F18425/45

ZCD - Zero-Cross Detection Module

Equation 35-3.ꢀR-C Calcuation Example

= 120

ꢑ

ꢄꢫꢍ

ꢑ

= ꢑ

× 2 = 169.7

ꢀꢝꢞꢤ

ꢄꢫꢍ

ꢬ = 60 ꢕꢧ

ꢌ = 0.1 ꢨꢢ

ꢑ

169.7

ꢀꢝꢞꢤ

ꢱ =

=

= 565.7 ꢩΩ

−4

3 × 10

1

ꢥ =

=

= 26.53 ꢩΩ

ꢌ

−7

2ꢲꢬꢌ

2ꢲ × 60 × 10

2

ꢉ = ꢱ − ꢥ = 565.1 ꢩΩ ꢎꢆꢫꢯꢒꢓꢃꢇ

ꢌ

ꢉ = 560 ꢩΩ ꢒꢍꢃꢇ

ꢏ

2

ꢱ =

ꢉ

+ ꢥ = 560.6 ꢩΩ

ꢉ

ꢏ ꢌ

ꢑ

ꢀꢝꢞꢤ

−6

ꢡ

=

= 302.7 × 10

ꢞ

ꢀꢝꢞꢤ

ꢱ

ꢉ

ꢑ = ꢥ × ꢡ

= 8.0 ꢑ

ꢌ

ꢀꢝꢞꢤ

ꢥ

ꢌ

−1

Φ = tan

ꢳ

= 0.047ꢄꢏꢇꢅꢏꢛꢍ

ꢉ

Φ

2ꢲꢬ

ꢈ

=

= 125.6ꢨꢍ

Φ

35.5.2 Correction By Offset Current

When the waveform is varying relative to V_SS, then the zero cross is detected too early as the waveform falls and too

late as the waveform rises. When the waveform is varying relative to V_DD, then the zero cross is detected too late as

the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal

waveforms with the corresponding equations shown below.

Equation 35-4.ꢀZCD Event Offset

When External Voltage source is relative to V_SS

ꢱ

ꢌꢀꢡꢠꢑ

−1

sin

ꢑ

ꢀꢝꢞꢤ

ꢈ

=

ꢆꢬꢬꢍꢃꢓ

2ꢲꢬ

When External Voltage source is relative to V_DD

ꢑ

− ꢱ

ꢌꢀꢡꢠꢑ

ꢙꢙ

−1

sin

ꢑ

ꢀꢝꢞꢤ

ꢈ

=

ꢆꢬꢬꢍꢃꢓ

2ꢲꢬ

This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up

resistor is used when the external voltage source is varying relative to V_SS. A pull-down resistor is used when the

voltage is varying relative to V_DD. The resistor adds a bias to the ZCD pin so that the target external voltage source

must go to zero to pull the pin voltage to the Z_CPINVswitching voltage. The pull-up or pull-down value can be

determined with the equations shown below.

Equation 35-5.ꢀZCD Pull-up/Pull-down Resistor

When External Voltage source is relative to V_SS

DS40002002B-page 573

Datasheet

PIC16(L)F18425/45

ZCD - Zero-Cross Detection Module

ꢉ

ꢑ

− ꢱ

ꢋꢝꢉꢡꢝꢋ ꢯꢒꢐꢐꢒꢯ ꢌꢀꢡꢠꢑ

ꢉ

=

ꢯꢒꢐꢐꢒꢯ

ꢱ

ꢌꢀꢡꢠꢑ

When External Voltage source is relative to V_DD

ꢉ

ꢱ

ꢋꢝꢉꢡꢝꢋ ꢌꢀꢡꢠꢑ

ꢉ

=

ꢯꢒꢐꢐꢇꢆꢭꢛ

ꢑ

− ꢱ

ꢌꢀꢡꢠꢑ

ꢙꢙ

35.6

Handling V_PEAKVariations

If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD

current source and sink below the design maximum range of ± 600 μA and above a reasonable minimum range. A

general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To

ensure that the maximum current does not exceed ± 600 μA and the minimum is at least ± 100 μA, compute the

series resistance as shown in Equation 35-6. The compensating pull-up for this series resistance can be determined

with the equations shown in Equation 35-5 because the pull-up value is independent from the peak voltage.

Equation 35-6.ꢀSeries R for V range

ꢑ

+ ꢑ

ꢂꢞꢥ_ꢀꢝꢞꢤ

ꢂꢡꢠ_ꢀꢝꢞꢤ

−4

ꢉ

=

ꢋꢝꢉꢡꢝꢋ

7 × 10

35.7

35.8

Operation During Sleep

The ZCD current sources and interrupts are unaffected by Sleep.

Effects of a Reset

The ZCD circuit can be configured to default to the Active or Inactive state on Power-on Reset (POR). When the ZCD

Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the SEN bit

must be set to enable the ZCD module.

35.9

Disabling the ZCD Module

The ZCD module can be disabled in two ways:

1. The ZCD Configuration bit disables the ZCD module when set. When this is the case then the ZCD module will

be enabled by setting the SEN bit. When the ZCD bit is cleared, the ZCD is always enabled and the SEN bit

has no effect.

2. The ZCD can also be disabled using the ZCDMD bit of the PMD3 register. This is subject to the status of the

ZCD bit.

DS40002002B-page 574

Datasheet

PIC16(L)F18425/45

ZCD - Zero-Cross Detection Module

35.10 Register Summary: ZCD Control

Offset

Name

Bit Pos.

0x00

...

Reserved

ZCDCON

0x091E

0x091F

7:0

SEN

OUT

POL

INTP

INTN

35.11 Register Definitions: ZCD Control

DS40002002B-page 575

Datasheet

PIC16(L)F18425/45

ZCD - Zero-Cross Detection Module

35.11.1 ZCDCON

Name:ꢀ

Offset:ꢀ

ZCDCON

0x91F

Zero-Cross Detect Control Register

Bit

7

6

5

OUT

RO

x

4

3

2

1

INTP

R/W

0

INTN

R/W

0

SEN

R/W

0

POL

R/W

0

Access

Reset

Bit 7 – SENꢀZero-Cross Detect Software Enable bit

This bit is ignored when ZCD fuse is cleared.

Value

Condition

Description

X

ZCD Config fuse = 0 Zero-cross detect is always enabled. This bit is ignored.

1

ZCD Config fuse = 1 Zero-cross detect is enabled. ZCD pin is forced to output to source and sink

current.

0

ZCD Config fuse = 1 Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS

controls.

Bit 5 – OUTꢀZero-Cross Detect Data Output bit

Value

1

0

1

0

Condition

POL = 0

POL = 1

Description

ZCD pin is sinking current

ZCD pin is sourcing current

ZCD pin is sinking current

Bit 4 – POLꢀZero-Cross Detect Polarity bit

Value

Description

1

0

ZCD logic output is inverted

ZCD logic output is not inverted

Bit 1 – INTPꢀZero-Cross Detect Positive-Going Edge Interrupt Enable bit

Value

Description

1

0

ZCDIF bit is set on low-to-high ZCD_output transition

ZCDIF bit is unaffected by low-to-high ZCD_output transition

Bit 0 – INTNꢀZero-Cross Detect Negative-Going Edge Interrupt Enable bit

Value

Description

1

0

ZCDIF bit is set on high-to-low ZCD_output transition

ZCDIF bit is unaffected by high-to-low ZCD_output transition

DS40002002B-page 576

Datasheet

PIC16(L)F18425/45

Register Summary

36.

Register Summary

Offset

Name

Bit Pos.

0x00

0x01

0x02

0x03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x04

0x06

FSR0

FSR1

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PORTA

PORTB

PORTC

PCLATH[6:0]

GIE

PEIE

INTEDG

RA0

RA5

RB5

RC5

RA4

RB4

RC4

RA3

RA2

RC2

RA1

RC1

RB7

RC7

RB6

RC6

RC3

RC0

Reserved

0x11

0x12

0x13

0x14

0x15

...

TRISA

TRISB

TRISC

7:0

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

TRISB7

TRISC7

TRISB6

TRISC6

TRISC3

LATC3

Reserved

0x17

0x18

0x19

0x1A

0x1B

...

LATA

LATB

LATC

7:0

LATA5

LATB5

LATC5

LATA4

LATB4

LATC4

LATA2

LATC2

LATA1

LATC1

LATA0

LATC0

LATB7

LATC7

LATB6

LATC6

Reserved

0x7F

0x80

0x81

0x82

0x83

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

7:0

STATUS

7:0

TO

PD

Z

DC

C

7:0

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x84

0x86

FSR0

FSR1

15:8

7:0

15:8

7:0

0x88

0x89

0x8A

0x8B

BSR

BSR[5:0]

WREG

7:0

WREG[7:0]

PCLATH

INTCON

7:0

PCLATH[6:0]

7:0

GIE

PEIE

INTEDG

7:0

LTH[7:0]

0x8C

0x8E

0x90

0x92

0x94

ADLTH

ADUTH

ADERR

ADSTPT

ADFLTR

15:8

7:0

LTH[15:8]

UTH[7:0]

15:8

7:0

UTH[15:8]

ERR[7:0]

15:8

7:0

ERR[15:8]

STPT[7:0]

STPT[15:8]

FLTR[7:0]

FLTR[15:8]

ACC[7:0]

15:8

7:0

15:8

7:0

0x96

0x99

ADACC

ADCNT

15:8

23:16

7:0

ACC[15:8]

ACC[17:16]

CNT[7:0]

DS40002002B-page 577

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x9A

ADRPT

7:0

RPT[7:0]

PREV[7:0]

PREV[15:8]

RES[7:0]

0x9B

0x9D

ADPREV

15:8

7:0

ADRES

ADPCH

15:8

7:0

RES[15:8]

0x9F

0xA0

PCH[5:0]

...

Reserved

0xFF

0x0100

0x0101

0x0102

0x0103

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

15:8

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0104

0x0106

FSR0

FSR1

0x0108

0x0109

0x010A

0x010B

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

ACQ[7:0]

0x010C

0x010E

0x010F

ADACQ

ADCAP

ADPRE

ACQ[12:8]

CAP[4:0]

PRE[7:0]

PRE[12:8]

FRM

0x0111

0x0112

0x0113

0x0114

0x0115

0x0116

0x0117

0x0118

0x0119

0x011A

ADCON0

ADCON1

ADCON2

ADCON3

ADSTAT

ADREF

ON

CONT

IPEN

CS

GO

PPOL

PSIS

GPOL

CRS[2:0]

CALC[2:0]

LTHR

DSEN

ACLR

SOI

MD[2:0]

TMD[2:0]

STAT[2:0]

OV

UTHR

MATH

NREF

PREF[1:0]

ADACT

ACT[4:0]

ADCLK

CS[5:0]

RC1REG

TX1REG

RCREG[7:0]

TXREG[7:0]

SPBRG[7:0]

SPBRG[15:8]

0x011B

SP1BRG

0x011D

0x011E

RC1STA

TX1STA

SPEN

CSRC

RX9

TX9

SREN

TXEN

CREN

ADDEN

SENDB

BRG16

FERR

BRGH

OERR

TRMT

WUE

RX9D

TX9D

SYNC

SCKP

0x011F

0x0120

...

BAUD1CON

ABDOVF

RCIDL

ABDEN

Reserved

0x017F

0x0180

0x0181

0x0182

0x0183

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0184

0x0186

FSR0

FSR1

0x0188

0x0189

0x018A

0x018B

0x018C

0x018D

0x018E

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

SSP1BUF

SSP1ADD

SSP1MSK

PCLATH[6:0]

GIE

PEIE

INTEDG

MSK0

BUF[7:0]

ADD[7:0]

MSK[6:0]

DS40002002B-page 578

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x018F

0x0190

0x0191

0x0192

0x0193

...

SSP1STAT

SSP1CON1

SSP1CON2

SSP1CON3

7:0

SMP

WCOL

GCEN

ACKTIM

CKE

SSPOV

ACKSTAT

PCIE

D/A

P

S

R/W

SSPM[3:0]

UA

BF

SSPEN

ACKDT

SCIE

CKP

ACKEN

BOEN

RCEN

PEN

RSEN

AHEN

SEN

SDAHT

SBCDE

DHEN

Reserved

0x0195

0x0196

0x0197

0x0198

0x0199

0x019A

0x019B

0x019C

0x019D

...

SSP2BUF

SSP2ADD

SSP2MSK

SSP2STAT

SSP2CON1

SSP2CON2

SSP2CON3

7:0

BUF[7:0]

ADD[7:0]

MSK[6:0]

MSK0

BF

SMP

WCOL

GCEN

ACKTIM

CKE

SSPOV

ACKSTAT

PCIE

D/A

P

S

R/W

UA

SSPEN

ACKDT

SCIE

CKP

SSPM[3:0]

ACKEN

BOEN

RCEN

PEN

RSEN

AHEN

SEN

SDAHT

SBCDE

DHEN

Reserved

0x01FF

0x0200

0x0201

0x0202

0x0203

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

15:8

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0204

0x0206

FSR0

FSR1

0x0208

0x0209

0x020A

0x020B

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

GE

PEIE

INTEDG

ON

TMRx[7:0]

TMRx[15:8]

0x020C

TMR1

0x020E

0x020F

0x0210

0x0211

T1CON

T1GCON

CKPS[1:0]

GTM GSPM

SYNC

GVAL

RD16

GPOL

GGO/DONE

TMR1GATE

TMR1CLK

GSS[4:0]

CS[4:0]

TMRx[7:0]

TMRx[15:8]

0x0212

TMR3

0x0214

0x0215

0x0216

0x0217

T3CON

T3GCON

CKPS[1:0]

GTM GSPM

SYNC

GVAL

ON

GE

GPOL

GGO/DONE

TMR3GATE

TMR3CLK

GSS[4:0]

CS[4:0]

TMRx[7:0]

0x0218

TMR5

TMRx[15:8]

0x021A

0x021B

0x021C

0x021D

0x021E

0x021F

0x0220

...

T5CON

CKPS[1:0]

GTM GSPM

SYNC

GVAL

T5GCON

GGO/DONE

TMR5GATE

TMR5CLK

CCPTMRS0

CCPTMRS1

GSS[4:0]

CS[4:0]

C4TSEL[1:0]

C3TSEL[1:0]

P7TSEL[1:0]

C2TSEL[1:0]

P6TSEL[1:0]

C1TSEL[1:0]

Reserved

0x027F

0x0280

0x0281

0x0282

0x0283

INDF0

INDF1

PCL

7:0

15:8

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

0x0284

FSR0

FSR0[15:8]

DS40002002B-page 579

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

15:8

7:0

FSR1[7:0]

0x0286

FSR1

FSR1[15:8]

0x0288

0x0289

0x028A

0x028B

0x028C

0x028D

0x028E

0x028F

BSR

WREG

PCLATH

INTCON

T2TMR

T2PR

BSR[5:0]

WREG[7:0]

PCLATH[6:0]

GIE

PEIE

INTEDG

TxTMR[7:0]

TxPR[7:0]

T2CON

T2HLT

ON

CKPS[2:0]

CSYNC

OUTPS[3:0]

MODE[4:0]

PSYNC

CPOL

0x0290

0x0291

0x0292

0x0293

0x0294

0x0295

0x0296

0x0297

0x0298

0x0299

0x029A

0x029B

0x029C

0x029D

0x029E

0x029F

0x02A0

...

T2CLKCON

T2RST

CS[3:0]

RSEL[3:0]

T4TMR

TxTMR[7:0]

TxPR[7:0]

T4PR

T4CON

ON

CKPS[2:0]

CSYNC

OUTPS[3:0]

T4HLT

PSYNC

CPOL

MODE[4:0]

T4CLKCON

T4RST

CS[3:0]

RSEL[3:0]

T6TMR

TxTMR[7:0]

TxPR[7:0]

T6PR

T6CON

ON

CKPS[2:0]

CSYNC

OUTPS[3:0]

T6HLT

PSYNC

MODE[4:0]

T6CLKCON

T6RST

CS[3:0]

RSEL[3:0]

Reserved

ADCPCON0

7:0

CPON

CPRDY

Reserved

0x02FF

0x0300

0x0301

0x0302

0x0303

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

15:8

7:0

15:8

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0304

0x0306

FSR0

FSR1

0x0308

0x0309

0x030A

0x030B

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

EN

PEIE

INTEDG

CCPR[7:0]

CCPR[15:8]

FMT

0x030C

CCPR1

0x030E

0x030F

CCP1CON

CCP1CAP

OUT

MODE[3:0]

CTS[2:0]

CCPR[7:0]

CCPR[15:8]

FMT

0x0310

CCPR2

0x0312

0x0313

CCP2CON

CCP2CAP

EN

MODE[3:0]

CTS[2:0]

CCPR[7:0]

0x0314

CCPR3

CCPR[15:8]

0x0316

0x0317

CCP3CON

CCP3CAP

FMT

MODE[3:0]

CTS[2:0]

CCPR[7:0]

0x0318

CCPR4

CCPR[15:8]

0x031A

0x031B

CCP4CON

CCP4CAP

FMT

MODE[3:0]

CTS[2:0]

DS40002002B-page 580

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x031C

...

Reserved

0x037F

0x0380

0x0381

0x0382

0x0383

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0384

0x0386

FSR0

FSR1

0x0388

0x0389

0x038A

0x038B

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

EN

PEIE

INTEDG

DCL[1:0]

0x038C

PWM6DC

DCH[7:0]

0x038E

0x038F

PWM6CON

Reserved

OUT

POL

7:0

15:8

7:0

0x0390

PWM7DC

DCH[7:0]

0x0392

0x0393

...

PWM7CON

EN

GIE

Reserved

0x03FF

0x0400

0x0401

0x0402

0x0403

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0404

0x0406

FSR0

FSR1

0x0408

0x0409

0x040A

0x040B

0x040C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

PEIE

INTEDG

Reserved

0x047F

0x0480

0x0481

0x0482

0x0483

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

7:0

STATUS

7:0

TO

PD

Z

DC

C

7:0

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0484

0x0486

FSR0

FSR1

15:8

7:0

15:8

7:0

0x0488

0x0489

0x048A

0x048B

BSR

BSR[5:0]

WREG

7:0

WREG[7:0]

PCLATH

INTCON

7:0

PCLATH[6:0]

7:0

PEIE

INTEDG

7:0

TMR[7:0]

0x048C

0x048F

SMT1TMR

SMT1CPR

15:8

23:16

7:0

TMR[15:8]

TMR[23:16]

CPR[7:0]

15:8

23:16

CPR[15:8]

CPR[23:16]

DS40002002B-page 581

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

15:8

23:16

7:0

CPW[7:0]

CPW[15:8]

CPW[23:16]

PR[7:0]

0x0492

0x0495

SMT1CPW

SMT1PR

15:8

23:16

7:0

PR[15:8]

PR[23:16]

0x0498

0x0499

0x049A

0x049B

0x049C

0x049D

0x049E

...

SMT1CON0

SMT1CON1

SMT1STAT

SMT1CLK

SMT1SIG

EN

GO

STP

WPOL

SPOL

CPOL

MODE[3:0]

PS[1:0]

7:0

REPEAT

CPWUP

7:0

CPRUP

RST

TS

WS

CSEL[2:0]

AS

7:0

SSEL[4:0]

WSEL[4:0]

SMT1WIN

7:0

Reserved

0x04FF

0x0500

0x0501

0x0502

0x0503

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0504

0x0506

FSR0

FSR1

0x0508

0x0509

0x050A

0x050B

0x050C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x057F

0x0580

0x0581

0x0582

0x0583

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

7:0

STATUS

7:0

TO

PD

Z

DC

C

7:0

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0584

0x0586

FSR0

FSR1

15:8

7:0

15:8

7:0

0x0588

0x0589

0x058A

0x058B

BSR

BSR[5:0]

WREG

7:0

WREG[7:0]

PCLATH

INTCON

7:0

PCLATH[6:0]

7:0

GIE

PEIE

INTEDG

7:0

ACC[7:0]

0x058C

0x058F

NCO1ACC

NCO1INC

15:8

23:16

7:0

ACC[15:8]

ACC[23:16]

INC[7:0]

15:8

23:16

7:0

INC[15:8]

INC[19:16]

0x0592

0x0593

0x0594

...

NCO1CON

NCO1CLK

EN

OUT

POL

PFM

7:0

PWS[2:0]

CKS[3:0]

Reserved

0x059B

0x059C

0x059D

0x059E

0x059F

TMR0L

TMR0H

T0CON0

T0CON1

7:0

TMR0L[7:0]

TMR0H[7:0]

T016BIT

T0EN

T0OUT

T0OUTPS[3:0]

T0CKPS[3:0]

T0CS[2:0]

T0ASYNC

DS40002002B-page 582

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x05A0

...

Reserved

0x05FF

0x0600

0x0601

0x0602

0x0603

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0604

0x0606

FSR0

FSR1

0x0608

0x0609

0x060A

0x060B

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

CS

0x060C

0x060D

0x060E

0x060F

0x0610

0x0611

0x0612

0x0613

0x0614

0x0615

0x0616

0x0617

0x0618

0x0619

0x061A

0x061B

0x061C

0x061D

0x061E

0x061F

...

CWG1CLK

CWG1ISM

CWG1DBR

CWG1DBF

CWG1CON0

CWG1CON1

CWG1AS0

CWG1AS1

CWG1STR

Reserved

ISM[3:0]

DBR[5:0]

DBF[5:0]

EN

LD

MODE[2:0]

POLB

IN

POLD

POLC

POLA

SHUTDOWN

OVRD

REN

LSBD[1:0]

LSAC[1:0]

AS5E

AS4E

AS3E

STRD

AS2E

STRC

AS1E

STRB

AS0E

STRA

OVRC

OVRB

OVRA

CWG2CLK

CWG2ISM

CWG2DBR

CWG2DBF

CWG2CON0

CWG2CON1

CWG2AS0

CWG2AS1

CWG2STR

7:0

CS

ISM[3:0]

DBR[5:0]

DBF[5:0]

EN

LD

MODE[2:0]

POLB

IN

POLD

POLC

POLA

SHUTDOWN

OVRD

REN

LSBD[1:0]

LSAC[1:0]

AS5E

AS4E

AS3E

STRD

AS2E

STRC

AS1E

STRB

AS0E

STRA

OVRC

OVRB

OVRA

Reserved

0x067F

0x0680

0x0681

0x0682

0x0683

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0684

0x0686

FSR0

FSR1

0x0688

0x0689

0x068A

0x068B

0x068C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x06FF

0x0700

0x0701

0x0702

0x0703

INDF0

INDF1

PCL

7:0

15:8

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

0x0704

FSR0

FSR0[15:8]

DS40002002B-page 583

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

15:8

7:0

FSR1[7:0]

0x0706

FSR1

FSR1[15:8]

0x0708

0x0709

0x070A

0x070B

0x070C

0x070D

0x070E

0x070F

0x0710

0x0711

0x0712

0x0713

0x0714

0x0715

0x0716

0x0717

0x0718

0x0719

0x071A

0x071B

0x071C

0x071D

0x071E

0x071F

...

BSR

WREG

PCLATH

INTCON

PIR0

BSR[5:0]

WREG[7:0]

PCLATH[6:0]

GIE

PEIE

INTEDG

INTF

TMR0IF

IOCIF

PIR1

OSFIF

CSWIF

ZCDIF

ADTIF

C2IF

ADIF

PIR2

C1IF

PIR3

RC1IF

TMR6IF

CL24IF

TX1IF

TMR5IF

CLC1IF

BCL2IF

TMR4IF

SSP2IF

TMR3IF

TMR5GIF

CCP3IF

BCL1IF

TMR2IF

TMR3GIF

CCP2IF

CWG2IF

SSP1IF

TMR1IF

TMR1GIF

CCP1IF

CWG1IF

SMT1IF

PIR4

PIR5

CLC4IF

CLC3IF

PIR6

CCP4IF

PIR7

NVMIF

NCO1IF

IOCIE

PIR8

SMT1PWAIF SMT1PRAIF

Reserved

PIE0

7:0

TMR0IE

INTE

ADIE

PIE1

OSFIE

CSWIE

ZCDIE

ADTIE

C2IE

PIE2

C1IE

PIE3

RC1IE

TMR6IE

CLC2IE

TX1IE

TMR5IE

CLC1IE

BCL2IE

TMR4IE

SSP2IE

TMR3IE

TMR5GIE

CCP3IE

BCL1IE

TMR2IE

TMR3GIE

CCP2IE

CWG2IE

SSP1IE

TMR1IE

TMR1GIE

CCP1IE

CWG1IE

SMT1IE

PIE4

PIE5

CLC4IE

CLC3IE

PIE6

CCP4IE

PIE7

NVMIE

NCO1IE

PIE8

SMT1PWAIE SMT1PRAIE

Reserved

0x077F

0x0780

0x0781

0x0782

0x0783

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0784

0x0786

FSR0

FSR1

0x0788

0x0789

0x078A

0x078B

0x078C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x0795

0x0796

0x0797

0x0798

0x0799

0x079A

0x079B

0x079C

0x079D

0x079E

...

PMD0

PMD1

PMD2

PMD3

PMD4

PMD5

PMD6

PMD7

7:0

SYSCMD

NCO1MD

FVRMD

NVMMD

CLKRMD

TMR1MD

IOCMD

TMR6MD

TMR5MD

TMR4MD

TMR3MD

CCP4MD

CLC3MD

TMR2MD

TMR0MD

DAC1MD

PWM7MD

CWG2MD

ADCMD

PWM6MD

CWG1MD

C2MD

C1MD

ZCDMD

CCP3MD

CCP2MD

CCP1MD

UART1MD

CLC4MD

MSSP2MD

CLC1MD

MSSP1MD

DSM1MD

SMT1MD

CLC2MD

Reserved

0x07FF

0x0800

0x0801

0x0802

0x0803

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

DS40002002B-page 584

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

15:8

7:0

15:8

7:0

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0804

0x0806

FSR0

FSR1

0x0808

0x0809

0x080A

0x080B

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

SEN

0x080C

0x080D

0x080E

0x080F

0x0810

0x0811

0x0812

0x0813

0x0814

0x0815

...

WDTCON0

WDTCON1

WDTPSL

WDTPSH

WDTTMR

BORCON

VREGCON

PCON0

WDTPS[4:0]

WDTCS[2:0]

WDTTMR[4:0]

WDTWV

WINDOW[2:0]

PSCNTL[7:0]

PSCNTH[7:0]

STATE

RI

PSCNT[1:0]

SBOREN

STKOVF

BORRDY

VREGPM

POR

STKUNF

RWDT

RMCLR

BOR

PCON1

MEMV

Reserved

0x0819

7:0

15:8

7:0

NVMADR[7:0]

NVMADR[14:8]

NVMDAT[7:0]

0x081A

0x081C

NVMADR

NVMDAT

15:8

7:0

NVMDAT[13:8]

WRERR WREN

0x081E

0x081F

0x0820

...

NVMCON1

NVMCON2

NVMREGS

LWLO

FREE

WR

RD

7:0

NVMCON2[7:0]

Reserved

0x087F

0x0880

0x0881

0x0882

0x0883

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0884

0x0886

FSR0

FSR1

0x0888

0x0889

0x088A

0x088B

0x088C

0x088D

0x088E

0x088F

0x0890

0x0891

0x0892

0x0893

0x0894

0x0895

0x0896

0x0897

0x0898

0x0899

0x089A

0x089B

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

PCLATH[6:0]

INTCON

GIE

PEIE

INTEDG

PLLR

CPUDOZE

OSCCON1

OSCCON2

OSCCON3

OSCSTAT

OSCEN

IDLEN

DOZEN

ROI

DOE

DOZE[2:0]

NOSC[2:0]

COSC[2:0]

NDIV[3:0]

CDIV[3:0]

CSWHOLD SOSCPWR

ORDY

LFOR

NOSCR

SOR

EXTOR

HFOR

MFOR

ADOR

ADOEN

EXTOEN

HFOEN

MFOEN

LFOEN

SOSCEN

OSCTUNE

OSCFRQ

Reserved

CLKRCON

CLKRCLK

MD1CON0

MD1CON1

MD1SRC

MD1CARL

MD1CARH

HFTUN[5:0]

HFFRQ[2:0]

DIV[2:0]

7:0

EN

DC[1:0]

CLK[3:0]

OUT

OPOL

BIT

CHPOL

CHSYNC

CLPOL

CLSYNC

SRCS[4:0]

CLS[3:0]

CHS[3:0]

DS40002002B-page 585

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x089C

...

Reserved

0x08FF

0x0900

0x0901

0x0902

0x0903

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0904

0x0906

FSR0

FSR1

0x0908

0x0909

0x090A

0x090B

0x090C

0x090D

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

FVRCON

Reserved

PCLATH[6:0]

GIE

PEIE

INTEDG

FVREN

FVRRDY

TSEN

OE1

TSRNG

CDAFVR[1:0]

ADFVR[1:0]

0x090E

0x090F

0x0910

...

DAC1CON0

DAC1CON1

7:0

EN

PSS[1:0]

DAC1R[4:0]

NSS

Reserved

ZCDCON

Reserved

0x091E

0x091F

0x0920

...

7:0

SEN

OUT

POL

INTP

INTN

0x097F

0x0980

0x0981

0x0982

0x0983

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0984

0x0986

FSR0

FSR1

0x0988

0x0989

0x098A

0x098B

0x098C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x098E

0x098F

0x0990

0x0991

0x0992

0x0993

0x0994

0x0995

0x0996

0x0997

0x0998

...

CMOUT

CM1CON0

CM1CON1

CM1NCH

CM1PCH

CM2CON0

CM2CON1

CM2NCH

CM2PCH

7:0

MC2OUT

HYS

MC1OUT

SYNC

EN

OUT

POL

INTP

INTN

NCH[2:0]

PCH[2:0]

HYS

SYNC

INTN

INTP

NCH[2:0]

PCH[2:0]

Reserved

0x09FF

0x0A00

0x0A01

0x0A02

0x0A03

INDF0

INDF1

PCL

7:0

15:8

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

0x0A04

FSR0

FSR0[15:8]

DS40002002B-page 586

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

15:8

7:0

FSR1[7:0]

0x0A06

FSR1

FSR1[15:8]

0x0A08

0x0A09

0x0A0A

0x0A0B

0x0A0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x0A7F

0x0A80

0x0A81

0x0A82

0x0A83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0A84

0x0A86

FSR0

FSR1

0x0A88

0x0A89

0x0A8A

0x0A8B

0x0A8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x0AFF

0x0B00

0x0B01

0x0B02

0x0B03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0B04

0x0B06

FSR0

FSR1

0x0B08

0x0B09

0x0B0A

0x0B0B

0x0B0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x0B7F

0x0B80

0x0B81

0x0B82

0x0B83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0B84

0x0B86

FSR0

FSR1

0x0B88

0x0B89

0x0B8A

0x0B8B

0x0B8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x0BFF

0x0C00

0x0C01

0x0C02

0x0C03

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

DS40002002B-page 587

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

15:8

7:0

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0C04

0x0C06

FSR0

FSR1

15:8

7:0

0x0C08

0x0C09

0x0C0A

0x0C0B

0x0C0C

...

BSR

BSR[5:0]

WREG

7:0

WREG[7:0]

PCLATH

INTCON

7:0

PCLATH[6:0]

7:0

GIE

PEIE

INTEDG

Reserved

0x0C7F

0x0C80

0x0C81

0x0C82

0x0C83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0C84

0x0C86

FSR0

FSR1

0x0C88

0x0C89

0x0C8A

0x0C8B

0x0C8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x0CFF

0x0D00

0x0D01

0x0D02

0x0D03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0D04

0x0D06

FSR0

FSR1

0x0D08

0x0D09

0x0D0A

0x0D0B

0x0D0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x0D7F

0x0D80

0x0D81

0x0D82

0x0D83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0D84

0x0D86

FSR0

FSR1

0x0D88

0x0D89

0x0D8A

0x0D8B

0x0D8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x0DFF

0x0E00

0x0E01

0x0E02

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

DS40002002B-page 588

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x0E03

STATUS

7:0

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0E04

0x0E06

FSR0

FSR1

15:8

7:0

15:8

7:0

0x0E08

0x0E09

0x0E0A

0x0E0B

0x0E0C

...

BSR

BSR[5:0]

WREG

7:0

WREG[7:0]

PCLATH

INTCON

7:0

PCLATH[6:0]

7:0

GIE

PEIE

INTEDG

Reserved

0x0E7F

0x0E80

0x0E81

0x0E82

0x0E83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0E84

0x0E86

FSR0

FSR1

0x0E88

0x0E89

0x0E8A

0x0E8B

0x0E8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x0EFF

0x0F00

0x0F01

0x0F02

0x0F03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0F04

0x0F06

FSR0

FSR1

0x0F08

0x0F09

0x0F0A

0x0F0B

0x0F0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x0F7F

0x0F80

0x0F81

0x0F82

0x0F83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

Z

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x0F84

0x0F86

FSR0

FSR1

0x0F88

0x0F89

0x0F8A

0x0F8B

0x0F8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

STKPTR

0x0FEC

0x0FED

7:0

STKPTR[4:0]

DS40002002B-page 589

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

TOS[7:0]

0x0FEE

TOS

15:8

TOS[15:8]

0x0FF0

...

Reserved

0x0FFF

0x1000

0x1001

0x1002

0x1003

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1004

0x1006

FSR0

FSR1

0x1008

0x1009

0x100A

0x100B

0x100C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x107F

0x1080

0x1081

0x1082

0x1083

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1084

0x1086

FSR0

FSR1

0x1088

0x1089

0x108A

0x108B

0x108C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x10FF

0x1100

0x1101

0x1102

0x1103

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1104

0x1106

FSR0

FSR1

0x1108

0x1109

0x110A

0x110B

0x110C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x117F

0x1180

0x1181

0x1182

0x1183

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

7:0

STATUS

7:0

PD

C

7:0

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1184

FSR0

15:8

7:0

0x1186

0x1188

FSR1

BSR

15:8

7:0

BSR[5:0]

DS40002002B-page 590

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1189

0x118A

0x118B

0x118C

...

WREG

PCLATH

INTCON

7:0

WREG[7:0]

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x11FF

0x1200

0x1201

0x1202

0x1203

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1204

0x1206

FSR0

FSR1

0x1208

0x1209

0x120A

0x120B

0x120C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x127F

0x1280

0x1281

0x1282

0x1283

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1284

0x1286

FSR0

FSR1

0x1288

0x1289

0x128A

0x128B

0x128C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x12FF

0x1300

0x1301

0x1302

0x1303

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1304

0x1306

FSR0

FSR1

0x1308

0x1309

0x130A

0x130B

0x130C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x137F

0x1380

0x1381

0x1382

0x1383

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

7:0

STATUS

7:0

PD

C

7:0

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1384

0x1386

FSR0

FSR1

15:8

7:0

15:8

DS40002002B-page 591

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1388

0x1389

0x138A

0x138B

0x138C

...

BSR

7:0

BSR[5:0]

WREG

WREG[7:0]

PCLATH[6:0]

PCLATH

INTCON

GIE

PEIE

INTEDG

Reserved

0x13FF

0x1400

0x1401

0x1402

0x1403

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1404

0x1406

FSR0

FSR1

0x1408

0x1409

0x140A

0x140B

0x140C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x147F

0x1480

0x1481

0x1482

0x1483

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1484

0x1486

FSR0

FSR1

0x1488

0x1489

0x148A

0x148B

0x148C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x14FF

0x1500

0x1501

0x1502

0x1503

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1504

0x1506

FSR0

FSR1

0x1508

0x1509

0x150A

0x150B

0x150C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x157F

0x1580

0x1581

0x1582

0x1583

INDF0

INDF1

PCL

7:0

15:8

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

0x1584

FSR0

FSR0[15:8]

DS40002002B-page 592

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

15:8

7:0

FSR1[7:0]

0x1586

FSR1

FSR1[15:8]

0x1588

0x1589

0x158A

0x158B

0x158C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x15FF

0x1600

0x1601

0x1602

0x1603

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1604

0x1606

FSR0

FSR1

0x1608

0x1609

0x160A

0x160B

0x160C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x167F

0x1680

0x1681

0x1682

0x1683

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1684

0x1686

FSR0

FSR1

0x1688

0x1689

0x168A

0x168B

0x168C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x16FF

0x1700

0x1701

0x1702

0x1703

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1704

0x1706

FSR0

FSR1

0x1708

0x1709

0x170A

0x170B

0x170C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x177F

0x1780

0x1781

0x1782

0x1783

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

DS40002002B-page 593

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

7:0

15:8

7:0

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1784

0x1786

FSR0

FSR1

15:8

7:0

0x1788

0x1789

0x178A

0x178B

0x178C

...

BSR

BSR[5:0]

WREG

7:0

WREG[7:0]

PCLATH

INTCON

7:0

PCLATH[6:0]

7:0

GIE

PEIE

INTEDG

Reserved

0x17FF

0x1800

0x1801

0x1802

0x1803

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1804

0x1806

FSR0

FSR1

0x1808

0x1809

0x180A

0x180B

0x180C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x187F

0x1880

0x1881

0x1882

0x1883

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1884

0x1886

FSR0

FSR1

0x1888

0x1889

0x188A

0x188B

0x188C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x18FF

0x1900

0x1901

0x1902

0x1903

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1904

0x1906

FSR0

FSR1

0x1908

0x1909

0x190A

0x190B

0x190C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x197F

0x1980

0x1981

0x1982

INDF0

INDF1

PCL

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

DS40002002B-page 594

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1983

STATUS

7:0

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1984

0x1986

FSR0

FSR1

15:8

7:0

15:8

7:0

0x1988

0x1989

0x198A

0x198B

0x198C

...

BSR

BSR[5:0]

WREG

7:0

WREG[7:0]

PCLATH

INTCON

7:0

PCLATH[6:0]

7:0

GIE

PEIE

INTEDG

Reserved

0x19FF

0x1A00

0x1A01

0x1A02

0x1A03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1A04

0x1A06

FSR0

FSR1

0x1A08

0x1A09

0x1A0A

0x1A0B

0x1A0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x1A7F

0x1A80

0x1A81

0x1A82

0x1A83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1A84

0x1A86

FSR0

FSR1

0x1A88

0x1A89

0x1A8A

0x1A8B

0x1A8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x1AFF

0x1B00

0x1B01

0x1B02

0x1B03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1B04

0x1B06

FSR0

FSR1

0x1B08

0x1B09

0x1B0A

0x1B0B

0x1B0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x1B7F

0x1B80

0x1B81

INDF0

INDF1

7:0

INDF0[7:0]

INDF1[7:0]

DS40002002B-page 595

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1B82

0x1B83

PCL

7:0

15:8

7:0

15:8

7:0

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1B84

0x1B86

FSR0

FSR1

0x1B88

0x1B89

0x1B8A

0x1B8B

0x1B8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x1BFF

0x1C00

0x1C01

0x1C02

0x1C03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1C04

0x1C06

FSR0

FSR1

0x1C08

0x1C09

0x1C0A

0x1C0B

0x1C0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x1C7F

0x1C80

0x1C81

0x1C82

0x1C83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1C84

0x1C86

FSR0

FSR1

0x1C88

0x1C89

0x1C8A

0x1C8B

0x1C8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

0x1CFF

0x1D00

0x1D01

0x1D02

0x1D03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

PD

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1D04

0x1D06

FSR0

FSR1

0x1D08

0x1D09

0x1D0A

0x1D0B

0x1D0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

INTEDG

Reserved

INDF0

0x1D7F

0x1D80

7:0

INDF0[7:0]

DS40002002B-page 596

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1D81

0x1D82

0x1D83

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1D84

0x1D86

FSR0

FSR1

0x1D88

0x1D89

0x1D8A

0x1D8B

0x1D8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x1DFF

0x1E00

0x1E01

0x1E02

0x1E03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1E04

0x1E06

FSR0

FSR1

0x1E08

0x1E09

0x1E0A

0x1E0B

0x1E0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x1E0E

0x1E0F

CLCDATA

7:0

MLC4OUT

INTN

MLC3OUT

G3POL

MLC2OUT

MODE[2:0]

G2POL

MLC1OUT

G1POL

0x1E10

0x1E11

0x1E12

0x1E13

0x1E14

0x1E15

0x1E16

0x1E17

0x1E18

0x1E19

0x1E1A

0x1E1B

0x1E1C

0x1E1D

0x1E1E

0x1E1F

0x1E20

0x1E21

0x1E22

0x1E23

0x1E24

0x1E25

0x1E26

0x1E27

0x1E28

0x1E29

0x1E2A

0x1E2B

0x1E2C

CLC1CON

CLC1POL

CLC1SEL0

CLC1SEL1

CLC1SEL2

CLC1SEL3

CLC1GLS0

CLC1GLS1

CLC1GLS2

CLC1GLS3

CLC2CON

CLC2POL

CLC2SEL0

CLC2SEL1

CLC2SEL2

CLC2SEL3

CLC2GLS0

CLC2GLS1

CLC2GLS2

CLC2GLS3

CLC3CON

CLC3POL

CLC3SEL0

CLC3SEL1

CLC3SEL2

CLC3SEL3

CLC3GLS0

CLC3GLS1

CLC3GLS2

EN

OUT

INTP

POL

G4POL

D1S[5:0]

D2S[5:0]

D3S[5:0]

D4S[5:0]

G1D4T

G2D4T

G3D4T

G4D4T

EN

G1D4N

G2D4N

G3D4N

G4D4N

G1D3T

G2D3T

G3D3T

G4D3T

OUT

G1D3N

G2D3N

G3D3N

G4D3N

INTP

G1D2T

G1D2N

G2D2N

G3D2N

G4D2N

G1D1T

G2D1T

G1D1N

G2D1N

G3D1N

G4D1N

G2D2T

G3D2T

G4D2T

INTN

G3D1T

G4D1T

MODE[2:0]

G2POL

POL

G4POL

G3POL

G1POL

D1S[5:0]

D2S[5:0]

D3S[5:0]

D4S[5:0]

G1D4T

G2D4T

G3D4T

G4D4T

EN

G1D4N

G2D4N

G3D4N

G4D4N

G1D3T

G2D3T

G3D3T

G4D3T

OUT

G1D3N

G2D3N

G3D3N

G4D3N

INTP

G1D2T

G1D2N

G2D2N

G3D2N

G4D2N

G1D1T

G2D1T

G1D1N

G2D1N

G3D1N

G4D1N

G2D2T

G3D2T

G4D2T

INTN

G3D1T

G4D1T

MODE[2:0]

G2POL

POL

G4POL

G3POL

G1POL

D1S[5:0]

D2S[5:0]

D3S[5:0]

D4S[5:0]

G1D4T

G2D4T

G3D4T

G1D4N

G2D4N

G3D4N

G1D3T

G2D3T

G3D3T

G1D3N

G2D3N

G3D3N

G1D2T

G1D2N

G2D2N

G3D2N

G1D1T

G2D1T

G3D1T

G1D1N

G2D1N

G3D1N

G2D2T

G3D2T

DS40002002B-page 597

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1E2D

0x1E2E

0x1E2F

0x1E30

0x1E31

0x1E32

0x1E33

0x1E34

0x1E35

0x1E36

0x1E37

0x1E38

...

CLC3GLS3

CLC4CON

CLC4POL

CLC4SEL0

CLC4SEL1

CLC4SEL2

CLC4SEL3

CLC4GLS0

CLC4GLS1

CLC4GLS2

CLC4GLS3

7:0

G4D4T

EN

G4D4N

G4D3T

OUT

G4D3N

INTP

G4D2T

INTN

G4D2N

G3POL

G4D1T

MODE[2:0]

G2POL

G4D1N

G1POL

POL

G4POL

D1S[5:0]

D2S[5:0]

D3S[5:0]

D4S[5:0]

G1D4T

G2D4T

G3D4T

G4D4T

G1D4N

G2D4N

G3D4N

G4D4N

G1D3T

G2D3T

G3D3T

G4D3T

G1D3N

G2D3N

G3D3N

G4D3N

G1D2T

G1D2N

G2D2N

G3D2N

G4D2N

G1D1T

G2D1T

G3D1T

G4D1T

G1D1N

G2D1N

G3D1N

G4D1N

G2D2T

G3D2T

G4D2T

Reserved

0x1E7F

0x1E80

0x1E81

0x1E82

0x1E83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1E84

0x1E86

FSR0

FSR1

0x1E88

0x1E89

0x1E8A

0x1E8B

0x1E8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x1E8E

0x1E8F

0x1E90

0x1E91

0x1E92

0x1E93

0x1E94

0x1E95

0x1E96

0x1E97

0x1E98

...

PPSLOCK

INTPPS

7:0

PPSLOCKED

PORT[1:0]

PIN[2:0]

T0CKIPPS

T1CKIPPS

T1GPPS

PORT[1:0]

T3CKIPPS

T3GPPS

T5CKIPPS

T5GPPS

Reserved

0x1E9B

0x1E9C

0x1E9D

0x1E9E

0x1E9F

...

T2INPPS

T4INPPS

T6INPPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EA0

0x1EA1

0x1EA2

0x1EA3

0x1EA4

0x1EA5

...

CCP1PPS

CCP2PPS

CCP3PPS

CCP4PPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EA8

0x1EA9

0x1EAA

0x1EAB

...

SMT1WINPPS

SMT1SIGPPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EB0

DS40002002B-page 598

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1EB1

0x1EB2

0x1EB3

...

CWG1PPS

CWG2PPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EB7

0x1EB8

0x1EB9

0x1EBA

0x1EBB

0x1EBC

0x1EBD

0x1EBE

0x1EBF

...

MDCARLPPS

MDCARHPPS

MDSRCPPS

CLCIN1PPS

CLCIN2PPS

CLCIN3PPS

CLCIN4PPS

7:0

PORT[1:0]

PIN[2:0]

Reserved

0x1EC2

0x1EC3

0x1EC4

0x1EC5

0x1EC6

0x1EC7

0x1EC8

0x1EC9

0x1ECA

0x1ECB

0x1ECC

0x1ECD

...

ADACTPPS

Reserved

7:0

PORT[1:0]

PIN[2:0]

SSP1CLKPPS

SSP1DATPPS

SSP1SSPPS

SSP2CLKPPS

SSP2DATPPS

SSP2SSPPS

RX1PPS

7:0

PORT[1:0]

PIN[2:0]

CK1PPS

Reserved

0x1EFF

0x1F00

0x1F01

0x1F02

0x1F03

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1F04

0x1F06

FSR0

FSR1

0x1F08

0x1F09

0x1F0A

0x1F0B

0x1F0C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x1F0F

0x1F10

0x1F11

0x1F12

0x1F13

0x1F14

0x1F15

0x1F16

...

RA0PPS

RA1PPS

RA2PPS

Reserved

RA4PPS

RA5PPS

7:0

PPS[5:0]

7:0

PPS[5:0]

Reserved

0x1F1B

0x1F1C

0x1F1D

0x1F1E

0x1F1F

0x1F20

0x1F21

0x1F22

RB4PPS

RB5PPS

RB6PPS

RB7PPS

RC0PPS

RC1PPS

RC2PPS

7:0

PPS[5:0]

DS40002002B-page 599

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1F23

0x1F24

0x1F25

0x1F26

0x1F27

0x1F28

...

RC3PPS

RC4PPS

RC5PPS

RC6PPS

RC7PPS

7:0

PPS[5:0]

Reserved

0x1F37

0x1F38

0x1F39

0x1F3A

ANSELA

WPUA

7:0

ANSELA5

WPUA5

ODCA5

SLRA5

ANSELA4

WPUA4

ODCA4

SLRA4

ANSELA2

ANSELA1

WPUA1

ODCA1

SLRA1

ANSELA0

WPUA0

ODCA0

SLRA0

WPUA3

WPUA2

ODCA2

SLRA2

ODCONA

0x1F3B

0x1F3C

0x1F3D

0x1F3E

0x1F3F

0x1F40

...

SLRCONA

INLVLA

IOCAP

INLVLA5

IOCAP5

IOCAN5

IOCAF5

INLVLA4

IOCAP4

IOCAN4

IOCAF4

INLVLA3

IOCAP3

IOCAN3

IOCAF3

INLVLA2

IOCAP2

IOCAN2

IOCAF2

INLVLA1

IOCAP1

IOCAN1

IOCAF1

INLVLA0

IOCAP0

IOCAN0

IOCAF0

IOCAN

IOCAF

Reserved

0x1F42

0x1F43

0x1F44

0x1F45

0x1F46

0x1F47

0x1F48

0x1F49

0x1F4A

0x1F4B

...

ANSELB

WPUB

7:0

ANSELB7

WPUB7

ODCB7

SLRB7

ANSELB6

WPUB6

ODCB6

SLRB6

ANSELB5

WPUB5

ODCB5

SLRB5

ANSELB4

WPUB4

ODCB4

SLRB4

ODCONB

SLRCONB

INLVLB

IOCBP

INLVLB7

IOCBP7

IOCBN7

IOCBF7

INLVLB6

IOCBP6

IOCBN6

IOCBF6

INLVLB5

IOCBP5

IOCBN5

IOCBF5

INLVLB4

IOCBP4

IOCBN4

IOCBF4

IOCBN

IOCBF

Reserved

0x1F4D

0x1F4E

0x1F4F

0x1F50

0x1F51

0x1F52

0x1F53

0x1F54

0x1F55

0x1F56

...

ANSELC

WPUC

7:0

ANSELC7

WPUC7

ODCC7

SLRC7

ANSELC6

WPUC6

ODCC6

SLRC6

ANSELC5

WPUC5

ODCC5

SLRC5

ANSELC4

WPUC4

ODCC4

SLRC4

ANSELC3

WPUC3

ODCC3

SLRC3

ANSELC2

WPUC2

ODCC2

SLRC2

ANSELC1

WPUC1

ODCC1

SLRC1

ANSELC0

WPUC0

ODCC0

SLRC0

ODCONC

SLRCONC

INLVLC

IOCCP

INLVLC7

IOCCP7

IOCCN7

IOCCF7

INLVLC6

IOCCP6

IOCCN6

IOCCF6

INLVLC5

IOCCP5

IOCCN5

IOCCF5

INLVLC4

IOCCP4

IOCCN4

IOCCF4

INLVLC3

IOCCP3

IOCCN3

IOCCF3

INLVLC2

IOCCP2

IOCCN2

IOCCF2

INLVLC1

IOCCP1

IOCCN1

IOCCF1

INLVLC0

IOCCP0

IOCCN0

IOCCF0

IOCCN

IOCCF

Reserved

0x1F7F

0x1F80

0x1F81

0x1F82

0x1F83

INDF0

INDF1

PCL

7:0

15:8

7:0

15:8

7:0

INDF0[7:0]

INDF1[7:0]

PCL[7:0]

STATUS

TO

PD

Z

DC

C

FSR0[7:0]

FSR0[15:8]

FSR1[7:0]

FSR1[15:8]

0x1F84

0x1F86

FSR0

FSR1

0x1F88

0x1F89

0x1F8A

0x1F8B

0x1F8C

...

BSR

BSR[5:0]

WREG

WREG[7:0]

PCLATH

INTCON

PCLATH[6:0]

GIE

PEIE

INTEDG

Reserved

0x1FE3

0x1FE4

0x1FE5

0x1FE6

STATUS_SHAD

WREG_SHAD

BSR_SHAD

7:0

TO

PD

Z

DC

C

WREG[7:0]

BSR[5:0]

DS40002002B-page 600

Datasheet

PIC16(L)F18425/45

Register Summary

...........continued

Offset

Name

Bit Pos.

0x1FE7

0x1FE8

PCLATH_SHAD

FSR0_SHAD

7:0

PCLATH[6:0]

FSR0_SHAD[7:0]

15:8

7:0

FSR1_SHAD[7:0]

0x1FEA

FSR1_SHAD

15:8

DS40002002B-page 601

Datasheet

PIC16(L)F18425/45

™

ICSP - In-Circuit Serial Programming

™

37.

ICSP - In-Circuit Serial Programming

™

ICSP programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can

be done after the assembly process, allowing the device to be programmed with the most recent firmware or a

™

custom firmware. Five pins are needed for ICSP programming:

•

ICSPCLK

ICSPDAT

MCLR/V_PP

V_DD

V_SS

In Program/Verify mode the program memory, User IDs and the Configuration Words are programmed through serial

communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is

™

the clock input. For more information on ICSP refer to “Memory Programming Specification” (DS40001970A).

37.1

37.2

High-Voltage Programming Entry Mode

The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low

then raising the voltage on MCLR/V_PPto V_IHH

.

Low-Voltage Programming Entry Mode

The Low-Voltage Programming Entry mode allows the PIC^®Flash MCUs to be programmed using V_DDonly, without

high voltage. When the LVP bit of Configuration Word 4 is set to ‘1’, the low-voltage ICSP programming entry is

enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’.

Entry into the Low-Voltage Programming Entry mode requires the following steps:

1. MCLR is brought to V_IL.

2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK.

Once the key sequence is complete, MCLR must be held at V_ILfor as long as Program/Verify mode is to be

maintained.

If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be

disabled. See the MCLR Section for more information.

The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode.

Related Links

10.4 MCLR Reset

37.3

Common Programming Interfaces

Connection to a target device is typically done through an ICSP header. A commonly found connector on

™

development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 37-1.

DS40002002B-page 602

Datasheet

PIC16(L)F18425/45

™

ICSP - In-Circuit Serial Programming

Figure 37-1.ꢀICD RJ-11 Style Connector Interface

ICSPDAT

NC

2 4 6

VDD

ICSPCLK

1 3

5

Target

PC Board

VPP/MCLR

VSS

Bottom Side

Pin Description*

1 = V_PP/MCLR

2 = V_DDTarget

3 = V_SS(ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

™

Another connector often found in use with the PICkit programmers is a standard 6-pin header with 0.1 inch spacing.

Refer to Figure 37-2.

For additional interface recommendations, refer to the specific device programmer manual prior to PCB design.

It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of

isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even

jumpers. See Figure 37-3 for more information.

™

Figure 37-2.ꢀPICkit Programmer Style Connector Interface

Pin 1 Indicator

1

2

3

4

5

6

Pin Description⁽¹⁾

1 = V_PP/MCLR

2 = V_DDTarget

3 = V_SS(ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

Note:ꢀ

1. Note:ꢀ The 6-pin header (0.100" spacing) accepts 0.025" square pins.

DS40002002B-page 603

Datasheet

PIC16(L)F18425/45

™

ICSP - In-Circuit Serial Programming

™

Figure 37-3.ꢀTypical Connection for ICSP Programming

External

Programming

Signals

Device to be

Programmed

VDD

VPP

VSS

MCLR/VPP

VSS

Data

ICSPDAT

ICSPCLK

Clock

*

To Normal Connections

Isolation devices (as required).

*

DS40002002B-page 604

Datasheet

PIC16(L)F18425/45

Instruction Set Summary

38.

Instruction Set Summary

PIC16(L)F18425/45 devices incorporate the standard set of 50 PIC16 core instructions. Each instruction is a 14-bit

word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad

categories:

•

Byte Oriented

Bit Oriented

Literal and Control

The literal and control category contains the most varied instruction word format.

The Instruction Set table lists the instructions recognized by the MPASM^™assembler.

All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or

three cycles:

•

Subroutine entry takes two cycles (CALL, CALLW)

Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE)

Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)

One additional instruction cycle will be used when any instruction references an indirect file register and the file

select register is pointing to program memory.

One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal

instruction execution rate of 1 MHz.

All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal

digit.

38.1

Read-Modify-Write Operations

Any WRITEinstruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified, and the result is stored according to either the working (W)

register, or the originating file register, depending on the state of the destination designator 'd' (see the table below for

more information). A read operation is performed on a register even if the instruction writes to that register.

Table 38-1.ꢀOpcode Field Descriptions

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

k

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

x

It is the recommended form of use for compatibility with all Microchip software tools.

Destination select; d = 0: store result in W, d = 1: store result in file register f.

FSR or INDF number. (0-1)

d

n

mm

Prepost increment-decrement mode selection

Table 38-2.ꢀAbbreviation Descriptions

Field

Description

PC

Program Counter

DS40002002B-page 605

Datasheet

PIC16(L)F18425/45

Instruction Set Summary

...........continued

Field

Description

Time-Out bit

Carry bit

TO

C

DC

Z

Digit Carry bit

Zero bit

PD

Power-Down bit

38.2

Standard Instruction Set

Table 38-3.ꢀInstruction Set

Mnemonic,

Operands

14-Bit Opcode

Status

Affected

Description

Cycles

MSb

Notes

LSb

BYTE-ORIENTED OPERATIONS

ADDWF f, d

ADDWFC f, d

ANDWF f, d

Add WREG and f

Add WREG and CARRY bit to f

AND WREG with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

1

C, DC, Z

2

00

11

00

11

00

0111

1101

0101

0111

0101

0110

0001

1001

0011

1010

0100

1000

0000

1101

1100

dfff

lfff

0000

dfff

1fff

dfff

ffff

00xx

ffff

C, DC, Z

Z

C, Z

Z

ASRF

LSLF

f, d

f

LSRF

CLRF

CLRW

COMF

DECF

INCF

–

Clear WREG

Z

f, d

f

Complement f

Z

2

Decrement f

Z

Increment f

Z

IORWF

MOVF

MOVWF

RLF

Inclusive OR WREG with f

Move f

Z

Move WREG to f

Rotate Left f through Carry

Rotate Right f through Carry

None

C

f, d

RRF

C

DS40002002B-page 606

Datasheet

PIC16(L)F18425/45

Instruction Set Summary

...........continued

Mnemonic,

14-Bit Opcode

Status

Affected

Description

Cycles

Notes

Operands

MSb

LSb

SUBWF f, d

SUBWFB f, d

SWAPF f, d

XORWF f, d

Subtract WREG from f

1

C, DC, Z

None

2

00

0010

1011

1110

0110

dfff

ffff

Subtract WREG from f with

borrow

1

2

11

00

ffff

Swap nibbles in f

Exclusive OR WREG with f

Z

BYTE ORIENTED SKIP OPERATIONS

DECFSZ f, d

INCFSZ f, d

Decrement f, Skip if 0

1(2)

None

1, 2

00

1011

1111

dfff

ffff

Increment f, Skip if 0

1(2)

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

f, b

Bit Clear f

1

None

2

01

00bb

01bb

bfff

ffff

Bit Set f

1

01

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS

f, b

Bit Test f, Skip if Clear

1(2)

None

1, 2

01

10bb

11bb

bfff

ffff

Bit Test f, Skip if Set

1(2)

1010

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

k

Add literal and WREG

AND literal with WREG

Inclusive OR literal with WREG

Move literal to BSR

1

C, DC, Z

Z

11

00

11

1110

1001

1000

000

kkkk

0k

kkkk

Z

None

C, DC, Z

Z

Move literal to PCLATH

Move literal to W

0001

0000

1100

1010

1kkk

kkkk

Subtract W from literal

Exclusive OR literal with W

CONTROL OPERATIONS

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Instruction Set Summary

...........continued

Mnemonic,

14-Bit Opcode

Status

Affected

Description

Cycles

Notes

Operands

MSb

LSb

BRA

k

—

k

Relative Branch

2

None

11

001k

0000

0kkk

0000

1kkk

0000

0100

0000

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

BRW

Relative Branch with WREG

Call Subroutine

2

00

10

00

10

00

11

00

1011

kkkk

1010

kkkk

1001

kkkk

1000

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN

—

k

Call Subroutine with WREG

Go to address

k

Return from interrupt

Return with literal in WREG

Return from Subroutine

k

—

INHERENT OPERATIONS

CLRWDT

NOP

—

f

Clear Watchdog Timer

1

TO, PD

None

00

0000

0110

0000

0110

0100

0000

0001

0011

0fff

No Operation

RESET

SLEEP

TRIS

Software device Reset

Go into Standby or Idle mode

Load TRIS register with WREG

None

TO, PD

None

C-COMPILER OPTIMIZED

ADDFSR n, k

n, mm

Add Literal k to FSRn

1

None

11

00

11

00

11

0001

0000

1111

0000

1111

0nkk

0001

0nkk

0001

1nkk

kkkk

0nmm

kkkk

1nmm

kkkk

Move Indirect FSRn to WREG with pre/post inc/dec

modifier, mm

Z

2, 3

2

MOVIW

k[n]

Move INDFn to WREG, Indexed Indirect.

n, mm

Move WREG to Indirect FSRn with pre/post inc/dec

modifier, mm

None 2, 3

None

MOVWI

k[n]

Move WREG to INDFn, Indexed Indirect.

2

Note:ꢀ

1. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

2. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will

require one additional instruction cycle.

3. Details on MOVIWand MOVWIinstruction descriptions are available in the next section.

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Instruction Set Summary

38.2.1 Standard Instruction Set

ADDFSR

Add Literal to FSRn

Syntax:

[ label ] ADDFSR FSRn, k

-32 ≤ k ≤ 31;

n ∈ [ 0, 1]

Operands:

Operation:

FSR(n) + k → FSR(n)

None

Status

Affected:

The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.

FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to

wrap-around.

Description:

ADDLW

ADD literal to W

Syntax:

[ label ] ADDLW k

Operands:

Operation:

Status Affected:

Description:

0 ≤ k ≤ 255

(W) + k → (W)

C, DC, Z

The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.

ADDWF

ADD W to f

Syntax:

[ label ] ADDWF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(W) + (f) → dest

Status Affected: C, DC, Z

Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

Description:

ADDWFC

ADD W and CARRY bit to f

Syntax:

[ label ] ADDWFC f {,d}

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(W) + (f) + (C) → dest

C, DC, Z

Status Affected:

Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.

Description:

ANDLW

AND literal with W

[ label ] ANDLW k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

(W) .AND. k → (W)

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Instruction Set Summary

...........continued

ANDLW

AND literal with W

Status Affected:

Description:

Z

The contents of W are AND’ed with the 8-bit literal ‘k’.

The result is placed in W.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(W) .AND. (f) → dest

Z

Status Affected:

AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

Description:

ASRF

Arithmetic Right Shift

Syntax:

[ label ] ASRF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

(f[7]) → dest[7]

(f[7:1]) → dest[6:0]

(f[0]) → C

Operation:

Status Affected:

C, Z

The contents of register ‘f’ are shifted one bit to the right through the Carry flag.

The MSb remains unchanged.

If ‘d’ is ‘0’, the result is placed in W.

Description:

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

Register f → C

BCF

Bit Clear f

Syntax:

[ label ] BCF f, b

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

0 → f[b]

Status Affected:

Description:

None

Bit ‘b’ in register ‘f’ is cleared.

BRA

Relative Branch

[ label ] BRA label

[ label ] BRA $+k

Syntax:

-256 ≤ label - PC + ≤ 255

-256 ≤ k ≤ 255

Operands:

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Instruction Set Summary

...........continued

BRA

Relative Branch

(PC) + 1 + k → PC

None

Operation:

Status

Affected:

Add the signed 9-bit literal ‘k’ to the PC.

Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 +

k.

Description:

This instruction is a 2-cycle instruction. This branch has a limited range.

BRW

Relative Branch with W

[ label ] BRW

Syntax:

Operands:

Operation:

None

(PC) + (W) → PC

Status Affected: None

Add the contents of W (unsigned) to the PC.

Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 +

(W).

Description:

This instruction is a 2-cycle instruction.

BSF

Bit Set f

Syntax:

[ label ] BSF f, b

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

1 → (f[b])

Status Affected:

Description:

None

Bit ‘b’ in register ‘f’ is set.

BTFSC

Bit Test File, Skip if Clear

Syntax:

[ label ] BTFSC f, b

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

skip if (f[b]) = 0

None

Status Affected:

If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded,

and a NOPis executed instead, making this a 2-cycle instruction.

Description:

BTFSS

Bit Test File, Skip if Set

Syntax:

[ label ] BTFSS f, b

0 ≤ f ≤ 127

0 ≤ b < 7

Operands:

Operation:

skip if (f[b]) = 1

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Instruction Set Summary

...........continued

BTFSS

Bit Test File, Skip if Set

Status Affected:

None

If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed.

If bit ‘b’ is ‘1’, then the next instruction is discarded,

Description:

and a NOPis executed instead, making this a 2-cycle instruction.

CALL

Subroutine Call

[ label ] CALL k

0 ≤ k ≤ 2047

Syntax:

Operands:

(PC) + 1 → TOS,

k → PC[10:0],

Operation:

(PCLATH[6:3]) → PC[14:11]

None

Status Affected:

Call Subroutine. First, return address (PC + 1) is pushed onto the stack.

The 11-bit immediate address is loaded into PC bits [10:0].

The upper bits of the PC are loaded from PCLATH.

CALLis a 2-cycle instruction.

Description:

CALLW

Syntax:

Subroutine Call with W

[ label ] CALLW

None

Operands:

(PC) + 1 → TOS,

(W) → PC[7:0],

Operation:

(PCLATH[6:0]) → PC[14:8]

Status Affected: None

Subroutine call with W.

First, the return address (PC + 1) is pushed onto the return stack.

Then, the contents of W is loaded into PC[7:0], and the contents of PCLATH into PC[14:8].

CALLWis a 2-cycle instruction.

Description:

CLRF

Clear f

Syntax:

Operands:

[ label ] CLRF f

0 ≤ f ≤ 127

000h → f

1 → Z

Operation:

Status Affected:

Description:

Z

The contents of register ‘f’ are cleared and the Z bit is set.

CLRW

Clear W

Syntax:

Operands:

[ label ] CLRW

None

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Instruction Set Summary

...........continued

CLRW

Clear W

00h → (W)

1 → Z

Operation:

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z) is set.

CLRWDT

Syntax:

Clear Watchdog Timer

[ label ] CLRWDT

None

Operands:

00h → WDT,

00h → WDT prescaler,

Operation:

1 → TO,

1 → PD

Status Affected:

Description:

TO, PD

CLRWDTinstruction resets the

Watchdog Timer.

It also resets the prescaler of the WDT.

Status bits, TO and PD, are set.

COMF

Complement f

Syntax:

[ label ] COMF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(f) → dest

Z

Status Affected:

The contents of register ‘f’ are complemented.

If ‘d’ is ‘0’, the result is stored in W.

Description:

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

DECF

Decrement f

Syntax:

[ label ] DECF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(f) – 1 → dest

Z

Status Affected:

Decrement register ‘f’.

If ‘d’ is ‘0’, the result is stored in the W register.

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

Description:

DECFSZ

Decrement f, skip if 0

[ label ] DECFSZ f, d

Syntax:

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Instruction Set Summary

...........continued

DECFSZ

Decrement f, skip if 0

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(f) – 1 → dest,

skip if result = 0

The contents of register ‘f’ are decremented.

If ‘d’ is ‘0’, the result is placed in the W register.

If ‘d’ is ‘1’, the result is placed back in register ‘f’.

If the result is ‘1’, the next instruction is executed.

If the result is ‘0’, then a NOPis executed instead,

making it a 2-cycle instruction.

Description:

GOTO

Unconditional Branch

[ label ] GOTO k

0 ≤ k ≤ 2047

Syntax:

Operands:

k → PC[10:0]

PCLATH[6:3] → PC[14:11]

Operation:

Status Affected:

None

GOTOis an unconditional branch.

The 11-bit immediate value is loaded into PC bits [10:0].

The upper bits of PC are loaded from PCLATH[4:3].

GOTOis a 2-cycle instruction.

Description:

INCF

Increment f

Syntax:

[ label ] INCF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(f) + 1 → dest

Z

Status Affected:

The contents of register ‘f’ are incremented.

If ‘d’ is ‘0’, the result is placed in the W register.

If ‘d’ is ‘1’, the result is placed back in register ‘f’.

Description:

INCFSZ

Increment f, skip if 0

Syntax:

[ label ] INCFSZ f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

(f) + 1 → dest,

skip if result = 0

Operation:

Status Affected:

None

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Instruction Set Summary

...........continued

INCFSZ

Increment f, skip if 0

The contents of register ‘f’ are incremented.

If ‘d’ is ‘0’, the result is placed in the W register.

If ‘d’ is ‘1’, the result is placed back in register ‘f’.

If the result is ‘1’, the next instruction is executed.

If the result is ‘0’, a NOPis executed instead,

making it a 2-cycle instruction.

Description:

IORLW

Inclusive OR literal with W

[ label ] IORLW k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Status Affected:

Description:

(W) .OR. k → (W)

Z

The contents of W are ORed with the 8-bit literal ‘k’.

The result is placed in W.

IORWF

Inclusive OR W with f

Syntax:

IORWF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(W) .OR. (f) → dest

Z

Status Affected:

Inclusive OR the W register with register ‘f’.

If ‘d’ is ‘0’, the result is placed in the W register.

If ‘d’ is ‘1’, the result is placed back in register ‘f’.

Description:

LSLF

Logical Left Shift

Syntax:

[ label ] LSLF f {,d}

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

(f[7]) → C

(f[6:0]) → dest[7:1]

Operation:

0 → dest[0]

C, Z

Status Affected:

The contents of register ‘f’ are shifted one bit to the left through the Carry flag.

A ‘0’ is shifted into the LSb.

If ‘d’ is ‘0’, the result is placed in W.

Description:

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

C ← Register f ← 0

LSRF

Logical Right Shift

Syntax:

[ label ] LSRF f {,d}

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Instruction Set Summary

...........continued

LSRF

Logical Right Shift

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 → dest[7]

(f[7:1]) → dest[6:0],

Operation:

(f[0]) → C

C, Z

Status Affected:

The contents of register ‘f’ are shifted one bit to the right through the Carry flag.

A ‘0’ is shifted into the MSb.

If ‘d’ is ‘0’, the result is placed in W.

Description:

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

0 → register f → C

MOVF

Move f

Syntax:

[ label ] MOVF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

f → dest

Z

Status Affected:

The contents of register f is moved to a destination dependent upon the status of d.

If d = 0, destination is W register.

If d = 1, the destination is file register f itself.

Description:

d = 1is useful to test a file register since status flag Z is affected.

Words:

Cycles:

1

Example:

MOVF

FSR, 0

After Instruction

W = value in FSR register

Z = 1

MOVIW

Move INDFn to W

[ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

Syntax:

n ∈ [0,1]

mm ∈ [00,01,10,11]

Operands:

-32 ≤ k ≤ 31

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Instruction Set Summary

...........continued

MOVIW

Move INDFn to W

INDFn → (W)

Effective address is determined by

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

Operation:

After the Move, the FSR value will be either:

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Unchanged

Z

MODE

SYNTAX

mm

00

01

10

11

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

Status

Affected:

This instruction is used to move data between W and one of the indirect registers (INDFn).

Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it.

The INDFn registers are not physical registers.

Description:

Any instruction that accesses an INDFn register actually accesses the register at the address

specified by the FSRn.

FSRn is limited to the range 0000h - FFFFh.

Incrementing/decrementing it beyond these bounds will cause it to wrap-around.

MOVLB

Move literal to BSR

Syntax:

[ label ] MOVLB k

Operands:

Operation:

Status Affected:

Description:

0 ≤ k ≤ 127

k → BSR

None

The 6-bit literal ‘k’ is loaded into the Bank Select Register (BSR).

MOVLP

Move literal to PCLATH

Syntax:

[ label ] MOVLP k

Operands:

Operation:

Status Affected:

Description:

0 ≤ k ≤ 127

k → PCLATH

None

The 7-bit literal ‘k’ is loaded into the PCLATH register.

MOVLW

Syntax:

Move literal to W

[ label ] MOVLW k

0 ≤ k ≤ 255

Operands:

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Instruction Set Summary

...........continued

MOVLW

Move literal to W

k → (W)

Operation:

Status Affected:

Description:

None

The 8-bit literal ‘k’ is loaded into W register.

The “don’t cares” will assemble as ‘0’s.

Words:

Cycles:

1

Example:

MOVLW

5Ah

After Instruction

W = 5Ah

MOVWF

Move W to f

Syntax:

[ label ] MOVWF f

Operands:

Operation:

Status Affected:

Description:

Words:

0 ≤ f ≤ 127

(W) → f

None

Move data from W to register ‘f’.

1

Cycles:

Example:

MOVWF

LATA

Before Instruction

LATA = FFh

W = 4Fh

After Instruction

LATA = 4Fh

W = 4Fh

MOVWI

Move W to INDFn

[ label ] MOVWI ++FSRn

[ label ] MOVWI --FSRn

[ label ] MOVWI FSRn++

[ label ] MOVWI FSRn--

[ label ] MOVWI k[FSRn]

Syntax:

n ∈ [0,1]

mm ∈ [00,01,10,11]

Operands:

-32 ≤ k ≤ 31

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Instruction Set Summary

...........continued

MOVWI

Move W to INDFn

(W) → INDFn

Effective address is determined by

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

Operation:

After the Move, the FSR value will be either:

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Unchanged

None

MODE

SYNTAX

mm

00

01

10

11

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

Status

Affected:

This instruction is used to move data between W and one of the indirect registers (INDFn).

Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it.

The INDFn registers are not physical registers.

Any instruction that accesses an INDFn register actually accesses the register at the address

specified by the FSRn.

Description:

FSRn is limited to the range 0000h-FFFFh.

Incrementing/decrementing it beyond these bounds will cause it to wrap-around.

The increment/decrement operation on FSRn WILL NOT affect any Status bits.

NOP

No Operation

[ label ] NOP

None

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

No operation

None

No operation.

1

Cycles:

1

NOP

Example:

None.

RESET

Software Reset

[ label ] RESET

None

Syntax:

Operands:

Operation:

Execute a device Reset.

Resets the RI flag of the PCON register.

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Instruction Set Summary

...........continued

RESET

Software Reset

Status Affected:

Description:

None

This instruction provides a way to execute a hardware Reset by software.

RETFIE

Syntax:

Return from Interrupt

[ label ] RETFIE k

None

Operands:

(TOS) → PC,

1 → GIE

Operation:

Status Affected:

None

Return from Interrupt.

Stack is POPed and Top-of-Stack (TOS) is loaded in the PC.

Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON[7]).

This is a 2-cycle instruction.

Description:

Words:

Cycles:

1

2

Example:

RETFIE

After Interrupt

PC = TOS

GIE = 1

RETLW

Syntax:

Return literal to W

[ label ] RETLW k

0 ≤ k ≤ 255

Operands:

k → (W),

(TOS) → PC,

Operation:

Status Affected:

None

The W register is loaded with the 8-bit literal ‘k’.

The program counter is loaded from the top of the stack (the return address).

This is a 2-cycle instruction.

Description:

Words:

Cycles:

1

2

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Instruction Set Summary

Example:

CALL TABLE

; W contains table

; offset value

; W now has

; table value

:

TABLE

ADDWF PC

RETLW k1

RETLW k2

:

; W = offset

; Begin table

;

:

RETLW kn

; End of table

Before Instruction

W = 07h

After Instruction

W = value of k8

RETURN

Syntax:

Return from Subroutine

[ label ] RETURN

None

Operands:

Operation:

(TOS) → PC,

Status Affected: None

Encoding:

0000

0001

001s

Return from subroutine.

Description:

The stack is POPped and the top of the stack (TOS) is loaded into the Program Counter.

This is a 2-cycle instruction.

RLF

Rotate Left f through Carry

Syntax:

[ label ] RLF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

(f[n]) → dest[n + 1],

(f[7]) → C,

Operation:

(C) → dest[0]

C

Status Affected:

Encoding:

0011

01da

ffff

The contents of register ‘f’ are rotated one bit to the left through the CARRY flag.

If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).

Description:

register f

C

Words:

Cycles:

1

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Datasheet

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Instruction Set Summary

Example:

RLF

REG1, 0

Before Instruction

REG1 = 1110 0110

C = 0

After Instruction

REG = 1110 0110

W = 1100 1100

C = 1

RRF

Rotate Right f through Carry

Syntax:

[ label ] RRF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

(f[n]) → dest[n – 1],

(f[0]) → C,

Operation:

(C) → dest[7]

C

Status Affected:

The contents of register ‘f’ are rotated one bit to the right through the CARRY flag.

If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).

Description:

register f

C

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

Operands:

00h → WDT,

0 → WDT prescaler,

Operation:

1 → TO,

0 → PD

Status Affected:

Description:

TO, PD

The Power-down Status bit (PD) is cleared.

The Time-out Status bit (TO) is set.

Watchdog Timer and its prescaler are cleared.

SUBLW

Subtract W from literal

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

Operands:

Operation:

Status Affected:

k – (W) → (W)

C, DC, Z

DS40002002B-page 622

Datasheet

PIC16(L)F18425/45

Instruction Set Summary

...........continued

SUBLW

Subtract W from literal

The W register is subtracted (2’s complement method) from the 8-bit literal ‘k’.

The result is placed in the W register.

C =0, W > k

Description

C = 1, W ≤ k

DC = 0, W[3:0] > k[3:0]

DC = 1, W[3:0] ≤ k[3:0]

SUBWF

Subtract W from f

Syntax:

[ label ] SUBWF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(f) - (W) → (dest)

C, DC, Z

Status Affected:

Subtract (2’s complement method) W register from register ‘f’.

If ‘d’ is ‘0’, the result is stored in the W register.

If ‘d’ is ‘1’, the result is stored back in register ‘f.

C =0, W > f

Description

C = 1, W ≤ f

DC = 0, W[3:0] > f[3:0]

DC = 1, W[3:0] ≤ f[3:0]

SUBFWB

Subtract W from f with Borrow

Syntax:

[ label ] SUBFWB f {,d}

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(W) – (f) – (B) → dest

C, DC, Z

Status Affected:

Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s complement method).

If ‘d’ is ‘0’, the result is stored in W.

Description:

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

SWAPF

Swap Nibbles in f

Syntax:

[ label ] SWAPF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

(f[3:0]) → dest[7:4],

(f[7:4]) → dest[3:0]

Operation:

Status Affected:

None

DS40002002B-page 623

Datasheet

PIC16(L)F18425/45

Instruction Set Summary

...........continued

SWAPF

Swap Nibbles in f

The upper and lower nibbles of register ‘f’ are exchanged.

If ‘d’ is ‘0’, the result is placed in W.

Description:

If ‘d’ is ‘1’, the result is placed in register ‘f’ (default).

TRIS

Load TRIS Register with W

[ label ] TRIS f

Syntax:

Operands:

Operation:

Status Affected:

5 ≤ f ≤ 7

(W) → TRIS register ‘f’

None

Move data from W register to TRIS register.

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

Description:

When ‘f’ = 7, TRISC is loaded.

XORLW

Exclusive OR literal with W

[ label ] XORLW k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Status Affected:

(W) .XOR. k → (W)

Z

The contents of W are XORed with the 8-bit literal ‘k’.

The result is placed in W.

Description:

XORWF

Exclusive OR W with f

Syntax:

[ label ] XORWF f, d

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(W) .XOR. (f) → dest

Z

Status Affected:

Exclusive OR the contents of the W register with register ‘f’.

If ‘d’ is ‘0’, the result is stored in the W register.

Description:

If ‘d’ is ‘1’, the result is stored back in register ‘f’.

DS40002002B-page 624

Datasheet

PIC16(L)F18425/45

Development Support

39.

Development Support

The PIC microcontrollers (MCU) and dsPIC digital signal controllers (DSC) are supported with a full range of

®

software and hardware development tools:

•

Integrated Development Environment

®

– MPLAB X IDE Software

Compilers/Assemblers/Linkers

– MPLAB XC Compiler

– MPASM^™Assembler

– MPLINK^™Object Linker/

MPLIB^™Object Librarian

– MPLAB Assembler/Linker/Librarian for

Various Device Families

•

Simulators

– MPLAB X SIM Software Simulator

Emulators

™

– MPLAB REAL ICE In-Circuit Emulator

In-Circuit Debuggers/Programmers

– MPLAB ICD 3

™

– PICkit 3 In-Circuit Debugger

•

Device Programmers

– MPLAB PM3 Device Programmer

•

Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits

Third-party development tools

39.1

MPLAB X Integrated Development Environment Software

The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware

development tool that runs on Windows^®, Linux and Mac OS^®X. Based on the NetBeans IDE, MPLAB X IDE is an

entirely new IDE with a host of free software components and plug-ins for high-performance application development

and debugging. Moving between tools and upgrading from software simulators to hardware debugging and

programming tools is simple with the seamless user interface.

With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that

includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the

ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for

the needs of experienced users.

Feature-Rich Editor:

•

Color syntax highlighting

Smart code completion makes suggestions and provides hints as you type

Automatic code formatting based on user-defined rules

Live parsing

User-Friendly, Customizable Interface:

•

Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc.

Call graph window

Project-Based Workspaces:

•

Multiple projects

Multiple tools

Multiple configurations

DS40002002B-page 625

Datasheet

PIC16(L)F18425/45

Development Support

•

Simultaneous debugging sessions

File History and Bug Tracking:

•

Local file history feature

Built-in support for Bugzilla issue tracker

39.2

MPLAB XC Compilers

The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC

devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use.

MPLAB XC Compilers run on Windows, Linux or MAC OS X.

For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.

The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and

offer sufficient code optimization for most applications.

MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that

can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC

Compiler uses the assembler to produce its object file. Notable features of the assembler include:

•

Support for the entire device instruction set

Support for fixed-point and floating-point data

Command-line interface

Rich directive set

Flexible macro language

MPLAB X IDE compatibility

39.3

MPASM Assembler

The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel^®standard HEX files,

MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated

machine code, and COFF files for debugging.

The MPASM Assembler features include:

•

Integration into MPLAB X IDE projects

User-defined macros to streamline

assembly code

•

Conditional assembly for multipurpose

source files

Directives that allow complete control over the assembly process

39.4

MPLINK Object Linker/MPLIB Object Librarian

The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable

objects from precompiled libraries, using directives from a linker script.

The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a

routine from a library is called from a source file, only the modules that contain that routine will be linked in with the

application. This allows large libraries to be used efficiently in many different applications.

The object linker/library features include:

•

Efficient linking of single libraries instead of many smaller files

Enhanced code maintainability by grouping related modules together

Flexible creation of libraries with easy module listing, replacement, deletion and extraction

DS40002002B-page 626

Datasheet

PIC16(L)F18425/45

Development Support

39.5

MPLAB Assembler, Linker and Librarian for Various Device Families

MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and

dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates

relocatable object files that can then be archived or linked with other relocatable object files and archives to create an

executable file. Notable features of the assembler include:

•

Support for the entire device instruction set

Support for fixed-point and floating-point data

Command-line interface

Rich directive set

Flexible macro language

MPLAB X IDE compatibility

39.6

MPLAB X SIM Software Simulator

The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC

MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified

and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-

time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track

program execution, actions on I/O, most peripherals and internal registers.

The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the

MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of

the hardware laboratory environment, making it an excellent, economical software development tool.

39.7

MPLAB REAL ICE In-Circuit Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip

Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-

use, powerful graphical user interface of the MPLAB X IDE.

The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the

target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise

tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers

significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace

analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters)

interconnection cables.

39.8

39.9

MPLAB ICD 3 In-Circuit Debugger System

The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/

programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and

dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed USB 2.0

interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE

systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.

PICkit 3 In-Circuit Debugger/Programmer

The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most

affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is

connected to the design engineer’s PC using a full-speed USB interface and can be connected to the target via a

DS40002002B-page 627

Datasheet

PIC16(L)F18425/45

Development Support

Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two

™

device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming (ICSP ).

39.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage

verification at V_DDMINand V_DDMAXfor maximum reliability. It features a large LCD display (128 x 64) for menus and

error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable

assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify

and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage

and data applications.

39.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows

quick application development on fully functional systems. Most boards include prototyping areas for adding custom

circuitry and provide application firmware and source code for examination and modification.

The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional EEPROM memory.

The demonstration and development boards can be used in teaching environments, for prototyping custom circuits

and for learning about various microcontroller applications.

™

In addition to the PICDEM and dsPICDEM demonstration/development board series of circuits, Microchip has a

line of evaluation kits and demonstration software for analog filter design, KeeLoq^®security ICs, CAN, IrDA^®,

PowerSmart battery management, SEEVAL^®evaluation system, Sigma-Delta ADC, flow rate sensing, plus many

more.

Also available are starter kits that contain everything needed to experience the specified device. This usually includes

a single application and debug capability, all on one board.

Check the Microchip webpage (www.microchip.com) for the complete list of demonstration, development and

evaluation kits.

39.12 Third-Party Development Tools

Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer

good value and unique functionality.

•

Device Programmers and Gang Programmers from companies, such as SoftLog and CCS

Software Tools from companies, such as Gimpel and Trace Systems

Protocol Analyzers from companies, such as Saleae and Total Phase

Demonstration Boards from companies, such as MikroElektronika, Digilent^®and Olimex

Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika^®

DS40002002B-page 628

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.

Electrical Specifications

40.1

Absolute Maximum Ratings^(†)

Parameter

Rating

Ambient temperature under bias

Storage temperature

-40°C to +125°C

-65°C to +150°C

Voltage on pins with respect to V_SS

•

on V_DDpin:

<

PIC16LF18425/45

PIC16F18425/45

-0.3V to +4.0V

-0.3V to +6.5V

•

on MCLR pin:

-0.3V to +9.0V

on all other pins:

-0.3V to (V_DD+ 0.3V)

Maximum current

-40°C ≤ T_A≤ +85°C

85°C < T_A≤ +125°C

-40°C ≤ T_A≤ +85°C

85°C < T_A≤ +125°C

250 mA

120 mA

250 mA

85 mA

•

on V_SSpin⁽¹⁾

•

on V_DDpin⁽¹⁾

on any standard I/O pin

±50 mA

Clamp current, I_K(V_PIN< 0 or V_PIN> V_DD

Total power dissipation⁽²⁾

)

±20 mA

800 mW

Important:ꢀ

1. Maximum current rating requires even load distribution across I/O pins. Maximum current rating

may be limited by the device package power dissipation characterizations, see Thermal

Characteristics to calculate device specifications.

2. Power dissipation is calculated as follows:

P_DIS= V_DDx {I_DD- Σ I_OH} + Σ {(V_DD- V_OH) x I_OH} + Σ (V_OIx I_OL

)

3. Internal Power Dissipation is calculated as follows: P_INTERNAL= I_DDx V_DDwhere I_DDis current to run

the chip alone without driving any load on the output pins.

4. I/O Power Dissipation is calculated as follows: P_I/O=Σ(I_OL*V_OL)+Σ(I_OH*(V_DD-V_OH))

5. Derated Power is calculated as follows: P_DER= PD_MAX(T_J-T_A)/θ_JAwhere T_A=Ambient Temperature,

T_J= Junction Temperature.

NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

40.2

Standard Operating Conditions

The standard operating conditions for any device are defined as:

Operating Voltage:

V_DDMIN≤ V_DD≤ V_DDMAX

DS40002002B-page 629

Datasheet

PIC16(L)F18425/45

Electrical Specifications

T_{A_MIN}≤ T_A≤ T_{A_MAX}

Operating Temperature:

Parameter

Ratings

V_DD— Operating Supply Voltage⁽¹⁾

V_DDMIN(F_OSC≤ 16 MHz)

V_DDMIN(F_OSC≤ 32 MHz)

V_DDMAX

+1.8V

+2.5V

+3.6V

+2.3V

+2.5V

+5.5V

PIC16LF18425/45

PIC16F18425/45

V_DDMIN(F_OSC≤ 16 MHz)

V_DDMIN(F_OSC≤ 32 MHz)

V_DDMAX

T_A— Operating Ambient Temperature Range

T_{A_MIN}

-40°C

Industrial Temperature

T_{A_MAX}

T_{A_MIN}

T_{A_MAX}

+85°C

-40°C

Extended Temperature

+125°C

Note:ꢀ

1. See Parameter D002, DC Characteristics: Supply Voltage.

Figure 40-1.ꢀVoltage Frequency Graph, -40°C ≤ T_A≤ +125°C, for PIC16F18425/45 only

Rev. 30-000069C

10/27/2016

5.5

2.5

2.3

0

4

10

16

32

Frequency (MHz)

Note:ꢀ

1. The shaded region indicates the permissible combinations of voltage and frequency.

2. Refer to 40.4.1 External Clock/Oscillator Timing Requirements for each Oscillator mode’s supported

frequencies.

DS40002002B-page 630

Datasheet

PIC16(L)F18425/45

Electrical Specifications

Figure 40-2.ꢀVoltage Frequency Graph, -40°C ≤ T_A≤ +125°C, for PIC16LF18425/45 Devices only

Rev. 30-000070B

10/27/2017

3.6

2.5

1.8

0

4

10

16

32

Frequency (MHz)

Note:ꢀ

1. The shaded region indicates the permissible combinations of voltage and frequency.

2. Refer to 40.4.1 External Clock/Oscillator Timing Requirements for each Oscillator mode’s supported

frequencies.

Related Links

40.3.1 Supply Voltage

40.3

DC Characteristics

40.3.1 Supply Voltage

Table 40-1.ꢀ

PIC16LF18425/45 only

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

Supply Voltage

Characteristic

Min.

Typ.†

Max.

Units

Conditions

1.8

2.5

—

3.6

V

F_OSC≤ 16 MHz

F_OSC> 16 MHz

D002

RAM Data Retention⁽¹⁾

D003 V_DR

V_DD

Device in Sleep

mode

—

V

1.5

Power-on Reset Release Voltage⁽²⁾

DS40002002B-page 631

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

PIC16LF18425/45 only

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

D004 V_POR

Power-on Reset Rearm Voltage⁽²⁾

D005 V_PORR

Characteristic

Min.

Typ.†

Max.

Units

Conditions

BOR or LPBOR

disabled⁽³⁾

—

V

1.6

BOR or LPBOR

disabled⁽³⁾

—

V

0.8

—

V_DDRise Rate to ensure internal Power-on Reset signal⁽²⁾

D006 S_VDD0.05

BOR or LPBOR

disabled⁽³⁾

—

V/ms

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. This is the limit to which V_DDcan be lowered in Sleep mode without losing RAM data.

2. See the following figure, POR and POR REARM with Slow Rising V_DD

.

3. Please see 40.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power

Brown-Out Reset Specifications for BOR and LPBOR trip point information.

PIC16F18425/45 only

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

Supply Voltage

Characteristic

Min.

Typ.†

Max.

Units

Conditions

2.3

2.5

—

5.5

V

F_OSC≤ 16 MHz

F_OSC> 16 MHz

D002

RAM Data Retention⁽¹⁾

D003 V_DR

Power-on Reset Release Voltage⁽²⁾

D004 V_POR

Power-on Reset Rearm Voltage⁽²⁾

D005 V_PORR

V_DD

Device in Sleep

mode

—

V

1.7

—

BOR or LPBOR

disabled⁽³⁾

1.6

1.5

—

BOR or LPBOR

disabled⁽³⁾

—

V

V_DDRise Rate to ensure internal Power-on Reset signal⁽²⁾

D006 S_VDD0.05

BOR or LPBOR

disabled⁽³⁾

V/ms

DS40002002B-page 632

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

PIC16F18425/45 only

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

Characteristic

Min.

Typ.†

Max.

Units

Conditions

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. This is the limit to which V_DDcan be lowered in Sleep mode without losing RAM data.

2. See the following figure, POR and POR REARM with Slow Rising V_DD

.

3. Please see 40.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power

Brown-Out Reset Specifications for BOR and LPBOR trip point information.

Figure 40-3.ꢀPOR and POR Rearm with Slow Rising V_DD

VDD

VPOR

VPORR

SVDD

VSS

(1)

NPOR

POR REARM

VSS

Note:ꢀ

1. When N_PORis low, the device is held in Reset.

(1,2,4)

40.3.2 Supply Current (I_DD

)

Table 40-2.ꢀ

PIC16LF18425/45 only

Standard Operating Conditions (unless otherwise stated)

Conditions

V_DDNote

Device

Characteristics

Param. No. Sym.

Min.

Typ.†

Max.

Units

D100

D101

I_DD

XT = 4 MHz

—

465

2.1

670

2.6

μA

3.0V

XT4

HFINTOSC = 16

MHz

I_DD

mA

HFO16

DS40002002B-page 633

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

PIC16LF18425/45 only

Standard Operating Conditions (unless otherwise stated)

Conditions

Units

Device

Characteristics

Param. No. Sym.

Min.

Typ.†

Max.

V_DD

3.0V

Note

HFINTOSC = 32

MHz

D102

D103

I_DD

—

3.9

3.6

4.8

4.4

mA

HFOPLL

I_DD

HS+PLL = 32 MHz

HSPLL32

IDLE mode,

HFINTOSC = 16

MHz

D104

D105

I_DD

—

1.5

1.9

—

mA

3.0V

IDLE

DOZE mode,

HFINTOSC = 16

MHz, Doze Ratio =

16

(3)

I_DD

DOZE

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. The test conditions for all I_DDmeasurements in active operation mode are: OSC1 = external square wave,

from

rail-to-rail; all I/O pins are outputs driven low; MCLR = V_DD; WDT disabled.

2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

3. I_DD_DOZE= [I_DD*(N-1)/N] + I_DD16/N where N = DOZE Ratio (see CPUDOZE register).

IDLE

HFO

4. PMD bits are all in the default state, no modules are disabled.

PIC16F18425/45 only

Standard Operating Conditions (unless otherwise stated)

Conditions

V_DDNote

Device

Characteristics

Param. No. Sym.

Min.

Typ.†

Max.

Units

D100

D101

I_DD

XT = 4 MHz

—

515

2.2

710

2.7

μA

3.0V

XT4

HFINTOSC = 16

MHz

I_DD

mA

HFO16

HFINTOSC = 32

MHz

D102

D103

I_DD

—

4.0

3.7

4.9

4.5

mA

3.0V

HFOPLL

I_DD

HS+PLL = 32 MHz

HSPLL32

IDLE mode,

HFINTOSC = 16

MHz

D104

D105

I_DD

—

1.6

2.0

—

mA

3.0V

IDLE

DOZE mode,

HFINTOSC = 16

MHz, Doze Ratio =

16

(3)

I_DD

DOZE

DS40002002B-page 634

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

PIC16F18425/45 only

Standard Operating Conditions (unless otherwise stated)

Conditions

Units

Device

Characteristics

Param. No. Sym.

Min.

Typ.†

Max.

V_DD

Note

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. The test conditions for all I_DDmeasurements in active operation mode are: OSC1 = external square wave,

from

rail-to-rail; all I/O pins are outputs driven low; MCLR = V_DD; WDT disabled.

2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

3. I_DD_DOZE= [I_DD*(N-1)/N] + I_DD16/N where N = DOZE Ratio (see CPUDOZE register).

IDLE

HFO

4. PMD bits are all in the default state, no modules are disabled.

Related Links

12.5.2 CPUDOZE

(1,2)

40.3.3 Power-Down Current (I_PD

)

Table 40-3.ꢀ

PIC16LF18425/45 only

Standard Operating Conditions (unless otherwise stated)

Conditions

Param.

No.

Device

Characteristics

Max.

+85°C

Max.

+125°C

Sym.

Min.

Typ.†

Units

V_DD

Note

D200

D201

I_PD

I_PDBase

—

0.08

2.0

2.8

7

8

μA

3.0V

Low-Frequency

Internal

I_{PD_WDT}

—

0.8

μA

3.0V

Oscillator/WDT

Secondary

Oscillator (S_OSC

D202

D203

D204

I_{PD_SOSC}

I_{PD_FVR}

I_{PD_BOR}

—

1.0

46

10

3.8

76

15

9

μA

3.0V

)

FVR

77

18

Brown-out Reset

(BOR)

Low-Power

D205

I_{PD_LPBOR}

Brown-out Reset

(LPBOR)

—

0.13

2.2

8

μA

3.0V

ADC - Non-

converting

ADC not

converting ⁽⁴⁾

D207

D208

I_{PD_ADCA}

I_{PD_CMP}

—

0.08

30

2.0

57

7.0

58

μA

3.0V

Comparator

DS40002002B-page 635

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

PIC16LF18425/45 only

Standard Operating Conditions (unless otherwise stated)

Conditions

Units

Param.

No.

Device

Characteristics

Max.

+85°C

Max.

+125°C

Sym.

Min.

Typ.†

V_DD

Note

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. The peripheral current is the sum of the base I_DDand the additional current consumed when this peripheral is

enabled. The peripheral ∆ current can be determined by subtracting the base I_DDor I_PDcurrent from this limit.

Max. values should be used when calculating total current consumption.

2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to V_SS

.

3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is

available.

4. ADC clock source is FRC.

PIC16F18425/45 only

Standard Operating Conditions (unless otherwise stated), VREGPM = 1

Conditions

Param.

No.

Device

Characteristics

Max.

+85°C

Max.

+125°C

Sym.

Min.

Typ.†

Units

V_DD

3.0V

Note

D200

—

0.40

18

2.5

25

8

μA

I_PD

I_PDBase

VREGPM = 0

D200A

30

Low-Frequency

Internal

D201

I_{PD_WDT}

—

1.0

2.9

9

μA

3.0V

Oscillator/WDT

Secondary

Oscillator (S_OSC

D202

D203

D204

I_{PD_SOSC}

I_{PD_FVR}

I_{PD_BOR}

—

1.2

40

11

4.3

69

16

9.2

70

19

μA

3.0V

)

FVR

Brown-out Reset

(BOR)

ADC - Non-

converting

ADC not

converting ⁽⁴⁾

D207

D208

I_{PD_ADCA}

I_{PD_CMP}

—

0.38

31

2.5

58

8.0

59

μA

3.0V

Comparator

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. The peripheral current is the sum of the base I_DDand the additional current consumed when this peripheral is

enabled. The peripheral ∆ current can be determined by subtracting the base I_DDor I_PDcurrent from this limit.

Max. values should be used when calculating total current consumption.

2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to V_SS

.

3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is

available.

4. ADC clock source is FRC.

DS40002002B-page 636

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.3.4 I/O Ports

Table 40-4.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

Device Characteristics

Min.

Typ.†

Max.

Units

Conditions

Input Low Voltage

V_IL

I/O PORT:

D300

—

0.8

V

4.5V≤V_DD≤5.5V

1.8V≤V_DD≤4.5V

2.0V≤V_DD≤5.5V

•

with TTL buffer

D301

0.15 V_DD

0.2 V_DD

D302

•

with Schmitt Trigger

buffer

D303

D304

—

0.3 V_DD

0.8

V

•

with I²C levels

2.7V≤V_DD≤5.5V

with SMBus levels

D305

MCLR

0.2 V_DD

Input High Voltage

V_IH

I/O PORT:

D320

2.0

—

V

4.5V≤V_DD≤5.5V

1.8V≤V_DD≤4.5V

2.0V≤V_DD≤5.5V

•

with TTL buffer

D321

0.25 V_DD+0.8

0.8V_DD

D322

•

with Schmitt Trigger

buffer

D323

D324

0.7 V_DD

2.1

—

V

•

with I²C levels

2.7V≤V_DD≤5.5V

with SMBus levels

D325

MCLR

0.7 V_DD

Input Leakage Current⁽¹⁾

D340

D341

D342

I_IL

I/O PORTS

—

±5

±125

±1000

±200

nA

V_SS≤V_PIN≤V_DD,

Pin at high-impedance,

85°C

V_SS≤V_PIN≤V_DD

,

Pin at high-impedance,

125°C

MCLR⁽²⁾

±50

V_SS≤V_PIN≤V_DD,

Pin at high-impedance,

85°C

Weak Pull-up Current

D350 I_PUR

Output Low Voltage

D360 V_OL

25

—

120

—

200

0.6

μA

V

V_DD=3.0V, V_PIN=V_SS

Standard I/O PORTS

I_OL= 10 mA, V_DD

3.0V

=

Output High Voltage

D370

V_OH

V_DD-0.7

—

5

—

V

I_OH= 6 mA, V_DD= 3.0V

All I/O Pins

D380

C_IO

50

pF

DS40002002B-page 637

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

Device Characteristics

Min.

Typ.†

Max.

Units

Conditions

† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:ꢀ

1. Negative current is defined as current sourced by the pin.

2. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal

operating conditions. Higher leakage current may be measured at different input voltages.

40.3.5 Memory Programming Specifications

Table 40-5.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param

No.

Sym.

Device

Characteristics

Min.

Typ†

Max.

Units

Conditions

High Voltage Entry Programming Mode Specifications

MEM01

V_IHH

Voltage on

8

—

9

V

(Note 2, Note 3)

MCLR/V_PPpin to

enter programming

mode

MEM02

I_PPGM

Current on

MCLR/V_PPpin during

programming mode

—

1

—

mA

(Note 2)

(Note 4)

Programming Mode Specifications

MEM10

MEM11

V_BE

V_DDfor Bulk Erase

—

V

I_DDPGM

Supply Current during

Programming

10

mA

operation

Data EEPROM Memory Specifications

MEM20

E_D

DataEE Byte

Endurance

100k

—

40

—

E/W

Year

E/W

-40°C≤T_A≤+85°C

MEM21

T_{D_RET}

Characteristic

Retention

Provided no

other

specifications are

violated

—

MEM22

N_{D_REF}

Total Erase/Write

Cycles before

Refresh

100k

—

MEM23

MEM24

V_{D_RW}

V_DDfor Read or

Erase/Write operation

V_DDMIN

—

V_DDMAX

5.0

V

T_{D_BEW}

Byte Erase and Write

Cycle Time

4.0

ms

Program Flash Memory Specifications

MEM30

E_P

Flash Memory Cell

Endurance

-40°C≤Ta≤+85°C

(Note 1)

10k

—

E/W

DS40002002B-page 638

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param

No.

Sym.

Device

Characteristics

Min.

Typ†

Max.

Units

Conditions

MEM32

T_{P_RET}

Characteristic

Retention

Provided no

other

specifications are

violated

—

40

—

Year

MEM33

MEM34

MEM35

V_{P_RD}

V_DDfor Read

operation

V_DDMIN

—

V_DDMAX

V

V_{P_REW}

V_DDfor Row Erase or

Write operation

V_DDMIN

V_DDMAX

T_{P_REW}

Self-Timed Row

Erase or Self-Timed

Write

—

2.0

2.8

ms

† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-

Timed Write.

2. Required only if CONFIG4, bit LVP is disabled.

®

3. The MPLAB ICD2 does not support variable V_PPoutput. Circuitry to limit the ICD2 V_PPvoltage must be

placed between the ICD2 and target system when programming or debugging with the ICD2.

4. Refer to the “PIC16(L)F184XX Memory Programming Specification” document for description.

Related Links

4.7.4 CONFIG4

40.3.6 Thermal Characteristics

Table 40-6.ꢀ

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Param No. Sym.

TH01 θ_JA

Characteristic

Typ. Units Conditions

Thermal Resistance Junction to Ambient 70.0 °C/W 14-pin PDIP package

95.3 °C/W 14-pin SOIC package

100.0 °C/W 14-pin TSSOP package

51.5 °C/W 16-pin UQFN 4x4mm package

62.2 °C/W 20-pin PDIP package

87.3 °C/W 20-pin SSOP package

77.7 °C/W 20-pin SOIC package

43.0 °C/W 20-pin UQFN 4x4mm package

DS40002002B-page 639

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Param No. Sym.

Characteristic

Typ. Units Conditions

TH02

θ_JC

Thermal Resistance Junction to Case

32.75 °C/W 14-pin PDIP package

31.0 °C/W 14-pin SOIC package

24.4 °C/W 14-pin TSSOP package

5.4 °C/W 16-pin UQFN 4x4mm package

27.5 °C/W 20-pin PDIP package

31.1 °C/W 20-pin SSOP package

23.1 °C/W 20-pin SOIC package

5.3 °C/W 20-pin UQFN 4x4mm package

TH03

TH04

TH05

TH06

TH07

Note:ꢀ

T_JMAX

PD

Maximum Junction Temperature

Power Dissipation

150

—

°C

W

PD=P_INTERNAL+P_I/O

P_INTERNAL=I_DDxV_DD

(1)

P_INTERNALInternal Power Dissipation

—

P_I/O

I/O Power Dissipation

Derated Power

—

P_I/O=Σ(I_OL*V_OL)+Σ(I_OH*(V_DD-V_OH))

(2)

P_DER

—

P_DER=PD_MAX(T_J-T_A)/θ_JA

1. I_DDis current to run the chip alone without driving any load on the output pins.

2. T_A= Ambient Temperature, T_J= Junction Temperature.

40.4

AC Characteristics

Figure 40-4.ꢀLoad Conditions

Rev. 10-000133A

8/1/2013

Load Condition

CL

VSS

Legend: CL=50 pF for all pins

DS40002002B-page 640

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.4.1 External Clock/Oscillator Timing Requirements

Figure 40-5.ꢀClock Timing

OS2,

OS4,

OS6

CLKIN

Q4

Q1

Q2

Q3

Q4

Q1

OS1,OS3,OS5

OS7,OS8,OS9

OS10,OS20

CLKOUT

OS21

Note:ꢀ See table below.

Table 40-7.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

ECL Oscillator

Characteristic

Min.

Typ. †

Max.

Units

Conditions

OS1

OS2

F_ECL

Clock Frequency

Clock Duty Cycle

—

500

60

kHz

%

T_{ECL_DC}

40

ECM Oscillator

OS3

OS4

F_ECM

T_{ECM_DC}

Clock Frequency

Clock Duty Cycle

—

4

MHz

%

40

60

ECH Oscillator

OS5

OS6

F_ECH

T_{ECH_DC}

Clock Frequency

Clock Duty Cycle

—

32

60

MHz

%

40

LP Oscillator

OS7

F_LP

Clock Frequency

—

100

4

kHz

MHz

kHz

Note 4

XT Oscillator

OS8

F_XT

Note 4

HS Oscillator

OS9

F_HS

—

20

Note 4

Secondary Oscillator

OS10

System Oscillator

OS20 F_OSC

F_SEC

32.4

—

32.768

—

33.1

32

Note 4

System Clock

Frequency

MHz

(Note 2, Note 3)

DS40002002B-page 641

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

Characteristic

Min.

Typ. †

Max.

Units

Conditions

OS21

F_CY

Instruction

Frequency

—

F_OSC/4

—

MHz

OS22

T_CY

Instruction Period

125

1/F_CY

—

ns

* These parameters are characterized but not tested.

† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. Instruction cycle period (T_CY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min” values with an external

clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)

for all devices.

2. The system clock frequency (F_OSC) is selected by the “main clock switch controls” as described in the

“Oscillator Module (with Fail-Safe Clock Monitor)” section.

3. The system clock frequency (F_OSC) must meet the voltage requirements defined in the “Standard Operating

Conditions” section.

4. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device.

For clocking the device with the external square wave, one of the EC mode selections must be used.

Related Links

8. OSC - Oscillator Module

40.2 Standard Operating Conditions

40.4.2 Internal Oscillator Parameters⁽¹⁾

Table 40-8.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

Characteristic

Min.

Typ. †

4

Max.

Units

Conditions

OS50

F_HFOSC

Precision Calibrated

HFINTOSC

Frequency

—

MHz

(Note 2)

8

12

16

32

OS51

F_HFOSCLP

Low-Power

Optimized

HFINTOSC

Frequency

0.92

1.84

0.88

1.76

1

2

1

2

1.08

2.16

1.12

2.24

MHz

-40°C to 85°C

-40°C to 125°C

OS52

OS53

F_MFOSC

Internal Calibrated

MFINTOSC

Frequency

—

500

—

kHz

F_LFOSC

Internal LFINTOSC

Frequency

—

31

—

kHz

DS40002002B-page 642

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

Characteristic

Min.

—

Typ. †

11

Max.

20

Units

μs

Conditions

VREGPM=0

VREGPM=1

OS54

OS56

T_HFOSCST

HFINTOSC Wake-up

from Sleep Start-up

Time

—

85

—

μs

T_LFOSCST

LFINTOSC Wake-up

from Sleep Start-up

Time

—

0.2

—

ms

† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. To ensure these oscillator frequency tolerances, V_DDand V_SSmust be capacitively decoupled as close to the

device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.

2. See the figure below.

Figure 40-6.ꢀPrecision Calibrated HFINTOSC Frequency Accuracy Over Device V_DDand Temperature

125

± 5%

85

± 3%

60

± 2%

0

± 5%

-40

1.8

2.0

2.3

3.5

4.0

VDD (V)

4.5

5.0

5.5

3.0

40.4.3 PLL Specifications

Table 40-9.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No.

Sym.

Characteristic

Min.

Typ. †

Max.

Units

Conditions

PLL01

F_PLLIN

PLL Input Frequency

Range

4

—

16

MHz

PLL02

F_PLLOUT

PLL Output Frequency

Range

16

—

32

MHz

(Note 1)

DS40002002B-page 643

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param No.

Sym.

Characteristic

Min.

Typ. †

Max.

Units

Conditions

PLL03

F_PLLST

PLL Lock Time from

Start-up

—

200

—

μs

PLL04

F_PLLJIT

PLL Output Frequency

Stability (Jitter)

-0.25

—

0.25

%

* - These parameters are characterized but not tested.

† - Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. The output frequency of the PLL must meet the F_OSCrequirements listed in Parameter D002.

40.4.4 I/O and CLKOUT Timing Specifications

Figure 40-7.ꢀCLKOUT and I/O Timing

Fetch

Q1

Read

Q2

Execute

Q3

Cycle

Write

Q4

FOSC

IO1

IO2

IO5

CLKOUT

IO4

IO6, IO7

IO8, IO9

IO3

I/O pin

(Input)

IO10, IO11

I/O pin

(Output)

Table 40-10.ꢀI/O and CLKOUT Timing Specifications

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

Characteristic

Min. Typ. † Max. Units Conditions

IO1*

IO2*

IO3*

IO4*

T_CLKOUTH

CLKOUT rising edge delay (rising edge F_OSC

(Q1 cycle) to falling edge CLKOUT

—

20

—

50

—

70

72

70

—

ns

T_CLKOUTL

CLKOUT falling edge delay (rising edge F_OSC

(Q3 cycle) to rising edge CLKOUT

T_{IO_VALID}

Port output valid time (rising edge F_OSC(Q1

cycle) to port valid)

T_{IO_SETUP}Port input setup time (Setup time before rising

edge F_OSC– Q2 cycle)

DS40002002B-page 644

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

Characteristic

Min. Typ. † Max. Units Conditions

IO5*

T_{IO_HOLD}

Port input hold time (Hold time after rising edge

F_OSC– Q2 cycle)

50

—

ns

IO6*

IO7*

IO8*

IO9*

IO10*

IO11*

T_{IOR_SLREN}Port I/O rise time, slew rate enabled

T_{IOR_SLRDIS}Port I/O rise time, slew rate disabled

T_{IOF_SLREN}Port I/O fall time, slew rate enabled

T_{IOF_SLRDIS}Port I/O fall time, slew rate disabled

—

25

5

—

ns V_DD=3.0V

ns

25

5

T_INT

T_IOC

INT pin high or low time to trigger an interrupt

—

Interrupt-on-Change minimum high or low time

to trigger interrupt

ns

* - These parameters are characterized but not tested.

40.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-

Out Reset Specifications

Figure 40-8.ꢀReset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

Rev. 30-000075A

4/6/2017

VDD

MCLR

RST01

Internal

POR

RST04

PWRT

Time-out

RST05

OSC

Start-up Time

(1)

Internal Reset

Watchdog Timer

(1)

Reset

RST03

RST02

I/O pins

Note:ꢀ

1. Asserted low.

DS40002002B-page 645

Datasheet

PIC16(L)F18425/45

Electrical Specifications

Figure 40-9.ꢀBrown-out Reset Timing and Characteristics

Rev. 30-000076A

4/6/2017

VDD

VBOR and VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

RST08

Reset

RST04⁽¹⁾

(due to BOR)

Note:ꢀ

1. Only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0.

Table 40-11.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

Characteristic

Min.

Typ. †

Max.

Units

Conditions

RST01*

RST02*

RST03

RST04*

RST05

RST06

T_MCLR

MCLR Pulse Width

Low to ensure Reset

2

—

μs

T_IOZ

I/O high-impedance

from Reset detection

—

16

2

μs

ms

T_WDT

T_PWRT

T_OST

V_BOR

Watchdog Timer

Time-out Period

—

1:512 Prescaler

Power-up Timer

Period

65

ms

Oscillator Start-up

Timer Period^{(1, 2)}

1024

T_OSC

Brown-out Reset

Voltage

2.55

2.30

1.80

2.7

2.85

2.60⁽³⁾

2.05

V

BORV=0

2.45

1.90

BORV=1(F

devices only)

V

BORV=1(LF

Devices only)

RST07

RST08

RST09

V_BORHYS

T_BORDC

V_LPBOR

Brown-out Reset

Hysteresis

—

40

3

—

mV

μs

V

Brown-out Reset

Response Time

Low-Power Brown-out

Reset Voltage

1.8

1.9

2.2

LF Devices only

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

Note:ꢀ

1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.

2. To ensure these voltage tolerances, V_DDand V_SSmust be capacitively decoupled as close to the device as

possible. 0.1 μF and 0.01 μF values in parallel are recommended.

3. This value corresponds to V_BORMAX

DS40002002B-page 646

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.4.6 Temperature Indicator Requirements

Table 40-12.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

Characteristic

Min.

Max.

Units

Conditions

Minimum ADC Acquisition

Time Delay

TS01

TS02

T_ACQMIN

—

25

—

μs

TSRNG = 1

TSRNG = 0

High Range

Low Range

—

-3.684

-3.456

—

mV/°C

Voltage

Sensitivity

Mv

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

40.4.7 Analog-to-Digital Converter (ADC) Accuracy Specifications^(1,2)

Table 40-13.ꢀ

Standard Operating Conditions (unless otherwise stated)

V_DD= 3.0V, T_A= 25°C, T_AD= 1μs

Param No. Sym.

Characteristic

Resolution

Min. Typ. † Max. Units Conditions

AD01

AD02

N_R

E_IL

—

12

bit

Integral Error

±1.0

±2.0

LSb ADC_REF+=3.0V, ADC_REF

= 0V

-

AD03

AD04

AD05

AD06

E_DL

Differential Error

Offset Error

—

±1.0

0.5

±1.0

6.0

LSb ADC_REF+=3.0V, ADC_REF

= 0V

E_OFF

LSb ADC_REF+=3.0V, ADC_REF

= 0V

E_GN

Gain Error

—

±0.2

—

±6.0

V_DD

LSb ADC_REF+=3.0V, ADC_REF

= 0V

V_ADREFADC Reference Voltage

(AD_REF+ - AD_REF-)

1.8

V

AD07

AD08

V_AIN

Z_AIN

Full-Scale Range

AD_REF

—

-

—

AD_REF

—

+

V

Recommended Impedance of

Analog Voltage Source

10

kΩ

AD09

R_VREFADC Voltage Reference Ladder

Impedance

—

50

—

kΩ

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors.

2. The ADC conversion result never decreases with an increase in the input and has no missing codes.

DS40002002B-page 647

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications

Table 40-14.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No. Sym. Characteristic

Min.

Typ. †

Max. Units Conditions

AD20

AD21

AD22

T_ADADC Clock Period

T_CNVConversion Time⁽¹⁾

T_ACQAcquisition Time

0.5

—

9

μs Using F_OSCas the ADC clock

source ADCS = 1

—

2

—

μs Using F_RCas the ADC clock

source ADCS = 0

14T_AD+2T_CY

16T_AD+2T_CY

—

Using F_OSCas the ADC clock

source ADCS = 1

Using F_RCas the ADC clock

source ADCS = 0

AD23

AD24

—

2

—

μs

—

T_HCDSample and Hold Capacitor

Disconnect Time

2T_AD+1T_CY

Using F_OSCas the ADC clock

source ADCS = 1

—

3T_AD+2T_CY

—

Using F_RCas the ADC clock

source ADCS = 0

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. Does not apply for the F_RCoscillator.

Figure 40-10.ꢀADC Conversion Timing (ADC Clock F_OSC-Based)

Rev. 10-000321B

7/31/2019

BSF ADCON0, GO

1 T_CY

AD22

AD23

1 T_CY

AD20

ADC_clk

ADRES

ADIF

OLD DATA

NEW DATA

GO

DONE

Sample

Sampling Stopped

DS40002002B-page 648

Datasheet

PIC16(L)F18425/45

Electrical Specifications

Figure 40-11.ꢀADC Conversion Timing (ADC Clock from F_RC

)

Rev. 10-000328B

7/31/2019

BSF ADCON0, GO

1 T_CY

AD22

AD23

(1)

2 T_CY

AD21

ADC_clk

ADRES

ADIF

OLD DATA

NEW DATA

GO

DONE

Sample

Sampling Stopped

Note:ꢀ

1. If the ADC clock source is selected as F_RC, a time of T_CYis added before the ADC clock starts. This allows the

SLEEPinstruction to be executed.

40.4.9 Comparator Specifications

Table 40-15.ꢀ

Standard Operating Conditions (unless otherwise stated)

V_DD= 3.0V, T_A= 25°C

Param No.

CM01

Sym.

V_IOFF

V_ICM

Characteristic

Min.

—

Typ. †

—

Max.

±60

Units Conditions

Input Offset Voltage

mV

V

V_ICM= V_DD/2

CM02

Input Common Mode

Range

GND

—

V_DD

CM03

CMRR

Common Mode Input

Rejection Ratio

—

50

—

dB

CM04

CM05

V_HYST

Comparator Hysteresis

15

—

25

35

mV

ns

(1)

T_RESP

Response Time, Rising

Edge

300

600

Response Time, Falling

Edge

—

220

—

500

10

ns

(2)

CM06*

T_MCV2VO

Mode Change to Valid

Output

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. Response time measured with one comparator input at V_DD/2, while the other input transitions from V_SSto

V_DD

.

2. A mode change includes changing any of the control register values, including module enable.

DS40002002B-page 649

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.4.10 5-Bit DAC Specifications

Table 40-16.ꢀ

Standard Operating Conditions (unless otherwise stated)

V_DD= 3.0V, T_A= 25°C

Param No.

Sym.

Characteristic

Min.

Typ. †

Max.

Units

Conditions

DSB01

V_LSB

Step Size

—

(V_DACREF+-

—

V

V_DACREF-)/32

DSB02

DSB03*

DSB04*

V_ACC

R_UNIT

T_ST

Absolute Accuracy

Unit Resistor Value

Settling Time⁽¹⁾

—

5000

—

±0.5

—

LSb

Ω

10

μs

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. Settling time measured while DACR[4:0] transitions from ‘00000’ to ‘01111’.

40.4.11 Fixed Voltage Reference (FVR) Specifications

Table 40-17.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No.

FVR01

Sym.

Characteristic

Min. Typ. † Max. Units Conditions

V_FVR

1

1x Gain (1.024V)

2x Gain (2.048V)

4x Gain (4.096V)

-4

-5

—

60

+4

+5

—

%

μs

VDD≥2.5V, -40°C to 85°C

VDD≥4.75V, -40°C to 85°C

FVR02

2

4

FVR03

FVR04

T_FVRSTFVR Start-up Time

40.4.12 Zero-Cross Detect (ZCD) Specifications

Table 40-18.ꢀ

Standard Operating Conditions (unless otherwise stated)

V_DD= 3.0V, T_A= 25°C

Param No.

Sym.

Characteristic

Min.

Typ. †

Max.

Units

Conditions

ZC01

V_PINZC

Voltage on Zero Cross

—

0.75

—

V

ZC02

ZC03

I_{ZCD_MAX}

T_RESPH

T_RESPL

Maximum source or

sink current

—

1

600

—

μA

μs

Response Time,

Rising Edge

Response Time,

Falling Edge

1

—

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

DS40002002B-page 650

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.4.13 Timer0 and Timer1 External Clock Requirements

Table 40-19.ꢀ

Standard Operating Conditions (unless otherwise stated)

Operating Temperature: -40°C≤T_A≤+125°C

Param

No.

Sym.

Characteristic

Min.

Typ. † Max. Units Conditions

40*

41*

42*

T_T0H

T0CKI High No Prescaler

0.5T_CY+20

10

—

ns

Pulse Width

With Prescaler

T_T0L

T_T0P

T0CKI Low No Prescaler

0.5T_CY+20

10

Pulse Width

With Prescaler

T0CKI Period

Greater of:

20 or (T_CY

+40)/N

ns N = Prescale

value

45*

T_T1H

T_T1L

T_T1P

T1CKI High Synchronous, No

0.5T_CY+20

—

ns

Time

Prescaler

Synchronous, with

Prescaler

15

Asynchronous

30

—

ns

46*

T1CKI Low Synchronous, No

0.5T_CY+20

Time

Prescaler

Synchronous, with

Prescaler

15

30

—

ns

Asynchronous

—

47*

49*

T1CKI Input Synchronous

Period

Greater of:

30 or (T_CY

+40)/N

ns N = Prescale

value

Asynchronous

60

—

ns

TCKEZ_TMR1 Delay from External Clock Edge

to Timer Increment

2 T_OSC

7 T_OSC

—

Timers in Sync

mode

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

DS40002002B-page 651

Datasheet

PIC16(L)F18425/45

Electrical Specifications

Figure 40-12.ꢀTimer0 and Timing1 External Clock Timings

Rev. 30-000079A

4/6/2017

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

40.4.14 Capture/Compare/PWM Requirements (CCP)

Table 40-20.ꢀ

Standard Operating Conditions (unless otherwise stated)

Operating Temperature: -40°C≤T_A≤+125°C

Param No. Sym.

Characteristic

Min.

Typ. † Max. Units Conditions

CC01*

CC02*

CC03*

T_CC

L

CCPx Input

Low Time

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5T_CY+20

20

—

ns

H

P

CCPx Input

High Time

0.5T_CY+20

20

CCPx Input

Period

(3T_CY+40)/N

N = Prescale

value

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Figure 40-13.ꢀCapture/Compare/PWM Timings (CCP)

Rev. 30-000080A

4/6/2017

CCPx

(Capture mode)

CC01

CC02

CC03

Note:ꢀ Refer to Figure 40-4 for load conditions.

DS40002002B-page 652

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.4.15 Configurable Logic Cell (CLC) Characteristics

Table 40-21.ꢀ

Standard Operating Conditions (unless otherwise stated)

Operating Temperature: -40°C≤T_A≤+125°C

Param No.

CLC01*

Sym.

T_CLCIN

T_CLC

Characteristic

Min.

—

Typ. †

7

Max. Units

Conditions

(Note1)

CLC input time

OS5 ns

CLC02*

CLC module input to output

propagation time

—

24

—

ns

—

V_DD= 1.8V

V_DD> 3.6V

(Note1)

—

12

CLC03*

CLC04*

T_CLCOUT

CLC output time

Rise Time

Fall Time

—

OS7

OS8

32

—

(Note1)

F_CLCMAX

CLC maximum switching

frequency

—

F_OSCMHz

* - These parameters are characterized but not tested.

† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note:ꢀ

1. See “I/O and CLKOUT Timing Specifications” for OS5, OS7 and OS8 rise and fall times.

Figure 40-14.ꢀCLC Propagation Timing

Rev. 30-000153A

10/27/2017

LCx_in[n]⁽¹⁾

CLC

Input time

CLC

Module

CLC

Output time

CLCxINn

CLCx

LCx_out⁽¹⁾

CLC

Input time

CLC

Module

CLC

Output time

LCx_in[n]⁽¹⁾

CLC01

CLC02

CLC03

Related Links

40.4.4 I/O and CLKOUT Timing Specifications

40.4.16 EUSART Synchronous Transmission Requirements

Table 40-22.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No.

Sym.

Characteristic

Min. Max. Units Conditions

US120

T_CKH2_DT

V

SYNC XMIT (Master and Slave)

Clock high to data-out valid

—

80

ns

3.0V≤V_DD≤5.5V

1.8V≤V_DD≤5.5V

100

DS40002002B-page 653

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param No.

Sym.

Characteristic

Min. Max. Units Conditions

US121

T_CKRF

Clock out rise time and fall time

(Master mode)

—

45

50

45

50

ns

3.0V≤V_DD≤5.5V

1.8V≤V_DD≤5.5V

3.0V≤V_DD≤5.5V

1.8V≤V_DD≤5.5V

US122

T_DTRF

Data-out rise time and fall time

Figure 40-15.ꢀEUSART Synchronous Transmission (Master/Slave) Timing

Rev. 30-000081A

4/6/2017

CK

US121

DT

US122

US120

Note:ꢀ Refer to Figure 40-4 for load conditions.

40.4.17 EUSART Synchronous Receive Requirements

Table 40-23.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No.

Sym.

Characteristic

Min. Max. Units Conditions

US125

T_DTV2_CKL

SYNC RCV (Master and Slave)

Data-setup before CK ↓ (DT hold time)

10

—

ns

US126

T_CKL2_DTL

Data-hold after CK ↓ (DT hold time)

15

—

ns

Figure 40-16.ꢀEUSART Synchronous Receive (Master/Slave) Timing

Rev. 30-000082A

4/6/2017

CK

US125

DT

US126

Note:ꢀ Refer to Figure 40-4 for load conditions.

40.4.18 SPI Mode Requirements

Table 40-24.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

SP70* T_SSL2_SCH,

T_SSL2_SC

Characteristic

Min.

Typ. † Max. Units Conditions

ns

SS↓ to SCK↓ or SCK↑

input

2.25*T_CY

—

L

DS40002002B-page 654

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param No. Sym.

Characteristic

Min.

Typ. † Max. Units Conditions

SP71*

SP72*

SP73*

T_SC

H

SCK input high time (Slave

mode)

T_CY+ 20

—

ns

T_SCL

SCK input low time (Slave

mode)

T_CY+ 20

100

T_DIV2_SCH,

T_DIV2_SC

Setup time of SDI data

input to SCK edge

L

SP74*

SP75*

T_SCH2_DIL,

T_SCL2_DIL

Hold time of SDI data input

to SCK edge

100

—

ns

T_DO

R

SDO data output rise time

—

10

25

10

—

25

50

25

50

ns

3.0V≤V_DD≤5.5V

1.8V≤V_DD≤5.5V

SP76*

SP77*

T_DO

F

SDO data output fall time

T_SSH2_DO

Z

SS↑ to SDO output high-

impedance

SP78*

T_SC

R

SCK output rise time

(Master mode)

—

10

25

10

25

50

25

ns

3.0V≤V_DD≤5.5V

1.8V≤V_DD≤5.5V

SP79*

SP80*

T_SCF

SCK output fall time

(Master mode)

T_SCH2_DOV, SDO data output valid after

SCK edge

—

50

145

—

ns

3.0V≤V_DD≤5.5V

1.8V≤V_DD≤5.5V

T_SCL2_DO

V

SP81*

T_DOV2_SCH, SDO data output setup to

SCK edge

1 T_CY

T_DOV2_SC

L

SP82*

SP83*

T_SSL2_DO

V

SDO data output valid after

SS↓ edge

—

50

—

ns

T_SCH2_SSH, SS ↑after SCK edge

T_SCL2_SS

1.5 T_CY+ 40

H

* - These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

DS40002002B-page 655

Datasheet

PIC16(L)F18425/45

Electrical Specifications

Figure 40-17.ꢀSPI Master Mode Timing (CKE = 0, SMP = 0)

Rev. 30-000083A

4/6/2017

SS

SP81

SCK

(CKP = 0)

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

LSb In

SP74

SP73

Note:ꢀ Refer to Figure 40-4 for load conditions.

Figure 40-18.ꢀSPI Master Mode Timing (CKE = 1, SMP = 1)

Rev. 30-000084A

4/6/2017

SS

SP81

SCK

(CKP = 0)

SP71

SP73

SP72

SP79

SP78

SCK

(CKP = 1)

SP80

LSb

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note:ꢀ Refer to Figure 40-4 for load conditions.

DS40002002B-page 656

Datasheet

PIC16(L)F18425/45

Electrical Specifications

Figure 40-19.ꢀSPI Slave Mode Timing (CKE = 0)

Rev. 30-000085A

4/6/2017

SS

SP70

SCK

(CKP = 0)

SP83

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

MSb

SDO

SDI

bit 6 - - - - - -1

SP75, SP76

bit 6 - - - -1

SP77

MSb In

SP74

SP73

LSb In

Note:ꢀ Refer to Figure 40-4 for load conditions.

Figure 40-20.ꢀSPI Slave Mode Timing (CKE = 1)

Rev. 30-000086A

4/6/2017

SP82

SS

SP70

SP83

SCK

(CKP = 0)

SP72

SP71

SCK

(CKP = 1)

SP80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note:ꢀ Refer to Figure 40-4 for load conditions.

DS40002002B-page 657

Datasheet

PIC16(L)F18425/45

Electrical Specifications

40.4.19 I²C Bus Start/Stop Bits Requirements

Table 40-25.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

Characteristic

T_SU:STAStart condition 100 kHz mode 4700

Setup time

Min. Typ. † Max. Units Conditions

SP90*

SP91*

—

ns Only relevant for Repeated

Start Setup time 400 kHz mode

600 condition

400 kHz mode 600

T_HD:STAStart condition 100 kHz mode 4000

Hold time

—

ns After this period, the first clock

Hold time 400 kHz mode 600

— — pulse is generated

400 kHz mode 600

SP92*

SP93*

T_SU:STOStop condition 100 kHz mode 4700

Setup time

—

ns

400 kHz mode 600

T_HD:STOStop condition 100 kHz mode 4000

Hold time

ns

400 kHz mode 600

* - These parameters are characterized but not tested.

Figure 40-21.ꢀI²C Bus Start/Stop Bits Timing

Rev. 30-000087A

4/6/2017

SCL

SP93

SP91

SP90

SP92

SDA

Stop

Condition

Start

Condition

Note:ꢀ Refer to Figure 40-4 for load conditions.

40.4.20 I²C Bus Data Requirements

Table 40-26.ꢀ

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

SP100* T_HIGH

Characteristic

Min.

Max.

Units

Conditions

Clock high

time

100 kHz

mode

4.0

—

μs

Device must

operate at a

minimum of 1.5

MHz

400 kHz

mode

0.6

—

μs

Device must

operate at a

minimum of 10

MHz

SSP module

1.5T_CY

DS40002002B-page 658

Datasheet

PIC16(L)F18425/45

Electrical Specifications

...........continued

Standard Operating Conditions (unless otherwise stated)

Param. No. Sym.

Characteristic

Min.

Max.

Units

Conditions

SP101*

T_LOW

Clock low

time

100 kHz

mode

4.7

—

μs

Device must

operate at a

minimum of 1.5

MHz

400 kHz

mode

1.3

—

μs

Device must

operate at a

minimum of 10

MHz

SSP module

1.5T_CY

—

SP102*

SP103*

SP106*

SP107*

SP109*

SP110*

SP111

T_R

SDA and

SCL rise

time

100 kHz

mode

1000

ns

μs

ns

μs

pF

400 kHz

mode

20 + 0.1C_B

300

250

—

C_Bis specified to

be from 10-400 pF

T_F

SDA and

SCL fall time mode

100 kHz

—

400 kHz

mode

20 + 0.1C_B

C_Bis specified to

be from 10-400 pF

T_HD:DAT

T_SU:DAT

T_AA

Data input

hold time

100 kHz

mode

0

400 kHz

mode

0.9

—

Data input

setup time

100 kHz

mode

250

100

—

(Note 2)

(Note 1)

400 kHz

mode

—

Output valid 100 kHz

from clock

3500

—

mode

400 kHz

mode

—

T_BUF

Bus free time 100 kHz

mode

4.7

1.3

—

Time the bus must

be free before a

new transmission

can start

400 kHz

mode

—

C_B

Bus capacitive loading

400

* - These parameters are characterized but not tested.

Note:ꢀ

1. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2. A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement T_SU:DAT≥250 ns must then be met. This will automatically be the case if the device does not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must output the next data bit to the SDA line TR max. + T_SU:DAT= 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification), before the SCL line is released.

DS40002002B-page 659

Datasheet

PIC16(L)F18425/45

Electrical Specifications

Figure 40-22.ꢀI²C Bus Data Timing

Rev. 30-000088A

4/6/2017

SP100

SP106

SP102

SP103

SP101

SCL

SP90

SP91

SP107

SP92

SDA

In

SP110

SP109

SDA

Out

Note:ꢀ Refer to Figure 40-4 for load conditions.

DS40002002B-page 660

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

41.

DC and AC Characteristics Graphs and Tables

The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables,

the data presented are outside specified operating range (i.e., outside specified V_DDrange). This is for information

only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs

apply to both the L and LF devices.

Note:ꢀ The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not

tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range

(e.g., outside specified power supply range) and therefore, outside the warranted range.

Note:ꢀ “Typical” represents the mean of the distribution at 25°C. “Maximum”, “Max.”, “Minimum” or “Min.” represents

(mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range.

41.1

Graphs

Figure 41-1.ꢀI_PDBase, Low-Power Sleep Mode

PIC16LF18425/45 only

Figure 41-2.ꢀI_PDWatchdog Timer (WDT)

PIC16LF18425/45 only

DS40002002B-page 661

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-3.ꢀI_PDWatchdog Timer (WDT)

PIC16F18425/45 only

Figure 41-4.ꢀI_PDFixed Voltage Reference (FVR)

PIC16LF18425/45 only

Figure 41-5.ꢀI_PDFixed Voltage Reference (FVR)

PIC16F18425/45 only

Figure 41-6.ꢀI_PDBrown-Out Reset (BOR), BORV = 1

PIC16LF18425/45 only

Figure 41-7.ꢀI_PDBrown-Out Reset (BOR), BORV = 1

Figure 41-8.ꢀI_PDLow-Power Brown-Out Reset,

LPBOR = 0 PIC16LF18425/45 only

PIC16F18425/45 only

DS40002002B-page 662

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-9.ꢀI_PDComparator PIC16LF18425/45 only

Figure 41-10.ꢀI_PDComparator PIC16F18425/45 only

Figure 41-11.ꢀI_PDBase, 01 PIC16F18425/45 only

Figure 41-12.ꢀI_PDBase, 11 PIC16F18425/45 only

Figure 41-13.ꢀI_DDXT Oscillator 4 MHz,

PIC16LF18425/45 only

Figure 41-14.ꢀI_DDXT Oscillator 4 MHz,

PIC16F18425/45 only

DS40002002B-page 663

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-15.ꢀI_DDHS Oscillator 32 MHz,

PIC16LF18425/45 only

Figure 41-16.ꢀI_DDHS Oscillator 32 MHz,

PIC16F18425/45 only

Figure 41-17.ꢀI_DDHFINTOSC Mode, F_OSC= 32 MHz,

PIC16LF18425/45 only

Figure 41-18.ꢀI_DDHFINTOSC Mode, F_OSC= 32 MHz,

PIC16F18425/45 only

Figure 41-19.ꢀI_DDHFINTOSC Mode, F_OSC= 16 MHz,

PIC16LF18425/45 only

Figure 41-20.ꢀI_DDHFINTOSC Mode, F_OSC= 16 MHz,

PIC16F18425/45 only

3.0

Max: 85°C + 3σ

Typical: 25°C

2.5

Max

2.0

Typical

1.5

1.0

0.5

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

DS40002002B-page 664

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-21.ꢀI_DDHFINTOSC Idle Mode, F_OSC= 16

Figure 41-22.ꢀI_DDHFINTOSC Idle Mode, F_OSC= 16

MHz, PIC16F18425/45 only

MHz, PIC16LF18425/45 only

Figure 41-23.ꢀI_DDHFINTOSC Doze Mode, F_OSC= 16

MHz, PIC16LF18425/45 only

Figure 41-24.ꢀI_DDHFINTOSC Doze Mode, F_OSC= 16

MHz, PIC16F18425/45 only

Figure 41-25.ꢀLFINTOSC Frequency,

PIC16LF18425/45 only

Figure 41-26.ꢀLFINTOSC Frequency, PIC16F18425/45

only

DS40002002B-page 665

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-27.ꢀHFINTOSC Typical Frequency Error,

PIC16LF18425/45 only

Figure 41-28.ꢀHFINTOSC Typical Frequency Error,

PIC16F18425/45 only

Figure 41-29.ꢀHFINTOSC Frequency Error V_DD= 3V, Figure 41-30.ꢀWeak Pull-Up Current, PIC16F18425/45

All devices

only

Figure 41-31.ꢀWeak Pull-Up Current,

PIC16LF18425/45 only

Figure 41-32.ꢀV_OHvs. I_OHOvertemperature, V_DD

5.5V, PIC16F18425/45 only

=

DS40002002B-page 666

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-33.ꢀV_OLvs. I_OLOvertemperature, V_DD

5.5V, PIC16F18425/45 only

=

Figure 41-34.ꢀV_OHvs. I_OHOvertemperature, V_DD

3.0V, All devices

=

Figure 41-35.ꢀV_OLvs. I_OLOvertemperature, V_DD

3.0V, All devices

=

Figure 41-36.ꢀV_OHvs. I_OHOvertemperature, V_DD

1.8V, PIC16LF18425/45 only

=

Figure 41-37.ꢀV_OLvs. I_OLOvertemperature, V_DD

1.8V, PIC16LF18425/45 only

=

Figure 41-38.ꢀBrown-Out Reset Voltage, Trip Point

BORV = 00, All devices

DS40002002B-page 667

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-39.ꢀBrown-Out Reset Hysteresis, Low Trip

Figure 41-40.ꢀBrown-Out Reset Voltage, Low Trip

Point BORV = 00, All devices

Point BORV = 01, PIC16LF18425/45 only

Figure 41-41.ꢀBrown-Out Reset Hysteresis, Trip

Figure 41-42.ꢀBrown-Out Reset Voltage, Trip Point

Point BORV = 01, PIC16LF18425/45 only

BORV = 01, PIC16F18425/45 only

Figure 41-43.ꢀBrown-Out Reset Hysteresis, Trip

Figure 41-44.ꢀLPBOR Reset Voltage, All devices

Point BORV = 01, PIC16F18425/45 only

DS40002002B-page 668

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-45.ꢀLPBOR Reset Hysteresis, All devices

Figure 41-46.ꢀBOR Response Time,

PIC16LF18425/45 only

Figure 41-47.ꢀBOR Response Time, PIC16F18425/45

only

Figure 41-48.ꢀADC 12-Bit Mode, Single-Ended

Typical DNL, V_DD= 3.0V, V_REF= 3.0V, T_AD= 0.5 uS,

25ºC, All devices

Figure 41-49.ꢀADC 12-Bit Mode, Single-Ended DNL,

Figure 41-50.ꢀADC 12-Bit Mode, Single-Ended DNL,

V_DD= 3.0V, V_REF= 3.0V, T_AD= 1 uS, 25ºC, All devices V_DD= 3.0V, V_REF= 3.0V, T_AD= 4 uS, 25ºC, All devices

DS40002002B-page 669

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-51.ꢀADC 12-Bit Mode, Single-Ended

Figure 41-52.ꢀADC 12-Bit Mode, Single-Ended INL,

Typical INL, V_DD= 3.0V, V_REF= 3.0V, T_AD= 0.5 uS,

25ºC, All devices

V_DD= 3.0V, V_REF= 3.0V, T_AD= 1 uS, 25ºC, All devices

Figure 41-53.ꢀADC 12-Bit Mode, Single-Ended INL,

V_DD= 3.0V, V_REF= 3.0V, T_AD= 4 uS, 25ºC, All devices

Figure 41-54.ꢀADC 12-Bit Mode, Single-Ended DNL,

V_DD= 3.0V, V_REF= 3.0V, All devices

Figure 41-55.ꢀADC 12-Bit Mode, Single-Ended INL,

V_DD= 3.0V, V_REF= 3.0V, All devices

Figure 41-56.ꢀADC 12-Bit Mode, Single-Ended DNL,

V_DD= 3.0V, T_AD= 1 uS, All devices

DS40002002B-page 670

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-57.ꢀADC 12-Bit Mode, Single-Ended INL,

V_DD= 3.0V, T_AD= 1 uS, All devices

Figure 41-58.ꢀADC 12-Bit Mode, Single-Ended Gain

Error, V_DD= 3.0V, T_AD= 1 uS, All devices

Figure 41-59.ꢀADC 12-Bit Mode, Single-Ended Offset Figure 41-60.ꢀADC 12-Bit Mode, Single-Ended DNL,

Error, V_DD= 3.0V, T_AD= 1 uS, All devices

V_DD= 3.0V, T_AD= 4 uS, All devices

Figure 41-61.ꢀADC 12-Bit Mode, Single-Ended INL,

V_DD= 3.0V, T_AD= 4 uS, All devices

Figure 41-62.ꢀADC 12-Bit Mode, Single-Ended Gain

Error, V_DD= 3.0V, T_AD= 4 uS, All devices

DS40002002B-page 671

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-63.ꢀADC 12-Bit Mode, Single-Ended Offset Figure 41-64.ꢀADC 12-Bit Mode, Single-Ended Gain

Error, V_DD= 3.0V, T_AD= 4 uS, All devices

Error, V_DD= 3.0V, V_REF= 3.0V, -40ºC to 85ºC, All

devices

Figure 41-65.ꢀADC 12-Bit Mode, Single-Ended Offset

Error, V_DD= 3.0V, V_REF= 3.0V, -40ºC to 85ºC, All

devices

Figure 41-66.ꢀADC RC Oscillator Period,

PIC16LF18425/45 only

Figure 41-67.ꢀADC RC Oscillator Period,

PIC16F18425/45 only

Figure 41-68.ꢀTypical DAC DNL Error, V_DD= 3.0V,

V_REF= External 3V, All devices

DS40002002B-page 672

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-69.ꢀTypical DAC INL Error, V_DD= 3.0V, V_REF

Figure 41-70.ꢀTypical DAC DNL Error, V_DD= 5.0V,

V_REF= External 5V, PIC16F18425/45 only

= External 3V, All devices

Figure 41-71.ꢀTypical DAC INL Error, V_DD= 5.0V, V_REF

= External 5V, PIC16F18425/45 only

Figure 41-72.ꢀDAC INL Error, V_DD= 3.0V,

PIC16LF18425/45 only

Figure 41-73.ꢀAbsolute Value of DAC DNL Error, V_DDFigure 41-74.ꢀAbsolute Value of DAC INL Error, V_DD

= 3.0V, V_REF= V_DD, All devices 3.0V, V_REF= V_DD, All devices

=

DS40002002B-page 673

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-75.ꢀAbsolute Value of DAC DNL Error, V_DDFigure 41-76.ꢀAbsolute Value of DAC INL Error, V_DD

=

= 5.0V, V_REF= V_DD, PIC16F18425/45 only

5.0V, V_REF= V_DD, PIC16F18425/45 only

Figure 41-77.ꢀComparator Hysteresis, Normal Power

Mode (CxSP = 1), V_DD= 3.0V, Typical Measured

Values, All devices

Figure 41-78.ꢀComparator Offset, Normal Power

Mode (CxSP = 1), V_DD= 3.0V, Typical Measured

Values at 25°C, All devices

Figure 41-79.ꢀComparator Offset, Normal Power

Mode (CxSP = 1), V_DD= 3.0V, Typical Measured

Values from -40°C to 125°C, All devices

Figure 41-80.ꢀComparator Hysteresis, Normal Power

Mode (CxSP = 1), V_DD= 5.5V, Typical Measured

Values, PIC16F18425/45 only

DS40002002B-page 674

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-81.ꢀComparator Offset, Normal Power

Mode (CxSP = 1), V_DD= 5.0V, Typical Measured

Figure 41-82.ꢀComparator Offset, Normal Power

Mode (CxSP = 1), V_DD= 5.5V, Typical Measured

Values from -40°C to 125°C, PIC16F18425/45 only

Values at 25°C, PIC16F18425/45 only

Figure 41-83.ꢀComparator Response Time

Figure 41-84.ꢀComparator Response Time

Overvoltage, Normal Power Mode (CxSP = 1), Typical Overvoltage, Normal Power Mode (CxSP = 1), Typical

Measured Values, PIC16LF18425/45 only

Measured Values, PIC16F18425/45 only

Figure 41-85.ꢀComparator Response Time Falling

Edge, PIC16LF18425/45 only

Figure 41-86.ꢀComparator Response Time Falling

Edge, PIC16F18425/45 only

DS40002002B-page 675

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-87.ꢀComparator Response Time Rising

Figure 41-88.ꢀComparator Response Time Rising

Edge, PIC16F18425/45 only

Edge, PIC16LF18425/45 only

Figure 41-89.ꢀBand Gap Ready Time,

PIC16LF18425/45 only

Figure 41-90.ꢀFVR Stabilization Period,

PIC16LF18425/45 only

Figure 41-91.ꢀTypical FVR Voltage 1x,

PIC16LF18425/45 only

Figure 41-92.ꢀFVR Voltage Error 1x, PIC16F18425/45

only

DS40002002B-page 676

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-93.ꢀFVR Voltage Error 2x,

PIC16LF18425/45 only

Figure 41-94.ꢀFVR Voltage Error 2x, PIC16F18425/45

only

Figure 41-95.ꢀFVR Voltage Error 4x, PIC16F18425/45

only

Figure 41-96.ꢀSchmitt Trigger High Values, All

devices

Figure 41-97.ꢀSchmitt Trigger Low Values, All

devices

Figure 41-98.ꢀInput Level TTL, All devices

DS40002002B-page 677

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-99.ꢀRise Time, Slew Rate Control Enabled, Figure 41-100.ꢀFall Time, Slew Rate Control Enabled,

All devices

Figure 41-101.ꢀRise Time, Slew Rate Control

Disabled, All devices

Figure 41-102.ꢀFall Time, Slew Rate Control

Disabled, All devices

Figure 41-103.ꢀOSCTUNE Center Frequency,

PIC16LF18425/45 only

Figure 41-104.ꢀPOR Release Voltage, All devices

DS40002002B-page 678

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-105.ꢀPOR REARM Voltage, Normal Power

Figure 41-106.ꢀPWRT Period, PIC16F18425/45 only

Mode, PIC16F18425/45 only

Figure 41-107.ꢀPWRT Period, PIC16LF18425/45 only

Figure 41-108.ꢀWake from Sleep, VREGPM = 0,

HFINTOSC = 4 MHz PIC16F18425/45 only

Figure 41-109.ꢀWake from Sleep, VREGPM = 1,

Figure 41-110.ꢀWake from Sleep, VREGPM = 0,

HFINTOSC = 4 MHz PIC16F18425/45 only

HFINTOSC = 16 MHz PIC16F18425/45 only

DS40002002B-page 679

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-111.ꢀWake from Sleep, VREGPM = 1,

Figure 41-112.ꢀWake from Sleep, VREGPM = 1,

HFINTOSC = 16 MHz PIC16F18425/45 only

PIC16F18425/45 only

Figure 41-113.ꢀWake from Sleep, PIC16LF18425/45

only

Figure 41-114.ꢀWDT Time-Out Period,

PIC16F18425/45 only

DS40002002B-page 680

Datasheet

PIC16(L)F18425/45

DC and AC Characteristics Graphs and Tables

Figure 41-115.ꢀWDT Time-Out Period, PIC16LF18425/45 only

DS40002002B-page 681

Datasheet

PIC16(L)F18425/45

Packaging Information

42.

Packaging Information

Package Marking Information

Rev. 30-009000A

5/17/2017

Legend: XX...X Customer-specific information or Microchip part number

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

®

e

P

3

b-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Rev. 30-009014A

09/21/2017

14-Lead PDIP (300 mil)

Example

PIC16F18425

/SO _e

3

1525017

Rev. 30-009014B

09/21/2017

14-Lead TSSOP (4.4 mm)

Example

16F18425

XXXXXXXX

YYWW

e

3

1525

017

NNN

DS40002002B-page 682

Datasheet

PIC16(L)F18425/45

Packaging Information

Rev. 30-009014C

09/21/2017

14-Lead SOIC (3.90 mm)

Example

PIC16F18425

e

3

/SO

1525017

Rev. 30-009016A

09/21/2017

16-Lead UQFN (4x4x0.5 mm)

Example

PIC16

F1842

PIN 1

5

3

e

/MV

525017

Rev. 30-009020A

09/21/2017

20-Lead PDIP (300 mil)

Example

PIC16F18445

XXXXXXXXXXXXXXXXX

e

3

/P

1525017

YYWWNNN

Rev. 30-009020B

09/21/2017

20-Lead SSOP (5.30 mm)

Example

PIC16F18445

e

3

/SO

1525017

DS40002002B-page 683

Datasheet

PIC16(L)F18425/45

Packaging Information

Rev. 30-009020C

09/21/2017

20-Lead SOIC (7.50 mm)

Example

PIC16F18445

/SO _e

3

1525017

Rev. 30-009020D

09/21/2017

20-Lead UQFN (4x4x0.5 mm)

Example

PIC16

PIN 1

F1844

5

e

3

/MV

525017

42.1

Package Details

The following sections give the technical details of the packages.

DS40002002B-page 684

Datasheet

PIC16(L)F18425/45

Packaging Information

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

c

A1

b1

b

e

eB

Units

INCHES

NOM

14

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.735

.115

.008

.045

.014

–

.130

–

.310

.250

.750

.130

.010

.060

.018

–

.325

.280

.775

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-005B

DS40002002B-page 685

Datasheet

PIC16(L)F18425/45

Packaging Information

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

2X

0.10 C A–B

D

NOTE 5

A

D

E

N

E

2

E2

2

E1

2X

0.10 C D

NOTE 1

2X N/2 TIPS

0.20 C

1

2

3

e

NX b

0.25

C A–B D

0.10 C

NOTE 5

B

TOP VIEW

C

A2

A

SEATING

PLANE

14X

0.10 C

SIDE VIEW

A1

h

R0.13

H

R0.13

c

SEE VIEW C

L

VIEW A–A

(L1)

VIEW C

Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2

DS40002002B-page 686

Datasheet

PIC16(L)F18425/45

Packaging Information

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

14

1.27 BSC

Overall Height

Molded Package Thickness

Standoff

Overall Width

A

-

1.75

-

0.25

A2

A1

E

1.25

0.10

§

6.00 BSC

Molded Package Width

Overall Length

Chamfer (Optional)

Foot Length

E1

D

h

3.90 BSC

8.65 BSC

0.25

0.40

-

0.50

1.27

L

Footprint

L1

1.04 REF

Lead Angle

Foot Angle

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

0°

0.10

0.31

5°

-

8°

0.25

0.51

15°

c

b

5°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Dimension D does not include mold flash, protrusions or gate burrs, which shall

not exceed 0.15 mm per end. Dimension E1 does not include interlead flash

or protrusion, which shall not exceed 0.25 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2

DS40002002B-page 687

Datasheet

PIC16(L)F18425/45

Packaging Information

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

14

SILK SCREEN

C

Y

1

2

X

E

RECOMMENDED LAND PATTERN

Units

MILLIMETERS

Dimension Limits

MIN

NOM

1.27 BSC

5.40

MAX

Contact Pitch

Contact Pad Spacing

Contact Pad Width (X14)

E

C

X

0.60

1.55

Contact Pad Length (X14)

Y

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2065-SL Rev D

DS40002002B-page 688

Datasheet

PIC16(L)F18425/45

Packaging Information

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40002002B-page 689

Datasheet

PIC16(L)F18425/45

Packaging Information

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40002002B-page 690

Datasheet

PIC16(L)F18425/45

Packaging Information

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40002002B-page 691

Datasheet

PIC16(L)F18425/45

Packaging Information

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM B)

(DATUM A)

2X

0.20 C

2X

TOP VIEW

0.20 C

0.10 C

A1

C

A

SEATING

PLANE

16X

(A3)

0.08 C

C A B

SIDE VIEW

0.10

D2

0.10

C A B

E2

2

1

e

2

NOTE 1

K

N

L

16X b

0.10

C A B

e

BOTTOM VIEW

Microchip Technology Drawing C04-257A Sheet 1 of 2

DS40002002B-page 692

Datasheet

PIC16(L)F18425/45

Packaging Information

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Terminal Width

Terminal Length

N

e

16

0.65 BSC

0.50

A

A1

A3

E

E2

D

D2

b

L

0.45

0.00

0.55

0.05

0.02

0.127 REF

4.00 BSC

2.60

4.00 BSC

2.60

2.50

2.70

2.50

0.25

0.30

0.20

2.70

0.35

0.50

-

0.30

0.40

-

Terminal-to-Exposed-Pad

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-257A Sheet 2 of 2

DS40002002B-page 693

Datasheet

PIC16(L)F18425/45

Packaging Information

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body

[UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

16

1

2

C2 Y2

Y1

X1

E

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.65 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

Contact Pad Width (X16)

Contact Pad Length (X16)

X2

Y2

C1

C2

X1

Y1

2.70

4.00

0.35

0.80

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2257A

DS40002002B-page 694

Datasheet

PIC16(L)F18425/45

Packaging Information

20-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

E1

NOTE 1

1

2

3

D

E

A2

A

L

c

A1

b1

eB

e

b

Units

INCHES

NOM

20

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.980

.115

.008

.045

.014

–

.130

–

.310

.250

1.030

.130

.010

.060

.018

–

.325

.280

1.060

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-019B

DS40002002B-page 695

Datasheet

PIC16(L)F18425/45

Packaging Information

20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

e

b

c

A2

A

φ

A1

L1

L

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

20

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.75

–

2.00

1.85

–

A2

A1

E

1.65

0.05

7.40

5.00

6.90

0.55

Overall Width

Molded Package Width

Overall Length

Foot Length

7.80

5.30

7.20

0.75

1.25 REF

–

8.20

5.60

7.50

0.95

E1

D

L

Footprint

L1

c

Lead Thickness

Foot Angle

0.09

0°

0.25

8°

φ

4°

Lead Width

b

0.22

–

0.38

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-072B

DS40002002B-page 696

Datasheet

PIC16(L)F18425/45

Packaging Information

20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

0.65

0.45

SILK SCREEN

c

Y1

G

X1

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Contact Pitch

Contact Pad Spacing

Contact Pad Width (X20)

E

C

X1

0.65 BSC

7.20

0.45

1.75

Contact Pad Length (X20)

Distance Between Pads

Y1

G

0.20

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2072B

DS40002002B-page 697

Datasheet

PIC16(L)F18425/45

Packaging Information

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40002002B-page 698

Datasheet

PIC16(L)F18425/45

Packaging Information

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40002002B-page 699

Datasheet

PIC16(L)F18425/45

Packaging Information

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40002002B-page 700

Datasheet

PIC16(L)F18425/45

Packaging Information

20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM B)

(DATUM A)

2X

0.20 C

2X

TOP VIEW

0.20 C

0.10 C

A1

C

A

SEATING

PLANE

20X

(A3)

0.08 C

C A B

SIDE VIEW

0.10

D2

L

0.10

C A B

E2

2

1

K

N

NOTE 1

20X b

0.10

C A B

e

BOTTOM VIEW

Microchip Technology Drawing C04-255A Sheet 1 of 2

DS40002002B-page 701

Datasheet

PIC16(L)F18425/45

Packaging Information

20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Terminals

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Terminal Width

Terminal Length

N

e

20

0.50 BSC

0.50

A

A1

A3

E

E2

D

D2

b

L

0.45

0.00

0.55

0.05

0.02

0.127 REF

4.00 BSC

2.70

4.00 BSC

2.70

2.60

2.80

2.60

0.20

0.30

0.20

2.80

0.30

0.50

-

0.25

0.40

-

Terminal-to-Exposed-Pad

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-255A Sheet 2 of 2

DS40002002B-page 702

Datasheet

PIC16(L)F18425/45

Packaging Information

20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

20

1

2

C2 Y2

G1

Y1

X1

E

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.50 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

X2

Y2

C1

C2

X1

Y1

G1

2.80

4.00

Contact Pad Spacing

Contact Pad Width (X20)

Contact Pad Length (X20)

Contact Pad to Center Pad (X20)

0.30

0.80

0.20

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2255A

DS40002002B-page 703

Datasheet

PIC16(L)F18425/45

Revision History

43.

Revision History

Doc Rev. Date

Comments

B

A

11/2019 Adding Electrical Specifications and DC and AC Characteristics Graphs and Tables. Other

minor corrections.

02/2018 Initial release of this document.

DS40002002B-page 704

Datasheet

PIC16(L)F18425/45

The Microchip Website

Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files

and information easily available to customers. Some of the content available includes:

•

Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online

discussion groups, Microchip design partner program member listing

Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of

seminars and events, listings of Microchip sales offices, distributors and factory representatives

Product Change Notification Service

Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will

receive email notification whenever there are changes, updates, revisions or errata related to a specified product

family or development tool of interest.

To register, go to http://www.microchip.com/pcn and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

•

Distributor or Representative

Local Sales Office

Embedded Solutions Engineer (ESE)

Technical Support

Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to

help customers. A listing of sales offices and locations is included in this document.

Technical support is available through the website at: http://www.microchip.com/support

DS40002002B-page 705

Datasheet

PIC16(L)F18425/45

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

PART NO.

Device

–X

/XX

[X]

Tape Temperature Package

and Reel Range

Device:

PIC16F18425, PIC16LF18425, PIC16F18445, PIC16LF18445

Tape & Reel Option:

Temperature Range:

Package:

Blank

T

= Tube

= Tape & Reel

I

= -40°C to +85°C (Industrial)

= -40°C to +125°C (Extended)

= 16-lead UQFN 4x4x0.5mm

= 14-lead, 20-lead PDIP

= 14-lead SOIC

E

JQ

P

SL

SO

SS

ST

GZ

= 20-lead SOIC

= 20-lead SSOP

= 14-lead TSSOP

= 20-lead UQFN 4x4x0.5mm

Pattern:

QTP, SQTP, Code or Special Requirements (blank otherwise)

Examples:

•

PIC16F18425- E/P Extended temperature PDIP package

Note:ꢀ

1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering

purposes and is not printed on the device package. Check with your Microchip Sales Office for package

availability with the Tape and Reel option.

2. Small form-factor packaging options may be available. Please check http://www.microchip.com/packaging for

small-form factor package availability, or contact your local Sales Office.

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today,

when used in the intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these

methods, to our knowledge, require using the Microchip products in a manner outside the operating

specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of

intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code

protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection

features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital

DS40002002B-page 706

Datasheet

PIC16(L)F18425/45

Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you

may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for your

convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with

your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER

EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,

indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such

use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless

otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,

BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,

KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,

MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,

QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,

HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,

ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,

Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,

CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,

INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,

PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad

I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.

and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

©

ISBN: 978-1-5224-5233-1

Quality Management System

For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.

DS40002002B-page 707

Datasheet

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/support

Web Address:

Australia - Sydney

Tel: 61-2-9868-6733

China - Beijing

India - Bangalore

Tel: 91-80-3090-4444

India - New Delhi

Tel: 91-11-4160-8631

India - Pune

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Tel: 86-10-8569-7000

China - Chengdu

Tel: 86-28-8665-5511

China - Chongqing

Tel: 86-23-8980-9588

China - Dongguan

Tel: 86-769-8702-9880

China - Guangzhou

Tel: 86-20-8755-8029

China - Hangzhou

Tel: 86-571-8792-8115

China - Hong Kong SAR

Tel: 852-2943-5100

China - Nanjing

Tel: 91-20-4121-0141

Japan - Osaka

Fax: 45-4485-2829

Finland - Espoo

Tel: 81-6-6152-7160

Japan - Tokyo

Tel: 358-9-4520-820

France - Paris

http://www.microchip.com

Atlanta

Tel: 81-3-6880- 3770

Korea - Daegu

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Garching

Tel: 49-8931-9700

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Austin, TX

Tel: 82-53-744-4301

Korea - Seoul

Tel: 82-2-554-7200

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Malaysia - Penang

Tel: 60-4-227-8870

Philippines - Manila

Tel: 63-2-634-9065

Singapore

Germany - Haan

Tel: 512-257-3370

Boston

Tel: 49-2129-3766400

Germany - Heilbronn

Tel: 49-7131-72400

Germany - Karlsruhe

Tel: 49-721-625370

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Germany - Rosenheim

Tel: 49-8031-354-560

Israel - Ra’anana

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Tel: 86-25-8473-2460

China - Qingdao

Tel: 86-532-8502-7355

China - Shanghai

Tel: 86-21-3326-8000

China - Shenyang

Tel: 86-24-2334-2829

China - Shenzhen

Tel: 86-755-8864-2200

China - Suzhou

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Tel: 65-6334-8870

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Taiwan - Taipei

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Tel: 972-9-744-7705

Italy - Milan

Tel: 86-186-6233-1526

China - Wuhan

Tel: 886-2-2508-8600

Thailand - Bangkok

Tel: 66-2-694-1351

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Padova

Novi, MI

Tel: 248-848-4000

Houston, TX

Tel: 86-27-5980-5300

China - Xian

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Norway - Trondheim

Tel: 47-72884388

Tel: 281-894-5983

Indianapolis

Tel: 86-29-8833-7252

China - Xiamen

Noblesville, IN

Tel: 86-592-2388138

China - Zhuhai

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

Los Angeles

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Raleigh, NC

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 919-844-7510

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

Tel: 44-118-921-5800

Fax: 44-118-921-5820

DS40002002B-page 708

Datasheet


型号：	PIC16LF18445-E/SSSQTP
厂家：	MICROCHIP
描述：	14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP 微控制器
文件：	总708页 (文件大小：10898K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16LF18445-E/SSSQTP [MICROCHIP]

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