PIC16LF1947T-I/PT [MICROCHIP]
64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology;型号: | PIC16LF1947T-I/PT |
厂家: | MICROCHIP |
描述: | 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology CD 微控制器 |
文件: | 总440页 (文件大小:4740K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16F/LF1946/47
Data Sheet
64-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
LCD Driver and nanoWatt XLP Technology
2010 Microchip Technology Inc.
Preliminary
DS41414A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
32
PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-049-2
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41414A-page 2
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
LCD Driver with nanoWatt XLP Technology
Devices Included In This Data Sheet:
PIC16LF1946/47 Low-Power Features:
• Standby Current:
- 60 nA @ 1.8V, typical
• Operating Current:
• PIC16F1946
• PIC16LF1946
• PIC16F1947
• PIC16LF1947
- 7.0 A @ 32 kHz, 1.8V, typical
(PIC16LF1946/47)
High-Performance RISC CPU:
- 75 A @ 1 MHz, 1.8V, typical
(PIC16LF1946/47)
• Timer1 Oscillator Current:
- 600 nA @ 32 kHz, 1.8V, typical
• Low-Power Watchdog Timer Current:
- 500 nA @ 1.8V, typical (PIC16LF1946/47)
• Only 49 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 32 MHz oscillator/clock input
- DC – 125 ns instruction cycle
• Up to 16K x 14 Words of Flash Program Memory
• Up to 1024 Bytes of Data Memory (RAM)
• Interrupt Capability with Automatic Context
Saving
Peripheral Features:
• Up to 54 I/O Pins and 1 Input-only pin:
- High-current source/sink for direct LED drive
- Individually programmable Interrupt-on-pin
change pins
• 16-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Processor Read Access to Program Memory
- Individually programmable weak pull-ups
• Integrated LCD Controller:
- Up to 184 segments
- Variable clock input
- Contrast control
- Internal voltage reference selections
• Capacitive Sensing Module (mTouchTM):
- Up to 16 selectable channels
• A/D Converter:
- 10-bit resolution and up to 14 channels
- Selectable 1.024/2.048/4.096V voltage
reference
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- Dedicated low-power 32 kHz oscillator driver
- 16-bit timer/counter with prescaler
- External Gate Input mode with toggle and
single shot modes
- Interrupt-on-gate completion
• Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture, Compare, PWM Modules (CCP):
- 16-bit Capture, max. resolution 125 ns
- 16-bit Compare, max. resolution 125 ns
- 10-bit PWM, max. frequency 31.25 kHz
• Three Enhanced Capture, Compare, PWM
Modules (ECCP):
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
32 MHz to 31 kHz
• Power-Saving Sleep mode
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset (BOR):
- Selectable between two trip points
- Disable in Sleep option
• Multiplexed Master Clear with Pull-up/Input Pin
• Programmable Code Protection
• High Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
• Wide Operating Voltage Range:
- 1.8V-5.5V (PIC16F1946/47)
- 1.8V-3.6V (PIC16LF1946/47)
- 3 PWM time-base options
- Auto-shutdown and auto-restart
- PWM steering
- Programmable Dead-band Delay
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 1
PIC16F/LF1946/47
Peripheral Features (Continued):
• Two Master Synchronous Serial Ports (MSSPs)
with SPI and I2CTM with:
- 7-bit address masking
- SMBus/PMBusTM compatibility
- Auto-wake-up on start
• Two Enhanced Universal Synchronous:
Asynchronous Receiver Transmitters (EUSARTs)
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
• SR Latch (555 Timer):
- Multiple Set/Reset input options
- Emulates 555 Timer applications
• 2 Comparators:
- Rail-to-rail inputs/outputs
- Power mode control
- Software enable hysteresis
• Voltage Reference Module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
PIC16F/LF1946/47 Family Types
PIC16F1946
PIC16LF1946
8192
256
256
512
54
54
17
17
17
17
3
3
4/1
4/1
2
2
2
2
3
3
2
2
184/4
184/4
PIC16F1947
PIC16LF1947
16384
1024
DS41414A-page 2
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
Pin Diagram – 64-Pin TQFP/QFN (PIC16F/LF1946/47)
64-pin TQFP, QFN
64
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VLCD2/P2C(1)/RE1
VLCD1/P2D(1)/RE0
SEG42/P3A/CCP3/RG0
RB0/INT/SRI/FLT0/SEG30
RB1/SEG8
RB2/SEG9
RB3/SEG10
RB4/SEG11
RB5/T1G/SEG29
RB6/ICSPCLK/ICDCLK/SEG38
VSS
RA6/OSC2/CLKOUT/SEG36
RA7/OSC1/CLKIN/SEG37
VDD
RB7/ICSPDAT/ICDDAT/SEG39
RC5/SDO1/SEG12
RC4/SDI1/SDA1/SEG16
RC3/SCK1/SCL1/SEG17
RC2/CCP1/P1A/SEG13
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG43/C3OUT/CK2/TX2/CPS15/AN15/RG1
SEG44/C3IN+/DT2/RX2/CPS14/AN14/RG2
SEG45/P3D/CCP4/C3IN0-/CPS13/AN13/RG3
VPP/MCLR/RG5
PIC16F/LF1946/47
SEG26/P1D/CCP5/C3IN1-/CPS12/AN12/RG4
VSS
VDD
9
10
11
12
13
14
15
16
SEG25/SS1/C1IN3-/C2IN3-/C3IN3-/CPS5/AN5/RF7
SEG24/C1IN+/CPS11/AN11/RF6
SEG23/DACOUT/C1IN1-/C2IN1-/CPS10/AN10/RF5
SEG22/C2IN+/CPS9/AN9/RF4
SEG21/C1IN2-/C2IN2-/C3IN2-/CPS8/AN8/RF3
SEG20/SRQ/C1OUT/CPS7/AN7/RF2
17 18 19 20 21 22 23 24 25 26 27 28
29 3031 32
Note 1: Pin location selected by APFCON register setting.
2: QFN package orientation is the same. No leads are present on the QFN package.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 3
PIC16F/LF1946/47
TABLE 1:
64-PIN SUMMARY(PIC16F/LF1946/47)
RA0 24
RA1 23
RA2 22
RA3 21
RA4 28
RA5 27
RA6 40
Y
Y
AN0
AN1
AN2
AN3
—
—
—
CPS0
CPS1
CPS2
CPS3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SEG33
SEG18
SEG34
SEG35
SEG14
SEG15
SEG36
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
VREF-
VREF+
—
—
Y
—
—
Y
T0CKI
—
AN4
—
—
CPS4
—
—
—
—
OSC2/
CLK-
OUT
RA7 39
RB0 48
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SEG37
SEG30
—
—
Y
OSC1/
CLKIN
SRI
FLT0
INT/
IOC
—
RB1 47
RB2 46
RB3 45
RB4 44
RB5 43
RB6 42
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SEG8
SEG9
IOC
IOC
IOC
IOC
IOC
IOC
Y
Y
Y
Y
Y
Y
—
—
—
—
—
—
SEG10
SEG11
SEG29
SEG38
—
T1G
—
ICSP-
CLK/
ICDCLK
RB7 37
—
—
—
—
—
—
—
—
—
—
SEG39
IOC
Y
ICSP-
DAT/
ICDDAT
RC0 30
RC1 29
RC2 33
RC3 34
RC4 35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1OSO/
T1CKI
T1OSI CCP2(1)
P2A(1)
—
—
—
—
—
—
—
—
—
—
SEG40
SEG32
SEG13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
/
—
—
—
CCP1/
P1A
—
—
SCK1/ SEG17
SCL1
SDI1/ SEG16
SDA1
RC5 36
RC6 31
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDO1 SEG12
—
—
—
—
—
—
TX1/
CK1
—
SEG27
RC7 32
—
—
—
—
—
—
—
—
RX1/
DT1
—
SEG28
—
—
—
RD0 58
RD1 55
RD2 54
RD3 53
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P2D(1)
P2C(1)
P2B(1)
—
—
—
—
—
—
—
—
SEG0
SEG1
SEG2
SEG3
—
—
—
—
—
—
—
—
—
—
—
—
P3C(1)
P3B(1)
P1C(1)
RD4 52
RD5 51
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDO2
SEG4
SEG5
—
—
—
—
—
—
SDI2
SDA2
RD6 50
—
—
—
—
—
—
—
—
P1B(1)
—
—
—
SCK2/ SEG6
SCL2
—
—
—
—
—
—
RD7 49
—
—
—
—
—
—
SS2
SEG7
Note 1: Pin functions can be moved using the APFCON register(s).
2: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
3: See Section 8.0.
DS41414A-page 4
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 1:
64-PIN SUMMARY(PIC16F/LF1946/47) (Continued)
RE0
RE1
2
1
Y
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P2D(1)
P2C(1)
P2B(1)
—
—
—
VLCD1
VLCD2
VLCD3
—
—
—
—
—
—
—
—
—
—
—
RE2 64
RE3 63
RE4 62
RE5 61
RE6 60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P3C(1)
P3B(1)
P1C(1)
P1B(1)
—
—
—
—
—
—
—
—
COM0
COM1
COM2
COM3
—
—
—
—
—
—
—
—
—
—
—
—
CCP2(1)
P2A(1)
/
RE7 59
RF0 18
—
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
SEG31
SEG41
—
—
—
—
—
(3)
AN16
CPS16 C1IN0-
C2IN0-
—
VCAP
RF1 17
Y
AN6
—
—
CPS6
C2OUT
C1OUT
SRNQ
—
—
—
SEG19
—
—
—
—
—
—
RF2 16
RF3 15
Y
Y
AN7
AN8
CPS7
CPS8
SRQ
—
—
—
—
—
—
—
SEG20
SEG21
—
—
—
—
—
—
C1IN2-
C2IN2-
C3IN2-
RF4 14
RF5 13
Y
Y
AN9
—
CPS9
C2IN+
—
—
—
—
—
—
—
—
—
SEG22
SEG23
—
—
—
—
—
—
AN10 DACOUT CPS10
C1IN1-
C2IN1-
RF6 12
RF7 11
Y
Y
AN11
AN5
—
—
CPS11
CPS5
C1IN+
—
—
—
—
—
—
—
—
—
SEG24
SEG25
—
—
—
—
—
—
C1IN3-
C2IN3-
C3IN3-
SS1
RG0
RG1
RG2
3
4
5
—
Y
—
—
—
—
—
—
—
—
—
—
—
—
CCP3
P3A
—
—
—
—
—
SEG42
SEG43
SEG44
—
—
—
—
—
—
—
—
—
—
—
—
AN15
AN14
CPS15 C3OUT
CPS14 C3IN+
—
TX2/
CK2
Y
—
RX2/
DT2
—
RG3
RG4
RG5
6
8
7
Y
Y
AN13
AN12
—
—
—
—
CPS13 C3IN0-
CPS12 C3IN1-
—
—
—
—
—
—
CCP4
P3D
SEG45
SEG26
—
CCP5
P1D
—
—
—
—
—
—
—
—
Y(2)
—
MCLR/
VPP
—
—
—
—
—
—
VDD 10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
26
38
57
VSS
9
—
—
—
—
VSS
25
41
56
AVDD 19
AVSS 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AVDD
AVSS
Note 1: Pin functions can be moved using the APFCON register(s).
2: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
3: See Section 8.0.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 5
PIC16F/LF1946/47
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 17
3.0 Memory Organization................................................................................................................................................................. 19
4.0 Device Configuration .................................................................................................................................................................. 53
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 59
6.0 Resets ........................................................................................................................................................................................ 75
7.0 Interrupts .................................................................................................................................................................................... 83
8.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 99
9.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 101
10.0 Watchdog Timer....................................................................................................................................................................... 103
11.0 Data EEPROM and Flash Program Memory Control............................................................................................................... 107
12.0 I/O Ports ................................................................................................................................................................................... 121
13.0 Interrupt-On-Change ................................................................................................................................................................ 147
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 151
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 153
16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 167
17.0 Comparator Module.................................................................................................................................................................. 173
18.0 SR Latch................................................................................................................................................................................... 181
19.0 Timer0 Module ......................................................................................................................................................................... 187
20.0 Timer1 Module with Gate Control............................................................................................................................................. 191
21.0 Timer2/4/6 Modules.................................................................................................................................................................. 203
22.0 Capture/Compare/PWM Modules ............................................................................................................................................ 207
23.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module .............................................................................................. 235
24.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 289
25.0 Capacitive Sensing Module...................................................................................................................................................... 317
26.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 327
27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 363
28.0 Instruction Set Summary.......................................................................................................................................................... 367
29.0 Electrical Specifications ........................................................................................................................................................... 381
30.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 413
31.0 Development Support............................................................................................................................................................... 415
32.0 Packaging Information.............................................................................................................................................................. 419
Appendix A: Data Sheet Revision History.......................................................................................................................................... 425
Appendix B: Migrating From Other PIC® Devices ............................................................................................................................. 425
Index .................................................................................................................................................................................................. 427
The Microchip Web Site..................................................................................................................................................................... 435
Customer Change Notification Service .............................................................................................................................................. 435
Customer Support.............................................................................................................................................................................. 435
Reader Response .............................................................................................................................................................................. 436
Product Identification System............................................................................................................................................................. 437
DS41414A-page 6
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
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2010 Microchip Technology Inc.
Preliminary
DS41414A-page 7
PIC16F/LF1946/47
NOTES:
DS41414A-page 8
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
1.0
DEVICE OVERVIEW
The PIC16F/LF1946/47 are described within this data
sheet. They are available in 64-pin packages.
Figure 1-1 shows
a
block diagram of the
PIC16F/LF1946/47 devices. Table 1-2 shows the pin-
out descriptions.
Reference Table 1-1 for peripherals available per
device.
TABLE 1-1:
DEVICE PERIPHERAL
SUMMARY
Peripheral
ADC
●
●
●
●
●
●
●
●
Capacitive Sensing Module (CSM)
●
●
●
●
●
●
Data EEPROM
Digital-to-Analog Converter (DAC)
Fixed Voltage Reference (FVR)
LCD
SR Latch
Capture/Compare/PWM Modules
ECCP1
●
●
●
●
●
●
●
●
●
●
ECCP2
ECCP3
CCP4
CCP5
Comparators
C1
●
●
●
●
●
●
C2
C3
EUSARTS
EUSART1
●
●
●
●
EUSART2
Master Synchronous Serial Ports
MSSP1
●
●
●
●
MSSP2
Timers
Timer0
Timer1
Timer2
Timer4
Timer6
●
●
●
●
●
●
●
●
●
●
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 9
PIC16F/LF1946/47
FIGURE 1-1:
PIC16F/LF1946/47 BLOCK DIAGRAM
Program
Flash Memory
EEPROM
PORTA
RAM
OSC2/CLKO
OSC1/CLKI
Timing
Generation
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
CPU
INTRC
Oscillator
Figure 2-1
MCLR
SR
Latch
ADC
10-Bit
Timer0
ECCP2
Timer1
Timer2
CCP4
Timer4
CCP5
Comparators
EUSARTx
Timer6
MSSPx
LCD
ECCP1
ECCP3
Note 1: See applicable chapters for more information on peripherals.
DS41414A-page 10
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 1-2:
PIC16F/LF1946/47 PINOUT DESCRIPTION
Input Output
Function
Name
Description
Type
Type
RA0/AN0/CPS0/SEG33
RA0
AN0
TTL
AN
AN
—
CMOS General purpose I/O.
—
—
A/D Channel 0 input.
Capacitive sensing input 0.
LCD Analog output.
CPS0
SEG33
AN
RA1/AN1/CPS1/SEG18
RA1
AN1
TTL
AN
AN
—
CMOS General purpose I/O.
—
—
A/D Channel 1 input.
Capacitive sensing input 1.
LCD Analog output.
CPS1
SEG18
RA2
AN
RA2/AN2/VREF-/CPS2/SEG34
TTL
AN
AN
AN
—
CMOS General purpose I/O.
AN2
—
—
A/D Channel 2 input.
VREF-
CPS2
SEG34
RA3
A/D Negative Voltage Reference input.
Capacitive sensing input 2.
LCD Analog output.
—
AN
RA3/AN3/VREF+/CPS3/SEG35
TTL
AN
AN
AN
—
CMOS General purpose I/O.
AN3
—
—
A/D Channel 3 input.
VREF+
CPS3
SEG35
RA4
A/D Voltage Reference input.
Capacitive sensing input 3.
LCD Analog output.
—
AN
RA4/T0CKI/SEG14
TTL
ST
CMOS General purpose I/O.
T0CKI
SEG14
RA5
—
Timer0 clock input.
LCD Analog output.
—
AN
RA5/AN4/CPS4/SEG15
TTL
AN
AN
—
CMOS General purpose I/O.
AN4
—
—
A/D Channel 4 input.
Capacitive sensing input 4.
LCD Analog output.
CPS4
SEG5
RA6
AN
RA6/OSC2/CLKOUT/SEG36
RA7/OSC1/CLKIN/SEG37
RB0/INT/SRI/FLT0/SEG30
TTL
—
CMOS General purpose I/O.
OSC2
CLKOUT
SEG36
RA7
XTAL Crystal/Resonator (LP, XT, HS modes).
CMOS FOSC/4 output.
—
—
AN
LCD Analog output.
TTL
XTAL
CMOS
—
CMOS General purpose I/O.
OSC1
CLKIN
SEG37
RB0
—
—
Crystal/Resonator (LP, XT, HS modes).
External clock input (EC mode).
LCD Analog output.
AN
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
INT
SRI
ST
—
—
ST
—
External interrupt.
SR Latch input.
FLT0
SEG30
RB1
ST
—
ECCP Auto-shutdown Fault input.
LCD analog output.
AN
RB1/SEG8
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
SEG8
—
AN
LCD Analog output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 11
PIC16F/LF1946/47
TABLE 1-2:
PIC16F/LF1946/47 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
RB2/SEG9
RB2
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
SEG9
RB3
—
AN
LCD Analog output.
RB3/SEG10
RB4/SEG11
RB5/T1G/SEG29
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
SEG10
RB4
—
AN
LCD Analog output.
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
SEG11
RB5
—
AN
LCD Analog output.
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
T1G
SEG29
RB6
ST
—
—
Timer1 Gate input.
LCD Analog output.
AN
RB6/ICSPCLK/ICDCLK/SEG38
RB7/ICSPDAT/ICDDAT/SEG39
RC0/T1OSO/T1CKI/SEG40
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPCLK
ICDCLK
SEG38
RB7
ST
ST
—
—
—
Serial Programming Clock.
In-Circuit Debug Clock.
LCD Analog output.
AN
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPDAT
ICDDAT
SEG39
RC0
ST
ST
—
CMOS ICSP™ Data I/O.
CMOS In-Circuit Data I/O.
AN
LCD Analog output.
ST
XTAL
ST
—
CMOS General purpose I/O.
T1OSO
T1CKI
SEG40
RC1
XTAL Timer1 oscillator connection.
—
Timer1 clock input.
LCD Analog output.
AN
(1)
(1)
RC1/T1OSI/P2A /CCP2
/
ST
XTAL
—
CMOS General purpose I/O.
XTAL Timer1 oscillator connection.
CMOS PWM output.
SEG32
T1OSI
P2A
CCP2
SEG32
RC2
ST
—
CMOS Capture/Compare/PWM2.
AN
LCD Analog output.
RC2/CCP1/P1A/SEG13
RC3/SCK/SCL/SEG17
RC4/SDI1/SDA1/SEG16
ST
ST
—
CMOS General purpose I/O.
CMOS Capture/Compare/PWM1.
CMOS PWM output.
CCP1
P1A
SEG13
RC3
—
AN
LCD Analog output.
ST
ST
CMOS General purpose I/O.
SCK
CMOS SPI clock.
2
2
SCL
I C
OD
AN
I C™ clock.
SEG17
RC4
—
ST
ST
LCD Analog output.
CMOS General purpose I/O.
SDI1
—
SPI data input.
2
2
SDA1
SEG16
I C
OD
AN
I C™ data input/output.
—
LCD Analog output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
DS41414A-page 12
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 1-2:
PIC16F/LF1946/47 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
RC5/SDO1/SEG12
RC5
SDO1
SEG12
RC6
ST
—
CMOS General purpose I/O.
CMOS SPI data output.
—
AN
LCD Analog output.
RC6/TX1/CK1/SEG27
ST
—
CMOS General purpose I/O.
TX1
CMOS USART1 asynchronous transmit.
CMOS USART1 synchronous clock.
CK1
ST
—
SEG27
RC7
AN
LCD Analog output.
RC7/RX1/DT1/SEG28
ST
ST
ST
—
CMOS General purpose I/O.
RX
—
USART1 asynchronous input.
DT1
CMOS USART1 synchronous data.
SEG28
RD0
AN
LCD Analog output.
(1)
RD0/P2D /SEG0
ST
—
CMOS General purpose I/O.
CMOS PWM output.
P2D
SEG0
RD1
—
AN
LCD Analog output.
(1)
RD1/P2C /SEG1
ST
—
CMOS General purpose I/O.
CMOS PWM output.
P2C
SEG1
RD2
—
AN
LCD Analog output.
(1)
RD2/P2B /SEG2
ST
—
CMOS General purpose I/O.
CMOS PWM output.
P2B
SEG2
RD3
—
AN
LCD Analog output.
(1)
RD3/P3C /SEG3
ST
—
CMOS General purpose I/O.
CMOS PWM output.
P3C
SEG3
RD4
—
AN
LCD analog output.
(1)
RD4/SDO2/P3B /SEG4
ST
—
CMOS General purpose I/O.
CMOS SPI data output.
CMOS PWM output.
SDO2
P3B
—
SEG4
RD5
—
AN
LCD analog output.
(1)
RD5/SDI2/SDA2/P1C /SEG5
ST
ST
CMOS General purpose I/O.
SDI2
SDA2
P1C
—
SPI data input.
2
2
I C
OD
I C™ data input/output.
—
—
CMOS PWM output.
SEG5
RD6
AN
LCD analog output.
(1)
RD6/SCK2/SCL2/P1B /SEG6
ST
CMOS General purpose I/O.
SCK2
SCL2
P1B
ST
CMOS SPI clock.
2
2
I C
OD
I C™ clock.
—
—
CMOS PWM output.
SEG6
RD7
AN
LCD analog output.
RD7/SS2/SEG7
ST
ST
—
CMOS General purpose I/O.
SS2
—
Slave Select input.
LCD analog output.
SEG7
RE0
AN
(1)
RE0/P2D /VLCD1
ST
—
CMOS General purpose I/O.
CMOS PWM output.
P2D
VLCD1
AN
—
LCD analog input.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 13
PIC16F/LF1946/47
TABLE 1-2:
PIC16F/LF1946/47 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
(1)
RE1/P2C /VLCD2
RE1
P2C
ST
—
CMOS General purpose I/O.
CMOS PWM output.
VLCD2
RE2
AN
ST
—
—
LCD analog input.
(1)
RE2/P2B /VLCD3
CMOS General purpose I/O.
CMOS PWM output.
P2B
VLCD3
RE3
AN
TTL
—
—
—
LCD analog input.
(1)
RE3/P3C /COM0
General purpose input.
P3C
CMOS PWM output.
COM0
RE4
—
AN
—
LCD Analog output.
General purpose input.
(1)
RE4/P3B /COM1
TTL
—
P3B
CMOS PWM output.
COM1
RE5
—
AN
—
LCD Analog output.
General purpose input.
(1)
RE5/P1C /COM2
TTL
—
P1C
CMOS PWM output.
COM2
RE6
—
AN
—
LCD Analog output.
General purpose input.
(1)
RE6/P1B /COM3
TTL
—
P1B
CMOS PWM output.
COM3
RE7
—
AN
—
LCD Analog output.
General purpose input.
(1)
(1)
RE7/CCP2 /P2A /SEG31
TTL
ST
—
CCP2
P2A
CMOS Capture/Compare/PWM2.
CMOS PWM output.
SEG31
RF0
—
AN
LCD analog output.
RF0/AN16/CPS16/C12IN0-/
SEG41/VCAP
TTL
AN
AN
AN
AN
—
CMOS General purpose I/O.
AN16
CPS16
C1IN0-
C2IN0-
SEG41
VCAP
RF1
—
—
A/D Channel 16 input.
Capacitive sensing input 16.
Comparator C1 negative input.
Comparator C2 negative input.
LCD Analog output.
—
—
AN
Power Power Filter capacitor for Voltage Regulator.
RF1/AN6/CPS6/C2OUT/SRNQ/
SEG19
TTL
AN
AN
—
CMOS General purpose I/O.
AN6
—
—
A/D Channel 6 input.
CPS6
C2OUT
SRNQ
SEG19
RF2
Capacitive sensing input 6.
CMOS Comparator C2 output.
CMOS SR Latch inverting output.
—
—
AN
LCD Analog output.
RF2/AN7/CPS7/C1OUT/SRQ/
SEG20
TTL
AN
AN
—
CMOS General purpose I/O.
AN7
—
—
A/D Channel 7 input.
CPS7
C1OUT
SRQ
Capacitive sensing input 7.
CMOS Comparator C1 output.
—
CMOS SR Latch non-inverting output.
SEG20
—
AN
LCD Analog output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
DS41414A-page 14
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 1-2:
PIC16F/LF1946/47 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
RF3/AN8/CPS8/C123IN2-/
SEG21
RF3
AN8
TTL
AN
AN
AN
AN
AN
—
CMOS General purpose I/O.
—
—
—
A/D Channel 8 input.
CPS8
C1IN2-
C2IN2-
C3IN2-
SEG21
RF4
Capacitive sensing input 8.
Comparator C1 negative input.
Comparator C2 negative input.
Comparator C3 negative input.
LCD Analog output.
—
—
AN
RF4/AN9/CPS9/C2IN+/SEG22
TTL
AN
AN
AN
—
CMOS General purpose I/O.
AN9
—
—
A/D Channel 9 input.
CPS9
C2IN+
SEG22
RF5
Capacitive sensing input 9.
Comparator C2 positive input.
LCD Analog output.
—
AN
RF5/AN10/CPS10/C12IN1-/
DACOUT/SEG23
TTL
AN
AN
AN
AN
—
CMOS General purpose I/O.
AN10
CPS10
C1IN1-
C2IN1-
DACOUT
SEG23
RF6
—
—
A/D Channel 10 input.
Capacitive sensing input 10.
Comparator C1 negative input.
Comparator C2 negative input.
Voltage Reference output.
LCD Analog output.
—
—
AN
AN
—
RF6/AN11/CPS11/C1IN+/SEG24
TTL
AN
AN
AN
—
CMOS General purpose I/O.
AN11
—
—
A/D Channel 11 input.
CPS11
C1IN+
SEG24
RF7
Capacitive sensing input 11.
Comparator C1 positive input.
LCD Analog output.
—
AN
RF7/AN5/CPS5/C123IN3-/SS1/
SEG25
TTL
AN
AN
AN
AN
AN
ST
—
CMOS General purpose I/O.
AN5
—
—
—
A/D Channel 5 input.
CPS5
C1IN3-
C2IN3-
C3IN3-
SS1
Capacitive sensing input 5.
Comparator C1negative input.
Comparator C2 negative input.
Comparator C3 negative input.
Slave Select input.
—
—
—
AN
SEG25
RG0
LCD Analog output.
RG0/CCP3/P3A/SEG42
ST
ST
—
CMOS General purpose I/O.
CMOS Capture/Compare/PWM3.
CMOS PWM output.
CCP3
P3A
SEG42
RG1
—
AN
LCD Analog output.
RG1/AN15/CPS15/TX2/CK2/
C3OUT/SEG43
ST
AN
AN
—
CMOS General purpose I/O.
AN15
CPS15
TX2
—
—
A/D Channel 15 input.
Capacitive sensing input 15.
CMOS USART2 asynchronous transmit.
CMOS USART2 synchronous clock.
CMOS Comparator C3 output.
CK2
ST
—
C3OUT
SEG43
—
AN
LCD Analog output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 15
PIC16F/LF1946/47
TABLE 1-2:
PIC16F/LF1946/47 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
RG2/AN14/CPS14/RX2/DT2/
C3IN+/SEG44
RG2
AN14
CPS14
RX2
ST
AN
AN
ST
CMOS General purpose I/O.
—
—
—
A/D Channel 14 input.
Capacitive sensing input 14.
USART2 asynchronous input.
DT2
ST
CMOS USART2 synchronous data.
C3IN+
SEG44
RG3
AN
—
—
Comparator C3 positive input.
LCD Analog output.
AN
RG3/AN13/CPS13/C3IN0-/
CCP4/P3D/SEG45
ST
CMOS General purpose I/O.
AN13
CPS13
C3IN0-
CCP4
P3D
AN
AN
AN
ST
—
—
—
A/D Channel 13 input.
Capacitive sensing input 13.
Comparator C3 negative input.
CMOS Capture/Compare/PWM4.
CMOS PWM output.
—
SEG45
RG4
—
AN
LCD Analog output.
RG4/AN12/CPS12/C3IN1-/
CCP5/P1D/SEG26
ST
CMOS General purpose I/O.
AN12
CPS12
C3IN1-
CCP5
P1D
AN
AN
AN
ST
—
—
—
A/D Channel 12 input.
Capacitive sensing input 12.
Comparator C3 negative input.
CMOS Capture/Compare/PWM5.
CMOS PWM output.
—
SEG26
RG5
—
AN
—
—
—
—
—
LCD Analog output.
RG5/MCLR/VPP
TTL
ST
General purpose input.
Master Clear with internal pull-up.
Programming voltage.
Positive supply.
MCLR
VPP
HV
Power
Power
VDD
VSS
VDD
VSS
Ground reference.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
DS41414A-page 16
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
2.0
ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
2.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2
16-level Stack with Overflow and
Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft-
ware Reset. See section Section 3.4 “Stack” for more
details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one data pointer for all memory. When an
FSR points to program memory, there is 1 additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 28.0 “Instruction Set Summary” for more
details.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 17
PIC16F/LF1946/47
FIGURE 2-1:
CORE BLOCK DIAGRAM
15
Configuration
15
8
Data Bus
RAM
Program Counter
Flash
Program
Memory
16-LevelStack
(15-bit)
Program
Bus
14
RAM Addr
Program Memory
Read (PMR)
12
Addr MUX
InstructionReg
Indirect
Addr
7
Direct Addr
12
12
5
BSR Reg
15
FSR0 Reg
FSR1 Reg
15
STATUSReg
8
3
MUX
Power-up
Timer
Oscillator
Instruction
Decodeand
Control
Start-up Timer
ALU
Power-on
Reset
OSC1/CLKIN
8
Timing
Generation
Watchdog
Timer
W Reg
OSC2/CLKOUT
Brown-out
Reset
Internal
Oscillator
Block
VDD
VSS
DS41414A-page 18
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
The following features are associated with access and
control of program memory and data memory:
3.0
MEMORY ORGANIZATION
There are three types of memory in PIC16F/LF1946/47
devices: Data Memory, Program Memory and Data
• PCL and PCLATH
• Stack
EEPROM Memory(1)
.
• Indirect Addressing
• Program Memory
• Data Memory
3.1
Program Memory Organization
- Core Registers
The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16F/LF1946/47 family.
Accessing a location above these boundaries will cause
a wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1, 3-1 and 3-2).
- Special Function Registers
- General Purpose RAM
- Common RAM
- Device Memory Maps
- Special Function Registers Summary
• Data EEPROM memory(1)
Note 1: The data EEPROM memory and the
method to access Flash memory through
the EECON registers is described in
Section 11.0 “Data EEPROM and Flash
Program Memory Control”.
TABLE 3-1:
DEVICE SIZES AND ADDRESSES
Device Program Memory Space (Words)
PIC16F/LF1946
Last Program Memory Address
8,192
1FFFh
3FFFh
PIC16F/LF1947
16,384
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 19
PIC16F/LF1946/47
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR
FIGURE 3-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16F/LF1946
PIC16F/LF1947
PC<14:0>
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
Stack Level 0
Stack Level 1
Stack Level 0
Stack Level 1
Stack Level 15
Reset Vector
Stack Level 15
Reset Vector
0000h
0000h
Interrupt Vector
Page 0
0004h
0005h
Interrupt Vector
Page 0
0004h
0005h
On-chip
Program
Memory
07FFh
0800h
07FFh
0800h
Page 1
Page 2
Page 1
Page 2
On-chip
Program
Memory
0FFFh
1000h
0FFFh
1000h
17FFh
1800h
17FFh
1800h
Page 3
Page 3
Page 4
1FFFh
2000h
1FFFh
2000h
Rollover to Page 0
Page 7
3FFFh
4000h
Rollover to Page 0
Rollover to Page 3
Rollover to Page 7
7FFFh
7FFFh
DS41414A-page 20
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
3.1.1
READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in pro-
gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1
RETLWInstruction
The RETLWinstruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1:
RETLW INSTRUCTION
constants
brw
;Add Index in W to
;program counter to
;select data
retlw DATA0
retlw DATA1
retlw DATA2
retlw DATA3
;Index0 data
;Index1 data
my_function
;… LOTS OF CODE…
movlw DATA_INDEX
call constants
;… THE CONSTANT IS IN W
The BRWinstruction makes this type of table very sim-
ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 21
PIC16F/LF1946/47
3.1.1.2
Indirect Read with FSR
3.2.1
CORE REGISTERS
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIWinstruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access-
ing the program memory via an FSR.
The core registers contain the registers that directly
affect the basic operation of the PIC16F/LF1946/47.
These registers are listed below:
• INDF0
• INDF1
• PCL
• STATUS
• FSR0 Low
• FSR0 High
• FSR1 Low
• FSR1 High
• BSR
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
• WREG
constants
• PCLATH
• INTCON
retlw DATA0
retlw DATA1
retlw DATA2
retlw DATA3
my_function
;Index0 data
;Index1 data
Note:
The core registers are the first 12
addresses of every data memory bank.
;… LOTS OF CODE…
movlw
movwf
movlw
movwf
LOW constants
FSR1L
HIGH constants
FSR1H
moviw 0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.2
Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
DS41414A-page 22
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u= unchanged).
3.2.1.1
STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 28.0
“Instruction Set Summary”).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as Borrow and
Digit Borrow out bits, respectively, in
subtraction.
REGISTER 3-1:
STATUS: STATUS REGISTER
U-0
—
U-0
—
U-0
—
R-1/q
TO
R-1/q
PD
R/W-0/u
Z
R/W-0/u
DC(1)
R/W-0/u
C(1)
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-5
bit 4
Unimplemented: Read as ‘0’
TO: Time-out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
bit 3
bit 2
bit 1
bit 0
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 23
PIC16F/LF1946/47
3.2.2
SPECIAL FUNCTION REGISTER
3.2.5
DEVICE MEMORY MAPS
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The registers asso-
ciated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.
The memory maps for the device family are as shown
in Table 3-2.
TABLE 3-2:
Device
MEMORY MAP TABLES
Banks
Table No.
PIC16F/LF1946/47
0-7
Table 3-3
Table 3-4, Table 3-7
Table 3-5
3.2.3
GENERAL PURPOSE RAM
8-15
There are up to 80 bytes of GPR in each data memory
bank.
16-23
23-31
Table 3-6, Table 3-8
3.2.3.1
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-3:
BANKED MEMORY
PARTITIONING
Memory Region
7-bit Bank Offset
00h
Core Registers
(12 bytes)
0Bh
0Ch
Special Function Registers
(20 bytes maximum)
1Fh
20h
General Purpose RAM
(80 bytes maximum)
6Fh
70h
Common RAM
(16 bytes)
7Fh
DS41414A-page 24
Preliminary
2010 Microchip Technology Inc.
TABLE 3-3:
PIC16F/LF1946/1947 MEMORY MAP, BANKS 0-7
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
INDF0
INDF1
PCL
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
INDF0
INDF1
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
INDF0
INDF1
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
INDF0
INDF1
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
INDF0
INDF1
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
INDF0
INDF1
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
INDF0
INDF1
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATF
LATG
—
PCL
PCL
PCL
PCL
PCL
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
STATUS
FSR0L
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
FSR0H
FSR1L
FSR0H
FSR1L
FSR0H
FSR1L
FSR1H
BSR
FSR1H
BSR
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB
PORTC
PORTD
PORTE
PIR1
WREG
PCLATH
INTCON
TRISA
WREG
WREG
PCLATH
INTCON
ANSELA
—
WREG
WREG
WREG
PCLATH
INTCON
TRISF
PCLATH
INTCON
LATA
PCLATH
INTCON
—
PCLATH
INTCON
PORTF
PORTG
—
TRISB
LATB
WPUB
TRISG
—
TRISC
LATC
—
—
TRISD
LATD
—
—
—
—
—
TRISE
LATE
ANSELE
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
—
—
—
—
PIE1
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
—
—
PIR2
PIE2
—
PIR3
PIE3
—
PIR4
PIE4
IOCBP
IOCBN
IOCBF
—
TMR0
OPTION
PCON
TMR1L
TMR1H
T1CON
T1GCON
TMR2
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
CCPR4L
CCPR4H
CCP4CON
—
—
RC1REG
TX1REG
SP1BRGL
SP1BRGH
RC1STA
TX1STA
SSP2BUF
SSP2ADD
SSP2MSK
SSP2STAT
SSP2CON1
SSP2CON2
—
—
PR2
—
T2CON
—
CCPR5L
CCPR5H
CCP5CON
—
APFCON
CM3CON0
—
CPSCON0
—
01Fh
020h
CPSCON1
09Fh
0A0h
—
11Fh
120h
CM3CON1
19Fh
1A0h
BAUD1CON
21Fh
220h
SSP2CON3
29Fh
2A0h
CCPTMRS1
31Fh
320h
—
39Fh
3A0h
—
General Purpose
Register
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
16 Bytes
32Fh
330h
Register
General
Purpose
Register
96 Bytes
General Purpose
Register
80 Bytes(1)
64 Bytes(1)
36Fh
370h
3EFh
3F0h
06Fh
070h
0EFh
0F0h
16Fh
170h
1EFh
1F0h
26Fh
270h
2EFh
2F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
07Fh
0FFh
17Fh
1FFh
27Fh
2FFh
37Fh
3FFh
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’.
Not available on PIC16F1946.
TABLE 3-4:
PIC16F/LF1946/1947 MEMORY MAP, BANKS 8-15
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
BANK 15
INDF0
INDF1
PCL
INDF0
INDF1
PCL
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
60Ah
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
780h
781h
782h
783h
784h
785h
786h
787h
788h
789h
78Ah
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELF
ANSELG
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
WPUG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RC2REG
TX2REG
SP2BRG
SP2BRGH
RC2STA
TX2STA
BAUDCON2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR4
PR4
—
—
—
—
—
—
—
—
—
—
T4CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
See Table 3-7
TMR6
PR6
—
—
—
—
—
—
—
—
—
—
—
—
T6CON
—
—
—
—
—
—
—
—
—
—
—
—
—
41Fh
420h
49Fh
4A0h
51Fh
520h
59Fh
5A0h
61Fh
620h
69Fh
6A0h
71Fh
720h
79Fh
7A0h
General Purpose
Register
General
Purpose
General
Purpose
General
Purpose
General
Purpose
48 Bytes(1)
Unimplemented
Unimplemented
Register
Register
Register
Register
Read as ‘0’
Read as ‘0’
80 Bytes(1)
80 Bytes(1)
80 Bytes(1)
80 Bytes(1)
Unimplemented
Read as ‘0’
46Fh
470h
4EFh
4F0h
56Fh
570h
5EFh
5F0h
66Fh
670h
6EFh
6F0h
76Fh
770h
7EFh
7F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
4FFh
57Fh
47Fh
5FFh
67Fh
6FFh
77Fh
7FFh
Legend:
= Unimplemented data memory locations, read as ‘0’
Note 1:
Not available on PIC16F1946.
TABLE 3-5:
PIC16F/LF1946/47 MEMORY MAP, BANKS 16-23
BANK 16
BANK 17
BANK 18
BANK 19
BANK 20
BANK 21
BANK 22
BANK 23
800h
801h
802h
803h
804h
805h
806h
807h
808h
809h
80Ah
80Bh
80Ch
80Dh
80Eh
80Fh
810h
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
880h
881h
882h
883h
884h
885h
886h
887h
888h
889h
88Ah
88Bh
88Ch
88Dh
88Eh
88Fh
890h
891h
892h
893h
894h
895h
896h
897h
898h
899h
89Ah
89Bh
89Ch
89Dh
89Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
900h
901h
902h
903h
904h
905h
906h
907h
908h
909h
90Ah
90Bh
90Ch
90Dh
90Eh
90Fh
910h
911h
912h
913h
914h
915h
916h
917h
918h
919h
91Ah
91Bh
91Ch
91Dh
91Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
980h
981h
982h
983h
984h
985h
986h
987h
988h
989h
98Ah
98Bh
98Ch
98Dh
98Eh
98Fh
990h
991h
992h
993h
994h
995h
996h
997h
998h
999h
99Ah
99Bh
99Ch
99Dh
99Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
A00h
A01h
A02h
A03h
A04h
A05h
A06h
A07h
A08h
A09h
A0Ah
A0Bh
A0Ch
A0Dh
A0Eh
A0Fh
A10h
A11h
A12h
A13h
A14h
A15h
A16h
A17h
A18h
A19h
A1Ah
A1Bh
A1Ch
A1Dh
A1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
A80h
A81h
A82h
A83h
A84h
A85h
A86h
A87h
A88h
A89h
A8Ah
A8Bh
A8Ch
A8Dh
A8Eh
A8Fh
A90h
A91h
A92h
A93h
A94h
A95h
A96h
A97h
A98h
A99h
A9Ah
A9Bh
A9Ch
A9Dh
A9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
B00h
B01h
B02h
B03h
B04h
B05h
B06h
B07h
B08h
B09h
B0Ah
B0Bh
B0Ch
B0Dh
B0Eh
B0Fh
B10h
B11h
B12h
B13h
B14h
B15h
B16h
B17h
B18h
B19h
B1Ah
B1Bh
B1Ch
B1Dh
B1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
B80h
B81h
B82h
B83h
B84h
B85h
B86h
B87h
B88h
B89h
B8Ah
B8Bh
B8Ch
B8Dh
B8Eh
B8Fh
B90h
B91h
B92h
B93h
B94h
B95h
B96h
B97h
B98h
B99h
B9Ah
B9Bh
B9Ch
B9Dh
B9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
81Fh
820h
—
89Fh
8A0h
—
91Fh
920h
—
99Fh
9A0h
—
A1Fh
A20h
—
A9Fh
AA0h
—
B1Fh
B20h
—
B9Fh
BA0h
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
9EFh
9F0h
AEFh
AF0h
BEFh
BF0h
86Fh
870h
8EFh
8F0h
96Fh
970h
A6Fh
A70h
B6Fh
B70h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
87Fh
8FFh
97Fh
9FFh
A7Fh
AFFh
B7Fh
BFFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
TABLE 3-6:
PIC16F/LF1946/47 MEMORY MAP, BANKS 24-31
BANK 24
BANK 25
BANK 26
BANK 27
BANK 28
BANK 29
BANK 30
BANK 31
C00h
C01h
C02h
C03h
C04h
C05h
C06h
C07h
C08h
C09h
C0Ah
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
C80h
C81h
C82h
C83h
C84h
C85h
C86h
C87h
C88h
C89h
C8Ah
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
D00h
D01h
D02h
D03h
D04h
D05h
D06h
D07h
D08h
D09h
D0Ah
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
D80h
D81h
D82h
D83h
D84h
D85h
D86h
D87h
D88h
D89h
D8Ah
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
E00h
E01h
E02h
E03h
E04h
E05h
E06h
E07h
E08h
E09h
E0Ah
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
E80h
E81h
E82h
E83h
E84h
E85h
E86h
E87h
E88h
E89h
E8Ah
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
F00h
F01h
F02h
F03h
F04h
F05h
F06h
F07h
F08h
F09h
F0Ah
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
F80h
F81h
F82h
F83h
F84h
F85h
F86h
F87h
F88h
F89h
F8Ah
F8Bh
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
F98h
F99h
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
See Table 3-8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1Fh
C20h
—
C9Fh
CA0h
—
D1Fh
D20h
—
D9Fh
DA0h
—
E1Fh
E20h
—
E9Fh
EA0h
—
F1Fh
F20h
—
F9Fh
FA0h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
C6Fh
C70h
CEFh
CF0h
D6Fh
D70h
DEFh
DF0h
E6Fh
E70h
EEFh
EF0h
F6Fh
F70h
FEFh
FF0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
CFFh
D7Fh
DFFh
E7Fh
EFFh
F7Fh
FFFh
CFFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
PIC16F/LF1946/47
TABLE 3-7:
PIC16F/LF1946/47 MEMORY
MAP, BANK 15
TABLE 3-8:
PIC16F/LF1946/47 MEMORY
MAP, BANK 31
Bank 15
Bank 31
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
—
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
ICDIO(2)
ICDCON0(2)
ICDCON1(2)
ICDCON2(2)
—
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
ICDSTAT(2)
—
—
—
—
LCDSE0
LCDSE1
LCDSE2
—
DEVSEL(2)
F95h
F96h
F97h
F98h
F99h
F9Ah
ICDINSTL(2)
ICDINSTH(2)
ICDCC0(2)
—
—
ICDCC1(2)
—
ICDCC2(2)
—
79Fh
7A0h
7A1h
7A2h
7A3h
7A4h
7A5h
7A6h
7A7h
7A8h
7A9h
7AAh
7ABh
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
FA1h
FA2h
FA3h
FA4h
FA5h
FA6h
FA7h
FA8h
FA9h
ICDCC3(2)
LCDDATA0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
—
ICDBK0CON(2)
ICDBK0L(2)
ICDBK0H(2)
ICDBK0D(2)
ICDBK0CNT(2)
ICDBK1CON(2)
ICDBK1L(2)
ICDBK1H(2)
ICDBK1D(2)
ICDBK1CNT(2)
ICDBK2CON(2)
ICDBK2L(2)
ICDBK2H(2)
ICDBK2D(2)
ICDBK2CNT(2)
7ACh
7ADh
7AEh
7AFh
7B0h
7B1h
7B2h
7B3h
7B4h
7B5h
7B6h
7B7h
7B8h
—
—
—
—
—
—
—
—
—
—
—
FAAh
FABh
—
FDFh
FC0h
—
FDFh
FE0h
FE1h
FE2h
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
—
—
—
Unimplemented
Read as ‘0’
BSR_ICDSHAD(2)
STATUS_SHAD
7EFh
Legend:
= Unimplemented data memory locations,
read as ‘0’.
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
TOSH
Legend:
= Unimplemented data memory locations,
read as ‘0’.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 29
PIC16F/LF1946/47
3.2.6
SPECIAL FUNCTION REGISTERS
SUMMARY
The Special Function Register Summary for the device
family are as follows:
Device
Bank(s)
Page No.
0
31
32
33
34
35
36
37
38
39
41
42
44
45
1
2
3
4
5
PIC16F/LF1946/47
6
7
8
9-14
15
16-30
31
DS41414A-page 30
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
000h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
001h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
002h(2)
003h(2)
004h(2)
005h(2)
006h(2)
007h(2)
008h(2)
009h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx xxxx uuuu
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
00Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
00Bh(2)
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
INTCON
PORTA
PORTB
PORTC
PORTD
PORTE
PIR1
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
PORTE Data Latch when written: PORTE pins when read
TMR1GIF
OSFIF
—
ADIF
C2IF
RCIF
C1IF
TXIF
EEIF
SSPIF
BCLIF
TMR6IF
—
CCP1IF
LCDIF
—
TMR2IF
C3IF
TMR1IF 0000 0000 0000 0000
CCP2IF 0000 0000 0000 0000
PIR2
PIR3
CCP5IF
—
CCP4IF
RC2IF
CCP3IF
TX2IF
TMR4IF
BCL2IF
—
-000 0-0- -000 0-0-
PIR4
—
—
SSP2IF --00 --00 --00 --00
xxxx xxxx uuuu uuuu
TMR0
Timer0 Module Register
TMR1L
TMR1H
T1CON
T1GCON
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1CS<1:0>
TMR1GE T1GPOL
T1CKPS<1:0>
T1GTM T1GSPM
T1OSCEN T1SYNC
—
TMR1ON 0000 00-0 uuuu uu-u
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
0000 0x00 uuuu uxuu
01Ah
TMR2
Timer 2 Module Register
Timer 2 Period Register
—
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
01Bh
01Ch
01Dh
01Eh
01Fh
PR2
T2CON
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
Unimplemented
—
—
CPSCON0
CPSCON1
CPSON
—
CPSRM
—
—
—
—
CPSRNG1 CPSRNG0 CPSOUT T0XCS 00-- 0000 00-- 0000
CPSCH<4:0> ---0 0000 ---0 0000
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 31
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
080h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
081h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
082h(2)
083h(2)
084h(2)
085h(2)
086h(2)
087h(2)
088h(2)
089h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
08Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
08Bh(2)
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
Legend:
INTCON
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
TRISE7
TMR1GIE
OSFIE
—
TRISE6
ADIE
C2IE
TRISE5
RCIE
C1IE
TRISE4
TXIE
TRISE3
SSPIE
TRISE2
CCP1IE
LCDIE
—
TRISE1
TMR2IE
C3IE
TRISE0 1111 1111 1111 1111
TMR1IE 0000 0000 0000 0000
CCP2IE 0000 0000 0000 0000
PIE2
EEIE
BCLIE
PIE3
CCP5IE
—
CCP4IE
RC2IE
T0CS
—
CCP3IE
TX2IE
T0SE
—
TMR6IE
—
TMR4IE
BCL2IE
PS<2:0>
POR
—
-000 0-0- -000 0-0-
PIE4
—
—
SSP2IE --00 --00 --00 --00
OPTION_REG WPUEN
INTEDG
STKUNF
—
PSA
1111 1111 1111 1111
PCON
STKOVF
—
RMCLR
WDTPS<4:0>
RI
BOR
00-- 11qq qq-- qquu
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
SWDTEN --01 0110 --01 0110
—
—
TUN<5:0>
--00 0000 --00 0000
SPLLEN
T1OSCR
IRCF<3:0>
—
SCS<1:0>
0011 1-00 0011 1-00
HFIOFS 00q0 0q0- qqqq qq0-
xxxx xxxx uuuu uuuu
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
A/D Result Register Low
A/D Result Register High
—
xxxx xxxx uuuu uuuu
CHS<4:0>
GO/DONE
ADON
-000 0000 -000 0000
ADFM
ADCS<2:0>
—
ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000
Unimplemented
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
DS41414A-page 32
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
100h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
101h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
102h(2)
103h(2)
104h(2)
105h(2)
106h(2)
107h(2)
108h(2)
109h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
10Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
10Bh(2)
10Ch
10Dh
10Eh
10Fh
110h
111h
INTCON
LATA
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PORTA Data Latch
PORTB Data Latch
PORTC Data Latch
PORTD Data Latch
PORTE Data Latch
LATB
LATC
LATD
LATE
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
C1ON
C1INTP
C2ON
C2INTP
—
C1OUT
C1OE
C1PCH1
C2OE
C2PCH1
—
C1POL
C1PCH0
C2POL
C2PCH0
—
—
—
—
—
—
—
C1SP
—
C1HYS C1SYNC 0000 -100 0000 -100
C1NCH<1:0> 0000 --00 0000 --00
C2HYS C2SYNC 0000 -100 0000 -100
C2NCH<1:0> 0000 --00 0000 --00
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
Legend:
C1INTN
C2OUT
C2INTN
—
C2SP
—
MC3OUT MC2OUT MC1OUT ---- -000 ---- -000
BORRDY 1--- ---q u--- ---u
ADFVR<1:0> 0q00 0000 0q00 0000
SBOREN
FVREN
DACEN
—
—
—
—
—
—
FVRRDY
DACLPS
—
Reserved
DACOE
—
Reserved CDAFVR1 CDAFVR0
—
DACPSS<1:0>
DACR<4:0>
SRNQEN
—
DACNSS 000- 00-0 000- 00-0
---0 0000 ---0 0000
SRLEN
SRSPE
SRCLK2
SRSCKE
SRCLK1
SRSC2E
SRCLK0
SRSC1E
SRQEN
SRRPE
SRPS
SRPR
0000 0000 0000 0000
SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
Unimplemented
—
—
APFCON
CM3CON0
CM3CON1
P3CSEL
C3ON
P3BSEL
P2DSEL
C3OE
P2CSEL
C3POL
P2BSEL
CCP2SEL P1CSEL P1BSEL 0000 0000 0000 0000
C3OUT
C3INTN
—
—
C3SP
—
C3HYS C3SYNC 0000 -100 0000 -100
C3NCH<1:0> 0000 --00 0000 --00
C3INTP
C3PCH1
C3PCH0
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 33
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 3
180h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
181h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
182h(2)
183h(2)
184h(2)
185h(2)
186h(2)
187h(2)
188h(2)
189h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
18Ah(1, 2) PCLATH
—
GIE
—
Write Buffer for the upper 7 bits of the Program Counter
18Bh(2)
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
Legend:
INTCON
ANSELA
—
PEIE
—
TMR0IE
ANSA5
INTE
—
IOCIE
TMR0IF
ANSA2
INTF
IOCIF
ANSA3
ANSA1
ANSA0 --1- 1111 --1- 1111
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
ANSELE
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
—
—
—
—
ANSE2
ANSE1
ANSE0 ---- -111 ---- -111
0000 0000 0000 0000
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
EEPROM / Program Memory Address Register Low Byte
EEPROM / Program Memory Address Register High Byte
EEPROM / Program Memory Read Data Register Low Byte
—
—
—
EEPROM / Program Memory Read Data Register High Byte
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
0000 x000 0000 q000
0000 0000 0000 0000
EEPROM control register 2
Unimplemented
—
—
—
—
—
Unimplemented
RCREG
TXREG
SP1BRGL
SP1BRGH
RCSTA
TXSTA
BAUD1CON
USART Receive Data Register
USART Transmit Data Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000x
0000 0010 0000 0010
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
SPEN
CSRC
RX9
TX9
SREN
TXEN
—
CREN
SYNC
SCKP
ADDEN
SENDB
BRG16
FERR
BRGH
—
OERR
TRMT
WUE
RX9D
TX9D
ABDOVF
RCIDL
ABDEN 01-0 0-00 01-0 0-00
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
DS41414A-page 34
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 4
200h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
201h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
202h(2)
203h(2)
204h(2)
205h(2)
206h(2)
207h(2)
208h(2)
209h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
20Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
20Bh(2)
20Ch
20Dh
20Eh
20Fh
210h
211h
INTCON
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
Unimplemented
—
—
WPUB
—
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0 1111 1111 1111 1111
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
SSP1BUF
SSP1ADD
SSP1MSK
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
Synchronous Serial Port Receive Buffer/Transmit Register
212h
213h
ADD<7:0>
MSK<7:0>
214h
215h
216h
217h
218h
219h
21Ah
21Bh
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
—
SMP
WCOL
GCEN
ACKTIM
CKE
SSPOV
ACKSTAT
PCIE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
SSPEN
ACKDT
SCIE
CKP
SSPM<3:0>
ACKEN
BOEN
RCEN
PEN
RSEN
AHEN
SEN
SDAHT
SBCDE
DHEN
Unimplemented
—
—
SSP2BUF
SSP2ADD
SSP2MSK
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
Synchronous Serial Port Receive Buffer/Transmit Register
ADD<7:0>
MSK<7:0>
21Ch
SSP2STAT
SSP2CON1
SSP2CON2
SSP2CON3
SMP
WCOL
GCEN
ACKTIM
CKE
SSPOV
ACKSTAT
PCIE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
21Dh
SSPEN
ACKDT
SCIE
CKP
SSPM<3:0>
21Eh
ACKEN
BOEN
RCEN
PEN
RSEN
AHEN
SEN
21Fh
SDAHT
SBCDE
DHEN
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 35
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 5
280h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
281h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
282h(2)
283h(2)
284h(2)
285h(2)
286h(2)
287h(2)
288h(2)
289h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
28Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE
28Bh(2)
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
Legend:
INTCON
PORTF
GIE
TMR0IF
INTF
RG1
IOCIF
RG0
PORTF Data Latch when written: PORTF pins when read
PORTG
—
—
—
RG5
RG4
RG3
RG2
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
P1M<1:0>
P1RSEN
DC1B<1:0>
CCP1M<3:0>
P1DC<6:0>
STR1D
CCP1ASE
—
CCP1AS<2:0>
—
PSS1AC<1:0>
PSS1BD<1:0>
STR1B STR1A ---0 0001 ---0 0001
—
STR1SYNC
STR1C
Unimplemented
—
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
CCPTMRS1
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
P2M<1:0>
P2RSEN
DC2B<1:0>
CCP2M<3:0>
P2DC<6:0>
CCP2ASE
—
CCP2AS<2:0>
PSS2AC<1:0>
STR2D STR2C
C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
C5TSEL<1:0> ---- --00 ---- --00
PSS2BD<1:0>
—
—
C3TSEL1
—
STR2SYNC
C3TSEL0
—
STR2B
STR2A ---0 0001 ---0 0001
C4TSEL1 C4TSEL0
—
—
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
DS41414A-page 36
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 6
300h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
301h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
302h(2)
303h(2)
304h(2)
305h(2)
306h(2)
307h(2)
308h(2)
309h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
1111 1111 1111 1111
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
30Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
30Bh(2)
30Ch
30Dh
30Eh
30Fh
310h
311h
INTCON
TRISF
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PORTF Data Direction Register
TRISG
—
—
—
TRISG5
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0 --11 1111 --11 1111
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
—
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
Legend:
P3M<1:0>
P3RSEN
DC3B<1:0>
CCP3M<1:0>
0000 0000 0000 0000
P3DC<6:0>
0000 0000 0000 0000
CCP3ASE
—
CCP3AS<2:0>
STR3SYNC
PSS3AC<1:0>
PSS3BD<1:0>
0000 0000 0000 0000
—
—
STR3D
STR3C
STR3B
STR3A ---0 0001 ---0 0001
Unimplemented
—
—
CCPR4L
CCPR4H
CCP4CON
—
Capture/Compare/PWM Register 4 (LSB)
Capture/Compare/PWM Register 4 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
—
—
DC4B<1:0>
CCP4M<3:0>
Unimplemented
—
—
CCPR5L
CCPR5H
CCP5CON
—
Capture/Compare/PWM Register 5 (LSB)
Capture/Compare/PWM Register 5 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
—
—
DC5B<1:0>
CCP5M<3:0>
Unimplemented
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 37
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 7
380h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
381h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
382h(2)
383h(2)
384h(2)
385h(2)
386h(2)
387h(2)
388h(2)
389h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
38Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
38Bh(2)
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
Legend:
INTCON
LATF
LATG
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PORTF Data Latch
—
—
LATG5
LATG4
LATG3
LATG2
LATG1
LATG0 --xx xxxx --uu uuuu
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
IOCBP7
IOCBN7
IOCBF7
IOCBP6
IOCBN6
IOCBF6
IOCBP5
IOCBN5
IOCBF5
IOCBP4
IOCBN4
IOCBF4
IOCBP3
IOCBN3
IOCBF3
IOCBP2
IOCBN2
IOCBF2
IOCBP1
IOCBP0 0000 0000 0000 0000
IOCBN1 IOCBN0 0000 0000 0000 0000
IOCBF1 IOCBF0 0000 0000 0000 0000
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
DS41414A-page 38
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 8
400h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
401h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
402h(2)
403h(2)
404h(2)
405h(2)
406h(2)
407h(2)
408h(2)
409h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
40Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
40Bh(2)
40Ch
40Dh
40Eh
40Fh
410h
411h
INTCON
ANSELF
ANSELG
—
GIE
INTF
IOCIF
ANSELF7 ANSELF6 ANSELF5 ANSELF4 ANSELF3 ANSELF2 ANSELF1 ANSELF0 1111 1111 1111 1111
—
—
—
ANSELG4 ANSELG3 ANSELG2 ANSELG1
—
---1 111- ---1 111-
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
Legend:
—
—
—
TMR4
PR4
T4CON
—
Timer 4 Module Register
Timer 4 Period Register
—
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer 6 Module Register
Timer 6 Period Register
—
—
—
—
—
—
—
—
—
—
—
—
TMR6
PR6
T6CON
—
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
Unimplemented
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 39
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 9
480h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
481h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
482h(2)
483h(2)
404h(2)
485h(2)
486h(2)
487h(2)
488h(2)
489h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
48Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
48Bh(2)
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
Legend:
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
—
IOCIF
—
—
Unimplemented
—
—
—
WPUG
—
WPUG5
—
—
—
--1- ---- --1- ----
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
RC2REG
USART Receive Data Register
USART Transmit Data Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000x
0000 0010 0000 0010
TX2REG
SP2BRGL
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
SP2BRGH
RC2STA
SPEN
CSRC
RX9
TX9
SREN
TXEN
—
CREN
SYNC
SCKP
ADDEN
SENDB
BRG16
FERR
BRGH
—
OERR
TRMT
WUE
RX9D
TX9D
TX2STA
BAUDCON2
ABDOVF
RCIDL
ABDEN 01-0 0-00 01-0 0-00
—
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
DS41414A-page 40
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Banks 10-14
x00h/
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
x80h(2)
x00h/
INDF1
PCL
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
x81h(2)
x02h/
Program Counter (PC) Least Significant Byte
x82h(2)
x03h/
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
x83h(2)
x04h/
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
x84h(2)
x05h/
x85h(2)
x06h/
x86h(2)
x07h/
x87h(2)
x08h/
—
—
—
BSR<4:0>
x88h(2)
x09h/
WREG
PCLATH
INTCON
—
Working Register
x89h(2)
x0Ah/
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
x8Ah(1),(2)
x0Bh/
GIE
INTF
IOCIF
x8Bh(2)
x0Ch/
x8Ch
—
Unimplemented
—
—
x1Fh/
x9Fh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 41
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 15
780h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
781h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
782h(2)
783h(2)
784h(2)
785h(2)
786h(2)
787h(2)
788h(2)
789h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
78Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
78Bh(2)
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
INTCON
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
—
LCDEN
WFT
SLPEN
WERR
LCDA
LCDIRI
—
—
WA
—
CS<1:0>
LMUX<1:0>
000- 0011 000- 0011
0000 0000 0000 0000
000- 000- 000- 000-
---- -000 ---- -000
0000 -000 0000 -000
BIASMD
LCDIRS
—
LP<3:0>
VLCD3PE VLCD2PE VLCD1PE
LCDIRE
—
—
—
—
—
LCDCST<2:0>
LRLAT<2:0>
LRLAP<1:0>
LRLBP<1:0>
Unimplemented
Unimplemented
—
—
—
—
—
LCDSE0
LCDSE1
LCDSE2
LCDSE3
LCDSE4
LCDSE5
—
SE<7:0>
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
--00 0000 --uu uuuu
SE<15:8>
SE<23:16>
SE<31:24>
SE<39:32>
—
—
SE<45:40>
Unimplemented
Unimplemented
—
—
—
—
—
LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
xxxx xxxx uuuu uuuu
7A1h
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
xxxx xxxx uuuu uuuu
7A2h
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16 xxxx xxxx uuuu uuuu
COM0
7A3h
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
7A4h
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
7A5h
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16 xxxx xxxx uuuu uuuu
COM1
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
DS41414A-page 42
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 15 (Continued)
7A6h
7A7h
7A8h
7A9h
7AAh
7ABh
7ABh
7ABh
7ABh
7ABh
7ABh
7ABh
7ABh
7ABh
7ABh
7ABh
7ABh
7ABh
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
LCDDATA12
LCDDATA13
LCDDATA14
LCDDATA15
LCDDATA16
LCDDATA17
LCDDATA18
LCDDATA19
LCDDATA20
LCDDATA21
LCDDATA22
LCDDATA23
—
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16 xxxx xxxx uuuu uuuu
COM2
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16 xxxx xxxx uuuu uuuu
COM3
SEG31
COM0
SEG30
COM0
SEG29
COM0
SEG28
COM0
SEG27
COM0
SEG26
COM0
SEG25
COM0
SEG24 xxxx xxxx uuuu uuuu
COM0
SEG39
COM0
SEG38
COM0
SEG37
COM0
SEG36
COM0
SEG35
COM0
SEG34
COM0
SEG33
COM0
SEG32 xxxx xxxx uuuu uuuu
COM0
—
—
SEG45
COM0
SEG44
COM0
SEG43
COM0
SEG42
COM0
SEG41
COM0
SEG40 --xx xxxx --uu uuuu
COM0
SEG31
COM1
SEG30
COM1
SEG29
COM1
SEG28
COM1
SEG27
COM1
SEG26
COM1
SEG25
COM1
SEG24 xxxx xxxx uuuu uuuu
COM1
SEG39
COM1
SEG38
COM1
SEG37
COM1
SEG36
COM1
SEG35
COM1
SEG34
COM1
SEG33
COM1
SEG32 xxxx xxxx uuuu uuuu
COM1
—
—
SEG45
COM1
SEG44
COM1
SEG43
COM1
SEG42
COM1
SEG41
COM1
SEG40 --xx xxxx --uu uuuu
COM1
SEG31
COM2
SEG30
COM2
SEG29
COM2
SEG28
COM2
SEG27
COM2
SEG26
COM2
SEG25
COM2
SEG24 xxxx xxxx uuuu uuuu
COM2
SEG39
COM2
SEG38
COM2
SEG37
COM2
SEG36
COM2
SEG35
COM2
SEG34
COM2
SEG33
COM2
SEG32 xxxx xxxx uuuu uuuu
COM2
—
—
SEG45
COM2
SEG44
COM2
SEG43
COM2
SEG42
COM2
SEG41
COM2
SEG40 --xx xxxx --uu uuuu
COM2
SEG31
COM3
SEG30
COM3
SEG29
COM3
SEG28
COM3
SEG27
COM3
SEG26
COM3
SEG25
COM3
SEG24 xxxx xxxx uuuu uuuu
COM3
SEG39
COM3
SEG38
COM3
SEG37
COM3
SEG36
COM3
SEG35
COM3
SEG34
COM3
SEG33
COM3
SEG32 xxxx xxxx uuuu uuuu
COM3
—
—
SEG45
COM3
SEG44
COM3
SEG43
COM3
SEG42
COM3
SEG41
COM3
SEG40 --xx xxxx --uu uuuu
COM3
7ACh
—
Unimplemented
—
—
7EFh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
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PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Banks 16-30
x00h/
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
x80h(2)
x00h/
INDF1
PCL
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
x81h(2)
x02h/
Program Counter (PC) Least Significant Byte
x82h(2)
x03h/
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
x83h(2)
x04h/
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
x84h(2)
x05h/
x85h(2)
x06h/
x86h(2)
x07h/
x87h(2)
x08h/
—
—
—
BSR<4:0>
x88h(2)
x09h/
WREG
PCLATH
INTCON
—
Working Register
x89h(2)
x0Ah/
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
x8Ah(1),(2)
x0Bh/
GIE
INTF
IOCIF
x8Bh(2)
x0Ch/
x8Ch
—
Unimplemented
—
—
x1Fh/
x9Fh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
DS41414A-page 44
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 3-9:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 31
F80h(2)
INDF0
INDF1
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
F81h(2)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
F82h(2)
F83h(2)
F84h(2)
F85h(2)
F86h(2)
F87h(2)
F88h(2)
F89h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
WREG
Working Register
F8Ah(1),(2 PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
)
F8Bh(2)
INTCON
—
GIE
PEIE TMR0IE INTE IOCIE TMR0IF
INTF
DC
IOCIF
C
0000 000x 0000 000u
F8Ch
—
FE3h
Unimplemented
—
—
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
STATUS_
Z
---- -xxx ---- -uuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
-xxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SHAD
WREG_
SHAD
BSR_
Working Register Normal (Non-ICD) Shadow
Bank Select Register Normal (Non-ICD) Shadow
Program Counter Latch High Register Normal (Non-ICD) Shadow
Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow
Unimplemented
SHAD
PCLATH_
SHAD
FSR0L_
SHAD
FSR0H_
SHAD
FSR1L_
SHAD
FSR1H_
SHAD
FECh
FEDh
FEEh
—
—
—
—
—
—
Current Stack pointer
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
-xxx xxxx -uuu uuuu
STKPTR
TOSL
Top of Stack Low byte
Top of Stack High byte
FEFh
—
TOSH
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
2010 Microchip Technology Inc.
Preliminary
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PIC16F/LF1946/47
3.3.3
COMPUTED FUNCTION CALLS
3.3
PCL and PCLATH
A computed function CALLallows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.
If using the CALLinstruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
FIGURE 3-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
The CALLWinstruction enables computed calls by com-
bining PCLATH and W to form the destination address.
A computed CALLWis accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
14
0
Instruction with
PCL as
Destination
PCH
PCL
PC
8
7
6
0
ALU Result
PCLATH
14
0
PCH
PCL
3.3.4
BRANCHING
GOTO, CALL
PC
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
4
11
6
0
0
PCLATH
OPCODE <10:0>
14
0
PCH
PCL
CALLW
PC
7
8
6
W
PCLATH
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
14
0
0
PCH
PCH
PCL
BRW
PC
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRAinstruction.
15
PC + W
14
PCL
BRA
PC
15
PC + OPCODE <8:0>
3.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program Coun-
ter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values con-
tained in the PCLATH register and those being written
to the PCL register.
3.3.2
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTOmethod, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the Application
Note AN556, “Implementing a Table Read” (DS00556).
DS41414A-page 46
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
3.4.1
ACCESSING THE STACK
3.4
Stack
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-3 and 3-3). The stack space is
not part of either program or data space. The PC is
PUSHed onto the stack when CALLor CALLWinstruc-
tions are executed or an interrupt causes a branch. The
stack is POPed in the event of a RETURN, RETLWor a
RETFIEinstruction execution. PCLATH is not affected
by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit = 0 (Configuration Word 2). This means that after
the stack has been PUSHed sixteen times, the seven-
teenth PUSH overwrites the value that was stored from
the first PUSH. The eighteenth PUSH overwrites the
second PUSH (and so on). The STKOVF and STKUNF
flag bits will be set on an Overflow/Underflow, regard-
less of whether the Reset is enabled.
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLWand
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIEwill decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement the STK-
PTR.
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
Reference Figure through Figure for examples of
accessing the stack.
FIGURE 3-5:
ACCESSING THE STACK EXAMPLE 1
Stack Reset Disabled
STKPTR = 0x1F
TOSH:TOSL
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x1F
(STVREN = 0)
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
Stack Reset Enabled
STKPTR = 0x1F
TOSH:TOSL
0x0000
(STVREN = 1)
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
FIGURE 3-6:
ACCESSING THE STACK EXAMPLE 2
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
This figure shows the stack configuration
after the first CALLor a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
TOSH:TOSL
Return Address
STKPTR = 0x00
FIGURE 3-7:
ACCESSING THE STACK EXAMPLE 3
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURNinstructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
STKPTR = 0x06
TOSH:TOSL
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
DS41414A-page 48
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 3-8:
ACCESSING THE STACK EXAMPLE 4
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
When the stack is full, the next CALLor
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
TOSH:TOSL
STKPTR = 0x10
3.4.2
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Word 2 is set to ‘1’,
the device will be reset if the stack is PUSHed beyond
the sixteenth level or POPed beyond the first level,
setting the appropriate bits (STKOVF or STKUNF,
respectively) in the PCON register.
3.5
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
FIGURE 3-9:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
0x1FFF
0x2000
Reserved
Linear
Data Memory
0x29AF
0x29B0
Reserved
0x0000
FSR
Address
Range
0x7FFF
0x8000
Program
Flash Memory
0xFFFF
0x7FFF
Note:
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS41414A-page 50
Preliminary
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3.5.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-10:
TRADITIONAL DATA MEMORY MAP
Direct Addressing
From Opcode
Indirect Addressing
4
BSR
6
7
FSRxH
0
7
FSRxL
0
0
0
0
0
0
0
Location Select
Bank Select
Bank Select
Location Select
0000 0001 0010
1111
0x00
0x7F
Bank 0 Bank 1 Bank 2
Bank 31
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3.5.2
LINEAR DATA MEMORY
3.5.3
PROGRAM FLASH MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-12:
PROGRAM FLASH
MEMORY MAP
FIGURE 3-11:
LINEAR DATA MEMORY
MAP
7
7
0
0
FSRnH
FSRnL
7
1
7
0
0
FSRnH
FSRnL
0
0 1
Location Select
0x8000
0x0000
Location Select
0x2000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x7FFF
0xFFFF
0xF6F
0x29AF
DS41414A-page 52
Preliminary
2010 Microchip Technology Inc.
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4.0
DEVICE CONFIGURATION
Device Configuration consists of Configuration Word 1
and Configuration Word 2 registers, Code Protection
and Device ID.
4.1
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1
register at 8007h and Configuration Word 2 register at
8008h.
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
REGISTER 4-1:
CONFIGURATION WORD 1
R/P-1/1
FCMEN
bit 13
R/P-1/1
IESO
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
CPD
R/P-1/1
CP
CLKOUTEN
BOREN1
BOREN0
bit 7
bit 0
R/P-1/1
MCLRE
bit 6
R/P-1/1
PWRTE
R/P-1/1
WDTE1
R/P-1/1
WDTE0
R/P-1/1
FOSC2
R/P-1/1
FOSC1
R/P-1/1
FOSC0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
P = Programmable bit
bit 13
bit 12
bit 11
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor is enabled
0= Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1= Internal/External Switchover mode is enabled
0= Internal/External Switchover mode is disabled
CLKOUTEN: Clock Out Enable bit
1= CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT
0= CLKOUT function is enabled on RA6/CLKOUT
(1)
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
11= BOR enabled
10= BOR enabled during operation and disabled in Sleep
01= BOR controlled by SBOREN bit of the BORCON register
00= BOR disabled
(2)
bit 8
bit 7
bit 6
CPD: Data Code Protection bit
1= Data memory code protection is disabled
0= Data memory code protection is enabled
(3)
CP: Code Protection bit
1= Program memory code protection is disabled
0= Program memory code protection is enabled
MCLRE: RE3/MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1= RE3/MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0= RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3
bit.
(1)
bit 5
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11= WDT enabled
10= WDT enabled while running and disabled in Sleep
01= WDT controlled by the SWDTEN bit in the WDTCON register
00= WDT disabled
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
DS41414A-page 54
Preliminary
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REGISTER 4-1:
CONFIGURATION WORD 1 (CONTINUED)
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111= ECH: External Clock, High-Power mode: CLKIN on RA7/OSC1/CLKIN
110= ECM: External Clock, Medium-Power mode: CLKIN on RA7/OSC1/CLKIN
101= ECL: External Clock, Low-Power mode: CLKIN on RA7/OSC1/CLKIN
100= INTOSC oscillator: I/O function on RA7/OSC1/CLKIN
011= EXTRC oscillator: RC function on RA7/OSC1/CLKIN
010= HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
001= XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
000= LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
REGISTER 4-2:
CONFIGURATION WORD 2
R/P-1/1
LVP
R/P-1/1
DEBUG
U-1
—
R/P-1/1
BORV
R/P-1/1
R/P-1/1
PLLEN
U-1
—
STVREN
bit 13
bit 7
bit 0
U-1
—
U-1
—
R/P-1/1
U-1
—
U-1
—
R/P-1/1
WRT1
R/P-1/1
WRT0
VCAPEN
bit 6
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
P = Programmable bit
(1)
bit 13
bit 12
LVP: Low-Voltage Programming Enable bit
1= Low-voltage programming enabled
0= High-voltage on MCLR/VPP must be used for programming
DEBUG: In-Circuit Debugger Mode bit
1= In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0= In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
bit 11
bit 10
Unimplemented: Read as ‘1’
BORV: Brown-out Reset Voltage Selection bit
1= Brown-out Reset voltage set to 1.9V
0= Brown-out Reset voltage set to 2.5V
bit 9
bit 8
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Stack Overflow or Underflow will cause a Reset
0= Stack Overflow or Underflow will not cause a Reset
PLLEN: PLL Enable bit
1= 4xPLL enabled
0= 4xPLL disabled
bit 7-5
bit 4
Unimplemented: Read as ‘1’
VCAPEN>: Voltage Regulator Capacitor Enable bits
0= VCAP functionality is enabled on RF0
1= No capacitor on VCAP pin
bit 2-3
bit 1-0
Unimplemented: Read as ‘1’
WRT<1:0>: Flash Memory Self-Write Protection bits
8 kW Flash memory (PIC16F/LF1946 only):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to 1FFFh may be modified by EECON control
01= 000h to FFFh write-protected, 1000h to 1FFFh may be modified by EECON control
00= 000h to 1FFFh write-protected, no addresses may be modified by EECON control
16 kW Flash memory (PIC16F/LF1947):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to 3FFFh may be modified by EECON control
01= 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by EECON control
00= 000h to 3FFFh write-protected, no addresses may be modified by EECON control
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
DS41414A-page 56
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
4.2
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data EEPROM protection are controlled independently.
Internal access to the program memory and data
EEPROM are unaffected by any code protection
setting.
4.2.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Word 1. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 4.3
“Write
Protection” for more information.
4.2.2
DATA EEPROM PROTECTION
The entire data EEPROM is protected from external
reads and writes by the CPD bit. When CPD = 0,
external reads and writes of data EEPROM are
inhibited. The CPU can continue to read and write data
EEPROM regardless of the protection bit settings.
4.3
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Word 2 define the
size of the program memory block that is protected.
4.4
User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 4.5 “Device ID and Revision ID” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC16F193X/LF193X/PIC16F194X/LF194X Memory
Programming Specification” (DS41397).
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 57
PIC16F/LF1946/47
4.5
Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
REGISTER 4-3:
DEVICEID: DEVICE ID REGISTER(1)
R
DEV8
R
R
R
R
R
R
DEV7
DEV6
DEV5
DEV4
DEV3
DEV2
bit 13
bit 7
bit 0
R
DEV1
R
R
R
R
R
R
DEV0
REV4
REV3
REV2
REV1
REV0
bit 6
Legend:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
x = Bit is unknown
bit 13-5
bit 4-0
DEV<8:0>: Device ID bits
100011001= PIC16F1946
100011010= PIC16F1947
100011011= PIC16LF1946
100011100= PIC16LF1947
REV<4:0>: Revision ID bits
These bits are used to identify the revision.
Note 1: This location cannot be written.
DS41414A-page 58
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
The oscillator module can be configured in one of six
clock modes.
5.0
5.1
OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
1. EC – External clock (ECL, ECM, ECH. See
Section 5.2.1.1 “EC Mode”).
Overview
2. LP – 32 kHz Low-Power Crystal mode.
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
3. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
4. HS – High Gain Crystal or Ceramic Resonator
mode.
5. RC – External Resistor-Capacitor (RC).
6. INTOSC – Internal oscillator.
Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds
selectable via software. Additional clock features
include:
Clock Source modes are selected by the FOSC<2:0>
bits in the Configuration Word 1. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
The EC clock mode relies on an external logic level
signal as the device clock source. The LP, XT, and HS
clock modes require an external crystal or resonator to
be connected to the device. Each mode is optimized for
a different frequency range. The RC clock mode
requires an external resistor and capacitor to set the
oscillator frequency.
• Selectable system clock source between external
or internal sources via software.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
The INTOSC internal oscillator block produces low,
medium, and high frequency clock sources, designated
LFINTOSC, MFINTOSC and HFINTOSC. (see Internal
Oscillator Block, Figure 5-1). A wide selection of device
clock frequencies may be derived from these three
clock sources.
automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources
FIGURE 5-1:
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
External
Oscillator
LP, XT, HS, RC, EC
OSC2
Sleep
4 x PLL
Sleep
OSC1
Timer1
CPU and
Oscillator
T1OSC
FOSC<2:0> = 100
T1OSO
Peripherals
T1OSCEN
Enable
Oscillator
IRCF<3:0>
T1OSI
Internal Oscillator
16 MHz
8 MHz
Internal
Oscillator
Block
4 MHz
2 MHz
Clock
1 MHz
Control
HFPLL
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
16 MHz
(HFINTOSC)
FOSC<2:0> SCS<1:0>
500 kHz
Source
500 kHz
(MFINTOSC)
Clock Source Option
for other modules
31 kHz
Source
31 kHz
31 kHz (LFINTOSC)
WDT, PWRT, Fail-Safe Clock Monitor
Two-Speed Start-up and other modules
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 59
PIC16F/LF1946/47
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
5.2
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator mod-
ules (EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resis-
tor-Capacitor (RC) mode circuits.
Internal clock sources are contained internally within
the oscillator module. The internal oscillator block has
FIGURE 5-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
two
internal
oscillators
and
a
dedicated
phase-locked-loop (HFPLL) that are used to generate
three internal system clock sources: the 16 MHz
High-Frequency Internal Oscillator (HFINTOSC), 500
kHZ (MFINTOSC) and the 31 kHz Low-Frequency
Internal Oscillator (LFINTOSC).
OSC1/CLKIN
PIC® MCU
Clock from
Ext. System
OSC2/CLKOUT
(1)
FOSC/4 or
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3
“Clock Switching” for additional information.
I/O
Note 1: Output depends upon CLKOUTEN bit of the
Configuration Word 1.
5.2.1
EXTERNAL CLOCK SOURCES
5.2.1.2
LP, XT, HS Modes
An external clock source can be used as the device
system clock by performing one of the following
actions:
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
• Program the FOSC<2:0> bits in the Configuration
Word 1 to select an external clock source that will
be used as the default system clock upon a
device Reset.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- Timer1 Oscillator during run-time, or
- An external clock source determined by the
value of the FOSC bits.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
See Section 5.3 “Clock Switching”for more informa-
tion.
5.2.1.1
EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 5-3 and Figure 5-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
EC mode has 3 power modes to select from through
Configuration Word 1:
• High-power, 4-32 MHz (FOSC = 111)
• Medium power, 0.5-4 MHz (FOSC = 110)
• Low-power, 0-0.5 MHz (FOSC = 101)
DS41414A-page 60
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 5-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 5-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC® MCU
PIC® MCU
OSC1/CLKIN
OSC1/CLKIN
C1
C1
To Internal
Logic
To Internal
Logic
Quartz
Crystal
(2)
Sleep
RF
(3)
(2)
RP
RF
Sleep
OSC2/CLKOUT
(1)
C2
RS
OSC2/CLKOUT
(1)
C2
RS
Ceramic
Resonator
Note 1: A series resistor (RS) may be required for
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
5.2.1.3
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.4
“Two-Speed Clock Start-up Mode”).
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
5.2.1.4
4X PLL
The oscillator module contains a 4X PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4X PLL must fall within specifications. See the PLL
Clock Timing Specifications in Section 29.0
“Electrical Specifications”.
The 4X PLL may be enabled for use by one of two
methods:
1. Program the PLLEN bit in Configuration Word 2
to a ‘1’.
2. Write the SPLLEN bit in the OSCCON register to
a ‘1’. If the PLLEN bit in Configuration Word 2 is
programmed to a ‘1’, then the value of SPLLEN
is ignored.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 61
PIC16F/LF1946/47
5.2.1.5
TIMER1 Oscillator
5.2.1.6
External RC Mode
The Timer1 Oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is opti-
mized for timekeeping operations with a 32.768 kHz
crystal connected between the T1OSO and T1OSI
device pins.
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The Timer1 Oscillator can be used as an alternate sys-
tem clock source and can be selected during run-time
using clock switching. Refer to Section 5.3 “Clock
Switching” for more information.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
state of the CLKOUTEN bit in Configuration Word 1.
Figure 5-6 shows the external RC mode connections.
FIGURE 5-5:
QUARTZ CRYSTAL
OPERATION (TIMER1
OSCILLATOR)
FIGURE 5-6:
EXTERNAL RC MODES
VDD
PIC® MCU
PIC® MCU
REXT
OSC1/CLKIN
Internal
Clock
T1OSI
C1
To Internal
Logic
CEXT
VSS
32.768 kHz
Quartz
Crystal
OSC2/CLKOUT
(1)
FOSC/4 or I/O
T1OSO
C2
Recommended values: 10 k REXT 100 k, <3V
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
Note 1: Output depends upon CLKOUTEN bit of the
Configuration Word 1.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
The user also needs to take into account variation due
to tolerance of external RC components used.
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)
DS41414A-page 62
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
5.2.2
INTERNAL CLOCK SOURCES
5.2.2.1
HFINTOSC
The device may be configured to use the internal oscil-
lator block as the system clock by performing one of the
following actions:
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).
• Program the FOSC<2:0> bits in Configuration
Word 1 to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3
“Clock Switching”for more information.
The HFINTOSC is enabled by:
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<2:0> = 100, or
The function of the OSC2/CLKOUT pin is determined
by the state of the CLKOUTEN bit in Configuration
Word 1.
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
The High Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running and can be utilized.
The internal oscillator block has two independent
oscillators and a dedicated Phase-Locked Loop,
HFPLL that can produce one of three internal system
clock sources.
The High Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The HFINTOSC source is generated
from the 500 kHz MFINTOSC source and the
dedicated Phase-Locked Loop, HFPLL. The
frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 5-3).
The High Frequency Internal Oscillator Status Stable
bit (HFIOFS) of the OSCSTAT register indicates when
the HFINTOSC is running within 0.5% of its final value.
5.2.2.2
The
MFINTOSC
Medium-Frequency
Internal
Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 5-3).
2. The MFINTOSC (Medium-Frequency Internal
Oscillator) is factory calibrated and operates at
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 5-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.7 “Internal
Oscillator Clock Switch Timing” for more information.
3. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
The MFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running and can be utilized.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 63
PIC16F/LF1946/47
5.2.2.3
Internal Oscillator Frequency
Adjustment
5.2.2.5
Internal Oscillator Frequency
Selection
The 500 kHz internal oscillator is factory calibrated.
This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 5-3). Since
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator a change in
the OSCTUNE register value will apply to both.
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 5-1). The Internal Oscillator Frequency
Select bits IRCF<3:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
the following frequencies can be selected via software:
The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.
• 32 MHz (requires 4X PLL)
• 16 MHz
When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
• 8 MHz
• 4 MHz
• 2 MHz
• 1 MHz
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
• 500 kHz (Default after Reset)
• 250 kHz
• 125 kHz
• 62.5 kHz
• 31.25 kHz
• 31 kHz (LFINTOSC)
5.2.2.4
LFINTOSC
Note:
Following any Reset, the IRCF<3:0> bits of
the OSCCON register are set to ‘0111’ and
the frequency selection is set to 500 kHz.
The user can modify the IRCF bits to
select a different frequency.
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). Select 31 kHz, via
software, using the IRCF<3:0> bits of the OSCCON
register. See Section 5.2.2.7 “Internal Oscillator
Clock Switch Timing” for more information. The
LFINTOSC is also the frequency for the Power-up Timer
(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock
Monitor (FSCM).
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli-
cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi-
tion times can be obtained between frequency changes
that use the same oscillator source.
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000)as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
Peripherals that use the LFINTOSC are:
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The Low Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running and can be utilized.
DS41414A-page 64
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
5.2.2.6
32 MHz Internal Oscillator
Frequency Selection
5.2.2.7
Internal Oscillator Clock Switch
Timing
The Internal Oscillator Block can be used with the 4X
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz inter-
nal clock source:
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 5-7). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
• The FOSC bits in Configuration Word 1 must be
set to use the INTOSC source as the device sys-
tem clock (FOSC<2:0> = 100).
• The IRCF bits in the OSCCON register must be
set to the 8 MHz HFINTOSC selection
(IRCF<3:0> = 1110).
1. IRCF<3:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
• The SPLLEN bit in the OSCCON register must be
set to enable the 4xPLL, or the PLLEN bit of the
Configuration Word 2 must be programmed to a
‘1’.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
Note:
When using the PLLEN bit of the
Configuration Word 2, the 4xPLL cannot
be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
The 4xPLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4xPLL with the internal oscillator.
See Figure 5-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
Start-up delay specifications are located in the
oscillator tables of Section 29.0 “Electrical
Specifications”.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 65
PIC16F/LF1946/47
FIGURE 5-7:
INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/
MFINTOSC
LFINTOSC (FSCM and WDT disabled)
HFINTOSC/
MFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
0
0
IRCF <3:0>
System Clock
HFINTOSC/
MFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC/
MFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
0
0
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Running
LFINTOSC
Start-up Time 2-cycle Sync
HFINTOSC/
MFINTOSC
= 0
0
IRCF <3:0>
System Clock
DS41414A-page 66
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
5.3.3
TIMER1 OSCILLATOR
5.3
Clock Switching
The Timer1 Oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the T1OSO and T1OSI device
pins.
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
The Timer1 oscillator is enabled using the T1OSCEN
control bit in the T1CON register. See Section 20.0
“Timer1 Module with Gate Control” for more
information about the Timer1 peripheral.
• Default system oscillator determined by FOSC
bits in Configuration Word 1
• Timer1 32 kHz crystal oscillator
• Internal Oscillator Block (INTOSC)
5.3.4
TIMER1 OSCILLATOR READY
(T1OSCR) BIT
5.3.1
SYSTEM CLOCK SELECT (SCS)
BITS
The user must ensure that the Timer1 Oscillator is
ready to be used before it is selected as a system clock
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the OSCSTAT register indicates whether the Timer1
oscillator is ready to be used. After the T1OSCR bit is
set, the SCS bits can be configured to select the Timer1
oscillator.
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Word 1.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the SCS
bits of the OSCCON register. The user can
monitor the OSTS bit of the OSCSTAT
register to determine the current system
clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in Table 5-1.
5.3.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word 1, or from the internal clock source. In particular,
OSTS indicates that the Oscillator Start-up Timer
(OST) has timed out for LP, XT or HS modes. The OST
does not reflect the status of the Timer1 Oscillator.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 67
PIC16F/LF1946/47
5.4.1
TWO-SPEED START-UP MODE
CONFIGURATION
5.4
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Word 1) = 1; Inter-
nal/External Switchover bit (Two-Speed Start-up
mode enabled).
• SCS (of the OSCCON register) = 00.
• FOSC<2:0> bits in the Configuration Word 1
configured for LP, XT or HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
Two-Speed Start-up provides benefits when the oscil-
lator module is configured for LP, XT or HS modes.
The Oscillator Start-up Timer (OST) is enabled for
these modes and must count 1024 oscillations before
the oscillator can be used as the system clock source.
• Wake-up from Sleep.
If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT reg-
ister is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
TABLE 5-1:
Switch From
OSCILLATOR SWITCHING DELAYS
Switch To
Frequency
Oscillator Delay
LFINTOSC(1)
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Sleep/POR
Oscillator Warm-up Delay (TWARM)
Sleep/POR
LFINTOSC
EC, RC(1)
EC, RC(1)
DC – 32 MHz
DC – 32 MHz
2 cycles
1 cycle of each
Timer1 Oscillator
LP, XT, HS(1)
Sleep/POR
32 kHz-20 MHz
1024 Clock Cycles (OST)
MFINTOSC(1)
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Any clock source
2 s (approx.)
HFINTOSC(1)
Any clock source
Any clock source
PLL inactive
LFINTOSC(1)
Timer1 Oscillator
PLL active
31 kHz
1 cycle of each
32 kHz
1024 Clock Cycles (OST)
2 ms (approx.)
16-32 MHz
Note 1: PLL inactive.
DS41414A-page 68
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
5.4.2
TWO-SPEED START-UP
SEQUENCE
5.4.3
CHECKING TWO-SPEED CLOCK
STATUS
1. Wake-up from Power-on Reset or Sleep.
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word 1, or the
internal oscillator.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
FIGURE 5-8:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
0
1
1022 1023
OSC2
Program Counter
PC - N
PC + 1
PC
System Clock
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 69
PIC16F/LF1946/47
5.5.3
FAIL-SAFE CONDITION CLEARING
5.5
Fail-Safe Clock Monitor
The Fail-Safe condition is cleared after a Reset,
executing a SLEEPinstruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared and the device
will be operating from the external clock source. The
Fail-Safe condition must be cleared before the OSFIF
flag can be cleared.
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word 1. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, Timer1
Oscillator and RC).
FIGURE 5-9:
FSCM BLOCK DIAGRAM
5.5.4
RESET OR WAKE-UP FROM SLEEP
Clock Monitor
Latch
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
External
Clock
S
Q
LFINTOSC
Oscillator
÷ 64
R
Q
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.
Clock
Failure
Detected
5.5.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 5-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
5.5.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
DS41414A-page 70
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 5-10:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 71
PIC16F/LF1946/47
5.6
Oscillator Control Registers
REGISTER 5-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1
IRCF<3:0>
R/W-0/0
SPLLEN
bit 7
U-0
—
R/W-0/0
R/W-0/0
SCS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
SPLLEN: Software PLL Enable bit
If PLLEN in Configuration Word 1 = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Word 1 = 0:
1= 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
000x= 31 kHz LF
0010= 31.25 kHz MF
0011= 31.25 kHz HF(1)
0100= 62.5 kHz MF
0101= 125 kHz MF
0110= 250 kHz MF
0111= 500 kHz MF (default upon Reset)
1000= 125 kHz HF(1)
1001= 250 kHz HF(1)
1010= 500 kHz HF(1)
1011= 1 MHz HF
1100= 2 MHz HF
1101= 4 MHz HF
1110= 8 MHz or 32 MHz HF(see Section 5.2.1.4 “4X PLL”)
1111= 16 MHz HF
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x= Internal oscillator block
01= Timer1 oscillator
00= Clock determined by FOSC<2:0> in Configuration Word 1.
Note 1: Duplicate frequency derived from HFINTOSC.
DS41414A-page 72
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 5-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
R-1/q
T1OSCR
bit 7
R-0/q
PLLR
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Conditional
bit 7
T1OSCR: Timer1 Oscillator Ready bit
If T1OSCEN = 1:
1= Timer1 oscillator is ready
0= Timer1 oscillator is not ready
If T1OSCEN = 0:
1= Timer1 clock source is always ready
bit 6
bit 5
PLLR 4x PLL Ready bit
1= 4x PLL is ready
0= 4x PLL is not ready
OSTS: Oscillator Start-up Time-out Status bit
1= Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1
0= Running from an internal oscillator (FOSC<2:0> = 100)
bit 4
bit 3
bit 2
bit 1
bit 0
HFIOFR: High Frequency Internal Oscillator Ready bit
1= HFINTOSC is ready
0= HFINTOSC is not ready
HFIOFL: High Frequency Internal Oscillator Locked bit
1= HFINTOSC is at least 2% accurate
0= HFINTOSC is not 2% accurate
MFIOFR: Medium Frequency Internal Oscillator Ready bit
1= MFINTOSC is ready
0= MFINTOSC is not ready
LFIOFR: Low Frequency Internal Oscillator Ready bit
1= LFINTOSC is ready
0= LFINTOSC is not ready
HFIOFS: High Frequency Internal Oscillator Stable bit
1= HFINTOSC is at least 0.5% accurate
0= HFINTOSC is not 0.5% accurate
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 73
PIC16F/LF1946/47
REGISTER 5-3:
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
TUN<5:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<4:0>: Frequency Tuning bits
011111= Maximum frequency
011110=
•
•
•
000001=
000000= Oscillator module is running at the factory-calibrated frequency.
111111=
•
•
•
100000= Minimum frequency
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
OSCSTAT
OSCTUNE
PIE2
SPLLEN
T1OSCR
—
IRCF<3:0>
—
SCS<1:0>
72
73
PLLR
—
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
TUN<5:0>
74
(1)
LCDIE
LCDIF
OSFIE
OSFIF
C2IE
C2IF
C1IE
C1IF
EEIE
EEIF
BCLIE
BCLIF
—
—
—
CCP2IE
CCP2IF
91
(1)
PIR2
95
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
T1SYNC
TMR1ON
199
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
Note 1: PIC16F1947 only.
TABLE 5-3:
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Register
on Page
Name
CONFIG1
CONFIG2
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
CP
—
—
MCLRE
—
FCMEN
PWRTE
LVP
IESO
CLKOUTEN
BOREN<1:0>
CPD
54
56
WDTE<1:0>
FOSC<2:0>
STVREN
13:8
7:0
DEBUG
—
—
—
BORV
—
PLLEN
—
—
VCAPEN
WRT<1:0>
Legend:
Note 1:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
PIC16F1946/47 only.
DS41414A-page 74
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
6.0
RESETS
There are multiple ways to reset this device:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• WDT Reset
• RESETinstruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
FIGURE 6-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Programming Mode Exit
RESET Instruction
Stack Overflow/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
BOR
Enable
PWRT
64 ms
Zero
LFINTOSC
PWRTEN
2010 Microchip Technology Inc.
Preliminary
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PIC16F/LF1946/47
6.1
Power-on Reset (POR)
6.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when Vdd
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu-
ration Word 1. The four operating modes are:
• BOR is always on
6.1.1
POWER-UP TIMER (PWRT)
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
The Power-up Timer provides a nominal 64 ms time-
out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Word 1.
Refer to Table 6-3 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Word 2.
A VDD noise rejection filter prevents the BOR from trig-
gering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device
will reset. See Figure 6-3 for more information.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1:
BOR OPERATING MODES
Device
Device
BOREN
Config bits
Operation upon
SBOREN
Device Mode
BOR Mode
Operation upon
release of POR
wake-up from
Sleep
BOR_ON (11)
X
X
X
1
0
X
X
Awake
Sleep
X
Active
Active
Waits for BOR ready(1)
BOR_NSLEEP (10)
BOR_NSLEEP (10)
BOR_SBOREN (01)
BOR_SBOREN (01)
BOR_OFF (00)
Waits for BOR ready
Disabled
Active
Begins immediately
Begins immediately
Begins immediately
X
Disabled
Disabled
X
Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in
start-up.
6.2.1
BOR IS ALWAYS ON
6.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Word 1 are set
to ‘11’, the BOR is always on. The device start-up will
be delayed until the BOR is ready and VDD is higher
than the BOR threshold.
When the BOREN bits of Configuration Word 1 are set
to ‘01’, the BOR is controlled by the SBOREN bit of the
BORCON register. The device start-up is not delayed
by the BOR ready condition or the VDD level.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
6.2.2
BOR IS OFF IN SLEEP
BOR protection is unchanged by Sleep.
When the BOREN bits of Configuration Word 1 are set
to ‘10’, the BOR is on, except in Sleep. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
DS41414A-page 76
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 6-2:
BROWN-OUT READY
SBOREN
TBORRDY
BOR Protection Active
BORRDY
FIGURE 6-3:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
(1)
TPWRT
VDD
VBOR
Internal
Reset
< TPWRT
(1)
TPWRT
VDD
VBOR
Internal
Reset
(1)
TPWRT
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
REGISTER 6-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
SBOREN
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R-q/u
—
BORRDY
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
SBOREN: Software Brown-out Reset Enable bit
If BOREN <1:0> in Configuration Word 1 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Word 1 = 01:
1= BOR Enabled
0= BOR Disabled
bit 6-1
bit 0
Unimplemented: Read as ‘0’
BORRDY: Brown-out Reset Circuit Ready Status bit
1= The Brown-out Reset circuit is active
0= The Brown-out Reset circuit is inactive
2010 Microchip Technology Inc.
Preliminary
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6.3
MCLR
6.7
Programming Mode Exit
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2 (Table 6-2).
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.8
Power-Up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
TABLE 6-2:
MCLRE
MCLR CONFIGURATION
LVP
MCLR
0
1
x
0
0
1
Disabled
Enabled
Enabled
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word 1.
6.9
Start-up Sequence
6.3.1
MCLR ENABLED
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
1. Power-up Timer runs to completion (if enabled).
2. Oscillator start-up timer runs to completion (if
required for oscillator source).
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
3. MCLR must be released (if enabled).
Note:
A Reset does not drive the MCLR pin low.
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for more information.
6.3.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.6 “PORTE
Registers” for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 6-4). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
6.4
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDTinstruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
“Watchdog Timer” for more information.
6.5
RESET Instruction
A RESETinstruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.6
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration Word
2. See Section 3.4.2 “Overflow/Underflow Reset” for
more information.
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FIGURE 6-4:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
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6.10 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RMCLR
RI
POR
BOR
TO
PD
Condition
0
0
0
0
u
u
u
u
u
u
1
u
0
0
0
0
u
u
u
u
u
u
u
1
1
1
1
1
u
u
u
0
0
u
u
u
1
1
1
1
u
u
u
u
u
0
u
u
0
0
0
u
u
u
u
u
u
u
u
u
x
x
x
0
u
u
u
u
u
u
u
u
1
0
x
1
0
0
1
u
1
u
u
u
1
x
0
1
u
0
0
u
0
u
u
u
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
TABLE 6-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
0000h
---1 1000
---u uuuu
00-- 110x
uu-- 0uuu
MCLR Reset during normal operation
0000h
MCLR Reset during Sleep
WDT Reset
0000h
0000h
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
1u-- uuuu
u1-- uuuu
WDT Wake-up from Sleep
Brown-out Reset
PC + 1
0000h
Interrupt Wake-up from Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
PC + 1(1)
0000h
0000h
0000h
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
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6.11 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• Stack Overflow Reset (STKOVF)
• Stack Underflow Reset (STKUNF)
• MCLR Reset (RMCLR)
The PCON register bits are shown in Register 6-2.
REGISTER 6-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q R/W/HS-0/q
U-0
—
U-0
—
R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF
bit 7
STKUNF
RMCLR
RI
POR
BOR
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
U = Unimplemented bit, read as ‘0’
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
-m/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
STKOVF: Stack Overflow Flag bit
1= A Stack Overflow occurred
0= A Stack Overflow has not occurred or set to ‘0’ by firmware
STKUNF: Stack Underflow Flag bit
1= A Stack Underflow occurred
0= A Stack Underflow has not occurred or set to ‘0’ by firmware
bit 5-4
bit 3
Unimplemented: Read as ‘0’
RMCLR: MCLR Reset Flag bit
1= A MCLR Reset has not occurred or set to ‘1’ by firmware
0= A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
bit 2
bit 1
bit 0
RI: RESETInstruction Flag bit
1= A RESETinstruction has not been executed or set to ‘1’ by firmware
0= A RESETinstruction has been executed (set to ‘0’ in hardware upon executing a RESETinstruction)
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
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TABLE 6-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BORCON SBOREN
—
—
—
—
—
—
—
RMCLR
PD
—
RI
Z
—
POR
DC
BORRDY
BOR
77
81
PCON
STKOVF STKUNF
STATUS
WDTCON
—
—
—
—
TO
C
23
WDTPS<4:0>
SWDTEN
105
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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7.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce Interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1 and Figure 7-2.
FIGURE 7-1:
INTERRUPT LOGIC
Wake-up (If in Sleep mode)
TMR0IF
TMR0IE
INTF
INTE
Interrupt to CPU
IOCIF
IOCIE
From Peripheral Interrupt
Logic (Figure 7-2)
PEIE
GIE
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FIGURE 7-2:
PERIPHERAL INTERRUPT LOGIC
TMR1GIF
TMR1GIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
CCP5IF
CCP5IE
OSFIF
OSFIE
TMR1IF
TMR1IE
To Interrupt Logic
(Figure 7-1)
TMR6IF
TMR6IE
C2IF
C2IE
C1IF
C1IE
EEIF
EEIE
BCLIF
BCLIE
LCDIF
LCDIE
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7.1
Operation
7.2
Interrupt Latency
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 7-3
and Figure 7-4 for more details.
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)
The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 7-3:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
Interrupt Sampled
during Q1
Interrupt
GIE
PC-1
PC
PC+1
0004h
NOP
0005h
PC
1 Cycle Instruction at PC
Execute
Inst(PC)
NOP
Inst(0004h)
Interrupt
GIE
PC+1/FSR
ADDR
New PC/
PC+1
PC-1
PC
0004h
NOP
0005h
PC
Execute
2 Cycle Instruction at PC
Inst(PC)
NOP
Inst(0004h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
NOP
PC+2
NOP
0004h
NOP
0005h
PC
Execute
3 Cycle Instruction at PC
Inst(0004h)
Inst(0005h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
NOP
PC+2
0004h
NOP
0005h
PC
NOP
Execute
3 Cycle Instruction at PC
NOP
Inst(0004h)
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FIGURE 7-4:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
INTF
(1)
(1)
(2)
(5)
Interrupt Latency
GIE
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
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7.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEPinstruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 9.0 “Power-
Down Mode (Sleep)” for more details.
7.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION register determines on which
edge the interrupt will occur. When the INTEDG bit is
set, the rising edge will cause the interrupt. When the
INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
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7.5.1
INTCON REGISTER
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.
REGISTER 7-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
GIE
R/W-0/0
PEIE
R/W-0/0
TMR0IE
R/W-0/0
INTE
R/W-0/0
IOCIE
R/W-0/0
TMR0IF
R/W-0/0
INTF
R-0/0
IOCIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1= Enables all active interrupts
0= Disables all interrupts
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEIE: Peripheral Interrupt Enable bit
1= Enables all active peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: Timer0 Overflow Interrupt Enable bit
1= Enables the Timer0 interrupt
0= Disables the Timer0 interrupt
INTE: INT External Interrupt Enable bit
1= Enables the INT external interrupt
0= Disables the INT external interrupt
IOCIE: Interrupt-on-Change Enable bit
1= Enables the interrupt-on-change
0= Disables the interrupt-on-change
TMR0IF: Timer0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed
0= TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1= The INT external interrupt occurred
0= The INT external interrupt did not occur
IOCIF: Interrupt-on-Change Interrupt Flag bit
1= When at least one of the interrupt-on-change pins changed state
0= None of the interrupt-on-change pins have changed state
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7.5.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 7-2.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
TMR1GIE
bit 7
R/W-0/0
ADIE
R/W-0/0
RCIE
R/W-0/0
TXIE
R/W-0/0
SSPIE
R/W-0/0
CCP1IE
R/W-0/0
TMR2IE
R/W-0/0
TMR1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIE: Timer1 Gate Interrupt Enable bit
1= Enables the Timer1 Gate Acquisition interrupt
0= Disables the Timer1 Gate Acquisition interrupt
ADIE: A/D Converter (ADC) Interrupt Enable bit
1= Enables the ADC interrupt
0= Disables the ADC interrupt
RCIE: USART1 Receive Interrupt Enable bit
1= Enables the USART1 receive interrupt
0= Disables the USART1 receive interrupt
TXIE: USART1 Transmit Interrupt Enable bit
1= Enables the USART1 transmit interrupt
0= Disables the USART1 transmit interrupt
SSPIE: Synchronous Serial Port (MSSP1) Interrupt Enable bit
1= Enables the MSSP1 interrupt
0= Disables the MSSP1 interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the Timer2 to PR2 match interrupt
0= Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
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7.5.3
PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 7-3.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-3:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
OSFIE
bit 7
R/W-0/0
C2IE
R/W-0/0
C1IE
R/W-0/0
EEIE
R/W-0/0
BCLIE
R/W-0/0
LCDIE
U-0
—
R/W-0/0
CCP2IE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables the Oscillator Fail interrupt
0= Disables the Oscillator Fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1= Enables the Comparator C2 interrupt
0= Disables the Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1= Enables the Comparator C1 interrupt
0= Disables the Comparator C1 interrupt
EEIE: EEPROM Write Completion Interrupt Enable bit
1= Enables the EEPROM Write Completion interrupt
0= Disables the EEPROM Write Completion interrupt
BCLIE: MSSP1 Bus Collision Interrupt Enable bit
1= Enables the MSSP1 Bus Collision Interrupt
0= Disables the MSSP1 Bus Collision Interrupt
LCDIE: LCD Module Interrupt Enable bit
1= Enables the LCD module interrupt
0= Disables the LCD module interrupt
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
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7.5.4
PIE3 REGISTER
The PIE3 register contains the interrupt enable bits, as
shown in Register 7-4.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-4:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
R/W-0/0
CCP5IE
R/W-0/0
CCP4IE
R/W-0/0
CCP3IE
R/W-0/0
TMR6IE
U-0
—
R/W-0/0
TMR4IE
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
CCP5IE: CCP5 Interrupt Enable bit
1= Enables the CCP5 interrupt
0= Disables the CCP5 interrupt
bit 5
bit 4
bit 3
CCP4IE: CCP4 Interrupt Enable bit
1= Enables the CCP4 interrupt
0= Disables the CCP4 interrupt
CCP3IE: CCP3 Interrupt Enable bit
1= Enables the CCP3 interrupt
0= Disables the CCP3 interrupt
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1= Enables the TMR6 to PR6 Match interrupt
0= Disables the TMR6 to PR6 Match interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= Enables the TMR4 to PR4 Match interrupt
0= Disables the TMR4 to PR4 Match interrupt
bit 0
Unimplemented: Read as ‘0’
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7.5.5
PIE4 REGISTER
The PIE4 register contains the interrupt enable bits, as
shown in Register 7-5.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-5:
PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
U-0
—
U-0
—
R/W-0/0
RC2IE
R/W-0/0
TX2IE
U-0
—
U-0
—
R/W-0/0
BCL2IE
R/W-0/0
SSP2IE
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IE: USART2 Receive Interrupt Enable bit
1= Enables the USART2 receive interrupt
0= Disables the USART2 receive interrupt
bit 4
TX2IE: USART2 Transmit Interrupt Enable bit
1= Enables the USART2 transmit interrupt
0= Disables the USART2 transmit interrupt
bit 3-2
bit 1
Unimplemented: Read as ‘0’
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1= Enables the MSSP2 Bus Collision Interrupt
0= Disables the MSSP2 Bus Collision Interrupt
bit 0
SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit
1= Enables the MSSP2 interrupt
0= Disables the MSSP2 interrupt
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 93
PIC16F/LF1946/47
7.5.6
PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 7-6.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-6:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
TMR1GIF
bit 7
R/W-0/0
ADIF
R-0/0
RCIF
R-0/0
TXIF
R/W-0/0
SSPIF
R/W-0/0
CCP1IF
R/W-0/0
TMR2IF
R/W-0/0
TMR1IF
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIF: Timer1 Gate Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
ADIF: A/D Converter Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
RCIF: USART1 Receive Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TXIF: USART1 Transmit Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
SSPIF: Synchronous Serial Port (MSSP1) Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
CCP1IF: CCP1 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TMR1IF: Timer1 Overflow Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
DS41414A-page 94
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
7.5.7
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 7-7.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-7:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
OSFIF
R/W-0/0
C2IF
R/W-0/0
C1IF
R/W-0/0
EEIF
R/W-0/0
BCLIF
R/W-0/0
LCDIF
U-0
—
R/W-0/0
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
OSFIF: Oscillator Fail Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
C2IF: Comparator C2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
C1IF: Comparator C1 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
EEIF: EEPROM Write Completion Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
BCLIF: MSSP1 Bus Collision Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
LCDIF: LCD Module Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 95
PIC16F/LF1946/47
7.5.8
PIR3 REGISTER
The PIR3 register contains the interrupt flag bits, as
shown in Register 7-8.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-8:
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
R/W-0/0
R/W-0/0
CCP5IF
R/W-0/0
CCP4IF
R/W-0/0
CCP3IF
R/W-0/0
TMR6IF
R/W-0/0
—
R/W-0/0
TMR4IF
R/W-0/0
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
CCP5IF: CCP5 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 5
bit 4
bit 3
CCP4IF: CCP4 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
CCP3IF: CCP3 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TMR6IF: TMR6 to PR6 Match Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 0
Unimplemented: Read as ‘0’
DS41414A-page 96
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
7.5.9
PIR4 REGISTER
The PIR4 register contains the interrupt flag bits, as
shown in Register 7-9.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-9:
PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
U-0
—
U-0
—
R/W-0/0
RC2IF
R/W-0/0
TX2IF
U-0
—
U-0
—
R/W-0/0
BCL2IF
R/W-0/0
SSP2IF
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IF: USART2 Receive Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 4
TX2IF: USART2 Transmit Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 3-2
bit 1
Unimplemented: Read as ‘0’
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 0
SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
2010 Microchip Technology Inc.
Preliminary
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PIC16F/LF1946/47
TABLE 7-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
T0CS
RCIE
INTE
T0SE
TXIE
EEIE
IOCIE
PSA
TMR0IF
INTF
IOCIF
89
189
90
91
92
93
94
95
96
97
OPTION_REG WPUEN INTEDG
PS<2:0>
PIE1
PIE2
PIE3
PIE4
PIR1
PIR2
PIR3
PIR4
TMR1GIE
OSFIE
—
ADIE
C2IE
SSPIE
BCLIE
CCP1IE TMR2IE TMR1IE
C1IE
LCDIE
—
—
CCP2IE
—
CCP5IE CCP4IE CCP3IE TMR6IE
TMR4IE
—
—
RC2IE
RCIF
C1IF
TX2IE
TXIF
—
—
BCL2IE SSP2IE
TMR1GIF
OSFIF
—
ADIF
C2IF
SSPIF
BCLIF
CCP1IF TMR2IF TMR1IF
EEIF
LCDIF
—
—
CCP2IF
—
CCP5IF CCP4IF CCP3IF TMR6IF
RC2IF TX2IF
TMR4IF
—
—
—
—
BCL2IF SSP2IF
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.
DS41414A-page 98
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is held in Reset while a constant current source
charges the external capacitor. After the cap is fully
charged, the device is released from Reset. For more
information on recommended capacitor values and the
constant current rate, refer to the LDO Regulator
Characteristics Table in Section 29.0 “Electrical
Specifications”.
8.0
LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F1946/47 has an internal Low Dropout
Regulator (LDO) which provides operation above 3.6V.
The LDO regulates a voltage for the internal device
logic while permitting the VDD and I/O pins to operate
at a higher voltage. There is no user enable/disable
control available for the LDO, it is always active. The
PIC16LF1946/47 operates at a maximum VDD of 3.6V
and does not incorporate an LDO.
A device I/O pin may be configured as the LDO voltage
output, identified as the VCAP pin. Although not
required, an external low-ESR capacitor may be con-
nected to the VCAP pin for additional regulator stability.
The VCAPEN bit of Configuration Word 2 determines
which pin is assigned as the VCAP pin. Refer to Table 8-1.
TABLE 8-1:
VCAPEN<1:0>
00
11
VCAPEN<1:0> SELECT BITS
Pin
RF0
No Vcap
TABLE 8-2:
SUMMARY OF CONFIGURATION WORD WITH LDO
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
—
—
LVP
DEBUG
—
—
—
BORV
—
STVREN
WRT1
PLLEN
WRT0
CONFIG2
56
VCAPEN1
Legend:
— = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 99
PIC16F/LF1946/47
NOTES:
DS41414A-page 100
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
9.1
Wake-up from Sleep
9.0
POWER-DOWN MODE (SLEEP)
The device can wake-up from Sleep through one of the
following events:
The Power-down mode is entered by executing a
SLEEPinstruction.
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
Upon entering Sleep mode, the following conditions
exist:
3. POR Reset
1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.
4. Watchdog Timer, if enabled
5. Any external interrupt
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
6. Interrupts by peripherals capable of running dur-
ing Sleep (see individual peripheral for more
information)
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
The first three events will cause a device Reset. The
last three events are considered a continuation of pro-
gram execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 6.10
“Determining the Cause of a Reset”.
6. Timer1 oscillator is unaffected and peripherals
that operate from it may continue operation in
Sleep.
7. ADC is unaffected, if the dedicated FRC clock is
selected.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
8. Capacitive Sensing oscillator is unaffected.
9. I/O ports maintain the status they had before
SLEEPwas executed (driving high, low or high-
impedance).
10. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following condi-
tions should be considered:
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• Modules using Timer1 oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 16.0 “Digital-to-Analog Con-
verter (DAC) Module” and Section 14.0 “Fixed Volt-
age Reference (FVR)” for more information on these
modules.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 101
PIC16F/LF1946/47
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction
9.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
- SLEEPinstruction will be completely exe-
cuted
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
• If the interrupt occurs before the execution of a
SLEEPinstruction
- SLEEPinstruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
- PD bit of the STATUS register will not be
cleared.
FIGURE 9-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
(3)
CLKOUT(2)
TOST
Interrupt Latency(4)
Interrupt flag
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Instruction
Executed
Dummy Cycle
Dummy Cycle
Sleep
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1:
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS or LP Oscillator modes, but shown here for timing reference.
TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
2:
3:
4:
GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 9-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
IOCBF
IOCBN
IOCBP
PIE1
GIE
IOCBF7
IOCBN7
IOCBP7
TMR1GIE
OSFIE
—
PEIE
IOCBF6
IOCBN6
IOCBP6
ADIE
C2IE
CCP5IE
—
TMR0IE
IOCBF5
IOCBN5
IOCBP5
RCIE
INTE
IOCBF4
IOCBN4
IOCBP4
TXIE
IOCIE
IOCBF3
IOCBN3
IOCBP3
SSPIE
BCLIE
TMR6IE
—
TMR0IF
IOCBF2
IOCBN2
IOCBP2
CCP1IE
LCDIE
—
INTF
IOCBF1
IOCBN1
IOCBP1
TMR2IE
—
IOCIF
IOCBF0
IOCBN0
IOCBP0
TMR1IE
CCP2IE
—
89
148
148
148
90
PIE2
C1IE
EEIE
91
PIE3
CCP4IE
RC2IE
RCIF
CCP3IE
TX2IE
TXIF
TMR4IE
BCL2IE
TMR2IF
—
92
PIE4
—
—
SSP2IE
TMR1IF
CCP2IF
—
93
PIR1
TMR1GIF
OSFIF
—
ADIF
C2IF
SSPIF
BCLIF
CCP1IF
LCDIF
—
94
PIR2
C1IF
EEIF
95
PIR3
CCP5IF
—
CCP4IF
RC2IF
—
CCP3IF
TX2IF
TO
TMR6IF
—
TMR4IF
BCL2IF
DC
96
PIR4
—
—
SSP2IF
C
97
STATUS
WDTCON
—
—
PD
Z
23
—
—
WDTPS<4:0>
SWDTEN
105
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.
DS41414A-page 102
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
10.0 WATCHDOG TIMER
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (typical)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 10-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
23-bit Programmable
WDT Time-out
WDTE<1:0> = 11
LFINTOSC
Prescaler WDT
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 103
PIC16F/LF1946/47
10.1 Independent Clock Source
10.3 Time-Out Period
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator.
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds. After a
Reset, the default time-out period is 2 seconds.
10.2 WDT Operating Modes
10.4 Clearing the WDT
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word 1. See Table 10-1.
The WDT is cleared when any of the following condi-
tions occur:
• Any Reset
10.2.1
WDT IS ALWAYS ON
• CLRWDTinstruction is executed
• Device enters Sleep
When the WDTE bits of Configuration Word 1 are set to
‘11’, the WDT is always on.
• Device wakes up from Sleep
• Oscillator fail event
WDT protection is active during Sleep.
• WDT is disabled
10.2.2
WDT IS OFF IN SLEEP
• Oscillator Start-up TImer (OST) is running
When the WDTE bits of Configuration Word 1 are set to
See Table 10-2 for more information.
‘10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
10.5 Operation During Sleep
10.2.3
WDT CONTROLLED BY SOFTWARE
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the WDTE bits of Configuration Word 1 are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator
Module (With Fail-Safe Clock Monitor)” for more
information on the OST.
WDT protection is unchanged by Sleep. See
Table 10-1 for more details.
TABLE 10-1: WDT OPERATING MODES
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device wakes
up and resumes operation. The TO and PD bits in the
STATUS register are changed to indicate the event. See
Section 3.0 “Memory Organization” and STATUS
register (Register 3-1) for more information.
WDTE
Config bits
Device
Mode
WDT
Mode
SWDTEN
WDT_ON (11)
X
X
X
1
0
X
X
Active
Active
WDT_NSLEEP (10)
WDT_NSLEEP (10)
WDT_SWDTEN (01)
WDT_SWDTEN (01)
WDT_OFF (00)
Awake
Sleep Disabled
X
X
X
Active
Disabled
Disabled
TABLE 10-2: WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDTCommand
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
Unaffected
Change INTOSC divider (IRCF bits)
DS41414A-page 104
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
WDTPS<4:0>
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-m/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-1
Unimplemented: Read as ‘0’
WDTPS<4:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
00000 = 1:32 (Interval 1 ms typ)
00001 = 1:64 (Interval 2 ms typ)
00010 = 1:128 (Interval 4 ms typ)
00011 = 1:256 (Interval 8 ms typ)
00100 = 1:512 (Interval 16 ms typ)
00101 = 1:1024 (Interval 32 ms typ)
00110 = 1:2048 (Interval 64 ms typ)
00111 = 1:4096 (Interval 128 ms typ)
01000 = 1:8192 (Interval 256 ms typ)
01001 = 1:16384 (Interval 512 ms typ)
01010 = 1:32768 (Interval 1s typ)
01011 = 1:65536 (Interval 2s typ) (Reset value)
01100 = 1:131072 (217) (Interval 4s typ)
01101 = 1:262144 (218) (Interval 8s typ)
01110 = 1:524288 (219) (Interval 16s typ)
01111 = 1:1048576 (220) (Interval 32s typ)
10000 = 1:2097152 (221) (Interval 64s typ)
10001 = 1:4194304 (222) (Interval 128s typ)
10010 = 1:8388608 (223) (Interval 256s typ)
10011 = Reserved. Results in minimum interval (1:32)
•
•
•
11111 = Reserved. Results in minimum interval (1:32)
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
This bit is ignored.
If WDTE<1:0> = 01:
1= WDT is turned on
0= WDT is turned off
If WDTE<1:0> = 1x:
This bit is ignored.
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NOTES:
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Preliminary
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11.1 EEADRL and EEADRH Registers
11.0 DATA EEPROM AND FLASH
PROGRAM MEMORY
CONTROL
The EEADRH:EEADRL register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 32K words of program memory.
The Data EEPROM and Flash program memory are
readable and writable during normal operation (full VDD
range). These memories are not directly mapped in the
register file space. Instead, they are indirectly
addressed through the Special Function Registers
(SFRs). There are six SFRs used to access these
memories:
When selecting a program address value, the MSB of
the address is written to the EEADRH register and the
LSB is written to the EEADRL register. When selecting
a EEPROM address value, only the LSB of the address
is written to the EEADRL register.
11.1.1
EECON1 AND EECON2 REGISTERS
• EECON1
• EECON2
• EEDATL
• EEDATH
• EEADRL
• EEADRH
EECON1 is the control register for EE memory
accesses.
Control bit EEPGD determines if the access will be a
program or data memory access. When clear, any
subsequent operations will operate on the EEPROM
memory. When set, any subsequent operations will
operate on the program memory. On Reset, EEPROM is
selected by default.
When interfacing the data memory block, EEDATL
holds the 8-bit data for read/write, and EEADRL holds
the address of the EEDATL location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 0h to 0FFh.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
When accessing the program memory block, the EED-
ATH:EEDATL register pair forms a 2-byte word that
holds the 14-bit data for read/write, and the EEADRL
and EEADRH registers form a 2-byte word that holds
the 15-bit address of the program memory location
being read.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The EEPROM data memory allows byte read and write.
An EEPROM byte write automatically erases the loca-
tion and writes the new data (erase before write).
Interrupt flag bit EEIF of the PIR2 register is set when
write is complete. It must be cleared in the software.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
Reading EECON2 will read all ‘0’s. The EECON2 reg-
ister is used exclusively in the data EEPROM write
sequence. To enable writes, a specific pattern must be
written to EECON2.
Depending on the setting of the Flash Program
Memory Self Write Enable bits WRT<1:0> of the
Configuration Word 2, the device may or may not be
able to write certain blocks of the program memory.
However, reads from the program memory are always
allowed.
When the device is code-protected, the device
programmer can no longer access data or program
memory. When code-protected, the CPU may continue
to read and write the data EEPROM memory and Flash
program memory.
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11.2.2
WRITING TO THE DATA EEPROM
MEMORY
11.2 Using the Data EEPROM
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). When vari-
ables in one section change frequently, while variables
in another section do not change, it is possible to
exceed the total number of write cycles to the
EEPROM without exceeding the total number of write
cycles to a single byte. Refer to Section 29.0 “Electri-
cal Specifications”. If this is the case, then a refresh
of the array must be performed. For this reason, vari-
ables that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
To write an EEPROM data location, the user must first
write the address to the EEADRL register and the data
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set the WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
11.2.1
READING THE DATA EEPROM
MEMORY
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD and
CFGS control bits of the EECON1 register, and then
set control bit RD. The data is available at the very next
cycle, in the EEDATL register; therefore, it can be read
in the next instruction. EEDATL will hold this value until
another read or until it is written to by the user (during
a write operation).
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
11.2.3
PROTECTION AGAINST SPURIOUS
WRITE
EXAMPLE 11-1:
DATA EEPROM READ
BANKSELEEADRL
;
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also, the
Power-up Timer (64 ms duration) prevents EEPROM
write.
MOVLW
MOVWF
DATA_EE_ADDR ;
EEADRL
;Data Memory
;Address to read
EECON1, CFGS ;Deselect Config space
EECON1, EEPGD;Point to DATA memory
BCF
BCF
BSF
MOVF
EECON1, RD
EEDATL, W
;EE Read
;W = EEDATL
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• Brown-out
Note:
Data EEPROM can be read regardless of
the setting of the CPD bit.
• Power Glitch
• Software Malfunction
11.2.4
DATA EEPROM OPERATION
DURING CODE-PROTECT
Data memory can be code-protected by programming
the CPD bit in the Configuration Word 1 (Register 4-1)
to ‘0’.
When the data memory is code-protected, only the
CPU is able to read and write data to the data
EEPROM. It is recommended to code-protect the pro-
gram memory when code protecting data memory. This
prevents anyone from replacing your program with a
program that will access the contents of the data
EEPROM.
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EXAMPLE 11-2:
DATA EEPROM WRITE
BANKSEL EEADRL
;
MOVLW
MOVWF
MOVLW
MOVWF
BCF
DATA_EE_ADDR
EEADRL
DATA_EE_DATA
EEDATL
;
;Data Memory Address to write
;
;Data Memory Value to write
;Deselect Configuration space
EECON1, CFGS
BCF
EECON1, EEPGD ;Point to DATA memory
BSF
EECON1, WREN
;Enable writes
BCF
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
EECON1, WR
$-2
;Disable INTs.
;
;Write 55h
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BTFSC
GOTO
;Write AAh
;Set WR bit to begin write
;Enable Interrupts
;Disable writes
;Wait for write to complete
;Done
FIGURE 11-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
PC + 1
EEADRH,EEADRL
PC + 3
PC + 4
PC + 5
Flash ADDR
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDATL
INSTR (PC + 3)
INSTR (PC + 4)
BSF EECON1,RD
executed here
INSTR(PC - 1)
executed here
INSTR(PC + 1)
executed here
Forced NOP
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
EEDATH
EEDATL
Register
EERHLT
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11.3.1
READING THE FLASH PROGRAM
MEMORY
11.3 Flash Program Memory Overview
It is important to understand the Flash program mem-
ory structure for erase and programming operations.
Flash Program memory is arranged in rows. A row con-
sists of a fixed number of 14-bit program memory
words. A row is the minimum block size that can be
erased by user software.
To read a program memory location, the user must:
1. Write the Least and Most Significant address
bits to the EEADRH:EEADRL register pair.
2. Clear the CFGS bit of the EECON1 register.
3. Set the EEPGD control bit of the EECON1
register.
Flash program memory may only be written or erased
if the destination address is in a segment of memory
that is not write-protected, as defined in bits WRT<1:0>
of Configuration Word 2.
4. Then, set control bit RD of the EECON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF EECON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the EEDATH:EEDATL register pair; therefore, it can
be read as two bytes in the following instructions.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the EEDATH:EEDATL register pair.
EEDATH:EEDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Note 1: The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
The number of data write latches is not equivalent to
the number of row locations. During programming, user
software will need to fill the set of write latches and ini-
tiate a programming operation multiple times in order to
fully reprogram an erased row. For example, a device
with a row size of 32 words and eight write latches will
need to load the write latches with data and initiate a
programming operation four times.
2: Flash program memory can be read
regardless of the setting of the CP bit.
The size of a program memory row and the number of
program memory write latches may vary by device.
See Table 11-1 for details.
TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE
Device
Erase Block (Row) Size/Boundary
Number of Write Latches/Boundary
PIC16F/LF1946/47
32 words, EEADRL<4:0> = 00000
8 words, EEADRL<2:0> = 000
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EXAMPLE 11-3:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI: PROG_ADDR_LO
*
*
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL
; Select Bank for EEPROM registers
MOVLW
MOVWF
MOVLW
MOVWL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
; Do not select Configuration Space
; Select Program Memory
; Disable interrupts
; Initiate read
; Executed (Figure 11-1)
; Ignored (Figure 11-1)
; Restore interrupts
INTCON,GIE
MOVF
EEDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
EEDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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The following steps should be completed to load the
write latches and program a block of program memory.
These steps are divided into two parts. First, all write
latches are loaded with data except for the last program
memory location. Then, the last write latch is loaded
and the programming sequence is initiated. A special
unlock sequence is required to load a write latch with
data or initiate a Flash programming operation. This
unlock sequence should not be interrupted.
11.3.2
ERASING FLASH PROGRAM
MEMORY
While executing code, program memory can only be
erased by rows. To erase a row:
1. Load the EEADRH:EEADRL register pair with
the address of new row to be erased.
2. Clear the CFGS bit of the EECON1 register.
3. Set the EEPGD, FREE, and WREN bits of the
EECON1 register.
1. Set the EEPGD and WREN bits of the EECON1
register.
4. Write 55h, then AAh, to EECON2 (Flash
programming unlock sequence).
2. Clear the CFGS bit of the EECON1 register.
5. Set control bit WR of the EECON1 register to
begin the erase operation.
3. Set the LWLO bit of the EECON1 register. When
the LWLO bit of the EECON1 register is ‘1’, the
write sequence will only load the write latches
and will not initiate the write to Flash program
memory.
6. Poll the FREE bit in the EECON1 register to
determine when the row erase has completed.
See Example 11-4.
4. Load the EEADRH:EEADRL register pair with
the address of the location to be written.
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOPinstructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the EECON1 write instruction.
5. Load the EEDATH:EEDATL register pair with
the program memory data to be written.
6. Write 55h, then AAh, to EECON2, then set the
WR bit of the EECON1 register (Flash
programming unlock sequence). The write latch
is now loaded.
7. Increment the EEADRH:EEADRL register pair
to point to the next location.
11.3.3
WRITING TO FLASH PROGRAM
MEMORY
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
Program memory is programmed using the following
steps:
9. Clear the LWLO bit of the EECON1 register.
When the LWLO bit of the EECON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
1. Load the starting address of the word(s) to be
programmed.
2. Load the write latches with data.
10. Load the EEDATH:EEDATL register pair with
the program memory data to be written.
3. Initiate a programming operation.
4. Repeat steps 1 through 3 until all data is written.
11. Write 55h, then AAh, to EECON2, then set the
WR bit of the EECON1 register (Flash
programming unlock sequence). The entire
latch block is now written to Flash program
memory.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Pro-
gram memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 11-2 (block writes to program memory with 16
write latches) for more details. The write latches are
aligned to the address boundary defined by EEADRL
as shown in Table 11-1. Write operations do not cross
these boundaries. At the completion of a program
memory write operation, the write latches are reset to
contain 0x3FFF.
It is not necessary to load the entire write latch block
with user program data. However, the entire write latch
block will be written to program memory.
An example of the complete write sequence for eight
words is shown in Example 11-5. The initial address is
loaded into the EEADRH:EEADRL register pair; the
eight words of data are loaded using indirect
addressing.
Note:
The code sequence provided in
Example 11-5 must be repeated multiple
times to fully program an erased program
memory row.
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After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the write operation. The
user must place two NOPinstructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
continue to run. The processor does not stall when
LWLO = 1, loading the write latches. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 write instruction.
FIGURE 11-2:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES
7
5
0
0 7
EEDATH
6
EEDATA
8
Last word of block
to be written
First word of block
to be written
14
14
14
14
EEADRL<3:0> = 0000
EEADRL<3:0> = 0001
Buffer Register
EEADRL<3:0> = 0010
EEADRL<3:0> = 1111
Buffer Register
Buffer Register
Buffer Register
Program Memory
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EXAMPLE 11-4:
ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase block is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
BCF
INTCON,GIE
EEADRL
ADDRL,W
EEADRL
ADDRH,W
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
BSF
BSF
EEADRH
EECON1,EEPGD
EECON1,CFGS
EECON1,FREE
EECON1,WREN
; Point to program memory
; Not configuration space
; Specify an erase operation
; Enable writes
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
0AAh
EECON2
EECON1,WR
; Start of required sequence to initiate erase
; Write 55h
;
; Write AAh
; Set WR bit to begin erase
; Any instructions here are ignored as processor
; halts to begin erase sequence
; Processor will stop here and wait for erase complete.
NOP
NOP
; after erase processor continues with 3rd instruction
BCF
BSF
EECON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
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EXAMPLE 11-5:
WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
;
stored in little endian format
; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
;
BCF
INTCON,GIE
EEADRH
ADDRH,W
EEADRH
ADDRL,W
EEADRL
; Disable ints so required sequences will execute properly
; Bank 3
; Load initial address
;
;
;
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
LOW DATA_ADDR ; Load initial data address
FSR0L
HIGH DATA_ADDR ; Load initial data address
;
FSR0H
;
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,LWLO
; Point to program memory
; Not configuration space
; Enable writes
BCF
BSF
BSF
; Only Load Write Latches
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
EEDATL
FSR0++
EEDATH
; Load first data byte into lower
;
; Load second data byte into upper
;
MOVF
EEADRL,W
0x07
0x07
STATUS,Z
START_WRITE
; Check if lower bits of address are '000'
; Check if we're on the last of 8 addresses
;
; Exit if last of eight words,
;
XORLW
ANDLW
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
0AAh
EECON2
EECON1,WR
; Start of required write sequence:
; Write 55h
;
; Write AAh
; Set WR bit to begin write
NOP
; Any instructions here are ignored as processor
; halts to begin write sequence
NOP
; Processor will stop here and wait for write to complete.
; After write processor continues with 3rd instruction.
INCF
GOTO
EEADRL,F
LOOP
; Still loading latches Increment address
; Write next latches
START_WRITE
BCF
EECON1,LWLO
; No more loading latches - Actually start Flash program
; memory write
MOVLW
55h
EECON2
0AAh
EECON2
EECON1,WR
; Start of required write sequence:
; Write 55h
;
MOVWF
MOVLW
MOVWF
BSF
; Write AAh
; Set WR bit to begin write
; Any instructions here are ignored as processor
; halts to begin write sequence
; Processor will stop here and wait for write complete.
NOP
NOP
; after write processor continues with 3rd instruction
; Disable writes
; Enable interrupts
BCF
BSF
EECON1,WREN
INTCON,GIE
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11.4 Modifying Flash Program Memory
11.5 User ID, Device ID and
Configuration Word Access
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
Instead of accessing program memory or EEPROM
data memory, the User ID’s, Device ID/Revision ID and
Configuration Words can be accessed when CFGS = 1
in the EECON1 register. This is the region that would
be pointed to by PC<15> = 1, but not all addresses are
accessible. Different access may exist for reads and
writes. Refer to Table 11-2.
1. Load the starting address of the row to be
modified.
2. Read the existing data from the row into a RAM
image.
When read access is initiated on an address outside the
parameters listed in Table 11-2, the EEDATH:EEDATL
register pair is cleared.
3. Modify the RAM image to contain the new data
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
8. Repeat steps 6 and 7 as many times as required
to reprogram the erased row.
TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
8006h
User IDs
Yes
Yes
Yes
Yes
No
No
Device ID/Revision ID
Configuration Words 1 and 2
8007h-8008h
EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL
; Select correct Bank
;
; Store LSB of address
; Clear MSB of address
MOVLW
MOVWF
CLRF
PROG_ADDR_LO
EEADRL
EEADRH
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
INTCON,GIE
EECON1,RD
; Select Configuration Space
; Disable interrupts
; Initiate read
; Executed (See Figure 11-1)
; Ignored (See Figure 11-1)
; Restore interrupts
INTCON,GIE
MOVF
EEDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
EEDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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11.6 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM or program memory should be verified (see
Example 11-6) to the desired value to be written.
Example 11-6 shows how to verify a write to EEPROM.
EXAMPLE 11-6:
EEPROM WRITE VERIFY
BANKSELEEDATL
;
MOVF
EEDATL, W ;EEDATL not changed
;from previous write
BSF
EECON1, RD ;YES, Read the
;value written
XORWF
BTFSS
GOTO
:
EEDATL, W
;
STATUS, Z ;Is data the same
WRITE_ERR ;No, handle error
;Yes, continue
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REGISTER 11-1: EEDATL: EEPROM DATA REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory
REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
EEDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 11-3: EEADRL: EEPROM ADDRESS REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
REGISTER 11-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘0’
EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address
bit 6-0
DS41414A-page 118
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER
R/W-0/0
EEPGD
R/W-0/0
CFGS
R/W-0/0
LWLO
R/W/HC-0/0
FREE
R/W-x/q
WRERR
R/W-0/0
WREN
R/S/HC-0/0 R/S/HC-0/0
WR RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
bit 5
EEPGD: Flash Program/Data EEPROM Memory Select bit
1= Accesses program space Flash memory
0= Accesses data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Accesses Configuration, User ID and Device ID Registers
0= Accesses Flash Program or data EEPROM Memory
LWLO: Load Write Latches Only bit
If CFGS = 1(Configuration space) OR CFGS = 0and EEPGD = 1 (program Flash):
1= The next WR command does not initiate a write; only the program memory latches are
updated.
0= The next WR command writes a value from EEDATH:EEDATL into program memory latches
and initiates a write of all the data stored in the program memory latches.
If CFGS = 0and EEPGD = 0: (Accessing data EEPROM)
LWLO is ignored. The next WR command initiates a write to the data EEPROM.
bit 4
FREE: Program Flash Erase Enable bit
If CFGS = 1(Configuration space) OR CFGS = 0and EEPGD = 1 (program Flash):
1= Performs an erase operation on the next WR command (cleared by hardware after
completion of erase).
0= Performs a write operation on the next WR command.
If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM)
FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.
bit 3
WRERR: EEPROM Error Flag bit
1= Condition indicates an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (write ‘1’) of the WR bit).
0= The program or erase operation completed normally.
bit 2
bit 1
WREN: Program/Erase Enable bit
1= Allows program/erase cycles
0= Inhibits programming/erasing of program Flash and data EEPROM
WR: Write Control bit
1= Initiates a program Flash or data EEPROM program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0= Program/erase operation to the Flash or data EEPROM is complete and inactive.
bit 0
RD: Read Control bit
1= Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in
hardware. The RD bit can only be set (not cleared) in software.
0= Does not initiate a program Flash or data EEPROM data read.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 119
PIC16F/LF1946/47
REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
EEPROM Control Register 2
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit can only be set
‘1’ = Bit is set
bit 7-0
Data EEPROM Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
EECON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes. Refer to Section 11.2.2 “Writing to the Data EEPROM
Memory” for more information.
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EECON1
EECON2
EEADRL
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
119
107*
118
118
118
118
89
EEPROM Control Register 2 (not a physical register)
EEADRL<7:0>
EEADRH
EEDATL
—
EEADRH<6:0
EEDATL<7:0>
EEDATH
INTCON
PIE2
—
—
EEDATH<5:0>
GIE
PEIE
C2IE
C2IF
TMR0IE
C1IE
INTE
EEIE
EEIF
IOCIE
BCLIE
BCLIF
TMR0IF
LCDIE
LCDIF
INTF
C3IE
C3IF
IOCIF
CCP2IE
CCP2IF
OSFIE
OSFIF
91
PIR2
C1IF
95
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Data EEPROM module.
*
Page provides register information.
DS41414A-page 120
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
12.1 Alternate Pin Function
12.0 I/O PORTS
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 12-1. For this device family, the
following functions can be moved between different
pins.
Depending on the device selected and peripherals
enabled, there are up to five ports available. In general,
when a peripheral is enabled, that pin may not be used
as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• CCP3/P3C output
• CCP3/P3B output
• CCP2/P2D output
• CCP2/P2C output
• CCP2/P2B output
• CCP2/P2A output
• CCP1/P1C output
• CCP1/P1B output
• TRISx registers (data direction register)
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (output latch)
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
affect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
Ports with analog functions also have an ANSELx
register which can disable the digital input and save
power. A simplified model of a generic I/O port, without
the interfaces to other peripherals, is shown in
Figure 12-1.
FIGURE 12-1:
GENERIC I/O PORT
OPERATION
Read LATx
TRISx
D
Q
Write LATx
Write PORTx
CK
Data Register
VDD
Data Bus
Read PORTx
To peripherals
I/O pin
VSS
ANSELx
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 121
PIC16F/LF1946/47
REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
R/W-0/0
P3CSEL
R/W-0/0
P3BSEL
R/W-0/0
P2DSEL
R/W-0/0
P2CSEL
R/W-0/0
P2BSEL
R/W-0/0
R/W-0/0
P1CSEL
R/W-0/0
P1BSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
P3CSEL: CCP3 PWM C Output Pin Selection bit
0= P3C function is on RE3/P3C/COM0
1= P3C function is on RD3/P3C/SEG3
P3BSEL: CCP3 PWM B Output Pin Selection bit
0= P3B function is on RE4/P3B/COM1
1= P3B function is on RD4/P3B/SEG4
P2DSEL: CCP2 PWM D Output Pin Selection bit
0= P2D function is on RE0/P2D/VLCD1
1= P2D function is on RD0/P2D/SEG0
P2CSEL: CCP2 PWM C Output Pin Selection bit
0= P2C function is on RE1/P2C/VLCD2
1= P2C function is on RD1/P2C/SEG1
P2BSEL: CCP2 PWM B Output Pin Selection bit
0= P2B function is on RE2/P2B/VLCD3
1= P2B function is on RD2/P2B/SEG2
CCP2SEL: CCP2 Input/Output Pin Selection bit
0= CCP2/P2A function is on RC1/CCP2/P2A/T1OSI/SEG32
1= CCP2/P2A function is on RE7/CCP2/P2A/SEG31
P1CSEL: CCP1 PWM C Output Pin Selection bit
0= P1C function is on RE5/P1C/COM2
1= P1C function is on RD5/P1C/SEG5
P1BSEL: CCP1 PWM B Output Pin Selection bit
0= P1B function is on RE6/P1B/COM3
1= P1B function is on RD6/P1B/SEG6
DS41414A-page 122
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
12.2.2
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
12.2 PORTA Registers
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 12-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 12-1 shows how to
initialize PORTA.
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
Analog input functions, such as ADC, comparator and
CapSense inputs, are not shown in the priority lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELx registers. Digital
output functions may control the pin when it is in Analog
mode with the priority shown below.
Reading the PORTA register (Register 12-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
RA0
1. AN0 (ADC)
2. SEG33 (LCD)
3. CPS0 (CSM)
The TRISA register (Register 12-3) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
RA1
1. SEG18
2. CPS1 (CSM)
RA2
12.2.1
ANSELA REGISTER
1. SEG34 (LCD)
2. VREF- (DAC)
3. AN2 (ADC)
4. CPS2 (CSM)
The ANSELA register (Register 12-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
RA3
1. VREF+ (DAC)
2. SEG35 (LCD)
3. AN3 (ADC)
4. CPS3 (CSM)
The state of the ANSELA bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
RA4
1. SEG14 (LCD)
2. T0CKI (TMR0)
Note:
The ANSELA register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
RA5
1. AN4 (ADC)
2. SEG15 (LCD)
3. CPS4 (CSM)
RA6
EXAMPLE 12-1:
INITIALIZING PORTA
1. OSC2 (enabled by Configuration Word)
2. CLKOUT (enabled by Configuration Word)
3. SEG36 (LCD)
BANKSEL PORTA
;
CLRF
BANKSEL LATA
CLRF LATA
BANKSEL ANSELA
CLRF ANSELA
BANKSEL TRISA
PORTA
;Init PORTA
;Data Latch
;
;
;digital I/O
;
RA7
1. OSC1/CLKIN (enabled by Configuration Word)
2. SEG37 (LCD)
MOVLW
MOVWF
B'11110000' ;Set RA<7:4> as inputs
TRISA
;and set RA<3:0> as
;outputs
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 123
PIC16F/LF1946/47
REGISTER 12-2: PORTA: PORTA REGISTER
R/W-x/u
RA7
R/W-x/u
RA6
R/W-x/u
RA5
R/W-x/u
RA4
R/W-x/u
RA3
R/W-x/u
RA2
R/W-x/u
RA1
R/W-x/u
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RA<7:0>: PORTA I/O Value bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER
R/W-1/1
TRISA7
R/W-1/1
TRISA6
R/W-1/1
TRISA5
R/W-1/1
TRISA4
R/W-1/1
TRISA3
R/W-1/1
TRISA2
R/W-1/1
TRISA1
R/W-1/1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISA<7:0>: PORTA Tri-State Control bit
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER
R/W-x/u
LATA7
R/W-x/u
LATA6
R/W-x/u
LATA5
R/W-x/u
LATA4
R/W-x/u
LATA3
R/W-x/u
LATA2
R/W-x/u
LATA1
R/W-x/u
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATA<7:0>: PORTA Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
DS41414A-page 124
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER
U-0
—
U-0
—
R/W-1/1
ANSA5
U-0
—
R/W-1/1
ANSA3
R/W-1/1
ANSA2
R/W-1/1
ANSA1
R/W-1/1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5
Unimplemented: Read as ‘0’
ANSA5: Analog Select between Analog or Digital Function on pins RA<5>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 4
Unimplemented: Read as ‘0’
bit 3-0
ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON0
ADCON1
ANSELA
—
ADFM
—
CHS<4:0>
ADON
GO/DONE
159
160
ADCS<2:0>
ANSA5
—
—
ADPREF<1:0>
—
—
—
ANSA3
ANSA2
ANSA1
ANSA0
T0XCS
125
323
324
171
124
333
333
333
189
124
124
CPSCON0
CPSCON1
DACCON0
LATA
CPSON
—
CPSRM
—
—
—
CPSRNG1 CPSRNG0 CPSOUT
CPSCH<4:0>
DACEN
LATA7
SE15
DACLPS
LATA6
SE14
DACOE
LATA5
SE13
SE21
SE37
TMR0CS
RA5
---
DACPSS<1:0>
---
DACNSS
LATA0
SE8
LATA4
SE12
LATA3
LATA2
SE10
SE18
SE34
LATA1
SE9
LCDSE1
LCDSE2
LCDSE4
OPTION_REG
PORTA
SE11
SE19
SE35
PSA
SE23
SE22
SE20
SE17
SE33
PS<2:0>
RA1
SE16
SE39
SE38
SE36
SE32
WPUEN
RA7
INTEDG
RA6
TMR0SE
RA4
RA3
RA2
RA0
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 12-2: SUMMARY OF CONFIGURATION WORD WITH PORTA
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0>
FOSC<2:0>
CPD
CONFIG1
54
CP
MCLRE
WDTE<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 125
PIC16F/LF1946/47
12.3.3
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
12.3 PORTB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 12-7). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-2 shows how to initialize PORTB.
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions, such as the EUSART RX
signal, override other port functions and are included in
the priority list.
Reading the PORTB register (Register 12-6) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATB).
RB0
The TRISB register (Register 12-7) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
1. SEG30 (LCD)
2. FLT0 (CCP)
3. SRI (SR Latch)
4. INT
RB1
12.3.1
WEAK PULL-UPS
1. SEG8 (LCD)
RB2
Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:0> enable or
disable each pull-up (see Register 12-9). Each weak
pull-up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the WPUEN bit of the OPTION
register.
1. SEG9 (LCD)
RB3
1. SEG10 (LCD)
RB4
1. SEG11 (LCD)
RB5
12.3.2
INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as
an interrupt-on-change pin. Control bits IOCB<7:0>
enable or disable the interrupt function for each pin.
The interrupt-on-change feature is disabled on a
1. SEG29 (LCD)
2. T1G (TMR1)
RB6
Power-on
Reset.
Reference
Section 13.0
1. ICSPCLK (Programming)
2. ICDCLK (enabled by Configuration Word)
3. SEG38 (LCD)
“Interrupt-On-Change” for more information.
EXAMPLE 12-2:
INITIALIZING PORTB
BANKSEL PORTDB;
RB7
CLRF
BANKSEL LATDB
CLRF LATB
BANKSEL TRISD
PORTB
;Init PORTD
;Data Latch
;
;
1. ICSPDAT (Programming)
2. ICDDAT (enabled by Configuration Word)
3. SEG39 (LCD)
MOVLW
MOVWF
B'11110000' ;Set RD<7:4> as inputs
TRISD
;and set RD<3:0> as
;outputs
DS41414A-page 126
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 12-6: PORTB: PORTB REGISTER
R/W-x/u
RB7
R/W-x/u
RB6
R/W-x/u
RB5
R/W-x/u
RB4
R/W-x/u
RB3
R/W-x/u
RB2
R/W-x/u
RB1
R/W-x/u
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RB<7:0>: PORTB I/O Pin bit
1= Port pin is > VIH
0= Port pin is < VIL
REGISTER 12-7: TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
TRISB7
R/W-1/1
TRISB6
R/W-1/1
TRISB5
R/W-1/1
TRISB4
R/W-1/1
TRISB3
R/W-1/1
TRISB2
R/W-1/1
TRISB1
R/W-1/1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISB<7:0>: PORTB Tri-State Control bit
1= PORTB pin configured as an input (tri-stated)
0= PORTB pin configured as an output
REGISTER 12-8: LATB: PORTB DATA LATCH REGISTER
R/W-x/u
LATB7
R/W-x/u
LATB6
R/W-x/u
LATB5
R/W-x/u
LATB4
R/W-x/u
LATB3
R/W-x/u
LATB2
R/W-x/u
LATB1
R/W-x/u
LATB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATB<7:0>: PORTB Output Latch Value bits(1)
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 127
PIC16F/LF1946/47
REGISTER 12-9: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
WPUB7
R/W-1/1
WPUB6
R/W-1/1
WPUB5
R/W-1/1
WPUB4
R/W-1/1
WPUB3
R/W-1/1
WPUB2
R/W-1/1
WPUB1
R/W-1/1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
WPUB<7:0>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
IOCBP6
IOCBN6
IOCBF6
LATB6
SE14
TMR0IE
IOCBP5
IOCBN5
IOCBF5
LATB5
SE13
INTE
IOCBP4
IOCBN4
IOCBF4
LATB4
SE12
IOCIE
IOCBP3
IOCBN3
IOCBF3
LATB3
SE11
TMR0IF
IOCBP2
IOCBN2
IOCBF2
LATB2
SE10
INTF
IOCBP1
IOCBN1
IOCBF1
LATB1
SE9
IOCIF
IOCBP0
IOCBN0
IOCBF0
LATB0
SE8
89
IOCBP
IOCBN
IOCBF
LATB
IOCBP7
IOCBN7
IOCBF7
LATB7
SE15
148
148
148
127
333
333
333
189
127
200
127
128
LCDSE1
LCDSE3
LCDSE4
SE31
SE30
SE29
SE28
SE27
SE26
SE25
SE24
SE39
SE38
SE37
SE36
SE35
SE34
SE33
SE32
OPTION_REG WPUEN
INTEDG
RB6
TMR0CS TMR0SE
PSA
PS<2:0>
RB1
PORTB
T1GCON
TRISB
RB7
RB5
RB4
RB3
RB2
RB0
TMR1GE T1GPOL
T1GTM
TRISB5
WPUB5
T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
TRISB7
WPUB7
TRISB6
WPUB6
TRISB4
WPUB4
TRISB3
WPUB3
TRISB2
WPUB2
TRISB1
WPUB1
TRISB0
WPUB0
WPUB
Legend:
x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
DS41414A-page 128
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
12.4.1
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
12.4 PORTC Registers
PORTC is
a 8-bit wide, bidirectional port. The
Each PORTC pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
corresponding data direction register is TRISC
(Register 12-11). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-3 shows how to initialize PORTC.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
Reading the PORTC register (Register 12-10) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
RC0
1. T1OSO (Timer1 Oscillator)
2. T1CKI (TMR1)
3. SEG40 (ICD)
The TRISC register (Register 12-11) controls the
PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them
as analog inputs. I/O pins configured as analog input
always read ‘0’.
RC1
1. T1OSI (Timer1 Oscillator)
2. CCP2/P2A
3. SEG32 (ICD)
EXAMPLE 12-3:
INITIALIZING PORTC
RC2
BANKSEL PORTC
;
CLRF
BANKSEL LATC
CLRF LATC
BANKSEL TRISC
PORTC
;Init PORTC
;Data Latch
;
;
1. SEG13 (LCD)
2. CCP1/P1A
RC3
MOVLW
MOVWF
B'11110000' ;Set RC<7:4> as inputs
1. SEG17 (LCD)
2. SCL1 (MSSP1)
3. SCK1 (MSSP1)
TRISC
;and set RC<3:0> as
;outputs
RC4
1. SEG16 (LCD)
2. SDA1 (MSSP1)
3. SDI1 (MSSP1)
RC5
1. SEG12 (LCD)
2. SDO1 (MSSP1)
RC6
1. SEG27 (LCD)
2. TX1 (EUSART1)
3. CK2 (EUSART1)
RC7
1. SEG28 (LCD)
2. DT1 (EUSART1)
3. RX1 (EUSART1)
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 129
PIC16F/LF1946/47
REGISTER 12-10: PORTC: PORTC REGISTER
R/W-x/u
RC7
R/W-x/u
RC6
R/W-x/u
RC5
R/W-x/u
RC4
R/W-x/u
RC3
R/W-x/u
RC2
R/W-x/u
RC1
R/W-x/u
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RC<7:0>: PORTC General Purpose I/O Pin bits
1= Port pin is > VIH
0= Port pin is < VIL
REGISTER 12-11: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
TRISC7
R/W-1/1
TRISC6
R/W-1/1
TRISC5
R/W-1/1
TRISC4
R/W-1/1
TRISC3
R/W-1/1
TRISC2
R/W-1/1
TRISC1
R/W-1/1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISC<7:0>: PORTC Tri-State Control bits
1= PORTC pin configured as an input (tri-stated)
0= PORTC pin configured as an output
REGISTER 12-12: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
LATC7
R/W-x/u
LATC6
R/W-x/u
LATC5
R/W-x/u
LATC4
R/W-x/u
LATC3
R/W-x/u
LATC2
R/W-x/u
LATC1
R/W-x/u
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATC<7:0>: PORTC Output Latch Value bits(1)
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
DS41414A-page 130
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3CSEL
P3BSEL
P2DSEL
P2CSEL
P2BSEL
CCP2SEL P1CSEL
P1BSEL
APFCON
LATC
122
130
333
333
333
333
333
LATC7
SE15
SE23
SE31
SE39
—
LATC6
SE14
SE22
SE30
SE38
—
LATC5
SE13
SE21
SE29
SE37
SE45
LATC4
SE12
SE20
SE28
SE36
SE44
LATC3
SE11
SE19
SE27
SE35
SE43
LATC2
SE10
SE18
SE26
SE34
SE42
LATC1
SE9
LATC0
SE8
LCDSE1
LCDSE2
LCDSE3
LCDSE4
LCDSE5
SE17
SE25
SE33
SE41
SE16
SE24
SE32
SE40
PORTC
RC7
RC6
RC5
SREN
SREN
SSPEN
D/A
RC4
CREN
CREN
CKP
P
RC3
RC2
RC1
RC0
RX9D
RX9D
130
299
299
284
283
199
298
298
RC1STA
RC2STA
SSP1CON1
SSP2STAT
T1CON
SPEN
SPEN
WCOL
SMP
RX9
ADDEN
ADDEN
FERR
FERR
OERR
OERR
RX9
SSPOV
CKE
SSPM<3:0>
S
R/W
UA
—
BF
TMR1ON
TX9D
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN T1SYNC
TX1STA
TX2STA
CSRC
CSRC
TX9
TX9
TXEN
TXEN
SYNC
SYNC
BRGH
BRGH
TRMT
TRMT
—
—
TX9D
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
130
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 131
PIC16F/LF1946/47
12.5.1
PORTD FUNCTIONS AND OUTPUT
PRIORITIES
12.5 PORTD Registers
PORTD is
a 8-bit wide, bidirectional port. The
Each PORTD pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
corresponding data direction register is TRISD
(Register 12-13). Setting a TRISD bit (= 1) will make the
corresponding PORTD pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-4 shows how to initialize PORTD.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
Reading the PORTD register (Register 12-13) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATD).
RD0
1. SEG0 (LCD)
2. P2D (CCP)
The TRISD register (Register 12-14) controls the
PORTD pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISD register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
RD1
1. SEG1 (LCD)
2. P2C (CCP)
RD2
EXAMPLE 12-4:
INITIALIZING PORTD
1. P2B (CCP)
2. SEG2 (LCD)
BANKSEL PORTD
;
CLRF
BANKSEL LATD
CLRF LATD
BANKSEL TRISD
PORTD
;Init PORTD
;Data Latch
;
;
RD3
1. SEG3 (LCD)
2. P3C (CCP)
MOVLW
MOVWF
B'11110000' ;Set RD<7:4> as inputs
TRISD
;and set RD<3:0> as
;outputs
RD4
1. SEG4 (LCD)
2. P3D (CCP)
3. SDO2 (SSP2)
RD5
1. SEG5 (LCD)
2. P1C (CCP)
3. SDI2/SDA2 (SSP2)
RD6
1. SEG5 (LCD)
2. P1B (CCP)
3. SCK2/SCL2 (SSP2)
RD7
1. SEG7 (LCD)
2. SS2 (SSP2)
DS41414A-page 132
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 12-13: PORTD: PORTD REGISTER
R/W-x/u
RD7
R/W-x/u
RD6
R/W-x/u
RD5
R/W-x/u
RD4
R/W-x/u
RD3
R/W-x/u
RD2
R/W-x/u
RD1
R/W-x/u
RD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RD<7:0>: PORTD General Purpose I/O Pin bits
1= Port pin is > VIH
0= Port pin is < VIL
REGISTER 12-14: TRISD: PORTD TRI-STATE REGISTER
R/W-1/1
TRISD7
R/W-1/1
TRISD6
R/W-1/1
TRISD5
R/W-1/1
TRISD4
R/W-1/1
TRISD3
R/W-1/1
TRISD2
R/W-1/1
TRISD1
R/W-1/1
TRISD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISD<7:0>: PORTD Tri-State Control bits
1= PORTD pin configured as an input (tri-stated)
0= PORTD pin configured as an output
REGISTER 12-15: LATD: PORTD DATA LATCH REGISTER
R/W-x/u
LATD7
R/W-x/u
LATD6
R/W-x/u
LATD5
R/W-x/u
LATD4
R/W-x/u
LATD3
R/W-x/u
LATD2
R/W-x/u
LATD1
R/W-x/u
LATD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATD<7:0>: PORTD Output Latch Value bits(1)
Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is
return of actual I/O pin values.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 133
PIC16F/LF1946/47
TABLE 12-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Registeron
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3CSEL
P3BSEL
P2DSEL
P2CSEL
P2BSEL CCP2SEL P1CSEL
CCPxM<3:0>
P1BSEL
APFCON
CCPxCON
LATD
122
229
133
329
333
133
133
(1)
PxM<1:0>
DCxB<1:0>
LATD7
LCDEN
SE7
LATD6
SLPEN
SE6
LATD5
WERR
SE5
LATD4
—
LATD3
LATD2
LATD1
LATD0
LCDCON
LCDSE0
PORTD
TRISD
CS<1:0>
LMUX<1:0>
SE4
SE3
RD3
SE2
RD2
SE1
RD1
SE0
RD0
RD7
RD6
RD5
RD4
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
Note 1: Applies to ECCP modules only.
DS41414A-page 134
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
12.6.2
PORTE FUNCTIONS AND OUTPUT
PRIORITIES
12.6 PORTE Registers
PORTE is
a 4-bit wide, bidirectional port. The
Each PORTE pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
‘1’. Example 12-5 shows how to initialize PORTE.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions, such as the EUSART RX
signal, override other port functions and are included in
the priority list.
Reading the PORTE register (Register 12-16) reads
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are
read-modify-write operations. Therefore, a write to a
port implies that the port pins are read, this value is
modified and then written to the PORT data latch
(LATE). RE3 reads ‘0’ when MCLRE = 1.
RE0
1. P2D (CCP)
2. VLCD1 (LCD)
12.6.1
ANSELE REGISTER
RE1
The ANSELE register (Register 12-19) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELE bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
1. P2C (CCP)
2. VLCD2 (LCD)
RE2
1. P2B (CCP)
The state of the ANSELE bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
2. VLCD3 (LCD)
RE3
1. P3C (CCP)
2. COM0 (LCD)
RE4
The TRISE register (Register 12-17) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
1. P3B (CCP)
2. COM1 (LCD)
RE5
1. P1C (CCP)
2. COM32(LCD)
Note:
The ANSELE register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
RE6
1. P1B (CCP)
2. COM3 (LCD)
RE7
EXAMPLE 12-5:
INITIALIZING PORTE
1. CCP2/P2A (CCP)
2. SEG31 (LCD)
BANKSELPORTE
;
CLRF
BANKSEL LATE
CLRF LATE
BANKSELANSELE
CLRF ANSELE
BANKSELTRISE
PORTE
;Init PORTE
;Data Latch
;
;
;digital I/O
;
MOVLW
MOVWF
B‘00001100’ ;Set RE<3:2> as inputs
TRISE
;and set RE<1:0>
;as outputs
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 135
PIC16F/LF1946/47
REGISTER 12-16: PORTE: PORTE REGISTER
R/W-x/u
RE7
R/W-x/u
RE6
R/W-x/u
RE5
R/W-x/u
RE4
R/W-x/u
RE3
R/W-x/u
RE2
R/W-x/u
RE1
R/W-x/u
RE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RE<7:0>: PORTE I/O Pin bits
1= Port pin is > VIH
0= Port pin is < VIL
REGISTER 12-17: TRISE: PORTE TRI-STATE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISE<7:0>: RE<7:0> Tri-State Control bits
1= PORTE pin configured as an input (tri-stated)
0= PORTE pin configured as an output
DS41414A-page 136
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 12-18: LATE: PORTE DATA LATCH REGISTER
R/W-x/u
LATE7
R/W-x/u
LATE6
R/W-x/u
LATE5
R/W-x/u
LATE4
R/W-x/u
LATE3
R/W-x/u
LATE2
R/W-x/u
LATE1
R/W-x/u
LATE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
LATE<7:0>: PORTE Output Latch Value bits(1)
Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of
actual I/O pin values.
REGISTER 12-19: ANSELE: PORTE ANALOG SELECT REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSE7
ANSE6
ANSE5
ANSE4
ANSE3
ANSE2
ANSE1
ANSE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
bit 7-0
ANSE<7:0>: Analog Select between Analog or Digital Function on Pins RE<7:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3CSEL
ANSE7
P3BSEL
P2DSEL
ANSE5
P2CSEL
ANSE4
P2BSEL CCP2SEL
P1CSEL
ANSE1
P1BSEL
ANSE0
APFCON
ANSELE
CCPxCON
LATE
122
137
229
137
329
331
333
ANSE6
ANSE3
LATE3
ANSE2
LATE2
(1)
PxM<1:0>
DCxB<1:0>
CCPxM<3:0>
LATE7
LCDEN
LCDIRE
SE31
LATE6
SLPEN
LCDIRS
SE30
LATE5
WERR
LCDIRI
SE29
LATE4
—
LATE1
LATE0
LCDCON
LCDREF
LCDSE2
PORTE
LMUX<1:0>
CS<1:0>
—
VLCD3PE VLCD2PE VLCD1PE
—
SE28
RE4
SE27
RE3
SE26
RE2
SE25
RE1
SE24
RE0
RE7
RE6
RE5
136
136
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Applies to ECCP modules only.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 137
PIC16F/LF1946/47
12.7 PORTF Registers
PORTF is
a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISF
(Register 12-21). Setting a TRISF bit (= 1) will make the
corresponding PORTF pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISF bit (= 0) will make the corresponding
PORTF pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-4 shows how to initialize PORTF.
Reading the PORTF register (Register 12-13) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATF).
The TRISF register (Register 12-14) controls the
PORTF pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISF register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
12.7.1
ANSELF REGISTER
The ANSELF register (Register 12-23) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELF bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELF bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELF register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
EXAMPLE 12-6:
INITIALIZING PORTF
BANKSEL PORTF
;
CLRF
BANKSEL LATF
CLRF LATF
BANKSEL ANSELF
CLRF ANSELF
BANKSEL TRISF
PORTF
;Init PORTF
;Data Latch
;
;
;digital I/O
;
MOVLW
MOVWF
B'11110000' ;Set RF<7:4> as inputs
TRISF
;and set RF<3:0> as
;outputs
DS41414A-page 138
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
RF5
12.7.2
PORTF FUNCTIONS AND OUTPUT
PRIORITIES
1. AN10 (ADC)
Each PORTF pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
2. CPS10 (CSM)
3. C12IN1- (Comparator)
4. DACOUT (DAC)
5. SEG23 (LCD)
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
RF6
1. AN11 (ADC)
2. CPS11 (CSM)
3. C1IN+ (Comparator)
4. DACOUT (DAC)
5. SEG24 (LCD)
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
RF7
RF0
1. AN5 (ADC)
1. AN16 (ADC)
2. CPS5 (CSM)
2. CPS16 (CSM)
3. C12IN0- (Comparator)
4. SEG41 (LCD)
5. VCAP (LDO)
3. C123IN3- (Comparator)
4. SS1 (MSSP1)
5. SEG25 (LCD)
RF1
1. AN6 (ADC)
2. CPS6 (CSM)
3. C2OUT (Comparator)
4. SRNQ (SR Latch)
5. SEG19 (LCD)
RF2
1. AN7 (ADC)
2. CPS7 (CSM)
3. C1OUT (Comparator)
4. SEG20 (LCD)
5. SRQ (SR Latch)
RF3
1. AN8 (ADC)
2. CPS8 (CSM)
3. C123IN2- (Comparator)
4. SEG21 (LCD)
RF4
1. AN9 (ADC)
2. CPS9 (CSM)
3. C2IN+ (Comparator)
4. SEG22 (LCD)
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 139
PIC16F/LF1946/47
REGISTER 12-20: PORTF: PORTF REGISTER
R/W-x/u
RF7
R/W-x/u
RF6
R/W-x/u
RF5
R/W-x/u
RF4
R/W-x/u
RF3
R/W-x/u
RF2
R/W-x/u
RF1
R/W-x/u
RF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RF<7:0>: PORTF General Purpose I/O Pin bits
1= Port pin is > VIH
0= Port pin is < VIL
REGISTER 12-21: TRISF: PORTF TRI-STATE REGISTER
R/W-1/1
TRISF7
R/W-1/1
TRISF6
R/W-1/1
TRISF5
R/W-1/1
TRISF4
R/W-1/1
TRISF3
R/W-1/1
TRISF2
R/W-1/1
TRISF1
R/W-1/1
TRISF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISF<7:0>: PORTF Tri-State Control bits
1= PORTF pin configured as an input (tri-stated)
0= PORTF pin configured as an output
REGISTER 12-22: LATF: PORTF DATA LATCH REGISTER
R/W-x/u
LATF7
R/W-x/u
LATF6
R/W-x/u
LATF5
R/W-x/u
LATF4
R/W-x/u
LATF3
R/W-x/u
LATF2
R/W-x/u
LATF1
R/W-x/u
LATF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATF<7:0>: PORTF Output Latch Value bits(1)
Note 1: Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return
of actual I/O pin values.
DS41414A-page 140
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 12-23: ANSELF: PORTF ANALOG SELECT REGISTER
R/W-1/1
ANSF7
R/W-1/1
ANSF6
R/W-1/1
ANSF5
R/W-1/1
ANSDF4
R/W-1/1
ANSF3
R/W-1/1
ANSF2
R/W-1/1
ANSDF1
R/W-1/1
ANSF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ANSF<7:0>: Analog Select between Analog or Digital Function on Pins RF<7:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
TABLE 12-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Registeron
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
ADCON0
ANSELF
CCPxCON
CMOUT
—
CHS<4:0>
ANSF4
GO/DONE
ANSF1
ADON
159
141
229
179
179
179
323
324
171
133
329
333
333
333
ANSF7
ANSF6
ANSF5
ANSF3
ANSF2
ANSF0
(1)
PxM<1:0>
DCxB<1:0>
CCPxM<3:0>
MC3OUT MC2OUT MC1OUT
—
—
—
C1PCH1
C2PCH1
—
—
C1PCH0
C2PCH0
—
—
—
—
CM1CON1
CM2CON1
CPSCON0
CPSCON1
DACCON0
LATD
C1INTP
C2INTP
CPSON
—
C1INTN
C2INTN
CPSRM
—
—
C1NCH<1:0>
C2NCH<1:0>
CPSRNG<1:0>
CPSOUT
T0XCS
—
—
—
CPSCH<3:0>
DACEN
LATF7
LCDEN
SE23
DACLPS
LATF6
SLPEN
SE22
DACOE
LATF5
WERR
SE21
SE29
SE45
—
DACPSS<1:0>
LATF3 LATF2
CS<1:0>
SE19
—
DACNSS
LATF0
LATF4
—
LATF1
LCDCON
LCDSE2
LCDSE3
LCDSE5
LMUX<1:0>
SE20
SE28
SE44
SE18
SE26
SE42
SE17
SE25
SE41
SE16
SE24
SE40
SE31
SE30
SE27
SE43
—
—
PORTF
SRCON0
TRISF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
140
183
140
SRLEN
TRISF7
SRCLK2
TRISF6
SRCLK1
TRISF5
SRCLK0
TRISF4
SRQEN
TRISF3
SRNQEN
TRISF2
SRPS
TRISF1
SRPR
TRISF0
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF.
Note 1: Applies to ECCP modules only.
TABLE 12-8: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
—
—
LVP
DEBUG
—
—
—
BORV
—
STVREN
PLLEN
CONFIG2
56
VCAPEN
WRT<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 141
PIC16F/LF1946/47
12.8.2
PORTG FUNCTIONS AND OUTPUT
PRIORITIES
12.8 PORTG Registers
PORTG is
a 8-bit wide, bidirectional port. The
Each PORTG pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
corresponding data direction register is TRISG
(Register 12-25). Setting a TRISG bit (= 1) will make the
corresponding PORTG pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISG bit (= 0) will make the corresponding
PORTG pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-4 shows how to initialize PORTG.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
Reading the PORTG register (Register 12-24) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATG).
RG0
1. CCP3 (CCP)
2. P3A (CCP)
3. SEG42 (LCD)
The TRISG register (Register 12-25) controls the
PORTG pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISG register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
RG1
1. AN15 (ADC)
2. CPS15 (CSM)
3. TX2 (EUSART)
4. CK2 (EUSART)
5. C3OUT (Comparator)
6. SEG43 (LCD)
12.8.1
ANSELG REGISTER
The ANSELG register (Register 12-27) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELG bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
RG2
1. AN14 (ADC)
The state of the ANSELG bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
2. CPS14 (CSM)
3. DT2/RX2 (EUSART)
4. C3IN+ (Comparator)
5. SEG44 (LCD)
RG3
Note:
The ANSELG register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
1. AN13 (ADC)
2. CPS13 (CSM)
3. C3IN0- (Comparator)
4. CCP4 (CCP)
5. P3D (CCP)
EXAMPLE 12-7:
INITIALIZING PORTG
6. SEG45 (LCD)
BANKSEL PORTG
;
RG4
CLRF
BANKSEL LATG
CLRF LATG
BANKSEL ANSELG
CLRF ANSELG
BANKSEL TRISG
PORTG
;Init PORTG
;Data Latch
;
;
;digital I/O
;
1. AN12 (ADC)
2. CPS12 (CSM)
3. C3IN1- (Comparator)
4. CCP5 (CCP)
5. P1D (CCP)
MOVLW
MOVWF
B'11110000' ;Set RG<7:4> as inputs
TRISG
;and set RG<3:0> as
;outputs
6. SEG26 (LCD)
RG5
1. VPP/MCLR (Basic)SEG18 (LCD)
DS41414A-page 142
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 12-24: PORTG: PORTG REGISTER
U-0
—
U-0
—
R/W-x/u
RG5
R/W-x/u
RG4
R/W-x/u
RG3
R/W-x/u
RG2
R/W-x/u
RG1
R/W-x/u
RG0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’.
RG<5:0>: PORTG General Purpose I/O Pin bits
1= Port pin is > VIH
0= Port pin is < VIL
REGISTER 12-25: TRISG: PORTG TRI-STATE REGISTER
U-0
—
U-0
—
R-1/1
R/W-1/1
TRISG4
R/W-1/1
TRISG3
R/W-1/1
TRISG2
R/W-1/1
TRISG1
R/W-1/1
TRISG0
bit 0
TRISG5
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
Unimplemented: Read as ‘0’.
TRISG5: PORTG Tri-State Control bit
This bit (RG5 pin) is an input only and always read as ‘1’.
bit 4-0
TRISG<4:0>: PORTG Tri-State Control bits
1= PORTG pin configured as an input (tri-stated)
0= PORTG pin configured as an output
REGISTER 12-26: LATG: PORTG DATA LATCH REGISTER
U-0
—
U-0
—
R/W-x/u
LATG5
R/W-x/u
LATG4
R/W-x/u
LATG3
R/W-x/u
LATG2
R/W-x/u
LATG1
R/W-x/u
LATG0
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’.
LATG<5:0>: PORTG Output Latch Value bits
Note 1: Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is return of actual
I/O pin values.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 143
PIC16F/LF1946/47
REGISTER 12-27: ANSELG: PORTG ANALOG SELECT REGISTER
U-0
—
U-0
—
U-0
—
R/W-1/1
ANSG4
R/W-1/1
ANSG3
R/W-1/1
ANSG2
R/W-1/1
ANSG1
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
bit 4-1
Unimplemented: Read as ‘0’.
ANSG<4:1>: Analog Select between Analog or Digital Function on Pins RG<4:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 0
Unimplemented: Read as ‘0’.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 12-28: WPUG: WEAK PULL-UP PORTB REGISTER
U-0
—
U-0
—
R/W-1/1
WPUG5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
Unimplemented: Read as ‘0’.
WPUG5: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
bit 4-0
Unimplemented: Read as ‘0’.
Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
DS41414A-page 144
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Registeron
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON0
ANSELG
CCPxCON
CMOUT
—
—
CHS<4:0>
ANSG4
GO/DONE
ANSG1
ADON
—
159
144
229
179
179
179
323
324
143
329
333
—
—
ANSG3
ANSG2
)
(1
PxM<1:0>
DCxB<1:0>
CCPxM<3:0>
MC3OUT MC2OUT MC1OUT
—
—
—
C1PCH1
C2PCH1
—
—
C1PCH0
C2PCH0
—
—
—
—
CM1CON1
CM2CON1
CPSCON0
CPSCON1
LATG
C1INTP
C2INTP
CPSON
—
C1INTN
C2INTN
CPSRM
—
—
C1NCH<1:0>
C2NCH<1:0>
CPSRNG<1:0>
CPSOUT
T0XCS
—
—
—
—
CPSCH<3:0>
—
—
—
LATG4
—
LATG3
LATG2
LATG1
SE41
LCDCON
LCDSE5
LCDEN
SLPEN
WERR
SE45
CS<1:0>
LMUX<1:0>
SE44
SE43
SE42
SE40
—
—
—
—
—
—
—
—
PORTG
TRISG
RG5
RG4
TRISG4
—
RG3
TRISG3
—
RG2
TRISG2
—
RG1
TRISG1
—
RG0
TRISG0
—
143
143
144
TRISG5
WPUG5
WPUG
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Applies to ECCP modules only.
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NOTES:
DS41414A-page 146
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13.3 Interrupt Flags
13.0 INTERRUPT-ON-CHANGE
The IOCBFx bits located in the IOCBF register are
status flags that correspond to the Interrupt-on-change
pins of PORTB. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCBFx bits.
The PORTB pins can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual PORTB pin, or
combination of PORTB pins, can be configured to
generate an interrupt. The interrupt-on-change module
has the following features:
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
13.4 Clearing Interrupt Flags
• Rising and falling edge detection
• Individual pin interrupt flags
The individual status flags, (IOCBFx bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 13-1 is a block diagram of the IOC module.
13.1 Enabling the Module
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
To allow individual PORTB pins to generate an interrupt,
the IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
EXAMPLE 13-1:
13.2 Individual Pin Configuration
MOVLW 0xff
XORWF IOCBF, W
ANDWF IOCBF, F
For each PORTB pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated IOCBPx bit of the IOCBP
register is set. To enable a pin to detect a falling edge,
the associated IOCBNx bit of the IOCBN register is set.
13.5 Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both the IOCBPx bit
and the IOCBNx bit of the IOCBP and IOCBN registers,
respectively.
If an edge is detected while in Sleep mode, the IOCBF
register will be updated prior to the first instruction
executed out of Sleep.
FIGURE 13-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCIE
IOCBFx
IOCBNx
D
Q
From all other IOCBFx
individual pin detectors
CK
R
IOC Interrupt to
CPU Core
RBx
IOCBPx
D
Q
CK
R
Q2 Clock Cycle
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REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER
R/W-0/0
IOCBP7
R/W-0/0
IOCBP6
R/W-0/0
IOCBP5
R/W-0/0
IOCBP4
R/W-0/0
IOCBP3
R/W-0/0
IOCBP2
R/W-0/0
IOCBP1
R/W-0/0
IOCBP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER
R/W-0/0
IOCBN7
R/W-0/0
IOCBN6
R/W-0/0
IOCBN5
R/W-0/0
IOCBN4
R/W-0/0
IOCBN3
R/W-0/0
IOCBN2
R/W-0/0
IOCBN1
R/W-0/0
IOCBN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCBF7
bit 7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
bit 7-0
IOCBF<7:0>: Interrupt-on-Change Flag bits
1= An enabled change was detected on the associated pin.
Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling
edge was detected on RBx.
0= No change was detected, or the user cleared the detected change.
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TABLE 13-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
INTCON
IOCBF
IOCBN
IOCBP
TRISB
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
89
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
148
148
148
127
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.
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NOTES:
DS41414A-page 150
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14.1 Independent Gain Amplifiers
14.0 FIXED VOLTAGE REFERENCE
(FVR)
The output of the FVR supplied to the ADC,
Comparators, and DAC is routed through two
independent programmable gain amplifiers. Each
amplifier can be configured to amplify the reference
voltage by 1x, 2x or 4x, to produce the three possible
voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
ence Section 15.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
• ADC input channel
• ADC positive reference
• Comparator positive input
• Digital-to-Analog Converter (DAC)
• LCD bias generator
The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the DAC and Comparator
module. Reference Section 16.0 “Digital-to-Analog
Converter (DAC) Module” and Section 17.0 “Com-
parator Module” for additional information.
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
14.2 FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 29.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 14-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
X1
X2
X4
FVR BUFFER1
(To ADC Module)
CDAFVR<1:0>
2
X1
X2
X4
FVR BUFFER2
(To Comparators, DAC)
FVR VREF
(To LCD Bias Generator)
+
_
FVREN
FVRRDY
1.024V Fixed
Reference
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REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
FVREN
R-q/q
FVRRDY(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
Reserved
Reserved
CDAFVR<1:0>
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
FVREN: Fixed Voltage Reference Enable bit
0= Fixed Voltage Reference is disabled
1= Fixed Voltage Reference is enabled
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
0= Fixed Voltage Reference output is not ready or not enabled
1= Fixed Voltage Reference output is ready for use
bit 5-4
bit 3-2
Reserved: Read as ‘0’. Maintain these bits clear.
CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit
00= Comparator and DAC Fixed Voltage Reference Peripheral output is off
01= Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V)
10= Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11= Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
bit 1-0
ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit
00= ADC Fixed Voltage Reference Peripheral output is off
01= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
10= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11= ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
Note 1: FVRRDY is always ‘1’ on devices with LDO (PIC16F1946/47).
2: Fixed Voltage Reference output cannot exceed VDD.
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
FVREN
FVRRDY
Reserved Reserved
CDAFVR<1:0>
ADFVR<1:0>
152
Legend:
Shaded cells are not used with the Fixed Voltage Reference.
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approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 15-1 shows the block diagram of the ADC.
15.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 15-1:
ADC BLOCK DIAGRAM
ADNREF = 1
VREF-
ADNREF = 0
VSS
VDD
ADPREF = 00
ADPREF = 11
VREF+
ADPREF = 10
AN0
AN1
00000
00001
00010
00011
00100
00101
AN2
AN3
AN4
AN5
AN6
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
AN7
AN8
ADC
AN9
10
GO/DONE
AN10
AN11
AN12
AN13
AN14
AN15
AN16
0= Left Justify
ADFM
1= Right Justify
ADON
16
ADRESH ADRESL
VSS
11110
11111
DAC
FVR Buffer1
CHS<4:0>
Note:
When ADON = 0, all multiplexer inputs are disconnected.
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15.1.4
CONVERSION CLOCK
15.1 ADC Configuration
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• FOSC/8
• FOSC/16
• FOSC/32
• Result formatting
• FOSC/64
15.1.1
PORT CONFIGURATION
• FRC (dedicated internal oscillator)
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 12.0 “I/O Ports” for more information.
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD
periods as shown in Figure 15-2.
For correct conversion, the appropriate TAD specifica-
tion must be met. Refer to the A/D conversion require-
ments in Section 29.0 “Electrical Specifications” for
more information. Table 15-1 gives examples of
appropriate ADC clock selections.
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input buf-
fer to conduct excess current.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
15.1.2
CHANNEL SELECTION
There are 16 channel selections available:
• AN<13:0> pins
• DAC Output
• FVR (Fixed Voltage Reference) Output
Refer to Section 16.0 “Digital-to-Analog Converter
(DAC) Module” and Section 14.0 “Fixed Voltage
Reference (FVR)” for more information on these chan-
nel selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 15.2
“ADC Operation” for more information.
15.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
• FVR
The ADNREF bit of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
• VREF- pin
• VSS
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more details on the fixed voltage reference.
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TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
Device Frequency (FOSC)
Device Frequency (FOSC)
ADC Clock Period (TAD)
ADC
ADCS<2:0>
Clock Source
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
(2)
(2)
(2)
(2)
(2)
Fosc/2
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
FRC
000
100
001
101
010
110
x11
62.5ns
125 ns
0.5 s
100 ns
200 ns
400 ns
125 ns
250 ns
250 ns
500 ns
500 ns
1.0 s
2.0 s
4.0 s
2.0 s
4.0 s
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
16.0 s
32.0 s
64.0 s
(3)
(3)
(3)
800 ns
1.0 s
800 ns
1.6 s
1.0 s
2.0 s
(3)
8.0 s
(3)
(3)
2.0 s
3.2 s
4.0 s
8.0 s
16.0 s
(1,4)
(1,4)
(1,4)
(1,4)
(1,4)
(1,4)
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
Legend:
Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD
TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5
b7
b6
b4
b1
b0
b9
b8
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
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15.1.5
INTERRUPTS
15.1.6
RESULT FORMATTING
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 15-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEPinstruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
Please refer to Section 15.1.5 “Interrupts” for more
information.
FIGURE 15-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
ADRESL
LSB
(ADFM = 0)
MSB
bit 7
bit 0
bit 0
bit 7
bit 7
bit 0
10-bit A/D Result
Unimplemented: Read as ‘0’
(ADFM = 1)
MSB
LSB
bit 0
bit 7
Unimplemented: Read as ‘0’
10-bit A/D Result
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15.2.4
ADC OPERATION DURING SLEEP
15.2 ADC Operation
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
15.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 15.2.6 “A/D Conver-
sion Procedure”.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
15.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
15.2.5
SPECIAL EVENT TRIGGER
• Update the ADRESH and ADRESL registers with
new conversion result
The Special Event Trigger of the CCPx/ECCPX module
allows periodic ADC measurements without software
intervention. When this trigger occurs, the GO/DONE
bit is set by hardware and the Timer1 counter resets to
zero.
15.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
TABLE 15-2: SPECIAL EVENT TRIGGER
Device
CCPx/ECCPx
PIC16F/LF1946/47
CCP5
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
Refer to Section 22.0 “Capture/Compare/PWM
Modules” for more information.
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15.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 15-1:
A/D CONVERSION
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
;This code block configures the ADC
;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
1. Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
;Conversion start & polling for completion
; are included.
;
• Configure pin as analog (Refer to the ANSEL
register)
BANKSEL
MOVLW
ADCON1
;
B’11110000’ ;Right justify, Frc
;clock
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
MOVWF
BANKSEL
BSF
BANKSEL
BSF
BANKSEL
MOVLW
MOVWF
CALL
ADCON1
TRISA
TRISA,0
ANSEL
ANSEL,0
ADCON0
;Vdd and Vss Vref
;
;Set RA0 to input
;
;Set RA0 to analog
;
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
B’00000001’ ;Select channel AN0
ADCON0
SampleTime
;Turn ADC On
;Acquisiton delay
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2)
BSF
BTFSC
GOTO
BANKSEL
MOVF
MOVWF
BANKSEL
MOVF
ADCON0,ADGO ;Start conversion
ADCON0,ADGO ;Is conversion done?
$-1
ADRESH
;No, test again
;
.
5. Start conversion by setting the GO/DONE bit.
ADRESH,W
RESULTHI
ADRESL
;Read upper 2 bits
;store in GPR space
;
6. Wait for ADC conversion to complete by one of
the following:
ADRESL,W
RESULTLO
;Read lower 8 bits
;Store in GPR space
• Polling the GO/DONE bit
MOVWF
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.3 “A/D Acquisition
Requirements”.
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15.2.7
ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the ADC.
REGISTER 15-1: ADCON0: A/D CONTROL REGISTER 0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADON
CHS<4:0>
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
00000= AN0
00001= AN1
00010= AN2
00011= AN3
00100= AN4
00101= AN5
00110= AN6
00111= AN7
01000= AN8
01001= AN9
01010= AN10
01011= AN11
01100= AN12
01101= AN13
01110= AN14
01111= AN15
10000= AN16
10001= Reserved. No channel connected.
•
•
•
11100= Reserved. No channel connected.
11101= Temp Sense(2)
11110= DAC output(1)
11111=FVR (Fixed Voltage Reference) Buffer 1 Output(2)
GO/DONE: A/D Conversion Status bit
bit 1
bit 0
1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0= A/D conversion completed/not in progress
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information.
2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
2010 Microchip Technology Inc.
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REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
ADCS<2:0>
ADNREF
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000=FOSC/2
001=FOSC/8
010=FOSC/32
011=FRC (clock supplied from a dedicated RC oscillator)
100=FOSC/4
101=FOSC/16
110=FOSC/64
111=FRC (clock supplied from a dedicated RC oscillator)
bit 3
bit 2
Unimplemented: Read as ‘0’
ADNREF: A/D Negative Voltage Reference Configuration bit
0= VREF- is connected to VSS
1= VREF- is connected to external VREF-
bit 1-0
ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits
00= VREF+ is connected to VDD
01= Reserved
10= VREF+ is connected to external VREF+
11= VREF+ is connected to internal fixed voltage reference
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REGISTER 15-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
ADRES<9:2>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 15-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
ADRES<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
Reserved: Do not use.
2010 Microchip Technology Inc.
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REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-2
bit 1-0
Reserved: Do not use.
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 15-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
ADRES<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
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source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 15-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
15.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 15-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor, CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 15-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 15-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + Temperature - 25°C0.05µs/°C
The value for TC can be approximated with the following equations:
1
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED1 – -------------------------- = VCHOLD
2n + 1 – 1
–TC
---------
RC
VAPPLIED 1 – e
= VCHOLD
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
–Tc
--------
RC
1
= VAPPLIED1 – --------------------------
2n + 1 – 1
VAPPLIED 1 – e
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –CHOLDRIC + RSS + RS ln(1/511)
= –10pF1k + 7k + 10k ln(0.001957)
= 1.12µs
Therefore:
TACQ = 2µs + 1.12µs + 50°C- 25°C0.05µs/°C
= 4.42µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
FIGURE 15-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Sampling
Switch
VT 0.6V
SS
RIC 1k
Rss
Rs
(1)
CPIN
5 pF
VA
I LEAKAGE
CHOLD = 10 pF
VSS/VREF-
VT 0.6V
6V
5V
RSS
VDD 4V
3V
Legend:
CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 1011
Sampling Switch
RIC
RSS
SS
VT
= Interconnect Resistance
= Resistance of Sampling Switch
= Sampling Switch
(k)
= Threshold Voltage
Note 1: Refer to Section 29.0 “Electrical Specifications”.
FIGURE 15-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
1 LSB ideal
Full-Scale
Transition
004h
003h
002h
001h
000h
Analog Input Voltage
1 LSB ideal
Zero-Scale
Transition
VREF+
VREF-
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TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
Name
ADCON0
ADCON1
ADRESH
ADRESL
ANSELA
ANSELE
CCP1CON
INTCON
PIE1
Bit 7
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CHS<4:0>
GO/DONE
ADON
159
160
162
162
125
137
229
89
ADFM
ADCS<2:0>
—
ADNREF
ADPREF<1:0>
A/D Result Register High
A/D Result Register Low
—
—
—
—
ANSA5
—
ANSA4
—
ANSA3
—
ANSA2
ANSE2
ANSA1
ANSE1
ANSA0
ANSE0
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
GIE
TMR1GIE
TMR1GIF
TRISA7
TRISB7
—
PEIE
ADIE
TMR0IE
RCIE
INTE
TXIE
IOCIE
SSPIE
SSPIF
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISB2
TRISE2
INTF
IOCIF
TMR2IE
TMR2IF
TRISA1
TRISB1
TRISE1
TMR1IE
TMR1IF
TRISA0
TRISB0
TRISE0
90
PIR1
ADIF
RCIF
TXIF
94
TRISA
TRISA6
TRISB6
—
TRISA5
TRISB5
—
TRISA4
TRISB4
—
TRISA3
TRISB3
TRISE3
124
127
136
152
171
171
TRISB
TRISE
FVRCON
DACCON0
DACCON1
Legend:
FVREN
DACEN
—
FVRRDY
DACLPS
—
Reserved Reserved
CDAFVR<1:0>
DACPSS<1:0>
DACR<4:0>
ADFVR<1:0>
DACOE
—
—
—
DACNSS
x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not
used for ADC module.
2010 Microchip Technology Inc.
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DS41414A-page 165
PIC16F/LF1946/47
NOTES:
DS41414A-page 166
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16.3.1
OUTPUT CLAMPED TO POSITIVE
VOLTAGE SOURCE
16.0 DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The DAC output voltage can be set to VSRC+ with the
least amount of power consumption by performing the
following:
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with the input source,
with 32 selectable output levels.
• Clearing the DACEN bit in the DACCON0 register.
• Setting the DACLPS bit in the DACCON0 register.
The input of the DAC can be connected to:
• External VREF pins
• Configuring the DACPSS bits to the proper
positive source.
• VDD supply voltage
• FVR (Fixed Voltage Reference)
• Configuring the DACR<4:0>x bits to ‘11111’ in
the DACCON1 register.
The output of the DAC can be configured to supply a
reference voltage to the following:
This is also the method used to output the voltage level
from the FVR to an output pin. See Section 16.4 “DAC
Voltage Reference Output” for more information.
• Comparator positive input
• ADC input channel
• DACOUT pin
Reference Figure 16-1 for output clamping examples.
The Digital-to-Analog Converter (DAC) can be enabled
by setting the DACEN bit of the DACCON0 register.
16.3.2
OUTPUT CLAMPED TO NEGATIVE
VOLTAGE SOURCE
The DAC output voltage can be set to VSRC- with the
least amount of power consumption by performing the
following:
16.1 Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels
are set with the DACR<4:0> bits of the DACCON1
register.
• Clearing the DACEN bit in the DACCON0 register.
• Clearing the DACLPS bit in the DACCON0 register.
The DAC output voltage is determined by the following
equations:
• Configuring the DACNSS bits to the proper
negative source.
• Configuring the DACR<4:0> bits to ‘00000’ in the
DACCON1 register.
EQUATION 16-1: DAC OUTPUT VOLTAGE
DACR<4:0>
+ VSRC-
This allows the comparator to detect a zero-crossing
while not consuming additional current through the DAC
module.
VOUT = VSOURCE+ – VSOURCE- ------------------------------
5
2
Note:
VSOURCE+ can equal FVR Buffer 2, VDD or
VREF+. VSOURCE- can equal VSS or VREF-.
Reference Figure 16-1 for output clamping examples.
16.2 Ratiometric Output Level
The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Section 29.0 “Electrical
Specifications”.
16.3 Low-Power Voltage State
In order for the DAC module to consume the least
amount of power, one of the two voltage reference input
sources to the resistor ladder must be disconnected.
Either the positive voltage source, (VSRC+), or the
negative voltage source, (VSRC-) can be disabled.
The negative voltage source is disabled by setting the
DACLPS bit in the DACCON0 register. Clearing the
DACLPS bit in the DACCON0 register disables the
positive voltage source.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 167
PIC16F/LF1946/47
FIGURE 16-1:
OUTPUT VOLTAGE CLAMPING EXAMPLES
Output Clamped to Positive Voltage Source
Output Clamped to Negative Voltage Source
VSRC+
VSRC+
R
R
R
DACR<4:0> = 11111
R
DACEN = 0
DACLPS = 1
DACEN = 0
DACLPS = 0
DAC Voltage Ladder
(see Figure 16-2)
DAC Voltage Ladder
(see Figure 16-2)
R
R
DACR<4:0> = 00000
VSRC-
VSRC-
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16.4 DAC Voltage Reference Output
The DAC can be output to the DACOUT pin by setting
the DACOE bit of the DACCON0 register to ‘1’.
Selecting the DAC reference voltage for output on the
DACOUT pin automatically overrides the digital output
buffer and digital input threshold detector functions of
that pin. Reading the DACOUT pin when it has been
configured for DAC reference voltage output will
always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to DACOUT. Figure 16-3 shows
an example buffering technique.
FIGURE 16-2:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC)
FVR BUFFER2
VSRC+
VDD
DACR<4:0>
5
VREF+
R
R
DACPSS<1:0>
2
R
R
R
DACEN
DACLPS
32
Steps
DAC
(To Comparator and
ADC Modules)
R
R
R
DACOUT
DACOE
DACNSS
VREF-
VSS
VSRC-
2010 Microchip Technology Inc.
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FIGURE 16-3:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module
R
+
–
Buffered DAC Output
DACOUT
Voltage
Reference
Output
Impedance
16.5 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
16.6 Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DACOUT pin.
• The DACR<4:0> range select bits are cleared.
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REGISTER 16-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0
DACEN
R/W-0/0
DACLPS
R/W-0/0
DACOE
U-0
—
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
DACPSS<1:0>
DACNSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
DACEN: DAC Enable bit
1= DAC is enabled
0= DAC is disabled
DACLPS: DAC Low-Power Voltage State Select bit
1= DAC Positive reference source selected
0= DAC Negative reference source selected
bit 5
DACOE: DAC Voltage Output Enable bit
1= DAC voltage level is also an output on the DACOUT pin
0= DAC voltage level is disconnected from the DACOUT pin
bit 4
Unimplemented: Read as ‘0’
bit 3-2
DACPSS<1:0>: DAC Positive Source Select bits
00= VDD
01= VREF+
10= FVR Buffer2 output
11= Reserved, do not use
bit 1
bit 0
Unimplemented: Read as ‘0’
DACNSS: DAC Negative Source Select bits
1= VREF-
0= VSS
REGISTER 16-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
DACR<4:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
DACR<4:0>: DAC Voltage Output Select bits
VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25)) + VSRC-
Note 1: The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
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TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH DAC MODULE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
DACCON0
DACCON1
Legend:
FVREN
DACEN
—
FVRRDY
DACLPS
—
Reserved Reserved
CDAFVR<1:0>
DACPSS<1:0>
DACR<4:0>
ADFVR<1:0>
152
171
171
DACOE
—
—
—
DACNSS
— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC Module.
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FIGURE 17-1:
SINGLE COMPARATOR
17.0 COMPARATOR MODULE
The PIC16F/LF1946/47 devices have three rail-to-rail
comparators, C1, C2 and C3, with input multiplexing.
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
VIN+
VIN-
+
Output
–
VIN-
VIN+
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
Output
• Wake-up from Sleep
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
• Programmable Speed/Power optimization
• PWM shutdown
• Programmable and fixed voltage reference
17.1
Comparator Overview
A single comparator is shown in Figure 17-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
FIGURE 17-2:
COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
CxNCH<1:0>
CxON(1)
2
CxINTP
Interrupt
det
0
CXIN0-
CXIN1-
CXIN2-
CXIN3-
Set CxIF
1
CxINTN
Interrupt
det
MUX
(2)
2
3
CXPOL
CxVN
CxVP
-
CXOUT
To Data Bus
D
Q
Cx(3)
MCXOUT
+
Q1
EN
0
CXIN+
CxHYS
MUX
DAC
1
(2)
CxSP
To ECCP PWM Logic
2
3
FVR Buffer2
CXSYNC
CXOE
CxON
VSS
TRIS bit
CXOUT
CXPCH<1:0>
0
1
2
D
Q
(from Timer1)
T1CLK
To Timer1 or SR Latch
SYNCCXOUT
Note 1:
When CxON = 0, the Comparator will produce a ‘0’ at the output.
When CxON = 0, all multiplexer inputs are disconnected.
Output of comparator can be frozen during debugging.
2:
3:
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17.2.3
COMPARATOR OUTPUT POLARITY
17.2 Comparator Control
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Each comparator has 2 control registers: CMxCON0 and
CMxCON1.
The CMxCON0 registers (see Register 17-1) contain
Control and Status bits for the following:
• Enable
Table 17-1 shows the output state versus input
conditions, including polarity control.
• Output selection
• Output polarity
TABLE 17-1: COMPARATOR OUTPUT
STATE VS. INPUT
• Speed/Power selection
• Hysteresis enable
• Output synchronization
CONDITIONS
Input Condition
CxPOL
CxOUT
The CMxCON1 registers (see Register 17-2) contain
Control bits for the following:
CxVN > CxVP
CxVN < CxVP
CxVN > CxVP
CxVN < CxVP
0
0
1
1
0
1
0
1
• Interrupt enable
• Interrupt edge polarity
• Positive input channel selection
• Negative input channel selection
17.2.4
COMPARATOR SPEED/POWER
SELECTION
17.2.1
COMPARATOR ENABLE
The trade-off between speed or power can be opti-
mized during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propaga-
tion delay by clearing the CxSP bit to ‘0’.
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
17.2.2
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit of the CMxCON0 register
overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
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17.3 Comparator Hysteresis
17.5 Comparator Interrupt
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a Falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
These hysteresis levels change as a function of the
comparator’s Speed/Power mode selection.
Table 17-2 shows the hysteresis levels.
To enable the interrupt, you must set the following bits:
• CxON, CxPOL and CxSP bits of the CMxCON0
register
TABLE 17-2: HYSTERESIS LEVELS
CxSP
CxHYS Enabled CxHYS Disabled
• CxIE bit of the PIE2 register
0
1
± 3mV
<< ± 1mV
± 3mV
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
± 20mV
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
These levels are approximate.
See Section 29.0 “Electrical Specifications” for
more information.
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
17.4 Timer1 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 20.6 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
Note:
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching the
comparator on or off with the CxON bit of
the CMxCON0 register.
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.
17.6 Comparator Positive Input
Selection
17.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
Configuring the CxPCH<1:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
The output from a comparator can be synchronized
with Timer1 by setting the CxSYNC bit of the
CMxCON0 register.
• CxIN+ analog pin
• DAC
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 17-2) and the Timer1 Block
Diagram (Figure 20-1) for more information.
• FVR (Fixed Voltage Reference)
• VSS (Ground)
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 16.0 “Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
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17.7 Comparator Negative Input
Selection
17.10 Analog Input Connection
Considerations
The CxNCH<1:0> bits of the CMxCON0 register direct
one of four analog pins to the comparator inverting
input.
A simplified circuit for an analog input is shown in
Figure 17-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
Note:
To use CxIN+ and CxINx- pins as analog
input, the appropriate bits must be set in
the ANSEL register and the corresponding
TRIS bits must also be set to disable the
output drivers.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
17.8 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage
Reference Specifications in Section 29.0 “Electrical
Specifications” for more details.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
17.9 Interaction with ECCP Logic
The comparators can be used as general purpose
comparators. Their outputs can be brought out to the
pins. When the ECCP Auto-Shutdown is active it can
use one or both comparator signals. If auto-restart is
also enabled, the comparators can be configured as a
closed loop analog feedback to the ECCP, thereby,
creating an analog controlled PWM.
FIGURE 17-3:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
VT 0.6V
RIC
Rs < 10K
To Comparator
(1)
ILEAKAGE
CPIN
5 pF
VA
VT 0.6V
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
VT
= Threshold Voltage
Note 1: See Section 29.0 “Electrical Specifications”.
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REGISTER 17-1: CMxCON0: COMPARATOR X CONTROL REGISTER 0
R/W-0/0
CxON
R-0/0
R/W-0/0
CxOE
R/W-0/0
CxPOL
U-0
—
R/W-1/1
CxSP
R/W-0/0
CxHYS
R/W-0/0
CxSYNC
CxOUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
CxON: Comparator Enable bit
1= Comparator is enabled and consumes no active power
0= Comparator is disabled
CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1= CxVP < CxVN
0= CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1= CxVP > CxVN
0= CxVP < CxVN
bit 5
bit 4
CxOE: Comparator Output Enable bit
1= CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0= CxOUT is internal only
CxPOL: Comparator Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
bit 3
bit 2
Unimplemented: Read as ‘0’
CxSP: Comparator Speed/Power Select bit
1= Comparator operates in normal power, higher speed mode
0= Comparator operates in low-power, low-speed mode
bit 1
bit 0
CxHYS: Comparator Hysteresis Enable bit
1= Comparator hysteresis enabled
0= Comparator hysteresis disabled
CxSYNC: Comparator Output Synchronous Mode bit
1= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0= Comparator output to Timer1 and I/O pin is asynchronous
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REGISTER 17-2: CMxCON1: COMPARATOR CX CONTROL REGISTER 1
R/W-0/0
CxINTP
R/W-0/0
CxINTN
R/W-0/0
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
CxPCH<1:0>
CxNCH<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CxINTP: Comparator Interrupt on Positive Going Edge Enable bit
1= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0= No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6
CxINTN: Comparator Interrupt on Negative Going Edge Enable bit
1= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0= No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4
CxPCH<1:0>: Comparator Positive Input Channel Select bits
00= CxVP connects to CxIN+ pin
01= CxVP connects to DAC Voltage Reference
10= CxVP connects to FVR Voltage Reference
11= CxVP connects to VSS
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
CxNCH<1:0>: Comparator Negative Input Channel Select bits
00= CxVN connects to CxIN0- pin
01= CxVN connects to CxIN1- pin
10= CxVN connects to CxIN2- pin
11= CxVN connects to CxIN3- pin
REGISTER 17-3: CMOUT: COMPARATOR OUTPUT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0/0
R-0/0
R-0/0
MC3OUT
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-3
bit 2
Unimplemented: Read as ‘0’
MC3OUT: Mirror Copy of C3OUT bit
MC2OUT: Mirror Copy of C2OUT bit
MC1OUT: Mirror Copy of C1OUT bit
bit 1
bit 0
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TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELF
ANSELG
CM1CON0
CM2CON0
CM1CON1
CM2CON1
CM3CON0
CM3CON1
CMOUT
ANSF7
—
ANSF6
—
ANSF5
ANSG5
C1OE
ANSF4
ANSG4
C1POL
C2POL
ANSF3
ANSG3
—
ANSF2
ANSG2
C1SP
C2SP
—
ANSF1
ANSG1
C1HYS
C2HYS
ANSF0
ANSG0
141
144
178
178
179
179
178
179
179
152
171
171
89
C1ON
C2ON
C1NTP
C2NTP
C3ON
C3INTP
—
C1OUT
C2OUT
C1INTN
C2INTN
C3OUT
C3INTN
—
C1SYNC
C2SYNC
C2OE
—
C1PCH<1:0>
C2PCH<1:0>
—
C1NCH<1:0>
C2NCH<1:0>
C3HYS C3SYNC
—
—
C3OE
C3POL
C3PCH0
—
—
C3SP
—
C3PCH1
—
—
C3NCH<1:0>
MC2OUT MC1OUT
ADFVR<1:0>
—
—
FVRCON
DACCON0
DACCON1
INTCON
PIE2
FVREN
DACEN
—
FVRRDY
DACLPS
—
Reserved Reserved
CDAFVR<1:0>
DACPSS<1:0>
DACR<4:0>
DACOE
—
—
—
DACNSS
GIE
PEIE
TMR0IE
C1IE
INTE
EEIE
IOCIE
BCLIE
TMR0IF
LCDIE
INTF
—
IOCIF
OSFIE
OSFIF
TRISF7
—
C2IE
CCP2IE
CCP2IF
TRISF0
TRISG0
91
PIR2
C2IF
C1IF
EEIF
BCLIF
LCDIF
—
95
TRISF
TRISF6
—
TRISF5
TRISG5
TRISF4
TRISG4
TRISF3
TRISG3
TRISF2
TRISG2
TRISF1
TRISG1
140
143
TRISG
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are unused by the Comparator module.
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18.2 Latch Output
18.0 SR LATCH
The SRQEN and SRNQEN bits of the SRCON0 regis-
ter control the Q and Q latch outputs. Both of the SR
Latch outputs may be directly output to an I/O pin at the
same time.
The module consists of a single SR Latch with multiple
Set and Reset inputs as well as separate latch outputs.
The SR Latch module includes the following features:
• Programmable input selection
• SR Latch output is available externally
• Separate Q and Q outputs
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
• Firmware Set and Reset
18.3 Effects of a Reset
The SR Latch can be used in a variety of analog appli-
cations, including oscillator circuits, one-shot circuit,
hysteretic controllers, and analog timing applications.
Upon any device Reset, the SR Latch output is not ini-
tialized to a known state. The user’s firmware is
responsible for initializing the latch output before
enabling the output pins.
18.1 Latch Operation
The latch is a Set-Reset Latch that does not depend on
a clock source. Each of the Set and Reset inputs are
active-high. The latch can be Set or Reset by:
• Software control (SRPS and SRPR bits)
• Comparator C1 output (SYNCC1OUT)
• Comparator C2 output (SYNCC2OUT)
• SRI pin
• Programmable clock (SRCLK)
The SRPS and the SRPR bits of the SRCON0 register
may be used to Set or Reset the SR Latch, respec-
tively. The latch is Reset-dominant. Therefore, if both
Set and Reset inputs are high, the latch will go to the
Reset state. Both the SRPS and SRPR bits are self
resetting which means that a single write to either of the
bits is all that is necessary to complete a latch Set or
Reset operation.
The output from Comparator C1 or C2 can be used as
the Set or Reset inputs of the SR Latch. The output of
either Comparator can be synchronized to the Timer1
clock source. See Section 17.0 “Comparator Mod-
ule” and Section 20.0 “Timer1 Module with Gate
Control” for more information.
An external source on the SRI pin can be used as the
Set or Reset inputs of the SR Latch.
An internal clock source is available that can periodically
set or reset the SR Latch. The SRCLK<2:0> bits in the
SRCON0 register are used to select the clock source
period. The SRSCKE and SRRCKE bits of the SRCON1
register enable the clock source to Set or Reset the SR
Latch, respectively.
Note:
Enabling both the Set and Reset inputs
from any one source at the same time may
result in indeterminate operation, as the
Reset dominance cannot be assured.
2010 Microchip Technology Inc.
Preliminary
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FIGURE 18-1:
SR LATCH SIMPLIFIED BLOCK DIAGRAM
SRLEN
SRQEN
SRPS
Pulse
(2)
Gen
SRI
S
Q
SRSPE
SRCLK
SRQ
SRSCKE
(3)
SYNCC2OUT
SRSC2E
(3)
SYNCC1OUT
SRSC1E
SR
(1)
Latch
SRPR
Pulse
(2)
Gen
SRI
SRRPE
SRCLK
R
Q
SRNQ
SRRCKE
SRLEN
(3)
SYNCC2OUT
SRNQEN
SRRC2E
(3)
SYNCC1OUT
SRRC1E
Note 1: If R = 1and S = 1simultaneously, Q = 0, Q = 1.
2: Pulse generator causes a 1 Q-state pulse width.
3: Name denotes the connection point at the comparator output.
DS41414A-page 182
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TABLE 18-1: SRCLK FREQUENCY TABLE
SRCLK
Divider
FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz
FOSC = 1 MHz
111
110
101
100
011
010
001
000
512
256
128
64
32
16
8
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
39.0 kHz
78.1 kHz
156 kHz
313 kHz
625 kHz
1.25 MHz
2.5 MHz
5 MHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
7.81 kHz
15.6 kHz
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
1.95 kHz
3.90 kHz
7.81 kHz
15.6 kHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
2 MHz
4 MHz
2 MHz
4
8 MHz
4 MHz
REGISTER 18-1: SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0
SRLEN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SRQEN
R/W-0/0
R/S-0/0
SRPS
R/S-0/0
SRPR
bit 0
SRCLK<2:0>
SRNQEN
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit is set only
bit 7
SRLEN: SR Latch Enable bit
1= SR Latch is enabled
0= SR Latch is disabled
SRCLK<2:0>: SR Latch Clock Divider bits
bit 6-4
000= Generates a 1 FOSC wide pulse every 4th FOSC cycle clock
001= Generates a 1 FOSC wide pulse every 8th FOSC cycle clock
010= Generates a 1 FOSC wide pulse every 16th FOSC cycle clock
011= Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock
100= Generates a 1 FOSC wide pulse every 64th FOSC cycle clock
101= Generates a 1 FOSC wide pulse every 128th FOSC cycle clock
110= Generates a 1 FOSC wide pulse every 256th FOSC cycle clock
111= Generates a 1 FOSC wide pulse every 512th FOSC cycle clock
bit 3
bit 2
SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1= Q is present on the SRQ pin
0= External Q output is disabled
If SRLEN = 0:
SR Latch is disabled
SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1= Q is present on the SRnQ pin
0= External Q output is disabled
If SRLEN = 0:
SR Latch is disabled
bit 1
bit 0
SRPS: Pulse Set Input of the SR Latch bit(1)
1= Pulse set input for 1 Q-clock period
0= No effect on set input
SRPR: Pulse Reset Input of the SR Latch bit(1)
1= Pulse reset input for 1 Q-clock period
0= No effect on reset input
Note 1: Set only, always reads back ‘0’.
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER
R/W-0/0
SRSPE
R/W-0/0
R/W-0/0
SRSC2E
R/W-0/0
SRSC1E
R/W-0/0
SRRPE
R/W-0/0
R/W-0/0
R/W-0/0
SRSCKE
SRRCKE
SRRC2E
SRRC1E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRSPE: SR Latch Peripheral Set Enable bit
1= SR Latch is set when the SRI pin is high
0= SRI pin has no effect on the set input of the SR Latch
SRSCKE: SR Latch Set Clock Enable bit
1= Set input of SR Latch is pulsed with SRCLK
0= SRCLK has no effect on the set input of the SR Latch
SRSC2E: SR Latch C2 Set Enable bit
1= SR Latch is set when the C2 Comparator output is high
0= C2 Comparator output has no effect on the set input of the SR Latch
SRSC1E: SR Latch C1 Set Enable bit
1= SR Latch is set when the C1 Comparator output is high
0= C1 Comparator output has no effect on the set input of the SR Latch
SRRPE: SR Latch Peripheral Reset Enable bit
1= SR Latch is reset when the SRI pin is high
0= SRI pin has no effect on the reset input of the SR Latch
SRRCKE: SR Latch Reset Clock Enable bit
1= Reset input of SR Latch is pulsed with SRCLK
0= SRCLK has no effect on the reset input of the SR Latch
SRRC2E: SR Latch C2 Reset Enable bit
1= SR Latch is reset when the C2 Comparator output is high
0= C2 Comparator output has no effect on the reset input of the SR Latch
SRRC1E: SR Latch C1 Reset Enable bit
1= SR Latch is reset when the C1 Comparator output is high
0= C1 Comparator output has no effect on the reset input of the SR Latch
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TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
SRCON0
SRCON1
TRISA
—
—
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
SRPS
ANSA0
SRPR
125
183
184
124
SRLEN
SRSPE
TRISA7
SRCLK<2:0>
SRQEN SRNQEN
SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E
TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the SR Latch module.
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NOTES:
DS41414A-page 186
Preliminary
2010 Microchip Technology Inc.
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When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
19.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
Note:
The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
19.1.2
8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin or the
Capacitive Sensing Oscillator (CPSCLK) signal.
• TMR0 can be used to gate Timer1
Figure 19-1 is a block diagram of the Timer0 module.
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION register to ‘1’
and resetting the T0XCS bit in the CPSCON0 register to
‘0’.
19.1 Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
8-Bit Counter mode using the Capacitive Sensing
Oscillator (CPSCLK) signal is selected by setting the
TMR0CS bit in the OPTION register to ‘1’ and setting
the T0XCS bit in the CPSCON0 register to ‘1’.
19.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the OPTION
register.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION register.
FIGURE 19-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
1
8
T0CKI
1
Sync
0
1
TMR0
2 TCY
0
Set Flag bit TMR0IF
From CPSCLK
on Overflow
TMR0CS
TMR0SE
8-bit
Prescaler
PSA
Overflow to Timer1
T0XCS
8
PS<2:0>
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PIC16F/LF1946/47
19.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be disabled by setting the
PSA bit of the OPTION register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
19.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
19.1.5
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 29.0 “Electrical
Specifications”.
19.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
DS41414A-page 188
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REGISTER 19-1: OPTION_REG: OPTION REGISTER
R/W-1/1
WPUEN
R/W-1/1
INTEDG
R/W-1/1
R/W-1/1
R/W-1/1
PSA
R/W-1/1
R/W-1/1
PS<2:0>
R/W-1/1
bit 0
TMR0CS
TMR0SE
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-up Enable bit
1= All weak pull-ups are disabled (except MCLR, if it is enabled)
0= Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
TMR0CS: Timer0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
TMR0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is not assigned to the Timer0 module
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPSCON0
INTCON
CPSON CPSRM
GIE PEIE
—
—
CPSRNG<1:0>
CPSOUT T0XCS
323
89
TMR0IE
INTE
IOCIE
PSA
TMR0IF
INTF
IOCIF
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
PS<2:0>
189
187*
124
TMR0
TRISA
Timer0 Module Register
TRISA7 TRISA6 TRISA5 TRISA4
TRISA3
TRISA2
TRISA1 TRISA0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 189
PIC16F/LF1946/47
NOTES:
DS41414A-page 190
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
• Gate Toggle Mode
20.0 TIMER1 MODULE WITH GATE
CONTROL
• Gate Single-pulse Mode
• Gate Value Status
The Timer1 module is a 16-bit timer/counter with the
following features:
• Gate Event Interrupt
Figure 20-1 is a block diagram of the Timer1 module.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Dedicated 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP/ECCP)
• Selectable Gate Source Polarity
FIGURE 20-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1G
T1GSPM
00
From Timer0
Overflow
0
01
10
11
T1G_IN
D
Data Bus
T1GVAL
0
1
D
Q
Comparator 1
SYNCC1OUT
Single Pulse
Acq. Control
RD
1
T1GCON
Q1 EN
Q
Q
Comparator 2
SYNCC2OUT
Interrupt
Set
T1GGO/DONE
CK
R
TMR1ON
T1GTM
TMR1GIF
det
T1GPOL
TMR1GE
Set flag bit
TMR1IF on
Overflow
TMR1ON
To Comparator Module
TMR1(2)
EN
D
Synchronized
clock input
0
T1CLK
TMR1H
TMR1L
Q
1
TMR1CS<1:0>
T1SYNC
T1OSO
OUT
Cap. Sensing
Oscillator
11
10
Synchronize(3)
det
T1OSC
EN
Prescaler
1, 2, 4, 8
1
0
T1OSI
2
T1CKPS<1:0>
FOSC
Internal
Clock
01
00
FOSC/2
Internal
Clock
T1OSCEN
T1CKI
Sleep input
FOSC/4
Internal
Clock
(1)
To LCD and Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
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Preliminary
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20.1 Timer1 Operation
20.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> and T1OSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Table 20-2 displays the clock source selections.
20.2.1
INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and incre-
ments on every selected edge of the external source.
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 20-1 displays the Timer1 enable
selections.
TABLE 20-1: TIMER1 ENABLE
SELECTIONS
The following asynchronous sources may be used:
• Asynchronous event on the T1G pin to Timer1
Gate
Timer1
Operation
TMR1ON
TMR1GE
• C1 or C2 comparator input to Timer1 Gate
0
0
1
1
0
1
0
1
Off
Off
20.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
Always On
Count Enabled
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI or the
capacitive sensing oscillator signal. Either of these
external clock sources can be synchronized to the
microcontroller system clock or they can run
asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 20-2: CLOCK SOURCE SELECTIONS
TMR1CS1
TMR1CS0
T1OSCEN
Clock Source
0
0
1
1
1
1
0
1
0
0
x
x
x
0
1
System Clock (FOSC)
Instruction Clock (FOSC/4)
Capacitive Sensing Oscillator
External Clocking on T1CKI Pin
Osc.Circuit On T1OSI/T1OSO Pins
DS41414A-page 192
Preliminary
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20.3 Timer1 Prescaler
20.6 Timer1 Gate
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 Gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 Gate can also be driven by multiple selectable
sources.
20.6.1
TIMER1 GATE ENABLE
20.4 Timer1 Oscillator
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins T1OSI (input) and T1OSO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 20-3 for timing details.
The oscillator circuit is enabled by setting the
T1OSCEN bit of the T1CON register. The oscillator will
continue to run during Sleep.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
TABLE 20-3: TIMER1 GATE ENABLE
SELECTIONS
T1CLK T1GPOL
T1G
Timer1 Operation
20.5 Timer1 Operation in
Asynchronous Counter Mode
0
0
1
1
0
1
0
1
Counts
Holds Count
Holds Count
Counts
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 20.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
20.6.2
TIMER1 GATE SOURCE
SELECTION
The Timer1 Gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
TABLE 20-4: TIMER1 GATE SOURCES
T1GSS
Timer1 Gate Source
Timer1 Gate Pin
00
01
Overflow of Timer0
20.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
(TMR0 increments from FFh to 00h)
10
11
Comparator 1 Output SYNCC1OUT
(optionally Timer1 synchronized output)
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
Comparator 2 Output SYNCC2OUT
(optionally Timer1 synchronized output)
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
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20.6.2.1
T1G Pin Gate Operation
20.6.4
TIMER1 GATE SINGLE-PULSE
MODE
The T1G pin is one source for Timer1 Gate Control. It
can be used to supply an external source to the Timer1
Gate circuitry.
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software.
20.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h,
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 Gate circuitry.
a
20.6.2.3
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 Gate Control. The
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/DONE bit. See Figure 20-5 for
timing details.
Comparator
1
output (SYNCC1OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 17.4.1 “Comparator
Output Synchronization”.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
Gate source to be measured. See Figure 20-6 for
timing details.
20.6.2.4
Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 Gate Control.
The Comparator 2 output (SYNCC2OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 17.4.1 “Comparator
Output Synchronization”.
20.6.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
20.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
20.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is pos-
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 20-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
Note:
Enabling Toggle mode at the same time as
changing the gate polarity may result in
indeterminate operation.
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Preliminary
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20.7 Timer1 Interrupt
20.9 ECCP/CCP Capture/Compare Time
Base
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
For
more
information,
see
Section 22.0
Note:
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
“Capture/Compare/PWM Modules”.
20.10 ECCP/CCP Special Event Trigger
When any of the CCP’s are configured to trigger a spe-
cial event, the trigger will clear the TMR1H:TMR1L reg-
ister pair. This special event does not cause a Timer1
interrupt. The CCP module may still be configured to
generate a CCP interrupt.
20.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
Timer1 should be synchronized and FOSC/4 should be
selected as the clock source in order to utilize the Spe-
cial Event Trigger. Asynchronous operation of Timer1
can cause a Special Event Trigger to be missed.
• TMR1CS bits of the T1CON register must be
configured
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
• T1OSCEN bit of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
For more information, see Section 15.2.5 “Special
Event Trigger”.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 20-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
2010 Microchip Technology Inc.
Preliminary
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PIC16F/LF1946/47
FIGURE 20-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TIMER1
N
N + 1
N + 2
N + 3
N + 4
FIGURE 20-4:
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1
N
N + 1 N + 2 N + 3 N + 4
N + 5 N + 6 N + 7 N + 8
DS41414A-page 196
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 20-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
N
N + 1
N + 2
Cleared by
software
Set by hardware on
falling edge of T1GVAL
Cleared by software
TMR1GIF
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 197
PIC16F/LF1946/47
FIGURE 20-6:
TMR1GE
T1GPOL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1GSPM
T1GTM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
N + 4
N + 2 N + 3
N
N + 1
Set by hardware on
falling edge of T1GVAL
Cleared by
software
Cleared by software
TMR1GIF
DS41414A-page 198
Preliminary
2010 Microchip Technology Inc.
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20.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 20-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 20-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
T1SYNC
U-0
—
R/W-0/u
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
11=Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)
10=Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
01=Timer1 clock source is system clock (FOSC)
00=Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: LP Oscillator Enable Control bit
1= Dedicated Timer1 oscillator circuit enabled
0= Dedicated Timer1 oscillator circuit disabled
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X
1= Do not synchronize external clock input
0= Synchronize external clock input with system clock (FOSC)
TMR1CS<1:0> = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Clears Timer1 Gate flip-flop
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
20.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 20-2, is used to control Timer1 Gate.
REGISTER 20-2: T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
T1GPOL
R/W-0/u
T1GTM
R/W-0/u
R/W/HC-0/u
R-x/x
R/W-0/u
R/W-0/u
TMR1GE
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1= Timer1 counting is controlled by the Timer1 gate function
0= Timer1 counts regardless of Timer1 gate function
bit 6
bit 5
T1GPOL: Timer1 Gate Polarity bit
1= Timer1 gate is active-high (Timer1 counts when gate is high)
0= Timer1 gate is active-low (Timer1 counts when gate is low)
T1GTM: Timer1 Gate Toggle Mode bit
1= Timer1 Gate Toggle mode is enabled
0= Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
bit 3
T1GSPM: Timer1 Gate Single-Pulse Mode bit
1= Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0= Timer1 gate Single-Pulse mode is disabled
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1= Timer1 gate single-pulse acquisition is ready, waiting for an edge
0= Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits
00= Timer1 Gate pin
01= Timer0 overflow output
10= Comparator 1 optionally synchronized output (SYNCC1OUT)
11= Comparator 2 optionally synchronized output (SYNCC2OUT)
DS41414A-page 200
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 20-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP1CON
CCP2CON
INTCON
PIE1
P1M<1:0>
P2M<1:0>
GIE
DC1B<1:0>
DC2B<1:0>
CCP1M<3:0>
CCP2M<3:0>
229
229
89
PEIE
ADIE
ADIF
TMR0IE
INTE
TXIE
TXIF
IOCIE
SSPIE
SSPIF
TMR0IF
INTF
IOCIF
TMR1IE
TMR1IF
TMR1GIE
TMR1GIF
RCIE
RCIF
CCP1IE
CCP1IF
TMR2IE
TMR2IF
90
PIR1
94
TMR1H
TMR1L
TRISB
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
195*
195*
127
130
199
200
TRISB7
TRISC7
TRISB6
TRISC6
TRISB5
TRISC5
TRISB4
TRISC4
TRISB3
TRISC3
TRISB2
TRISC2
T1SYNC
T1GVAL
TRISB1
TRISC1
—
TRISB0
TRISC0
TMR1ON
TRISC
T1CON
T1GCON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GSS<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
*
Page provides register information.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 201
PIC16F/LF1946/47
NOTES:
DS41414A-page 202
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
21.0 TIMER2/4/6 MODULES
There are up to three identical Timer2-type modules
available. To maintain pre-existing naming conventions,
the Timers are called Timer2, Timer4 and Timer6 (also
Timer2/4/6).
Note:
The ‘x’ variable used in this section is used
to designate Timer2, Timer4, or Timer6.
For example, TxCON references T2CON,
T4CON or T6CON. PRx references PR2,
PR4 or PR6.
The Timer2/4/6 modules incorporate the following
features:
• 8-bit Timer and Period registers (TMRx and PRx,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMRx match with PRx, respectively
• Optional use as the shift clock for the MSSPx
modules (Timer2 only)
See Figure 21-1 for a block diagram of Timer2/4/6.
FIGURE 21-1:
TIMER2/4/6 BLOCK DIAGRAM
Sets Flag
bit TMRxIF
TMRx
Output
Prescaler
TMRx
Reset
EQ
FOSC/4
1:1, 1:4, 1:16, 1:64
Postscaler
1:1 to 1:16
2
Comparator
TxCKPS<1:0>
PRx
4
TxOUTPS<3:0>
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 203
PIC16F/LF1946/47
21.1 Timer2/4/6 Operation
21.3 Timer2/4/6 Output
The clock input to the Timer2/4/6 modules is the
system instruction clock (FOSC/4).
The unscaled output of TMRx is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
TMRx increments from 00h on each clock edge.
Timer2 can be optionally used as the shift clock source
for the MSSPx modules operating in SPI mode.
Additional information is provided in Section 23.0
“Master Synchronous Serial Port (MSSP1 and
MSSP2) Module”.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
TxCKPS<1:0> of the TxCON register. The value of
TMRx is compared to that of the Period register, PRx, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMRx to 00h
on the next cycle and drives the output
counter/postscaler (see Section 21.2 “Timer2/4/6
Interrupt”).
21.4 Timer2/4/6 Operation During Sleep
The Timer2/4/6 timers cannot be operated while the
processor is in Sleep mode. The contents of the TMRx
and PRx registers will remain unchanged while the
processor is in Sleep mode.
The TMRx and PRx registers are both directly readable
and writable. The TMRx register is cleared on any
device Reset, whereas the PRx register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMRx register
• a write to the TxCON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESETInstruction
Note:
TMRx is not cleared when TxCON is written.
21.2 Timer2/4/6 Interrupt
Timer2/4/6 can also generate an optional device
interrupt. The Timer2/4/6 output signal (TMRx-to-PRx
match)
provides
the
input
for
the
4-bit
counter/postscaler. This counter generates the TMRx
match interrupt flag which is latched in TMRxIF of the
PIRx register. The interrupt is enabled by setting the
TMRx Match Interrupt Enable bit, TMRxIE of the PIEx
register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, TxOUTPS<3:0>, of the TxCON register.
DS41414A-page 204
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 21-1: TXCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TOUTPS<3:0>
TMRxON
TxCKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS<3:0>: Timer Output Postscaler Select bits
0000= 1:1 Postscaler
0001= 1:2 Postscaler
0010= 1:3 Postscaler
0011= 1:4 Postscaler
0100= 1:5 Postscaler
0101= 1:6 Postscaler
0110= 1:7 Postscaler
0111= 1:8 Postscaler
1000= 1:9 Postscaler
1001= 1:10 Postscaler
1010= 1:11 Postscaler
1011= 1:12 Postscaler
1100= 1:13 Postscaler
1101= 1:14 Postscaler
1110= 1:15 Postscaler
1111= 1:16 Postscaler
bit 2
TMRxON: Timerx On bit
1= Timerx is on
0= Timerx is off
bit 1-0
TxCKPS<1:0>: Timer2-type Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
10= Prescaler is 16
11= Prescaler is 64
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 205
PIC16F/LF1946/47
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP2CON
INTCON
PIE1
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
229
89
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
TMR1GIE
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE
TMR1IE
—
90
PIE3
CCP5IE
CCP4IE
CCP3IE
TMR6IE
—
TMR4IE
92
PIR1
TMR1GIF
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
—
TMR2IF
TMR4IF
TMR1IF
—
94
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR6IF
96
PR2
Timer2 Module Period Register
Timer4 Module Period Register
Timer6 Module Period Register
203*
203*
203*
205
205
205
203*
203*
203*
PR4
PR6
T2CON
T4CON
T6CON
TMR2
TMR4
TMR6
—
—
—
TOUTPS<3:0>
TOUTPS<3:0>
TOUTPS<3:0>
TMR2ON
TMR4ON
TMR6ON
T2CKPS<1:0>
T4CKPS<1:0>
T6CKPS<1:0>
Holding Register for the 8-bit TMR2 Register
Holding Register for the 8-bit TMR4 Register(1)
Holding Register for the 8-bit TMR6 Register(1)
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
Page provides register information.
*
DS41414A-page 206
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
22.0 CAPTURE/COMPARE/PWM
MODULES
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows
the timing of the duration of an event. The Compare
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The
PWM mode can generate Pulse-Width Modulated
signals of varying frequency and duty cycle.
2: Throughout
this
section,
generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to ECCP1,
ECCP2, ECCP3, CCP4 and CCP5.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.
This family of devices contains three Enhanced
Capture/Compare/PWM modules (ECCP1, ECCP2 and
ECCP3) and two standard Capture/Compare/PWM
modules (CCP4 and CCP5).
The Capture and Compare functions are identical for all
five CCP modules (ECCP1, ECCP2, ECCP3, CCP4
and CCP5). The only differences between CCP
modules are in the Pulse-Width Modulation (PWM)
function. The standard PWM function is identical in
modules, CCP4 and CCP5. In CCP modules ECCP1,
ECCP2 and ECCP3, the Enhanced PWM function has
slight variations from one another. Full-Bridge ECCP
modules have four available I/O pins while Half-Bridge
ECCP modules only have two available I/O pins. See
Table 22-1 for more information.
TABLE 22-1: PWM RESOURCES
Device Name
ECCP1
Enhanced PWM Enhanced PWM Enhanced PWM
Full-Bridge Full-Bridge Full-Bridge
ECCP2
ECCP3
CCP4
CCP5
PIC16F/LF1946/47
Standard PWM
Standard PWM
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 207
PIC16F/LF1946/47
22.1.2
TIMER1 MODE RESOURCE
22.1 Capture Mode
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
The Capture mode function described in this section is
available and identical for CCP modules ECCP1,
ECCP2, ECCP3, CCP4 and CCP5.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
See Section 20.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
22.1.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in Operating mode.
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 22-1 shows a simplified diagram of the Capture
operation.
22.1.4
CCP PRESCALER
There are four prescaler settings specified by the
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
22.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCPx pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function” for more
details.
Switching from one capture prescaler to another does
not clear the prescaler and may generate a false
interrupt. To avoid this unexpected operation, turn the
module off by clearing the CCPxCON register before
changing the prescaler. Example 22-1 demonstrates
the code to perform this function.
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
EXAMPLE 22-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 22-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
BANKSELCCPxCON
;Set Bank bits to point
;to CCPxCON
CLRF
MOVLW
CCPxCON
;Turn CCP module off
Set Flag bit CCPxIF
(PIRx register)
NEW_CAPT_PS;Load the W reg with
;the new prescaler
Prescaler
1, 4, 16
;move value and CCP ON
;Load CCPxCON with this
;value
CCPx
pin
CCPRxH
CCPRxL
MOVWF
CCPxCON
Capture
Enable
and
Edge Detect
22.1.5
CAPTURE DURING SLEEP
TMR1H
TMR1L
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
CCPxM<3:0>
System Clock (FOSC)
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
DS41414A-page 208
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
CCPxCON
CCPRxL
CCPRxH
INTCON
PIE1
PxM<1:0>
DCxB<1:0>
CCPxM<3:0>
229
208*
208*
89
Capture/Compare/PWM Register x Low Byte (LSB)
Capture/Compare/PWM Register x High Byte (MSB)
GIE
TMR1GIE
OSFIE
—
PEIE
ADIE
TMR0IE
RCIE
INTE
TXIE
IOCIE
SSPIE
TMR0IF
CCP1IE
LCDIE
—
INTF
IOCIF
TMR1IE
CCP2IE
—
TMR2IE
—
90
PIE2
C2IE
C1IE
EEIE
BCLIE
91
PIE3
CCP5IE
ADIF
CCP4IE
RCIF
CCP3IE
TXIF
TMR6IE
SSPIF
TMR4IE
TMR2IF
—
92
PIR1
TMR1GIF
OSFIF
—
CCP1IF
LCDIF
—
TMR1IF
CCP2IF
—
94
PIR2
C2IF
C1IF
EEIF
BCLIF
95
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR6IF
T1OSCEN
TMR4IF
—
96
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TRISB
TRISC
TRISD
TRISE
TMR1CS<1:0>
T1CKPS<1:0>
T1SYNC
TMR1ON
199
200
195*
195*
124
127
130
133
136
TMR1GE
T1GPOL
T1GTM
T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA7
TRISB7
TRISC7
TRISD7
—
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISB5
TRISC5
TRISD5
—
TRISA4
TRISB4
TRISC4
TRISD4
—
TRISA3
TRISB3
TRISC3
TRISD3
TRISE3
TRISA2
TRISB2
TRISC2
TRISD2
TRISE2
TRISA1
TRISB1
TRISC1
TRISD1
TRISE1
TRISA0
TRISB0
TRISC0
TRISD0
TRISE0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.
Note 1: Applies to ECCP modules only.
*
Page provides register information.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 209
PIC16F/LF1946/47
22.2.2
TIMER1 MODE RESOURCE
22.2 Compare Mode
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
The Compare mode function described in this section
is available and identical for CCP modules ECCP1,
ECCP2, ECCP3, CCP4 and CCP5.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
See Section 20.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
22.2.3
SOFTWARE INTERRUPT MODE
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
All Compare modes can generate an interrupt.
Figure 22-2 shows
Compare operation.
a simplified diagram of the
22.2.4
SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
FIGURE 22-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
• Resets Timer1
CCPxM<3:0>
Mode Select
• Starts an ADC conversion if ADC is enabled
(CCP5 only)
Set CCPxIF Interrupt Flag
The CCPx module does not assert control of the CCPx
pin in this mode.
(PIRx)
4
CCPx
Pin
CCPRxH CCPRxL
Comparator
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. The
Special Event Trigger output starts an A/D conversion
(if the A/D module is enabled). This feature is only
available on CCP5. This allows the CCPRxH, CCPRxL
Q
S
R
Output
Logic
Match
TMR1H TMR1L
TRIS
Output Enable
Special Event Trigger
Special Event Trigger will:
register pair to effectively provide
programmable period register for Timer1.
a
16-bit
•
•
CCP<4:1>: Reset Timer1, but not set interrupt flag bit
TMR1IF.
CCP5: Reset Timer1, but not set interrupt flag bit and set bit
GO/DONE (ADCON0<1>).
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
22.2.1
CCP PIN CONFIGURATION
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Also, the CCPx pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function” for more
details.
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
DS41414A-page 210
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
22.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
CCPxCON
CCPRxL
CCPRxH
INTCON
PIE1
PxM<1:0>
DCxB<1:0>
CCPxM<3:0>
229
208*
208*
89
Capture/Compare/PWM Register x Low Byte (LSB)
Capture/Compare/PWM Register x High Byte (MSB)
GIE
TMR1GIE
OSFIE
—
PEIE
ADIE
TMR0IE
RCIE
INTE
TXIE
IOCIE
SSPIE
TMR0IF
CCP1IE
LCDIE
—
INTF
IOCIF
TMR1IE
CCP2IE
—
TMR2IE
—
90
PIE2
C2IE
C1IE
EEIE
BCLIE
91
PIE3
CCP5IE
ADIF
CCP4IE
RCIF
CCP3IE
TXIF
TMR6IE
SSPIF
TMR4IE
TMR2IF
—
92
PIR1
TMR1GIF
OSFIF
—
CCP1IF
LCDIF
—
TMR1IF
CCP2IF
—
94
PIR2
C2IF
C1IF
EEIF
BCLIF
95
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR6IF
T1OSCEN
TMR4IF
—
96
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TRISB
TRISC
TRISD
TRISE
TMR1CS<1:0>
T1CKPS<1:0>
T1SYNC
TMR1ON
199
200
195*
195*
124
127
130
133
136
TMR1GE
T1GPOL
T1GTM
T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA7
TRISB7
TRISC7
TRISD7
—
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISB5
TRISC5
TRISD5
—
TRISA4
TRISB4
TRISC4
TRISD4
—
TRISA3
TRISB3
TRISC3
TRISD3
TRISE3
TRISA2
TRISB2
TRISC2
TRISD2
TRISE2
TRISA1
TRISB1
TRISC1
TRISD1
TRISE1
TRISA0
TRISB0
TRISC0
TRISD0
TRISE0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
Note 1: Applies to ECCP modules only.
*
Page provides register information.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 211
PIC16F/LF1946/47
FIGURE 22-3:
CCP PWM OUTPUT SIGNAL
22.3 PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
Period
Pulse Width
TMRx = PRx
TMRx = CCPRxH:CCPxCON<5:4>
TMRx = 0
FIGURE 22-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCPxCON<5:4>
Duty Cycle Registers
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
CCPRxL
CCPRxH(2) (Slave)
Comparator
CCPx
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
R
S
Q
(1)
TMRx
TRIS
Figure 22-3 shows a typical waveform of the PWM
signal.
Comparator
PRx
Clear Timer,
toggle CCPx pin and
latch duty cycle
22.3.1
STANDARD PWM OPERATION
The standard PWM function described in this section is
available and identical for CCP modules ECCP1,
ECCP2, ECCP3, CCP4 and CCP5.
Note 1: The 8-bit timer TMRx register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
2: In PWM mode, CCPRxH is a read-only register.
• PRx registers
• TxCON registers
• CCPRxL registers
• CCPxCON registers
Figure 22-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.
DS41414A-page 212
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
When TMRx is equal to PRx, the following three events
occur on the next increment cycle:
22.3.2
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for standard PWM operation:
• TMRx is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
1. Disable the CCPx pin output driver by setting the
associated TRIS bit.
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
2. Load the PRx register with the PWM period
value.
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
Note:
The Timer postscaler (see Section 21.0
“Timer2/4/6 Modules”) is not used in the
determination of the PWM frequency.
4. Load the CCPRxL register and the DCxBx bits
of the CCPxCON register, with the PWM duty
cycle value.
22.3.5
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PRx and TMRx
registers occurs). While using the PWM, the CCPRxH
register is read-only.
5. Configure and start Timer2/4/6:
• Select the Timer2/4/6 resource to be used
for PWM generation by setting the
CxTSEL<1:0> bits in the CCPTMRSx
register.
• Clear the TMRxIF interrupt flag bit of the
PIRx register. See Note below.
• Configure the TxCKPS bits of the TxCON
register with the Timer prescale value.
• Enable the Timer by setting the TMRxON
bit of the TxCON register.
Equation 22-2 is used to calculate the PWM pulse
width.
6. Enable PWM output pin:
• Wait until the Timer overflows and the
TMRxIF bit of the PIRx register is set. See
Note below.
Equation 22-2 is used to calculate the PWM duty cycle
ratio.
• Enable the CCPx pin output driver by clear-
ing the associated TRIS bit.
EQUATION 22-2: PULSE WIDTH
Pulse Width = CCPRxL:CCPxCON<5:4>
TOSC (TMRx Prescale Value)
Note:
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
EQUATION 22-3: DUTY CYCLE RATIO
22.3.3
TIMER2/4/6 TIMER RESOURCE
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = ----------------------------------------------------------------------
4PRx + 1
The PWM standard mode makes use of one of the 8-bit
Timer2/4/6 timer resources to specify the PWM period.
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Configuring the CxTSEL<1:0> bits in the CCPTMRSx
register selects which Timer2/4/6 timer is used.
22.3.4
PWM PERIOD
The 8-bit timer TMRx register is concatenated with either
the 2-bit internal system clock (FOSC), or 2 bits of the
prescaler, to create the 10-bit time base. The system
clock is used if the Timer2/4/6 prescaler is set to 1:1.
The PWM period is specified by the PRx register of
Timer2/4/6. The PWM period can be calculated using
the formula of Equation 22-1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 22-4).
EQUATION 22-1: PWM PERIOD
PWM Period = PRx + 1 4 TOSC
(TMRx Prescale Value)
Note 1: TOSC = 1/FOSC
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 213
PIC16F/LF1946/47
22.3.6
PWM RESOLUTION
EQUATION 22-4: PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
log4PRx + 1
Resolution = ----------------------------------------- bits
log2
The maximum PWM resolution is 10 bits when PRx is
255. The resolution is a function of the PRx register
value as shown by Equation 22-4.
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 22-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz)
PWM Frequency
1.95 kHz
7.81 kHz
31.25 kHz
125 kHz
250 kHz
333.3 kHz
Timer Prescale (1, 4, 16)
PRx Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 22-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PRx Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 22-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16)
PRx Value
16
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
Maximum Resolution (bits)
DS41414A-page 214
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
22.3.7
OPERATION IN SLEEP MODE
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
22.3.8
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
22.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 22-7: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
CCPxCON
CCPTMRS0
CCPTMRS1
INTCON
PIE1
PxM<1:0>
DCxB<1:0>
C3TSEL<1:0>
CCPxM<3:0>
C2TSEL<1:0> C1TSEL<1:0>
C5TSEL<1:0>
229
230
231
89
C4TSEL<1:0>
—
—
—
—
—
—
GIE
TMR1GIE
OSFIE
—
PEIE
TMR0IE
RCIE
INTE
IOCIE
SSPIE
BCLIE
TMR6IE
SSPIF
BCLIF
TMR6IF
TMR0IF
CCP1IE
LCDIE
—
INTF
IOCIF
TMR1IE
CCP2IE
—
ADIE
TXIE
TMR2IE
—
90
PIE2
C2IE
C1IE
EEIE
91
PIE3
CCP5IE
ADIF
CCP4IE
RCIF
CCP3IE
TXIF
TMR4IE
TMR2IF
—
92
PIR1
TMR1GIF
OSFIF
—
CCP1IF
LCDIF
—
TMR1IF
CCP2IF
—
94
PIR2
C2IF
C1IF
EEIF
95
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR4IF
96
PRx
Timer2/4/6 Period Register
—
203*
205
203
124
127
130
133
136
TxCON
TMRx
TxOUTPS<3:0>
TMRxON
TxCKPS<:0>1
Timer2/4/6 Module Register
TRISA
TRISB
TRISC
TRISD
TRISE
TRISA7
TRISB7
TRISC7
TRISD7
—
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISB5
TRISC5
TRISD5
—
TRISA4
TRISB4
TRISC4
TRISD4
—
TRISA3
TRISB3
TRISC3
TRISD3
TRISE3
TRISA2
TRISB2
TRISC2
TRISD2
TRISE2
TRISA1
TRISB1
TRISC1
TRISD1
TRISE1
TRISA0
TRISB0
TRISC0
TRISD0
TRISE0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Note 1: Applies to ECCP modules only.
*
Page provides register information.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 215
PIC16F/LF1946/47
To select an Enhanced PWM Output mode, the PxM bits
of the CCPxCON register must be configured
appropriately.
22.4 PWM (Enhanced Mode)
The enhanced PWM function described in this section is
available for CCP modules ECCP1, ECCP2 and
ECCP3, with any differences between modules noted.
The PWM outputs are multiplexed with I/O pins and are
designated PxA, PxB, PxC and PxD. The polarity of the
PWM pins is configurable and is selected by setting the
CCPxM bits in the CCPxCON register appropriately.
The enhanced PWM mode generates a Pulse-Width
Modulation (PWM) signal on up to four different output
pins with up to 10 bits of resolution. The period, duty
cycle, and resolution are controlled by the following
registers:
Figure 22-5 shows an example of a simplified block
diagram of the Enhanced PWM module.
Table 22-8 shows the pin assignments for various
Enhanced PWM modes.
• PRx registers
• TxCON registers
• CCPRxL registers
• CCPxCON registers
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
The ECCP modules have the following additional PWM
registers which control Auto-shutdown, Auto-restart,
Dead-band Delay and PWM Steering modes:
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.
3: Any pin not used in the enhanced PWM
mode is available for alternate pin
functions, if applicable.
• CCPxAS registers
• PSTRxCON registers
• PWMxCON registers
4: To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits
until the start of a new PWM period before
generating a PWM signal.
The enhanced PWM module can generate the following
five PWM Output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward Mode
• Full-Bridge PWM, Reverse Mode
• Single PWM with PWM Steering Mode
FIGURE 22-5:
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DCxB<1:0>
PxM<1:0>
CCPxM<3:0>
4
Duty Cycle Registers
2
CCPRxL
CCPx/PxA
CCPx/PxA
PxB
TRISx
TRISx
TRISx
TRISx
CCPRxH (Slave)
Comparator
PxB
Output
Controller
R
S
Q
PxC
PxC
(1)
TMRx
PxD
PxD
Comparator
PRx
Clear Timer,
toggle PWM pin and
latch duty cycle
PWMxCON
Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time
base.
DS41414A-page 216
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 22-8: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode
PxM<1:0>
CCPx/PxA
PxB
PxC
PxD
Single
00
10
01
11
Yes(1)
Yes
Yes(1)
Yes
Yes(1)
No
Yes(1)
No
Half-Bridge
Full-Bridge, Forward
Full-Bridge, Reverse
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 1: PWM Steering enables outputs in Single mode.
FIGURE 22-6:
EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH
STATE)
PRX+1
Pulse
Width
0
Signal
PxM<1:0>
Period
PxA Modulated
(Single Output)
00
10
Delay
Delay
PxA Modulated
PxB Modulated
PxA Active
(Half-Bridge)
PxB Inactive
(Full-Bridge,
Forward)
01
PxC Inactive
PxD Modulated
PxA Inactive
PxB Modulated
PxC Active
(Full-Bridge,
Reverse)
11
PxD Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 217
PIC16F/LF1946/47
FIGURE 22-7:
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
PRx+1
Pulse
Width
0
Signal
PxM<1:0>
Period
PxA Modulated
PxA Modulated
PxB Modulated
PxA Active
(Single Output)
00
10
Delay
Delay
(Half-Bridge)
(Full-Bridge,
Forward)
PxB Inactive
PxC Inactive
PxD Modulated
PxA Inactive
PxB Modulated
PxC Active
01
(Full-Bridge,
Reverse)
11
PxD Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
DS41414A-page 218
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
Since the PxA and PxB outputs are multiplexed with the
PORT data latches, the associated TRIS bits must be
cleared to configure PxA and PxB as outputs.
22.4.1
HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCPx/PxA pin, while the complementary PWM
output signal is output on the PxB pin (see
Figure 22-9). This mode can be used for Half-Bridge
applications, as shown in Figure 22-9, or for Full-Bridge
applications, where four power switches are being
modulated with two PWM signals.
FIGURE 22-8:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
Period
Period
Pulse Width
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
Half-Bridge power devices. The value of the PDC<6:0>
bits of the PWMxCON register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 22.4.5 “Programmable Dead-Band Delay
Mode” for more details of the dead-band delay
operations.
(2)
(2)
PxA
td
td
PxB
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMRx register is equal to the
PRx register.
2: Output signals are shown as active-high.
FIGURE 22-9:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
-
PxA
Load
FET
Driver
+
-
PxB
Half-Bridge Output Driving a Full-Bridge Circuit
V+
FET
Driver
FET
Driver
PxA
Load
FET
FET
Driver
Driver
PxB
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 219
PIC16F/LF1946/47
22.4.2
FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs.
An example of Full-Bridge application is shown in
Figure 22-10.
In the Forward mode, pin CCPx/PxA is driven to its active
state, pin PxD is modulated, while PxB and PxC will be
driven to their inactive state as shown in Figure 22-11.
In the Reverse mode, PxC is driven to its active state, pin
PxB is modulated, while PxA and PxD will be driven to
their inactive state as shown Figure 22-11.
PxA, PxB, PxC and PxD outputs are multiplexed with
the PORT data latches. The associated TRIS bits must
be cleared to configure the PxA, PxB, PxC and PxD
pins as outputs.
FIGURE 22-10:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
QC
QA
FET
Driver
FET
Driver
PxA
PxB
Load
FET
Driver
FET
Driver
PxC
PxD
QD
QB
V-
DS41414A-page 220
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 22-11:
EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
PxA
Pulse Width
(2)
PxB
(2)
PxC
(2)
PxD
(1)
(1)
Reverse Mode
Period
Pulse Width
(2)
PxA
(2)
PxB
(2)
PxC
(2)
PxD
(1)
(1)
Note 1: At this time, the TMRx register is equal to the PRx register.
2: Output signal is shown as active-high.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 221
PIC16F/LF1946/47
The Full-Bridge mode does not provide dead-band
delay. As one output is modulated at a time, dead-band
delay is generally not required. There is a situation
where dead-band delay is required. This situation
occurs when both of the following conditions are true:
22.4.2.1
Direction Change in Full-Bridge
Mode
In the Full-Bridge mode, the PxM1 bit in the CCPxCON
register allows users to control the forward/reverse
direction. When the application firmware changes this
direction control bit, the module will change to the new
direction on the next PWM cycle.
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off time of the power switch, including
the power device and driver circuit, is greater
than the turn on time.
A direction change is initiated in software by changing
the PxM1 bit of the CCPxCON register. The following
sequence occurs four Timer cycles prior to the end of
the current PWM period:
Figure 22-13 shows an example of the PWM direction
changing from forward to reverse, at a near 100% duty
cycle. In this example, at time t1, the output PxA and
PxD become inactive, while output PxC becomes
active. Since the turn-off time of the power devices is
longer than the turn-on time, a shoot-through current
will flow through power devices QC and QD (see
Figure 22-10) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
• The modulated outputs (PxB and PxD) are placed
in their inactive state.
• The associated unmodulated outputs (PxA and
PxC) are switched to drive in the opposite
direction.
• PWM modulation resumes at the beginning of the
next period.
See Figure 22-12 for an illustration of this sequence.
If changing PWM direction at high duty cycle is required
for an application, two possible solutions for eliminating
the shoot-through current are:
1. Reduce PWM duty cycle for one PWM period
before changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 22-12:
EXAMPLE OF PWM DIRECTION CHANGE
(1)
Period
Period
Signal
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
PxD (Active-High)
(2)
Pulse Width
Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.
DS41414A-page 222
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 22-13:
EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
PxA
PxB
PW
PxC
PxD
PW
TON
External Switch C
External Switch D
TOFF
Potential
T = TOFF – TON
Shoot-Through Current
Note 1: All signals are shown as active-high.
2: TON is the turn on delay of power switch QC and its driver.
3: TOFF is the turn off delay of power switch QD and its driver.
• Drive logic ‘1’
• Drive logic ‘0’
22.4.3
ENHANCED PWM
AUTO-SHUTDOWN MODE
• Tri-state (high-impedance)
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
Note 1: The auto-shutdown condition is
a
level-based signal, not an edge-based
signal. As long as the level is present, the
auto-shutdown will persist.
The auto-shutdown sources are selected using the
CCPxAS<2:0> bits of the CCPxAS register. A shutdown
event may be generated by:
2: Writing to the CCPxASE bit is disabled
while an auto-shutdown condition
persists.
• A logic ‘0’ on the INT pin
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
• A logic ‘1’ on a Comparator (Cx) output
A shutdown condition is indicated by the CCPxASE
(Auto-Shutdown Event Status) bit of the CCPxAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
4: Prior to an auto-shutdown event caused
by a comparator output or INT pin event,
a software shutdown can be triggered in
firmware by setting the CCPxASE bit to a
‘1’. The auto-restart feature tracks the
active status of a shutdown caused by a
comparator output or INT pin event only,
so if it is enabled at this time, it will imme-
diately clear this bit and restart the ECCP
module at the beginning of the next PWM
period.
When a shutdown event occurs, two things happen:
The CCPxASE bit is set to ‘1’. The CCPxASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 22.4.4 “Auto-Restart Mode”).
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [PxA/PxC] and [PxB/PxD]. The state
of each pin pair is determined by the PSSxAC and
PSSxBD bits of the CCPxAS register. Each pin pair may
be placed into one of three states:
2010 Microchip Technology Inc.
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PIC16F/LF1946/47
FIGURE 22-14:
PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0)
Missing Pulse
(Auto-Shutdown)
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Resumes
Shutdown
Event Occurs
Shutdown
Event Clears
CCPxASE
Cleared by
Firmware
If auto-restart is enabled, the CCPxASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
CCPxASE bit will be cleared via hardware and normal
operation will resume.
22.4.4
AUTO-RESTART MODE
The Enhanced PWM can be configured to automati-
cally restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PxRSEN bit in the PWMxCON register.
FIGURE 22-15:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1)
Missing Pulse
(Auto-Shutdown)
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Resumes
Shutdown
Event Occurs
Shutdown
Event Clears
CCPxASE
Cleared by
Hardware
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PIC16F/LF1946/47
22.4.5
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 22-16:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
Period
Period
Pulse Width
(2)
(2)
PxA
td
td
During this brief interval,
a very high current
PxB
(shoot-through current) will flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMRx register is equal to the
PRx register.
In Half-Bridge mode,
a
digitally programmable
2: Output signals are shown as active-high.
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 22-16 for
illustration. The lower seven bits of the associated
PWMxCON register (Register 22-5) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
FIGURE 22-17:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
V
-
PxA
Load
FET
Driver
+
V
-
PxB
V-
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22.4.6
PWM STEERING MODE
In Single Output mode, PWM steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Once the Single Output mode is selected
(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STRx<D:A> bits of the
PSTRxCON register, as shown in Table 22-8.
Note:
The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
While the PWM Steering mode is active, CCPxM<1:0>
bits of the CCPxCON register select the PWM output
polarity for the Px<D:A> pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 22.4.3
“Enhanced PWM Auto-shutdown mode”. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
FIGURE 22-18:
SIMPLIFIED STEERING
BLOCK DIAGRAM
STRxA
PxA Signal
CCPxM1
PxA pin
1
PORT Data
STRxB
0
TRIS
PxB pin
CCPxM0
1
PORT Data
STRxC
0
TRIS
PxC pin
1
CCPxM1
PORT Data
0
TRIS
STRxD
PxD pin
1
CCPxM0
PORT Data
0
TRIS
Note 1: Port outputs are configured as shown when
the CCPxCON register bits PxM<1:0> = 00
and CCPxM<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
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drivers are enabled. Changing the polarity
configuration while the PWM pin output drivers are
enable is not recommended since it may result in
damage to the application circuits.
22.4.6.1
Steering Synchronization
The STRxSYNC bit of the PSTRxCON register gives
the user two selections of when the steering event will
happen. When the STRxSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the
output signal at the Px<D:A> pins may be an
incomplete PWM waveform. This operation is useful
when the user firmware needs to immediately remove
a PWM signal from the pin.
The PxA, PxB, PxC and PxD output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMRxIF bit of the PIRx register
being set as the second PWM period begins.
When the STRxSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Note:
When the microcontroller is released from
Reset, all of the I/O pins are in the
high-impedance state. The external cir-
cuits must keep the power switch devices
in the Off state until the microcontroller
drives the I/O pins with the proper signal
levels or activates the PWM output(s).
Figures 22-19 and 22-20 illustrate the timing diagrams
of the PWM steering depending on the STRxSYNC
setting.
22.4.7
START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
The CCPxM<1:0> bits of the CCPxCON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (PxA/PxC and PxB/PxD). The PWM output
polarities must be selected before the PWM pin output
FIGURE 22-19:
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)
PWM Period
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 22-20:
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION
(STRxSYNC = 1)
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
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TABLE 22-9: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
CCPxCON
CCPxAS
CCPTMRS0
CCPTMRS1
INTCON
PIE1
PxM<1:0>
DCxB<1:0>
CCPxM<3:0>
PSSxAC<1:0> PSSxBD<1:0>
C2TSEL<1:0>
229
232
230
231
89
CCPxASE
CCPxAS<2:0>
C4TSEL<1:0>
C3TSEL<1:0>
C1TSEL<1:0>
C5TSEL<1:0>
—
GIE
—
—
—
—
—
PEIE
TMR0IE
RCIE
INTE
IOCIE
SSPIE
BCLIE
TMR6IE
SSPIF
BCLIF
TMR0IF
CCP1IE
LCDIE
—
INTF
IOCIF
TMR1IE
CCP2IE
—
TMR1GIE
OSFIE
—
ADIE
TXIE
TMR2IE
—
90
PIE2
C2IE
C1IE
EEIE
91
PIE3
CCP5IE
ADIF
CCP4IE
RCIF
CCP3IE
TXIF
TMR4IE
TMR2IF
—
92
PIR1
TMR1GIF
OSFIF
—
CCP1IF
LCDIF
—
TMR1IF
CCP2IF
—
94
PIR2
C2IF
C1IF
EEIF
95
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR4IF
96
PRx
Timer2/4/6 Period Register
203*
234
233
PSTRxCON
PWMxCON
TxCON
—
PxRSEN
—
—
—
STRxSYNC
STRxD
STRxC
STRxB
STRxA
PxDC<6:0>
TxOUTPS<3:0>
TMRxON
TxCKPS<:0>1
205
203
216
216
216
216
216
TMRx
TRISA
TRISB
TRISC
TRISD
TRISE
Timer2/4/6 Module Register
TRISA7
TRISB7
TRISC7
TRISD7
—
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISA4
TRISB4
TRISC4
TRISD4
—
TRISA3
TRISB3
TRISC3
TRISD3
TRISE3
TRISA2
TRISB2
TRISC2
TRISD2
TRISE2
TRISA1
TRISB1
TRISC1
TRISD1
TRISE1
TRISA0
TRISB0
TRISC0
TRISD0
TRISE0
TRISB5
TRISC5
TRISD5
—
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Note 1: Applies to ECCP modules only.
*
Page provides register information.
DS41414A-page 228
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REGISTER 22-1: CCPxCON: CCPx CONTROL REGISTER
R/W-00
PxM<1:0>
R/W-0/0
(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DCxB<1:0>
CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Reset
(1)
bit 7-6
PxM<1:0>: Enhanced PWM Output Configuration bits
Capture mode:
Unused
Compare mode:
Unused
If CCPxM<3:2> = 00, 01, 10:
xx= PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins
If CCPxM<3:2> = 11:
00= Single output; PxA modulated; PxB, PxC, PxD assigned as port pins
01= Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive
10= Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins
11= Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive
bit 5-4
DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM<3:0>: ECCPx Mode Select bits
0000= Capture/Compare/PWM off (resets ECCPx module)
0001= Reserved
0010= Compare mode: toggle output on match
0011= Reserved
0100= Capture mode: every falling edge
0101= Capture mode: every rising edge
0110= Capture mode: every 4th rising edge
0111= Capture mode: every 16th rising edge
1000= Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)
1001= Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)
1010= Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state
1011= Compare mode: Special Event Trigger (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger
(1)
also starts A/D conversion if A/D module is enabled)
CCP4/CCP5 only:
11xx= PWM mode
ECCP1/ECCP2/ECCP3 only:
1100= PWM mode: PxA, PxC active-high; PxB, PxD active-high
1101= PWM mode: PxA, PxC active-high; PxB, PxD active-low
1110= PWM mode: PxA, PxC active-low; PxB, PxD active-high
1111= PWM mode: PxA, PxC active-low; PxB, PxD active-low
Note 1: These bits are not implemented on CCP<5:4>.
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REGISTER 22-2: CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
bit 3-2
bit 1-0
C4TSEL<1:0>: CCP4 Timer Selection bits
00= CCP4 is based off Timer 2 in PWM Mode
01= CCP4 is based off Timer 4 in PWM Mode
10= CCP4 is based off Timer 6 in PWM Mode
11= Reserved
C3TSEL<1:0>: CCP3 Timer Selection bits
00= CCP3 is based off Timer 2 in PWM Mode
01= CCP3 is based off Timer 4 in PWM Mode
10= CCP3 is based off Timer 6 in PWM Mode
11= Reserved
C2TSEL<1:0>: CCP2 Timer Selection bits
00= CCP2 is based off Timer 2 in PWM Mode
01= CCP2 is based off Timer 4 in PWM Mode
10= CCP2 is based off Timer 6 in PWM Mode
11= Reserved
C1TSEL<1:0>: CCP1 Timer Selection bits
00= CCP1 is based off Timer 2 in PWM Mode
01= CCP1 is based off Timer 4 in PWM Mode
10= CCP1 is based off Timer 6 in PWM Mode
11= Reserved
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REGISTER 22-3: CCPTMRS1: PWM TIMER SELECTION CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
C5TSEL<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
C5TSEL<1:0>: CCP5 Timer Selection bits
00= CCP5 is based off Timer 2 in PWM Mode
01= CCP5 is based off Timer 4 in PWM Mode
10= CCP5 is based off Timer 6 in PWM Mode
11= Reserved
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REGISTER 22-4: CCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CCPxASE
CCPxAS<2:0>
PSSxAC<1:0>
PSSxBD<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CCPxASE: CCPx Auto-Shutdown Event Status bit
1= A shutdown event has occurred; CCPx outputs are in shutdown state
0= CCPx outputs are operating
bit 6-4
CCPxAS<2:0>: CCPx Auto-Shutdown Source Select bits
000= Auto-shutdown is disabled
001= Comparator C1 output high(1)
010= Comparator C3 output high(1)
011= Either Comparator C1 or C3 high(1)
100= VIL on INT pin
101= VIL on INT pin or Comparator C1 high(1)
110= VIL on INT pin or Comparator C3 high(1)
111= VIL on INT pin or Comparator C1 or Comparator C3 high(1)
bit 3-2
bit 1-0
PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits
00= Drive pins PxA and PxC to ‘0’
01= Drive pins PxA and PxC to ‘1’
1x= Pins PxA and PxC tri-state
PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits
00= Drive pins PxB and PxD to ‘0’
01= Drive pins PxB and PxD to ‘1’
1x= Pins PxB and PxD tri-state
Note 1: If CxSYNC is enabled, the shutdown will be delayed by Timer1.
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REGISTER 22-5: PWMxCON: ENHANCED PWM CONTROL REGISTER
R/W-0/0
PxRSEN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
PxDC<6:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
PxRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away;
the PWM restarts automatically
0= Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM
bit 6-0
PxDC<6:0>: PWM Delay Count bits
PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
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REGISTER 22-6: PSTRxCON: PWM STEERING CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
STRxD
R/W-0/0
STRxC
R/W-0/0
STRxB
R/W-1/1
STRxA
STRxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-5
bit 4
Unimplemented: Read as ‘0’
STRxSYNC: Steering Sync bit
1= Output steering update occurs on next PWM period
0= Output steering update occurs at the beginning of the instruction cycle boundary
bit 3
bit 2
bit 1
bit 0
STRxD: Steering Enable bit D
1= PxD pin has the PWM waveform with polarity control from CCPxM<1:0>
0= PxD pin is assigned to port pin
STRxC: Steering Enable bit C
1= PxC pin has the PWM waveform with polarity control from CCPxM<1:0>
0= PxC pin is assigned to port pin
STRxB: Steering Enable bit B
1= PxB pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxB pin is assigned to port pin
STRxA: Steering Enable bit A
1= PxA pin has the PWM waveform with polarity control from CCPxM<1:0>
0= PxA pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11and
PxM<1:0> = 00.
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23.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP1 AND
MSSP2) MODULE
23.1 Master SSPx (MSSPx) Module
Overview
The Master Synchronous Serial Port (MSSPx) module
is a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSPx module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy chain connection of slave devices
Figure 23-1 is a block diagram of the SPI interface
module.
FIGURE 23-1:
MSSPX BLOCK DIAGRAM (SPI MODE)
Data Bus
Read
Write
SSPxBUF Reg
SSPxSR Reg
SDIx
Shift
Clock
bit 0
SDOx
SSx
Control
Enable
SSx
2 (CKP, CKE)
Clock Select
Edge
Select
SSPxM<3:0>
4
TMR2 Output
(
)
2
SCKx
Edge
Select
TOSC
Prescaler
4, 16, 64
Baud rate
generator
(SSPxADD)
TRIS bit
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The I2C interface supports the following modes and
features:
The PIC16F1947 has two MSSP modules, MSSP1 and
MSSP2, each module operating independently from
the other.
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
Note 1: In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCONx register names.
SSP1CON1 and SSP1CON2 registers
control different operational aspects of the
same module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
2: Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names, module I/O sig-
nals, and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module
when required.
• Address Hold and Data Hold modes
• Selectable SDAx hold times
Figure 23-2 is a block diagram of the I2C interface mod-
ule in Master mode. Figure 23-3 is a diagram of the I2C
interface module in Slave mode.
FIGURE 23-2:
MSSPX BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal
data bus
[SSPxM 3:0]
Read
Write
SSPxBUF
SSPxSR
Baud rate
generator
(SSPxADD)
SDAx
Shift
Clock
SDAx in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPxCON2)
SCLx
Start bit detect,
Stop bit detect
SCLx in
Bus Collision
Write collision detect
Clock arbitration
State counter for
Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV
Reset SEN, PEN (SSPxCON2)
Set SSPxIF, BCLxIF
end of XMIT/RCV
Address Match detect
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FIGURE 23-3:
MSSPx BLOCK DIAGRAM (I2C™ SLAVE MODE)
Internal
Data Bus
Read
Write
SSPxBUF Reg
SSPxSR Reg
SCLx
SDAx
Shift
Clock
MSb
LSb
SSPxMSK Reg
Match Detect
SSPxADD Reg
Addr Match
Set, Reset
S, P bits
(SSPxSTAT Reg)
Start and
Stop bit Detect
2010 Microchip Technology Inc.
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its SDOx pin) and the slave device is reading this bit
and saving it as the LSb of its shift register, that the
slave device is also sending out the MSb from its shift
register (on its SDOx pin) and the master device is
reading this bit and saving it as the LSb of its shift
register.
23.2 SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full Duplex mode. Devices communicate in
a master/slave environment where the master device
initiates the communication.
A slave device is
After 8 bits have been shifted out, the master and slave
have exchanged register values.
controlled through a chip select known as Slave Select.
The SPI bus specifies four signal connections:
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
• Serial Clock (SCKx)
• Serial Data Out (SDOx)
• Serial Data In (SDIx)
• Slave Select (SSx)
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
Figure 23-1 shows the block diagram of the MSSPx
module when operating in SPI Mode.
• Master sends useful data and slave sends dummy
data.
• Master sends useful data and slave sends useful
data.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select con-
nection is required from the master device to each
slave device.
• Master sends dummy data and slave sends useful
data.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it
deselects the slave.
Figure 23-4 shows a typical connection between a
master device and multiple slave devices.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Every slave device connected to the bus that has not
been selected through its slave select line must disre-
gard the clock and transmission signals and must not
transmit out any data of its own.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 23-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the pro-
grammed clock edge and latched on the opposite edge
of the clock.
The master device transmits information out on its
SDOx output pin which is connected to, and received
by, the slave’s SDIx input pin. The slave device trans-
mits information out on its SDOx output pin, which is
connected to, and received by, the master’s SDIx input
pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
DS41414A-page 238
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FIGURE 23-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCKx
SDOx
SCKx
SDIx
SDOx
SSx
SPI Master
SPI Slave
#1
SDIx
General I/O
General I/O
General I/O
SCKx
SDIx
SDOx
SSx
SPI Slave
#2
SCKx
SDIx
SDOx
SSx
SPI Slave
#3
23.2.1 SPI MODE REGISTERS
The MSSPx module has five registers for SPI mode
operation. These are:
• MSSPx STATUS register (SSPxSTAT)
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 3 (SSPxCON3)
• MSSPx Data Buffer register (SSPxBUF)
• MSSPx Address register (SSPxADD)
• MSSPx Shift register (SSPxSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and
STATUS registers in SPI mode operation. The
SSPxCON1 register is readable and writable. The
lower 6 bits of the SSPxSTAT are read-only. The upper
two bits of the SSPxSTAT are read/write.
In one SPI master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 23.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPxSR.
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23.2.2 SPI MODE OPERATION
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
The MSSPx consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPxSR until the received data is ready. Once the
8 bits of data have been received, that byte is moved to
the SSPxBUF register. Then, the Buffer Full Detect bit,
BF of the SSPxSTAT register, and the interrupt flag bit,
SSPxIF, are set. This double-buffering of the received
data (SSPxBUF) allows the next byte to start reception
before reading the data that was just received. Any
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
write
to
the
SSPxBUF
register
during
• Slave Select mode (Slave mode only)
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPxCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the
SSPxBUF register to complete successfully.
To enable the serial port, SSPx Enable bit, SSPxEN of
the SSPxCON1 register, must be set. To reset or recon-
figure SPI mode, clear the SSPxEN bit, re-initialize the
SSPxCONx registers and then set the SSPxEN bit.
This configures the SDIx, SDOx, SCKx and SSx pins
as serial port pins. For the pins to behave as the serial
port function, some must have their data direction bits
(in the TRIS register) appropriately programmed as
follows:
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the
next byte of data to transfer is written to the SSPxBUF.
The Buffer Full bit, BF of the SSPxSTAT register,
indicates when SSPxBUF has been loaded with the
received data (transmission is complete). When the
SSPxBUF is read, the BF bit is cleared. This data may
be irrelevant if the SPI is only a transmitter. Generally,
the MSSPx interrupt is used to determine when the
transmission/reception has completed. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur.
• SDIx must have corresponding TRIS bit set
• SDOx must have corresponding TRIS bit cleared
• SCKx (Master mode) must have corresponding
TRIS bit cleared
• SCKx (Slave mode) must have corresponding
TRIS bit set
• SSx must have corresponding TRIS bit set
FIGURE 23-5:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPxM<3:0> = 00xx
= 1010
SPI Slave SSPxM<3:0> = 010x
SDOx
SDIx
Serial Input Buffer
Serial Input Buffer
(SSPxBUF)
(BUF)
SDIx
SDOx
Shift Register
(SSPxSR)
Shift Register
(SSPxSR)
LSb
MSb
MSb
LSb
Serial Clock
SCKx
SCKx
SSx
Slave Select
(optional)
General I/O
Processor 2
Processor 1
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The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 23-6, Figure 23-8 and Figure 23-9,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
23.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCKx line. The master
determines when the slave (Processor 2, Figure 23-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
• FOSC/4 (or TCY)
• FOSC/16 (or 4 * TCY)
• FOSC/64 (or 16 * TCY)
• Timer2 output/2
• Fosc/(4 * (SSPxADD + 1))
Figure 23-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 23-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDOx
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDOx
(CKE = 1)
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
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23.2.4
SPI SLAVE MODE
23.2.5
SLAVE SELECT
SYNCHRONIZATION
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCKx. When the last
bit is latched, the SSPxIF interrupt flag bit is set.
The Slave Select can also be used to synchronize com-
munication. The Slave Select line is held high until the
master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCKx pin. The Idle state is
determined by the CKP bit of the SSPxCON1 register.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will even-
tually become out of sync with the master. If the slave
misses a bit, it will always be one bit off in future trans-
missions. Use of the Slave Select line allows the slave
and master to align themselves at the beginning of
each transmission.
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This exter-
nal clock must meet the minimum high and low times
as specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCKx pin
input and when a byte is received, the device will gen-
erate an interrupt. If enabled, the device will wake-up
from Sleep.
23.2.4.1 Daisy-Chain Configuration
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SSx pin control
enabled (SSPxCON1<3:0> = 0100).
The SPI bus can sometimes be connected in a
daisy-chain configuration. The first slave output is con-
nected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one large communication shift register. The
daisy-chain feature only requires a single Slave Select
line from the master device.
When the SSx pin is low, transmission and reception
are enabled and the SDOx pin is driven.
When the SSx pin goes high, the SDOx pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the applica-
tion.
Note 1: When the SPI is in Slave mode with SSx
pin control enabled (SSPxCON1<3:0> =
0100), the SPI module will reset if the SSx
pin is set to VDD.
Figure 23-7 shows the block diagram of a typical
Daisy-Chain connection when operating in SPI Mode.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPxCON3 register will enable writes
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SSx pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSPxSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPxEN bit.
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FIGURE 23-7:
SPI DAISY-CHAIN CONNECTION
SCK
SCK
SPI Master
SDOx
SDIx
SDIx
SDOx
SSx
SPI Slave
#1
General I/O
SCK
SDIx
SDOx
SSx
SPI Slave
#2
SCK
SDIx
SDOx
SSx
SPI Slave
#3
FIGURE 23-8:
SLAVE SELECT SYNCHRONOUS WAVEFORM
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
bit 6
bit 6
bit 7
bit 7
bit 0
SDOx
SDIx
bit 7
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
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FIGURE 23-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDOx
bit 7
SDIx
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
FIGURE 23-10:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDOx
bit 7
bit 7
SDIx
bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
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23.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
APFCON
INTCON
PIE1
ANSA7
P3CSEL
GIE
ANSA6
P3BSEL
PEIE
ADIE
—
ANSA5
P2DSEL
TMR0IE
RCIE
ANSA4
P2CSEL
INTE
ANSA3
P2BSEL
IOCIE
SSP1IE
—
ANSA2
CCP2SEL
TMR0IF
CCP1IE
—
ANSA1
P1CSEL
INTF
ANSA0
P1BSEL
IOCIF
125
122
89
TMR1GIE
—
TXIE
TMR2IE
BCL2IE
TMR2IF
BCL2IF
TMR1IE
SSP2IE
TMR1IF
SSP2IF
90
PIE4
RC2IE
RCIF
TX2IE
TXIF
93
PIR1
TMR1GIF
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
RC2IF
TX2IF
97
SSPxBUF
SSPxCON1
Synchronous Serial Port Receive Buffer/Transmit Register
239*
284
286
283
124
127
WCOL
SSPxOV
PCIE
SSPxEN
SCIE
CKP
SSPxM<3:0>
SSPxCON3 ACKTIM
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSPxSTAT
TRISA
SMP
CKE
D/A
P
S
R/W
UA
BF
TRISA7
TRISB7
TRISA6
TRISB6
TRISA5
TRISB5
TRISA4
TRISB4
TRISA3
TRISB3
TRISA2
TRISB2
TRISA1
TRISB1
TRISA0
TRISB0
TRISB
Legend:
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
*
Page provides register information.
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I2C MASTER/
23.3 I2C MODE OVERVIEW
FIGURE 23-11:
SLAVE CONNECTION
The Inter-Integrated Circuit Bus (I²C™) is
a
multi-master serial data communication bus. Devices
communicate in a master/slave environment where the
master devices initiate the communication. A Slave
device is controlled through addressing.
VDD
SCLx
SCLx
The I2C bus specifies two signal connections:
VDD
• Serial Clock (SCLx)
• Serial Data (SDAx)
Master
Slave
SDAx
SDAx
Figure 23-11 shows the block diagram of the MSSPx
module when operating in I2C Mode.
Both the SCLx and SDAx connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDAx line low to indicate to the trans-
mitter that the slave device has received the transmit-
ted data and is ready to receive more.
Figure 23-11 shows a typical connection between two
processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
The transition of a data bit is always performed while
the SCLx line is held low. Transitions that occur while
the SCLx line is held high are used to indicate Start and
Stop bits.
If the master intends to write to the slave, then it repeat-
edly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this exam-
ple, the master device is in Master Receive mode and
the slave is Slave Transmit mode.
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is indi-
cated by a low-to-high transition of the SDAx line while
the SCLx line is held high.
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a sin-
gle Read/Write bit, which determines whether the mas-
ter intends to transmit to or receive data from the slave
device.
In some cases, the master may want to maintain con-
trol of the bus and re-initiate another transmission. If
so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
The I2C bus specifies three message protocols;
• Single message where a master writes data to a
slave.
A Start bit is indicated by a high-to-low transition of the
SDAx line while the SCLx line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
• Single message where a master reads data from
a slave.
• Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
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When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a log-
ical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCLx line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDAx line, it is called arbitration. Arbitration
ensures that there is only one master device communi-
cating at any single time.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less com-
mon.
If two master devices are sending a message to two dif-
ferent slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a neces-
sary process for proper multi-master support.
23.3.1
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of Clock Stretching. An addressed slave
device may hold the SCLx clock line low after receiving
or sending a bit, indicating that it is not yet ready to con-
tinue. The master that is communicating with the slave
will attempt to raise the SCLx line in order to transfer
the next bit, but will detect that the clock line has not yet
been released. Because the SCLx connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
23.4 I2C Mode Operation
All MSSPx I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and 2 interrupt
flags interface the module with the PIC® microcon-
troller and user software. Two pins, SDAx and SCLx,
are exercised by the module to communicate with
other external I2C devices.
23.4.1 BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a Master to a Slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the 8th
falling edge of the SCLx line, the device outputting data
on the SDAx changes that pin to an input and reads in
an acknowledge value on the next clock pulse.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
23.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
The clock signal, SCLx, is provided by the master.
Data is valid to change while the SCLx signal is low,
and sampled on the rising edge of the clock. Changes
on the SDAx line while the SCLx line is high define
special conditions on the bus, explained below.
However, two master devices may try to initiate a trans-
mission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDAx data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels don’t match, loses arbitra-
tion, and must stop transmitting on the SDAx line.
23.4.2 DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description of
I2C communication that have definitions specific to I2C.
That word usage is defined below and may be used in
the rest of this document without explanation. This table
was adapted from the Phillips I2C specification.
For example, if one transmitter holds the SDAx line to
a logical one (lets it float) and a second transmitter
holds it to a logical zero (pulls it low), the result is that
the SDAx line will be low. The first transmitter then
observes that the level of the line is different than
expected and concludes that another transmitter is
communicating.
23.4.3 SDAX AND SCLX PINS
Selection of any I2C mode with the SSPxEN bit set,
forces the SCLx and SDAx pins to be open-drain.
These pins should be set by the user to inputs by set-
ting the appropriate TRIS bits.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDAx
line. If this transmitter is also a master device, it also
must stop driving the SCLx line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDAx line continues with its
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Note: Data is tied to output zero when an I2C mode
is enabled.
23.4.4 SDAX HOLD TIME
The hold time of the SDAx pin is selected by the
SDAHT bit of the SSPxCON3 register. Hold time is the
time SDAx is held valid after the falling edge of SCLx.
Setting the SDAHT bit selects a longer 300 ns mini-
mum hold time and may help on buses with large
capacitance.
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TABLE 23-2: I2C BUS TERMS
23.4.5 START CONDITION
The I2C specification defines a Start condition as a
transition of SDAx from a high to a low state while
SCLx line is high. A Start condition is always gener-
ated by the master and signifies the transition of the
bus from an Idle to an Active state. Figure 23-10
shows wave forms for Start and Stop conditions.
TERM
Description
Transmitter
The device which shifts data out
onto the bus.
Receiver
Master
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
A bus collision can occur on a Start condition if the
module samples the SDAx line low before asserting it
low. This does not conform to the I2C Specification that
states no bus collision can occur on a Start.
Slave
The device addressed by the mas-
ter.
Multi-master
Arbitration
A bus with more than one device
that can initiate data transfers.
23.4.6 STOP CONDITION
A Stop condition is a transition of the SDAx line from
low-to-high state while the SCLx line is high.
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
Note: At least one SCLx low time must appear
before a Stop is valid, therefore, if the SDAx
line goes low then high again while the SCLx
line stays high, only the Start condition is
detected.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDAx and SCLx lines are
high.
23.4.7
RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPxADD.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
Write Request
Read Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condi-
tion, a high address with R/W clear, or high address
match fails.
Clock Stretching When a device on the bus holds
SCLx low to stall communication.
23.4.8 START/STOP CONDITION INTERRUPT
MASKING
Bus Collision
Any time the SDAx line is sampled
low by the module while it is out-
putting and expected high state.
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
DS41414A-page 248
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FIGURE 23-12:
I2C START AND STOP CONDITIONS
SDAx
SCLx
S
P
Change of
Change of
Data Allowed
Data Allowed
Stop
Start
Condition
Condition
FIGURE 23-13:
I2C RESTART CONDITION
Sr
Change of
Change of
Data Allowed
Data Allowed
Restart
Condition
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23.5 I2C SLAVE MODE OPERATION
23.4.9 ACKNOWLEDGE SEQUENCE
The 9th SCLx pulse for any transferred byte in I2C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDAx line low. The transmitter must release con-
trol of the line during this time to shift in the response.
The Acknowledge (ACK) is an active-low signal, pull-
ing the SDAx line low indicated to the transmitter that
the device has received the transmitted data and is
ready to receive more.
The MSSPx Slave mode operates in one of four
modes selected in the SSPxM bits of SSPxCON1 reg-
ister. The modes can be divided into 7-bit and 10-bit
Addressing mode. 10-bit Addressing modes operate
the same as 7-bit with some additional overhead for
handling the larger addresses.
Modes with Start and Stop bit interrupts operated the
same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
condition.
The result of an ACK is placed in the ACKSTAT bit of
the SSPxCON2 register.
23.5.1 SLAVE MODE ADDRESSES
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPxCON2 reg-
ister is set/cleared to determine the response.
The SSPxADD register (Register 23-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPxBUF register and an
interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the soft-
ware that anything happened.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPxCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPxSTAT regis-
ter or the SSPxOV bit of the SSPxCON1 register are
set when a byte is received.
The SSPx Mask register (Register 23-5) affects the
address matching process. See Section 23.5.9
“SSPx Mask Register” for more information.
When the module is addressed, after the 8th falling
edge of SCLx on the bus, the ACKTIM bit of the
SSPxCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
23.5.1.1 I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
23.5.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte, the UA bit is
set and SCLx is held low until the user updates
SSPxADD with the low address. The low address byte
is clocked in and all 8 bits are compared to the low
address value in SSPxADD. Even if there is not an
address match; SSPxIF and UA are set, and SCLx is
held low until SSPxADD is updated to receive a high
byte again. When SSPxADD is updated, the UA bit is
cleared. This ensures the module is ready to receive
the high address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hard-
ware will then acknowledge the read request and pre-
pare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
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23.5.2 SLAVE RECEPTION
23.5.2.2 7-bit Reception with AHEN and DHEN
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPxSTAT register is
cleared. The received address is loaded into the
SSPxBUF register and acknowledged.
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th fall-
ing edge of SCLx. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF bit of the
SSPxSTAT register is set, or bit SSPxOV bit of the
SSPxCON1 register is set. The BOEN bit of the
SSPxCON3 register modifies this operation. For more
information see Register 23-4.
This list describes the steps that need to be taken by
slave software to use these options for I2C communi-
cation. Figure 23-15 displays a module using both
address and data holding. Figure 23-16 includes the
operation with the SEN bit of the SSPxCON2 register
set.
An MSSPx interrupt is generated for each transferred
data byte. Flag bit, SSPxIF, must be cleared by
software.
1. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
When the SEN bit of the SSPxCON2 register is set,
SCLx will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSPxCON1 register, except
sometimes in 10-bit mode. See Section 23.2.3 “SPI
Master Mode” for more detail.
2. Matching address with R/W bit clear is clocked
in. SSPxIF is set and CKP cleared after the 8th
falling edge of SCLx.
3. Slave clears the SSPxIF.
4. Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if the SSPxIF
was after or before the ACK.
23.5.2.1 7-bit Addressing Reception
This section describes a standard sequence of events
for the MSSPx module configured as an I2C Slave in
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 23-13 and Figure 23-14 is used as a visual
reference for this description.
5. Slave reads the address value from SSPxBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
This is a step by step process of what typically must
be done to accomplish I2C communication.
8. SSPxIF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
1. Start bit detected.
clock after the ACK.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
10. Slave clears SSPxIF.
Note: SSPxIF is still set after the 9th falling edge of
SCLx even if there is no clock stretching and
BF has been cleared. Only if NACK is sent to
Master is SSPxIF not set
3. Matching address with R/W bit clear is received.
4. The slave pulls SDAx low sending an ACK to the
master, and sets SSPxIF bit.
5. Software clears the SSPxIF bit.
11. SSPxIF set and CKP cleared after 8th falling
edge of SCLx for a received data byte.
6. Software reads received address from
SSPxBUF clearing the BF flag.
12. Slave looks at ACKTIM bit of SSPxCON3 to
determine the source of the interrupt.
7. If SEN = 1; Slave software sets CKP bit to
release the SCLx line.
13. Slave reads the received data from SSPxBUF
clearing BF.
8. The master clocks out a data byte.
9. Slave drives SDAx low sending an ACK to the
master, and sets SSPxIF bit.
14. Steps 7-14 are the same for each received data
byte.
10. Software clears SSPxIF.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
11. Software reads the received byte from
SSPxBUF clearing BF.
12. Steps 8-12 are repeated for all received bytes
from the Master.
13. Master sends Stop condition, setting P bit of
SSPxSTAT, and the bus goes idle.
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FIGURE 23-14:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
DS41414A-page 252
Preliminary
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FIGURE 23-15:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 253
PIC16F/LF1946/47
FIGURE 23-16:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
DS41414A-page 254
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FIGURE 23-17:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 255
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23.5.3
SLAVE TRANSMISSION
23.5.3.2
7-bit Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish
a
standard transmission.
Figure 23-17 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit
and the SCLx pin is held low (see Section 23.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1. Master sends a Start condition on SDAx and
SCLx.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
3. Matching address with R/W bit set is received by
the Slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPxSR register. Then
the SCLx pin should be released by setting the CKP bit
of the SSPxCON1 register. The eight data bits are
shifted out on the falling edge of the SCLx input. This
ensures that the SDAx signal is valid during the SCLx
high time.
4. Slave hardware generates an ACK and sets
SSPxIF.
5. SSPxIF bit is cleared by user.
6. Software reads the received address from
SSPxBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes idle and waits for
another occurrence of the Start bit. If the SDAx line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, the SCLx pin must be
released by setting bit CKP.
8. The slave software loads the transmit data into
SSPxBUF.
9. CKP bit is set releasing SCLx, allowing the
master to clock the data out of the slave.
10. SSPxIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPxIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
An MSSPx interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCLx (9th) rather than the
falling.
23.5.3.1
Slave Mode Bus Collision
13. Steps 9-13 are repeated for each transmitted
byte.
A slave receives a Read request and begins shifting
data out on the SDAx line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCLxIF bit of the PIRx register is set. Once a bus
collision is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLxIF bit
to handle a slave bus collision.
14. If the master sends a not ACK; the clock is not
held, but SSPxIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
DS41414A-page 256
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 23-18:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 257
PIC16F/LF1946/47
23.5.3.3
7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSPxIF interrupt is
set.
Figure 23-18 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCLx line the
CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCLx.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCLx pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCLx
line to receive a Stop.
DS41414A-page 258
Preliminary
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FIGURE 23-19:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
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23.5.4 SLAVE MODE 10-BIT ADDRESS
RECEPTION
23.5.5 10-BIT ADDRESSING WITH ADDRESS OR
DATA HOLD
This section describes a standard sequence of events
for the MSSPx module configured as an I2C Slave in
10-bit Addressing mode.
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPxADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCLx line is held low are the
same. Figure 23-20 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 23-19 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
Figure 23-21 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
1. Bus starts Idle.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCLx.
8. Master sends matching low address byte to the
Slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
9. Slave sends ACK and SSPxIF is set.
Note: If the low address does not match, SSPxIF
and UA are still set so that the slave software
can set SSPxADD back to the high address.
BF is not set because there is no match.
CKP is unaffected.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
from SSPxBUF clearing BF.
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCLx
pulse; SSPxIF is set.
14. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCLx.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS41414A-page 260
Preliminary
2010 Microchip Technology Inc.
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FIGURE 23-20:
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 261
PIC16F/LF1946/47
FIGURE 23-21:
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
DS41414A-page 262
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 23-22:
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
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23.5.6 CLOCK STRETCHING
23.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus
holds the SCLx line low effectively pausing communi-
cation. The slave may stretch the clock to allow more
time to handle data or prepare a response for the mas-
ter device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and han-
dled by the hardware that generates SCLx.
In 10-bit Addressing mode, when the UA bit is set, the
clock is always stretched. This is the only time the
SCLx is stretched without CKP being cleared. SCLx is
released immediately after a write to SSPxADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
23.5.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to con-
trol stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCLx line to go
low and then hold it. Setting CKP will release SCLx
and allow more communication.
When AHEN bit of SSPxCON3 is set; CKP is cleared
by hardware after the 8th falling edge of SCLx for a
received matching address byte. When DHEN bit of
SSPxCON3 is set; CKP is cleared after the 8th falling
edge of SCLx for received data.
23.5.6.1 Normal Clock Stretching
Stretching after the 8th falling edge of SCLx allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
Following an ACK if the R/W bit of SSPxSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
23.5.7 CLOCK SYNCHRONIZATION AND
THE CKP BIT
Any time the CKP bit is cleared, the module will wait
for the SCLx line to go low and then hold it. However,
clearing the CKP bit will not assert the SCLx output
low until the SCLx output is already sampled low.
Therefore, the CKP bit will not assert the SCLx line
until an external I2C master device has already
asserted the SCLx line. The SCLx output will remain
low until the CKP bit is set and all other devices on the
I2C bus have released SCLx. This ensures that a write
to the CKP bit will not violate the minimum high time
requirement for SCLx (see Figure 23-22).
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPxBUF was read before the 9th falling
edge of SCLx.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPxBUF was loaded before the 9th fall-
ing edge of SCLx. It is now always cleared
for read requests.
FIGURE 23-23:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
SCLx
DX
DX ‚ – 1
Master device
asserts clock
CKP
Master device
releases clock
WR
SSPxCON1
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23.5.8 GENERAL CALL ADDRESS SUPPORT
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
If the AHEN bit of the SSPxCON3 register is set, just
as with any other address reception, the slave hard-
ware will stretch the clock after the 8th falling edge of
SCLx. The slave must then set its ACKDT value and
release the clock with communication progressing as it
would normally.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPxCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPxBUF and respond.
Figure 23-23 shows
sequence.
a
general call reception
FIGURE 23-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
ACK
General Call Address
SDAx
D7 D6
D0
8
SCLx
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
’1’
23.5.9 SSPX MASK REGISTER
An SSPx Mask (SSPxMSK) register (Register 23-5) is
available in I2C Slave mode as a mask for the value
held in the SSPxSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSPx operation until written with a mask value.
The SSPx Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSPx mask has no effect during the
reception of the first (high) byte of the address.
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23.6.1 I2C MASTER MODE OPERATION
2
23.6 I C MASTER MODE
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode is enabled by setting and clearing the
appropriate SSPxM bits in the SSPxCON1 register and
by setting the SSPxEN bit. In Master mode, the SCLx
and SDAx lines are set as inputs and are manipulated
by the MSSPx hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSPx module is disabled. Con-
trol of the I2C bus may be taken when the P bit is set,
or the bus is Idle.
In Master Transmitter mode, serial data is output
through SDAx, while SCLx outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDAx and SCLx lines.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDAx, while SCLx outputs
the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
The following events will cause the SSPx Interrupt Flag
bit, SSPxIF, to be set (SSPx interrupt, if enabled):
• Start condition detected
• Stop condition detected
• Data transfer byte transmitted/received
• Acknowledge transmitted/received
• Repeated Start generated
A Baud Rate Generator is used to set the clock
frequency output on SCLx. See Section 23.7 “Baud
Rate Generator” for more detail.
Note 1: The MSSPx module, when configured in
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.
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23.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<7:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 23-25).
FIGURE 23-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDAx
DX
DX ‚ – 1
SCLx deasserted but slave holds
SCLx low (clock arbitration)
SCLx allowed to transition high
SCLx
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCLx is sampled high, reload takes
place and BRG starts its count
BRG
Reload
23.6.3 WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write doesn’t occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not Idle.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
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23.6.4 I C MASTER MODE START
by hardware; the Baud Rate Generator is suspended,
leaving the SDAx line held low and the Start condition
is complete.
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPxCON2 register. If the
SDAx and SCLx pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPxADD<7:0> and starts its count. If SCLx and
SDAx are both sampled high when the Baud Rate
Generator times out (TBRG), the SDAx pin is driven
low. The action of the SDAx being driven low while
SCLx is high is the Start condition and causes the S bit
of the SSPxSTAT1 register to be set. Following this,
the Baud Rate Generator is reloaded with the contents
of SSPxADD<7:0> and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
Note 1: If at the beginning of the Start condition,
the SDAx and SCLx pins are already sam-
pled low, or if during the Start condition,
the SCLx line is sampled low before the
SDAx line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLxIF, is set, the Start condition is
aborted and the I2C module is reset into its
Idle state.
2: The Philips I2C Specification states that a
bus collision cannot occur on a Start.
FIGURE 23-26:
FIRST START BIT TIMING
Set S bit (SSPxSTAT<3>)
Write to SEN bit occurs here
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
SDAx = 1,
SCLx = 1
TBRG
TBRG
Write to SSPxBUF occurs here
SDAx
2nd bit
1st bit
TBRG
SCLx
S
TBRG
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23.6.5 I C MASTER MODE REPEATED
SSPxCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDAx pin held low. As soon as a Start condition is
detected on the SDAx and SCLx pins, the S bit of the
SSPxSTAT register will be set. The SSPxIF bit will not
be set until the Baud Rate Generator has timed out.
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSPxCON2 register is programmed high and the
Master state machine is no longer active. When the
RSEN bit is set, the SCLx pin is asserted low. When the
SCLx pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDAx pin is released
(brought high) for one Baud Rate Generator count
(TBRG). When the Baud Rate Generator times out, if
SDAx is sampled high, the SCLx pin will be deasserted
(brought high). When SCLx is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDAx
and SCLx must be sampled high for one TBRG. This
action is then followed by assertion of the SDAx pin
(SDAx = 0) for one TBRG while SCLx is high. SCLx is
asserted low. Following this, the RSEN bit of the
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDAx is sampled low when SCLx
goes from low-to-high.
• SCLx goes low before SDAx is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 23-27:
REPEAT START CONDITION WAVEFORM
S bit set by hardware
Write to SSPxCON2
occurs here
SDAx = 1,
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
SDAx = 1,
SCLx = 1
SCLx (no change)
TBRG
TBRG
TBRG
1st bit
SDAx
SCLx
Write to SSPxBUF occurs here
TBRG
Sr
Repeated Start
TBRG
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23.6.6 I2C MASTER MODE TRANSMISSION
23.6.6.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPxCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDAx pin after the falling edge of SCLx is
asserted. SCLx is held low for one Baud Rate Genera-
tor rollover count (TBRG). Data should be valid before
SCLx is released high. When the SCLx pin is released
high, it is held that way for TBRG. The data on the SDAx
pin must remain stable for that duration and some hold
time after the next falling edge of SCLx. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDAx.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPxIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPxBUF, leaving SCLx low and
SDAx unchanged (Figure 23-27).
23.6.6.4 Typical transmit sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
3. SSPxIF is cleared by software.
4. The MSSPx module will wait the required start
time before any other operation takes place.
5. The user loads the SSPxBUF with the slave
address to transmit.
6. Address is shifted out the SDAx pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPxBUF is written to.
7. The MSSPx module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
8. The MSSPx module generates an interrupt at
the end of the ninth clock cycle by setting the
SSPxIF bit.
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCLx until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDAx pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDAx pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT Status bit of the
SSPxCON2 register. Following the falling edge of the
ninth clock transmission of the address, the SSPxIF is
set, the BF flag is cleared and the Baud Rate Generator
is turned off until another write to the SSPxBUF takes
place, holding SCLx low and allowing SDAx to float.
9. The user loads the SSPxBUF with eight bits of
data.
10. Data is shifted out the SDAx pin until all 8 bits
are transmitted.
11. The MSSPx module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPxCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
23.6.6.1
BF Status Flag
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all 8 bits are shifted out.
23.6.6.2
WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared by software before the next
transmission.
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FIGURE 23-28:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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I2C MASTER MODE RECEPTION
23.6.7.4 Typical Receive Sequence:
23.6.7
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPxCON2
register.
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
Note:
The MSSPx module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
3. SSPxIF is cleared by software.
4. User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCLx pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPxSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPxSR are loaded into the SSPxBUF, the
BF flag bit is set, the SSPxIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCLx low. The MSSPx is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPxCON2 register.
5. Address is shifted out the SDAx pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPxBUF is written to.
6. The MSSPx module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
7. The MSSPx module generates an interrupt at
the end of the ninth clock cycle by setting the
SSPxIF bit.
8. User sets the RCEN bit of the SSPxCON2 regis-
ter and the Master clocks in a byte from the slave.
9. After the 8th falling edge of SCLx, SSPxIF and
BF are set.
10. Master clears SSPxIF and reads the received
byte from SSPxUF, clears BF.
23.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
11. Master sets ACK value sent to slave in ACKDT
bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
23.6.7.2
SSPxOV Status Flag
12. Masters ACK is clocked out to the Slave and
SSPxIF is set.
In receive operation, the SSPxOV bit is set when 8 bits
are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
13. User clears SSPxIF.
14. Steps 8-13 are repeated for each received byte
from the slave.
23.6.7.3
WCOL Status Flag
15. Master sends a not ACK or Stop to end
communication.
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur).
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FIGURE 23-29:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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23.6.8
ACKNOWLEDGE SEQUENCE
TIMING
23.6.9
STOP CONDITION TIMING
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPxCON2 register. At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit of the
SSPxSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 23-30).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPxCON2 register. When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCLx pin is deasserted (pulled high).
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCLx pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSPx module then goes into Idle mode
(Figure 23-29).
23.6.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
23.6.8.1
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 23-30:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPxCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDAx
SCLx
D0
8
9
SSPxIF
Cleared in
SSPxIF set at
the end of receive
software
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
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FIGURE 23-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCLx = 1for TBRG, followed by SDAx = 1for TBRG
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
Write to SSPxCON2,
set PEN
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
Falling edge of
9th clock
TBRG
SCLx
ACK
SDAx
P
TBRG
TBRG
TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
23.6.10 SLEEP OPERATION
23.6.13 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSPx interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
outputs a ‘1’ on SDAx, by letting SDAx float high and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx pin is
‘0’, then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLxIF, and reset
the I2C port to its Idle state (Figure 23-31).
23.6.11 EFFECTS OF A RESET
A Reset disables the MSSPx module and terminates
the current transfer.
23.6.12 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSPx module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPxSTAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSPx interrupt will
generate the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume communica-
tion by asserting a Start condition.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLxIF bit.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred, the
condition is aborted, the SDAx and SCLx lines are deas-
serted and the respective control bits in the SSPxCON2
register are cleared. When the user services the bus col-
lision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 275
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FIGURE 23-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDAx. While SCLx is high,
data doesn’t match what is driven
by the master.
Data changes
while SCLx = 0
SDAx line pulled low
by another source
Bus collision has occurred.
SDAx released
by master
SDAx
SCLx
Set bus collision
interrupt (BCLxIF)
BCLxIF
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If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 23-34). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to zero; if the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
23.6.13.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDAx or SCLx are sampled low at the beginning
of the Start condition (Figure 23-32).
b) SCLx is sampled low before SDAx is asserted
low (Figure 23-33).
During a Start condition, both the SDAx and the SCLx
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted,
• the BCLxIF flag is set and
•
the MSSPx module is reset to its Idle state
(Figure 23-32).
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the Baud Rate Generator is loaded and counts down. If
the SCLx pin is sampled low while SDAx is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 23-33:
BUS COLLISION DURING START CONDITION (SDAX ONLY)
SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx
SCLx
SEN
Set SEN, enable Start
condition if SDAx = 1, SCLx = 1
SEN cleared automatically because of bus collision.
SSPx module reset into Idle state.
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
BCLxIF
SSPxIF and BCLxIF are
cleared by software
S
SSPxIF
SSPxIF and BCLxIF are
cleared by software
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FIGURE 23-34:
BUS COLLISION DURING START CONDITION (SCLX = 0)
SDAx = 0, SCLx = 1
TBRG
TBRG
SDAx
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
SCLx
SEN
SCLx = 0before SDAx = 0,
bus collision occurs. Set BCLxIF.
SCLx = 0before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
by software
S
’0’
’0’
’0’
’0’
SSPxIF
FIGURE 23-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S
Set SSPxIF
Less than TBRG
TBRG
SDAx pulled low by other master.
Reset BRG and assert SDAx.
SDAx
SCLx
S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
’0’
BCLxIF
S
SSPxIF
Interrupts cleared
by software
SDAx = 0, SCLx = 1,
set SSPxIF
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If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 23-35).
If SDAx is sampled high, the BRG is reloaded and
begins counting. If SDAx goes from high-to-low before
the BRG times out, no bus collision occurs because no
two masters can assert SDAx at exactly the same time.
23.6.13.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDAx when SCLx
goes from low level to high level.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition, see Figure 23-36.
b) SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user releases SDAx and the pin is allowed to
float high, the BRG is loaded with SSPxADD and
counts down to zero. The SCLx pin is then deasserted
and when sampled high, the SDAx pin is sampled.
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
FIGURE 23-36:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDAx
SCLx
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
RSEN
BCLxIF
Cleared by software
’0’
S
’0’
SSPxIF
FIGURE 23-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDAx
SCLx
SCLx goes low before SDAx,
BCLxIF
RSEN
set BCLxIF. Release SDAx and SCLx.
Interrupt cleared
by software
’0’
S
SSPxIF
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The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPxADD and
counts down to 0. After the BRG times out, SDAx is
sampled. If SDAx is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 23-37). If the SCLx pin is
sampled low before SDAx is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 23-38).
23.6.13.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
b) After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
FIGURE 23-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDAx sampled
low after TBRG,
set BCLxIF
TBRG
TBRG
TBRG
SDAx
SDAx asserted low
SCLx
PEN
BCLxIF
P
’0’
’0’
SSPxIF
FIGURE 23-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDAx
SCLx goes low before SDAx goes high,
set BCLxIF
Assert SDAx
SCLx
PEN
BCLxIF
P
’0’
’0’
SSPxIF
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TABLE 23-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Valueson
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIE1
GIE
TMR1GIE
OSFIE
—
PEIE
ADIE
C2IE
—
TMR0IE
RCIE
C1IE
—
INTE
TXIE
EEIE
—
IOCIE
SSP1IE
BCL1IE
—
TMR0IF
CCP1IE
—
INTF
TMR2IE
—
IOCIF
89
90
TMR1IE
(1)
PIE2
CCP2IE
SSP2IE
TMR1IF
91
(1)
BCL2IE
TMR2IF
—
PIE4
—
CCP1IF
—
93
TMR1GIF
OSFIF
ADIF
C2IF
RCIF
C1IF
TXIF
EEIF
SSP1IF
BCL1IF
PIR1
PIR2
94
(1)
CCP2IF
SSP2IF
TRISA0
TRISB0
95
(1)
BCL2IF
TRISA1
TRISB1
PIR4
—
—
—
—
—
—
97
TRISA
TRISA7
TRISB7
TRISA6
TRISB6
TRISA5
TRISB5
TRISA4
TRISB4
TRISA3
TRISB3
TRISA2
TRISB2
124
127
287
239*
284
285
286
287
283
TRISB
SSPxADD
SSPxBUF
SSPxCON1
SSPxCON2
SSPxCON3
SSPxMSK
SSPxSTAT
ADD<7:0>
MSSPx Receive Buffer/Transmit Register
WCOL
GCEN
SSPOV
ACKSTAT
PCIE
SSPEN
ACKDT
SCIE
CKP
ACKEN
BOEN
SSPM<3:0>
RCEN
PEN
RSEN
AHEN
SEN
ACKTIM
SDAHT
SBCDE
DHEN
MSK<7:0>
SMP
CKE
D/A
P
S
R/W
UA
BF
2
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I C™ mode.
*
Page provides register information.
Note 1: PIC16F1947 only.
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module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSPx is
being operated in.
23.7 BAUD RATE GENERATOR
The MSSPx module has a Baud Rate Generator avail-
able for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 23-6).
When a write occurs to SSPxBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Table 23-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
EQUATION 23-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
FOSC
FCLOCK = -------------------------------------------------
SSPxADD + 14
An internal signal “Reload” in Figure 23-39 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 23-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPxM<3:0>
SSPxADD<7:0>
SSPxM<3:0>
SCLx
Reload
Control
Reload
BRG Down Counter
SSPxCLK
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 23-4: MSSPx CLOCK RATE W/BRG
FCLOCK
(2 Rollovers of BRG)
FOSC
FCY
BRG Value
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
13h
19h
4Fh
09h
0Ch
27h
09h
400 kHz(1)
308 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
100 kHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS41414A-page 282
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REGISTER 23-1: SSPxSTAT: SSPx STATUS REGISTER
R/W-0/0
SMP
R/W-0/0
CKE
R-0/0
D/A
R-0/0
P
R-0/0
S
R-0/0
R/W
R-0/0
UA
R-0/0
BF
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
2
In I C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
2
In I C™ mode only:
1= Enable input logic so that thresholds are compliant with SMBus specification
0= Disable SMBus specific inputs
2
bit 5
bit 4
D/A: Data/Address bit (I C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: Stop bit
2
(I C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)
1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0= Stop bit was not detected last
bit 3
bit 2
S: Start bit
2
(I C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)
1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0= Start bit was not detected last
2
R/W: Read/Write bit information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
2
In I C Slave mode:
1= Read
0= Write
2
In I C Master mode:
1= Transmit is in progress
0= Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode.
2
bit 1
bit 0
UA: Update Address bit (10-bit I C mode only)
1= Indicates that the user needs to update the address in the SSPxADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes):
1= Receive complete, SSPxBUF is full
0= Receive not complete, SSPxBUF is empty
2
Transmit (I C mode only):
1= Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full
0= Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty
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REGISTER 23-2: SSPxCON1: SSPx CONTROL REGISTER 1
R/C/HS-0/0
WCOL
R/C/HS-0/0
SSPxOV
R/W-0/0
SSPxEN
R/W-0/0
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware C = User cleared
bit 7
WCOL: Write Collision Detect bit
Master mode:
1= A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0= No collision
Slave mode:
1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0= No collision
bit 6
SSPxOV: Receive Overflow Indicator bit(1)
In SPI mode:
1= A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
0= No overflow
In I2C mode:
1= A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode
(must be cleared in software).
0= No overflow
bit 5
SSPxEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2)
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3)
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
In I2C Slave mode:
SCLx release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPxM<3:0>: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0101= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1000= I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4)
1001= Reserved
1010= SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))
1011= I2C firmware controlled Master mode (Slave idle)
1100= Reserved
1101= Reserved
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDAx and SCLx pins must be configured as inputs.
SSPxADD values of 0, 1 or 2 are not supported for I2C Mode.
2:
3:
4:
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REGISTER 23-3: SSPxCON2: SSPx CONTROL REGISTER 2
R/W-0/0
GCEN
R-0/0
R/W-0/0
ACKDT
R/S/HS-0/0 R/S/HS-0/0
ACKEN RCEN
R/S/HS-0/0
PEN
R/S/HS-0/0 R/W/HS-0/0
RSEN SEN
bit 0
ACKSTAT
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware S = User set
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (in I2C Slave mode only)
1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1= Acknowledge was not received
0= Acknowledge was received
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1= Not Acknowledge
0= Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
bit 3
bit 2
RCEN: Receive Enable bit (in I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKx Release Control:
1= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Stop condition Idle
bit 1
bit 0
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
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REGISTER 23-4: SSPxCON3: SSPx CONTROL REGISTER 3
R-0/0
R/W-0/0
PCIE
R/W-0/0
SCIE
R/W-0/0
BOEN
R/W-0/0
SDAHT
R/W-0/0
SBCDE
R/W-0/0
AHEN
R/W-0/0
DHEN
ACKTIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)
1= Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCLx clock
0= Not an Acknowledge sequence, cleared on 9TH rising edge of SCLx clock
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Stop condition
0= Stop detection interrupts are disabled(2)
SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Start or Restart conditions
0= Start detection interrupts are disabled(2)
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1= SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0= If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the
SSPxCON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
This bit is ignored.
In I2C Slave mode:
1= SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the
state of the SSPxOV bit only if the BF bit = 0.
0= SSPxBUF is only updated when SSPxOV is clear
bit 3
bit 2
SDAHT: SDAx Hold Time Selection bit (I2C mode only)
1= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCLxIF bit of the PIR2 register is set, and bus goes idle
1= Enable slave bus collision interrupts
0= Slave bus collision interrupts are disabled
bit 1
bit 0
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the
SSPxCON1 register will be cleared and the SCLx will be held low.
0= Address holding is disabled
DHEN: Data Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
of the SSPxCON1 register and SCLx is held low.
0= Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
DS41414A-page 286
Preliminary
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PIC16F/LF1946/47
REGISTER 23-5: SSPxMSK: SSPx MASK REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-1
bit 0
MSK<7:1>: Mask bits
1= The received address bit n is compared to SSPxADD<n> to detect I2C address match
0= The received address bit n is not used to detect I2C address match
MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPxM<3:0> = 0111or 1111):
1= The received address bit 0 is compared to SSPxADD<0> to detect I2C address match
0= The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 23-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
Master mode:
bit 7-0
ADD<7:0>: Baud Rate Clock Divider bits
SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode – Most Significant Address byte:
bit 7-3
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
ADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address byte:
bit 7-0
ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1
bit 0
ADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 287
PIC16F/LF1946/47
NOTES:
DS41414A-page 288
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
24.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
Note:
The PIC16F/LF/1946/47 devices have two
EUSARTs. Therefore, all information in
this section refers to both EUSART 1 and
EUSART 2.
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
• Programmable clock and data polarity
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
system.
Full-Duplex
mode
is
useful
for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 24-1 and Figure 24-2.
FIGURE 24-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXxIE
Interrupt
TXxIF
TXxREG Register
8
TXx/CKx pin
MSb
(8)
LSb
0
Pin Buffer
and Control
• • •
Transmit Shift Register (TSR)
TXEN
TRMT
Baud Rate Generator
BRG16
FOSC
÷ n
TX9
n
+ 1
Multiplier x4
x16 x64
TX9D
SYNC
BRGH
BRG16
1
X
X
X
1
1
0
1
0
0
0
1
0
0
0
SPxBRGH SPxBRGL
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 289
PIC16F/LF1946/47
FIGURE 24-2:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
RCIDL
RXx/DTx pin
RSR Register
MSb
Stop (8)
LSb
0
START
Pin Buffer
and Control
Data
Recovery
7
1
• • •
Baud Rate Generator
FOSC
RX9
÷ n
BRG16
n
+ 1
Multiplier
x4
x16 x64
SYNC
BRGH
BRG16
1
X
1
1
0
1
0
0
0
1
0
0
0
FIFO
SPxBRGH SPxBRGL
X
X
RX9D
FERR
RCxREG Register
8
Data Bus
RCxIF
RCxIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXxSTA)
• Receive Status and Control (RCxSTA)
• Baud Rate Control (BAUDxCON)
These registers are detailed in Register 24-1,
Register 24-2 and Register 24-3, respectively.
For all modes of EUSART operation, the TRIS control
bits corresponding to the RXx/DTx and TXx/CKx pins
should be set to ‘1’. The EUSART control will
automatically reconfigure the pin from input to output, as
needed.
When the receiver or transmitter section is not enabled
then the corresponding RXx/DTx or TXx/CKx pin may be
used for general purpose input and output.
DS41414A-page 290
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24.1.1.2
Transmitting Data
24.1 EUSART Asynchronous Mode
A transmission is initiated by writing a character to the
TXxREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXxREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXxREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXxREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXxREG.
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 24-5
for examples of baud rate configurations.
24.1.1.3
Transmit Data Polarity
The polarity of the transmit data can be controlled with
the CKTXP bit of the BAUDxCON register. The default
state of this bit is ‘0’ which selects high true transmit
idle and data bits. Setting the CKTXP bit to ‘1’ will invert
the transmit data resulting in low true idle and data bits.
The CKTXP bit controls transmit data polarity only in
Asynchronous mode. In Synchronous mode the
CKTXP bit has a different function.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
24.1.1.4
Transmit Interrupt Flag
24.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
The TXxIF interrupt flag bit of the PIR1/PIR3 register is
set whenever the EUSART transmitter is enabled and
no character is being held for transmission in the
TXxREG. In other words, the TXxIF bit is only clear
when the TSR is busy with a character and a new
character has been queued for transmission in the
TXxREG. The TXxIF flag bit is not cleared immediately
upon writing TXxREG. TXxIF becomes valid in the
second instruction cycle following the write execution.
Polling TXxIF immediately following the TXxREG write
will return invalid results. The TXxIF bit is read-only, it
cannot be set or cleared by software.
The EUSART transmitter block diagram is shown in
Figure 24-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXxREG register.
24.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
The TXxIF interrupt can be enabled by setting the
TXxIE interrupt enable bit of the PIE1/PIE3 register.
However, the TXxIF flag bit will be set whenever the
TXxREG is empty, regardless of the state of TXxIE
enable bit.
All other EUSART control bits are assumed to be in
their default state.
To use interrupts when transmitting data, set the TXxIE
bit only when there is more data to send. Clear the
TXxIE interrupt enable bit upon writing the last
character of the transmission to the TXxREG.
Setting the TXEN bit of the TXxSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXxSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART. The program-
mer must set the corresponding TRIS bit to configure the
TX/CK I/O pin as an output. If the TXx/CKx pin is shared
with an analog peripheral, the analog I/O function must
be disabled by clearing the corresponding ANSEL bit.
Note:
The TXxIF transmitter interrupt flag is set
when the TXEN enable bit is set.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 291
PIC16F/LF1946/47
24.1.1.5
TSR Status
24.1.1.7
Asynchronous Transmission Set-up:
The TRMT bit of the TXxSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXxREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user needs to
poll this bit to determine the TSR status.
1. Initialize the SPxBRGH:SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 24.3 “EUSART
Baud Rate Generator (BRG)”).
2. Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
3. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
4. If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the 8 Least Significant data bits are an address
when the receiver is set for address detection.
24.1.1.6
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXxSTA register is set the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXxSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXxREG. All nine
bits of data will be transferred to the TSR shift register
immediately after the TXxREG is written.
5. Set the CKTXP control bit if inverted transmit
data polarity is desired.
6. Enable the transmission by setting the TXEN
control bit. This will cause the TXxIF interrupt bit
to be set.
7. If interrupts are desired, set the TXxIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 24.1.2.8 “Address
Detection” for more information on the Address mode.
8. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
9. Load 8-bit data into the TXxREG register. This
will start the transmission.
FIGURE 24-3:
ASYNCHRONOUS TRANSMISSION
Write to TXxREG
Word 1
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS41414A-page 292
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 24-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXxREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TXx/CKx
pin
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
Word 2
1 TCY
Word 1
TXxIF bit
(Interrupt Reg. Flag)
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg
Transmit Shift Reg
Note:
This timing diagram shows two consecutive transmissions.
TABLE 24-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON ABDOVF
BAUD2CON ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
ABDEN
ABDEN
IOCIF
300
300
89
—
INTCON
PIE1
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TMR0IF
CCP1IE
—
INTF
TX1IE
TX2IE
TX1IF
TX2IF
CREN
CREN
TMR2IE
BCL2IE
TMR2IF
BCL2IF
OERR
OERR
TMR1IE
SSP2IE
TMR1IF
SSP2IF
RX9D
90
PIE4
—
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1STA
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1REG
TX1STA
TX2REG
TX2STA
SPEN
SPEN
RX9
RX9
ADDEN
ADDEN
FERR
FERR
299
299
301*
301*
301*
301*
291*
298
291*
298
RX9D
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
EUSART1 Transmit Register
CSRC
CSRC
TX9
TX9
TXEN
SYNC
EUSART2 Transmit Register
SYNC SENDB
SENDB
BRGH
TRMT
TRMT
TX9D
TX9D
TXEN
BRGH
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 293
PIC16F/LF1946/47
24.1.2
EUSART ASYNCHRONOUS
RECEIVER
24.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 24.1.2.5 “Receive Framing
Error” for more information on framing errors.
The Asynchronous mode would typically be used in
RS-232 systems. The receiver block diagram is shown
in Figure 24-2. The data is received on the RXx/DTx
pin and drives the data recovery block. The data
recovery block is actually
a high-speed shifter
operating at 16 times the baud rate, whereas the serial
Receive Shift Register (RSR) operates at the bit rate.
When all 8 or 9 bits of the character have been shifted
in, they are immediately transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCxREG
register.
24.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCxIF interrupt
flag bit of the PIR1/PIR3 register is set. The top charac-
ter in the FIFO is transferred out of the FIFO by reading
the RCxREG register.
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Note:
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 24.1.2.6
“Receive Overrun Error” for more
information on overrun errors.
Setting the CREN bit of the RCxSTA register enables
the receiver circuitry of the EUSART. Clearing the SYNC
bit of the TXxSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART. The
programmer must set the corresponding TRIS bit to
configure the TX/CK I/O pin as an input.
24.1.2.3
Receive Data Polarity
The polarity of the receive data can be controlled with
the DTRXP bit of the BAUDxCON register. The default
state of this bit is ‘0’ which selects high true receive idle
and data bits. Setting the DTRXP bit to ‘1’ will invert the
receive data resulting in low true idle and data bits. The
DTRXP bit controls receive data polarity only in
Asynchronous mode. In synchronous mode the
DTRXP bit has a different function.
Note 1: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
If the RXx/DTx pin is shared with an analog peripheral
the analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
DS41414A-page 294
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
24.1.2.4
Receive Interrupts
24.1.2.7
Receiving 9-bit Characters
The RCxIF interrupt flag bit of the PIR1/PIR3 register is
set whenever the EUSART receiver is enabled and
there is an unread character in the receive FIFO. The
RCxIF interrupt flag bit is read-only, it cannot be set or
cleared by software.
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set, the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCxSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCxREG.
RCxIF interrupts are enabled by setting the following
bits:
• RCxIE interrupt enable bit of the PIE1/PIE3
register
24.1.2.8
Address Detection
• PEIE peripheral interrupt enable bit of the INTCON
register
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCxSTA
register.
• GIE global interrupt enable bit of the INTCON
register
The RCxIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCxIF interrupt
bit. All other characters will be ignored.
24.1.2.5
Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCxSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCxREG.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCxSTA register which resets the EUSART.
Clearing the CREN bit of the RCxSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCxREG will not clear the FERR bit.
24.1.2.6
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCxSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCxSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCxSTA register.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 295
PIC16F/LF1946/47
24.1.2.9
Asynchronous Reception Set-up:
24.1.2.10 9-bit Address Detection Mode Set-up
1. Initialize the SPxBRGH:SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 24.3 “EUSART
Baud Rate Generator (BRG)”).
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 24.3 “EUSART
Baud Rate Generator (BRG)”).
2. Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
3. Enable the serial port by setting the SPEN bit
and the RXx/DTx pin TRIS bit. The SYNC bit
must be clear for asynchronous operation.
2. Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
4. If interrupts are desired, set the RCxIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
5. If 9-bit reception is desired, set the RX9 bit.
4. If interrupts are desired, set the RCxIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
6. Set the DTRXP if inverted receive polarity is
desired.
7. Enable reception by setting the CREN bit.
5. Enable 9-bit reception by setting the RX9 bit.
8. The RCxIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCxIE interrupt enable bit was also set.
6. Enable address detection by setting the ADDEN
bit.
7. Set the DTRXP if inverted receive polarity is
desired.
9. Read the RCxSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
8. Enable reception by setting the CREN bit.
9. The RCxIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCxIE interrupt enable
bit was also set.
10. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCxREG
register.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
10. Read the RCxSTA register to get the error flags.
The ninth data bit will always be set.
11. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCxREG
register. Software determines if this is the
device’s address.
12. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
13. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
DS41414A-page 296
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 24-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RXx/DTx pin
bit 7/8
bit 7/8
bit 0 bit 1
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCxREG
Word 1
RCxREG
RCIDL
Read Rcv
Buffer Reg
RCxREG
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
TABLE 24-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON
BAUD2CON
INTCON
PIE1
ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
ABDEN
ABDEN
IOCIF
300
300
89
ABDOVF
—
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
TMR0IF
CCP1IE
—
INTF
TX1IE
TX2IE
TX1IF
TX2IF
TMR2IE
BCL2IE
TMR2IF
BCL2IF
TMR1IE
SSP2IE
TMR1IF
SSP2IF
90
PIE4
—
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TRISC
EUSART1 Receive Register
SREN CREN ADDEN
EUSART2 Receive Register
SREN CREN ADDEN
294*
299
294*
299
301*
301*
301*
301*
130
298
298
SPEN
SPEN
RX9
RX9
FERR
FERR
OERR
OERR
RX9D
RX9D
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
TRISC7
CSRC
CSRC
TRISC6
TX9
TRISC5 TRISC4 TRISC3
TRISC2
BRGH
BRGH
TRISC1
TRMT
TRMT
TRISC0
TX9D
TX1STA
TX2STA
TXEN
TXEN
SYNC
SYNC
SENDB
SENDB
TX9
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 297
PIC16F/LF1946/47
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 5.2
“Clock Source Types” for more information.
24.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (HFINTOSC). However, the HFINTOSC
frequency may drift as VDD or temperature changes,
and this directly affects the asynchronous baud rate.
Two methods may be used to adjust the baud rate
clock, but both require a reference clock source of
some kind.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 24.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 24-1: TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
(1)
TXEN
SENDB
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
(1)
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS41414A-page 298
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
REGISTER 24-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCxREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 299
PIC16F/LF1946/47
REGISTER 24-3: BAUDxCON: BAUD RATE CONTROL REGISTER
R-0/0
R-1/1
U-0
—
R/W-0/0
SCKP
R/W-0/0
BRG16
U-0
—
R/W-0/0
WUE
R/W-0/0
ABDEN
ABDOVF
RCIDL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1= Auto-baud timer overflowed
0= Auto-baud timer did not overflow
Synchronous mode:
Don’t care
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1= Receiver is Idle
0= Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1= Transmit inverted data to the TXx/CKx pin
0= Transmit non-inverted data to the TXx/CKx pin
Synchronous mode:
1= Data is clocked on rising edge of the clock
0= Data is clocked on falling edge of the clock
bit 3
BRG16: 16-bit Baud Rate Generator bit
1= 16-bit Baud Rate Generator is used
0= 8-bit Baud Rate Generator is used
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0= Receiver is operating normally
Synchronous mode:
Don’t care
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0= Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
DS41414A-page 300
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
24.3 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDxCON register selects 16-bit
mode.
EXAMPLE 24-1:
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
The SPxBRGH:SPxBRGL register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the
TXxSTA register and the BRG16 bit of the BAUDxCON
register. In Synchronous mode, the BRGH bit is ignored.
FOSC
Desired Baud Rate = -------------------------------------------------------------------------
64[SPxBRGH:SPxBRG] + 1
Solving for SPxBRGH:SPxBRGL:
FOSC
---------------------------------------------
Example 24-1 provides a sample calculation for deter-
mining the desired baud rate, actual baud rate, and
baud rate % error.
Desired Baud Rate
SPxBRGH: SPxBRGL = --------------------------------------------- – 1
64
16000000
-----------------------
9600
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 24-5. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
= ----------------------- – 1
64
= 25.042 = 25
16000000
ActualBaudRate = --------------------------
6425 + 1
= 9615
Writing a new value to the SPxBRGH, SPxBRGL
register pair causes the BRG timer to be reset (or
cleared). This ensures that the BRG does not wait for a
timer overflow before outputting the new baud rate.
Calc. Baud Rate – Desired Baud Rate
Baud Rate % Error =--------------------------------------------------------------------------------------------
Desired Baud Rate
9615 – 9600
= ---------------------------------- = 0 . 1 6 %
9600
TABLE 24-3: BAUD RATE FORMULAS
Configuration Bits
Baud Rate Formula
BRG/EUSART Mode
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend:
x= Don’t care, n = value of SPxBRGH, SPxBRGL register pair
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 301
PIC16F/LF1946/47
TABLE 24-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Reset
Valueson
page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON
BAUD2CON
RC1STA
ABDOVF
ABDOVF
SPEN
RCIDL
RCIDL
RX9
—
SCKP
SCKP
CREN
CREN
BRG16
BRG16
ADDEN
ADDEN
—
WUE
WUE
ABDEN
ABDEN
RX9D
300
300
299
299
301*
301*
301*
301*
298
—
—
SREN
SREN
FERR
FERR
OERR
OERR
RC2STA
SPEN
RX9
RX9D
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1STA
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
CSRC
CSRC
TX9
TX9
TXEN
TXEN
SYNC
SYNC
SENDB
SENDB
BRGH
BRGH
TRMT
TRMT
TX9D
TX9D
TX2STA
298
Legend:
— = unimplemented, read as ‘0’. Shaded bits are not used by the BRG.
*
Page provides register information.
TABLE 24-5: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 32.000 MHz
FOSC = 18.432 MHz
FOSC = 16.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPxBRGL
SPxBRGL
SPxBRGL
SPxBRGL
value
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Error
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
(decimal)
300
1200
2400
9600
10417
19.2k
57.6k
115.2k
—
—
—
—
—
—
—
—
—
239
119
29
27
14
7
—
1202
2404
9615
10417
19.23k
—
—
—
207
103
25
—
—
0.00
0.00
0.00
-2.42
0.00
0.00
—
—
143
71
17
16
8
1200
2400
9600
10286
19.20k
57.60k
—
0.00
0.00
0.00
-1.26
0.00
0.00
—
0.16
0.16
0.16
0.00
0.16
—
1200
2400
9600
10165
19.20k
57.60k
—
2404
9615
10417
19.23k
55.55k
—
0.16
0.16
0.00
0.16
-3.55
—
207
51
47
25
3
23
12
—
2
—
—
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPxBRGL
SPxBRGL
value
SPxBRGL
value
SPxBRGL
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
0.00
0.00
0.00
0.00
—
300
1200
2400
9600
10417
19.2k
57.6k
115.2k
—
1202
2404
9615
10417
—
—
0.16
0.16
0.16
0.00
—
—
103
51
12
11
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
300
1200
2400
9600
—
191
47
23
5
300
1202
—
0.16
0.16
—
51
12
—
—
—
—
—
—
—
—
10417
—
0.00
—
—
2
—
—
—
—
—
—
19.20k
57.60k
—
0.00
0.00
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
DS41414A-page 302
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 24-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPxBRGL
SPxBRGL
value
SPxBRGL
value
SPxBRGL
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
71
65
35
11
5
300
1200
2400
9600
10417
19.2k
57.6k
115.2k
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9615
10417
19.23k
57.14k
117.64k
0.16
0.00
0.16
-0.79
2.12
207
191
103
34
9600
10378
19.20k
57.60k
115.2k
0.00
-0.37
0.00
0.00
0.00
119
110
59
19
9
9615
10417
19.23k
58.82k
111.1k
0.16
0.00
0.16
2.12
-3.55
103
95
51
16
8
9600
10473
19.20k
57.60k
115.2k
0.00
0.53
0.00
0.00
0.00
16
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPxBRGL
SPxBRGL
value
SPxBRGL
value
SPxBRGL
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
300
1200
2400
9600
10417
19.2k
57.6k
115.2k
—
1202
2404
9615
10417
19.23k
—
—
—
207
103
25
—
—
—
191
95
23
21
11
3
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
—
0.16
0.16
0.16
0.00
0.16
—
1200
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2404
9615
10417
19231
55556
—
0.16
0.16
0.00
0.16
-3.55
—
207
51
47
25
8
2400
9600
23
10473
19.2k
57.60k
115.2k
10417
—
0.00
—
12
—
—
—
—
—
—
—
—
—
—
1
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPxBRGH:
SPxBRGH:
SPxBRGL
(decimal)
SPxBRGH:
SPxBRGL
(decimal)
SPxBRGH:
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
SPxBRGL
(decimal)
SPxBRGL
(decimal)
Error
Error
300
1200
2400
9600
10417
19.2k
57.6k
115.2k
300.0
1200.1
2401
0.00
0.02
-0.04
0.16
0.00
0.16
-0.79
2.12
6666
3332
832
207
191
103
34
300.0
1200
0.00
0.00
0.00
0.00
-0.37
0.00
0.00
0.00
3839
959
479
119
110
59
300.03
1200.5
2398
0.01
0.04
-0.08
0.16
0.00
0.16
2.12
-3.55
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2303
575
287
71
2400
2400
9615
9600
9615
9600
10417
19.23k
57.14k
117.6k
10378
19.20k
57.60k
115.2k
10417
19.23k
58.82k
111.11k
10473
19.20k
57.60k
115.2k
65
51
35
19
16
11
16
9
8
5
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 303
PIC16F/LF1946/47
TABLE 24-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 8.000 MHz
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPxBRGH:
SPxBRGH:
SPxBRGH:
SPxBRGH:
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
SPxBRGL
(decimal)
SPxBRGL
(decimal)
SPxBRGL
(decimal)
SPxBRGL
(decimal)
Error
Error
Error
Error
300
1200
2400
9600
10417
19.2k
57.6k
115.2k
299.9
1199
-0.02
-0.08
0.16
0.16
0.00
0.16
-3.55
—
1666
416
207
51
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
767
191
95
23
21
11
3
300.5
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
2404
9615
10417
19.23k
55556
—
2400
9600
47
23
10473
19.20k
57.60k
115.2k
10417
—
0.00
—
25
12
—
—
—
8
—
—
—
—
—
—
—
1
—
—
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPxBRGH:
SPxBRGH:
SPxBRGH:
SPxBRGH:
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
SPxBRGL
(decimal)
SPxBRGL
(decimal)
SPxBRGL
(decimal)
SPxBRGL
(decimal)
Error
Error
Error
Error
300
1200
2400
9600
10417
19.2k
57.6k
115.2k
300
1200
0.00
0.00
0.01
0.04
0.00
-0.08
-0.08
0.64
26666
6666
3332
832
300.0
1200
0.00
0.00
0.00
0.00
0.08
0.00
0.00
0.00
15359
3839
1919
479
441
239
79
300.0
1200.1
2399.5
9592
0.00
0.01
-0.02
-0.08
0.00
0.16
0.64
-0.79
13332
3332
1666
416
383
207
68
300.0
1200
0.00
0.00
0.00
0.00
0.16
0.00
0.00
0.00
9215
2303
1151
287
264
143
47
2400
2400
2400
9604
9600
9600
10417
19.18k
57.55k
115.9
767
10425
19.20k
57.60k
115.2k
10417
19.23k
57.97k
114.29k
10433
19.20k
57.60k
115.2k
416
138
68
39
34
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPxBRGH:
SPxBRGH:
SPxBRGH:
SPxBRGH:
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
SPxBRGL
(decimal)
SPxBRGL
(decimal)
SPxBRGL
(decimal)
SPxBRGL
(decimal)
Error
Error
Error
Error
300
1200
2400
9600
10417
19.2k
57.6k
115.2k
300.0
1200
0.00
-0.02
0.04
0.16
0.00
0.16
-0.79
2.12
6666
1666
832
207
191
103
34
300.0
1200
0.01
0.04
0.08
0.16
0.00
0.16
2.12
-3.55
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
3071
767
383
95
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
2401
2398
2400
9615
9615
9600
10417
19.23k
57.14k
117.6k
10417
19.23k
58.82k
111.1k
10473
19.20k
57.60k
115.2k
87
23
51
47
12
16
15
—
16
8
7
—
—
—
DS41414A-page 304
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
BRGH and SPxBRGL registers are clocked at 1/8th the
BRG base clock rate. The resulting byte measurement
is the average bit time when clocked at full speed.
24.3.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Section 24.3.3
“Auto-Wake-up
on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
Setting the ABDEN bit of the BAUDxCON register
starts
the
auto-baud
calibration
sequence
(Figure 24.3.2). While the ABD sequence takes place,
the EUSART state machine is held in Idle. On the first
rising edge of the receive line, after the Start bit, the
SPxBRGL begins counting up using the BRG counter
clock as shown in Table 24-6. The fifth rising edge will
occur on the RXx/DTx pin at the end of the eighth bit
period. At that time, an accumulated value totaling the
proper BRG period is left in the SPxBRGH:SPxBRGL
register pair, the ABDEN bit is automatically cleared,
and the RCxIF interrupt flag is set. A read operation on
the RCxREG needs to be performed to clear the RCxIF
interrupt. RCxREG content should be discarded. When
calibrating for modes that do not use the SPxBRGH
register the user can verify that the SPxBRGL register
did not overflow by checking for 00h in the SPxBRGH
register.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPxBRGH:SPxBRGL
register pair.
TABLE 24-6: BRG COUNTER CLOCK
RATES
BRG Base
Clock
BRG ABD
Clock
BRG16 BRGH
0
0
0
1
FOSC/64
FOSC/16
FOSC/512
FOSC/128
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 24-6. During ABD,
both the SPxBRGH and SPxBRGL registers are used
as a 16-bit counter, independent of the BRG16 bit set-
ting. While calibrating the baud rate period, the SPx-
1
1
0
1
FOSC/16
FOSC/4
FOSC/128
FOSC/32
Note:
During the ABD sequence, SPxBRGL and
SPxBRGH registers are both used as a
16-bit counter, independent of BRG16
setting.
FIGURE 24-6:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
0000h
001Ch
BRG Value
Edge #5
Stop bit
Edge #1
bit 1
Edge #2
bit 3
Edge #3
bit 5
Edge #4
bit 7
bit 6
RXx/DTx pin
BRG Clock
Start
bit 0
bit 2
bit 4
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCxIF bit
(Interrupt)
Read
RCxREG
XXh
XXh
1Ch
00h
SPxBRGL
SPxBRGH
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 305
PIC16F/LF1946/47
24.3.2
AUTO-BAUD OVERFLOW
24.3.3.1
Special Considerations
During the course of automatic baud detection, the
ABDOVF bit of the BAUDxCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPxBRGH:SPxBRGL
register pair. After the ABDOVF has been set, the coun-
ter continues to count until the fifth rising edge is
detected on the RXx/DTx pin. Upon detecting the fifth
RXx/DTx edge, the hardware will set the RCxIF inter-
rupt flag and clear the ABDEN bit of the BAUDxCON
register. The RCxIF flag can be subsequently cleared
by reading the RCxREG. The ABDOVF flag can be
cleared by software directly.
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
To terminate the auto-baud process before the RCxIF
flag is set, clear the ABDEN bit then clear the ABDOVF
bit. The ABDOVF bit will remain set if the ABDEN bit is
not cleared first.
Oscillator Startup Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
24.3.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RXx/DTx
line. This feature is available only in Asynchronous
mode.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCxIF bit. The WUE bit is cleared by
hardware by a rising edge on RXx/DTx. The interrupt
condition is then cleared by software by reading the
RCxREG register and discarding its contents.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDxCON register. Once set, the
normal receive sequence on RXx/DTx is disabled, and
the EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RXx/DTx line. (This coincides with the start of a Sync
Break or a wake-up signal character for the LIN
protocol.)
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The EUSART module generates an RCxIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 24-7), and asynchronously if
the device is in Sleep mode (Figure 24-8). The interrupt
condition is cleared by reading the RCxREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RXx line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
DS41414A-page 306
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 24-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4
OSC1
Auto Cleared
Bit set by user
WUE bit
RXx/DTx Line
RCxIF
Cleared due to User Read of RCxREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 24-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q4
Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3
Q1
Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
Auto Cleared
OSC1
Bit Set by User
WUE bit
RXx/DTx Line
RCxIF
Note 1
Cleared due to User Read of RCxREG
Sleep Command Executed
Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 307
PIC16F/LF1946/47
When the TXxREG becomes empty, as indicated by
the TXxIF, the next data byte can be written to TXxREG.
24.3.4
BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
24.3.5
RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
To send a Break character, set the SENDB and TXEN
bits of the TXxSTA register. The Break character trans-
mission is then initiated by a write to the TXxREG. The
value of data written to TXxREG will be ignored and all
‘0’s will be transmitted.
The first method to detect a Break character uses the
FERR bit of the RCxSTA register and the Received
data as indicated by RCxREG. The Baud Rate
Generator is assumed to have been initialized to the
expected baud rate.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
A Break character has been received when;
• RCxIF bit is set
• FERR bit is set
• RCxREG = 00h
The TRMT bit of the TXxSTA register indicates when the
transmit operation is active or Idle, just as it does during
normal transmission. See Figure 24-9 for the timing of
the Break character sequence.
The second method uses the Auto-Wake-up feature
described in Section 24.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RXx/DTx, cause an
RCxIF interrupt, and receive the next data byte
followed by another interrupt.
24.3.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDxCON register before placing the EUSART in
Sleep mode.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXxREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXxREG to load the Sync charac-
ter into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
FIGURE 24-9:
SEND BREAK CHARACTER SEQUENCE
Write to TXxREG
Dummy Write
BRG Output
(Shift Clock)
TXx/CKx (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TXxIF bit
(Transmit
interrupt Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB Sampled Here
Auto Cleared
SENDB
(send Break
control bit)
DS41414A-page 308
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
24.4.1.2
Clock Polarity
24.4 EUSART Synchronous Mode
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the CKTXP
bit of the BAUDxCON register. Setting the CKTXP bit
sets the clock Idle state as high. When the CKTXP bit
is set, the data changes on the falling edge of each
clock and is sampled on the rising edge of each clock.
Clearing the CKTXP bit sets the Idle state as low. When
the CKTXP bit is cleared, the data changes on the
rising edge of each clock and is sampled on the falling
edge of each clock.
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and
transmit shift registers. Since the data line is
bidirectional, synchronous operation is half-duplex
only. Half-duplex refers to the fact that master and
slave devices can receive and transmit data but not
both simultaneously. The EUSART can operate as
either a master or slave device.
24.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RXx/DTx
pin. The RXx/DTx and TXx/CKx pin output drivers are
automatically enabled when the EUSART is configured
for synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXxREG register. If the TSR still contains all or part of
a previous character the new character data is held in
the TXxREG until the last bit of the previous character
has been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXxREG is immediately trans-
ferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXxREG.
Start and Stop bits are not used in synchronous
transmissions.
24.4.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for Synchronous Master operation:
• SYNC = 1
• CSRC = 1
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXxSTA register configures the device as a
master. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured
to receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART. If the RXx/DTx or TXx/CKx pins
are shared with an analog peripheral the analog I/O
functions must be disabled by clearing the corresponding
ANSEL bits.
24.4.1.4
Data Polarity
The polarity of the transmit and receive data can be
controlled with the DTRXP bit of the BAUDxCON
register. The default state of this bit is ‘0’ which selects
high true transmit and receive data. Setting the DTRXP
bit to ‘1’ will invert the data resulting in low true transmit
and receive data.
The TRIS bits corresponding to the RXx/DTx and
TXx/CKx pins should be set.
24.4.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a master transmits the clock on the TXx/CKx line. The
TXx/CKx pin output driver is automatically enabled when
the EUSART is configured for synchronous transmit or
receive operation. Serial data bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One clock cycle is generated for each data bit.
Only as many clock cycles are generated as there are
data bits.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 309
PIC16F/LF1946/47
4. Disable Receive mode by clearing bits SREN
and CREN.
24.4.1.5
Synchronous Master Transmission
Set-up:
5. Enable Transmit mode by setting the TXEN bit.
6. If 9-bit transmission is desired, set the TX9 bit.
1. Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 24.3 “EUSART
Baud Rate Generator (BRG)”).
7. If interrupts are desired, set the TXxIE, GIE and
PEIE interrupt enable bits.
2. Set the RXx/DTx and TXx/CKx TRIS controls to
8. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
‘1’.
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Set the
TRIS bits corresponding to the RXx/DTx and
TXx/CKx I/O pins.
9. Start transmission by loading data to the
TXxREG register.
FIGURE 24-10:
SYNCHRONOUS TRANSMISSION
RXx/DTx
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
TXxREG Reg
Write Word 1
Write Word 2
TXxIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note:
Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 24-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RXx/DTx pin
bit 0
bit 2
bit 1
bit 6
bit 7
TXx/CKx pin
Write to
TXxREG reg
TXxIF bit
TRMT bit
TXEN bit
DS41414A-page 310
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 24-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON ABDOVF
BAUD2CON ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
INTF
ABDEN
ABDEN
IOCIF
300
300
89
—
INTCON
PIE1
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TMR0IF
CCP1IE
—
TX1IE
TX2IE
TX1IF
TX2IF
CREN
CREN
TMR2IE TMR1IE
90
PIE4
—
BCL2IE
TMR2IF
BCL2IF
OERR
SSP2IE
TMR1IF
SSP2IF
RX9D
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1STA
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TRISC
SPEN
SPEN
RX9
RX9
ADDEN
ADDEN
FERR
FERR
299
299
301*
301*
301*
301*
130
291*
298
291*
298
OERR
RX9D
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
TRISC7
CSRC
CSRC
TRISC6
TX9
TRISC5
EUSART1 Transmit Register
TXEN SYNC SENDB
EUSART2 Transmit Register
TXEN SYNC SENDB
TRISC4
TRISC3
TRISC2
BRGH
BRGH
TRISC1
TRMT
TRMT
TRISC0
TX9D
TX1REG
TX1STA
TX2REG
TX2STA
TX9
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master transmission.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 311
PIC16F/LF1946/47
If the overrun occurred when the CREN bit is set then
the error condition is cleared by either clearing the
CREN bit of the RCxSTA register or by clearing the
SPEN bit which resets the EUSART.
24.4.1.6
Synchronous Master Reception
Data is received at the RXx/DTx pin. The RXx/DTx pin
output driver must be disabled by setting the
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
24.4.1.9
Receiving 9-bit Characters
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCxSTA register) or the Continuous Receive Enable
bit (CREN of the RCxSTA register).
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCxSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCxREG.
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
24.4.1.10 Synchronous Master Reception
Set-up:
1. Initialize the SPxBRGH, SPxBRGL register pair
for the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
To initiate reception, set either SREN or CREN. Data is
sampled at the RXx/DTx pin on the trailing edge of the
TXx/CKx clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCxIF bit is set and the
character is automatically transferred to the two
character receive FIFO. The Least Significant eight bits
of the top character in the receive FIFO are available in
RCxREG. The RCxIF bit remains set as long as there
are un-read characters in the receive FIFO.
2. Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Disable
RXx/DTx and TXx/CKx output drivers by setting
the corresponding TRIS bits.
4. Ensure bits CREN and SREN are clear.
5. If using interrupts, set the GIE and PEIE bits of
the INTCON register and set RCxIE.
24.4.1.7
Slave Clock
6. If 9-bit reception is desired, set bit RX9.
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TXx/CKx line. The
TXx/CKx pin output driver must be disabled by setting
the associated TRIS bit when the device is configured
for synchronous slave transmit or receive operation.
Serial data bits change on the leading edge to ensure
they are valid at the trailing edge of each clock. One data
bit is transferred for each clock cycle. Only as many
clock cycles should be received as there are data bits.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt flag bit RCxIF will be set when recep-
tion of a character is complete. An interrupt will
be generated if the enable bit RCxIE was set.
9. Read the RCxSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCxREG register.
24.4.1.8
Receive Overrun Error
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCxREG is read to access
the FIFO. When this happens the OERR bit of the
RCxSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCxREG.
DS41414A-page 312
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 24-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RXx/DTx
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCxIF bit
(Interrupt)
Read
RCxREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 24-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON
BAUD2CON
INTCON
PIE1
ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
ABDEN
ABDEN
IOCIF
300
300
89
ABDOVF
—
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
TMR0IF
CCP1IE
—
INTF
TX1IE
TX2IE
TX1IF
TX2IF
TMR2IE
BCL2IE
TMR2IF
BCL2IF
TMR1IE
SSP2IE
TMR1IF
SSP2IF
90
PIE4
—
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1STA
TX2STA
EUSART1 Receive Register
CREN ADDEN
EUSART2 Receive Register
CREN ADDEN
294*
299
294*
299
301*
301*
301*
301*
298
298
SPEN
SPEN
RX9
RX9
SREN
FERR
OERR
OERR
RX9D
RX9D
SREN
FERR
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
CSRC
CSRC
TX9
TX9
TXEN
TXEN
SYNC
SYNC
SENDB
SENDB
BRGH
BRGH
TRMT
TRMT
TX9D
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 313
PIC16F/LF1946/47
If two words are written to the TXxREG and then the
SLEEPinstruction is executed, the following will occur:
24.4.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXxREG
register.
• CSRC = 0
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
3. The TXxIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXxREG register will transfer the
second character to the TSR and the TXxIF bit
will now be set.
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXxSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured to
receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART. If the RXx/DTx or TXx/CKx pins
are shared with an analog peripheral the analog I/O
functions must be disabled by clearing the corresponding
ANSEL bits.
5. If the PEIE and TXxIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
24.4.2.2
Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
RXx/DTx and TXx/CKx pin output drivers must be
disabled by setting the corresponding TRIS bits.
2. Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
3. Clear the CREN and SREN bits.
24.4.2.1
EUSART Synchronous Slave
Transmit
4. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXxIE bit.
The operation of the Synchronous Master and Slave
modes are identical (see Section 24.4.1.3
“Synchronous Master Transmission”), except in the
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
case of the Sleep mode.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant 8 bits to the TXxREG register.
DS41414A-page 314
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 24-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON ABDOVF
BAUD2CON ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
ABDEN
ABDEN
IOCIF
300
300
89
—
INTCON
PIE1
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TMR0IF
CCP1IE
—
INTF
TX1IE
TX2IE
TX1IF
TX2IF
CREN
CREN
TMR2IE
BCL2IE
TMR2IF
BCL2IF
OERR
OERR
TMR1IE
SSP2IE
TMR1IF
SSP2IF
RX9D
90
PIE4
—
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1STA
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TRISC
SPEN
SPEN
RX9
RX9
ADDEN
ADDEN
FERR
FERR
299
299
301*
301*
301*
301*
130
291*
298
291*
298
RX9D
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
TRISC7
CSRC
CSRC
TRISC6
TX9
TRISC5
EUSART1 Transmit Register
TXEN SYNC SENDB
EUSART2 Transmit Register
TXEN SYNC SENDB
TRISC4 TRISC3
TRISC2
TRISC1
TRMT
TRMT
TRISC0
TX9D
TX1REG
TX1STA
TX2REG
TX2STA
BRGH
TX9
BRGH
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave transmission.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 315
PIC16F/LF1946/47
24.4.2.3
EUSART Synchronous Slave
Reception
24.4.2.4
Synchronous Slave Reception
Set-up:
The operation of the Synchronous Master and Slave
modes is identical (Section 24.4.1.6 “Synchronous
Master Reception”), with the following exceptions:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
• Sleep
3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCxIE bit.
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCxREG register. If the RCxIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
6. The RCxIF bit will be set when reception is
complete. An interrupt will be generated if the
RCxIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCxSTA
register.
8. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCxREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 24-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON
BAUD2CON
INTCON
PIE1
ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
ABDEN
ABDEN
IOCIF
300
300
89
ABDOVF
—
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
TMR0IF
CCP1IE
—
INTF
TX1IE
TX2IE
TX1IF
TX2IF
TMR2IE
BCL2IE
TMR2IF
BCL2IF
TMR1IE
SSP2IE
TMR1IF
SSP2IF
90
PIE4
—
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1STA
TX2STA
EUSART1 Receive Register
CREN ADDEN
EUSART2 Receive Register
CREN ADDEN
294*
299
294*
299
301*
301*
301*
301*
298
298
SPEN
SPEN
RX9
RX9
SREN
FERR
OERR
OERR
RX9D
RX9D
SREN
FERR
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
CSRC
CSRC
TX9
TX9
TXEN
TXEN
SYNC
SYNC
SENDB
SENDB
BRGH
BRGH
TRMT
TRMT
TX9D
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.
Page provides register information.
*
DS41414A-page 316
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
25.0 CAPACITIVE SENSING
MODULE
The capacitive sensing module allows for an interaction
with an end user without a mechanical interface. In a
typical application, the capacitive sensing module is
attached to a pad on a Printed Circuit Board (PCB),
which is electrically isolated from the end user. When the
end user places their finger over the PCB pad, a
capacitive load is added, causing a frequency shift in the
capacitive sensing module. The capacitive sensing
module requires software and at least one timer
resource to determine the change in frequency. Key
features of this module include:
• Analog MUX for monitoring multiple inputs
• Capacitive sensing oscillator
• Multiple Power modes
• High power range with variable voltage references
• Multiple timer resources
• Software control
• Operation during Sleep
FIGURE 25-1:
CAPACITIVE SENSING BLOCK DIAGRAM
Timer0 Module
CPSCH<3:0>
CPSON(1)
Set
TMR0CS
TMR0IF
T0XCS
T0CKI
CPS0
CPS1
CPS2
CPS3
CPS4
CPS5
CPS6
CPS7
CPS8
CPS9
CPS10
CPS11
CPS12
CPS13
CPS14
CPS15
CPS16
FOSC/4
0
1
Overflow
TMR0
0
1
CPSRNG<1:0>
CPSON
Capacitive
Sensing
Oscillator
Timer1 Module
T1CS<1:0>
CPSOSC
FOSC
FOSC/4
CPSCLK
CPSOUT
Int.
Ref.
0
1
TMR1H:TMR1L
T1OSC/
T1CKI
Ref-
EN
DAC
T1GSEL<1:0>
T1G
0
Ref+
1
FVR
Timer1 Gate
Control Logic
SYNCC1OUT
SYNCC2OUT
CPSRM
Note 1: If CPSON = 0, disabling capacitive sensing, no channel is selected.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 317
PIC16F/LF1946/47
FIGURE 25-2:
CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM
Oscillator Module
VDD
(1)
(2)
(2)
+
-
S
R
Q
CPSCLK
CPSx
(1)
Analog Pin
-
+
Internal
References
0
1
0
Ref-
Ref+
FVR
1
DAC
CPSRM
Note 1: Module Enable and Power mode selections are not shown.
2: Comparators remain active in Noise Detection mode.
DS41414A-page 318
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
25.1 Analog MUX
25.3 Voltage References
The capacitive sensing module can monitor up to 16
inputs. The capacitive sensing inputs are defined as
CPS<15:0>. To determine if a frequency change has
occurred the user must:
The capacitive sensing oscillator uses voltage refer-
ences to provide two voltage thresholds for oscillation.
The upper voltage threshold is referred to as Ref+ and
the lower voltage threshold is referred to as Ref-.
• Select the appropriate CPS pin by setting the
CPSCH<4:0> bits of the CPSCON1 register.
The user can elect to use fixed voltage references,
which are internal to the capacitive sensing oscillator,
or variable voltage references, which are supplied by
the Fixed Voltage Reference (FVR) module and the
Digital-to-Analog Converter (DAC) module.
• Set the corresponding ANSEL bit.
• Set the corresponding TRIS bit.
• Run the software algorithm.
When the fixed voltage references are used, the VSS
voltage determines the lower threshold level (Ref-) and
the VDD voltage determines the upper threshold level
(Ref+).
Selection of the CPSx pin while the module is enabled
will cause the capacitive sensing oscillator to be on the
CPSx pin. Failure to set the corresponding ANSEL and
TRIS bits can cause the capacitive sensing oscillator to
stop, leading to false frequency readings.
When the variable voltage references are used, the
DAC voltage determines the lower threshold level
(Ref-) and the FVR voltage determines the upper
threshold level (Ref+). An advantage of using these ref-
erence sources is that oscillation frequency remains
constant with changes in VDD.
25.2 Capacitive Sensing Oscillator
The capacitive sensing oscillator consists of a constant
current source and a constant current sink, to produce
a
triangle waveform. The CPSOUT bit of the
Different oscillation frequencies can be obtained
through the use of these variable voltage references.
The more the upper voltage reference level is lowered
and the more the lower voltage reference level is
raised, the higher the capacitive sensing oscillator
frequency becomes.
CPSCON0 register shows the status of the capacitive
sensing oscillator, whether it is a sinking or sourcing
current. The oscillator is designed to drive a capacitive
load (single PCB pad) and at the same time, be a clock
source to either Timer0 or Timer1. The oscillator has
three different current settings as defined by
CPSRNG<1:0> of the CPSCON0 register. The different
current settings for the oscillator serve two purposes:
Selection between the voltage references is controlled
by the CPSRM bit of the CPSCON0 register. Setting
this bit selects the variable voltage references and
clearing this bit selects the fixed voltage references.
• Maximize the number of counts in a timer for a
fixed time base.
Please see Section 14.0 “Fixed Voltage Reference
(FVR)” and Section 16.0 “Digital-to-Analog Converter
(DAC) Module” for more information on configuring the
variable voltage levels.
• Maximize the count differential in the timer during
a change in frequency.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 319
PIC16F/LF1946/47
The remaining mode is a Noise Detection mode that
resides within the high range. The Noise Detection
mode is unique in that it disables the sinking and sourc-
ing of current on the analog pin but leaves the rest of
the oscillator circuitry active. This reduces the oscilla-
tion frequency on the analog pin to zero and also
greatly reduces the current consumed by the oscillator
module.
25.4 Power Modes
The capacitive sensing oscillator can operate in one of
seven different power modes. The power modes are
separated into two ranges; the low range and the high
range.
When the oscillator’s low range is selected, the fixed
internal voltage references of the capacitive sensing
oscillator are being used. When the oscillator’s high
range is selected, the variable voltage references
supplied by the FVR and DAC modules are being used.
Selection between the voltage references is controlled
by the CPSRM bit of the CPSCON0 register. See
Section 25.3 “Voltage References” for more
information.
When noise is introduced onto the pin, the oscillator is
driven at the frequency determined by the noise. This
produces a detectable signal at the comparator output,
indicating the presence of activity on the pin.
Figure 25-2 shows a more detailed drawing of the
current sources and comparators associated with the
oscillator.
Within each range there are three distinct Power modes;
low, medium and high. Current consumption is dependent
upon the range and mode selected. Selecting Power
modes within each range is accomplished by configuring
the CPSRNG <1:0> bits in the CPSCON0 register. See
Table 25-1 for proper Power mode selection.
TABLE 25-1: POWER MODE SELECTION
CPSRM
Range
CPSRNG<1:0>
Mode
Nominal Current(1)
00
01
10
11
00
01
10
11
Off
Low
0.0 A
0.25 A
1.5 A
7.5 A
0.0 A
9 A
0
Low
Medium
High
Noise Detection
Low
1
High
Medium
High
30 A
100 A
Note 1: See Section 29.0 “Electrical Specifications” for more information.
DS41414A-page 320
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
25.5 Timer Resources
25.7 Software Control
To measure the change in frequency of the capacitive
sensing oscillator, a fixed time base is required. For the
period of the fixed time base, the capacitive sensing
oscillator is used to clock either Timer0 or Timer1. The
frequency of the capacitive sensing oscillator is equal
to the number of counts in the timer divided by the
period of the fixed time base.
The software portion of the capacitive sensing module
is required to determine the change in frequency of the
capacitive sensing oscillator. This is accomplished by
the following:
• Setting a fixed time base to acquire counts on
Timer0 or Timer1.
• Establishing the nominal frequency for the
capacitive sensing oscillator.
25.6 Fixed Time Base
• Establishing the reduced frequency for the capac-
itive sensing oscillator due to an additional capac-
itive load.
To measure the frequency of the capacitive sensing
oscillator, a fixed time base is required. Any timer
resource or software loop can be used to establish the
fixed time base. It is up to the end user to determine the
method in which the fixed time base is generated.
• Set the frequency threshold.
25.7.1
NOMINAL FREQUENCY
(NO CAPACITIVE LOAD)
Note:
The fixed time base can not be generated
by the timer resource that the capacitive
sensing oscillator is clocking.
To determine the nominal frequency of the capacitive
sensing oscillator:
• Remove any extra capacitive load on the selected
CPSx pin.
25.6.1
TIMER0
To select Timer0 as the timer resource for the capacitive
sensing module:
• At the start of the fixed time base, clear the timer
resource.
• At the end of the fixed time base save the value in
the timer resource.
• Set the T0XCS bit of the CPSCON0 register.
• Clear the TMR0CS bit of the OPTION register.
The value of the timer resource is the number of
oscillations of the capacitive sensing oscillator for the
given time base. The frequency of the capacitive
sensing oscillator is equal to the number of counts on
in the timer divided by the period of the fixed time base.
When Timer0 is chosen as the timer resource, the
capacitive sensing oscillator will be the clock source for
Timer0. Refer to Section 19.0 “Timer0 Module” for
additional information.
25.6.2
TIMER1
25.7.2
REDUCED FREQUENCY
To select Timer1 as the timer resource for the
capacitive sensing module, set the TMR1CS<1:0> of
the T1CON register to ‘11’. When Timer1 is chosen as
the timer resource, the capacitive sensing oscillator will
be the clock source for Timer1. Because the Timer1
module has a gate control, developing a time base for
the frequency measurement can be simplified by using
the Timer0 overflow flag.
(ADDITIONAL CAPACITIVE LOAD)
The extra capacitive load will cause the frequency of the
capacitive sensing oscillator to decrease. To determine
the reduced frequency of the capacitive sensing
oscillator:
• Add a typical capacitive load on the selected
CPSx pin.
It is recommend that the Timer0 overflow flag, in
conjunction with the Toggle mode of the Timer1 Gate, be
used to develop the fixed time base required by the soft-
ware portion of the capacitive sensing module. Refer to
Section 20.12 “Timer1 Gate Control Register” for
additional information.
• Use the same fixed time base as the nominal
frequency measurement.
• At the start of the fixed time base, clear the timer
resource.
• At the end of the fixed time base save the value in
the timer resource.
The value of the timer resource is the number of oscil-
lations of the capacitive sensing oscillator with an addi-
tional capacitive load. The frequency of the capacitive
sensing oscillator is equal to the number of counts on
in the timer divided by the period of the fixed time base.
This frequency should be less than the value obtained
during the nominal frequency measurement.
TABLE 25-2: TIMER1 ENABLE FUNCTION
TMR1ON
TMR1GE
Timer1 Operation
0
0
1
0
1
0
Off
Off
On
1
1
Count Enabled by input
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PIC16F/LF1946/47
25.7.3
FREQUENCY THRESHOLD
The frequency threshold should be placed midway
between the value of nominal frequency and the
reduced frequency of the capacitive sensing oscillator.
Refer to Application Note AN1103, “Software Handling
for Capacitive Sensing” (DS01103) for more detailed
information on the software required for capacitive
sensing module.
Note:
For more information on general capacitive
sensing refer to Application Notes:
• AN1101, “Introduction to Capacitive
Sensing” (DS01101)
• AN1102, “Layout and Physical Design
Guidelines for Capacitive Sensing”
(DS01102)
25.8 Operation during Sleep
The capacitive sensing oscillator will continue to run as
long as the module is enabled, independent of the part
being in Sleep. In order for the software to determine if
a frequency change has occurred, the part must be
awake. However, the part does not have to be awake
when the timer resource is acquiring counts.
Note:
Timer0 does not operate when in Sleep,
and therefore cannot be used for
capacitive sense measurements in Sleep.
DS41414A-page 322
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PIC16F/LF1946/47
REGISTER 25-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0
R/W-0/0
CPSON
R/W-0/0
CPSRM
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
T0XCS
CPSRNG<1:0>
CPSOUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
CPSON: Capacitive Sensing Module Enable bit
1= Capacitive sensing module is enabled
0= Capacitive sensing module is disabled
CPSRM: Capacitive Sensing Reference Mode bit
1= Capacitive Sensing module is in high range. DAC and FVR provide oscillator voltage references.
0= Capacitive Sensing module is in the low range. Internal oscillator voltage references are used.
bit 5-4
bit 3-2
Unimplemented: Read as ‘0’
CPSRNG<1:0>: Capacitive Sensing Current Range
If CPSRM = 0 (low range):
00= Oscillator is off
01= Oscillator is in Low Range. Charge/Discharge Current is nominally 0.1 µA
10= Oscillator is in Medium Range. Charge/Discharge Current is nominally 1.2 µA
11= Oscillator is in High Range. Charge/Discharge Current is nominally 18 µA
If CPSRM = 1 (high range):
00= Oscillator is on. Noise Detection mode. No Charge/Discharge current is supplied.
01= Oscillator is in Low Range. Charge/Discharge Current is nominally 9 µA
10= Oscillator is in Medium Range. Charge/Discharge Current is nominally 30 µA
11= Oscillator is in High Range. Charge/Discharge Current is nominally 100 µA
bit 1
bit 0
CPSOUT: Capacitive Sensing Oscillator Status bit
1= Oscillator is sourcing current (Current flowing out of the pin)
0= Oscillator is sinking current (Current flowing into the pin)
T0XCS: Timer0 External Clock Source Select bit
If TMR0CS = 1:
The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0:
1= Timer0 clock source is the capacitive sensing oscillator
0= Timer0 clock source is the T0CKI pin
If TMR0CS = 0:
Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 323
PIC16F/LF1946/47
REGISTER 25-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CPSCH<4:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
CPSCH<4:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
These bits are ignored. No channel is selected.
If CPSON = 1:
00000= channel 0, (CPS0)
00001= channel 1, (CPS1)
00010= channel 2, (CPS2)
00011= channel 3, (CPS3)
00100= channel 4, (CPS4)
00101= channel 5, (CPS5)
00110= channel 6, (CPS6)
00111= channel 7, (CPS7)
01000= channel 8, (CPS8)
01001= channel 9, (CPS9)
01010= channel 10, (CPS10)
01011= channel 11, (CPS11)
01100= channel 12, (CPS12)
01101= channel 13, (CPS13)
01110= channel 14, (CPS14)
01111= channel 15, (CPS15)
10000= channel 16, (CPS16)
10001= Reserved. Do not use.
.
.
.
11111= Reserved. Do not use.
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TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
CPSON
—
—
CPSRM
—
ANSA5
—
ANSA4
—
ANSA3
ANSA2
ANSA1
ANSA0
T0XCS
125
323
324
189
199
124
127
133
CPSRNG<1:0>
CPSOUT
CPSCON0
CPSCON1
—
CPSCH<4:0>
PS2
OPTION_REG WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS1
—
PS0
T1CON
TRISA
TRISB
TRISD
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN T1SYNC
TMR1ON
TRISA0
TRISB0
TRISA7
TRISB7
TRISA6
TRISB6
TRISA5
TRISB5
TRISA4
TRISB4
TRISA3
TRISB3
TRISA2
TRISB2
TRISA1
TRISB1
TRISD<7:0>
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the capacitive sensing module.
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PIC16F/LF1946/47
NOTES:
DS41414A-page 326
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26.1 LCD Registers
26.0 LIQUID CRYSTAL DISPLAY
(LCD) DRIVER MODULE
The module contains the following registers:
The Liquid Crystal Display (LCD) driver module
generates the timing control to drive a static or
multiplexed LCD panel. In the PIC16F/LF1946/47
device, the module drives the panels of up to four
commons and up to 46 segments. The LCD module
also provides control of the LCD pixel data.
• LCD Control register (LCDCON)
• LCD Phase register (LCDPS)
• LCD Reference Ladder register (LCDRL)
• LCD Contrast Control register (LCDCST)
• LCD Reference Voltage Control register
(LCDREF)
The LCD driver module supports:
• Up to 6 LCD Segment Enable registers (LCDSEn)
• Up to 24 LCD data registers (LCDDATAn)
• Direct driving of LCD panel
• Three LCD clock sources with selectable prescaler
• Up to four common pins:
- Static (1 common)
- 1/2 multiplex (2 commons)
- 1/3 multiplex (3 commons)
- 1/4 multiplex (4 commons)
• Segment pins up to:
- 64 (PIC16F/LF1946/47)
• Static, 1/2 or 1/3 LCD Bias
FIGURE 26-1:
LCD DRIVER MODULE BLOCK DIAGRAM
(2)
SEG<23:0>
LCDDATAx
Registers
Data Bus
(1)
MUX
To I/O Pads
Timing Control
LCDCON
LCDPS
COM<3:0>
(1)
To I/O Pads
LCDSEn
FOSC/256
Clock Source
Select and
Prescaler
T1OSC
LFINTOSC
Note 1: These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of
the LCD module.
2: SEG<23:0> on PIC16F1947, SEG<15:0> on PIC16F1946/ PIC16LF1946.
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PIC16F/LF1946/47
TABLE 26-1: LCD SEGMENT AND DATA
REGISTERS
# of LCD Registers
Device
Segment
Enable
Data
PIC16F/LF1946/47
6
24
The LCDCON register (Register 26-1) controls the
operation of the LCD driver module. The LCDPS regis-
ter (Register 26-2) configures the LCD clock source
prescaler and the type of waveform; Type-A or Type-B.
The LCDSEn registers (Register 26-5) configure the
functions of the port pins.
The following LCDSEn registers are available:
• LCDSE0 SE<7:0>
• LCDSE1 SE<15:8>
• LCDSE2 SE<23:16>(1)
• LCDSE3 SE<31:24>
• LCDSE4 SE<39:32>
• LCDSE5 SE<45:40>
Once the module is initialized for the LCD panel, the
individual bits of the LCDDATAn registers are
cleared/set to represent a clear/dark pixel, respectively:
• LCDDATA0 SEG<7:0>COM0
• LCDDATA1 SEG<15:8>COM0
• LCDDATA2 SEG<23:16>COM0
• LCDDATA3 SEG<7:0>COM1
• LCDDATA4 SEG<15:8>COM1
• LCDDATA5 SEG<23:16>COM1
• LCDDATA6 SEG<7:0>COM2
• LCDDATA7 SEG<15:8>COM2
• LCDDATA8 SEG<23:16>COM2
• LCDDATA9 SEG<7:0>COM3
• LCDDATA10 SEG<15:8>COM3
• LCDDATA11 SEG<23:16>COM3
• LCDDATA12 SEG<31:24>COM0
• LCDDATA13 SEG<39:32>COM0
• LCDDATA14 SEG<45:40>COM0
• LCDDATA15 SEG<31:24>COM1
• LCDDATA16 SEG<39:32>COM1
• LCDDATA17 SEG<45:40>COM1
• LCDDATA18 SEG<31:24>COM2
• LCDDATA19 SEG<39:32>COM2
• LCDDATA20 SEG<45:40>COM2
• LCDDATA21 SEG<31:24>COM3
• LCDDATA22 SEG<39:32>COM3
• LCDDATA23 SEG<45:40>COM3
As an example, LCDDATAn is detailed in
Register 26-6.
Once the module is configured, the LCDEN bit of the
LCDCON register is used to enable or disable the LCD
module. The LCD panel can also operate during Sleep
by clearing the SLPEN bit of the LCDCON register.
DS41414A-page 328
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REGISTER 26-1: LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER
R/W-0/0
LCDEN
R/W-0/0
SLPEN
R/C-0/0
WERR
U-0
—
R/W-0/0
R/W-0/0
R/W-1/1
R/W-1/1
CS<1:0>
LMUX<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
C = Only clearable bit
bit 7
bit 6
bit 5
LCDEN: LCD Driver Enable bit
1= LCD driver module is enabled
0= LCD driver module is disabled
SLPEN: LCD Driver Enable in Sleep Mode bit
1= LCD driver module is disabled in Sleep mode
0= LCD driver module is enabled in Sleep mode
WERR: LCD Write Failed Error bit
1 = LCDDATAn register written while the WA bit of the LCDPS register = 0 (must be cleared in
software)
0= No LCD write error
bit 4
Unimplemented: Read as ‘0’
bit 3-2
CS<1:0>: Clock Source Select bits
00= FOSC/256
01= T1OSC (Timer1)
1x= LFINTOSC (31 kHz)
bit 1-0
LMUX<1:0>: Commons Select bits
Maximum Number of Pixels
LMUX<1:0>
Multiplex
Bias
PIC16F1946/47/
PIC16LF1946/47
00
01
10
11
Static (COM0)
1/2 (COM<1:0>)
1/3 (COM<2:0>)
1/4 (COM<3:0>)
46
92
Static
1/2 or 1/3
1/2 or 1/3
1/3
138
184
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 329
PIC16F/LF1946/47
REGISTER 26-2: LCDPS: LCD PHASE REGISTER
R/W-0/0
WFT
R/W-0/0
BIASMD
R-0/0
LCDA
R-0/0
WA
R/W-0/0
R/W-0/0
R/W-1/1
R/W-1/1
bit 0
LP<3:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
C = Only clearable bit
bit 7
bit 6
WFT: Waveform Type bit
1= Type-B phase changes on each frame boundary
0= Type-A phase changes within each common type
BIASMD: Bias Mode Select bit
When LMUX<1:0> = 00:
0= Static Bias mode (do not set this bit to ‘1’)
When LMUX<1:0> = 01:
1= 1/2 Bias mode
0= 1/3 Bias mode
When LMUX<1:0> = 10:
1= 1/2 Bias mode
0= 1/3 Bias mode
When LMUX<1:0> = 11:
0= 1/3 Bias mode (do not set this bit to ‘1’)
LCDA: LCD Active Status bit
bit 5
1= LCD driver module is active
0= LCD driver module is inactive
bit 4
WA: LCD Write Allow Status bit
1= Writing to the LCDDATAn registers is allowed
0= Writing to the LCDDATAn registers is not allowed
bit 3-0
LP<3:0>: LCD Prescaler Selection bits
1111= 1:16
1110= 1:15
1101= 1:14
1100= 1:13
1011= 1:12
1010= 1:11
1001= 1:10
1000= 1:9
0111= 1:8
0110= 1:7
0101= 1:6
0100= 1:5
0011= 1:4
0010= 1:3
0001= 1:2
0000= 1:1
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REGISTER 26-3: LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER
R/W-0/0
LCDIRE
R/W-0/0
LCDIRS
R/W-0/0
LCDIRI
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
VLCD3PE
VLCD2PE
VLCD1PE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
C = Only clearable bit
bit 7
bit 6
LCDIRE: LCD Internal Reference Enable bit
1= Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit
0= Internal LCD Reference is disabled
LCDIRS: LCD Internal Reference Source bit
If LCDIRE = 1:
0= Internal LCD Contrast Control is powered by VDD
1= Internal LCD Contrast Control is powered by a 3.072V output of the FVR.
If LCDIRE = 0:
Internal LCD Contrast Control is unconnected. LCD bandgap buffer is disabled.
bit 5
LCDIRI: LCD Internal Reference Ladder Idle Enable bit
Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’
1= When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled.
0= The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode.
bit 4
bit 3
Unimplemented: Read as ‘0’
VLCD3PE: VLCD3 Pin Enable bit
1= The VLCD3 pin is connected to the internal bias voltage LCDBIAS3(1)
0= The VLCD3 pin is not connected
bit 2
bit 1
bit 0
VLCD2PE: VLCD2 Pin Enable bit
1= The VLCD2 pin is connected to the internal bias voltage LCDBIAS2(1)
0= The VLCD2 pin is not connected
VLCD1PE: VLCD1 Pin Enable bit
1= The VLCD1 pin is connected to the internal bias voltage LCDBIAS1(1)
0= The VLCD1 pin is not connected
Unimplemented: Read as ‘0’
Note 1: Normal pin controls of TRISx and ANSELx are unaffected.
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Preliminary
DS41414A-page 331
PIC16F/LF1946/47
REGISTER 26-4: LCDCST: LCD CONTRAST CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
LCDCST<2:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
C = Only clearable bit
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
LCDCST<2:0>: LCD Contrast Control bits
Selects the resistance of the LCD contrast control resistor ladder
Bit Value = Resistor ladder
000= Minimum Resistance (Maximum contrast). Resistor ladder is shorted.
001= Resistor ladder is at 1/7th of maximum resistance
010= Resistor ladder is at 2/7th of maximum resistance
011= Resistor ladder is at 3/7th of maximum resistance
100= Resistor ladder is at 4/7th of maximum resistance
101= Resistor ladder is at 5/7th of maximum resistance
110= Resistor ladder is at 6/7th of maximum resistance
111= Resistor ladder is at maximum resistance (Minimum contrast).
DS41414A-page 332
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PIC16F/LF1946/47
REGISTER 26-5: LCDSEn: LCD SEGMENT ENABLE REGISTERS
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
SEn: Segment Enable bits
1= Segment function of the pin is enabled
0= I/O function of the pin is enabled
REGISTER 26-6: LCDDATAn: LCD DATA REGISTERS
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy
R/W-x/u
R/W-x/u
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
SEGx-COMy: Pixel On bits
1= Pixel on (dark)
0= Pixel off (clear)
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PIC16F/LF1946/47
Using bits CS<1:0> of the LCDCON register can select
any of these clock sources.
26.2 LCD Clock Source Selection
The LCD module has 3 possible clock sources:
26.2.1
LCD PRESCALER
• FOSC/256
• T1OSC
A 4-bit counter is available as a prescaler for the LCD
clock. The prescaler is not directly readable or writable;
its value is set by the LP<3:0> bits of the LCDPS register,
which determine the prescaler assignment and prescale
ratio.
• LFINTOSC
The first clock source is the system clock divided by
256 (FOSC/256). This divider ratio is chosen to provide
about 1 kHz output when the system clock is 8 MHz.
The divider is not programmable. Instead, the LCD
prescaler bits LP<3:0> of the LCDPS register are used
to set the LCD frame clock rate.
The prescale values are selectable from 1:1 through
1:16.
The second clock source is the T1OSC. This also gives
about 1 kHz when a 32.768 kHz crystal is used with the
Timer1 oscillator. To use the Timer1 oscillator as a
clock source, the T1OSCEN bit of the T1CON register
should be set.
The third clock source is the 31 kHz LFINTOSC, which
provides approximately 1 kHz output.
The second and third clock sources may be used to
continue running the LCD while the processor is in
Sleep.
FIGURE 26-2:
LCD CLOCK GENERATION
FOSC
÷256
To Ladder
Power Control
Static
÷4
÷2
T1OSC 32 kHz
Crystal Osc.
Segment
÷1, 2, 3, 4
Ring Counter
4-bit Prog
Prescaler
÷ 32
Counter
1/2
Clock
1/3,
1/4
LFINTOSC
Nominal = 31 kHz
LP<3:0>
CS<1:0>
LMUX<1:0>
DS41414A-page 334
Preliminary
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PIC16F/LF1946/47
TABLE 26-2: LCD BIAS VOLTAGES
26.3 LCD Bias Voltage Generation
Static Bias
1/2 Bias
1/3 Bias
The LCD module can be configured for one of three
bias types:
LCD Bias 0
LCD Bias 1
LCD Bias 2
LCD Bias 3
VSS
—
VSS
VSS
1/2 VDD
1/2 VDD
VLCD3
1/3 VDD
2/3 VDD
VLCD3
• Static Bias (2 voltage levels: VSS and VLCD)
—
• 1/2 Bias (3 voltage levels: VSS, 1/2 VLCD and
VLCD)
VLCD3
• 1/3 Bias (4 voltage levels: VSS, 1/3 VLCD,
2/3 VLCD and VLCD)
So that the user is not forced to place external compo-
nents and use up to three pins for bias voltage generation,
internal contrast control and an internal reference ladder
are provided internally to the PIC16F/LF1946/47. Both of
these features may be used in conjunction with the exter-
nal VLCD<3:1> pins, to provide maximum flexibility. Refer
to Figure 26-3.
FIGURE 26-3:
LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM
LCDIRE
LCDIRS
LCDA
VDD
1.024V from
FVR
3.072V
x 3
LCDRLP1
LCDRLP0
LCDIRE
LCDIRS
LCDA
LCDCST<2:0>
VLCD3PE
LCDA
VLCD3
lcdbias3
VLCD2PE
VLCD2
lcdbias2
BIASMD
VLCD1PE
VLCD1
lcdbias1
lcdbias0
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PIC16F/LF1946/47
26.4.2
POWER MODES
26.4 LCD Bias Internal Reference
Ladder
The internal reference ladder may be operated in one of
three power modes. This allows the user to trade off LCD
contrast for power in the specific application. The larger
the LCD glass, the more capacitance is present on a
physical LCD segment, requiring more current to
maintain the same contrast level.
The internal reference ladder can be used to divide the
LCD bias voltage two or three equally spaced voltages
that will be supplied to the LCD segment pins. To create
this, the reference ladder consists of three matched
resistors. Refer to Figure 26-3.
Three different power modes are available, LP, MP and
HP. The internal reference ladder can also be turned off
for applications that wish to provide an external ladder
or to minimize power consumption. Disabling the
internal reference ladder results in all of the ladders
being disconnected, allowing external voltages to be
supplied.
26.4.1
BIAS MODE INTERACTION
When in 1/2 Bias mode (BIASMD = 1), then the middle
resistor of the ladder is shorted out so that only two
voltages are generated. The current consumption of the
ladder is higher in this mode, with the one resistor
removed.
Whenever the LCD module is inactive (LCDA = 0), the
internal reference ladder will be turned off.
TABLE 26-3:
LCD INTERNAL LADDER
POWER MODES (1/3 BIAS)
Power
Mode
Nominal Resistance of
Entire Ladder
Nominal
IDD
Low
3 Mohm
300 kohm
30 kohm
1 µA
10 µA
100 µA
Medium
High
DS41414A-page 336
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
The LCDRL register allows switching between two
power modes, designated ‘A’ and ‘B’. ‘A’ Power mode
is active for a programmable time, beginning at the
time when the LCD segments transition. ‘B’ Power
mode is the remaining time before the segments or
commons change again. The LRLAT<2:0> bits select
how long, if any, that the ‘A’ Power mode is active.
Refer to Figure 26-4.
26.4.3
AUTOMATIC POWER MODE
SWITCHING
As an LCD segment is electrically only a capacitor, cur-
rent is drawn only during the interval where the voltage
is switching. To minimize total device current, the LCD
internal reference ladder can be operated in a different
power mode for the transition portion of the duration.
This is controlled by the LCDRL Register
(Register 26-7).
To implement this, the 5-bit prescaler used to divide
the 32 kHz clock down to the LCD controller’s 1 kHz
base rate is used to select the power mode.
FIGURE 26-4:
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –
TYPE A
Single Segment Time
32 kHz Clock
Ladder Power
Control
‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07
‘H0E ‘H0F ‘H00 ‘H01
Segment Clock
LRLAT<2:0>
‘H3
Segment Data
LRLAT<2:0>
Power Mode
COM0
Power Mode A
Power Mode B
Mode A
V1
V0
V1
V0
SEG0
V1
V0
COM0-SEG0
-V1
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 337
FIGURE 26-5:
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE)
Single Segment Time
Single Segment Time
32 kHz Clock
Ladder Power
Control
‘H00
‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07
‘H0E ‘H0F
‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07
‘H01
‘H0E ‘H0F
Segment Clock
Segment Data
Power Mode
Power Mode A
Power Mode B
Power Mode A
Power Mode B
LRLAT<2:0> = 011
LRLAT<2:0> = 011
V
V
V
2
1
0
COM0-SEG0
-V
1
2
-V
FIGURE 26-6:
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE)
Single Segment Time
Single Segment Time
Single Segment Time
Single Segment Time
32 kHz Clock
Ladder Power
Control
‘H00
‘H02 ‘H03
‘H0E ‘H0F ‘H10
‘H12 ‘H13
‘H1E ‘H1F ‘H00
‘H02 ‘H03
‘H0E ‘H0F ‘H10
‘H12 ‘H13
‘H11
‘H1E ‘H1F
‘H01
‘H11
‘H01
Segment Clock
Segment Data
Power Mode
Power Mode A
LRLAT<2:0> 011
Power Mode A
LRLAT<2:0> 011
Power
Mode B
Power
Mode B
Power
Mode B
Power
Mode B
Power Mode A
LRLAT<2:0> 011
Power Mode A
LRLAT<2:0> 011
=
=
=
=
V2
V1
V0
COM0-SEG0
-V1
-V2
PIC16F/LF1946/47
REGISTER 26-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
LRLAP<1:0>
LRLBP<1:0>
LRLAT<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits
During Time interval A (Refer to Figure 26-4):
00= Internal LCD Reference Ladder is powered down and unconnected
01= Internal LCD Reference Ladder is powered in low-power mode
10= Internal LCD Reference Ladder is powered in medium-power mode
11= Internal LCD Reference Ladder is powered in high-power mode
LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits
During Time interval B (Refer to Figure 26-4):
00= Internal LCD Reference Ladder is powered down and unconnected
01= Internal LCD Reference Ladder is powered in low-power mode
10= Internal LCD Reference Ladder is powered in medium-power mode
11= Internal LCD Reference Ladder is powered in high-power mode
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LRLAT<2:0>: LCD Reference Ladder A Time interval control bits
Sets the number of 32 kHz clocks that the A Time interval power mode is active
For type A waveforms (WFT = 0):
000= Internal LCD Reference Ladder is always in ‘B’ power mode
001= Internal LCD Reference Ladder is in ‘A’ power mode for 1 clock and ‘B’ power mode for 15 clocks
010= Internal LCD Reference Ladder is in ‘A’ power mode for 2 clocks and ‘B’ power mode for 14 clocks
011= Internal LCD Reference Ladder is in ‘A’ power mode for 3 clocks and ‘B’ power mode for 13 clocks
100= Internal LCD Reference Ladder is in ‘A’ power mode for 4 clocks and ‘B’ power mode for 12 clocks
101= Internal LCD Reference Ladder is in ‘A’ power mode for 5 clocks and ‘B’ power mode for 11 clocks
110= Internal LCD Reference Ladder is in ‘A’ power mode for 6 clocks and ‘B’ power mode for 10 clocks
111= Internal LCD Reference Ladder is in ‘A’ power mode for 7 clocks and ‘B’ power mode for 9 clocks
For type B waveforms (WFT = 1):
000= Internal LCD Reference Ladder is always in ‘B’ power mode.
001= Internal LCD Reference Ladder is in ‘A’ power mode for 1 clock and ‘B’ power mode for 31 clocks
010= Internal LCD Reference Ladder is in ‘A’ power mode for 2 clocks and ‘B’ power mode for 30 clocks
011= Internal LCD Reference Ladder is in ‘A’ power mode for 3 clocks and ‘B’ power mode for 29 clocks
100= Internal LCD Reference Ladder is in ‘A’ power mode for 4 clocks and ‘B’ power mode for 28 clocks
101= Internal LCD Reference Ladder is in ‘A’ power mode for 5 clocks and ‘B’ power mode for 27 clocks
110= Internal LCD Reference Ladder is in ‘A’ power mode for 6 clocks and ‘B’ power mode for 26 clocks
111= Internal LCD Reference Ladder is in ‘A’ power mode for 7 clocks and ‘B’ power mode for 25 clocks
DS41414A-page 340
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
The contrast control circuit is used to decrease the
output voltage of the signal source by a total of
approximately 10%, when LCDCST = 111.
26.4.4
CONTRAST CONTROL
The LCD contrast control circuit consists of a
seven-tap resistor ladder, controlled by the LCDCST
bits. Refer to Figure 26-7.
Whenever the LCD module is inactive (LCDA = 0), the
contrast control ladder will be turned off (open).
FIGURE 26-7:
INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM
VDDIO
7 Stages
R
R
R
R
3.072V
Analog
MUX
From FVR
Buffer
7
0
To top of
Reference Ladder
LCDCST<2:0>
3
Internal Reference
Contrast control
26.4.5
INTERNAL REFERENCE
26.4.6
VLCD<3:1> PINS
Under firmware control, an internal reference for the
LCD bias voltages can be enabled. When enabled, the
source of this voltage can be either VDDIO or a voltage
3 times the main fixed voltage reference (3.072V).
When no internal reference is selected, the LCD con-
trast control circuit is disabled and LCD bias must be
provided externally.
The VLCD<3:1> pins provide the ability for an external
LCD bias network to be used instead of the internal lad-
der. Use of the VLCD<3:1> pins does not prevent use
of the internal ladder. Each VLCD pin has an indepen-
dent control in the LCDREF register (Register 26-3),
allowing access to any or all of the LCD Bias signals.
This architecture allows for maximum flexibility in
different applications
Whenever the LCD module is inactive (LCDA = 0), the
internal reference will be turned off.
For example, the VLCD<3:1> pins may be used to add
capacitors to the internal reference ladder, increasing
the drive capacity.
When the internal reference is enabled and the Fixed
Voltage Reference is selected, the LCDIRI bit can be
used to minimize power consumption by tieing into the
LCD reference ladder automatic power mode switching.
When LCDIRI = 1 and the LCD reference ladder is in
Power mode ‘B’, the LCD internal FVR buffer is
disables.
For applications where the internal contrast control is
insufficient, the firmware can choose to only enable the
VLCD3 pin, allowing an external contrast control circuit
to use the internal reference divider.
.
Note:
The LCD module automatically turns on the
fixed voltage reference when needed.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 341
PIC16F/LF1946/47
26.5 LCD Multiplex Types
26.7 Pixel Control
The LCD driver module can be configured into one of
four multiplex types:
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
• Static (only COM0 is used)
Register 26-6 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
• 1/2 multiplex (COM<1:0> are used)
• 1/3 multiplex (COM<2:0> are used)
• 1/4 multiplex (COM<3:0> are used)
Any LCD pixel location not being used for display can
be used as general purpose RAM.
The LMUX<1:0> bit setting of the LCDCON register
decides which of the LCD common pins are used (see
Table 26-4 for details).
26.8 LCD Frame Frequency
The rate at which the COM and SEG outputs change is
called the LCD frame frequency.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
then the TRIS setting of that pin is overridden.
TABLE 26-5: FRAME FREQUENCY
FORMULAS
TABLE 26-4: COMMON PIN USAGE
LMUX
Multiplex
Frame Frequency =
Multiplex
COM3
COM2
COM1
<1:0>
Static
1/2
Clock source/(4 x 1 x (LPD Prescaler) x 32))
Clock source/(2 x 2 x (LPD Prescaler) x 32))
Clock source/(1 x 3 x (LPD Prescaler) x 32))
Clock source/(1 x 4 x (LPD Prescaler) x 32))
Static
1/2
00
01
10
11
Unused
Unused
Unused
Active
Unused
Unused
Active
Unused
Active
Active
Active
1/3
1/3
1/4
1/4
Active
Note:
Clock source is FOSC/256, T1OSC or
LFINTOSC.
26.6 Segment Enables
TABLE 26-6: APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
FOSC @ 8 MHz, TIMER1 @
The LCDSEn registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
as one of the pin’s alternate functions. To configure the
pin as a segment pin, the corresponding bits in the
LCDSEn registers must be set to ‘1’.
32.768 kHz OR LFINTOSC
LP<3:0>
Static
1/2
1/3
1/4
2
3
4
5
6
7
122
81
61
49
41
35
122
81
61
49
41
35
162
108
81
122
81
61
49
41
35
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEn
registers overrides any bit settings in the corresponding
TRIS register.
65
Note:
On a Power-on Reset, these pins are
configured as normal I/O, not LCD pins.
54
47
DS41414A-page 342
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 26-7: LCD SEGMENT MAPPING WORKSHEET
LCD
Function
COM0
COM1
COM2
LCDDATAx
COM3
LCDDATAx
LCDDATAx
LCD
LCDDATAx
LCD
LCD
LCD
Address
Segment
Address
Segment
Address
Segment
Address
Segment
SEG0
LCDDATA0, 0
LCDDATA0, 1
LCDDATA0, 2
LCDDATA0, 3
LCDDATA0, 4
LCDDATA0, 5
LCDDATA0, 6
LCDDATA0, 7
LCDDATA1, 0
LCDDATA1, 1
LCDDATA1, 2
LCDDATA1, 3
LCDDATA1, 4
LCDDATA1, 5
LCDDATA1, 6
LCDDATA1, 7
LCDDATA2, 0
LCDDATA2, 1
LCDDATA2, 2
LCDDATA2, 3
LCDDATA2, 4
LCDDATA2, 5
LCDDATA2, 6
LCDDATA2, 7
LCDDATA12, 0
LCDDATA12, 1
LCDDATA12, 2
LCDDATA12, 3
LCDDATA12, 4
LCDDATA12, 5
LCDDATA12, 6
LCDDATA12, 7
LCDDATA13, 0
LCDDATA13, 1
LCDDATA13, 2
LCDDATA13, 3
LCDDATA13, 4
LCDDATA13, 5
LCDDATA13, 6
LCDDATA13, 7
LCDDATA14, 0
LCDDATA14, 1
LCDDATA14, 2
LCDDATA14, 3
LCDDATA14, 4
LCDDATA14, 5
LCDDATA3, 0
LCDDATA3, 1
LCDDATA3, 2
LCDDATA3, 3
LCDDATA3, 4
LCDDATA3, 5
LCDDATA3, 6
LCDDATA3, 7
LCDDATA4, 0
LCDDATA4, 1
LCDDATA4, 2
LCDDATA4, 3
LCDDATA4, 4
LCDDATA4, 5
LCDDATA4, 6
LCDDATA4, 7
LCDDATA5, 0
LCDDATA5, 1
LCDDATA5, 2
LCDDATA5, 3
LCDDATA5, 4
LCDDATA5, 5
LCDDATA5, 6
LCDDATA5, 7
LCDDATA15, 0
LCDDATA15, 1
LCDDATA15, 2
LCDDATA15, 3
LCDDATA15, 4
LCDDATA15, 5
LCDDATA15, 6
LCDDATA15, 7
LCDDATA16, 0
LCDDATA16, 1
LCDDATA16, 2
LCDDATA16, 3
LCDDATA16, 4
LCDDATA16, 5
LCDDATA16, 6
LCDDATA16, 7
LCDDATA17, 0
LCDDATA17, 1
LCDDATA17, 2
LCDDATA17, 3
LCDDATA17, 4
LCDDATA17, 5
LCDDATA6, 0
LCDDATA6, 1
LCDDATA6, 2
LCDDATA6, 3
LCDDATA6, 4
LCDDATA6, 5
LCDDATA6, 6
LCDDATA6, 7
LCDDATA7, 0
LCDDATA7, 1
LCDDATA7, 2
LCDDATA7, 3
LCDDATA7, 4
LCDDATA7, 5
LCDDATA7, 6
LCDDATA7, 7
LCDDATA8, 0
LCDDATA8, 1
LCDDATA8, 2
LCDDATA8, 3
LCDDATA8, 4
LCDDATA8, 5
LCDDATA8, 6
LCDDATA8, 7
LCDDATA18, 0
LCDDATA18, 1
LCDDATA18, 2
LCDDATA18, 3
LCDDATA18, 4
LCDDATA18, 5
LCDDATA18, 6
LCDDATA18, 7
LCDDATA19, 0
LCDDATA19, 1
LCDDATA19, 2
LCDDATA19, 3
LCDDATA19, 4
LCDDATA19, 5
LCDDATA19, 6
LCDDATA19, 7
LCDDATA20, 0
LCDDATA20, 1
LCDDATA20, 2
LCDDATA20, 3
LCDDATA20, 4
LCDDATA20, 5
LCDDATA9, 0
LCDDATA9, 1
LCDDATA9, 2
LCDDATA9, 3
LCDDATA9, 4
LCDDATA9, 5
LCDDATA9, 6
LCDDATA9, 7
LCDDATA10, 0
LCDDATA10, 1
LCDDATA10, 2
LCDDATA10, 3
LCDDATA10, 4
LCDDATA10, 5
LCDDATA10, 6
LCDDATA10, 7
LCDDATA11, 0
LCDDATA11, 1
LCDDATA11, 2
LCDDATA11, 3
LCDDATA11, 4
LCDDATA11, 5
LCDDATA11, 6
LCDDATA11, 7
LCDDATA21, 0
LCDDATA21, 1
LCDDATA21, 2
LCDDATA21, 3
LCDDATA21, 4
LCDDATA21, 5
LCDDATA21, 6
LCDDATA21, 7
LCDDATA22, 0
LCDDATA22, 1
LCDDATA22, 2
LCDDATA22, 3
LCDDATA22, 4
LCDDATA22, 5
LCDDATA22, 6
LCDDATA22, 7
LCDDATA23, 0
LCDDATA23, 1
LCDDATA23, 2
LCDDATA23, 3
LCDDATA23, 4
LCDDATA23, 5
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 343
PIC16F/LF1946/47
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In Type-A waveform, the phase
changes within each common type, whereas in Type-B
waveform, the phase changes on each frame
boundary. Thus, Type-A waveform maintains 0 VDC
over a single frame, whereas Type-B waveform takes
two frames.
26.9 LCD Waveform Generation
LCD waveforms are generated so that the net AC
voltage across the dark pixel should be maximized and
the net AC voltage across the clear pixel should be
minimized. The net DC voltage across any pixel should
be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
Note 1: If Sleep has to be executed with LCD
Sleep disabled (LCDCON<SLPEN> is
‘1’), then care must be taken to execute
Sleep only when VDC on all the pixels is
‘0’.
The pixel signal (COM-SEG) will have no DC
component and it can take only one of the two RMS
values. The higher RMS value will create a dark pixel
and a lower RMS value will create a clear pixel.
2: When the LCD clock source is FOSC/256,
if Sleep is executed, irrespective of the
LCDCON<SLPEN> setting, the LCD
immediately goes into Sleep. Thus, take
care to see that VDC on all pixels is ‘0’
when Sleep is executed.
As the number of commons increases, the delta
between the two RMS values decreases. The delta
represents the maximum contrast that the display can
have.
Figure 26-8 through Figure 26-18 provide waveforms
for static, half-multiplex, 1/3-multiplex and 1/4-multiplex
drives for Type-A and Type-B waveforms.
FIGURE 26-8:
TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
V1
COM0 pin
SEG0 pin
SEG1 pin
V0
V1
COM0
V0
V1
V0
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
COM0-SEG1
segment voltage
(inactive)
V0
1 Frame
DS41414A-page 344
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 26-9:
TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
V1
V0
COM0 pin
COM1 pin
COM1
V2
V1
V0
COM0
V2
V1
V0
SEG0 pin
SEG1 pin
V2
V1
V0
V2
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
-V2
V2
V1
V0
COM0-SEG1
segment voltage
(inactive)
-V1
-V2
1 Frame
1 Segment Time
Note:
1 Frame = 2 single segment times.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 345
PIC16F/LF1946/47
FIGURE 26-10:
TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
V1
V0
COM1
COM0 pin
COM0
V2
V1
V0
COM1 pin
SEG0 pin
V2
V1
V0
V2
V1
V0
SEG1 pin
V2
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
-V2
V2
V1
V0
COM0-SEG1
segment voltage
(inactive)
-V1
-V2
2 Frames
1 Segment Time
Note:
1 Frame = 2 single segment times.
DS41414A-page 346
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 26-11:
TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM1
COM0 pin
COM0
COM1 pin
SEG0 pin
SEG1 pin
V3
V2
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
segment voltage
(inactive)
-V1
-V2
-V3
1 Frame
1 Segment Time
Note:
1 Frame = 2 single segment times.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 347
PIC16F/LF1946/47
FIGURE 26-12:
TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM1
COM0 pin
COM0
COM1 pin
SEG0 pin
SEG1 pin
V3
V2
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
segment voltage
(inactive)
-V1
-V2
-V3
2 Frames
1 Segment Time
Note:
1 Frame = 2 single segment times.
DS41414A-page 348
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 26-13:
TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
V1
V0
COM0 pin
V2
V1
V0
COM2
COM1 pin
COM2 pin
COM1
COM0
V2
V1
V0
V2
V1
V0
SEG0 and
SEG2 pins
V2
V1
V0
SEG1 pin
V2
V1
V0
COM0-SEG0
segment voltage
(inactive)
-V1
-V2
V2
V1
V0
COM0-SEG1
segment voltage
(active)
-V1
-V2
1 Frame
1 Segment Time
Note:
1 Frame = 2 single segment times.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 349
PIC16F/LF1946/47
FIGURE 26-14:
TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
V1
V0
COM0 pin
COM1 pin
COM2 pin
SEG0 pin
SEG1 pin
COM2
V2
V1
V0
COM1
COM0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
COM0-SEG0
segment voltage
(inactive)
-V1
-V2
V2
V1
V0
COM0-SEG1
segment voltage
(active)
-V1
-V2
2 Frames
1 Segment Time
Note:
1 Frame = 2 single segment times.
DS41414A-page 350
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 26-15:
TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V1
-V2
-V3
V3
V2
V1
V0
-V1
-V2
-V3
COM0 pin
COM1 pin
COM2 pin
COM2
COM1
COM0
SEG0 and
SEG2 pins
SEG1 pin
COM0-SEG0
segment voltage
(inactive)
COM0-SEG1
segment voltage
(active)
1 Frame
1 Segment Time
Note:
1 Frame = 2 single segment times.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 351
PIC16F/LF1946/47
FIGURE 26-16:
TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V1
-V2
-V3
V3
V2
V1
V0
-V1
-V2
-V3
COM0 pin
COM1 pin
COM2 pin
SEG0 pin
SEG1 pin
COM2
COM1
COM0
COM0-SEG0
segment voltage
(inactive)
COM0-SEG1
segment voltage
(active)
2 Frames
1 Segment Time
Note:
1 Frame = 2 single segment times.
DS41414A-page 352
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 26-17:
COM3
TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V
V
V
V
3
2
1
0
COM0 pin
COM1 pin
COM2
V
V
V
V
3
2
1
0
COM1
COM0
V
V
V
V
3
2
1
0
COM2 pin
COM3 pin
SEG0 pin
SEG1 pin
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
-V
-V
-V
3
2
1
0
COM0-SEG0
segment voltage
(active)
1
2
3
V
V
V
V
-V
-V
-V
3
2
1
0
COM0-SEG1
segment voltage
(inactive)
1
2
3
1 Frame
1 Segment Time
Note:
1 Frame = 2 single segment times.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 353
PIC16F/LF1946/47
FIGURE 26-18:
TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
COM3
V
V
V
V
3
2
1
0
COM0 pin
COM1 pin
COM2
V
V
V
V
3
2
1
0
COM1
COM0
V
V
V
V
3
2
1
0
COM2 pin
COM3 pin
SEG0 pin
SEG1 pin
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
-V
-V
-V
3
2
1
0
COM0-SEG0
segment voltage
(active)
1
2
3
V
V
V
V
-V
-V
-V
3
2
1
0
COM0-SEG1
segment voltage
(inactive)
1
2
3
2 Frames
1 Segment Time
Note:
1 Frame = 2 single segment times.
DS41414A-page 354
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
26.10 LCD Interrupts
The LCD module provides an interrupt in two cases. An
interrupt when the LCD controller goes from active to
inactive controller. An interrupt also provides unframe
boundaries for Type B waveform. The LCD timing gen-
eration provides an interrupt that defines the LCD
frame timing.
26.10.1 LCD INTERRUPT ON MODULE
SHUTDOWN
An LCD interrupt is generated when the module
completes shutting down (LCDA goes from ‘1’ to ‘0’).
26.10.2 LCD FRAME INTERRUPTS
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes access-
ing all pixel data required for a frame. This will occur at
a fixed interval before the frame boundary (TFINT), as
shown in Figure 26-19. The LCD controller will begin to
access data for the next frame within the interval from
the interrupt to when the controller begins to access
data after the interrupt (TFWR). New data must be writ-
ten within TFWR, as this is when the LCD controller will
begin to access the data for the next frame.
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’ (static
drive), there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
were allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
component would be introduced into the panel.
Therefore, when using Type-B waveforms, the user
must synchronize the LCD pixel updates to occur within
a subframe after the frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR bit of the LCDCON register is set and the
write does not occur.
Note: The LCD frame interrupt is not generated
when the Type-A waveform is selected and
when the Type-B with no multiplex (static)
is selected.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 355
PIC16F/LF1946/47
FIGURE 26-19:
WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE
(EXAMPLE – TYPE-B, NON-STATIC)
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
V
V
V
V
3
2
1
0
COM0
COM1
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
COM2
COM3
V
V
V
V
3
2
1
0
2 Frames
TFINT
TFWR
Frame
Frame
Frame
Boundary
Boundary
Boundary
TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2
TFINT = (TFWR/2 – (2 TCY + 40 ns)) minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns)) maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)
DS41414A-page 356
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
Table 26-8 shows the status of the LCD module during
a Sleep while using each of the three available clock
sources.
26.11 Operation During Sleep
The LCD module can operate during Sleep. The
selection is controlled by bit SLPEN of the LCDCON
register. Setting the SLPEN bit allows the LCD module
to go to Sleep. Clearing the SLPEN bit allows the
module to continue to operate during Sleep.
Note:
When the LCDEN bit is cleared, the LCD
module will be disabled at the completion
of frame. At this time, the port pins will
revert to digital functionality. To minimize
power consumption due to floating digital
inputs, the LCD pins should be driven low
using the PORT and TRIS registers.
If a SLEEPinstruction is executed and SLPEN = 1, the
LCD module will cease all functions and go into a very
low-current Consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines.
Figure 26-20 shows this operation.
If a SLEEPinstruction is executed and SLPEN = 0, the
module will continue to display the current contents of
the LCDDATA registers. To allow the module to
continue operation while in Sleep, the clock source
must be either the LFINTOSC or T1OSC external
oscillator. While in Sleep, the LCD data cannot be
changed. The LCD module current consumption will
not decrease in this mode; however, the overall
consumption of the device will be lower due to shut
down of the core and other peripheral functions.
The LCD module can be configured to operate during
Sleep. The selection is controlled by bit SLPEN of the
LCDCON register. Clearing SLPEN and correctly con-
figuring the LCD module clock will allow the LCD mod-
ule to operate during Sleep. Setting SLPEN and
correctly executing the LCD module shutdown will
disable the LCD module during Sleep and save power.
If a SLEEPinstruction is executed and SLPEN = 1, the
LCD module will immediately cease all functions, drive
the outputs to Vss and go into a very low-current mode.
The SLEEP instruction should only be executed after
the LCD module has been disabled and the current
cycle completed, thus ensuring that there are no DC
voltages on the glass. To disable the LCD module,
clear the LCDEN bit. The LCD module will complete the
disabling process after the current frame, clear the
LCDA bit and optionally cause an interrupt.
Table 26-8 shows the status of the LCD module during
Sleep while using each of the three available clock
sources:
TABLE 26-8: LCD MODULE STATUS
DURING SLEEP
Operational
During Sleep
Clock Source
T1OSC
SLPEN
0
1
0
1
0
1
Yes
No
Yes
No
No
No
The steps required to properly enter Sleep with the
LCD disabled are:
• Clear LCDEN
LFINTOSC
FOSC/4
• Wait for LCDA = 0either by polling or by interrupt
• Execute SLEEP
If SLPEN = 0 and SLEEP is executed while the LCD
module clock source is FOSC/4, then the LCD module
will halt with the pin driving the last LCD voltage pat-
tern. Prolonged exposure to a fixed LCD voltage pat-
tern will cause damage to the LCD glass. To prevent
LCD glass damage, either perform the proper LCD
module shutdown prior to Sleep, or change the LCD
module clock to allow the LCD module to continue
operation during Sleep.
Note:
The LFINTOSC or external T1OSC
oscillator must be used to operate the LCD
module during Sleep.
If LCD interrupts are being generated (Type-B wave-
form with a multiplex mode not static) and LCDIE = 1,
the device will awaken from Sleep on the next frame
boundary.
If a SLEEPinstruction is executed and SLPEN = 0and
the LCD module clock is either T1OSC or LFINTOSC,
the module will continue to display the current contents
of the LCDDATA registers. While in Sleep, the LCD
data cannot be changed. If the LCDIE bit is set, the
device will wake from Sleep on the next LCD frame
boundary. The LCD module current consumption will
not decrease in this mode; however, the overall device
power consumption will be lower due to the shutdown
of the CPU and other peripherals.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 357
PIC16F/LF1946/47
FIGURE 26-20:
SLEEP ENTRY/EXIT WHEN SLPEN = 1
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM2
SEG0
2 Frames
Wake-up
SLEEPInstruction Execution
DS41414A-page 358
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
26.12 Configuring the LCD Module
26.14 LCD Current Consumption
The following is the sequence of steps to configure the
LCD module.
When using the LCD module the current consumption
consists of the following three factors:
1. Select the frame clock prescale using bits
LP<3:0> of the LCDPS register.
• Oscillator Selection
• LCD Bias Source
2. Configure the appropriate pins to function as
segment drivers using the LCDSEn registers.
• Capacitance of the LCD segments
The current consumption of just the LCD module can
be considered negligible compared to these other
factors.
3. Configure the LCD module for the following
using the LCDCON register:
- Multiplex and Bias mode, bits LMUX<1:0>
- Timing source, bits CS<1:0>
- Sleep mode, bit SLPEN
26.14.1 OSCILLATOR SELECTION
The current consumed by the clock source selected
must be considered when using the LCD module. See
Section 29.0 “Electrical Specifications” for oscillator
current consumption information.
4. Write initial values to pixel data registers,
LCDDATA0 through LCDDATA23.
5. Clear LCD Interrupt Flag, LCDIF bit of the PIR2
register and if desired, enable the interrupt by
setting bit LCDIE of the PIE2 register.
26.14.2 LCD BIAS SOURCE
The LCD bias source, internal or external, can contrib-
ute significantly to the current consumption. Use the
highest possible resistor values while maintaining
contrast to minimize current.
6. Configure bias voltages by setting the LCDRL,
LCDREF and the associated ANSELx
registers as needed.
7. Enable the LCD module by setting bit LCDEN of
the LCDCON register.
26.14.3 CAPACITANCE OF THE LCD
SEGMENTS
26.13 Disabling the LCD Module
The LCD segments which can be modeled as capaci-
tors which must be both charged and discharged every
frame. The size of the LCD segment and its technology
determines the segment’s capacitance.
To disable the LCD module, write all ‘0’s to the
LCDCON register.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 359
PIC16F/LF1946/47
TABLE 26-9: SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION
Register
on Page
Name
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
LCDEN
—
PEIE
SLPEN
—
TMR0IE
WERR
—
INTE
—
IOCIE
TMR0IF
INTF
IOCIF
89
LCDCON
LCDCST
CS<1:0>
LMUX<1:0>
329
332
333
—
—
LCDCST<2:0>
LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
LCDDATA12
LCDDATA13
LCDDATA14
LCDDATA15
LCDDATA16
LCDDATA17
LCDDATA18
LCDDATA19
LCDDATA20
LCDDATA21
Legend:
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
333
333
333
333
333
333
333
333
333
333
333
333
333
333
333
333
333
333
333
333
333
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
SEG31
COM0
SEG30
COM0
SEG29
COM0
SEG28
COM0
SEG27
COM0
SEG26
COM0
SEG25
COM0
SEG24
COM0
SEG39
COM0
SEG38
COM0
SEG37
COM0
SEG36
COM0
SEG35
COM0
SEG34
COM0
SEG33
COM0
SEG32
COM0
—
—
SEG45
COM0
SEG44
COM0
SEG43
COM0
SEG42
COM0
SEG41
COM0
SEG40
COM0
SEG31
COM1
SEG30
COM1
SEG29
COM1
SEG28
COM1
SEG27
COM1
SEG26
COM1
SEG25
COM1
SEG24
COM1
SEG39
COM1
SEG38
COM1
SEG37
COM1
SEG36
COM1
SEG35
COM1
SEG34
COM1
SEG33
COM1
SEG32
COM1
—
—
SEG45
COM1
SEG44
COM1
SEG43
COM1
SEG42
COM1
SEG41
COM1
SEG40
COM1
SEG31
COM2
SEG30
COM2
SEG29
COM2
SEG28
COM2
SEG27
COM2
SEG26
COM2
SEG25
COM2
SEG24
COM2
SEG39
COM2
SEG38
COM2
SEG37
COM2
SEG36
COM2
SEG35
COM2
SEG34
COM2
SEG33
COM2
SEG32
COM2
—
—
SEG45
COM2
SEG44
COM2
SEG43
COM2
SEG42
COM2
SEG41
COM2
SEG40
COM2
SEG31
COM3
SEG30
COM3
SEG29
COM3
SEG28
COM3
SEG27
COM3
SEG26
COM3
SEG25
COM3
SEG24
COM3
— = unimplemented location, read as ‘0’. Shaded cells are not used by the LCD module.
DS41414A-page 360
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 26-9: SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION (CONTINUED)
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDDATA22
SEG39
COM3
SEG38
COM3
SEG37
COM3
SEG36
COM3
SEG35
COM3
SEG34
COM3
SEG33
COM3
SEG32
COM3
333
LCDDATA23
—
—
SEG45
COM3
SEG44
COM3
SEG43
COM3
SEG42
COM3
SEG41
COM3
SEG40
COM3
333
LCDPS
LCDREF
LCDRL
LCDSE0
LCDSE1
LCDSE2
LCDSE3
LCDSE4
LCDSE5
PIE2
WFT
BIASMD
LCDIRS
LCDA
WA
—
LP<3:0>
VLCD3PE VLCD2PE VLCD1PE
330
331
340
333
333
333
333
333
333
91
LCDIRE
LCDIRI
—
LRLAP<1:0>
LRLBP<1:0>
—
LRLAT<2:0>
SE<7:0>
SE<15:8>
SE<23:16>
SE<31:24>
SE<39:32>
—
—
SE<45:40>
OSFIE
OSFIF
C2IE
C2IF
C1IE
C1IF
EEIE
EEIF
BCLIE
BCLIF
LCDIE
LCDIF
—
—
—
CCP2IE
CCP2IF
TMR1ON
PIR2
95
T1CON
Legend:
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN T1SYNC
199
— = unimplemented location, read as ‘0’. Shaded cells are not used by the LCD module.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 361
PIC16F/LF1946/47
NOTES:
DS41414A-page 362
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
27.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
In Program/Verify mode the Program Memory, User
IDs and the Configuration Words are programmed
through serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data
and the ICSPCLK pin is the clock input. For more
information
on
ICSP™
refer
to
the
“PIC16F193X/LF193X/PIC16F194X/LF194X Memory
Programming Specification” (DS41397).
27.1 High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
Some programmers produce VPP greater than VIHH
(9.0V), an external circuit is required to limit the VPP
voltage. See Figure 27-1 for example circuit.
FIGURE 27-1:
VPP LIMITER EXAMPLE CIRCUIT
RJ11-6PIN
6
5
4
3
2
1
VPP
2
VDD
3
VSS
4
ICSP_DATA
ICSP_CLOCK
NC
5
6
1
RJ11-6PIN
R1
To MPLAB® ICD 2
To Target Board
270 Ohm
LM431BCMX
1
2
A
A
A
A
K
U1
3
6
7
4
5
NC
NC
VREF
8
R2
R3
10k 1%
24k 1%
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 363
PIC16F/LF1946/47
27.3 Common Programming Interfaces
Note:
The ICD 2 produces a VPP voltage greater
than the maximum VPP specification of the
PIC16F/LF1946/47.
Connection to a target device is typically done
through an ICSP™ header. A commonly found
connector on development tools is the RJ-11 in the
6P6C (6 pin,
Figure 27-2.
6
connector) configuration. See
27.2 Low-Voltage Programming Entry
Mode
FIGURE 27-2:
ICD RJ-11 STYLE
CONNECTOR INTERFACE
The Low-Voltage Programming Entry mode allows the
PIC16F/LF1946/47 devices to be programmed using
VDD only, without high voltage. When the LVP bit of
Configuration Word 2 is set to ‘1’, the low-voltage ICSP
programming entry is enabled. To disable the
Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’.
ICSPDAT
NC
2 4 6
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
VDD
ICSPCLK
1 3
5
Target
PC Board
Bottom Side
1. MCLR is brought to VIL.
VPP/MCLR
VSS
2.
A
32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.3 “MCLR” for more
information.
5 = ICSPCLK
6 = No Connect
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 27-3.
FIGURE 27-3:
PICkit™ STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
1
2
3
4
5
6
5 = ICSPCLK
6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
DS41414A-page 364
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 27-4 for more
information.
FIGURE 27-4:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
VSS
MCLR/VPP
VSS
Data
ICSPDAT
ICSPCLK
Clock
*
*
*
To Normal Connections
Isolation devices (as required).
*
2010 Microchip Technology Inc.
Preliminary
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PIC16F/LF1946/47
NOTES:
DS41414A-page 366
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
28.1 Read-Modify-Write Operations
28.0 INSTRUCTION SET SUMMARY
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
Each PIC16 instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most var-
ied instruction word format.
TABLE 28-1: OPCODE FIELD
DESCRIPTIONS
Table 28-3 lists the instructions recognized by the
MPASMTM assembler.
Field
Description
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
k
x
Don’t care location (= 0or 1).
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
TABLE 28-2: ABBREVIATION
DESCRIPTIONS
Field
Description
PC
TO
C
Program Counter
Time-out bit
Carry bit
DC
Z
Digit carry bit
Zero bit
PD
Power-down bit
2010 Microchip Technology Inc.
Preliminary
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PIC16F/LF1946/47
FIGURE 28-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
7 6
0
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLPinstruction only
13
7
6
0
0
OPCODE
k (literal)
k = 7-bit immediate value
MOVLBinstruction only
13
5 4
OPCODE
k (literal)
k = 5-bit immediate value
BRAinstruction only
13
9
8
0
OPCODE
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
7
6
5
0
0
OPCODE
n
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSRIncrement instructions
13
3
2
n
1
OPCODE
m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
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TABLE 28-3: PIC16F/LF1946/47 ENHANCED INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC f, d
ANDWF
ASRF
LSLF
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C, DC, Z
11 1101 dfff ffff C, DC, Z
00 0101 dfff ffff Z
11 0111 dfff ffff C, Z
11 0101 dfff ffff C, Z
11 0110 dfff ffff C, Z
2
2
2
2
2
2
2
f, d
f, d
f, d
f, d
f
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB f, d
SWAPF
XORWF
00 0001 lfff ffff
00 0001 0000 00xx
00 1001 dfff ffff
00 0011 dfff ffff
00 1010 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 1fff ffff
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
Z
Z
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
2
2
2
2
2
2
2
2
2
2
2
2
C
C
00 0010 dfff ffff C, DC, Z
11 1011 dfff ffff C, DC, Z
00 1110 dfff ffff
f, d
f, d
00 0110 dfff ffff
Z
BYTE ORIENTED SKIP OPERATIONS
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00
1011 dfff ffff
1111 dfff ffff
1, 2
1, 2
DECFSZ
INCFSZ
BIT-ORIENTED FILE REGISTER OPERATIONS
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
BCF
BSF
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1, 2
1, 2
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110 kkkk kkkk C, DC, Z
1001 kkkk kkkk
1000 kkkk kkkk
0000 001k kkkk
0001 1kkk kkkk
0000 kkkk kkkk
Z
Z
Subtract W from literal
Exclusive OR literal with W
1100 kkkk kkkk C, DC, Z
1010 kkkk kkkk
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
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TABLE 28-3: PIC16F/LF1946/47 ENHANCED INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k kkkk kkkk
0000 0000 1011
0kkk kkkk kkkk
0000 0000 1010
1kkk kkkk kkkk
0000 0000 1001
0100 kkkk kkkk
0000 0000 1000
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
00
00
00
00
00
00
0000 0110 0100 TO, PD
0000 0000 0000
0000 0110 0010
0000 0000 0001
0000 0110 0011 TO, PD
0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal k to FSR, n = FSR0 or FSR1
Move Indirect to W, n = FSR0 or FSR1, with
pre/post inc/dec modifier.
Move INDFn to W, Indexed Indirect.
Move W to Indirect, n = FSR0 or FSR1, with
pre/post inc/dec modifier.
1
1
1
1
1
11 0001 0nkk kkkk
00 0000 0001 0nmm
11 1111 0nkk kkkk
00 0000 0001 1nmm
11 1111 1nkk kkkk
MOVIW
n
Z
Z
2
2
2
2
MOVWI
k[n]
n
k[n]
Move W to INDFn, Indexed Indirect.
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
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28.2 Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
-32 k 31
n [ 0, 1]
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
FSR(n) + k FSR(n)
Z
Status Affected:
Description:
None
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
ANDWF
AND W with f
ADDLW
Add literal and W
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] ADDLW
0 k 255
k
Operands:
0 f 127
d 0,1
Operands:
Operation:
Status Affected:
Description:
(W) + k (W)
C, DC, Z
Operation:
(W) .AND. (f) (destination)
Status Affected:
Description:
Z
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
ADDWF
Add W and f
Syntax:
[ label ] ASRF f {,d}
Syntax:
[ label ] ADDWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d 0,1
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Operation:
(W) + (f) (destination)
Status Affected:
Description:
C, DC, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
ADDWFC
ADD W and CARRY bit to f
C
register f
Syntax:
[ label ] ADDWFC
f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(W) + (f) + (C) dest
Status Affected:
Description:
C, DC, Z
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
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BTFSC
Bit Test f, Skip if Clear
BCF
Bit Clear f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] BCF f,b
Operands:
0 f 127
0 b 7
Operands:
0 f 127
0 b 7
Operation:
skip if (f<b>) = 0
Operation:
0 (f<b>)
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
Bit ‘b’ in register ‘f’ is cleared.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOPis
executed instead, making this a
2-cycle instruction.
BTFSS
Bit Test f, Skip if Set
BRA
Relative Branch
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Operands:
0 f 127
0 b < 7
Operands:
-256 label - PC + 1 255
-256 k 255
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOPis
executed instead, making this a
2-cycle instruction.
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruc-
tion. This branch has a limited range.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
None
Operands:
Operation:
Status Affected:
Description:
(PC) + (W) PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0 f 127
0 b 7
Operation:
1 (f<b>)
Status Affected:
Description:
None
Bit ‘b’ in register ‘f’ is set.
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CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL
0 k 2047
k
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
Description:
None
Status Affected:
Description:
TO, PD
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a two-cycle instruc-
tion.
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
COMF
Complement f
CALLW
Subroutine Call With W
Syntax:
[ label ] COMF f,d
Syntax:
[ label ] CALLW
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
(PC) +1 TOS,
(W) PC<7:0>,
Operation:
(f) (destination)
(PCLATH<6:0>) PC<14:8>
Status Affected:
Description:
Z
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Status Affected:
Description:
None
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLWis a two-cycle
instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] CLRF
0 f 127
f
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h (f)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
The contents of register ‘f’ are cleared
and the Z bit is set.
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h (W)
1 Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z) is
set.
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DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
Description:
None
Status Affected:
Description:
None
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOPis executed instead, making it a
2-cycle instruction.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOPis
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO
0 k 2047
k
Syntax:
[ label ] IORLW
0 k 255
(W) .OR. k (W)
Z
k
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected:
Description:
None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
GOTOis an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ] INCF f,d
Syntax:
[ label ] IORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
(W) .OR. (f) (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
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LSLF
Logical Left Shift
MOVF
Move f
Syntax:
[ label ] LSLF f {,d}
Syntax:
[ label ] MOVF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
Operation:
(f) (dest)
(f<6:0>) dest<7:1>
0 dest<0>
Status Affected:
Description:
Z
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0,
destination is W register. If d = 1, the
destination is file register f itself. d = 1
is useful to test a file register since
status flag Z is affected.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Words:
1
1
C
register f
0
Cycles:
Example:
MOVF
FSR, 0
After Instruction
LSRF
Logical Right Shift
W
Z
=
=
value in FSR register
1
Syntax:
[ label ] LSLF f {,d}
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0
C
register f
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MOVIW
Move INDFn to W
MOVLP
Move literal to PCLATH
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
Syntax:
[ label ] MOVLP
0 k 127
k PCLATH
None
k
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
n [0,1]
-32 k 31
If not present, k = 0.
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
INDFn W
Effective address is determined by
MOVLW
Move literal to W
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
Syntax:
[ label ] MOVLW
0 k 255
k (W)
k
Operands:
Operation:
Status Affected:
Description:
After the Move, the FSR value will be
either:
None
•
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assem-
ble as ‘0’s.
Status Affected:
Z
Words:
1
1
Cycles:
Example:
Mode
Syntax
MOVLW
0x5A
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
After Instruction
W
=
0x5A
MOVWF
Move W to f
[ label ] MOVWF
0 f 127
(W) (f)
Syntax:
f
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Operands:
Operation:
Status Affected:
Description:
None
Move data from W register to register
‘f’.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
Words:
1
1
Cycles:
Example:
MOVWF
Before Instruction
OPTION =
OPTION
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
0xFF
0x4F
W
=
After Instruction
OPTION =
W
0x4F
0x4F
=
MOVLB
Move literal to BSR
Syntax:
[ label ] MOVLB
0 k 15
k BSR
None
k
Operands:
Operation:
Status Affected:
Description:
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
DS41414A-page 376
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
NOP
No Operation
MOVWI
Move W to INDFn
Syntax:
[ label ] NOP
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Operands:
Operation:
Status Affected:
Description:
Words:
None
No operation
None
No operation.
Operands:
Operation:
n [0,1]
-32 k 31
If not present, k = 0.
1
Cycles:
1
W INDFn
Effective address is determined by
Example:
NOP
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
Load OPTION_REG Register
with W
OPTION
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Syntax:
[ label ] OPTION
None
Unchanged
Operands:
Operation:
Status Affected:
Description:
Status Affected:
None
(W) OPTION_REG
None
Mode
Syntax
Move data from W register to
OPTION_REG register.
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRFn++
FSRn--
RESET
Software Reset
Syntax:
[ label ] RESET
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Operands:
Operation:
None
Execute a device Reset. Resets the
nRI flag of the PCON register.
Status Affected:
Description:
None
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
This instruction provides a way to
execute a hardware Reset by soft-
ware.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 377
PIC16F/LF1946/47
RETURN
Return from Subroutine
RETFIE
Syntax:
Return from Interrupt
[ label ] RETFIE k
None
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
TOS PC
None
TOS PC,
1 GIE
Status Affected:
Description:
None
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a two-cycle
instruction.
Words:
1
Cycles:
Example:
2
RETFIE
After Interrupt
PC
=
TOS
GIE =
1
RETLW
Syntax:
Return with literal in W
RLF
Rotate Left f through Carry
[ label ] RETLW
0 k 255
k
Syntax:
Operands:
[ label ]
RLF f,d
Operands:
Operation:
0 f 127
d [0,1]
k (W);
TOS PC
Operation:
See description below
C
Status Affected:
Description:
None
Status Affected:
Description:
The W register is loaded with the eight
bit literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words:
1
2
C
Register f
Cycles:
Example:
CALL TABLE;W contains table
;offset value
Words:
1
1
Cycles:
Example:
•
•
•
;W now has table value
TABLE
RLF
REG1,0
Before Instruction
ADDWF PC ;W = offset
RETLW k1 ;Begin table
REG1
C
=
=
1110 0110
0
RETLW k2
;
After Instruction
•
•
•
REG1
W
C
=
=
=
1110 0110
1100 1100
1
RETLW kn ; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
DS41414A-page 378
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
SUBLW
Subtract W from literal
RRF
Rotate Right f through Carry
Syntax:
[ label ] SUBLW
0 k 255
k
Syntax:
[ label ] RRF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 f 127
d [0,1]
k - (W) W)
C, DC, Z
Operation:
See description below
C
The W register is subtracted (2’s com-
plement method) from the eight-bit
literal ‘k’. The result is placed in the W
register.
Status Affected:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
C = 0
W k
C = 1
W k
C
Register f
DC = 0
DC = 1
W<3:0> k<3:0>
W<3:0> k<3:0>
SUBWF
Subtract W from f
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Syntax:
[ label ] SUBWF f,d
Syntax:
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
Operation:
(f) - (W) destination)
Status Affected:
Description:
C, DC, Z
0 PD
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
Status Affected:
Description:
TO, PD
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
C = 0
W f
The processor is put into Sleep mode
with the oscillator stopped.
C = 1
W f
DC = 0
DC = 1
W<3:0> f<3:0>
W<3:0> f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(f) – (W) – (B) dest
Status Affected:
Description:
C, DC, Z
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 379
PIC16F/LF1946/47
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW
0 k 255
k
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k W)
Z
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
The contents of the W register are
XOR’ed with the eight-bit
literal ‘k’. The result is placed in the
W register.
Status Affected:
Description:
None
The upper and lower nibbles of regis-
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
XORWF
Exclusive OR W with f
TRIS
Load TRIS Register with W
Syntax:
[ label ] XORWF f,d
Syntax:
[ label ] TRIS f
5 f 7
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) TRIS register ‘f’
None
Operation:
(W) .XOR. (f) destination)
Status Affected:
Description:
Z
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.
DS41414A-page 380
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
29.0 ELECTRICAL SPECIFICATIONS
(†)
Absolute Maximum Ratings
Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V
Voltage on VCAP pin with respect to VSS.............................................................................................. -0.3V to +4.0V
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin, -40°C TA +85°C for industrial............................................................... 425 mA
Maximum current out of VSS pin, -40°C TA +125°C for extended ............................................................ 175 mA
Maximum current into VDD pin, -40°C TA +85°C for industrial.................................................................. 425 mA
Maximum current into VDD pin, -40°C TA +125°C for extended............................................................... 175 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 381
PIC16F/LF1946/47
FIGURE 29-1:
PIC16F/LF1946/47 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
5.5
3.6
2.5
2.0
1.8
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 29-1 for each Oscillator mode’s supported frequencies.
FIGURE 29-2:
PIC16F/LF1946/47 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
3.6
2.5
2.3
2.0
1.8
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 29-1 for each Oscillator mode’s supported frequencies.
DS41414A-page 382
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 29-3:
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
± 5%
85
60
25
± 2.5%
± 2%
0
-20
± 5%
-40
1.8
2.0
2.5
3.5
4.0
VDD (V)
4.5
5.0
5.5
3.0
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 383
PIC16F/LF1946/47
29.1 DC Characteristics: PIC16F/LF1946/47-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F1946/47
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param.
No.
Sym.
Characteristic
Supply Voltage
Min.
Typ† Max.
Units
Conditions
D001
VDD
PIC16LF1946/47
1.8
2.3
—
—
3.6
3.6
V
V
FOSC 16 MHz:
FOSC 32 MHz (NOTE 2)
D001
PIC16F1946/47
1.8
2.3
—
—
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 32 MHz (NOTE 2)
D002*
VDR
RAM Data Retention Voltage(1)
PIC16LF1946/47
1.5
1.7
—
—
—
—
—
—
V
V
V
Device in Sleep mode
Device in Sleep mode
D002*
PIC16F1946/47
Power-on Reset Release Voltage
Power-on Reset Rearm Voltage
PIC16LF1946/47
VPOR*
1.6
VPORR*
—
—
0.8
1.7
—
—
V
V
Device in Sleep mode
Device in Sleep mode
PIC16F1946/47
D003
VADFVR
Fixed Voltage Reference Voltage
for ADC, Initial Accuracy
-6
-7
-7
-8
-7
-8
—
—
—
—
—
—
4
4
6
6
4
4
%
1.024V, VDD 1.8V, 85°C(3)
1.024V, VDD 1.8V, 125°C(3)
2.048V, VDD 2.5V, 85°C
2.048V, VDD 2.5V, 125°C
4.096V, VDD 4.75V, 85°C
4.096V, VDD 4.75V, 125°C
D003A
D003B
VCDAFVR
Fixed Voltage Reference Voltage
for Comparator and DAC, Initial
Accuracy
-7
-8
-8
-9
-8
-8
—
—
—
—
—
—
5
5
7
7
4
4
%
1.024V, VDD 1.8V, 85°C
1.024V, VDD 1.8V, 125°C
2.048V, VDD 2.5V, 85°C
2.048V, VDD 2.5V, 125°C
4.096V, VDD 4.75V, 85°C
4.096V, VDD 4.75V, 125°C
VLCDFVR
Fixed Voltage Reference Voltage
for LCD Bias, Initial Accuracy
-9
-9.5
—
—
9
9
%
3.072V, VDD 3.6V, 85°C
3.072V, VDD 3.6V, 125°C
D003C* TCVFVR
Temperature Coefficient, Fixed
Voltage Reference
—
-130
0.270
—
—
—
—
ppm/°C
%/V
D003D* VFVR/
VIN
Line Regulation, Fixed Voltage Ref-
erence
—
D004*
SVDD
VDD Rise Rate to ensure internal
0.05
V/ms
See Section 6.1 “Power-on Reset
(POR)” for details.
Power-on Reset signal
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: PLL required for 32 MHz operation.
3: Selection not usable as ADC reference voltage.
DS41414A-page 384
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 29-4:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
(3)
(2)
TPOR
TVLOW
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 385
PIC16F/LF1946/47
29.2 DC Characteristics: PIC16F/LF1946/47-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
PIC16LF1946/47
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F1946/47
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Device
Min.
Typ†
Max.
Units
No.
Characteristics
VDD
Note
(1, 2)
Supply Current (IDD)
LDO Regulator
D009
—
350
—
A
—
HS, EC OR INTOSC/INTOSCIO (8-16 MHZ)
Clock modes with all VCAP pins disabled
—
—
—
50
30
5
A
A
A
—
—
—
All VCAP pins disabled
VCAP enabled on RF0
—
—
—
LP Clock mode and Sleep (requires FVR and
BOR to be disabled)
D010
D010
—
—
7.0
9.0
16
20
A
A
1.8
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40°C TA +85°C
—
—
—
—
—
24
30
40
45
50
—
—
A
A
A
A
A
1.8
3.0
5.0
1.8
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4, 5),
-40°C TA +85°C
32
D010A
D010A
7.0
9.0
FOSC = 32 kHz
LP Oscillator mode (Note 4)
-40°C TA +125°C
—
—
—
—
—
—
—
—
—
—
—
—
—
24
30
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
—
—
FOSC = 32 kHz
LP Oscillator mode (Note 4, 5)
-40°C TA +125°C
32
—
D011
D011
75
FOSC = 1 MHz
XT Oscillator mode
150
225
175
250
690
350
700
450
800
1320
150
95
FOSC = 1 MHz
XT Oscillator mode (Note 5)
170
390
210
390
230
410
930
D012
D012
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode (Note 5)
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP (RF0).
6: 8 MHz crystal oscillator with 4x PLL enabled.
DS41414A-page 386
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
29.2 DC Characteristics: PIC16F/LF1946/47-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF1946/47
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F1946/47
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Device
Min.
Typ†
Max.
Units
No.
Characteristics
VDD
Note
(1, 2)
Supply Current (IDD)
D013
D013
—
—
—
—
—
—
—
25
45
A
A
A
A
A
A
A
1.8
3.0
1.8
3.0
5.0
1.8
3.0
FOSC = 500 kHz
EC Oscillator Low-Power mode
50
90
40
FOSC = 500 kHz
EC Oscillator Low-Power mode (Note 5)
110
200
350
350
600
60
225
190
330
D014
D014
FOSC = 4 MHz
EC Oscillator mode
Medium Power mode
—
—
—
—
—
—
—
—
—
—
—
—
220
350
980
2.6
3.2
2.6
6.0
5
450
700
1390
4.5
5.0
4.5
8.0
12
A
A
A
mA
mA
mA
mA
A
A
A
A
A
1.8
3.0
5.0
3.0
3.6
3.0
5.0
1.8
3.0
1.8
3.0
5.0
FOSC = 4 MHz
EC Oscillator mode (Note 5)
Medium Power mode
D015
D015
D016
D016
FOSC = 32 MHz
EC Oscillator High-Power mode
FOSC = 32 MHz
EC Oscillator High-Power mode (Note 5)
FOSC = 32 kHz
LFINTOSC mode, 85°C
8
16
21
FOSC = 32 kHz
LFINTOSC mode, 85°C (Note 5)
35
27
40
28
45
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP (RF0).
6: 8 MHz crystal oscillator with 4x PLL enabled.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 387
PIC16F/LF1946/47
29.2 DC Characteristics: PIC16F/LF1946/47-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF1946/47
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F1946/47
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Device
Min.
Typ†
Max.
Units
No.
Characteristics
VDD
Note
(1, 2)
Supply Current (IDD)
D017
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
130
190
150
210
270
610
990
0.650
1.1
A
A
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
3.0
3.6
3.0
5.0
FOSC = 500 kHz
MFINTOSC mode
175
250
250
345
425
1000
1500
1.1
D017
A
FOSC = 500 kHz
MFINTOSC mode (Note 5)
A
A
D018
D018
A
FOSC = 8 MHz
HFINTOSC mode
A
mA
mA
mA
mA
mA
mA
mA
mA
A
FOSC = 8 MHz
HFINTOSC mode (Note 5)
1.6
2.0
2.8
D019
D019
1.0
FOSC = 16 MHz
HFINTOSC mode
1.5
1.5
2.5
1.1
1.6
FOSC = 16 MHz
HFINTOSC mode (Note 5)
1.6
2.6
3.1
4.6
D020
D020
200
350
240
370
860
2.6
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
350
550
400
650
1350
4.5
A
A
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
A
A
D021
D021
mA
mA
mA
mA
FOSC = 32 MHz
HS Oscillator mode (Note 6)
3.2
5.0
2.6
4.5
FOSC = 32 MHz
HS Oscillator mode (Note 5, Note 6)
6.0
8.0
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP (RF0).
6: 8 MHz crystal oscillator with 4x PLL enabled.
DS41414A-page 388
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
29.3 DC Characteristics: PIC16F/LF1946/47-I/E (Power-Down)
Standard Operating Conditions (unless otherwise stated)
PIC16LF1946/47
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F1946/47
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Max.
Max.
Device Characteristics
Min.
Typ†
Units
No.
+85°C +125°C
VDD
Note
(2)
Power-down Base Current (IPD)
D023
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.06
0.08
15
1
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
3.0
3.0
5.0
1.8
3.0
1.8
3.0
5.0
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
D023
35
40
45
6
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
18
19
D024
D024
0.5
0.8
16
LPWDT Current (Note 1)
LPWDT Current (Note 1)
7
35
40
45
23
26
50
72
120
TBD
57
100
5
19
20
D025
D025
8.5
8.5
32
FVR current
FVR current (Note 4)
39
70
D026
D026
7.5
34
BOR Current (Note 1)
BOR Current (Note 1, Note 4)
67
D027
D027
0.6
1.8
16
T1OSC Current (Note 1)
T1OSC Current (Note 1)
6
35
40
45
21
25
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Legend:
TBD = To Be Determined
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
4: 0.1 F capacitor on VCAP (RF0).
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 389
PIC16F/LF1946/47
29.3 DC Characteristics: PIC16F/LF1946/47-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF1946/47
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F1946/47
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Max.
Max.
Device Characteristics
Min.
Typ†
Units
No.
+85°C +125°C
VDD
Note
(2)
Power-down Base Current (IPD)
D028
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.1
0.1
16
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
3.0
3.0
3.0
5.0
5.0
5.0
A/D Current (Note 1, Note 3), no
conversion in progress
6
D028
35
40
50
—
—
—
—
—
7
A/D Current (Note 1, Note 3), no
conversion in progress
21
25
D029
D029
250
250
280
280
280
3.5
7
A/D Current (Note 1, Note 3),
conversion in progress
A/D Current (Note 1, Note 3,
Note 4), conversion in progress
D030
D030
Cap Sense, Low Power mode
Cap Sense, Low Power mode
9
17
38
50
70
—
—
—
—
—
—
21
22
D031
D031
1
LCD Bias Ladder, Low-power
LCD Bias Ladder, Medium-power
LCD Bias Ladder, High-power
LCD Bias Ladder, Low-power
LCD Bias Ladder, Medium-power
LCD Bias Ladder, High-power
10
100
1.7
17
170
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Legend:
TBD = To Be Determined
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
4: 0.1 F capacitor on VCAP (RF0).
DS41414A-page 390
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
29.4 DC Characteristics: PIC16F/LF1946/47-I/E
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
VIL
Input Low Voltage
I/O PORT:
D032
D032A
D033
with TTL buffer
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.8
V
V
V
V
V
V
V
4.5V VDD 5.5V
0.15 VDD
0.2 VDD
0.3 VDD
0.8
1.8V VDD 4.5V
2.0V VDD 5.5V
with Schmitt Trigger buffer
2
with I C™ levels
with SMBus levels
2.7V VDD 5.5V
(1)
D034
MCLR, OSC1 (RC mode)
0.2 VDD
0.3 VDD
D034A
OSC1 (HS mode)
Input High Voltage
I/O ports:
VIH
D040
with TTL buffer
2.0
—
—
—
—
V
V
4.5V VDD 5.5V
1.8V VDD 4.5V
D040A
0.25 VDD +
0.8
D041
with Schmitt Trigger buffer
0.8 VDD
0.7 VDD
2.1
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
2.0V VDD 5.5V
2.7V VDD 5.5V
2
with I C™ levels
with SMBus levels
MCLR
D042
0.8 VDD
0.7 VDD
0.9 VDD
D043A
D043B
OSC1 (HS mode)
OSC1 (RC mode)
(Note 1)
(2)
IIL
Input Leakage Current
D060
I/O ports
—
—
± 5
± 125
nA
VSS VPIN VDD, Pin at high-
impedance @ 85°C
± 5
± 1000
± 200
nA 125°C
(3)
D061
MCLR
± 50
nA
A
V
VSS VPIN VDD @ 85°C
IPUR
VOL
Weak Pull-up Current
D070*
25
25
100
140
200
300
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
(4)
Output Low Voltage
D080
D090
I/O ports
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
—
—
—
0.6
—
(4)
VOH
Output High Voltage
I/O ports
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
VDD - 0.7
V
Legend:
TBD = To Be Determined
These parameters are characterized but not tested.
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 391
PIC16F/LF1946/47
29.4 DC Characteristics: PIC16F/LF1946/47-I/E (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
Capacitive Loading Specs on Output Pins
D101*
COSC2 OSC2 pin
—
—
—
15
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO
All I/O pins
—
50
pF
VCAP Capacitor Charging
Charging current
D102
—
—
200
0.0
—
—
A
mA
D102A
Source/sink capability when
charging complete
Legend:
TBD = To Be Determined
These parameters are characterized but not tested.
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
DS41414A-page 392
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
29.5 Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
DC CHARACTERISTICS
Param
Sym.
No.
Characteristic
Program Memory
Min.
Typ†
Max.
Units
Conditions
Programming Specifications
D110
D111
VIHH
IDDP
Voltage on MCLR/VPP/RE3 pin
8.0
—
—
—
9.0
10
V
(Note 3, Note 4)
Supply Current during
Programming
mA
D112
D113
VDD for Bulk Erase
2.7
—
—
VDD
max.
V
V
VPEW
VDD for Write or Row Erase
VDD
min.
VDD
max.
D114
D115
IPPPGM Current on MCLR/VPP during Erase/
Write
—
—
1.0
mA
mA
IDDPGM Current on VDD during Erase/Write
—
5.0
Data EEPROM Memory
D116
D117
ED
Byte Endurance
100K
—
—
—
E/W -40C to +85C
VDD
min.
VDD
max.
VDRW VDD for Read/Write
V
D118
D119
TDEW Erase/Write Cycle Time
TRETD Characteristic Retention
—
4.0
—
5.0
—
ms
20
Year -40°C to +55°C
Provided no other
specifications are violated
D120
TREF
Number of Total Erase/Write
Cycles before Refresh
1M
10M
—
—
E/W -40°C to +85°C
(2)
Program Flash Memory
Cell Endurance
D121
D122
EP
10K
—
—
E/W -40C to +85C (Note 1)
VDD
min.
VDD
max.
VPR
VDD for Read
V
D123
D124
TIW
Self-timed Write Cycle Time
—
2
2.5
—
ms
TRETD Characteristic Retention
40
—
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Refer to Section 11.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Required only if single-supply programming is disabled.
4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be
placed between the ICD 2 and target system when programming or debugging with the ICD 2.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 393
PIC16F/LF1946/47
29.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No.
Sym.
JA
Characteristic
Typ.
Units
Conditions
64-pin TQFP package
48.3
28
C/W
C/W
C/W
C/W
C
TH01
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
64-pin QFN package
64-pin TQFP package
64-pin QFN package
TH02
JC
26.1
0.24
150
—
TH03
TH04
TH05
TH06
TH07
TJMAX
PD
Maximum Junction Temperature
Power Dissipation
W
PD = PINTERNAL + PI/O
PINTERNAL = IDD x VDD
(1)
PINTERNAL Internal Power Dissipation
—
W
PI/O
I/O Power Dissipation
Derated Power
—
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
(2)
PDER
—
W
PDER = PDMAX (TJ - TA)/JA
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
DS41414A-page 394
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
29.7
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O PORT
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 29-5:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 395
PIC16F/LF1946/47
29.8 AC Characteristics: PIC16F/LF1946/47-I/E
FIGURE 29-6:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 29-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
(1)
OS01
FOSC
TOSC
TCY
External CLKIN Frequency
DC
DC
DC
—
—
—
0.5
4
MHz EC Oscillator mode (low)
MHz EC Oscillator mode (medium)
MHz EC Oscillator mode (high)
—
32
—
4
(1)
Oscillator Frequency
32.768
—
kHz
LP Oscillator mode
0.1
1
MHz XT Oscillator mode
—
4
MHz HS Oscillator mode, VDD 2.5V
MHz HS Oscillator mode, VDD > 2.5V
MHz RC Oscillator mode
1
—
20
4
DC
27
—
(1)
OS02
External CLKIN Period
—
s
ns
ns
ns
s
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
TCY = 4/FOSC
250
50
—
—
31.25
—
—
(1)
Oscillator Period
30.5
—
—
10,000
1,000
—
DC
—
—
—
250
50
—
250
200
2
—
(1)
OS03
Instruction Cycle Time
TCY
—
OS04*
TosH,
TosL
External CLKIN High,
External CLKIN Low
LP oscillator
100
20
—
XT oscillator
—
HS oscillator
OS05*
TosR,
TosF
External CLKIN Rise,
External CLKIN Fall
0
—
LP oscillator
0
—
XT oscillator
0
—
HS oscillator
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS41414A-page 396
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 29-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
Sym.
No.
Freq.
Tolerance
Characteristic
Min. Typ† Max. Units
Conditions
OS08
HFOSC
Internal Calibrated HFINTOSC
Frequency
2%
2.5
5%
2%
2.5%
5%
—
—
—
—
—
—
—
—
16.0
16.0
16.0
500
500
500
5
—
—
—
—
—
—
8
MHz 0°C TA +60°C, VDD 2.5V
MHz 60°C TA +85°C, VDD 2.5V
MHz -40°C TA +125°C
kHz 0°C TA +60°C, VDD 2.5V
kHz 60°C TA +85°C, VDD 2.5V
kHz -40°C TA +125°C
s
(2)
OS08A MFOSC
Internal Calibrated MFINTOSC
(2)
Frequency
OS10* TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
MFINTOSC
Wake-up from Sleep Start-up Time
—
—
20
30
s
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
TABLE 29-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)
Param
Sym.
Characteristic
Min.
Typ†
Max.
Units Conditions
No.
F10
FOSC Oscillator Frequency Range
4
16
—
—
—
—
8
32
MHz
MHz
ms
F11
FSYS On-Chip VCO System Frequency
F12
F13*
TRC
PLL Start-up Time (Lock Time)
—
2
CLK CLKOUT Stability (Jitter)
-0.25%
+0.25%
%
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 397
PIC16F/LF1946/47
FIGURE 29-7:
CLKOUT AND I/O TIMING
Cycle
Write
Q4
Fetch
Q1
Read
Q2
Execute
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS13
OS18
OS16
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
DS41414A-page 398
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 29-4: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
OS11 TosH2ckL FOSC to CLKOUT (1)
OS12 TosH2ckH FOSC to CLKOUT (1)
OS13 TckL2ioV CLKOUT to Port out valid(1)
—
—
—
—
—
—
70
72
20
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
ns
OS14 TioV2ckH Port input valid before CLKOUT(1)
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid
TOSC + 200 ns
—
50
—
—
70*
—
ns
—
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
OS16 TosH2ioI
Fosc (Q2 cycle) to Port input invalid
50
(I/O in hold time)
OS17 TioV2osH Port input valid to Fosc(Q2 cycle)
20
—
—
ns
(I/O in setup time)
OS18 TioR
OS19 TioF
Port output rise time(2)
—
—
40
15
72
32
ns
ns
VDD = 1.8V
VDD = 3.3-5.0V
Port output fall time(2)
—
—
28
15
55
30
VDD = 1.8V
VDD = 3.3-5.0V
OS20* Tinp
OS21* Tioc
INT pin input high or low time
25
25
—
—
—
—
ns
ns
Interrupt-on-change new input level
time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Includes OSC2 in CLKOUT mode.
FIGURE 29-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
(1)
Internal Reset
Watchdog Timer
(1)
Reset
31
34
34
I/O pins
Note 1: Asserted low.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 399
PIC16F/LF1946/47
FIGURE 29-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(1)
33
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
2 ms delay if PWRTE = 0and VREGEN = 1.
DS41414A-page 400
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 29-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
TMCL
Characteristic
Min. Typ† Max. Units
Conditions
30
MCLR Pulse Width (low)
2
5
—
—
—
—
s VDD = 3.3-5V, -40°C to +85°C
s VDD = 3.3-5V
31
TWDTLP Low-Power Watchdog Timer
Time-out Period (No Prescaler)
10
18
27
ms VDD = 3.3V-5V
32
TOST
Oscillator Start-up Timer Period(1), (2)
—
1024
65
—
140
2.0
Tosc (Note 3)
33*
34*
TPWRT Power-up Timer Period, PWRTE = 0 40
ms
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
—
—
s
35
VBOR
Brown-out Reset Voltage
2.38
1.80
2.5
1.9
2.73
2.11
V
BORV=2.5V
BORV=1.9V
36*
37*
VHYST
Brown-out Reset Hysteresis
0
1
25
3
50
5
mV -40°C to +85°C
TBORDC Brown-out Reset DC Response
Time
s VDD VBOR
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 29-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 401
PIC16F/LF1946/47
TABLE 29-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
Typ†
Max.
Units
Conditions
40*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45*
TT1H
T1CKI High Synchronous, No Prescaler
0.5 TCY + 20
15
—
—
—
—
ns
ns
Time
Synchronous,
with Prescaler
Asynchronous
30
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
46*
47*
TT1L
TT1P
T1CKI Low Synchronous, No Prescaler
0.5 TCY + 20
Time
Synchronous, with Prescaler
Asynchronous
15
30
T1CKI Input Synchronous
Period
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
—
—
ns
48
FT1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
32.4
32.768
33.1
kHz
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC
—
7 TOSC
—
Timers in Sync
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 29-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)
CC01
CC02
CC03
Note: Refer to Figure 29-5 for load conditions.
TABLE 29-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
CC01* TccL CCPx Input Low Time
CC02* TccH CCPx Input High Time
CC03* TccP CCPx Input Period
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
20
0.5TCY + 20
20
3TCY + 40
N
N = prescale value (1, 4 or 16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS41414A-page 402
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 29-8: PIC16F/LF1946/47 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
AD01 NR
AD02 EIL
AD03 EDL
Resolution
—
—
—
—
—
—
10
±1.7
±1
bit
Integral Error
LSb VREF = 3.0V
Differential Error
LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error
—
—
—
—
—
—
—
±2
±1.5
VDD
VREF
50
LSb VREF = 3.0V
AD05 EGN Gain Error
LSb VREF = 3.0V
(3)
AD06 VREF Reference Voltage
AD07 VAIN Full-Scale Range
1.8
VSS
—
V
V
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
k Can go higher if external 0.01F capacitor is
present on input pin.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
TABLE 29-9: PIC16F/LF1946/47 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max. Units
Conditions
AD130* TAD
A/D Clock Period
1.0
1.0
—
9.0
6.0
s
s
TOSC-based
ADCS<1:0> = 11(ADRC mode)
A/D Internal RC Oscillator
Period
1.6
AD131 TCNV Conversion Time (not including
—
—
11
—
—
TAD Set GO/DONE bit to conversion
complete
(1)
Acquisition Time)
AD132* TACQ Acquisition Time
5.0
s
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 403
PIC16F/LF1946/47
FIGURE 29-12:
PIC16F/LF1946/47 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2
AD134
Q4
)
AD131
AD130
A/D CLK
7
6
5
4
3
2
1
0
A/D Data
ADRES
NEW_DATA
1 TCY
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
FIGURE 29-13:
PIC16F/LF1946/47 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
Q4
(1)
(TOSC/2 + TCY
1 TCY
)
AD131
AD130
A/D CLK
A/D Data
7
6
5
3
2
1
0
4
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
DS41414A-page 404
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 29-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym.
Characteristics
Input Offset Voltage
Min.
Typ.
Max.
Units
Comments
CM01
VIOFF
—
0
±7.5
—
±60
VDD
—
mV
V
CM02
CM03
CM04
CM05
VICM
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time
CMRR
TRESP
—
—
—
50
dB
ns
s
150
—
400
10
Note 1
TMC2OV Comparator Mode Change to
Output Valid*
CM06
CHYSTER Comparator Hysteresis
—
65
—
mV
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
TABLE 29-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym.
Characteristics
Step Size(2)
Min.
Typ.
Max.
Units
Comments
DAC01*
DAC02*
DAC03*
DAC04*
*
CLSB
—
—
—
—
VDD/32
—
—
1/2
—
V
LSb
CACC
CR
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
TBD
—
CST
10
s
These parameters are characterized but not tested.
Legend: TBD = To Be Determined
Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
FIGURE 29-14:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
DT
US121
US121
US122
US120
Refer to Figure 29-5 for load conditions.
Note:
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 405
PIC16F/LF1946/47
TABLE 29-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param.
Symbol
No.
Characteristic
Min.
Max.
Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
US121 TCKRF
Clock out rise time and fall time
(Master mode)
50
US122 TDTRF
Data-out rise time and fall time
45
50
FIGURE 29-15:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
DT
US125
US126
Note: Refer to Figure 29-5 for load conditions.
TABLE 29-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param.
Symbol
No.
Characteristic
Min.
Max. Units
Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK (DT hold time)
10
15
—
—
ns
ns
US126 TCKL2DTL Data-hold after CK (DT hold time)
DS41414A-page 406
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
FIGURE 29-16:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP70
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
LSb In
SP74
SP73
Note: Refer to Figure 29-5 for load conditions.
FIGURE 29-17:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71
SP73
SP72
SP79
SCK
(CKP = 1)
SP80
SP78
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
SP74
Note: Refer to Figure 29-5 for load conditions.
LSb In
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 407
PIC16F/LF1946/47
FIGURE 29-18:
SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
SDO
SDI
bit 6 - - - - - -1
SP77
SP75, SP76
bit 6 - - - -1
MSb In
SP74
SP73
LSb In
Note: Refer to Figure 29-5 for load conditions.
FIGURE 29-19:
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SS
SP83
SCK
(CKP = 0)
SP72
SP71
SCK
(CKP = 1)
SP80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
SP77
SP75, SP76
bit 6 - - - -1
MSb In
SP74
LSb In
Note: Refer to Figure 29-5 for load conditions.
DS41414A-page 408
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 29-14: SPI MODE REQUIREMENTS
Param
Symbol
Characteristic
Min.
Typ† Max. Units Conditions
No.
SP70* TSSL2SCH, SS to SCK or SCK input
TCY
—
—
ns
TSSL2SCL
SP71* TSCH
SP72* TSCL
SCK input high time (Slave mode)
SCK input low time (Slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK edge
TDIV2SCL
SP74* TSCH2DIL, Hold time of SDI data input to SCK edge
TSCL2DIL
100
—
—
ns
SP75* TDOR
SDO data output rise time
3.0-5.5V
1.8-5.5V
—
—
—
10
—
—
—
—
—
Tcy
10
25
10
—
10
25
10
—
—
—
25
50
25
50
25
50
25
50
145
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP76* TDOF
SDO data output fall time
SP77* TSSH2DOZ SS to SDO output high-impedance
SP78* TSCR
SCK output rise time
(Master mode)
3.0-5.5V
1.8-5.5V
SP79* TSCF
SCK output fall time (Master mode)
SP80* TSCH2DOV, SDO data output valid after
TSCL2DOV SCK edge
3.0-5.5V
1.8-5.5V
SP81* TDOV2SCH, SDO data output setup to SCK edge
TDOV2SCL
SP82* TSSL2DOV SDO data output valid after SS edge
—
—
—
50
—
ns
ns
SP83* TSCH2SSH, SS after SCK edge
1.5TCY + 40
TSCL2SSH
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 29-20:
I2C™ BUS START/STOP BITS TIMING
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 29-5 for load conditions.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 409
PIC16F/LF1946/47
TABLE 29-15: I2C™ BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol
Characteristic
Min. Typ Max. Units
Conditions
SP90* TSU:STA Start condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
Start condition
SP91* THD:STA Start condition
Hold time
4000
600
ns After this period, the first
clock pulse is generated
SP92* TSU:STO Stop condition
Setup time
4700
600
ns
SP93 THD:STO Stop condition
Hold time
4000
600
ns
*
These parameters are characterized but not tested.
FIGURE 29-21:
I2C™ BUS DATA TIMING
SP100
SP103
SP102
SP101
SCL
SP90
SP106
SP107
SP92
SP91
SDA
In
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 29-5 for load conditions.
DS41414A-page 410
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
TABLE 29-16: I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min.
Max. Units
Conditions
No.
SP100* THIGH
Clock high time
100 kHz mode
4.0
—
—
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
4.7
—
—
SP101* TLOW
Clock low time
100 kHz mode
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
SSP module
1.3
—
Device must operate at a
minimum of 10 MHz
1.5TCY
—
—
SP102* TR
SP103* TF
SDA and SCL rise 100 kHz mode
time
1000
ns
ns
400 kHz mode
20 + 0.1CB 300
CB is specified to be from
10-400 pF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
250
ns
ns
20 + 0.1CB 250
CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode
400 kHz mode
0
—
0.9
—
ns
s
ns
ns
ns
ns
s
s
0
SP107* TSU:DAT Data input setup
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
250
100
—
(Note 2)
(Note 1)
—
SP109* TAA
Output valid from
clock
3500
—
—
SP110* TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
SP111 CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to
the Standard mode I2C bus specification), before the SCL line is released.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 411
PIC16F/LF1946/47
TABLE 29-17: CAP SENSE OSCILLATOR SPECIFICATIONS
Param.
No.
Symbol
Characteristic
Min.
Typ†
Max. Units
Conditions
CS01
ISRC
Current Source
High
-3
-0.8
-0.1
2.5
0.6
0.1
—
-15
-3
A
A
A
A
A
A
mV
mV
-8
-1.5
-0.3
7.5
Medium
Low
-0.4
14
CS02
ISNK
Current Sink
High
Medium
Low
1.5
2.9
0.6
—
0.25
0.8
CS03 VCTH
CS04 VCTL
Cap Threshold
Cap Threshold
—
0.4
—
CS05 VCHYST Cap Hysteresis
(VCTH-VCTL)
High
Medium
Low
350
250
175
525
375
300
725
500
\425
mV
mV
mV
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 29-22:
CAP SENSE OSCILLATOR
VCTH
VCTL
ISRC
Enabled
ISNK
Enabled
DS41414A-page 412
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
30.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 413
PIC16F/LF1946/47
NOTES:
DS41414A-page 414
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
31.1 MPLAB Integrated Development
Environment Software
31.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 415
PIC16F/LF1946/47
31.2 MPASM Assembler
31.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
31.6 MPLAB SIM Software Simulator
31.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcon-
trollers and the dsPIC30 and dsPIC33 family of digital
signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
31.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS41414A-page 416
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
31.7 MPLAB ICE 2000
High-Performance
31.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
31.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
31.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 417
PIC16F/LF1946/47
31.11 PICSTART Plus Development
Programmer
31.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
31.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS41414A-page 418
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
32.0 PACKAGING INFORMATION
32.1 Package Marking Information
64-Lead QFN (9x9x1mm)
Example
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC16F1947
-I/PT
0610017
64-Lead TQFP (10x10x1mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F1946
-I/PT
0610017
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*
Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 419
PIC16F/LF1946/47
32.2 Package Details
The following sections give the technical details of the packages.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41414A-page 420
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 421
PIC16F/LF1946/47
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DS41414A-page 422
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
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2010 Microchip Technology Inc.
Preliminary
DS41414A-page 423
PIC16F/LF1946/47
NOTES:
DS41414A-page 424
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
APPENDIX A: DATA SHEET
REVISION HISTORY
APPENDIX B: MIGRATING FROM
OTHER PIC®
DEVICES
Revision A
This shows a comparison of features in the migration
from the PIC16F917 device to the PIC16F1946 family
of devices.
Original release (3/2010).
B.1
TABLE B-1:
Feature
PIC16F917 to PIC16F1946
FEATURE COMPARISON
PIC16F917 PIC16F1946
Max. Operating Speed
20 MHz
8K
32 MHz
8K
Max. Program
Memory (Words)
Max. SRAM (Bytes)
A/D Resolution
368
512
10-bit
10-bit
Timers (8/16-bit)
Oscillator Modes
Brown-out Reset
Internal Pull-ups
Interrupt-on-change
Comparator
2/1
4/1
4
8
Y
Y
RB<7:0>
RB<7:0>
RB<7:4>
RB<7:0>
2
1/0
Y
2
0/2
Y
AUSART/EUSART
Extended WDT
Software Control
N
Y
Option of WDT/BOR
INTOSC Frequencies
30 kHz -
8 MHz
31 kHz -
16 MHz
Clock Switching
Capacitive Sensing
CCP/ECCP
Y
N
Y
Y
2/0
N
2/3
Y
Enhanced PIC16 CPU
MSSP/SSP
0/1
Y
2/0
Y
LCD
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 425
PIC16F/LF1946/47
NOTES:
DS41414A-page 426
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
INDEX
EUSART Receive..................................................... 290
EUSART Transmit.................................................... 289
External RC Mode ...................................................... 62
Fail-Safe Clock Monitor (FSCM)................................. 70
Generic I/O Port........................................................ 121
Interrupt Logic............................................................. 83
LCD Bias Voltage Generation .................................. 335
LCD Clock Generation.............................................. 334
On-Chip Reset Circuit................................................. 75
Peripheral Interrupt Logic ........................................... 84
PIC16F/LF1946/47 ............................................... 10, 18
PWM (Enhanced) ..................................................... 216
Resonator Operation .................................................. 61
Timer0 ...................................................................... 187
Timer1 ...................................................................... 191
Timer1 Gate.............................................. 196, 197, 198
Timer2/4/6 ................................................................ 203
Voltage Reference.................................................... 151
Voltage Reference Output Buffer Example .............. 170
BORCON Register.............................................................. 77
BRA .................................................................................. 372
Break Character (12-bit) Transmit and Receive ............... 308
Brown-out Reset (BOR)...................................................... 77
Specifications ........................................................... 401
Timing and Characteristics....................................... 400
A
A/D
Specifications............................................................ 403
Absolute Maximum Ratings (PIC16F/LF1946/47) ............ 381
AC Characteristics
Industrial and Extended ............................................ 396
Load Conditions........................................................ 395
ACKSTAT ......................................................................... 270
ACKSTAT Status Flag ...................................................... 270
ADC .................................................................................. 153
Acquisition Requirements ......................................... 163
Associated registers.................................................. 165
Block Diagram........................................................... 153
Calculating Acquisition Time..................................... 163
Channel Selection..................................................... 154
Configuration............................................................. 154
Configuring Interrupt ................................................. 158
Conversion Clock...................................................... 154
Conversion Procedure .............................................. 158
Internal Sampling Switch (RSS) Impedance.............. 163
Interrupts................................................................... 156
Operation .................................................................. 157
Operation During Sleep ............................................ 157
Port Configuration..................................................... 154
Reference Voltage (VREF)......................................... 154
Source Impedance.................................................... 163
Special Event Trigger................................................ 157
Starting an A/D Conversion ...................................... 156
ADCON0 Register....................................................... 32, 159
ADCON1 Register....................................................... 32, 160
ADDFSR ........................................................................... 371
ADDWFC .......................................................................... 371
ADRESH Register............................................................... 32
ADRESH Register (ADFM = 0)......................................... 161
ADRESH Register (ADFM = 1)......................................... 162
ADRESL Register (ADFM = 0).......................................... 161
ADRESL Register (ADFM = 1).......................................... 162
Alternate Pin Function....................................................... 121
Analog-to-Digital Converter. See ADC
C
C Compilers
MPLAB C18.............................................................. 416
MPLAB C30.............................................................. 416
CALL................................................................................. 373
CALLW ............................................................................. 373
Capacitive Sensing........................................................... 317
Associated registers w/ Capacitive Sensing............. 325
Specifications ........................................................... 412
Capture Module. See Enhanced Capture/Compare/
PWM(ECCP)
Capture/Compare/PWM ................................................... 207
Capture/Compare/PWM (CCP)
Associated Registers w/ Capture ............................. 209
Associated Registers w/ Compare ........................... 211
Associated Registers w/ PWM ......................... 215, 228
Capture Mode........................................................... 208
CCPx Pin Configuration............................................ 208
Compare Mode......................................................... 210
CCPx Pin Configuration.................................... 210
Software Interrupt Mode........................... 208, 210
Special Event Trigger....................................... 210
Timer1 Mode Resource............................ 208, 210
Prescaler .................................................................. 208
PWM Mode
ANSELA Register ............................................................. 125
ANSELE Register ............................................................. 137
ANSELF Register.............................................................. 141
APFCON Register............................................................. 122
Assembler
MPASM Assembler................................................... 416
B
BAUDCON Register.......................................................... 300
BF ............................................................................. 270, 272
BF Status Flag .......................................................... 270, 272
Block Diagram
Capacitive Sensing ........................................... 317, 318
Block Diagrams
Duty Cycle ........................................................ 213
Effects of Reset................................................ 215
Example PWM Frequencies and
(CCP) Capture Mode Operation ............................... 208
ADC .......................................................................... 153
ADC Transfer Function ............................................. 164
Analog Input Model........................................... 164, 177
CCP PWM................................................................. 212
Clock Source............................................................... 59
Comparator............................................................... 174
Compare Mode Operation ........................................ 210
Crystal Operation.................................................. 61, 62
Digital-to-Analog Converter (DAC)............................ 169
Resolutions, 20 MHZ................................ 214
Example PWM Frequencies and
Resolutions, 32 MHZ................................ 214
Example PWM Frequencies and
Resolutions, 8 MHz .................................. 214
Operation in Sleep Mode.................................. 215
Resolution ........................................................ 214
System Clock Frequency Changes .................. 215
PWM Operation........................................................ 212
PWM Overview......................................................... 212
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 427
PIC16F/LF1946/47
PWM Period..............................................................213
PWM Setup...............................................................213
CCP1CON Register ...................................................... 36, 37
CCPR1H Register......................................................... 36, 37
CCPR1L Register.......................................................... 36, 37
CCPTMRS0 Register........................................................230
CCPTMRS1 Register........................................................231
CCPxAS Register..............................................................232
CCPxCON (ECCPx) Register ...........................................229
Clock Accuracy with Asynchronous Operation .................298
Clock Sources
External Modes...........................................................60
EC.......................................................................60
HS.......................................................................60
LP........................................................................60
OST.....................................................................61
RC.......................................................................62
XT .......................................................................60
Internal Modes ............................................................63
HFINTOSC..........................................................63
Internal Oscillator Clock Switch Timing...............65
LFINTOSC ..........................................................64
MFINTOSC .........................................................63
Clock Switching...................................................................67
CMOUT Register...............................................................179
CMxCON0 Register ..........................................................178
CMxCON1 Register ..........................................................179
Code Examples
A/D Conversion.........................................................158
Changing Between Capture Prescalers....................208
Initializing PORTA.....................................................123
Initializing PORTB.....................................................126
Initializing PORTC.....................................................129
Initializing PORTD.....................................................132
Initializing PORTE.....................................................135
Initializing PORTF.....................................................138
Initializing PORTG ....................................................142
Write Verify ...............................................................117
Writing to Flash Program Memory ............................115
Comparator
Associated Registers ................................................180
Operation ..................................................................173
Comparator Module ..........................................................173
Cx Output State Versus Input Conditions .................175
Comparator Specifications................................................405
Comparators
Reading .................................................................... 108
Writing ...................................................................... 108
Data Memory ................................................................ 22, 25
DC and AC Characteristics............................................... 413
DC Characteristics
Extended and Industrial (PIC16F/LF1946/47-I/E)..... 391
Industrial and Extended (PIC16F/LF1946/47).......... 384
Development Support....................................................... 415
Device Configuration .......................................................... 53
Code Protection.......................................................... 57
Configuration Word..................................................... 53
User ID ................................................................. 57, 58
Device Overview........................................................... 9, 103
Digital-to-Analog Converter (DAC) ................................... 167
Associated Registers................................................ 172
Effects of a Reset ..................................................... 169
Specifications ........................................................... 405
E
ECCP/CCP. See Enhanced Capture/Compare/PWM
EEADR Registers ............................................................. 107
EEADRH Registers........................................................... 107
EEADRL Register............................................................. 118
EEADRL Registers ........................................................... 107
EECON1 Register..................................................... 107, 119
EECON2 Register..................................................... 107, 120
EEDATH Register............................................................. 118
EEDATL Register ............................................................. 118
EEPROM Data Memory
Avoiding Spurious Write ........................................... 108
Write Verify............................................................... 117
Effects of Reset
PWM mode............................................................... 215
Electrical Specifications (PIC16F/LF1946/47) .................. 381
Enhanced Capture/Compare/PWM (ECCP)..................... 207
Enhanced PWM Mode.............................................. 216
Auto-Restart ..................................................... 224
Auto-shutdown.................................................. 223
Direction Change in Full-Bridge Output Mode.. 222
Full-Bridge Application...................................... 220
Full-Bridge Mode .............................................. 220
Half-Bridge Application..................................... 219
Half-Bridge Application Examples .................... 225
Half-Bridge Mode.............................................. 219
Output Relationships (Active-High and
Active-Low)............................................... 217
Output Relationships Diagram.......................... 218
Programmable Dead Band Delay..................... 225
Shoot-through Current...................................... 225
Start-up Considerations.................................... 227
Specifications ........................................................... 402
Enhanced Mid-range CPU.................................................. 17
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) .............................. 289
Errata.................................................................................... 7
EUSART ........................................................................... 289
Asynchronous Mode................................................. 291
12-bit Break Transmit and Receive .................. 308
Associated Registers, Receive......................... 297
Associated Registers, Transmit........................ 293
Auto-Wake-up on Break ................................... 306
Baud Rate Generator (BRG) ............................ 301
Clock Accuracy................................................. 298
Receiver ........................................................... 294
Setting up 9-bit Mode with Address Detect ...... 296
Transmitter ....................................................... 291
C2OUT as T1 Gate ...................................................193
Compare Module. See Enhanced Capture/
Compare/PWM (ECCP)
CONFIG1 Register..............................................................54
CONFIG2 Register..............................................................56
Core Registers ....................................................................31
CPSCON0 Register ..........................................................323
CPSCON1 Register ..........................................................324
Customer Change Notification Service .............................435
Customer Notification Service...........................................435
Customer Support.............................................................435
D
DACCON0 (Digital-to-Analog Converter Control 0)
Register.....................................................................171
DACCON1 (Digital-to-Analog Converter Control 1)
Register.....................................................................171
Data EEPROM Memory....................................................107
Associated Registers ................................................120
Code Protection ........................................................108
DS41414A-page 428
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
Baud Rate Generator (BRG)
Stop Condition Timing .............................................. 274
Associated Registers........................................ 302
Auto Baud Rate Detect..................................... 305
Baud Rate Error, Calculating ............................ 301
Baud Rates, Asynchronous Modes .................. 302
Formulas........................................................... 301
High Baud Rate Select (BRGH Bit) .................. 301
Clock polarity
Synchronous Mode........................................... 309
Data Polarity
Asynchronous Receive ..................................... 294
Data polarity
INDF Register
...... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45
Indirect Addressing............................................................. 49
Instruction Format............................................................. 368
Instruction Set................................................................... 367
ADDLW..................................................................... 371
ADDWF .................................................................... 371
ADDWFC.................................................................. 371
ANDLW..................................................................... 371
ANDWF .................................................................... 371
BRA .......................................................................... 372
CALL......................................................................... 373
CALLW ..................................................................... 373
LSLF......................................................................... 375
LSRF ........................................................................ 375
MOVF ....................................................................... 375
MOVIW..................................................................... 376
MOVLB..................................................................... 376
MOVWI..................................................................... 377
OPTION.................................................................... 377
RESET...................................................................... 377
SUBWFB .................................................................. 379
TRIS ......................................................................... 380
BCF .......................................................................... 372
BSF........................................................................... 372
BTFSC...................................................................... 372
BTFSS...................................................................... 372
CALL......................................................................... 373
CLRF ........................................................................ 373
CLRW....................................................................... 373
CLRWDT .................................................................. 373
COMF....................................................................... 373
DECF........................................................................ 373
DECFSZ ................................................................... 374
GOTO....................................................................... 374
INCF ......................................................................... 374
INCFSZ..................................................................... 374
IORLW...................................................................... 374
IORWF...................................................................... 374
MOVLW.................................................................... 376
MOVWF.................................................................... 376
NOP.......................................................................... 377
RETFIE..................................................................... 378
RETLW..................................................................... 378
RETURN................................................................... 378
RLF........................................................................... 378
RRF .......................................................................... 379
SLEEP...................................................................... 379
SUBLW..................................................................... 379
SUBWF..................................................................... 379
SWAPF..................................................................... 380
XORLW .................................................................... 380
XORWF .................................................................... 380
INTCON Register................................................................ 89
Internal Oscillator Block
Asynchronous Transmit .................................... 291
Synchronous Mode........................................... 309
Interrupts
Asynchronous Receive ..................................... 295
Asynchronous Transmit .................................... 291
Synchronous Master Mode............................... 309, 314
Associated Registers, Receive ......................... 313
Associated Registers, Transmit ................ 310, 315
Reception.......................................................... 312
Transmission .................................................... 309
Synchronous Slave Mode
Associated Registers, Receive ......................... 316
Reception.......................................................... 316
Transmission .................................................... 314
Extended Instruction Set
ADDFSR ................................................................... 371
F
Fail-Safe Clock Monitor....................................................... 70
Fail-Safe Condition Clearing....................................... 70
Fail-Safe Detection ..................................................... 70
Fail-Safe Operation..................................................... 70
Reset or Wake-up from Sleep..................................... 70
Firmware Instructions........................................................ 367
Fixed Voltage Reference (FVR)
Associated Registers ................................................ 152
Flash Program Memory .................................................... 107
Erasing...................................................................... 112
Modifying................................................................... 116
Writing....................................................................... 112
FSR Register
...... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45
FVRCON (Fixed Voltage Reference Control) Register..... 152
I
2
I C Mode (MSSPx)
Acknowledge Sequence Timing................................ 274
Bus Collision
During a Repeated Start Condition................... 279
During a Stop Condition.................................... 280
Effects of a Reset...................................................... 275
2
I C Clock Rate w/BRG.............................................. 282
Master Mode
Operation .......................................................... 266
Reception.......................................................... 272
Start Condition Timing .............................. 268, 269
Transmission .................................................... 270
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 275
Multi-Master Mode .................................................... 275
Read/Write Bit Information (R/W Bit) ........................ 251
Slave Mode
INTOSC
Specifications ................................................... 397
Internal Sampling Switch (RSS) Impedance ..................... 163
Internet Address ............................................................... 435
Interrupt-On-Change......................................................... 147
Associated Registers................................................ 149
Interrupts ............................................................................ 83
ADC.......................................................................... 158
Associated registers w/ Interrupts .............................. 98
Transmission .................................................... 256
Sleep Operation........................................................ 275
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 429
PIC16F/LF1946/47
2
Configuration Word w/ Clock Sources ................ 74, 141
Configuration Word w/ LDO........................................99
TMR1 ........................................................................195
INTOSC Specifications .....................................................397
IOCBF Register.................................................................148
IOCBN Register ................................................................148
IOCBP Register.................................................................148
I C Mode .................................................................. 246
I C Mode Operation.................................................. 247
SPI Mode.................................................................. 238
SSPxBUF Register ................................................... 241
SSPxSR Register ..................................................... 241
2
O
OPCODE Field Descriptions............................................. 367
OPTION............................................................................ 377
OPTION Register.............................................................. 189
OSCCON Register.............................................................. 72
Oscillator
Associated Registers.................................................. 74
Oscillator Module................................................................ 59
EC............................................................................... 59
HS............................................................................... 59
INTOSC ...................................................................... 59
LP ............................................................................... 59
RC .............................................................................. 59
XT ............................................................................... 59
Oscillator Parameters ....................................................... 397
Oscillator Specifications.................................................... 396
Oscillator Start-up Timer (OST)
L
LATA Register...................................................................124
LATB Register...................................................................127
LATC Register...................................................................130
LATD Register...................................................................133
LATE Register...................................................................137
LATF Register...................................................................140
LATG Register ..................................................................143
LCD
Associated Registers ................................................360
Bias Voltage Generation ................................... 335, 336
Clock Source Selection.............................................334
Configuring the Module.............................................359
Disabling the Module ................................................359
Frame Frequency......................................................342
Interrupts...................................................................355
LCDCON Register ....................................................327
LCDPS Register........................................................327
Multiplex Types.........................................................342
Operation During Sleep ............................................357
Pixel Control..............................................................342
Prescaler...................................................................334
Segment Enables......................................................342
Waveform Generation...............................................344
LCDCON Register..................................................... 327, 329
LCDCST Register .............................................................332
LCDDATAx Registers ............................................... 333, 340
LCDPS Register........................................................ 327, 330
LP Bits.......................................................................334
LCDREF Register .............................................................331
LCDRL Register................................................................340
LCDSEn Registers............................................................333
Liquid Crystal Display (LCD) Driver ..................................327
Load Conditions ................................................................395
LSLF..................................................................................375
LSRF.................................................................................375
Specifications ........................................................... 401
Oscillator Switching
Fail-Safe Clock Monitor .............................................. 70
Two-Speed Clock Start-up.......................................... 68
OSCSTAT Register ............................................................ 73
OSCTUNE Register............................................................ 74
P
P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/
PWM (ECCP)............................................................ 216
Packaging......................................................................... 419
Marking............................................................. 419, 420
PDIP Details ............................................................. 420
PCL and PCLATH............................................................... 18
PCL Register
...... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45
PCLATH Register
...... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45
PCON Register............................................................. 32, 81
PICSTART Plus Development Programmer..................... 418
PIE1 Register................................................................ 32, 90
PIE2 Register................................................................ 32, 91
PIE3 Register................................................................ 32, 92
PIE4 Register...................................................................... 32
Pin Diagram
M
Master Synchronous Serial Port. See MSSPx
MCLR..................................................................................78
Internal ........................................................................78
Memory Organization
PIC16F/LF1946/47, 64-pin TQFP/QFN ........................ 3
Pinout Descriptions
Data ...................................................................... 22, 25
Program ......................................................................19
Microchip Internet Web Site..............................................435
Migrating from other PIC Microcontroller Devices.............425
MOVIW..............................................................................376
MOVLB..............................................................................376
MOVWI..............................................................................377
MPLAB ASM30 Assembler, Linker, Librarian ...................416
MPLAB ICD 2 In-Circuit Debugger....................................417
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator ....................................................417
MPLAB Integrated Development Environment Software ..415
MPLAB PM3 Device Programmer.....................................417
MPLAB REAL ICE In-Circuit Emulator System.................417
MPLINK Object Linker/MPLIB Object Librarian ................416
MSSPx ..............................................................................235
PIC16F/LF1946/47 ..................................................... 11
PIR1 Register ............................................................... 31, 94
PIR2 Register ............................................................... 31, 95
PIR3 Register ............................................................... 31, 96
PIR4 Register ......................................................... 31, 93, 97
PORTA ............................................................................. 123
ANSELA Register ..................................................... 123
Associated Registers................................................ 125
Configuration Word w/ PORTA................................. 125
LATA Register ............................................................ 33
PORTA Register......................................................... 31
Specifications ........................................................... 399
PORTA Register............................................................... 124
PORTB ............................................................................. 126
Associated Registers................................................ 128
Interrupt-on-Change ................................................. 126
DS41414A-page 430
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
LATB Register............................................................. 33
P1B/P1C/P1D.See Enhanced Capture/Compare/
PWMxCON Register......................................................... 233
R
PWM+ (ECCP+) ............................................... 126
RC2REG Register .............................................................. 40
RC2STA Register ............................................................... 40
RCREG............................................................................. 296
RCREG Register ................................................................ 34
RCSTA Register ......................................................... 34, 299
Reader Response............................................................. 436
Read-Modify-Write Operations ......................................... 367
Register
Pin Functions and Output Priorities .......................... 126
PORTB Register ......................................................... 31
PORTB Register ............................................................... 127
PORTC ............................................................................. 129
Associated Registers ................................................ 131
LATC Register ............................................................ 33
P1A.See Enhanced Capture/Compare/PWM+
(ECCP+) ........................................................... 129
RCREG Register ...................................................... 305
Registers
Pin Functions and Output Priorities .......................... 129
PORTC Register......................................................... 31
Specifications............................................................ 399
PORTC Register............................................................... 130
PORTD ............................................................................. 132
Associated Registers ................................................ 134
LATD Register ............................................................ 33
P1B/P1C/P1D.See Enhanced Capture/Compare/
ADCON0 (ADC Control 0)........................................ 159
ADCON1 (ADC Control 1)........................................ 160
ADRESH (ADC Result High) with ADFM = 0) .......... 161
ADRESH (ADC Result High) with ADFM = 1) .......... 162
ADRESL (ADC Result Low) with ADFM = 0)............ 161
ADRESL (ADC Result Low) with ADFM = 1)............ 162
ANSELA (PORTA Analog Select) ............................ 125
ANSELE (PORTE Analog Select) ............................ 137
ANSELF (PORTF Analog Select)............................. 141
APFCON (Alternate Pin Function Control) ............... 122
BAUDCON (Baud Rate Control)............................... 300
BORCON Brown-out Reset Control) .......................... 77
CCPTMRS0 (PWM Timer Selection Control 0)........ 230
CCPTMRS1 (PWM Timer Selection Control 1)........ 231
CCPxAS (CCPx Auto-Shutdown Control) ................ 232
CCPxCON (ECCPx Control) .................................... 229
CMOUT (Comparator Output) .................................. 179
CMxCON0 (Cx Control)............................................ 178
CMxCON1 (Cx Control 1)......................................... 179
Configuration Word 1.................................................. 54
Configuration Word 2.................................................. 56
CPSCON0 (Capacitive Sensing Control
PWM+ (ECCP+) ............................................... 132
Pin Functions and Output Priorities .......................... 132
PORTD Register......................................................... 31
PORTD Register............................................................... 133
PORTE.............................................................................. 135
ANSELE Register ..................................................... 135
Associated Registers ................................................ 137
LATE Register............................................................. 33
Pin Functions and Output Priorities .......................... 135
PORTE Register ......................................................... 31
PORTE Register ............................................................... 136
PORTF.............................................................................. 138
ANSELF Register...................................................... 138
Associated Registers ................................................ 141
LATF Register............................................................. 38
Pin Functions and Output Priorities .......................... 139
PORTF Register ......................................................... 36
PORTF Register ............................................................... 140
PORTG ............................................................................. 142
ANSELG Register..................................................... 142
Associated Registers ................................................ 145
LATG Register ............................................................ 38
Pin Descriptions and Output Priorities ...................... 142
PORTG Register......................................................... 36
PORTG Register............................................................... 143
Power-Down Mode (Sleep)............................................... 101
Associated Registers ................................................ 102
Power-on Reset .................................................................. 76
Power-up Timer (PWRT) .................................................... 76
Specifications............................................................ 401
PR2 Register................................................................. 31, 39
Precision Internal Oscillator Parameters........................... 397
Program Memory ................................................................ 19
Map and Stack............................................................ 25
Map and Stack (PIC16F/LF1946/47) .................... 20, 25
Map and Stack (PIC16F1946) .................................... 20
Map and Stack (PIC16F1947) .................................... 20
Map and Stack PIC16F/LF1946/47) ........................... 19
Programming Mode Exit ..................................................... 78
Programming, Device Instructions .................................... 367
PSTRxCON Register ........................................................ 234
PWM (ECCP Module)
Register 0)........................................................ 323
CPSCON1 (Capacitive Sensing Control
Register 1)........................................................ 324
DACCON0................................................................ 171
DACCON1................................................................ 171
EEADRL (EEPROM Address).................................. 118
EECON1 (EEPROM Control 1) ................................ 119
EECON2 (EEPROM Control 2) ................................ 120
EEDATH (EEPROM Data) ....................................... 118
EEDATL (EEPROM Data)........................................ 118
FVRCON .................................................................. 152
INTCON (Interrupt Control) ........................................ 89
IOCBF (Interrupt-on-Change Flag)........................... 148
IOCBN (Interrupt-on-Change Negative Edge).......... 148
IOCBP (Interrupt-on-Change Positive Edge)............ 148
LATA (Data Latch PORTA) ...................................... 124
LATB (Data Latch PORTB) ...................................... 127
LATC (Data Latch PORTC)...................................... 130
LATD (Data Latch PORTD)...................................... 133
LATE (Data Latch PORTE) ...................................... 137
LATF (Data Latch PORTF)....................................... 140
LATG (Data Latch PORTG)...................................... 143
LCDCON (LCD Control) ........................................... 329
LCDCST (LCD Contrast Control) ............................. 332
LCDDATAx (LCD Data).................................... 333, 340
LCDPS (LCD Phase)................................................ 330
LCDREF (LCD Reference Voltage Control) ............. 331
LCDRL (LCD Reference Voltage Control)................ 340
LCDSEn (LCD Segment Enable) ............................. 333
OPTION_REG (OPTION)......................................... 189
OSCCON (Oscillator Control)..................................... 72
PWM Steering........................................................... 226
Steering Synchronization.......................................... 227
PWM Mode. See Enhanced Capture/Compare/PWM ...... 216
PWM Steering................................................................... 226
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 431
PIC16F/LF1946/47
OSCSTAT (Oscillator Status) .....................................73
OSCTUNE (Oscillator Tuning)....................................74
PCON (Power Control Register).................................81
PCON (Power Control) ...............................................81
PIE1 (Peripheral Interrupt Enable 1)...........................90
PIE2 (Peripheral Interrupt Enable 2)...........................91
PIE3 (Peripheral Interrupt Enable 3)...........................92
PIR1 (Peripheral Interrupt Register 1) ........................94
PIR2 (Peripheral Interrupt Request 2) ........................95
PIR3 (Peripheral Interrupt Request 3) ........................96
PIR4 (Peripheral Interrupt Request 4) .................. 93, 97
PORTA......................................................................124
PORTB......................................................................127
PORTC .....................................................................130
PORTD .....................................................................133
PORTE......................................................................136
PORTF......................................................................140
PORTG .....................................................................143
PSTRxCON (PWM Steering Control) .......................234
PWMxCON (Enhanced PWM Control) .....................233
RCxSTA (Receive Status and Control).....................299
Special Function, Summary........................................31
SRCON0 (SR Latch Control 0) .................................183
SRCON1 (SR Latch Control 1) .................................184
SSPxADD (MSSPx Address and Baud Rate,
SRCON0 Register ............................................................ 183
SRCON1 Register ............................................................ 184
SSP1ADD Register............................................................. 35
SSP1BUF Register............................................................. 35
SSP1CON1 Register .......................................................... 35
SSP1CON2 Register .......................................................... 35
SSP1CON3 Register .......................................................... 35
SSP1MSK Register ............................................................ 35
SSP1STAT Register........................................................... 35
SSP2ADD Register............................................................. 35
SSP2BUF Register............................................................. 35
SSP2CON1 Register .......................................................... 35
SSP2CON2 Register .......................................................... 35
SSP2CON3 Register .......................................................... 35
SSP2MSK Register ............................................................ 35
SSP2STAT Register........................................................... 35
SSPxADD Register........................................................... 287
SSPxCON1 Register ........................................................ 284
SSPxCON2 Register ........................................................ 285
SSPxCON3 Register ........................................................ 286
SSPxMSK Register........................................................... 287
SSPxOV............................................................................ 272
SSPxOV Status Flag ........................................................ 272
SSPxSTAT Register ......................................................... 283
R/W Bit ..................................................................... 251
Stack................................................................................... 47
Accessing ................................................................... 47
Reset .......................................................................... 49
Stack Overflow/Underflow .................................................. 78
STATUS Register ............................................................... 23
SUBWFB .......................................................................... 379
2
I C Mode)..........................................................287
SSPxCON1 (MSSPx Control 1)................................284
SSPxCON2 (SSPx Control 2)...................................285
SSPxCON3 (SSPx Control 3)...................................286
SSPxMSK (SSPx Mask) ...........................................287
SSPxSTAT (SSPx Status) ........................................283
STATUS......................................................................23
T1CON (Timer1 Control)...........................................199
T1GCON (Timer1 Gate Control)...............................200
TRISA (Tri-State PORTA).........................................124
TRISB (Tri-State PORTB).........................................127
TRISC (Tri-State PORTC) ........................................130
TRISD (Tri-State PORTD) ........................................133
TRISE (Tri-State PORTE).........................................136
TRISF (Tri-State PORTF) .........................................140
TRISG (Tri-State PORTG)........................................143
TXCON .....................................................................205
TXxSTA (Transmit Status and Control) ....................298
WDTCON (Watchdog Timer Control)........................105
WPUB (Weak Pull-up PORTB).................................128
WPUG (Weak Pull-up PORTG) ................................144
RESET ..............................................................................377
Reset Instruction .................................................................78
Resets.................................................................................75
Associated Registers ..................................................82
Revision History ................................................................425
T
T1CON Register ......................................................... 31, 199
T1GCON Register ............................................................ 200
T2CON Register ........................................................... 31, 39
Thermal Considerations (PIC16F/LF1946/47).................. 394
Timer0............................................................................... 187
Associated Registers................................................ 189
Operation.................................................................. 187
Specifications ........................................................... 402
Timer1............................................................................... 191
Associated registers ................................................. 201
Asynchronous Counter Mode ................................... 193
Reading and Writing......................................... 193
Clock Source Selection............................................. 192
Interrupt .................................................................... 195
Operation.................................................................. 192
Operation During Sleep ............................................ 195
Oscillator................................................................... 193
Prescaler .................................................................. 193
Specifications ........................................................... 402
Timer1 Gate
S
Shoot-through Current ......................................................225
Software Simulator (MPLAB SIM).....................................416
SP2BRG Register ...............................................................40
SPBRG..............................................................................301
SPBRG Register ........................................................... 33, 34
SPBRGH...........................................................................301
Special Event Trigger........................................................157
Special Function Registers (SFRs).....................................31
SPI Mode (MSSPx)
Selecting Source .............................................. 193
TMR1H Register....................................................... 191
TMR1L Register........................................................ 191
Timer2
Associated registers ................................................. 206
Timer2/4/6......................................................................... 203
Associated registers ................................................. 206
Timers
Timer1
Associated Registers ................................................245
SPI Clock ..................................................................241
SR Latch ...........................................................................181
Associated registers w/ SR Latch .............................185
T1CON ............................................................. 199
T1GCON........................................................... 200
Timer2/4/6
TXCON............................................................. 205
DS41414A-page 432
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
Timing Diagrams
A/D Conversion......................................................... 404
Type-A in 1/3 Mux, 1/2 Bias Drive............................ 349
Type-A in 1/3 Mux, 1/3 Bias Drive............................ 351
Type-A in 1/4 Mux, 1/3 Bias Drive............................ 353
Type-A/Type-B in Static Drive .................................. 344
Type-B in 1/2 Mux, 1/2 Bias Drive............................ 346
Type-B in 1/2 Mux, 1/3 Bias Drive............................ 348
Type-B in 1/3 Mux, 1/2 Bias Drive............................ 350
Type-B in 1/3 Mux, 1/3 Bias Drive............................ 352
Type-B in 1/4 Mux, 1/3 Bias Drive............................ 354
USART Synchronous Receive (Master/Slave)......... 406
USART Synchronous Transmission
A/D Conversion (Sleep Mode) .................................. 404
Acknowledge Sequence ........................................... 274
Asynchronous Reception.......................................... 297
Asynchronous Transmission..................................... 292
Asynchronous Transmission (Back to Back) ............ 293
Auto Wake-up Bit (WUE) During Normal Operation . 307
Auto Wake-up Bit (WUE) During Sleep .................... 307
Automatic Baud Rate Calculator............................... 306
Baud Rate Generator with Clock Arbitration............. 267
BRG Reset Due to SDA Arbitration During
Start Condition .................................................. 278
Brown-out Reset (BOR)............................................ 400
Brown-out Reset Situations ........................................ 77
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................ 279
Bus Collision During a Repeated Start Condition
(Master/Slave).................................................. 405
Wake-up from Interrupt............................................. 102
Timing Diagrams and Specifications
PLL Clock ................................................................. 397
Timing Parameter Symbology .......................................... 395
Timing Requirements
2
I C Bus Data............................................................. 411
(Case 2) ............................................................ 279
Bus Collision During a Start Condition (SCL = 0) ..... 278
Bus Collision During a Stop Condition (Case 1) ....... 280
Bus Collision During a Stop Condition (Case 2) ....... 280
Bus Collision During Start Condition (SDA only) ...... 277
Bus Collision for Transmit and Acknowledge............ 276
CLKOUT and I/O....................................................... 398
Clock Synchronization .............................................. 264
Clock Timing ............................................................. 396
Comparator Output ................................................... 173
Enhanced Capture/Compare/PWM (ECCP)............. 402
Fail-Safe Clock Monitor (FSCM)................................. 71
First Start Bit Timing ................................................. 268
Full-Bridge PWM Output........................................... 221
Half-Bridge PWM Output .................................. 219, 225
I2C Bus Start/Stop Bits............................................. 410
SPI Mode.................................................................. 409
TMR0 Register.................................................................... 31
TMR1H Register................................................................. 31
TMR1L Register.................................................................. 31
TMR2 Register.............................................................. 31, 39
TRIS ................................................................................. 380
TRISA Register........................................................... 32, 124
TRISB ............................................................................... 126
TRISB Register........................................................... 32, 127
TRISC............................................................................... 129
TRISC Register........................................................... 32, 130
TRISD............................................................................... 132
TRISD Register........................................................... 32, 133
TRISE ............................................................................... 135
TRISE Register........................................................... 32, 136
TRISF ............................................................................... 138
TRISF Register........................................................... 37, 140
TRISG............................................................................... 142
TRISG Register .......................................................... 37, 143
Two-Speed Clock Start-up Mode........................................ 68
TX2REG Register............................................................... 40
TX2STA Register................................................................ 40
TXCON (Timer2/4/6) Register .......................................... 205
TXREG ............................................................................. 291
TXREG Register................................................................. 34
TXSTA Register.......................................................... 34, 298
BRGH Bit.................................................................. 301
2
I C Bus Data............................................................. 410
2
I C Bus Start/Stop Bits.............................................. 409
2
I C Master Mode (7 or 10-Bit Transmission) ............ 271
2
I C Master Mode (7-Bit Reception)........................... 273
2
I C Stop Condition Receive or Transmit Mode......... 275
INT Pin Interrupt.......................................................... 87
Internal Oscillator Switch Timing................................. 66
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 356
LCD Sleep Entry/Exit when SLPEN = 1
or CS = 00......................................................... 358
PWM Auto-shutdown ................................................ 224
Firmware Restart .............................................. 224
PWM Direction Change ............................................ 222
PWM Direction Change at Near 100% Duty Cycle... 223
PWM Output (Active-High)........................................ 217
PWM Output (Active-Low) ........................................ 218
Repeat Start Condition.............................................. 269
Reset Start-up Sequence............................................ 79
Reset, WDT, OST and Power-up Timer ................... 399
Send Break Character Sequence ............................. 308
SPI Master Mode (CKE = 1, SMP = 1) ..................... 407
SPI Mode (Master Mode).......................................... 241
SPI Slave Mode (CKE = 0) ....................................... 408
SPI Slave Mode (CKE = 1) ....................................... 408
Synchronous Reception (Master Mode, SREN) ....... 313
Synchronous Transmission....................................... 310
Synchronous Transmission (Through TXEN) ........... 310
Timer0 and Timer1 External Clock ........................... 401
Timer1 Incrementing Edge........................................ 195
Two Speed Start-up.................................................... 69
Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 345
Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 347
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 406
Requirements, Synchronous Transmission...... 406
Timing Diagram, Synchronous Receive ........... 406
Timing Diagram, Synchronous Transmission... 405
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break............................................................ 306
Wake-up Using Interrupts................................................. 102
Watchdog Timer (WDT)...................................................... 78
Modes....................................................................... 104
Specifications ........................................................... 401
WCOL....................................................... 267, 270, 272, 274
WCOL Status Flag.................................... 267, 270, 272, 274
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 433
PIC16F/LF1946/47
WDTCON Register............................................................105
WPUB Register.................................................................128
WPUG Register.................................................................144
Write Protection...................................................................57
WWW Address..................................................................435
WWW, On-Line Support........................................................7
DS41414A-page 434
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 435
PIC16F/LF1946/47
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC16F/LF1946/47
DS41414A
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41414A-page 436
Preliminary
2010 Microchip Technology Inc.
PIC16F/LF1946/47
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
PIC16LF1946 - I/P = Industrial temp., Plastic
DIP package, low-voltage VDD limits.
PIC16F1947 - I/PT = Industrial temp., TQFP
package, standard VDD limits.
Device:
PIC16F1946, PIC16LF1946, PIC16F1946T, PIC16LF1946T(1)
PIC16F1947, PIC16LF1947, PIC16F1947T, PIC16LF1947T(1)
Temperature
Range:
I
E
=
=
-40C to +85C
-40C to +125C
Package:
Pattern:
MR
PT
=
=
Micro Lead Frame (QFN)
TQFP (Thin Quad Flatpack)
3-Digit Pattern Code for QTP (blank otherwise)
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Low Voltage Range
In tape and reel for QFN and TQFP
packages only.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 437
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
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Corporate Office
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Technical Support:
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Fax: 886-2-2508-0102
Santa Clara
China - Xian
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Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS41414A-page 438
Preliminary
2010 Microchip Technology Inc.
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