PIC16LF720T-E/SS_技术文档

PIC16(L)F720/721

20-Pin Flash Microcontrollers

Devices Included In This Data Sheet:

Low-Power Features:

• Standby Current:

• PIC16F720

• PIC16F721

• PIC16LF720

• PIC16LF721

- 40 nA @ 1.8V, typical

• Low-Power Watchdog Timer Current:

- 500 nA @ 1.8V, typical

High-Performance RISC CPU:

• Only 35 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 16 MHz oscillator/clock input

- DC – 250 ns instruction cycle

Peripheral Features:

• Up to 17 I/O Pins and 1 Input-only Pin:

- High-current source/sink for direct LED drive

- Interrupt-on-change pins

• Up to 4K x 14 Words of Flash Program Memory

• Up to 256 bytes of Data Memory (RAM)

• Interrupt Capability

- Individually programmable weak pull-ups

• A/D Converter:

- 8-bit resolution

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

• Processor Self-Write/Read access to Program

Memory

- 12 channels

- Selectable Voltage reference

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Enhanced Timer1

- 16-bit timer/counter with prescaler

- External Gate Input mode with toggle and

single shot modes

Special Microcontroller Features:

• Precision Internal Oscillator:

- 16 MHz or 500 kHz operation

- Factory calibrated to ±1%, typical

- Software tunable

- Software selectable ÷1, ÷2, ÷4 or ÷8 divider

• Power-Saving Sleep mode

• Industrial and Extended Temperature Range

• Power-on Reset (POR)

• Power-up Timer (PWRT)

- Interrupt-on-gate completion

• Timer2: 8-Bit Timer/Counter with 8-Bit Period

Register, Prescaler and Postscaler

• Capture, Compare, PWM module (CCP)

- 16-bit Capture, max resolution 12.5 ns

- 16-bit Compare, max resolution 250 ns

- 10-bit PWM, max frequency 15 kHz

• Addressable Universal Synchronous

Asynchronous Receiver Transmitter (AUSART)

• Synchronous Serial Port (SSP)

• Brown-out Reset (BOR)

• Multiplexed Master Clear with Pull-up/Input Pin

• Programmable Code Protection

• In-Circuit Serial Programming^TM(ICSP^TM) via Two

Pins

- SPI (Master/Slave)

- I²C^TM(Slave) with Address Mask

• 128 Bytes High-Endurance Flash:

- 100,000 write Flash endurance (minimum)

• Wide Operating Voltage Range:

- 1.8V to 5.5V (PIC16F720/721)

- 1.8V to 3.6V (PIC16LF720/721)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 1

PIC16(L)F720/721

PIC16(L)F72X Family Types

Device

PIC16(L)F707

PIC16(L)F720

PIC16(L)F721

PIC16(L)F722

PIC16(L)F722A

PIC16(L)F723

PIC16(L)F723A

PIC16(L)F724

PIC16(L)F726

PIC16(L)F727

(1)

(2)

(4)

(3)

(4)

(3)

(4)

8192

2048

4096

2048

4096

8192

363

128

256

128

192

368

36 14 32

4/2

2/1

1

2

1

2

I

Y

—

Y

18 12

25 11

—

8

Y

8

Y

8

Y

36 14 16

25 11

36 14 16

Y

8

Y

Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS41418

2: DS41430

3: DS41417

4: DS41341

PIC16(L)F707 Data Sheet, 40/44-Pin Flash, 8-bit Microcontrollers.

PIC16(L)F720/721 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.

PIC16(L)F722A/723A Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.

PIC16(L)F72X Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers.

DS40001430E-page 2

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

Pin Diagrams – 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/721

PDIP, SOIC, SSOP

VDD

RA5/T1CKI/CLKIN

VSS

1

2

20

19

RA0/AN0/ICSPDAT

RA4/AN3/T1G/CLKOUT

RA3/MCLR/VPP

18 RA1/AN1/ICSPCLK

RA2/AN2/T0CKI/INT

3

17

4

16 RC0/AN4

15 RC1/AN5

5

RC5/CCP1

RC4

6

14

13

RC3/AN7

RC6/AN8/SS

7

RC2/AN6

8

RB4/AN10/SDI/SDA

12 RB5/AN11/RX/DT

11 RB6/SCK/SCL

RC7/AN9/SDO

RB7/TX/CK

9

10

Pin Diagrams – 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/721

QFN (4x4)

20 19 18

17 16

RA3/MCLR/VPP 1

RA1/AN1/ICSPCLK

RA2/AN2/T0CKI/INT

RC0/AN4

15

14

13

12

11

2

3

4

5

RC5/CCP1

RC4

PIC16F720/721

PIC16LF720/721

RC3/AN7

RC6/AN8/SS

RC1/AN5

RC2/AN6

9

10

6

7

8

 2010-2013 Microchip Technology Inc.

DS40001430E-page 3

PIC16(L)F720/721

TABLE 1:

20-PIN ALLOCATION TABLE (PIC16F720/721 AND PIC16LF720/721)

RA0

RA1

RA2

RA3

RA4

RA5

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

VDD

Vss

19

18

17

4

16

15

14

1

AN0

AN1

AN2

—

IOC

INT/IOC

IOC

—

Y

ICSPDAT

—

ICSPCLK

T0CKI

—

Y

—

MCLR/VPP

3

20

19

10

9

AN3

—

T1G

T1CKI

—

Y

CLKOUT

CLKIN

—

2

—

Y

13

12

11

10

16

15

14

7

AN10

AN11

—

SDI/SDA

Y

—

RX/DT

—

SCK/SCL

—

Y

—

8

—

Y

—

7

—

TX/CK

—

Y

—

13

12

11

4

AN4

AN5

AN6

AN7

—

6

3

—

5

2

—

CCP1

—

8

5

AN8

AN9

—

SS

—

9

6

—

SDO

—

1

18

17

—

VDD

VSS

20

—

DS40001430E-page 4

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

Table of Contents

1.0 Device Overview ......................................................................................................................................................................... 7

2.0 Memory Organization................................................................................................................................................................ 11

3.0 Resets ....................................................................................................................................................................................... 25

4.0 Interrupts ................................................................................................................................................................................... 35

5.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 43

6.0 I/O Ports .................................................................................................................................................................................... 45

7.0 Oscillator Module....................................................................................................................................................................... 65

8.0 Device Configuration................................................................................................................................................................. 71

9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 75

10.0 Fixed Voltage Reference........................................................................................................................................................... 85

11.0 Temperature Indicator Module ................................................................................................................................................... 87

12.0 Timer0 Module .......................................................................................................................................................................... 89

13.0 Timer1 Module with Gate Control.............................................................................................................................................. 93

14.0 Timer2 Module ........................................................................................................................................................................ 105

15.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................. 107

16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .......................................................... 117

17.0 SSP Module Overview ............................................................................................................................................................ 137

18.0 Flash Program Memory Self Read/Self Write Control............................................................................................................. 159

19.0 Power-Down Mode (Sleep) ..................................................................................................................................................... 167

20.0 In-Circuit Serial Programming™ (ICSP™) .............................................................................................................................. 169

21.0 Instruction Set Summary......................................................................................................................................................... 171

22.0 Development Support.............................................................................................................................................................. 181

23.0 Electrical Specifications........................................................................................................................................................... 185

24.0 DC and AC Characteristics Graphs and Charts...................................................................................................................... 211

25.0 Packaging Information............................................................................................................................................................. 231

Appendix A: Data Sheet Revision History......................................................................................................................................... 241

®

Appendix B: Migrating From Other PIC Devices............................................................................................................................. 241

The Microchip Web Site.................................................................................................................................................................... 249

Customer Change Notification Service ............................................................................................................................................. 249

Customer Support ............................................................................................................................................................................. 249

Reader Response............................................................................................................................................................................. 250

Product Identification System ............................................................................................................................................................ 251

 2010-2013 Microchip Technology Inc.

DS40001430E-page 5

PIC16(L)F720/721

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS40001430E-page 6

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

1.0

DEVICE OVERVIEW

The PIC16(L)F720/721 devices are covered by this

data sheet. They are available in 20-pin packages.

Figure 1-1 shows

a

block diagram of the

PIC16(L)F720/721 devices. Table 1-1 shows the pinout

descriptions.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 7

PIC16(L)F720/721

FIGURE 1-1:

20-PIN DEVICE BLOCK DIAGRAM FOR PIC16F720/721

PORTA

Configuration

RA0

RA1

RA2

RA3

RA4

RA5

13

8

Data Bus

Program Counter

Flash

Program

8K x 14

Memory⁽¹⁾

RAM

File

Program

8 Level Stack

(13-bit)

Memory

Registers⁽¹⁾

Registers

368 x 8

Program

Bus

PORTB

14

RAM Addr

9

Addr MUX

IInnssttrruuccttiioonnRreegg

RB4

RB5

RB6

RB7

Indirect

Addr

7

Direct Addr

8

FFSSRRRreegg

SSTTAATTUUSSRreegg

PORTC

8

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

3

MUX

Power-up

Timer

Instruction

Decode &

Control

Power-on

Reset

ALU

CLKIN

CLKOUT

Watchdog

Timer

8

Timing

Generation

Brown-out

Reset

WWRreegg

LDO

Regulator

PMDATL

Internal

Oscillator

Block

Self read/

write Flash

memory

MCLR VDD

VSS

PMADRL

CCP1

SCK/

/

SDI

ICSPDAT

ICSPCLK

RX/DT

TX/CK

SDO

SCL SS

SDA

T0CKI

T1G

T1CKI

AUSART

Synchronous

Serial Port

AICUSPA™RT

Timer0

Timer2

Timer1

Analog-To-Digital Converter

AN0 AN1 AN2 AN3 AN4

AN7

AN5 AN6

AN8 AN9 AN11

AN10

Note:

PIC16(L)F720 – 2k x 14 Flash, 128 x 8 RAM

PIC16(L)F721 – 4k x 14 Flash, 256 x 8 RAM.

DS40001430E-page 8

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TABLE 1-1:

Name

PINOUT DESCRIPTION

IN

OUT

Function

Description

RA0/AN0/ICSPDAT/ICDDAT

RA1/AN1/ICSPCLK/ICDCLK

RA2/AN2/T0CKI/INT

General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up.

RA0

TTL

CMOS

—

AN0

AN

ST

A/D Channel 0 Input.

ICSPDAT

CMOS ICSP™ Data I/O.

General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up.

RA1

TTL

CMOS

AN1

AN

ST

—

A/D Channel 1 Input.

ICSPCLK

RA2

ICSP™ Clock.

General purpose I/O with IOC and WPU.

TTL

AN

ST

CMOS

—

AN2

A/D Channel 2 Input.

T0CKI

INT

—

Timer0 Clock Input.

ST

—

External interrupt.

RA3

TTL

—

General purpose input-only with IOC and WPU.

RA3/MCLR/VPP

MCLR

VPP

ST

HV

TTL

AN

ST

—

Master Clear with internal pull-up.

Programming Voltage.

RA4

AN3

CMOS General purpose I/O with IOC and WPU.

RA4/AN3/T1G/CLKOUT

—

A/D Channel 3 Input.

Timer1 Gate Input.

T1G

CLKOUT

RA5

T1CKI

CLKIN

RB4

AN10

SDI

—

TTL

ST

CMOS FOSC/4 output.

RA5/T1CKI/CLKIN

RB4/AN10/SDI/SDA

CMOS General purpose I/O with IOC and WPU.

—

Timer1 Clock input.

ST

External Clock Input (EC mode).

TTL

AN

ST

CMOS General purpose I/O with IOC and WPU.

—

A/D Channel 10 Input.

SPI Data Input.

2

SDA

RB5

AN11

RX

I C

OD

I C™ Data.

RB5/AN11/RX/DT

TTL

AN

ST

CMOS General purpose I/O with IOC and WPU.

—

A/D Channel 11 Input.

USART asynchronous input.

DT

ST

CMOS USART synchronous data.

RB6/SCK/SCL

RB7/TX/CK

RB6

SCK

SCL

RB7

TX

TTL

ST

CMOS General purpose I/O with IOC and WPU.

CMOS SPI Clock.

2

I C

OD

I C™ Clock.

TTL

—

CMOS General purpose I/O with IOC and WPU.

CMOS USART asynchronous transmit.

CMOS USART synchronous clock.

CMOS General purpose I/O.

CK

ST

AN

ST

AN

ST

AN

ST

AN

RC0/AN4

RC1/AN5

RC2/AN6

RC3/AN7

RC0

AN4

RC1

AN5

RC2

AN6

RC3

AN7

—

A/D Channel 4 Input.

CMOS General purpose I/O.

A/D Channel 5 Input.

CMOS General purpose I/O.

A/D Channel 6 Input.

CMOS General purpose I/O.

A/D Channel 7 Input.

—

Legend:

AN = Analog input or output, CMOS = CMOS compatible input or output, OD = Open Drain, TTL = TTL compatible

input, ST = Schmitt Trigger input with CMOS levels, I C™ = Schmitt Trigger input with I C, HV = High Voltage,

XTAL = Crystal levels

2

 2010-2013 Microchip Technology Inc.

DS40001430E-page 9

PIC16(L)F720/721

TABLE 1-1:

Name

PINOUT DESCRIPTION (CONTINUED)

IN

OUT

Function

Description

RC4

RC5

CCP1

RC6

AN8

ST

AN

CMOS General purpose I/O.

RC5/CCP1

CMOS Capture/Compare/PWM 1.

CMOS General purpose I/O.

RC6/AN8/SS

—

A/D Channel 8 Input.

Slave Select input.

SS

ST

RC7/AN9/SDO

RC7

AN9

SDO

VDD

Vss

CMOS General purpose I/O.

A/D Channel 9 Input.

CMOS SPI Data Output.

AN

—

VDD

Vss

Power

—

Positive supply.

Ground supply.

Legend:

AN = Analog input or output, CMOS = CMOS compatible input or output, OD = Open Drain, TTL = TTL compatible

input, ST = Schmitt Trigger input with CMOS levels, I C™ = Schmitt Trigger input with I C, HV = High Voltage,

XTAL = Crystal levels

2

DS40001430E-page 10

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

2.0

2.1

MEMORY ORGANIZATION

Program Memory Organization

The PIC16(L)F720/721 has a 13-bit program counter

capable of addressing a 8K x 14 program memory

space. Table 2-1 shows the memory sizes

implemented. Accessing a location above these

boundaries will cause a wrap-around within the

implemented memory space. The Reset vector is at

0000h and the interrupt vector is at 0004h.

TABLE 2-1:

Device

DEVICE SIZE AND ADDRESSES

Program Memory Size

(Words)

Last Program Memory

High-Endurance Flash

Address

Memory Address Range⁽¹⁾

PIC16F720

PIC16LF720

2048

4096

07FFh

0780h-07FFh

0F80h-0FFFh

PIC16F721

PIC16LF721

0FFFh

Note 1: High-Endurance Flash applies to the low byte of each address in the range.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16(L)F720

FIGURE 2-2:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16(L)F721

PC<12:0>

CALL, RETURN

RETFIE, RETLW

CALL, RETURN

RETFIE, RETLW

13

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

Stack Level 8

Reset Vector

0000h

Interrupt Vector

Page 0

Interrupt Vector

Page 0

0004H

0005h

0004H

0005h

On-chip

Program

Memory

On-chip

Program

Memory

07FFh

0800h

07FFh

0800h

Page 1

Wraps to Page 0

0FFFh

1000h

0FFFh

1000h

Wraps to Page 0

17FFh

1800h

17FFh

1800h

Wraps to Page 1

1FFFh

 2010-2013 Microchip Technology Inc.

DS40001430E-page 11

PIC16(L)F720/721

2.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPRs)

and the Special Function Registers (SFRs). Bits RP0

and RP1 are bank select bits.

RP1

0

RP0

0



Bank 0 is selected

Bank 1 is selected

Bank 2 is selected

Bank 3 is selected

0

1

0

1

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function

Registers are the General Purpose Registers,

implemented as static RAM. All implemented banks

contain Special Function Registers. Some frequently

used Special Function Registers from one bank are

mirrored in another bank for code reduction and

quicker access.

DS40001430E-page 12

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file is organized as 128 x 8 bits in the

PIC16(L)F720, 256 x 8 bits in the PIC16(L)F721. Each

register is accessed either directly or indirectly through

the File Select Register (FSR), (Refer to Section 2.5

“Indirect Addressing, INDF and FSR Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (refer to Table 2-2).

These registers are static RAM.

The Special Function Registers can be classified into

two sets: core and peripheral. The Special Function

Registers associated with the “core” are described in

this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 13

PIC16(L)F720/721

FIGURE 2-3:

PIC16(L)F720 SPECIAL FUNCTION REGISTERS

File Address

180h

INDF^(*)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

INDF^(*)

80h

OPTION_REG 81h

INDF^(*)

TMR0

PCL

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

INDF^(*)

TMR0

PCL

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

PCL

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

STATUS

FSR

STATUS

FSR

STATUS

FSR

ANSELA

ANSELB

ANSELC

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

PMDATL

PMADRL

PMDATH

PMADRH

PCLATH

INTCON

PMCON1

PMCON2

TMR1L

TMR1H

T1CON

PCON

T1GCON

OSCCON

OSCTUNE

PR2

TMR2

T2CON

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

SSPADD/SSPMSK 93h

SSPSTAT

WPUA

IOCA

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

WPUB

IOCB

TXSTA

TXREG

RCREG

SPBRG

FVRCON

ADCON1

ADRES

ADCON0

General

Purpose

Register

32 Bytes

General

Purpose

Register

80 Bytes

BFh

C0h

EFh

F0h

06Fh

070h

16Fh

170h

1EFh

1F0h

Accesses

70h – 7Fh

Accesses

70h – 7Fh

Accesses

70h – 7Fh

Access RAM

BANK 0

7Fh

FFh

17Fh

1FFh

BANK 1

BANK 2

BANK 3

Legend:

= Unimplemented data memory locations, read as ‘0’.

*

= Not a physical register.

DS40001430E-page 14

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 2-4:

PIC16(L)F721 SPECIAL FUNCTION REGISTERS

File Address

180h

(*)

INDF

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

INDF

80h

INDF

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

INDF

TMR0

PCL

OPTION_REG 81h

TMR0

PCL

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

PCL

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

STATUS

FSR

STATUS

FSR

STATUS

FSR

ANSELA

ANSELB

ANSELC

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

PMDATL

PMADRL

PMDATH

PMADRH

PCLATH

INTCON

PMCON1

PMCON2

TMR1L

TMR1H

T1CON

PCON

T1GCON

OSCCON

OSCTUNE

PR2

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

SSPADD/SSPMSK 93h

SSPSTAT

WPUA

IOCA

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

WPUB

IOCB

TXSTA

TXREG

RCREG

SPBRG

FVRCON

ADCON1

ADRES

ADCON0

General

Purpose

Register

80 Bytes

General

Purpose

Register

80 Bytes

General

Purpose

Register

80 Bytes

06Fh

070h

EFh

F0h

16Fh

170h

1EFh

1F0h

Accesses

70h – 7Fh

Accesses

70h – 7Fh

Accesses

70h – 7Fh

Access RAM

BANK 0

FFh

17Fh

1FFh

7Fh

BANK 1

BANK 2

BANK 3

Legend:

= Unimplemented data memory locations, read as ‘0’.

*

= Not a physical register.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 15

PIC16(L)F720/721

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0

00h⁽2⁾

01h

02h⁽2⁾

03h⁽2⁾

04h⁽2⁾

05h

INDF

TMR0

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module Register

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

--xx xxxx --xx xxxx

xxxx ---- uuuu ----

xxxx xxxx uuuu uuuu

PCL

Program Counter (PC) Least Significant Byte

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

PORTA

PORTB

PORTC

—

RA5

RB5

RC5

RA4

RB4

RC4

RA3

—

RA2

—

RA1

—

RA0

—

06h

RB7

RC7

RB6

RC6

07h

RC3

RC2

RC1

RC0

08h

Unimplemented

—

09h

—

0Ah⁽1^),(2⁾PCLATH

—

GIE

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

0000 000x 0000 000x

0000 0000 0000 0000

0Bh⁽2⁾

0Ch

0Dh

0Eh

0Fh

10h

11h

INTCON

PIR1

PEIE

ADIF

TMR0IE

RCIF

INTE

TXIF

RABIE

SSPIF

TMR0IF

CCP1IF

INTF

RABIF

TMR1GIF

TMR2IF

TMR1IF

—

Unimplemented

—

TMR1L

TMR1H

T1CON

TMR2

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

TMR1CS1 TMR1CS0

T1CKPS1

T1CKPS0

Timer2 module Register

TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

—

T1SYNC

—

TMR1ON 0000 -0-0 uuuu -u-u

0000 0000 0000 0000

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

—

TOUTPS3

TOUTPS2

Synchronous Serial Port Receive Buffer/Transmit Register

SSPEN CKP SSPM3 SSPM2

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

WCOL

SSPOV

SSPM1

SSPM0

Capture/Compare/PWM Register Low Byte

Capture/Compare/PWM Register High Byte

—

DC1

B1

CCP1M3

ADDEN

CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

SPEN

RX9

SREN

CREN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

AUSART Transmit Data Register

AUSART Receive Data Register

Unimplemented

—

Unimplemented

—

Unimplemented

ADRES

ADCON0

ADC Result Register

xxxx xxxx uuuu uuuu

--00 0000 --00 0000

—

CHS3

CHS2

CHS1

CHS0

GO/

ADON

DONE

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.

4: This bit is unimplemented and reads as ‘1’.

5: See Register 6-2.

DS40001430E-page 16

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 1

80h⁽2⁾

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx xxxx xxxx

1111 1111 1111 1111

81h

OPTION_

REG

RABPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

82h⁽2⁾

83h⁽2⁾

84h⁽2⁾

85h⁽⁵⁾

86h

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

--11 -111 --11 -111

1111 ---- 1111 ----

1111 1111 1111 1111

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

(4)

TRISA

TRISB

TRISC

—

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

—

TRISA2

—

TRISA1

—

TRISA0

—

TRISB7

TRISC7

TRISB6

TRISC6

—

87h

TRISC3

TRISC2

TRISC1

TRISC0

88h

Unimplemented

—

89h

—

8Ah⁽1^),(2⁾PCLATH

—

GIE

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

0000 000x 0000 000x

0000 0000 0000 0000

8Bh⁽2⁾

INTCON

PIE1

PEIE

ADIE

TMR0IE

RCIE

INTE

TXIE

RABIE

SSPIE

TMR0IF

CCP1IE

INTF

RABIF

8Ch

TMR1GIE

TMR2IE

TMR1IE

8Dh

—

Unimplemented

—

8Eh

PCON

T1GCON

—

POR

BOR

---- --qq ---- --uu

8Fh

TMR1GE

T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS1

T1GSS0 0000 0x00 uuuu uxuu

90h

OSCCON

OSCTUNE

PR2

—

IRCF1

TUN5

IRCF0

TUN4

ICSL

ICSS

—

--10 qq-- --10 qq--

--00 0000 --uu uuuu

1111 1111 1111 1111

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

--11 1111 --11 1111

--00 0000 --00 0000

91h

TUN3

TUN2

TUN1

TUN0

92h

Timer2 module Period Register

ADD<7:0>

93h

93h⁽3⁾

SSPADD

SSPMSK

SSPSTAT

WPUA

IOCA

MSK<7:0>

94h

SMP

—

CKE

—

D/A

P

S

R/W

UA

BF

95h

WPUA5

IOCA5

WPUA4

IOCA4

WPUA3

IOCA3

WPUA2

IOCA2

WPUA1

IOCA1

WPUA0

IOCA0

96h

—

97h

—

Unimplemented

SYNC

—

98h

TXSTA

SPBRG

—

CSRC

BRG7

TX9

TXEN

BRG5

—

BRGH

BRG2

TRMT

BRG1

TX9D

BRG0

0000 -010 0000 -010

0000 0000 0000 0000

99h

BRG6

BRG4

BRG3

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

Unimplemented

TSRNG

—

FVRCON

—

FVRRDY

—

FVREN

ADCS2

TSEN

—

ADFVR1 ADFVR0 q000 --00 q000 --00

Unimplemented

ADCS0

—

ADCON1

ADCS1

—

-000 ---- -000 ----

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.

4: This bit is unimplemented and reads as ‘1’.

5: See Register 6-2.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 17

PIC16(L)F720/721

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 2

100h⁽2⁾

101h

102h⁽2⁾

103h⁽2⁾

104h⁽2⁾

105h

INDF

TMR0

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module Register

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

PCL

STATUS

FSR

—

Program Counter (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

Unimplemented

—

106h

—

Unimplemented

107h

—

Unimplemented

108h

—

Unimplemented

109h

—

Unimplemented

10Ah⁽1^),(2⁾PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

INTE RABIE TMR0IF INTF RABIF

---0 0000 ---0 0000

0000 000x 0000 000x

xxxx xxxx xxxx xxxx

0000 0000 0000 0000

--xx xxxx --xx xxxx

---0 0000 ---0 0000

10Bh⁽2⁾

10Ch

10Dh

10Eh

10Fh

110h

111h

INTCON

GIE

PEIE

TMR0IE

PMDATL

Program Memory Read Data Register Low Byte

Program Memory Read Address Register Low Byte

PMADRL

PMDATH

—

Program Memory Read Data Register High Byte

PMADRH

—

Program Memory Read Address Register High Byte

Unimplemented

—

Unimplemented

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

Legend:

—

Unimplemented

—

Unimplemented

—

Unimplemented

WPUB

IOCB

—

WPUB7

IOCB7

WPUB6

IOCB6

WPUB5

IOCB5

WPUB4

—

1111 ---- 1111 ----

0000 ---- 0000 ----

IOCB4

Unimplemented

—

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.

4: This bit is unimplemented and reads as ‘1’.

5: See Register 6-2.

DS40001430E-page 18

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 3

180h⁽2⁾

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx xxxx xxxx

1111 1111 1111 1111

181h

OPTION_

REG

RABPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

182h⁽2⁾

183h⁽2⁾

184h⁽2⁾

185h

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

---1 -111 ---1 -111

--11 ---- --11 ----

11-- 1111 11-- 1111

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

ANSELA

ANSELB

ANSELC

—

ANSB5

—

ANSA4

ANSB4

—

ANSA2

—

ANSA1

—

ANSA0

—

186h

187h

ANSC7

ANSC6

ANSC3

ANSC2

ANSC1

ANSC0

188h

Unimplemented

Write Buffer for the upper 5 bits of the Program Counter

—

18Ah⁽1^),(2⁾PCLATH

—

---0 0000 ---0 0000

0000 000x 0000 000x

1000 -000 1000 -000

---- ---- ---- ----

18Bh⁽2⁾

18Ch

18Dh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

Legend:

INTCON

GIE

PEIE

CFGS

TMR0IE

LWLO

INTE

RABIE

—

TMR0IF

WREN

INTF

WR

RABIF

RD

(4)

PMCON1

—

FREE

PMCON2

—

Program Memory Control Register 2 (not a physical register)

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.

4: This bit is unimplemented and reads as ‘1’.

5: See Register 6-2.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 19

PIC16(L)F720/721

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u= unchanged).

2.2.2.1

STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 21.0

“Instruction Set Summary”).

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

REGISTER 2-1:

STATUS: STATUS REGISTER

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC⁽¹⁾

R/W-x

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

IRP: Register Bank Select bit (used for indirect addressing)

1= Bank 2, 3 (100h-1FFh)

0= Bank 0, 1 (00h-FFh)

bit 6-5

RP<1:0>: Register Bank Select bits (used for direct addressing)

00= Bank 0 (00h-7Fh)

01= Bank 1 (80h-FFh)

10= Bank 2 (100h-17Fh)

11= Bank 3 (180h-1FFh)

bit 4

bit 3

bit 2

bit 1

bit 0

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

DS40001430E-page 20

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

2.2.2.2

OPTION_REG Register

Note:

To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT

by setting the PSA bit of the

OPTION_REG register to ‘1’. Refer to

The OPTION_REG register, shown in Register 2-2, is

a readable and writable register, which contains

various control bits to configure:

• Software programmable prescaler for the Timer0/

WDT

Section 12.1.3

“Software

Programmable Prescaler”.

• External RA2/INT interrupt

• Timer0

• Weak pull-ups on PORTA or PORTB

REGISTER 2-2:

OPTION_REG: OPTION REGISTER

R/W-1

RABPU

bit 7

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RABPU: PORTA or PORTB Pull-up Enable bit

1= PORTA or PORTB pull-ups are disabled

0= PORTA or PORTB pull-ups are enabled by individual bits in the WPUB register

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

 2010-2013 Microchip Technology Inc.

DS40001430E-page 21

PIC16(L)F720/721

2.2.2.3

PCON Register

The Power Control (PCON) register contains flag bits

(refer to Table 3-4) to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON register also controls the software enable of

the BOR.

The PCON register bits are shown in Register 2-3.

REGISTER 2-3:

PCON: POWER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-q

POR

R/W-q

BOR

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-2

bit 1

Unimplemented: Read as ‘0’

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

DS40001430E-page 22

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

2.3

PCL and PCLATH

Note 1: There are no Status bits to indicate stack

The Program Counter (PC) is 13 bits wide. The low

byte comes from the PCL register, which is a readable

and writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from

PCLATH. On any Reset, the PC is cleared. Figure 2-5

shows the two situations for the loading of the PC. The

upper example in Figure 2-5 shows how the PC is

loaded on a write to PCL (PCLATH<4:0>  PCH).

The lower example in Figure 2-5 shows how the PC is

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

loaded during

(PCLATH<4:3>  PCH).

a

CALL or GOTO instruction

2.4

Program Memory Paging

All devices are capable of addressing a continuous 8K

word block of program memory. The CALL and GOTO

instructions provide only 11 bits of address to allow

branching within any 2K program memory page. When

doing a CALLor GOTOinstruction, the upper two bits of

the address are provided by PCLATH<4:3>. When

doing a CALLor GOTOinstruction, the user must ensure

that the page select bits are programmed so that the

desired program memory page is addressed. If a return

from a CALL instruction (or interrupt) is executed, the

entire 13-bit PC is POPed off the stack. Therefore,

manipulation of the PCLATH<4:3> bits is not required

for the RETURNinstructions (which POPs the address

from the stack).

FIGURE 2-5:

LOADING OF PC IN

DIFFERENT SITUATIONS

PCH

PCL

Instruction with

12

8

7

0

PCL as

Destination

PC

8

PCLATH<4:0>

PCLATH

5

ALU Result

PCH

12 11 10

PC

PCL

8

7

0

GOTO, CALL

Note:

The contents of the PCLATH register are

unchanged after a RETURN or RETFIE

instruction is executed. The user must

rewrite the contents of the PCLATH regis-

ter for any subsequent subroutine calls or

GOTOinstructions.

PCLATH<4:3>

PCLATH

11

2

Opcode<10:0>

2.3.1

COMPUTED GOTO

Example 2-1 shows the calling of a subroutine in

page 1 of the program memory. This example assumes

that PCLATH is saved and restored by the Interrupt

Service Routine (if interrupts are used).

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTOmethod, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556, “Implementing a Table Read”

(DS00556).

EXAMPLE 2-1:

CALL OF A SUBROUTINE

IN PAGE 1 FROM PAGE 0

ORG 500h

PAGESELSUB_P1 ;Select page 1

;(800h-FFFh)

2.3.2

STACK

All devices have an 8-level x 13-bit wide hardware

stack (refer to Figures 2-1 and 2-2). The stack space is

not part of either program or data space and the Stack

Pointer is not readable or writable. The PC is PUSHed

onto the stack when a CALLinstruction is executed or

an interrupt causes a branch. The stack is POPed in

the event of a RETURN, RETLWor a RETFIEinstruction

execution. PCLATH is not affected by a PUSH or POP

operation.

CALL

:

SUB1_P1;Call subroutine in

;page 1 (800h-FFFh)

:

ORG

900h

;page 1 (800h-FFFh)

SUB1_P1

:

;called subroutine

;page 1 (800h-FFFh)

:

RETURN

;return to

;Call subroutine

;in page 0

;(000h-7FFh)

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

 2010-2013 Microchip Technology Inc.

DS40001430E-page 23

PIC16(L)F720/721

EXAMPLE 2-2:

INDIRECT ADDRESSING

2.5

Indirect Addressing, INDF and

FSR Registers

MOVLW 020h ;initialize pointer

MOVWF FSR

BANKISEL 020h

;to RAM

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

CONTINUE

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register

actually accesses data pointed to by the File Select

Register (FSR). Reading INDF itself indirectly will

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit of

the STATUS register, as shown in Figure 2-6.

;yes continue

A simple program to clear RAM location 020h-02Fh

using indirect addressing is shown in Example 2-2.

FIGURE 2-6:

DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

From Opcode

7

RP1 RP0

Bank Select

6

0

File Select Register

0

IRP

Bank Select

180h

Location Select

00h

00

01

10

11

Data

Memory

7Fh

1FFh

Bank 0

Bank 1 Bank 2

Bank 3

Note:

For memory map detail, refer to Figures 2-3 and 2-4.

DS40001430E-page 24

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

Most registers are not affected by a WDT wake-up

since this is viewed as the resumption of normal

operation. TO and PD bits are set or cleared differently

in different Reset situations, as indicated in Table 3-5.

These bits are used in software to determine the nature

of the Reset.

3.0

RESETS

The PIC16(L)F720/721 differentiates between various

kinds of Reset:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during Sleep

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 3-1.

d) MCLR Reset during normal operation

e) MCLR Reset during Sleep

f) Brown-out Reset (BOR)

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 23.0 “Electrical

Specifications” for pulse width specifications.

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset (POR)

• MCLR Reset

• MCLR Reset during Sleep

• WDT Reset

• Brown-out Reset (BOR)

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

MCLRE

MCLR/VPP

Sleep

WDT

Module

Time-out

Reset

POR

Power-on Reset

VDD

Brown-out⁽¹⁾

Reset

BOREN

Chip_Reset

CLKIN

PWRT

11-bit Ripple Counter

WDTOSC

Enable PWRT

Note 1: Refer to the Configuration Word Register 1 (Register 8-1).

 2010-2013 Microchip Technology Inc.

DS40001430E-page 25

PIC16(L)F720/721

TABLE 3-1:

STATUS BITS AND THEIR SIGNIFICANCE

POR

BOR

TO

PD

Condition

0

1

x

0

1

0

x

1

0

u

1

x

0

1

0

u

0

Power-on Reset or LDO Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during Sleep or interrupt wake-up from Sleep

TABLE 3-2:

RESET CONDITION FOR SPECIAL REGISTERS⁽²⁾

Program

STATUS

Register

PCON

Register

Condition

Counter

Power-on Reset

0000h

0001 1xxx

000u uuuu

---- --0x

---- --uu

MCLR Reset during normal operation

0000h

MCLR Reset during Sleep

WDT Reset

0000h

0001 0uuu

0000 1uuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

---- --uu

---- --u0

---- --uu

WDT Wake-up

PC + 1

Brown-out Reset

0000h

PC + 1⁽¹⁾

Interrupt Wake-up from Sleep

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is

pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

DS40001430E-page 26

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

3.1

MCLR

3.3

Power-up Timer (PWRT)

The PIC16(L)F720/721 has a noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

The Power-up Timer provides a fixed 72 ms (nominal)

time out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from the WDT

oscillator. For more information, see Section 7.3

“Internal Clock Modes”. The chip is kept in Reset as

long as PWRT is active. The PWRT delay allows the

VDD to rise to an acceptable level. A Configuration bit,

PWRTE, can disable (if set) or enable (if cleared or pro-

grammed) the Power-up Timer. The Power-up Timer

should be enabled when Brown-out Reset is enabled,

although it is not required.

It should be noted that a Reset does not drive the

MCLR pin low.

Voltages applied to the pin that exceed its specification

can result in both MCLR Resets and excessive current

beyond the device specification during the ESD event.

For this reason, Microchip recommends that the MCLR

pin no longer be tied directly to VDD. The use of an RC

network, as shown in Figure 3-2, is suggested.

The Power-up Timer delay will vary from chip-to-chip

and vary due to:

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

MCLRE = 0, the Reset signal to the chip is generated

internally. When the MCLRE = 1, the RA3/MCLR pin

becomes an external Reset input. In this mode, the

RA3/MCLR pin has a weak pull-up to VDD. In-Circuit

Serial Programming™ is not affected by selecting the

internal MCLR option.

• VDD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 23.0

“Electrical Specifications”).

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word.

FIGURE 3-2:

RECOMMENDED MCLR

CIRCUIT

3.4

Watchdog Timer (WDT)

VDD

R1

PIC^®MCU

The WDT has the following features:

• Shares an 8-bit prescaler with Timer0

10 k

• Time-out period is from 17 ms to 2.2 seconds,

nominal

MCLR

• Enabled by a Configuration bit

C1

0.1 F

WDT is cleared under certain conditions described in

Table 3-3.

3.4.1

WDT OSCILLATOR

The WDT derives its time base from 31 kHz internal

oscillator.

3.2

Power-on Reset (POR)

The on-chip POR circuit holds the chip in Reset until VDD

has reached a high enough level for proper operation. A

maximum rise time for VDD is required. See

Section 23.0 “Electrical Specifications” for details. If

the BOR is enabled, the maximum rise time specification

does not apply. The BOR circuitry will keep the device in

Reset until VDD reaches VBOR (see Section 3.5

“Brown-out Reset (BOR)”).

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

 2010-2013 Microchip Technology Inc.

DS40001430E-page 27

PIC16(L)F720/721

3.4.2

WDT CONTROL

The WDTEN bit is located in the Configuration Word

Register 1. When set, the WDT runs continuously.

The PSA and PS<2:0> bits of the OPTION_REG

register control the WDT period. See Section 12.0

“Timer0 Module” for more information.

FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM

T1GSS = 11

TMR1GE

From TMR0

Clock Source

WDTEN

Low-Power

WDT OSC

0

1

Postscaler

8

Divide by

512

PS<2:0>

TO TMR0

0

1

PSA

WDT Reset

To T1G

WDTEN

TABLE 3-3:

WDT STATUS

Conditions

WDT

Cleared

WDTEN = 0

CLRWDTCommand

Exit Sleep + System Clock = INTOSC, EXTCLK

DS40001430E-page 28

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

3.5

Brown-out Reset (BOR)

Brown-out Reset is enabled by programming the

BOREN<1:0> bits in the Configuration register.

Between the POR and BOR, complete voltage range

coverage for execution protection can be

implemented.

Two bits are used to enable the BOR. When

BOREN = 11, the BOR is always enabled. When

BOREN = 10, the BOR is enabled, but disabled during

Sleep. When BOREN = 0X, the BOR is disabled.

If VDD falls below VBOR for greater than parameter

(TBOR) (see Section 23.0 “Electrical Specifica-

tions”), the Brown-out situation will reset the device.

This will occur regardless of VDD slew rate. A Reset is

not ensured to occur if VDD falls below VBOR for more

than parameter (TBOR).

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

FIGURE 3-4:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

64 ms

VDD

VBOR

Internal

Reset

< 64 ms

(1)

64 ms

VDD

VBOR

Internal

Reset

(1)

64 ms

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 29

PIC16(L)F720/721

3.6

Time-out Sequence

3.7

Power Control (PCON) Register

PWRT time-out is invoked after POR has expired. The

total time-out will vary based on oscillator configuration

and PWRTE bit status. For example, in EC mode with

PWRTE bit = 1(PWRT disabled), there will be no time-

out at all. Figure 3-5, Figure 3-6 and Figure 3-7 depict

time-out sequences.

The Power Control (PCON) register has two Status bits

to indicate what type of Reset that last occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00in the Configuration Word register).

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 3-6). This is useful for testing purposes or

to synchronize more than one PIC16(L)F720/721

device operating in parallel.

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

Table 3-5 shows the Reset conditions for some special

registers.

For more information, see Section 3.5 “Brown-out

Reset (BOR)”.

TABLE 3-4:

TIME-OUT IN VARIOUS SITUATIONS

Power-up

Brown-out Reset

Wake-up from

Oscillator Configuration

Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

EC, INTOSC

TPWRT

—

TPWRT

—

TABLE 3-5:

POR

RESET BITS AND THEIR SIGNIFICANCE

BOR

TO

PD

Condition

0

1

u

0

u

1

0

1

u

0

Power-on Reset

Brown-out Reset

WDT Reset

WDT Wake-up

u

1

u

0

MCLR Reset during normal operation

MCLR Reset during Sleep

Legend: u= unchanged, x= unknown

FIGURE 3-5:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

Internal Reset

DS40001430E-page 30

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 3-6:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

Internal Reset

FIGURE 3-7:

TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

Internal Reset

 2010-2013 Microchip Technology Inc.

DS40001430E-page 31

PIC16(L)F720/721

TABLE 3-6:

Register

INITIALIZATION CONDITION FOR REGISTERS

Power-on Reset/

MCLR Reset/

WDT Reset

Wake-up from Sleep through

Interrupt/Time-out

Address

Brown-out Reset⁽¹⁾

W

—

xxxx xxxx

uuuu uuuu

xxxx xxxx

uuuu uuuu

INDF

00h/80h/

100h/180h

TMR0

PCL

01h/101h

xxxx xxxx

0000 0000

uuuu uuuu

0000 0000

uuuu uuuu

PC + 1⁽³⁾

02h/82h/

102h/182h

STATUS

FSR

03h/83h/

103h/183h

0001 1xxx

xxxx xxxx

000q quuu⁽⁴⁾

uuuu uuuu

uuuq quuu⁽⁴⁾

uuuu uuuu

04h/84h/

104h/184h

PORTA

PORTB

PORTC

PCLATH

05h

06h

07h

--xx xxxx

xxxx ----

xxxx xxxx

---0 0000

--xx xxxx

xxxx ----

xxxx xxxx

---0 0000

--uu uuuu

uuuu ----

uuuu uuuu

---u uuuu

0Ah/8Ah/

10Ah/18Ah

INTCON

0Bh/8Bh/

0000 000x

uuuu uuuu⁽²⁾

10Bh/18Bh

PIR1

0Ch

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Eh

1Fh

0000 0000

xxxx xxxx

0000 -0-0

0000 0000

-000 0000

xxxx xxxx

0000 0000

xxxx xxxx

--00 0000

0000 000x

0000 0000

xxxx xxxx

--00 0000

1111 1111

--11 -111

1111 ----

1111 1111

0000 0000

uuuu uuuu

0000 -0-0

0000 0000

-000 0000

xxxx xxxx

0000 0000

xxxx xxxx

--00 0000

0000 000x

0000 0000

uuuu uuuu

--00 0000

1111 1111

--11 -111

1111 ----

1111 1111

0000 0000

uuuu uuuu⁽²⁾

uuuu uuuu

uuuu -u-u

uuuu uuuu

-uuu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu -uuu

uuuu ----

uuuu uuuu

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

ADRES

ADCON0

OPTION_REG 81h/181h

TRISA

TRISB

TRISC

PIE1

85h

86h

87h

8Ch

Legend: u= unchanged, x= unknown, - = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 3-8 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

DS40001430E-page 32

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TABLE 3-6:

Register

INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Power-on Reset/

MCLR Reset/

WDT Reset

Wake-up from Sleep through

Interrupt/Time-out

Address

Brown-out Reset⁽¹⁾

PCON

8Eh

8Fh

---- --qq

0000 0x00

--10 qq--

--00 0000

1111 1111

0000 0000

1111 1111

0000 0000

1111 ----

--11 1111

0000 ----

--00 0000

0000 -010

0000 0000

q000 --00

-000 ----

xxxx xxxx

0000 0000

--xx xxxx

---0 0000

---1 -111

--11 ----

11-- 1111

1000 -000

---- --uu^(1,5)

uuuu uxuu

--10 qq--

--uu uuuu

1111 1111

0000 0000

1111 1111

0000 0000

1111 ----

--11 1111

0000 ----

--00 0000

0000 -010

0000 0000

q000 --00

-000 ----

xxxx xxxx

0000 0000

--xx xxxx

---0 0000

---1 -111

--11 ----

11-- 1111

1000 -000

---- --uu

uuuu uxuu

--uu qq--

--uu uuuu

uuuu uuuu

uuuu ----

--uu uuuu

uuuu ----

--uu uuuu

uuuu -uuu

uuuu uuuu

uuuu --uu

-uuu ----

uuuu uuuu

--uu uuuu

---u uuuu

---u -uuu

--uu ----

uu-- uuuu

1000 -000

T1GCON

OSCCON

OSCTUNE

PR2

90h

91h

92h

SSPADD

SSPMSK

SSPSTAT

WPUB

93h

94h

115h

95h

WPUA

IOCB

116h

96h

IOCA

TXSTA

98h

SPBRG

FVRCON

ADCON1

PMDATL

PMADRL

PMDATH

PMADRH

ANSELA

ANSELB

ANSELC

PMCON1

99h

9Dh

9Fh

10Ch

10Dh

10Eh

10Fh

185h

186h

187h

18Ch

Legend: u= unchanged, x= unknown, - = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 3-8 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 33

PIC16(L)F720/721

TABLE 3-7:

INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program

Counter

STATUS

Register

PCON

Register

Condition

Power-on Reset

0000h

0001 1xxx

000u uuuu

---- --0x

---- --uu

MCLR Reset during normal operation

MCLR Reset during Sleep

WDT Reset

0000h

0001 0uuu

0000 uuuu

uuu0 0uuu

0001 1xxx

uuu1 0uuu

---- --uu

---- --10

---- --uu

WDT Wake-up

PC + 1

0000h

PC + 1⁽¹⁾

Brown-out Reset

Interrupt Wake-up from Sleep

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the PC is loaded with

the interrupt vector (0004h) after execution of PC + 1.

TABLE 3-8:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register on

Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

STATUS

PCON

IRP

—

RP1

—

RP0

—

TO

—

PD

—

Z

DC

C

20

22

—

POR

BOR

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.

Shaded cells are not used by Resets.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS40001430E-page 34

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

The PIC16(L)F720/721 device family has 11 interrupt

sources, differentiated by corresponding interrupt

enable and flag bits:

4.0

INTERRUPTS

The PIC16(L)F720/721 device family features an

interruptible core, allowing certain events to preempt

normal program flow. An Interrupt Service Routine

(ISR) is used to determine the source of the interrupt

and act accordingly. Some interrupts can be configured

to wake the MCU from Sleep mode.

• Timer0 Overflow Interrupt

• External Edge Detect on INT Pin Interrupt

• Interrupt-on-change, PORTA and PORTB pins

• Timer1 Gate Interrupt

• A/D Conversion Complete Interrupt

• AUSART Receive Interrupt

• AUSART Transmit Interrupt

• SSP Event Interrupt

• CCP1 Event Interrupt

• Timer2 Match with PR2 Interrupt

• Timer1 Overflow Interrupt

A block diagram of the interrupt logic is shown in

Figure 4-1.

FIGURE 4-1:

INTERRUPT LOGIC

SSPIF

SSPIE

IOC-RB4

IOCB4

TXIF

TXIE

IOC-RB5

IOCB5

RCIF

RCIE

(1)

Wake-up (if in Sleep mode)

IOC-RB6

IOCB6

TMR0IF

TMR0IE

TMR2IF

TMR2IE

Interrupt to CPU

IOC-RB7

IOCB7

INTF

INTE

RABIF

TMR1IF

TMR1IE

IOC-RA0

IOCA0

RABIE

ADIF

ADIE

IOC-RA1

IOCA1

IOC-RA2

IOCA2

PEIE

GIE

TMR1GIF

TMR1GIE

IOC-RA3

IOCA3

CCP1IF

CCP1IE

IOC-RA4

IOCA4

IOC-RA5

IOCA5

Note 1: Some peripherals depend upon the

system clock for operation. Since the

system clock is suspended during

Sleep, these peripherals will not wake

the part from Sleep. See Section 19.1

“Wake-up from Sleep”.

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PIC16(L)F720/721

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its Interrupt Flag, but will not cause the

processor to redirect to the interrupt vector.

4.1

Operation

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

• GIE bit of the INTCON register

The RETFIE instruction exits the ISR by popping the

• Interrupt Enable bit(s) for the specific interrupt

event(s)

previous address from the stack and setting the GIE bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIE1 register)

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

The INTCON and PIR1 registers record individual

interrupts via interrupt flag bits. Interrupt flag bits will be

set, regardless of the status of the GIE, PEIE and

individual Interrupt Enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

4.2

Interrupt Latency

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The latency for synchronous

interrupts is three instruction cycles. For asynchronous

interrupts, the latency is three to four instruction cycles,

depending on when the interrupt occurs. See Figure 4-2

for timing details.

• Current Program Counter (PC) is pushed onto the

stack

• PC is loaded with the interrupt vector 0004h

The ISR determines the source of the interrupt by

polling the interrupt flag bits. The interrupt flag bits must

be cleared before exiting the ISR to avoid repeated

FIGURE 4-2:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

(3)

CLKOUT

(4)

INT pin

(1)

(2)

(5)

Interrupt Latency

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 23.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

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PIC16(L)F720/721

following the ISR from using invalid data. Examples of

key registers include the W, STATUS, FSR and

PCLATH registers.

4.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

Note:

The microcontroller does not normally

require saving the PCLATH register.

However, if computed GOTOs are used,

the PCLATH register must be saved at the

beginning of the ISR and restored when

the ISR is complete to ensure correct

program flow.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEPinstruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to the Section 19.0

“Power-Down Mode (Sleep)” for more details.

The code shown in Example 4-1 can be used to do the

following.

• Save the W register

• Save the STATUS register

• Save the PCLATH register

• Execute the ISR program

• Restore the PCLATH register

• Restore the STATUS register

• Restore the W register

4.4

INT Pin

The external interrupt, INT pin, causes an

asynchronous, edge-triggered interrupt. The INTEDG bit

of the OPTION_REG register determines on which edge

the interrupt will occur. When the INTEDG bit is set, the

rising edge will cause the interrupt. When the INTEDG

bit is clear, the falling edge will cause the interrupt. The

INTF bit of the INTCON register will be set when a valid

edge appears on the INT pin. If the GIE and INTE bits

are also set, the processor will redirect program

execution to the interrupt vector. This interrupt is

disabled by clearing the INTE bit of the INTCON register.

Since most instructions modify the W register, it must

be saved immediately upon entering the ISR. The

SWAPF instruction is used when saving and restoring

the W and STATUS registers because it will not affect

any bits in the STATUS register. It is useful to place

W_TEMP in shared memory because the ISR cannot

predict which bank will be selected when the interrupt

occurs.

4.5

Context Saving

The processor will branch to the interrupt vector by

loading the PC with 0004h. The PCLATH register will

remain unchanged. This requires the ISR to ensure

that the PCLATH register is set properly before using

an instruction that causes PCLATH to be loaded into

the PC. See Section 2.3 “PCL and PCLATH” for

details on PC operation.

When an interrupt occurs, only the return PC value is

saved to the stack. If the ISR modifies or uses an

instruction that modifies key registers, their values

must be saved at the beginning of the ISR and restored

when the ISR completes. This prevents instructions

EXAMPLE 4-1:

SAVING W, STATUS AND PCLATH REGISTERS IN RAM

;Copy W to W_TEMP register

MOVWFW_TEMP

SWAPFSTATUS,W

;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

;Select regardless of current bank

;Copy status to bank zero STATUS_TEMP register

;Copy PCLATH to W register

BANKSELSTATUS_TEMP

MOVWFSTATUS_TEMP

MOVF

MOVWF

:

PCLATH,W

PCLATH_TEMP

;Copy W register to PCLATH_TEMP

:(ISR)

:

;Insert user code here

BANKSELSTATUS_TEMP

;Select regardless of current bank

MOVF

PCLATH_TEMP,W ;

MOVWF

PCLATH

;Restore PCLATH

SWAPFSTATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into STATUS register

;Swap W_TEMP

MOVWFSTATUS

SWAPFW_TEMP,F

SWAPFW_TEMP,W

;Swap W_TEMP into W

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PIC16(L)F720/721

4.5.1

INTCON REGISTER

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

The INTCON register is a readable and writable

register, which contains the various enable and flag bits

for TMR0 register overflow, PORTB change and

external RA2/INT pin interrupts.

REGISTER 4-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

GIE

R/W-0

PEIE

R/W-0

INTE

R/W-0

RABIE⁽¹⁾

R/W-0

TMR0IF⁽²⁾

R/W-0

INTF

R/W-x

RABIF

TMR0IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

TMR0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: INT External Interrupt Enable bit

1= Enables the INT external interrupt

0= Disables the INT external interrupt

RABIE: PORTA or PORTB Change Interrupt Enable bit⁽¹⁾

1= Enables the PORTA or PORTB change interrupt

0= Disables the PORTA or PORTB change interrupt

TMR0IF: Timer0 Overflow Interrupt Flag bit⁽²⁾

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INTF: INT External Interrupt Flag bit

1= The INT external interrupt occurred (must be cleared in software)

0= The INT external interrupt did not occur

RABIF: PORTA or PORTB Change Interrupt Flag bit

1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be

cleared in software)

0= None of the PORTA or PORTB general purpose I/O pins have changed state

Note 1: The appropriate bits in the IOCB register must also be set.

2: TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing TMR0IF bit.

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4.5.2

PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as

shown in Register 4-2.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 4-2:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

TMR1GIE

bit 7

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

CCP1IE

TMR2IE

TMR1IE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TMR1GIE: Timer1 Gate Interrupt Enable bit

1= Enable the Timer1 gate acquisition complete interrupt

0= Disable the Timer1 gate acquisition complete interrupt

ADIE: A/D Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit

1= Enables the SSP interrupt

0= Disables the SSP interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

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PIC16(L)F720/721

4.5.3

PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 4-3.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 4-3:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0

TMR1GIF

bit 7

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

RCIF

TXIF

CCP1IF

TMR2IF

TMR1IF

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

TMR1GIF: Timer1 Gate Interrupt Flag bit

1= Timer1 gate is inactive

0= Timer1 gate is active

ADIF: A/D Converter Interrupt Flag bit

1= A/D conversion complete (must be cleared in software)

0= A/D conversion has not completed or has not been started

RCIF: USART Receive Interrupt Flag bit

1= The USART receive buffer is full (cleared by reading RCREG)

0= The USART receive buffer is not full

TXIF: USART Transmit Interrupt Flag bit

1= The USART transmit buffer is empty (cleared by writing to TXREG)

0= The USART transmit buffer is full

SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

1= The Transmission/Reception is complete (must be cleared in software)

0= Waiting to Transmit/Receive

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1

bit 0

TMR2IF: Timer2 to PR2 Interrupt Flag bit

1= A Timer2 to PR2 match occurred (must be cleared in software)

0= No Timer2 to PR2 match occurred

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= The TMR1 register overflowed (must be cleared in software)

0= The TMR1 register did not overflow

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PIC16(L)F720/721

TABLE 4-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

TMR0IE

INTE

RABIE TMR0IF

PSA PS2

INTF

PS1

RABIF

PS0

38

21

39

40

OPTION_REG

PIE1

RABPU

TMR1GIE

TMR1GIF

INTEDG

ADIE

T0CS

RCIE

RCIF

T0SE

TXIE

TXIF

SSPIE CCP1IE TMR2IE TMR1IE

SSPIF CCP1IF TMR2IF TMR1IF

PIR1

ADIF

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the

capture, compare and PWM.

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DS40001430E-page 41

PIC16(L)F720/721

NOTES:

DS40001430E-page 42

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PIC16(L)F720/721

5.0

LOW DROPOUT (LDO)

VOLTAGE REGULATOR

The PIC16F720/721 devices differ from the

PIC16LF720/721 devices due to an internal Low

Dropout (LDO) voltage regulator. The PIC16F720/721

contain an internal LDO, while the PIC16LF720/721 do

not.

The lithography of the die allows a maximum operating

voltage of 3.6V on the internal digital logic. In order to

continue to support 5.0V designs, a LDO voltage

regulator is integrated on the die. The LDO voltage

regulator allows for the internal digital logic to operate

at 3.2V, while I/O’s operate at 5.0V (VDD).

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PIC16(L)F720/721

NOTES:

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PIC16(L)F720/721

6.1.1

WEAK PULL-UPS

6.0

I/O PORTS

Each of the PORTA pins has an individually

configurable internal weak pull-up. Control bits

WPUA<5:0> enable or disable each pull-up (see

Register 6-5). Each weak pull-up is automatically

turned off when the port pin is configured as an output.

All pull-ups are disabled on a Power-on Reset by the

RABPU bit of the OPTION_REG register.

There are as many as eighteen general purpose I/O

pins available. Depending on which peripherals are

enabled, some or all of the pins may not be available as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

6.1

PORTA and TRISA Registers

6.1.2

INTERRUPT-ON-CHANGE

PORTA is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 6-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). Example 6-1 shows how to

initialize PORTA.

All of the PORTA pins are individually configurable as

an interrupt-on-change pin. Control bits IOCA<5:0>

enable or disable the interrupt function for each pin

(see Register 6-6). The interrupt-on-change feature is

disabled on a Power-on Reset.

For enable interrupt-on-change pins, the present value

is compared with the old value latched on the last read

of PORTA to determine which bits have changed or

mismatched the old value. The ‘mismatch’ outputs of

the last read are OR’d together to set the PORTA

Change Interrupt Flag bit (RABIF) in the INTCON

register. This interrupt can wake the device from Sleep.

The user, in the Interrupt Service Routine, clears the

interrupt by:

Reading the PORTA register (Register 6-1) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch.

1. Any read or write of PORTA. This will end the

mismatch condition.

The TRISA register (Register 6-2) controls the PORTA

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISA register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

2. Clear the flag bit RABIF.

A mismatch condition will continue to set flag bit RABIF.

Reading or writing PORTA will end the mismatch

condition and allow flag bit RABIF to be cleared. The

latch holding the last read value is not affected by a

MCLR or Brown-out Reset. After these Resets, the

RABIF flag will continue to be set if a mismatch is

present.

Note:

The ANSELA register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs

will read ‘0’.

Note:

When a pin change occurs at the same

time as a read operation on PORTA, the

RABIF flag will always be set. If multiple

PORTA pins are configured for the inter-

rupt-on-change, the user may not be able

to identify which pin changed state.

EXAMPLE 6-1:

INITIALIZING PORTA

BANKSELPORTA

;

CLRF

BANKSELANSELA

CLRF ANSELA

BANKSELTRISA

PORTA

;Init PORTA

;

;digital I/O

;

MOVLW

MOVWF

0Ch

TRISA

;Set RA<3:2> as inputs

;and set RA<5:4,1:0>

;as outputs

 2010-2013 Microchip Technology Inc.

DS40001430E-page 45

PIC16(L)F720/721

REGISTER 6-1:

PORTA: PORTA REGISTER

U-0

—

U-0

—

R/W-x/u

RA5

R/W-x/u

RA4

R/W-x/u

RA2

R/W-x/u

RA1

R/W-x/u

RA0

(1)

RA3

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RA<5:0>: PORTA I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: RA<3> is input only.

REGISTER 6-2:

TRISA: PORTA TRI-STATE REGISTER

U-0

—

U-0

—

R/W-1

U-1

R/W-1

(1)

TRISA5

TRISA4

—

TRISA2

TRISA1

TRISA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

TRISA<5:4>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

bit 3

Unimplemented: Read as ‘1’

bit 2-0

TRISA<2:0>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

Note 1: TRISA<3> is unimplemented and read as 1.

REGISTER 6-3:

WPUA: WEAK PULL-UP PORTA REGISTER

U-0

R/W-1

(2)

—

WPUA5

WPUA4

WPUA2

WPUA1

WPUA0

WPUA3

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

WPUA<5:0>: Weak Pull-up PORTA Control bits

(1)

1= Weak pull-up enabled

0= Weak pull-up disabled

Note 1: Enabling weak pull-ups also requires that the RABPU bit of the OPTION_REG register be cleared.

2: If MCLREN = 1, WPUA3 is always enabled.

DS40001430E-page 46

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PIC16(L)F720/721

REGISTER 6-4:

IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER

U-0

—

U-0

—

R/W-0

IOCA5

R/W-0

IOCA4

R/W-0

IOCA3

R/W-0

IOCA2

R/W-0

IOCA1

R/W-0

IOCA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOCA<5:0>: Interrupt-on-Change PORTA Control bits

(1)

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

Note 1: Interrupt-on-change also requires that the RABIE bit of the INTCON register be set.

6.1.3

ANSELA REGISTER

The ANSELA register (Register 6-5) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELA bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

REGISTER 6-5:

ANSELA: PORTA ANALOG SELECT REGISTER

U-0

—

U-0

—

U-0

—

R/W-1

U-0

—

R/W-1

ANSA4

ANSA2

ANSA1

ANSA0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4

Unimplemented: Read as ‘0’

ANSA4: Analog Select between Analog or Digital Function on Pin RA<4>

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer is disabled.

bit 3

Unimplemented: Read as ‘0’

bit 2-0

ANSA<2:0>: Analog Select between Analog or Digital Function on Pins RA<2:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer is disabled.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if

available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to

allow external control of the voltage on the pin.

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DS40001430E-page 47

PIC16(L)F720/721

6.1.4

PIN DESCRIPTIONS AND

DIAGRAMS

6.1.4.3

RA2/AN2/T0CKI/INT

Figure 6-3 shows the diagram for this pin. This pin is

configurable to function as one of the following:

Each PORTA pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the A/D Converter (ADC), refer to the

appropriate section in this data sheet.

• General purpose I/O

• Analog input for the ADC

• External interrupt

• Clock input for Timer0

6.1.4.1

RA0/AN0/ICSPDAT

The Timer0 clock input function works independently of

any TRIS register setting. Effectively, if TRISA2 = 0,

the PORTA2 register bit will output to the pad and Clock

Timer0 at the same time.

Figure 6-1 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• General purpose I/O

• Analog input for the ADC

6.1.4.4

RA3/MCLR/VPP

• ICSP programming data (separate controls from

TRISA)

Figure 6-4 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• ICD Debugging data (separate controls from

TRISA)

• General purpose I/O

• Master Clear Reset with weak pull-up

6.1.4.2

RA1/AN1/ICSPCLK

6.1.4.5

RA4/AN3/T1G/CLKOUT

Figure 6-2 shows the diagram for this pin. This pin is

configurable to function as one of the following:

Figure 6-5 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• General purpose I/O

• Analog input for the ADC

• Timer1 gate input

• Clock output

• Analog input for the ADC

• ICSP programming clock (separate controls from

TRISA)

• ICD Debugging clock (separate controls from

TRISA)

6.1.4.6

RA5/T1CKI/CLKIN

Figure 6-6 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• General purpose I/O

• Timer1 Clock input

• Clock input

DS40001430E-page 48

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 6-1:

BLOCK DIAGRAM OF RA0

ICSP™ mode

DEBUG

Analog⁽¹⁾

Input mode

VDD

Data Bus

Weak

D

Q

CK

WR

WPUA

RABPU

RD

WPUA

VDD

PORT_ICDDAT

10

D

Q

0

I/O Pin

WR

CK

PORTA

VSS

0

1

TRIS_ICDDAT

D

Q

WR

TRISA

CK

RD

TRISA

Analog⁽¹⁾

Input mode

RD

PORTA

D

Q

CK

WR

IOCA

Q

D

RD

IOCA

Q3

EN

D

EN

Interrupt-on-Change

RD PORTA

ICSPDAT

To A/D Converter

Note 1: ANSEL determines Analog Input mode.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 49

PIC16(L)F720/721

FIGURE 6-2:

BLOCK DIAGRAM OF RA1

ICSP™ mode

DEBUG

Analog⁽¹⁾

Input mode

Data Bus

D

Q

VDD

Weak

CK

WR WPUA

RABPU

RD WPUA

VDD

D

Q

PORT_ICDCLK

CK

WR PORTA

10

0

I/O Pin

D

Q

0

CK

WR TRISA

RD TRISA

VSS

1

Analog⁽¹⁾

Input mode

TRIS_ICDCLK

RD PORTA

WR IOCA

D

Q

D

CK

EN

Q3

RD IOCA

Q

Interrupt-on-Change

EN

RD PORTA

To A/D Converter

ICSPCLK

Note 1: ANSEL determines Analog Input mode.

DS40001430E-page 50

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 6-3:

BLOCK DIAGRAM OF RA2

Analog⁽¹⁾

Input mode

Data Bus

D

Q

VDD

Weak

WR

WPUA

CK

To

Voltage Regulator

only)

RABPU

RD

WPUA

(for

PIC16F720/721

VDD

D

Q

WR

PORTA

CK

I/O Pin

D

Q

WR

TRISA

CK

VSS

Analog⁽¹⁾

Input mode

RD

TRISA

RD

PORTA

D

Q

D

CK

WR

IOCA

Q3

EN

RD

IOCA

D

EN

Interrupt-on-

Change

RD PORTA

To Timer0

To INT

To A/D Converter

Note 1: ANSEL determines Analog Input mode.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 51

PIC16(L)F720/721

FIGURE 6-4:

BLOCK DIAGRAM OF RA3

FIGURE 6-5:

BLOCK DIAGRAM OF RA4

VDD

Weak

Analog⁽²⁾

Input mode

MCLRE

CLK

modes

VDD

Data Bus

D

Q

Data Bus

MCLRE

WR

CK

WPUA

Reset

Input

Weak

RD

TRISA

VSS

RABPU

RD

MCLRE

VSS

WPUA

RD

PORTA

D

Q

VDD

CLKOUT

Enable

Q

D

CK

WR

IOCA

FOSC/4

1

0

Q3

EN

D

Q

RD

IOCA

I/O Pin

WR

PORTA

CK

D

CLKOUT

Enable

EN

VSS

Interrupt-on-

Change

D

Q

INTOSC/

RC/EC⁽¹⁾

WR

TRISA

CK

RD PORTA

CLKOUT

Enable

RD

TRISA

Analog

Input mode

RD

PORTA

D

Q

D

CK

WR

IOCA

Q3

EN

RD

IOCA

Q

EN

Interrupt-on-

Change

RD PORTA

To T1G

To A/D Converter

Note 1: With CLKOUT option.

2: ANSEL determines Analog Input mode.

DS40001430E-page 52

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 6-6:

BLOCK DIAGRAM OF RA5

INTOSC

mode

Data Bus

D

VDD

Q

WR

CK

Weak

WPUA

RABPU

RD

WPUA

VDD

D

Q

WR

PORTA

CK

I/O Pin

D

Q

WR

TRISA

CK

VSS

INTOSC

mode

RD

TRISA

RD

PORTA

D

Q

D

CK

WR

IOCA

Q3

EN

RD

IOCA

D

EN

Interrupt-on-

Change

RD PORTA

To TMR1 or CLKIN

TABLE 6-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

—

ANSA4

T0SE

RA4

—

ANSA2

PS2

ANSA1

PS1

ANSA0

PS0

47

21

46

OPTION_REG RABPU INTEDG

T0CS

RA5

PSA

RA3

PORTA

TRISA

RA2

RA1

RA0

—

TRISA5 TRISA4

TRISA2 TRISA1 TRISA0

—

Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by

PORTA.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 53

PIC16(L)F720/721

6.2.1

ANSELB REGISTER

6.2

PORTB and TRISB Registers

The ANSELB register (Register 6-10) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 6-7). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 6-2 shows how to initialize PORTB.

The state of the ANSELB bits has no affect on digital

output functions. A pin with TRIS clear and ANSELB

set will still operate as a digital output, but the Input

mode will be analog. This can cause unexpected

behavior

instructions on the affected port.

when

executing

read-modify-write

Reading the PORTB register (Register 6-6) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch.

6.2.2

WEAK PULL-UPS

Each of the PORTB pins has an individually configurable

internal weak pull-up. Control bits WPUB<7:4> enable or

disable each pull-up (see Register 6-8). Each weak pull-

up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the RABPU bit of the OPTION_REG

register.

The TRISB register (Register 6-7) controls the PORTB

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’. Example 6-2 shows how to initialize PORTB.

6.2.3

INTERRUPT-ON-CHANGE

All of the PORTB pins are individually configurable as an

interrupt-on-change pin. Control bits IOCB<7:4> enable

or disable the interrupt function for each pin. Refer to

Register 6-9. The interrupt-on-change feature is

disabled on a Power-on Reset.

EXAMPLE 6-2:

INITIALIZING PORTB

BANKSELPORTB

;

CLRF

BANKSELANSELB

CLRF ANSELB ;Make RB<7:4> digital

BANKSELTRISB

PORTB

;Init PORTB

;

For enabled interrupt-on-change pins, the present value

is compared with the old value latched on the last read

of PORTB to determine which bits have changed or

mismatched the old value. The ‘mismatch’ outputs of

the last read are OR’d together to set the PORTB

Change Interrupt Flag bit (RABIF) in the INTCON

register.

MOVLW

MOVWF

B’11110000’;Set RB<7:4> as inputs

TRISB

;

Note:

The ANSELB register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs

will read ‘0’.

This interrupt can wake the device from Sleep. The user,

in the Interrupt Service Routine, clears the interrupt by:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear the flag bit RABIF.

A mismatch condition will continue to set flag bit RABIF.

Reading or writing PORTB will end the mismatch

condition and allow flag bit RABIF to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After these Resets, the RABIF flag will

continue to be set if a mismatch is present.

Note:

When a pin change occurs at the same

time as a read operation on PORTB, the

RABIF flag will always be set. If multiple

PORTB pins are configured for the

interrupt-on-change, the user may not be

able to identify which pin changed state.

DS40001430E-page 54

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

REGISTER 6-6:

PORTB: PORTB REGISTER

R/W-x/u

RB7

R/W-x/u

RB6

R/W-x/u

RB5

R/W-x/u

RB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

RB<7:4>: PORTB I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

bit 3-0

Unimplemented: Read as ‘0’

REGISTER 6-7:

TRISB: PORTB TRI-STATE REGISTER

R/W-1

TRISB7

bit 7

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

TRISB6

TRISB5

TRISB4

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

TRISB<7:4>: PORTB Tri-State Control bit

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

Unimplemented: Read as ‘0’

REGISTER 6-8:

WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1

WPUB7

bit 7

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

WPUB6

WPUB5

WPUB4

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

WPUB<7:4>: Weak Pull-up PORTB Control bits

1= Weak pull-up enabled ^(1,2)

0= Weak pull-up disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: Global RABPU bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 55

PIC16(L)F720/721

REGISTER 6-9:

IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER

R/W-0

IOCB7

bit 7

R/W-0

IOCB6

R/W-0

IOCB5

R/W-0

IOCB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

IOCB<7:4>: Interrupt-on-Change PORTB Control bits

1= Interrupt-on-change enabled⁽¹⁾

0= Interrupt-on-change disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: Interrupt-on-change also requires that the RABIE bit of the INTCON register be set.

REGISTER 6-10: ANSELB: PORTB ANALOG SELECT REGISTER

U-0

—

U-0

—

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

ANSB5

ANSB4

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

ANSB<5:4>: Analog Select between Analog or Digital Function on Pins RB<5:4>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

bit 3-0

Unimplemented: Read as ‘0’

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if

available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user, in order to

allow external control of the voltage on the pin.

DS40001430E-page 56

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

6.2.4

PIN DESCRIPTIONS AND

DIAGRAMS

FIGURE 6-7:

BLOCK DIAGRAM OF RB4

Each PORTB pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the SSP, I²C™ or interrupts, refer to the

appropriate section in this data sheet.

Analog⁽¹⁾

Input mode

Data Bus

D

Q

VDD

WR

WPUB

CK

Weak

6.2.4.1

RB4/AN10/SDI/SDA

RABPU

RD

WPUB

Figure 6-7 shows the diagram for this pin. The RB4 pin

is configurable to function as one of the following:

SSPEN

SSP

VDD

• General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up.

D

Q

10

WR

PORTB

CK

• Analog input for the A/D

• Synchronous Serial Port Input (SPI)

• I²C data I/O

01

I/O Pin

D

Q

From

SSP

10

WR

TRISB

CK

6.2.4.2

RB5/AN11/RX/DT

VSS

0

Figure 6-8 shows the diagram for this pin. The RB5 pin

is configurable to function as one of the following:

Analog⁽¹⁾

Input mode

RD

TRISB

• General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up.

RD

PORTB

• Analog input for the A/D

D

Q

• USART asynchronous receive

• USART synchronous receive

Q

D

CK

WR

IOCB

EN

Q3

6.2.4.3

RB6/SCK/SCL

RD

IOCB

D

Figure 6-9 shows the diagram for this pin. The RB6 pin

is configurable to function as one of the following:

ST

EN

Interrupt-on-

Change

• General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up.

• Synchronous Serial Port clock for both SPI and

I²C

RD PORTB

To SSP

To A/D Converter

6.2.4.4

RB7/TX/CK

Figure 6-10 shows the diagram for this pin. The RB7

pin is configurable to function as one of the following:

Note 1:

ANSEL determines Analog Input mode.

• General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up.

• USART asynchronous transmit

• USART synchronous clock

 2010-2013 Microchip Technology Inc.

DS40001430E-page 57

PIC16(L)F720/721

FIGURE 6-8:

BLOCK DIAGRAM OF RB5

FIGURE 6-9:

BLOCK DIAGRAM OF RB6

Analog⁽¹⁾

Input mode

Data Bus

D

Q

Data Bus

D

VDD

Q

VDD

Weak

WR

CK

Weak

WPUB

WR

CK

WPUB

RABPU

RD

RABPU

WPUB

RD

WPUB

SYNC

SPEN

SSPEN

VDD

D

Q

SSP

VDD

Clock

10

WR

PORTB

D

Q

CK

AUSART

DT

10

WR

CK

01

PORTB

I/O Pin

From

SSP

01

D

Q

10

I/O Pin

From

WR

D

Q

CK

AUSART 10

VSS

TRISB

01

WR

TRISB

CK

VSS

0

RD

TRISB

Analog⁽¹⁾

RD

TRISB

Input mode

RD

PORTB

RD

PORTB

D

Q

D

Q

CK

WR

IOCB

Q

D

CK

WR

IOCB

EN

Q3

RD

IOCB

EN

Q3

D

RD

IOCB

ST

Q

EN

ST

Interrupt-on-

Change

EN

Interrupt-on-

Change

RD PORTB

To SSP

RD PORTB

To AUSART RX/DT

To A/D Converter

Note 1:

ANSEL determines Analog Input mode.

DS40001430E-page 58

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 6-10:

BLOCK DIAGRAM OF RB7

Data Bus

D

Q

VDD

WR

WPUB

CK

Weak

Q

RABPU

RD

WPUB

SPEN

TXEN

SYNC

AUSART

CK

10

AUSART

TX

D

Q

0

VDD

WR

PORTB

CK

10

01

I/O Pin

D

Q

WR

‘1’

01

CK

TRISB

VSS

01

RD

TRISB

RD

PORTB

D

Q

D

CK

WR

IOCB

EN

Q3

RD

IOCB

Q

D

EN

Interrupt-on-

Change

RD PORTB

TABLE 6-2:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register on

Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

INTCON

IOCB

—

ANSB5

TMR0IE

IOCB5

ANSB4

INTE

—

INTF

—

RABIF

—

56

38

56

GIE

PEIE

IOCB6

RABIE TMR0IF

IOCB7

IOCB4

—

OPTION_REG RABPU INTEDG

T0CS

RB5

T0SE

RB4

PSA

—

PS2

—

PS1

—

PS0

—

21

55

PORTB

TRISB

WPUB

RB7

RB6

TRISB7 TRISB6 TRISB5 TRISB4

WPUB7 WPUB6 WPUB5 WPUB4

—

Legend: x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by

PORTB.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 59

PIC16(L)F720/721

The TRISC register (Register 6-12) controls the PORTC

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISC register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

6.3

PORTC and TRISC Registers

PORTC is

a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC

(Register 6-12). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISC bit (= 0) will make the corresponding

PORTC pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 6-3 shows how to initialize PORTC.

EXAMPLE 6-3:

INITIALIZING PORTC

BANKSELPORTC

;

CLRF

BANKSELTRISC

PORTC

;Init PORTC

;

Reading the PORTC register (Register 6-11) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch.

MOVLW

MOVWF

B‘00001100’ ;Set RC<3:2> as inputs

TRISC

;and set RC<7:4,1:0>

;as outputs

6.3.1

ANSELC REGISTER

The ANSELC register (Register 6-13) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELC bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELC bits has no effect on digital

output functions. A pin with TRIS clear and ANSELC

set will still operate as a digital output, but the Input

mode will be analog. This can cause unexpected

behavior

when

executing

read-modify-write

instructions on the affected port.

REGISTER 6-11: PORTC: PORTC REGISTER

R/W-x/u

RC7

R/W-x/u

RC6

R/W-x/u

RC5

R/W-x/u

RC4

R/W-x/u

RC3

R/W-x/u

RC2

R/W-x/u

RC1

R/W-x/u

RC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

RC<7:0>: PORTC General Purpose I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

DS40001430E-page 60

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

REGISTER 6-12: TRISC: PORTC TRI-STATE REGISTER

R/W-1

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

REGISTER 6-13: ANSELC: ANALOG SELECT REGISTER FOR PORTC

R/W-1

U-0

—

U-0

—

R/W-1

ANSC7

ANSC6

ANSC3

ANSC2

ANSC1

ANSC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-6

ANSC<7:6>: Analog Select between Analog or Digital Function on Pins RB<7:6>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

ANSC<3:0>: Analog Select between Analog or Digital Function on Pins RC<3:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available,

are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external

control of the voltage on the pin.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 61

PIC16(L)F720/721

6.3.2

RC0/AN4

FIGURE 6-11:

BLOCK DIAGRAM OF RC0

AND RC1

Figure 6-11 shows the diagram for this pin. The RC0 pin

is configurable to function as one of the following:

Data Bus

• General purpose I/O

VDD

• Analog input for the A/D

D

Q

WR

PORTC

CK

6.3.3

RC1/AN5

Q

Figure 6-11 shows the diagram for this pin. The RC1 pin

is configurable to function as one of the following:

I/O Pin

D

Q

• General purpose I/O

WR

TRISC

CK

• Analog input for the A/D

VSS

Analog Input

mode⁽¹⁾

6.3.4

RC2/AN6

RD

TRISC

Figure 6-12 shows the diagram for this pin. The RC2

pin is configurable to function as one of the following:

RD

PORTC

• General purpose I/O

• Analog input for the A/D

To A/D Converter

6.3.5

RC3/AN7

Note 1:

ANSEL determines Analog Input mode.

Figure 6-12 shows the diagram for this pin. The RC3 pin

is configurable to function as one of the following:

• General purpose I/O

• Analog input for the A/D

FIGURE 6-12:

BLOCK DIAGRAM OF RC2

AND RC3

6.3.6

RC4

Figure 6-13 shows the diagram for this pin. The RC4 pin

functions as one of the following:

Data Bus

• General purpose I/O

VDD

D

Q

6.3.7

RC5/CCP1

WR

PORTC

CK

Q

Figure 6-14 shows the diagram for this pin. The RC5 pin

is configurable to function as one of the following:

I/O Pin

D

Q

• General purpose I/O

WR

TRISC

CK

• Capture, Compare or PWM (1 output)

VSS

Analog Input

mode⁽¹⁾

6.3.8

RC6/AN8/SS

RD

TRISC

Figure 6-15 shows the diagram for this pin. The RC6 pin

is configurable to function as one of the following:

RD

PORTC

• General purpose I/O

• Analog input for the A/D

• SS input to SSP

To A/D Converter

6.3.9

RC7/AN9/SDO

Note 1:

ANSEL determines Analog Input mode.

Figure 6-16 shows the diagram for this pin. The RC7 pin

is configurable to function as one of the following:

• General purpose I/O

• Analog input for the A/D

• SDO output of SSP

DS40001430E-page 62

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 6-13:

BLOCK DIAGRAM OF RC4

FIGURE 6-15:

BLOCK DIAGRAM OF RC6

Data Bus

VDD

D

Q

WR

PORTC

CK

I/O Pin

Data Bus

D

Q

I/O Pin

WR

PORTC

CK

VSS

Q

D

Q

WR

TRISC

CK

VSS

Analog Input

D

Q

mode⁽¹⁾

WR

TRISC

CK

RD

TRISC

RD

TRISC

RD

PORTC

To SS Input

RD

PORTC

To A/D Converter

Note 1:

ANSEL determines Analog Input mode.

FIGURE 6-14:

BLOCK DIAGRAM OF RC5

Data bus

CCP1OUT

Enable

VDD

FIGURE 6-16:

BLOCK DIAGRAM OF RC7

D

Q

PORT/SDO

Select

WR

PORTC

CK

10

Q

CCP1OUT

Data Bus

10

SDO

01

I/O Pin

VDD

D

Q

D

Q

01

WR

TRISC

CK

WR

PORTC

CK

VSS

Q

RD

TRISC

I/O Pin

D

Q

WR

TRISC

CK

RD

PORTC

VSS

Analog Input

mode⁽¹⁾

To CCP1 input

RD

TRISC

RD

PORTC

To A/D Converter

Note 1:

ANSEL determines Analog Input mode.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 63

PIC16(L)F720/721

TABLE 6-3:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Registeron

Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELC

ANSC7

TRISC7

RC7

ANSC6

ANSC3 ANSC2 ANSC1 ANSC0

61

—

TRISC

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

RC6 RC5 RC4 RC3 RC2 RC1 RC0

61

60

PORTC

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by

PORTC.

DS40001430E-page 64

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

Clock source modes are configured by the FOSC bits

in Configuration Word 1 (CONFIG1). The oscillator

module can be configured for one of the following

modes of operation.

7.0

7.1

OSCILLATOR MODULE

Overview

The oscillator module has a variety of clock sources and

selection features that allow it to be used in a range of

applications while maximizing performance and

minimizing power consumption. Figure 7-1 illustrates a

block diagram of the oscillator module.

1. EC – CLKOUT function on RA4/CLKOUT pin,

CLKIN on RA5/CLKIN.

2. EC – I/O function on RA4/CLKOUT pin, CLKIN

on RA5/CLKIN.

3. INTOSC – CLKOUT function on RA4/CLKOUT

pin, I/O function on RA5/CLKIN

The system can be configured to use an internal

calibrated high-frequency oscillator as clock source, with

a choice of selectable speeds via software. In addition,

the system can also be configured to use an external

clock source via the CLKIN pin.

4. INTOSCIO – I/O function on RA4/CLKOUT pin,

I/O function on RA5/CLKIN

FIGURE 7-1:

SIMPLIFIED PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

FOSC<1:0>

(Configuration Word 1)

EC

CLKIN

System Clock

(CPU and Peripherals)

Internal Oscillator

IRCF<1:0>

(OSCCON Register)

MFINTOSC

INTOSC

0

1

500 kHz

16 MHz/500 kHz

11

10

01

00

32x

PLL

8 MHz/250 kHz

4 MHz/125 kHz

2 MHz/62.5 kHz

PLLEN

(Configuration Word 1)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 65

PIC16(L)F720/721

7.3.2

FREQUENCY SELECT BITS (IRCF)

7.2

Clock Source Modes

The output of the 500 kHz MFINTOSC and 16 MHz

HFINTOSC, with Phase-Locked Loop enabled, con-

nect to a postscaler and multiplexer (see Figure 7-1).

The Internal Oscillator Frequency Select bits (IRCF) of

the OSCCON register select the frequency output of

the internal oscillator. Depending upon the PLLEN bit,

one of four frequencies of two frequency sets can be

selected via software:

Clock source modes can be classified as external or

internal.

• Internal clock source (INTOSC) is contained

within the oscillator module and derived from a

500 kHz high precision oscillator. The oscillator

module has eight selectable output frequencies,

with a maximum internal frequency of 16 MHz.

• The External Clock mode (EC) relies on an

external signal for the clock source.

If PLLEN = 1, HFINTOSC frequency selection is as

follows:

The system clock can be selected between external or

internal clock sources via the FOSC bits of the

Configuration Word 1.

• 16 MHz

• 8 MHz (default after Reset)

• 4 MHz

• 2 MHz

7.3

Internal Clock Modes

If PLLEN = 0, MFINTOSC frequency selection is as

follows:

The oscillator module has eight output frequencies

derived from a 500 kHz high precision oscillator. The

IRCF bits of the OSCCON register select the

postscaler applied to the clock source dividing the

frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the

Configuration Word 1 locks the internal clock source to

16 MHz before the postscaler is selected by the IRCF

bits. The PLLEN bit must be set or cleared at the time

of programming; therefore, only the upper or low four

clock source frequencies are selectable in software.

• 500 kHz

• 250 kHz (default after Reset)

• 125 kHz

• 62.5 kHz

Note:

Following any Reset, the IRCF<1:0> bits

of the OSCCON register are set to ‘10’ and

the frequency selection is set to 8 MHz or

250 kHz. The user can modify the IRCF

bits to select a different frequency.

The internal oscillator block has one internal oscillator

and a dedicated Phase-Locked Loop that are used to

generate two internal system clock sources: the 16

MHz High-Frequency Internal Oscillator (HFINTOSC)

and the 500 kHz (MFINTOSC). Both can be user-

adjusted via software using the OSCTUNE register

(Register 7-2).

There is no start-up delay before a new frequency

selected in the IRCF bits takes effect. This is because

the old and new frequencies are derived from INTOSC

via the postscaler and multiplexer.

Start-up delay specifications are located in the

Table 23-2

Specifications”.

in

Section 23.0

“Electrical

7.3.1

INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when

the device is programmed using the oscillator selection

or the FOSC<1:0> bits in the CONFIG1 register. See

Section 8.0 “Device Configuration” for more

information.

In INTOSC mode, CLKIN is available for general

purpose I/O. CLKOUT outputs the selected internal

oscillator frequency divided by 4. The CLKOUT signal

may be used to provide a clock for external circuitry,

synchronization, calibration, test or other application

requirements.

In INTOSCIO mode, CLKIN and CLKOUT are available

for general purpose I/O.

DS40001430E-page 66

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

7.4

Oscillator Control

The Oscillator Control (OSCCON) register (Figure 7-1)

displays the status and allows frequency selection of the

internal oscillator (INTOSC) system clock. The

OSCCON register contains the following bits:

• Frequency selection bits (IRCF)

• Status Locked bits (ICSL)

• Status Stable bits (ICSS)

REGISTER 7-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

U-0

—

R/W-1

IRCF1

R/W-0

IRCF0

R-q

U-0

—

U-0

—

ICSL

ICSS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

IRCF<1:0>: Internal Oscillator Frequency Select bits

When PLLEN = 1 (16 MHz HFINTOSC)

11= 16 MHz

10= 8 MHz (default)

01= 4 MHz

00= 2 MHz

When PLLEN = 0 (500 kHz MFINTOSC)

11= 500 kHz

10= 250 kHz (default)

01= 125 kHz

00= 62.5 kHz

bit 3

ICSL: Internal Clock Oscillator Status Locked bit (2% Stable)

1= 16 MHz/500 kHz internal oscillator is in lock

0= 16 MHz/500 kHz internal oscillator has not yet locked

bit 2

ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable)

1= 16 MHz/500 kHz internal oscillator has stabilized to its maximum accuracy

0= 16 MHz/500 kHz internal oscillator has not yet reached its maximum accuracy

bit 1-0

Unimplemented: Read as ‘0’

 2010-2013 Microchip Technology Inc.

DS40001430E-page 67

PIC16(L)F720/721

7.5

Oscillator Tuning

The INTOSC is factory calibrated but can be adjusted

in software by writing to the OSCTUNE register

(Register 7-2).

The default value of the OSCTUNE register is ‘0’. The

value is a 6-bit two’s complement number.

When the OSCTUNE register is modified, the INTOSC

frequency will begin shifting to the new frequency. Code

execution continues during this shift. There is no

indication that the shift has occurred.

REGISTER 7-2:

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

R/W-0

TUN5

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<5:0>: Frequency Tuning bits

01 1111= Maximum frequency

01 1110=

•

00 0001=

00 0000= Oscillator module is running at the factory-calibrated frequency.

11 1111=

•

10 0000= Minimum frequency

DS40001430E-page 68

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

7.6

External Clock Modes

7.6.1

EC MODE

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the CLKIN input and the CLKOUT is

available for general purpose I/O. Figure 7-2 shows the

pin connections for EC mode.

FIGURE 7-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

CLKIN

Clock from

Ext. System

PIC^®MCU

CLKOUT

I/O

TABLE 7-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON

—

IRCF1

TUN5

IRCF0

TUN4

ICSL

ICSS

—

67

68

OSCTUNE

TUN3

TUN2

TUN1

TUN0

Legend: x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by

oscillators.

TABLE 7-2:

SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register

on Page

Name

Bits Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3 Bit 10/2 Bit 9/1

Bit 8/0

13:8

7:0

—

CP

—

MCLRE

—

PLLEN

PWRTE

—

WDTEN

—

BOREN1 BOREN0

CONFIG1

CONFIG2

72

73

FOSC1

—

FOSC0

—

13:8

7:0

—

WRT1

WRT0

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 69

PIC16(L)F720/721

NOTES:

DS40001430E-page 70

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

8.0

DEVICE CONFIGURATION

Device configuration consists of Configuration Word 1

and Configuration Word 2 registers, code protection

and Device ID.

8.1

Configuration Words

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1

register at 2007h and Configuration Word 2 register at

2008h. These registers are only accessible during

programming.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 71

PIC16(L)F720/721

REGISTER 8-1:

CONFIGURATION WORD 1

U-1

—

R/P-1

U-1

—

U-1

—

R/P-1

PLLEN

BOREN1

BOREN0

bit 13

bit 8

U-1

—

R/P-1

CP

R/P-1

U-1

—

R/P-1

MCLRE

PWRTE

WDTEN

FOSC1

FOSC0

bit 7

bit 0

Legend:

P = Programmable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13

bit 12

Unimplemented: Read as ‘1’

PLLEN: INTOSC PLL Enable bit

0= INTOSC frequency is up to 500 kHz (Max. MFINTOSC)

1= INTOSC frequency is up to 16 MHz (Max. HFINTOSC)

bit 11-10

bit 9-8

Unimplemented: Read as ‘1’

BOREN<1:0>: Brown-out Reset Enable bits⁽¹⁾

0x= Brown-out Reset disabled

10= Brown-out Reset enabled during operation and disabled in Sleep

11= Brown-out Reset enabled

bit 7

bit 6

Unimplemented: Read as ‘1’

CP: Flash Program Memory Code Protection bit

0= Program Memory code protection is enabled

1= Program Memory code protection is disabled

bit 5

bit 4

bit 3

MCLRE: MCLR/VPP Pin Function Select bit

1= MCLR/VPP pin function is MCLR; Weak pull-up enabled.

0= MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up disabled

PWRTE: Power-up Timer Enable bit

0= PWRT enabled

1= PWRT disabled

WDTEN: Watchdog Timer Enable bit

0= WDT disabled

1= WDT enabled

bit 2

Unimplemented: Read as ‘1’

bit 1-0

FOSC<1:0>: Oscillator Selection bits

11= EC oscillator: CLKOUT function on CLKOUT pin, and CLKIN function on CLKIN pin

10= EC oscillator: I/O function on CLKOUT pin, and CLKIN function on CLKIN pin

01= INTOSC oscillator: CLKOUT function on CLKOUT pin, and I/O function on CLKIN pin

00= INTOSCIO oscillator: I/O function on CLKOUT pin, and I/O function on CLKIN pin

Note 1: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.

DS40001430E-page 72

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

REGISTER 8-2:

CONFIGURATION WORD 2

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 13

bit 8

U-1

—

U-1

—

U-1

—

Reserved

—

U-1

—

U-1

—

R/P-1

WRT1

WRT0

bit 7

bit 0

Legend:

P = Programmable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 13-5

bit 4

Unimplemented: Read as ‘1’

Reserved: Maintain as ‘1’

Unimplemented: Read as ‘1’

bit 3-2

bit 1-0

WRT<1:0>: Flash Memory Self-Write Protection bits

2 kW Flash memory: PIC16(L)F720:

11= Write protection off

10= 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON1 control

01= 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON1 control

00= 000h to 7FFh write-protected, no addresses may be modified by PMCON1 control

4 kW Flash memory: PIC16(L)F721:

11= Write protection off

10= 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON1 control

01= 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON1 control

00= 000h to FFFh write-protected, no addresses may be modified by PMCON1 control

 2010-2013 Microchip Technology Inc.

DS40001430E-page 73

PIC16(L)F720/721

8.2

Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP™ for verification purposes.

Note:

The entire Flash program memory will be

erased when the code protection is turned

off. See the “PIC16(L)F720/721 Memory

Programming Specification” (DS41409)

for more information.

8.3

User ID

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are read-

able and writable during Program/Verify mode. Only

the Least Significant 7 bits of the ID locations are

reported when using MPLAB^®IDE. See the

“PIC16(L)F720/721 Memory Programming Specifica-

tion” (DS41409) for more information.

DS40001430E-page 74

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

9.0

ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 8-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates

a 8-bit binary result via successive

approximation and stores the conversion result into the

ADC result register (ADRES). Figure 9-1 shows the

block diagram of the ADC.

The ADC voltage reference, FVREF, is an internally

generated supply only.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

FIGURE 9-1:

ADC BLOCK DIAGRAM

VDD

AN0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

ADC

8

GO/DONE

ADRES

ADON

VSS

Temperature Indicator

FVREF

1110

1111

CHS<3:0>

 2010-2013 Microchip Technology Inc.

DS40001430E-page 75

PIC16(L)F720/721

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

9.1

ADC Configuration

When configuring and using the ADC the following

functions must be considered:

9.1.3

CONVERSION CLOCK

• Port configuration

• Channel selection

The source of the conversion clock is software

selectable via the ADCS bits of the ADCON1 register.

There are seven possible clock options:

• ADC conversion clock source

• Interrupt control

• FOSC/2

9.1.1

PORT CONFIGURATION

• FOSC/4

When converting analog signals, the I/O pin selected

as the input channel should be configured for analog by

setting the associated TRIS and ANSEL bits. Refer to

Section 6.0 “I/O Ports” for more information.

• FOSC/8

• FOSC/16

• FOSC/32

• FOSC/64

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input buf-

fer to conduct excess current.

• FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 8-bit conversion requires 10 TAD periods

as shown in Figure 9-2.

9.1.2

CHANNEL SELECTION

For correct conversion, the appropriate TAD

specification must be met. Refer to the A/D conversion

There are 14 channel selections available:

- AN<11:0> pins

requirements

in

Section 23.0

“Electrical

- Temperature Indicator

Specifications” for more information. Table 9-1 gives

examples of appropriate ADC clock selections.

- FVR (Fixed Voltage Reference) Output

Refer to Section 11.0 “Temperature Indicator Mod-

ule” and Section 10.0 “Fixed Voltage Reference” for

more information on these channel selections.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

TABLE 9-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

Device Frequency (FOSC)

ADC Clock Period (TAD)

ADC

Clock Source

ADCS<2:0>

16 MHz

8 MHz

4 MHz

1 MHz

FOSC/2

000

100

001

101

010

110

x11

125 ns⁽²⁾

250 ns⁽²⁾

0.5 s⁽²⁾

1.0 s

250 ns⁽²⁾

500 ns⁽²⁾

1.0 s

500 ns⁽²⁾

1.0 s

2.0 s

4.0 s

8 s⁽⁵⁾

FOSC/4

FOSC/8

FOSC/16

FOSC/32

FOSC/64

FRC

2.0 s

4.0 s

8 s⁽⁵⁾

16.0 s⁽⁵⁾

1.0-6.0 s^(1,4)

16.0 s⁽⁵⁾

32.0 s⁽³⁾

64.0 s⁽³⁾

1.0-6.0 s^(1,4)

2.0 s

4.0 s

8 s⁽⁵⁾

1.0-6.0 s^(1,4)

4.0 s

1.0-6.0 s^(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

5: Recommended values for VDD  2.0V and temperature -40°C to 85°C. The 16.0 s setting should be

avoided for temperature > 85°C.

DS40001430E-page 76

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 9-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY to TAD

TAD0

TAD1

TAD2

b7

TAD3

b6

TAD4

TAD5

b4

TAD6

b3

TAD7

TAD8

TAD9

b5

b2

b1

b0

Conversion Starts

Holding Capacitor is disconnected from Analog Input (typically 100 ns)

Set GO/DONE bit

ADRES register is loaded,

GO/DONE bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

9.1.4

INTERRUPTS

9.2

ADC Operation

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

9.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 9.2.6 “A/D Conversion

Procedure”.

2: The ADC operates during Sleep only

when the FRC oscillator is selected.

9.2.2

COMPLETION OF A CONVERSION

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the GIE and PEIE bits of the INTCON

register must be disabled. If the GIE and PEIE bits of

the INTCON register are enabled, execution will switch

to the Interrupt Service Routine.

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

• Update the ADRES register with new conversion

result

9.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRES register will be updated with the partially com-

plete Analog-to-Digital conversion sample. Incomplete

bits will match the last bit converted.

Please refer to Section 9.1.4 “Interrupts” for more

information.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

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4. Wait the required acquisition time⁽²⁾

.

9.2.4

ADC OPERATION DURING SLEEP

5. Start conversion by setting the GO/DONE bit.

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

6. Wait for ADC conversion to complete by one of

the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 9.3 “A/D Acquisition

Requirements”.

9.2.5

SPECIAL EVENT TRIGGER

The Special Event Trigger of the CCP module allows

periodic ADC measurements without software inter-

vention. When this trigger occurs, the GO/DONE bit is

set by hardware and the Timer1 counter resets to zero.

EXAMPLE 9-1:

A/D CONVERSION

;This code block configures the ADC

;for polling, Vdd reference, Frc clock

;and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

Using the Special Event Trigger does not assure

proper ADC timing. It is the user’s responsibility to

ensure that the ADC timing requirements are met.

Refer to Section 15.0 “Capture/Compare/PWM

(CCP) Module” for more information.

BANKSEL

MOVLW

ADCON1

;

B’01110000’;ADC Frc clock,

;VDD reference

9.2.6

A/D CONVERSION PROCEDURE

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

CALL

ADCON1

TRISA

TRISA,0

ANSELA

ANSELA,0

ADCON0

B’00000001’;AN0, On

ADCON0

SampleTime ;Acquisiton delay

ADCON0,GO ;Start conversion

ADCON0,GO ;Is conversion done?

;

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

;Set RA0 to input

;

;Set RA0 to analog

;

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

register)

;

• Configure pin as analog (Refer to the ANSEL

register)

BSF

BTFSC

GOTO

2. Configure the ADC module:

• Select ADC conversion clock

• Select ADC input channel

• Turn on ADC module

$-1

;No, test again

;

;Read result

;store in GPR space

BANKSEL

MOVF

MOVWF

ADRES

ADRES,W

RESULT

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

DS40001430E-page 78

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9.2.7

ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

REGISTER 9-1:

ADCON0: A/D CONTROL REGISTER 0

U-0

—

U-0

—

R/W-0

CHS3

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-2

Unimplemented: Read as ‘0’

CHS<3:0>: Analog Channel Select bits

0000= AN0

0001= AN1

0010= AN2

0011= AN3

0100= AN4

0101= AN5

0110= AN6

0111= AN7

1000= AN8

1001= AN9

1010= AN10

1011= AN11

1110= Temperature Indicator⁽¹⁾

1111= Fixed Voltage Reference (FVREF)⁽²⁾

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

Note 1: See Section 11.0 “Temperature Indicator Module” for more information.

2: See Section 10.0 “Fixed Voltage Reference” for more information.

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REGISTER 9-2:

ADCON1: A/D CONTROL REGISTER 1

U-0

—

R/W-0

ADCS2

R/W-0

ADCS1

R/W-0

ADCS0

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

011= FRC (clock supplied from a dedicated RC oscillator)

100= FOSC/4

101= FOSC/16

110= FOSC/64

111= FRC (clock supplied from a dedicated RC oscillator)

bit 3-0

Unimplemented: Read as ‘0’

REGISTER 9-3:

R/W-x

ADRES: ADC RESULT REGISTER

R/W-x

ADRES7

bit 7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-0

ADRES<7:0>: ADC Result Register bits

8-bit conversion result.

DS40001430E-page 80

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selected (or changed), an A/D acquisition must be

done before the conversion can be started. To

calculate the minimum acquisition time, Equation 9-1

may be used. This equation assumes that 1/2 LSb error

is used (256 steps for the ADC). The 1/2 LSb error is

the maximum error allowed for the ADC to meet its

specified resolution. It is noted that if the device is

operated at or below 2.0V VDD with the FRC clock

selected for the ADC and if the analog input changes

by more than one or two LSBs from the previous

conversion, then the use of at least 16 s TACQ time is

recommended.

9.3

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 9-3. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 9-3. The maximum recommended

impedance for analog sources is 10 k. As the

source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

EQUATION 9-1:

ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + Temperature - 25°C0.05µs/°C

Note: TCOFF is zero for temperatures below 25 degrees C.

The value for TC can be approximated with the following equations:

1





;[1] VCHOLD charged to within 1/2 lsb

^VAPPLIED^{1 – -------------------------- = VCHOLD}



2^{n + 1} – 1

–TC

---------





RC

VAPPLIED 1 – e

= VCHOLD







;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]



–Tc

--------









RC

1







^{= VAPPLIED}^{1 – --------------------------}

2^{n + 1} – 1

VAPPLIED 1 – e





Note: Where n = number of bits of the ADC.

Solving for TC:

TC = –CHOLDRIC + RSS + RS ln(1/511)

= –20pF1k + 7k + 10k ln(0.001957)

= 2.25µs

Therefore:

TACQ = 2µs + 2.25µs + 50°C- 25°C0.05µs/°C

= 5.5µs

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Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

FIGURE 9-3:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT  0.6V

ANx

SS

RIC  1k

Rss

Rs

(1)

CPIN

5 pF

VA

I LEAKAGE

CHOLD = 20 pF

VSS

VT  0.6V

6V

Legend:

CHOLD

CPIN

= Sample/Hold Capacitance

= Input Capacitance

VDD 4V

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

RIC

RSS

SS

VT

= Interconnect Resistance

= Resistance of Sampling Switch

= Sampling Switch

20

5

10

15

Sampling Switch, Typical

(k)

= Threshold Voltage

Note 1: Refer to Section 23.0 “Electrical Specifications”.

FIGURE 9-4:

ADC TRANSFER FUNCTION

Full-Scale Range

FFh

FEh

FDh

FCh

FBh

1 LSB ideal

Full-Scale

Transition

04h

03h

02h

01h

00h

Analog Input Voltage

1 LSB ideal

Zero-Scale

Transition

VREF

VSS

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TABLE 9-2:

Name

SUMMARY OF ASSOCIATED ADC REGISTERS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

—

CHS3

CHS2

CHS1

CHS0

GO/

ADON

79

DONE

ADCON1

ANSELA

ANSELB

ANSELC

ADRES

FVRCON

INTCON

PIE1

—

ADCS2

—

ADCS1

ANSA5

ANSB5

—

ADCS0

ANSA4

ANSB4

—

80

47

56

61

80

86

38

39

40

46

55

61

ANSA2

—

ANSA1

—

ANSA0

—

ANSC7

ANSC6

ANSC3

ANSC2

ANSC1

ANSC0

ADC Result Register

FVRRDY FVREN

TSEN

TMR0IE

RCIE

TSRNG

INTE

—

RABIE

SSPIE

SSPIF

—

ADFVR1 ADFVR0

INTF RABIF

GIE

TMR1GIE

TMR1GIF

—

PEIE

ADIE

TMR0IF

TXIE

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIR1

ADIF

RCIF

TXIF

TRISA

—

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA2

—

TRISA1

—

TRISA0

—

TRISB

TRISB7

TRISC7

TRISB6

TRISC6

—

TRISC

TRISC3

TRISC2 TRISC1 TRISC0

Legend: x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded

cells are not used for ADC module.

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NOTES:

DS40001430E-page 84

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10.0 FIXED VOLTAGE REFERENCE

This device contains an internal voltage regulator. To

provide a reference for the regulator, a fixed voltage

reference is provided. This fixed voltage is also user

accessible via an A/D converter channel.

User level fixed voltage functions are controlled by the

FVRCON register, which is shown in Register 10-1.

FIGURE 10-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

2

x1

x2

x4

FVR

(To ADC Module)

1.024V Fixed

Reference

+

-

FVREN

FVRRDY

Any peripheral requiring

the Fixed Reference

(See Table 10-1)

TABLE 10-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Peripheral

Conditions

Description

HFINTOSC

FOSC = 1

EC on CLKIN pin.

BOREN<1:0> = 11

BOR always enabled.

BOR

IVR

BOREN<1:0> = 10and BORFS = 1

BOREN<1:0> = 01and BORFS = 1

BOR disabled in Sleep mode, BOR Fast Start enabled.

BOR under software control, BOR Fast Start enabled.

All PIC16F720/721 devices, when

VREGPM1 = 1and not in Sleep

The device runs off of the Power-Save mode regulator when

in Sleep mode.

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REGISTER 10-1: FVRCON: FIXED VOLTAGE REFERENCE REGISTER

R-q

R/W-0

TSEN

R/W-0

U-0

—

U-0

—

R/W-0

FVRRDY

FVREN

TSRNG

ADFVR1

ADFVR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7

bit 6

FVRRDY⁽¹⁾: Fixed Voltage Reference Ready Flag bit

0= Fixed Voltage Reference output is not active or stable

1= Fixed Voltage Reference output is ready for use

FVREN: Fixed Voltage Reference Enable bit

0= Fixed Voltage Reference is disabled

1= Fixed Voltage Reference is enabled

bit 5

bit 4

TSEN: Temperature Indicator Enable bit⁽³⁾

0= Temperature indicator is disabled

1= Temperature indicator is enabled

TSRNG: Temperature Indicator Range Selection bit⁽³⁾

1= VOUT = VDD - 4VT (High Range)

0= VOUT = VDD - 2VT (Low Range)

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bits

00= A/D Converter Fixed Voltage Reference Peripheral output is off

01= A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)

10= A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)⁽²⁾

11= A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)⁽²⁾

Note 1: FVRRDY is always ‘1’ for the PIC16F720/721 devices.

2: Fixed Voltage Reference output cannot exceed VDD.

3: See Section 11.0 “Temperature Indicator Module” for additional information.

TABLE 10-2: SUMMARY OF ASSOCIATED FIXED VOLTAGE REFERENCE REGISTERS

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

86

FVRCON

FVRRDY FVREN

TSEN

TSRNG

—

ADFVR1 ADFVR0

Legend: x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded

cells are not used for Fixed Voltage Reference.

DS40001430E-page 86

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FIGURE 11-1:

TEMPERATURE CIRCUIT

DIAGRAM

11.0 TEMPERATURE INDICATOR

MODULE

This family of devices is equipped with a temperature

circuit designed to measure the operating temperature

of the silicon die. The circuit’s range of operating

temperature falls between -40°C and +85°C. The

output is a voltage that is proportional to the device

temperature. The output of the temperature indicator is

internally connected to the device ADC.

VDD

TSEN

TSRNG

The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,

depending on the level of calibration performed. A one-

point calibration allows the circuit to indicate a

temperature closely surrounding that point. A two-point

calibration allows the circuit to sense the entire range

of temperature more accurately. Reference Application

Note AN1333, “Use and Calibration of the Internal

Temperature Indicator” (DS01333) for more details

regarding the calibration process.

VOUT

To ADC

11.1 Circuit Operation

11.2 Minimum Operating VDD vs.

Minimum Sensing Temperature

Figure 11-1 shows a simplified block diagram of the

temperature circuit. The proportional voltage output is

achieved by measuring the forward voltage drop across

multiple silicon junctions.

When the temperature circuit is operated in low range,

the device may be operated at any operating voltage

that is within specifications.

Equation 11-1 describes the output characteristics of

the temperature indicator.

When the temperature circuit is operated in high range,

the device operating voltage, VDD, must be high

enough to ensure that the temperature circuit is

correctly biased.

EQUATION 11-1: VOUT RANGES

Table 11-1 shows the recommended minimum VDD vs.

range setting.

High Range: VOUT = VDD - 4VT

Low Range: VOUT = VDD - 2VT

TABLE 11-1: RECOMMENDED VDD VS.

RANGE

Min. VDD, TSRNG = 1

Min. VDD, TSRNG = 0

The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See

Section 10.0 “Fixed Voltage Reference” for more

information.

3.6V

1.8V

11.3 Temperature Output

The circuit is enabled by setting the TSEN bit of the

FVRCON register. When disabled, the circuit draws no

current.

The output of the circuit is measured using the internal

Analog-to-Digital Converter. Channel 14 is reserved for

the temperature circuit output. Refer to Section 9.0

“Analog-to-Digital Converter (ADC) Module” for

detailed information.

The circuit operates in either high or low range. The high

range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This

provides more resolution over the temperature range,

but may be less consistent from part to part. This range

requires a higher bias voltage to operate and thus, a

higher VDD is needed.

Note:

Every time the ADC MUX is changed to

the temperature indicator output selection

(CHS bit in the ADCCON0 register), wait

500 usec for the sampling capacitor to

fully charge before sampling the tempera-

ture indicator output.

The low range is selected by clearing the TSRNG bit of

the FVRCON register. The low range generates a lower

voltage drop and thus, a lower bias voltage is needed to

operate the circuit. The low range is provided for low

voltage operation.

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NOTES:

DS40001430E-page 88

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12.1.1

8-BIT TIMER MODE

12.0 TIMER0 MODULE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-Bit Timer mode is

selected by clearing the T0CS bit of the OPTION_REG

register.

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register

can be adjusted, in order to account for

the two instruction cycle delay when

TMR0 is written.

• TMR0 can be used to gate Timer1

Figure 12-1 is a block diagram of the Timer0 module.

12.1.2

8-BIT COUNTER MODE

12.1 Timer0 Operation

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin.

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

8-Bit Counter mode using the T0CKI pin is selected by

setting the T0CS bit in the OPTION_REG register to ‘1’.

The rising or falling transition of the incrementing edge

for either input source is determined by the T0SE bit in

the OPTION_REG register.

FIGURE 12-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

FOSC/4

Data Bus

0

1

8

T0CKI

1

SYNC

TMR0

2 TCY

0

Set Flag bit T0IF

on Overflow

0

1

T0CS

T0SE

8-bit

Prescaler

PSA

Overflow to Timer1

T1GSS = 11

TMR1GE

PSA

8

WDTEN

Low-Power

WDT

PS<2:0>

1

WDT

Time-out

Divide by

512

0

PSA

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12.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

12.1.4

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The TMR0IF

interrupt flag bit of the INTCON register is set every

time the TMR0 register overflows, regardless of

whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The Timer0

interrupt enable is the TMR0IE bit of the INTCON

register.

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the

OPTION_REG register. To assign the prescaler to

Timer0, the PSA bit must be cleared to a ‘0’.

There are eight prescaler options for the Timer0 mod-

ule ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION_REG

register. In order to have a 1:1 prescaler value for the

Timer0 module, the prescaler must be assigned to the

WDT module.

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

12.1.5

8-BIT COUNTER MODE

SYNCHRONIZATION

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing to

the TMR0 register will clear the prescaler.

When in 8-Bit Counter mode, the incrementing edge on

the T0CKI pin must be synchronized to the instruction

clock. Synchronization can be accomplished by

sampling the prescaler output on the Q2 and Q4 cycles

of the instruction clock. The high and low periods of the

external clocking source must meet the timing

requirements as shown in Section 23.0 “Electrical

Specifications”.

Note:

When the prescaler is assigned to WDT, a

CLRWDTinstruction will clear the prescaler

along with the WDT.

DS40001430E-page 90

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12.2 Option Register

REGISTER 12-1: OPTION_REG: OPTION REGISTER

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

RABPU

INTEDG

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RABPU: PORTA or PORTB Pull-up Enable bit

1= PORTA or PORTB pull-ups are disabled

0= PORTA or PORTB pull-ups are enabled by individual PORT latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

T0CS: TMR0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: TMR0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

TMR0IE

INTE

T0SE

RABIE TMR0IF

PSA PS2

INTF

PS1

RABIF

PS0

38

21

89

46

OPTION_REG RABPU INTEDG T0CS

TMR0

Timer0 module Register

TRISA2

TRISA

—

TRISA5 TRISA4

—

TRISA1

TRISA0

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the

Timer0 module.

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NOTES:

DS40001430E-page 92

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• Gate Toggle Mode

13.0 TIMER1 MODULE WITH GATE

CONTROL

• Gate Single-pulse Mode

• Gate Value Status

The Timer1 module is a 16-bit timer/counter with the

following features:

• Gate Event Interrupt

Figure 13-1 is a block diagram of the Timer1 module.

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 3-bit prescaler

• Synchronous or asynchronous operation

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP)

• Selectable Gate Source Polarity

FIGURE 13-1:

TIMER1 BLOCK DIAGRAM

T1GSS<1:0>

T1GSPM

00

T1G

0

01

10

11

From Timer0

Overflow

T1G_IN

D

Data Bus

T1GVAL

Q1

0

1

D

Q

From Timer2

Match PR2

Single Pulse

Acq. Control

RD

T1GCON

1

EN

Q

From WDT

Overflow

Interrupt

det

Set

TMR1GIF

T1GGO/DONE

CK

R

T1GPOL

TMR1GE

TMR1ON

T1GTM

TMR1ON

(2)

TMR1

TMR1H

EN

D

Synchronized

clock input

0

T1CLK

TMR1L

Q

1

Set flag bit

TMR1IF on

Overflow

TMR1CS<1:0>

T1SYNC

(1)

(3)

10

T1CKI

Synchronize

det

Prescaler

1, 2, 4, 8

Reserved

11

00

2

T1CKPS<1:0>

FOSC/4

Internal

Clock

FOSC/2

Internal

Clock

Sleep input

FOSC

Internal

Clock

01

Note 1: ST buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

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13.1 Timer1 Operation

13.2 Clock Source Selection

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

The TMR1CS<1:0> bits of the T1CON register are used

to select the clock source for Timer1. Table 13-2 displays

the clock source selections.

13.2.1

INTERNAL CLOCK SOURCE

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and

increments on every selected edge of the external

source.

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

13.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter. When enabled

to count, Timer1 is incremented on the rising edge of the

external clock input T1CKI.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 13-1 displays the Timer1 enable

selections.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

TABLE 13-1: TIMER1 ENABLE

SELECTIONS

Timer1

Operation

TMR1ON

TMR1GE

•Timer1 enabled after POR Reset

•Write to TMR1H or TMR1L

•Timer1 is disabled

0

1

0

1

0

1

Off

•Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON=1) when T1CKI is

low.

Always On

Count Enabled

TABLE 13-2: CLOCK SOURCE

SELECTIONS

TMR1CS<1:0>

Clock Source

01

00

10

11

System Clock (FOSC)

Instruction Clock (FOSC/4)

External Clocking on T1CKI Pin

Reserved

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13.3 Timer1 Prescaler

13.5 Timer1 Gate

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 gate count

enable.

Timer1 gate can also be driven by multiple selectable

sources.

13.4 Timer1 Operation in

13.5.1

TIMER1 GATE COUNT ENABLE

Asynchronous Counter Mode

The Timer1 gate is enabled by setting the TMR1GE bit

of the T1GCON register. The polarity of the Timer1 gate

is configured using the T1GPOL bit of the T1GCON

register.

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 13.4.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

When Timer1 Gate (T1G) input is active, Timer1 will

increment on the rising edge of the Timer1 clock

source. When Timer1 gate input is inactive, no

incrementing will occur and Timer1 will hold the current

count. See Figure 13-3 for timing details.

TABLE 13-3: TIMER1 GATE ENABLE

SELECTIONS

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

T1CLK T1GPOL

T1G

Timer1 Operation



0

1

0

1

0

1

Counts

Holds Count

Counts

13.4.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

13.5.2

TIMER1 GATE SOURCE

SELECTION

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

The Timer1 gate source can be selected from one of

four different sources. Source selection is controlled by

the T1GSS bits of the T1GCON register. The polarity

for each available source is also selectable. Polarity

selection is controlled by the T1GPOL bit of the

T1GCON register.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

TABLE 13-4: TIMER1 GATE SOURCES

T1GSS

Timer1 Gate Source

Timer1 Gate Pin

00

01

Overflow of Timer0

(TMR0 increments from FFh to 00h)

10

11

Timer2 match PR2

(TMR2 increments to match PR2)

Count Enabled by WDT Overflow

(Watchdog Time-out interval expired)

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13.5.2.1

T1G Pin Gate Operation

13.5.2.4

Watchdog Overflow Gate Operation

The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1

gate circuitry.

The Watchdog Timer oscillator, prescaler and counter

will be automatically turned on when TMR1GE = 1 and

T1GSS selects the WDT as a gate source for Timer1

(T1GSS = 11). TMR1ON does not factor into the oscil-

lator, prescaler and counter enable. See Table 13-5.

13.5.2.2

Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a low-to-

high pulse will automatically be generated and

internally supplied to the Timer1 gate circuitry.

The PSA and PS bits of the OPTION_REG register still

control what time-out interval is selected. Changing the

prescaler during operation may result in a spurious

capture.

13.5.2.3

Timer2 Match Gate Operation

Enabling the Watchdog Timer oscillator does not

automatically enable a Watchdog Reset or Wake-up

from Sleep upon counter overflow.

The TMR2 register will increment until it matches the

value in the PR2 register. On the very next increment

cycle, TMR2 will be reset to 00h. When this Reset

occurs, a low-to-high pulse will automatically be

generated and internally supplied to the Timer1 gate

circuitry.

Note:

When using the WDT as a gate source for

Timer1, operations that clear the Watchdog

Timer (CLRWDT, SLEEP instructions) will

affect the time interval being measured.

This includes waking from Sleep. All other

interrupts that might wake the device from

Sleep should be disabled to prevent them

from disturbing the measurement period.

As the gate signal coming from the WDT counter will

generate different pulse widths depending on if the

WDT is enabled, when the CLRWDT instruction is

executed, and so on, Toggle mode must be used. A

specific sequence is required to put the device into the

correct state to capture the next WDT counter interval.

TABLE 13-5: WDT/TIMER1 GATE INTERACTION

TMR1GE = 1

and

T1GSS = 11

WDT Oscillator

WDT Available for

WDTEN

WDT Reset

Wake-up

Enable

T1G Source

N

Y

N

1

0

Y

N

Y

N

Y

N

Y

N

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13.5.3

TIMER1 GATE TOGGLE MODE

13.5.5

TIMER1 GATE VALUE STATUS

When Timer1 Gate Toggle mode is enabled, it is

possible to measure the full-cycle length of a Timer1

gate signal, as opposed to the duration of a single level

pulse.

When Timer1 gate value status is utilized, it is possible

to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON

register. The T1GVAL bit is valid even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

The Timer1 gate source is routed through a flip-flop that

changes state on every incrementing edge of the

signal. See Figure 13-4 for timing details.

13.5.6

TIMER1 GATE EVENT INTERRUPT

When Timer1 gate event interrupt is enabled, it is

possible to generate an interrupt upon the completion

of a gate event. When the falling edge of T1GVAL

occurs, the TMR1GIF flag bit in the PIR1 register will be

set. If the TMR1GIE bit in the PIE1 register is set, then

an interrupt will be recognized.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

Note:

Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

The TMR1GIF flag bit operates even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

13.5.4

TIMER1 GATE SINGLE-PULSE

MODE

When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the

T1GGO/DONE bit in the T1GCON register must be set.

The Timer1 will be fully enabled on the next

incrementing edge. On the next trailing edge of the

pulse, the T1GGO/DONE bit will automatically be

cleared. No other gate events will be allowed to

increment Timer1 until the T1GGO/DONE bit is once

again set in software.

Clearing the T1GSPM bit of the T1GCON register will

also clear the T1GGO/DONE bit. See Figure 13-5 for

timing details.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1 gate

source to be measured. See Figure 13-6 for timing

details.

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13.6 Timer1 Interrupt

13.8 CCP Capture/Compare Time Base

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

The CCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

register pair is copied into the CCPR1H:CCPR1L

register pair on a configured event.

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

For more information, see Section 15.0 “Capture/

Compare/PWM (CCP) Module”.

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

13.9 CCP Special Event Trigger

When the CCP is configured to trigger a special event,

the trigger will clear the TMR1H:TMR1L register pair.

This special event does not cause a Timer1 interrupt.

The CCP module may still be configured to generate a

CCP interrupt.

13.7 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, the clock

source can be used to increment the counter. To set up

the timer to wake the device:

In this mode of operation, the CCPR1H:CCPR1L

register pair becomes the period register for Timer1.

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

Timer1 should be synchronized to the FOSC/4 to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

• TMR1CS bits of the T1CON register must be

configured

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the CCP, the write will

take precedence.

• TMR1GE bit of the T1GCON register must be

configured

For more information, see Section 9.2.5 “Special

Event Trigger”.

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine (0004h).

FIGURE 13-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

DS40001430E-page 98

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FIGURE 13-3:

TIMER1 GATE COUNT ENABLE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

TIMER1

N

N + 1

N + 2

N + 3

N + 4

FIGURE 13-4:

TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

T1G_IN

T1CKI

T1GVAL

TIMER1

N

N + 1 N + 2 N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

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FIGURE 13-5:

TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

T1G_IN

T1CKI

T1GVAL

TIMER1

N

N + 1

N + 2

Cleared by

software

Set by hardware on

falling edge of T1GVAL

Cleared by software

TMR1GIF

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FIGURE 13-6:

TMR1GE

T1GPOL

TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

T1GSPM

T1GTM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

T1G_IN

T1CKI

T1GVAL

TIMER1

N + 4

N + 2 N + 3

N

N + 1

Set by hardware on

falling edge of T1GVAL

Cleared by

software

Cleared by software

TMR1GIF

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13.10 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

Register 13-1, is used to control Timer1 and select the

various features of the Timer1 module.

REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

U-0

—

R/W-0

U-0

—

R/W-0

TMR1CS1

TMR1CS0

T1CKPS1

T1CKPS0

T1SYNC

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-6

bit 5-4

TMR1CS<1:0>: Timer1 Clock Source Select bits

11= Reserved

10= Timer1 clock source is pin or oscillator. External clock from T1CKI pin (on the rising edge)

01= Timer1 clock source is system clock (FOSC)

00= Timer1 clock source is instruction clock (FOSC/4)

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

Unimplemented: Read as ‘0’

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS<1:0> = 1X

1= Do not synchronize external clock input

0= Synchronize external clock input with system clock (FOSC)

TMR1CS<1:0> = 0X

This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.

bit 1

bit 0

Unimplemented: Read as ‘0’

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Clears Timer1 gate flip-flop

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13.11 Timer1 Gate Control Register

The Timer1 Gate Control register (T1GCON), shown in

Register 13-2, is used to control Timer1 gate.

REGISTER 13-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0

R-x

R/W-0

TMR1GE

T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS1

T1GSS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 counting is controlled by the Timer1 gate function

0= Timer1 counts regardless of Timer1 gate function

bit 6

bit 5

T1GPOL: Timer1 Gate Polarity bit

1= Timer1 gate is active-high (Timer1 counts when gate is high)

0= Timer1 gate is active-low (Timer1 counts when gate is low)

T1GTM: Timer1 Gate Toggle mode bit

1= Timer1 Gate Toggle mode is enabled.

0= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4

bit 3

T1GSPM: Timer1 Gate Single Pulse mode bit

1= Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate

0= Timer1 Gate Single-Pulse mode is disabled

T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1= Timer1 gate single-pulse acquisition is ready, waiting for an edge

0= Timer1 gate single-pulse acquisition has completed or has not been started

This bit is automatically cleared when T1GSPM is cleared.

bit 2

T1GVAL: Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

bit 1-0

T1GSS<1:0>: Timer1 Gate Source Select bits

00= Timer1 gate pin

01= Timer0 overflow output

10= TMR2 match PR2 output

11= Watchdog Timer scaler overflow

Watchdog Timer oscillator is turned on if TMR1GE = 1, regardless of the state of TMR1ON

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TABLE 13-6: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

CCP1CON

INTCON

PIE1

—

ANSB5

DC1

ANSB4

B1

—

56

107

38

—

CCP1M3 CCP1M2 CCP1M1 CCP1M0

GIE

PEIE

ADIE

ADIF

RB6

TMR0IE

RCIE

INTE

TXIE

TXIF

RB4

RABIE

SSPIE

SSPIF

—

TMR0IF

INTF

RABIF

TMR1GIE

TMR1GIF

RB7

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

39

PIR1

RCIF

40

PORTB

TMR1H

TMR1L

TRISB

RB5

—

55

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

98

TRISB7

TRISC7

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

—

55

TRISC

TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

T1SYNC TMR1ON

61

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0

—

102

103

T1CON

T1GCON

TMR1GE T1GPOL

T1GTM

T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0

DONE

Legend: x= unknown, u= unchanged, —= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1

module.

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The TMR2 and PR2 registers are both fully readable

and writable. On any Reset, the TMR2 register is set to

00h and the PR2 register is set to FFh.

14.0 TIMER2 MODULE

The Timer2 module is an 8-bit timer with the following

features:

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Timer2 is turned off by clearing

the TMR2ON bit to a ‘0’.

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

The Timer2 prescaler is controlled by the T2CKPS bits

in the T2CON register. The Timer2 postscaler is

controlled by the TOUTPS bits in the T2CON register.

The prescaler and postscaler counters are cleared

when:

See Figure 14-1 for a block diagram of Timer2.

• A write to TMR2 occurs.

• A write to T2CON occurs.

14.1 Timer2 Operation

The clock input to the Timer2 module is the system

instruction clock (FOSC/4). The clock is fed into the

Timer2 prescaler, which has prescale options of 1:1,

1:4 or 1:16. The output of the prescaler is then used to

increment the TMR2 register.

• Any device Reset occurs (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset).

Note:

TMR2 is not cleared when T2CON is

written.

The values of TMR2 and PR2 are constantly compared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle.

• The Timer2 postscaler is incremented.

The match output of the Timer2/PR2 comparator is

then fed into the Timer2 postscaler. The postscaler has

postscale options of 1:1 to 1:16 inclusive. The output of

the Timer2 postscaler is used to set the TMR2IF

interrupt flag bit in the PIR1 register.

FIGURE 14-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

TMR2

Output

Prescaler

Reset

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS<1:0>

4

TOUTPS<3:0>

 2010-2013 Microchip Technology Inc.

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PIC16(L)F720/721

14.2

Timer2 Control Register

REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

R/W-0

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

Unimplemented: Read as ‘0’

bit 6-3

TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000= 1:1 Postscaler

0001= 1:2 Postscaler

0010= 1:3 Postscaler

0011= 1:4 Postscaler

0100= 1:5 Postscaler

0101= 1:6 Postscaler

0110= 1:7 Postscaler

0111= 1:8 Postscaler

1000= 1:9 Postscaler

1001= 1:10 Postscaler

1010= 1:11 Postscaler

1011= 1:12 Postscaler

1100= 1:13 Postscaler

1101= 1:14 Postscaler

1110= 1:15 Postscaler

1111= 1:16 Postscaler

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

RABIE

SSPIE

SSPIF

TMR0IF

INTF

RABIF

TMR1IE

TMR1IF

38

39

TMR1GIE

TMR1GIF

CCP1IE TMR2IE

CCP1IF TMR2IF

PIR1

40

RCIF

PR2

Timer2 module Period Register

Timer2 module Register

105

106

TMR2

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

Legend: x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for Timer2

module.

DS40001430E-page 106

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15.0 CAPTURE/COMPARE/PWM

(CCP) MODULE

TABLE 15-1: CCP MODE – TIMER

RESOURCES REQUIRED

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events. In Capture mode, the peripheral allows the

timing of the duration of an event. The Compare mode

allows the user to trigger an external event when a

predetermined amount of time has expired. The PWM

mode can generate a Pulse-Width Modulated signal of

varying frequency and duty cycle.

CCP Mode

Capture

Timer Resource

Timer1

Timer2

Compare

PWM

The timer resources used by the module are shown in

Table 15-1.

Additional information on CCP modules is available in

the Application Note AN594, “Using the CCP Modules”

(DS00594).

REGISTER 15-1: CCP1CON: CCP1 CONTROL REGISTER

U-0

—

U-0

—

R/W-0

DC1

R/W-0

B1

R/W-0

CCP1M1

R/W-0

CCP1M3

CCP1M2

CCP1M0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

DC1:B1: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0

CCP1M<3:0>: CCP mode Select bits

0000= Capture/Compare/PWM off (resets CCP module)

0001= Unused (reserved)

0010= Compare mode, toggle output on match (CCP1IF bit of the PIRx register is set)

0011= Unused (reserved)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, set output on match (CCP1IF bit of the PIR1 register is set)

1001= Compare mode, clear output on match (CCP1IF bit of the PIR1 register is set)

1010= Compare mode, generate software interrupt on match (CCP1IF bit is set of the PIRx register,

CCP1 pin is unaffected)

1011= Compare mode, trigger special event (CCP1IF bit of the PIR1register is set, TMR1 is reset

and A/D conversion is started if the ADC module is enabled. CCP1 pin is unaffected.)

11xx= PWM mode.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 107

PIC16(L)F720/721

15.1.3

SOFTWARE INTERRUPT

15.1 Capture Mode

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP1IE interrupt enable bit of the PIE1 register clear to

avoid false interrupts. Additionally, the user should

clear the CCP1IF interrupt flag bit of the PIR1 register

following any change in operating mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin CCP1. An event is defined as one of the

following and is configured by the CCP1M<3:0> bits of

the CCP1CON register:

• Every falling edge

• Every rising edge

15.1.4

CCP PRESCALER

• Every 4th rising edge

• Every 16th rising edge

There are four prescaler settings specified by the

CCP1M<3:0> bits of the CCP1CON register.

Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter

is cleared. Any Reset will clear the prescaler counter.

When a capture is made, the Interrupt Request Flag bit

CCP1IF of the PIR1 register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPR1H, CCPR1L register pair

is read, the old captured value is overwritten by the new

captured value (refer to Figure 15-1).

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCP1CON register before changing the

prescaler (refer to Example 15-1).

15.1.1

CCP1 PIN CONFIGURATION

In Capture mode, the CCP1 pin should be configured

as an input by setting the associated TRIS control bit.

EXAMPLE 15-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

BANKSELCCP1CON

;Set Bank bits to point

;to CCP1CON

;Turn CCP module off

Note:

If the CCP1 pin is configured as an output,

a write to the port can cause a capture

condition.

CLRF

CCP1CON

MOVLW

NEW_CAPT_PS;Load the W reg with

; the new prescaler

; move value and CCP ON

;Load CCP1CON with this

; value

FIGURE 15-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

MOVWF

CCP1CON

Set Flag bit CCP1IF

(PIR1 register)

15.1.5

CAPTURE DURING SLEEP

Prescaler

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by the

instruction clock (FOSC/4), or by an external clock

source.

 1, 4, 16

CCP1

CCPR1H

CCPR1L

Capture

Enable

and

Edge Detect

TMR1H

TMR1L

If Timer1 is clocked by FOSC/4, then Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

CCP1CON<3:0>

System Clock (FOSC)

If Timer1 is clocked by an external clock source, then

Capture mode will operate as defined in Section 15.1

“Capture Mode”.

15.1.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode or when

Timer1 is clocked at FOSC, the capture operation may

not work.

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCP1

pin, Timer1 must be clocked from the

Instruction Clock (FOSC/4) or from an

external clock source.

DS40001430E-page 108

 2010-2013 Microchip Technology Inc.

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TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

CCP1CON

CCPR1L

CCPR1H

INTCON

—

ANSB5

DC1

ANSB4

B1

—

56

107

—

CCP1M3 CCP1M2 CCP1M1 CCP1M0

Capture/Compare/PWM Register Low Byte

Capture/Compare/PWM Register High Byte

—

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

RABIE

TMR0IF

INTF

RABIF

38

PIE1

TMR1GIE

TMR1GIF

SSPIE

SSPIF

—

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

39

PIR1

RCIF

40

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0

T1SYNC

—

TMR1ON

T1CON

T1GCON

102

103

TMR1GE

T1GPOL

T1GTM

T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0

DONE

TMR1L

TMR1H

TRISB

TRISC

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

98

55

61

TRISB7

TRISC7

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

—

TRISC3 TRISC2 TRISC1 TRISC0

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the

capture.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 109

PIC16(L)F720/721

15.2.2

TIMER1 MODE SELECTION

15.2 Compare Mode

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCP1 module may:

• Toggle the CCP1 output

• Set the CCP1 output

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. For the Compare operation of the

TMR1 register to the CCPR1 register to

occur, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

• Clear the CCP1 output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCP1M<3:0> control bits of the CCP1CON register.

All Compare modes can generate an interrupt.

15.2.3

SOFTWARE INTERRUPT MODE

When Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the CCP1IF bit in the PIR1

register is set and the CCP1 module does not assert

control of the CCP1 pin (refer to the CCP1CON

register).

FIGURE 15-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

CCP1CON<3:0>

Mode Select

15.2.4

SPECIAL EVENT TRIGGER

Set CCP1IF Interrupt Flag

(PIR1)

When Special Event Trigger mode is chosen

(CCP1M<3:0> = 1011), the CCP1 module does the

following:

4

CCPR1H CCPR1L

Comparator

CCP1

Q

S

R

Output

Logic

Match

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

TMR1H TMR1L

TRIS

The CCP1 module does not assert control of the CCP1

pin in this mode (refer to the CCP1CON register).

Output Enable

Special Event Trigger

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPR1H, CCPR1L

register pair. The TMR1H, TMR1L register pair is not

reset until the next rising edge of the Timer1 clock. This

allows the CCPR1H, CCPR1L register pair to

effectively provide a 16-bit programmable period

register for Timer1.

Special Event Trigger will:

•

Clear TMR1H and TMR1L registers.

NOT set interrupt flag bit TMR1IF of the PIR1 register.

Set the GO/DONE bit to start the ADC conversion.

15.2.1

CCP1 PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the associated TRIS bit.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

Note:

Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default low level. This is not the PORT I/O

data latch.

2: Removing the match condition by

changing the contents of the CCPR1H

and CCPR1L register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will

preclude the Reset from occurring.

15.2.5

COMPARE DURING SLEEP

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

DS40001430E-page 110

 2010-2013 Microchip Technology Inc.

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TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

—

CHS3

CHS2

CHS1

CHS0

GO/

ADON

79

DONE

ANSELB

CCP1CON

CCPR1L

CCPR1H

INTCON

—

ANSB5

DC1

ANSB4

B1

—

56

107

—

CCP1M3 CCP1M2 CCP1M1 CCP1M0

Capture/Compare/PWM Register Low Byte

Capture/Compare/PWM Register High Byte

—

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

RABIE

TMR0IF

INTF

RABIF

38

PIE1

TMR1GIE

TMR1GIF

SSPIE

SSPIF

—

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

39

PIR1

RCIF

40

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0

T1SYNC

—

TMR1ON

T1CON

T1GCON

102

103

TMR1GE T1GPOL

T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0

DONE

TMR1L

TMR1H

TRISB

TRISC

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

98

55

61

TRISB7

TRISC7

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

—

TRISC3

TRISC2 TRISC1 TRISC0

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the

compare.

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PIC16(L)F720/721

The PWM output (Figure 15-4) has a time base

(period) and a time that the output stays high (duty

cycle).

15.3 PWM Mode

The PWM mode generates a Pulse-Width Modulated

signal on the CCP1 pin. The duty cycle, period and

resolution are determined by the following registers:

FIGURE 15-4:

CCP PWM OUTPUT

• PR2

Period

• T2CON

• CCPR1L

• CCP1CON

Pulse Width

TMR2 = PR2

TMR2 = CCPR1L:CCP1CON<5:4>

In Pulse-Width Modulation (PWM) mode, the CCP

module produces up to a 10-bit resolution PWM output

on the CCP1 pin.

TMR2 = 0

Figure 15-3 shows a simplified block diagram of PWM

operation.

15.3.1

CCPX PIN CONFIGURATION

In PWM mode, the CCP1 pin is multiplexed with the

PORT data latch. The user must configure the CCP1

pin as an output by clearing the associated TRIS bit.

Figure 15-4 shows a typical waveform of the PWM

signal.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, refer to Section 15.3.8

“Setup for PWM Operation”.

Note:

Clearing the CCP1CON register will

relinquish CCP1 control of the CCP1 pin.

FIGURE 15-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

CCP1CON<5:4>

Duty Cycle Registers

CCPR1L

CCPR1H⁽²⁾(Slave)

Comparator

CCP1

R

S

Q

(1)

TMR2

TRIS

Comparator

PR2

Clear Timer2,

toggle CCP1 pin and

latch duty cycle

Note 1:

2:

The 8-bit timer TMR2 register is concatenated with

the 2-bit internal system clock (FOSC), or two bits of

the prescaler, to create the 10-bit time base.

In PWM mode, CCPR1H is a read-only register.

DS40001430E-page 112

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15.3.2

PWM PERIOD

15.3.3

PWM DUTY CYCLE

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 15-1.

The PWM duty cycle is specified by writing a 10-bit value

to multiple registers: CCPR1L register and DC1 and B1

bits of the CCP1CON register. The CCPR1L contains

the eight MSbs and the DC1 and B1 bits of the

CCP1CON register contain the two LSbs. CCPR1L and

DC1 and B1 bits of the CCP1CON register can be

written to at any time. The duty cycle value is not latched

into CCPR1H until after the period completes (i.e., a

match between PR2 and TMR2 registers occurs). While

using the PWM, the CCPR1H register is read-only.

EQUATION 15-1: PWM PERIOD

PWM Period = PR2 + 1  4  TOSC 

(TMR2 Prescale Value)

Note:

TOSC = 1/FOSC

Equation 15-2 is used to calculate the PWM pulse

width.

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

Equation 15-3 is used to calculate the PWM duty cycle

ratio.

• TMR2 is cleared

• The CCP1 pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

EQUATION 15-2: PULSE WIDTH

• The PWM duty cycle is latched from CCPR1L into

CCPR1H.

Pulse Width = CCPR1L:CCP1CON<5:4> 

TOSC  (TMR2 Prescale Value)

Note:

The

Timer2

postscaler

(refer

to

Section 14.1 “Timer2 Operation”) is not

used in the determination of the PWM

frequency.

Note: TOSC = 1/FOSC

EQUATION 15-3: DUTY CYCLE RATIO

CCPR1L:CCP1CON<5:4>

Duty Cycle Ratio = -----------------------------------------------------------------------

4PR2 + 1

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or two bits

of the prescaler, to create the 10-bit time base. The

system clock is used if the Timer2 prescaler is set to 1:1.

When the 10-bit time base matches the CCPR1H and

2-bit latch, then the CCP1 pin is cleared (refer to

Figure 15-3).

 2010-2013 Microchip Technology Inc.

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PIC16(L)F720/721

15.3.4

PWM RESOLUTION

EQUATION 15-4: PWM RESOLUTION

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution

will result in 1024 discrete duty cycles, whereas an 8-bit

resolution will result in 256 discrete duty cycles.

log4PR2 + 1

Resolution = ----------------------------------------- bits

log2

The maximum PWM resolution is 10 bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 15-4.

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 16 MHz)

PWM Frequency

977 Hz

3.91 kHz

15.625 kHz

62.50 kHz

125.0 kHz

250.0 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0x0F

6

0xFF

10

0xFF

10

Maximum Resolution (bits)

TABLE 15-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

Maximum Resolution (bits)

4. Load the CCPR1L register and the DCxBx bits of

the CCP1CON register, with the PWM duty cycle

value.

15.3.5

OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the CCP1

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMR2 will continue from its

previous state.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the PIR1

register. See Note below.

• Configure the T2CKPS bits of the T2CON

register with the Timer2 prescale value.

15.3.6

CHANGES IN SYSTEM CLOCK

FREQUENCY

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

The PWM frequency is derived from the system clock

frequency (FOSC). Any changes in the system clock

frequency will result in changes to the PWM frequency.

Refer to Section 7.0 “Oscillator Module” for

additional details.

6. Enable PWM output pin:

• Wait until Timer2 overflows, TMR2IF bit of the

PIR1 register is set. See Note below.

• Enable the PWM pin (CCP1) output driver(s)

by clearing the associated TRIS bit(s).

15.3.7

EFFECTS OF RESET

Note:

In order to send a complete duty cycle and

period on the first PWM output, the above

steps must be included in the setup

sequence. If it is not critical to start with a

complete PWM signal on the first output,

then step 6 may be ignored.

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

15.3.8

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Disable the PWM pin (CCP1) output driver(s) by

setting the associated TRIS bit(s).

2. Load the PR2 register with the PWM period value.

3. Configure the CCP module for the PWM mode

by loading the CCP1CON register with the

appropriate values.

DS40001430E-page 114

 2010-2013 Microchip Technology Inc.

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TABLE 15-6: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

CCP1CON

CCPR1L

CCPR1H

PR2

—

ANSB5

DC1

ANSB4

B1

—

56

107

—

CCP1M3 CCP1M2 CCP1M1 CCP1M0

Capture/Compare/PWM Register Low Byte

Capture/Compare/PWM Register High Byte

Timer2 module Period Register

—

105

106

105

55

T2CON

TMR2

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

Timer2 module Register

TRISB

TRISB7 TRISB6

TRISC7 TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

—

TRISC

TRISC3

TRISC2

TRISC1

TRISC0

61

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the

PWM.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 115

PIC16(L)F720/721

NOTES:

DS40001430E-page 116

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

The AUSART module includes the following capabilities:

16.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

ASYNCHRONOUS RECEIVER

TRANSMITTER (AUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Sleep operation

The

Addressable

Universal

Synchronous

Asynchronous Receiver Transmitter (AUSART)

module is a serial I/O communications peripheral. It

contains all the clock generators, shift registers and

data buffers necessary to perform an input or output

serial data transfer independent of device program

execution. The AUSART, also known as a Serial

Communications Interface (SCI), can be configured as

a full-duplex asynchronous system or half-duplex

synchronous system. Full-Duplex mode is useful for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

Block diagrams of the AUSART transmitter and

receiver are shown in Figure 16-1 and Figure 16-2.

FIGURE 16-1:

AUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIE

Interrupt

TXIF

TXREG Register

8

TX/CK

MSb

(8)

LSb

0

Pin Buffer

and Control

• • •

Transmit Shift Register (TSR)

TXEN

TRMT

SPEN

Baud Rate Generator

FOSC

÷ n

TX9

n

+ 1

Multiplier x4 x16 x64

TX9D

SYNC

BRGH

1

x

0

1

0

SPBRG

 2010-2013 Microchip Technology Inc.

DS40001430E-page 117

PIC16(L)F720/721

FIGURE 16-2:

AUSART RECEIVE BLOCK DIAGRAM

SPEN

CREN

OERR

RX/DT

RSR Register

MSb

Stop (8)

LSb

Pin Buffer

and Control

Data

Recovery

7

1

0

START

• • •

Baud Rate Generator

FOSC

RX9

÷ n

n

+ 1

Multiplier x4 x16 x64

SYNC

BRGH

1

x

0

1

0

FIFO

SPBRG

RX9D

FERR

RCREG Register

8

Data Bus

RCIF

RCIE

Interrupt

The operation of the AUSART module is controlled

through two registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

These registers are detailed in Register 16-1 and

Register 16-2, respectively.

DS40001430E-page 118

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

16.1 AUSART Asynchronous Mode

Note 1: When the SPEN bit is set the RX/DT I/O

pin is automatically configured as an input,

regardless of the state of the correspond-

ing TRIS bit and whether or not the AUS-

ART receiver is enabled. The RX/DT pin

data can be read via a normal PORT read

but PORT latch data output is precluded.

The AUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH Mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the Mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is eight bits. Each transmitted bit persists for a

period of 1/(baud rate). An on-chip dedicated 8-bit Baud

Rate Generator is used to derive standard baud rate

frequencies from the system oscillator. Refer to

Table 16-5 for examples of baud rate configurations.

2: The TXIF transmitter interrupt flag is set

when the TXEN enable bit is set.

16.1.1.2

Transmitting Data

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

The AUSART transmits and receives the LSb first. The

AUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

16.1.1

AUSART ASYNCHRONOUS

TRANSMITTER

16.1.1.3

Transmit Interrupt Flag

The AUSART transmitter block diagram is shown in

Figure 16-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

The TXIF interrupt flag bit of the PIR1 register is set

whenever the AUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execution. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

16.1.1.1

Enabling the Transmitter

The AUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

• TXEN = 1

• SYNC = 0

• SPEN = 1

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

All other AUSART control bits are assumed to be in

their default state.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the AUSART. Clearing the SYNC

bit of the TXSTA register configures the AUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the AUSART and automatically

configures the TX/CK I/O pin as an output.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 119

PIC16(L)F720/721

16.1.1.4

TSR Status

16.1.1.6

Asynchronous Transmission Setup:

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

1. Initialize the SPBRG register and the BRGH bit to

achieve the desired baud rate (Refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9

control bit. A set ninth data bit will indicate that

the eight Least Significant data bits are an

address when the receiver is set for address

detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

16.1.1.5

Transmitting 9-bit Characters

4. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

The AUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set, the

AUSART will shift nine bits out for each character trans-

mitted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the eight Least Significant bits into the TXREG. All nine

bits of data will be transferred to the TSR shift register

immediately after the TXREG is written.

5. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

6. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

7. Load 8-bit data into the TXREG register. This

will start the transmission.

A special 9-bit Address mode is available for use with

multiple receivers. Refer to Section 16.1.2.7 “Address

Detection” for more information on the Address mode.

FIGURE 16-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

TX/CK pin

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Empty Flag)

1 TCY

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

DS40001430E-page 120

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 16-4:

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

TX/CK pin

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

Word 2

TXIF bit

(Transmit Buffer

Empty Flag)

1 TCY

Word 1

1 TCY

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg.

Note:

This timing diagram shows two consecutive transmissions.

TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

RX9

TMR0IE

RCIE

INTE

TXIE

RABIE

SSPIE

SSPIF

ADDEN

BRG3

TMR0IF

INTF

RABIF

38

39

TMR1GIE

TMR1GIF

SPEN

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIR1

RCIF

TXIF

40

RCSTA

SPBRG

TRISC

TXREG

TXSTA

SREN

BRG5

CREN

BRG4

FERR

BRG2

OERR

BRG1

RX9D

BRG0

126

127

61

BRG7

BRG6

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

AUSART Transmit Data Register

—

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

125

Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for asynchronous transmission.

16.1.2

AUSART ASYNCHRONOUS

RECEIVER

16.1.2.1

Enabling the Receiver

The AUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 16-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all eight

or nine bits of the character have been shifted in, they

are immediately transferred to a two character First-In

First-Out (FIFO) memory. The FIFO buffering allows

reception of two complete characters and the start of a

third character before software must start servicing the

AUSART receiver. The FIFO and RSR registers are not

directly accessible by software. Access to the received

data is via the RCREG register.

• CREN = 1

• SYNC = 0

• SPEN = 1

All other AUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the AUSART. Clearing the SYNC bit

of the TXSTA register configures the AUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the AUSART and automatically

configures the RX/DT I/O pin as an input.

Note:

When the SPEN bit is set, the TX/CK I/O

pin is automatically configured as an

output, regardless of the state of the

corresponding TRIS bit and whether or

not the AUSART transmitter is enabled.

The PORT latch is disconnected from the

output driver so it is not possible to use the

TX/CK pin as a general purpose output.

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DS40001430E-page 121

PIC16(L)F720/721

16.1.2.2

Receiving Data

16.1.2.4

Receive Framing Error

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. Refer to Section 16.1.2.4 “Receive

Framing Error” for more information on framing

errors.

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the AUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the AUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

16.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

setting the AUSART by clearing the SPEN bit of the

RCSTA register.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition

is

cleared.

Refer

to

Section 16.1.2.5 “Receive Overrun

Error” for more information on overrun

errors.

16.1.2.3

Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the AUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

16.1.2.6

Receiving 9-bit Characters

The AUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set, the AUSART

will shift 9 bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE, Peripheral Interrupt Enable bit of the

INTCON register

• GIE, Global Interrupt Enable bit of the INTCON

register

The RCIF interrupt flag bit of the PIR1 register will be

set when there is an unread character in the FIFO,

regardless of the state of interrupt enable bits.

DS40001430E-page 122

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

16.1.2.7

Address Detection

16.1.2.9

9-bit Address Detection Mode Setup

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

register.

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit of the PIR1 register. All other characters will be

ignored.

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

4. Enable 9-bit reception by setting the RX9 bit.

5. Enable address detection by setting the ADDEN

bit.

6. Enable reception by setting the CREN bit.

7. The RCIF interrupt flag bit of the PIR1 register

will be set when a character with the ninth bit set

is transferred from the RSR to the receive buffer.

An interrupt will be generated if the RCIE inter-

rupt enable bit of the PIE1 register was also set.

16.1.2.8

Asynchronous Reception Setup:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

8. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

9. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register. Software determines if this is the

device’s address.

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

4. If 9-bit reception is desired, set the RX9 bit.

5. Enable reception by setting the CREN bit.

6. The RCIF interrupt flag bit of the PIR1 register

will be set when a character is transferred from

the RSR to the receive buffer. An interrupt will be

generated if the RCIE bit of the PIE1 register

was also set.

7. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

8. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register.

9. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 123

PIC16(L)F720/721

FIGURE 16-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

RABIE

SSPIE

SSPIF

TMR0IF

INTF

RABIF

38

39

TMR1GIE

TMR1GIF

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIR1

RCIF

40

RCREG

RCSTA

SPBRG

TRISC

TXSTA

AUSART Receive Data Register

123

126

127

61

SPEN

BRG7

RX9

SREN

BRG5

CREN

BRG4

ADDEN

BRG3

FERR

BRG2

OERR

BRG1

RX9D

BRG0

BRG6

TRISC7

CSRC

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

TX9 TXEN SYNC BRGH TRMT TX9D

—

125

Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for asynchronous reception.

DS40001430E-page 124

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

R/W-0

TX9

R/W-0

TXEN⁽¹⁾

R/W-0

SYNC

U-0

—

R/W-0

BRGH

R-1

R/W-0

TX9D

TRMT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit⁽¹⁾

1= Transmit enabled

0= Transmit disabled

SYNC: AUSART mode Select bit

1= Synchronous mode

0= Asynchronous mode

bit 3

bit 2

Unimplemented: Read as ‘0’

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Synchronous mode.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 125

PIC16(L)F720/721

REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit⁽¹⁾

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

Synchronous mode:

Must be set to ‘0’

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure

TRISx = 1.

DS40001430E-page 126

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

EXAMPLE 16-1:

CALCULATING BAUD

RATE ERROR

16.2 AUSART Baud Rate Generator

(BRG)

For a device with FOSC of 16 MHz, desired baud rate of

9600, and Asynchronous mode with SYNC = 0and BRGH

= 0(as seen in Table 16-5):

The Baud Rate Generator (BRG) is an 8-bit timer that

is dedicated to the support of both the asynchronous

and synchronous AUSART operation.

FOSC

Desired Baud Rate = ---------------------------------------

64SPBRG + 1

The SPBRG register determines the period of the free

running baud rate timer. In Asynchronous mode the

multiplier of the baud rate period is determined by the

BRGH bit of the TXSTA register. In Synchronous mode,

the BRGH bit is ignored.

Solving for SPBRG:

FOSC









--------------------------------------------------------

SPBRG =

=

– 1

Table 16-3 contains the formulas for determining the

baud rate. Example 16-1 provides a sample calculation

for determining the baud rate and baud rate error.

64Desired Baud Rate

16000000

649600







------------------------

– 1



Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 16-5. It may be

advantageous to use the high baud rate (BRGH = 1), to

reduce the baud rate error.

= 25.042 = 25

16000000

Actual Baud Rate = --------------------------

6425 + 1

= 9615

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures that

the BRG does not wait for a timer overflow before

outputting the new baud rate.

Actual Baud Rate – Desired Baud Rate





% Error = ------------------------------------------------------------------------------------------------- 100





Desired Baud Rate

9615 – 9600







-----------------------------

=

100 = 0.16%



9600

TABLE 16-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

AUSART Mode

SYNC

BRGH

0

1

0

1

x

Asynchronous

Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend:

x= Don’t care, n = value of SPBRG register

TABLE 16-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RCSTA

SPBRG

TXSTA

SPEN

BRG7

CSRC

RX9

BRG6

TX9

SREN

BRG5

TXEN

CREN

BRG4

SYNC

ADDEN

BRG3

—

FERR

BRG2

BRGH

OERR

BRG1

TRMT

RX9D

BRG0

TX9D

126

127

125

Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 127

PIC16(L)F720/721

TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0

FOSC = 16.0000 MHz

FOSC = 11.0592 MHz

FOSC = 8.000 MHz

FOSC = 4.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

—

1201

2403

9615

10416

19.23k

—

0.08

0.16

-0.01

0.16

—

207

103

25

300

1200

—

143

71

17

16

8

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

9600

10417

19.2k

57.6k

115.2k

23

10417

—

0.00

—

12

—

2

—

57.60k

—

SYNC = 0, BRGH = 0

FOSC = 3.6864 MHz FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

0.00

—

300

1200

300

1200

2400

9600

—

191

47

23

5

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

—

2

—

19.20k

0.00

—

0

—

57.60k

—

DS40001430E-page 128

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1

FOSC = 11.0592 MHz FOSC = 8.000 MHz

FOSC = 16.0000 MHz

FOSC = 4.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

0.16

0.00

0.16

—

2400

—

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

—

71

65

35

11

5

9600

9615

10417

19.23k

58.8k

—

0.16

0.00

0.16

2.12

—

103

95

51

16

—

9600

0.00

0.53

0.00

10417

19.2k

57.6k

115.2k

10473

19.20k

57.60k

115.2k

23

12

—

SYNC = 0, BRGH = 1

FOSC = 3.6864 MHz FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

300

1200

—

191

95

23

21

11

3

300

1202

2404

—

0.16

—

207

51

25

—

5

1200

0.00

0.53

0.00

2400

9600

10417

19.2k

57.6k

115.2k

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

1

—

 2010-2013 Microchip Technology Inc.

DS40001430E-page 129

PIC16(L)F720/721

16.3.1.2

Synchronous Master Transmission

16.3 AUSART Synchronous Mode

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the AUSART is configured for

synchronous master transmit operation.

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary

circuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character, the new character data is held in

the TXREG until the last bit of the previous character

has been transmitted. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately trans-

ferred to the TSR. The transmission of the character

commences immediately following the transfer of the

data to the TSR from the TXREG.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The AUSART can operate as either a master or slave

device.

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

Start and Stop bits are not used in synchronous

transmissions.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

16.3.1

SYNCHRONOUS MASTER MODE

16.3.1.3

Synchronous Master Transmission

Setup:

The following bits are used to configure the AUSART

for Synchronous Master operation:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

• SYNC = 1

• CSRC = 1

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

AUSART.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

16.3.1.1

Master Clock

8. Start transmission by loading data to the TXREG

register.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin output driver is automatically enabled

when the AUSART is configured for synchronous

transmit or receive operation. Serial data bits change

on the leading edge to ensure they are valid at the trail-

ing edge of each clock. One clock cycle is generated

for each data bit. Only as many clock cycles are

generated as there are data bits.

DS40001430E-page 130

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 16-6:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

FIGURE 16-7:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 16-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

RX9

TMR0IE

RCIE

INTE

TXIE

RABIE

SSPIE

SSPIF

ADDEN

BRG3

TMR0IF

INTF

RABIF

38

39

TMR1GIE

TMR1GIF

SPEN

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIR1

RCIF

TXIF

40

RCSTA

SPBRG

TRISC

TXREG

TXSTA

SREN

BRG5

CREN

BRG4

FERR

BRG2

OERR

BRG1

RX9D

BRG0

126

127

61

BRG7

BRG6

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

AUSART Transmit Data Register

—

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

125

Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for synchronous master

transmission.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 131

PIC16(L)F720/721

16.3.1.4

Synchronous Master Reception

16.3.1.7

Receiving 9-bit Characters

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

AUSART is configured for synchronous master receive

operation.

The AUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set, the AUSART

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

Address detection in Synchronous modes is not

supported, therefore the ADDEN bit of the RCSTA

register must be cleared.

16.3.1.8

Synchronous Master Reception

Setup

1. Initialize the SPBRG register for the appropriate

baud rate. Set or clear the BRGH bit, as

required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

Register (RSR). When a complete character is

received into the RSR, the RCIF bit of the PIR1 register

is set and the character is automatically transferred to

the two character receive FIFO. The Least Significant

eight bits of the top character in the receive FIFO are

available in RCREG. The RCIF bit remains set as long

as there are un-read characters in the receive FIFO.

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit reception is desired, set bit RX9.

6. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

16.3.1.5

Slave Clock

8. Interrupt flag bit RCIF of the PIR1 register will be

set when reception of a character is complete.

An interrupt will be generated if the RCIE inter-

rupt enable bit of the PIE1 register was set.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The TX/

CK pin output driver is automatically disabled when the

device is configured for synchronous slave transmit or

receive operation. Serial data bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One data bit is transferred for each clock cycle.

Only as many clock cycles should be received as there

are data bits.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit, which

resets the AUSART.

16.3.1.6

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register.

DS40001430E-page 132

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 16-8:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Synchronous Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

RABIE

SSPIE

SSPIF

TMR0IF

INTF

RABIF

38

39

TMR1GIE

TMR1GIF

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIR1

RCIF

40

RCREG

RCSTA

TRISC

TXSTA

AUSART Receive Data Register

SREN CREN ADDEN FERR

123

126

61

SPEN

TRISC7

CSRC

RX9

OERR

RX9D

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

TX9 TXEN SYNC BRGH TRMT TX9D

—

125

Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for synchronous master

reception.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 133

PIC16(L)F720/721

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

16.3.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the AUSART

for synchronous slave operation:

1. The first character will immediately transfer to

the TSR register and transmit.

• SYNC = 1

2. The second word will remain in TXREG register.

3. The TXIF bit will not be set.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

AUSART.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

16.3.2.2

Synchronous Slave Transmission

Setup

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

16.3.2.1

AUSART Synchronous Slave

Transmit

2. Clear the CREN and SREN bits.

The operation of the Synchronous Master and Slave

modes are identical (refer to Section 16.3.1.2

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

3. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

TXIE bit.

4. If 9-bit transmission is desired, set the TX9 bit.

5. Enable transmission by setting the TXEN bit.

6. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant 8 bits to the TXREG register.

TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

RX9

TMR0IE

RCIE

INTE

TXIE

RABIE

SSPIE

SSPIF

ADDEN

TMR0IF

INTF

RABIF

38

39

TMR1GIE

TMR1GIF

SPEN

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIR1

RCIF

TXIF

40

RCSTA

TRISC

TXREG

TXSTA

SREN

CREN

FERR

OERR

RX9D

126

61

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

AUSART Transmit Data Register

—

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

125

Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for synchronous slave

transmission.

DS40001430E-page 134

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

16.3.2.3

AUSART Synchronous Slave

Reception

16.3.2.4

Synchronous Slave Reception Setup

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

The operation of the Synchronous Master and Slave

modes is identical (Section 16.3.1.4 “Synchronous

Master Reception”), with the following exceptions:

2. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

• Sleep

3. If 9-bit reception is desired, set the RX9 bit.

• CREN bit is always set, therefore the receiver is

never Idle

4. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

• SREN bit, which is a “don’t care” in Slave mode

5. Set the CREN bit to enable reception.

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE interrupt enable bit

of the PIE1 register is set, the interrupt generated will

wake the device from Sleep and execute the next

instruction. If the GIE bit is also set, the program will

branch to the interrupt vector.

6. The RCIF bit of the PIR1 register will be set

when reception is complete. An interrupt will be

generated if the RCIE bit of the PIE1 register

was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

8. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register.

TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

TMR0IE

RCIE

INTE

TXIE

TXIF

RABIE

SSPIE

SSPIF

TMR0IF

INTF

RABIF

38

39

TMR1GIE

TMR1GIF

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIR1

RCIF

40

RCREG

RCSTA

TRISC

TXSTA

AUSART Receive Data Register

SREN CREN ADDEN FERR

123

126

61

SPEN

TRISC7

CSRC

RX9

OERR

RX9D

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

TX9 TXEN SYNC BRGH TRMT TX9D

—

125

Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.

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16.4.2

SYNCHRONOUS TRANSMIT

DURING SLEEP

16.4 AUSART Operation During Sleep

The AUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the

necessary signals to run the Transmit or Receive Shift

registers during Sleep.

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for synchronous slave transmission

(refer to Section 16.3.2.2 “Synchronous Slave

Transmission Setup”).

Synchronous Slave mode uses an externally generated

clock to run the Transmit and Receive Shift registers.

• The TXIF interrupt flag must be cleared by writing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

16.4.1

SYNCHRONOUS RECEIVE DURING

SLEEP

• If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON

register.

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for synchronous slave reception (refer

to Section 16.3.2.4 “Synchronous Slave

Reception Setup”).

Upon entering Sleep mode, the device will be ready to

accept clocks on the TX/CK pin and transmit data on

the RX/DT pin. When the data word in the TSR has

been completely clocked out by the external device, the

pending byte in the TXREG will transfer to the TSR and

the TXIF flag will be set. Thereby, waking the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

• If interrupts are desired, set the RCIE bit of the

PIE1 register and the PEIE bit of the INTCON

register.

• The RCIF interrupt flag must be cleared by

reading RCREG to unload any pending

characters in the receive buffer.

Upon waking from Sleep, the instruction following the

SLEEPinstruction will be executed. If the GIE, Global

Interrupt Enable bit is also set then the Interrupt

Service Routine at address 0004h will be called.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RCIF interrupt

flag bit of the PIR1 register will be set. Thereby, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the GIE, Global

Interrupt Enable bit of the INTCON register is also set,

then the Interrupt Service Routine at address 0004h

will be called.

DS40001430E-page 136

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PIC16(L)F720/721

A typical SPI connection between microcontroller

devices is shown in Figure 17-1. Addressing of more

than one slave device is accomplished via multiple

hardware slave select lines. External hardware and

additional I/O pins must be used to support multiple

slave select addressing. This prevents extra overhead

in software for communication.

17.0 SSP MODULE OVERVIEW

The Synchronous Serial Port (SSP) module is a serial

interface useful for communicating with other peripher-

als or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers,

display drivers, A/D converters, etc. The SSP module

can operate in one of two modes:

For SPI communication, typically three pins are used:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

17.1 SPI Mode

Additionally, a fourth pin may be used when in a Slave

mode of operation:

The SPI mode allows eight bits of data to be synchro-

nously transmitted and received, simultaneously. The

SSP module can be operated in one of two SPI modes:

• Slave Select (SS)

• Master mode

• Slave mode

SPI is a full-duplex protocol, with all communication

being bidirectional and initiated by a master device. All

clocking is provided by the master device and all bits

are transmitted, MSb first. Care must be taken to

ensure that all devices on the SPI bus are setup to

allow all controllers to send and receive data at the

same time.

FIGURE 17-1:

TYPICAL SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xx

SPI Slave SSPM<3:0> = 010x

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

SS

Slave Select

(optional)

General I/O

Processor 2

Processor 1

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DS40001430E-page 137

PIC16(L)F720/721

FIGURE 17-2:

SPI MODE BLOCK

DIAGRAM

Internal

Data Bus

Read

Write

SSPBUF Reg

SSPSR Reg

SDI

bit 0

bit 7

Shift

Clock

SDO

SS

Control

Enable

RA5/SS

RA0/SS

SSSEL

2

Clock Select

Edge

Select

TMR2

Output

2

Edge

Select

FOSC

Prescaler

4, 16, 64

SCK

4

TRISx

SSPM<3:0>

DS40001430E-page 138

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

17.1.1

MASTER MODE

17.1.1.3

Master Mode Setup

In Master mode, data transfer can be initiated at any

time because the master controls the SCK line. Master

mode determines when the slave (Figure 17-1,

Processor 2) transmits data via control of the SCK line.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is loaded with a byte

value. If the master is only going to receive, SDO output

could be disabled (programmed and used as an input).

The SSPSR register will continue to shift in the signal

present on the SDI pin at the programmed clock rate.

17.1.1.1

Master Mode Operation

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

register shifts the data in and out of the device, MSb

first. The SSPBUF register holds the data that is written

out of the master until the received data is ready. Once

the eight bits of data have been received, the byte is

moved to the SSPBUF register. The Buffer Full Status

bit, BF of the SSPSTAT register, and the SSP Interrupt

Flag bit, SSPIF of the PIR1 register, are then set.

When initializing SPI Master mode operation, several

options need to be specified. This is accomplished by

programming the appropriate control bits in the

SSPCON and SSPSTAT registers. These control bits

allow the following to be specified:

• SCK as clock output

• Idle state of SCK (CKP bit)

• Data input sample phase (SMP bit)

• Output data on rising/falling edge of SCK (CKE bit)

• Clock bit rate

Any write to the SSPBUF register during transmission/

reception of data will be ignored and the Write Collision

Detect bit, WCOL of the SSPCON register, will be set.

User software must clear the WCOL bit so that it can be

determined if the following write(s) to the SSPBUF

register completed successfully.

In Master mode, the SPI clock rate (bit rate) is user

selectable to be one of the following:

• FOSC/4 (or TCY)

• FOSC/16 (or 4  TCY)

• FOSC/64 (or 16  TCY)

• (Timer2 output)/2

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data is written to the SSPBUF. The BF bit of the

SSPSTAT register is set when SSPBUF has been

loaded with the received data (transmission is

complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. The SSP interrupt may be used to

determine when the transmission/reception is

complete and the SSPBUF must be read and/or

written. If interrupts are not used, then software polling

can be done to ensure that a write collision does not

occur. Example 17-1 shows the loading of the SSPBUF

(SSPSR) for data transmission.

This allows

a maximum data rate of 5 Mbps

(at FOSC = 16 MHz).

Figure 17-3 shows the waveforms for Master mode.

The clock polarity is selected by appropriately program-

ming the CKP bit of the SSPCON register. When the

CKE bit is set, the SDO data is valid before there is a

clock edge on SCK. The sample time of the input data

is shown based on the state of the SMP bit and can

occur at the middle or end of the data output time. The

time when the SSPBUF is loaded with the received

data is shown.

Note:

The SSPSR is not directly readable or

writable and can only be accessed by

addressing the SSPBUF register.

17.1.1.4

Sleep in Master Mode

In Master mode, all module clocks are halted and the

transmission/reception will remain in their current state,

paused, until the device wakes from Sleep. After the

device wakes up from Sleep, the module will continue

to transmit/receive data.

17.1.1.2

Enabling Master I/O

To enable the serial port, the SSPEN bit of the

SSPCON register, must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON register and then set the SSPEN bit. If a

Master mode of operation is selected in the SSPM bits

of the SSPCON register, the SDI, SDO and SCK pins

will be assigned as serial port pins.

For these pins to function as serial port pins, they must

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

• SDI configured as input

• SDO configured as output

• SCK configured as output

 2010-2013 Microchip Technology Inc.

DS40001430E-page 139

PIC16(L)F720/721

FIGURE 17-3:

SPI MASTER MODE WAVEFORM

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

SDO

(CKE = 0)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPIF

SSPSR to

SSPBUF

EXAMPLE 17-1:

LOADING THE SSPBUF (SSPSR) REGISTER

BANKSEL

SSPSTAT

;

LOOP

BTFSS

GOTO

SSPSTAT, BF ;Has data been received(transmit complete)?

LOOP

;No

BANKSEL

MOVF

MOVWF

MOVF

SSPBUF

SSPBUF, W

RXDATA

TXDATA, W

SSPBUF

;

;WREG reg = contents of SSPBUF

;Save in user RAM, if data is meaningful

;W reg = contents of TXDATA

;New data to xmit

MOVWF

DS40001430E-page 140

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

17.1.2

SLAVE MODE

17.1.2.2

Enabling Slave I/O

For any SPI device acting as a slave, the data is

transmitted and received as external clock pulses

appear on SCK pin. This external clock must meet the

minimum high and low times as specified in the

electrical specifications.

To enable the serial port, the SSPEN bit of the

SSPCON register must be set. If a Slave mode of

operation is selected in the SSPM bits of the SSPCON

register, the SDI, SDO and SCK pins will be assigned

as serial port pins.

For these pins to function as serial port pins, they must

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

17.1.2.1

Slave Mode Operation

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready.

• SDI configured as input

• SDO configured as output

• SCK configured as input

Optionally, a fourth pin, Slave Select (SS) may be used

in Slave mode. Slave Select may be configured to

operate on the RC6/SS pin via the SSSEL bit in the

APFCON register.

The slave has no control as to when data will be

clocked in or out of the device. All data that is to be

transmitted, to a master or another slave, must be

loaded into the SSPBUF register before the first clock

pulse is received.

Upon selection of a Slave Select pin, the appropriate

bits must be set in the ANSELA and TRISA registers.

Slave Select must be set as an input by setting the

corresponding bit in TRISA, and digital I/O must be

enabled on the SS pin by clearing the corresponding bit

of the ANSELA register.

Once eight bits of data have been received:

• Received byte is moved to the SSPBUF register

• BF bit of the SSPSTAT register is set

• SSPIF bit of the PIR1 register is set

Any write to the SSPBUF register during transmission/

reception of data will be ignored and the Write Collision

Detect bit, WCOL of the SSPCON register, will be set.

User software must clear the WCOL bit so that it can be

determined if the following write(s) to the SSPBUF

register completed successfully.

17.1.2.3

Slave Mode Setup

When initializing the SSP module to SPI Slave mode,

compatibility must be ensured with the master device.

This is done by programming the appropriate control

bits of the SSPCON and SSPSTAT registers. These

control bits allow the following to be specified:

The user’s firmware must read SSPBUF, clearing the

BF flag, or the SSPOV bit of the SSPCON register will

be set with the reception of the next byte and

communication will be disabled.

• SCK as clock input

• Idle state of SCK (CKP bit)

• Data input sample phase (SMP bit)

• Output data on rising/falling edge of SCK (CKE bit)

A SPI module transmits and receives at the same time,

occasionally causing dummy data to be transmitted/

received. It is up to the user to determine which data is

to be used and what can be discarded.

Figure 17-4 and Figure 17-5 show example waveforms

of Slave mode operation.

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PIC16(L)F720/721

FIGURE 17-4:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

FIGURE 17-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

DS40001430E-page 142

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PIC16(L)F720/721

When the SPI module resets, the bit counter is cleared

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit. Figure 17-6

shows the timing waveform for such a synchronization

event.

17.1.2.4

Slave Select Operation

The SS pin allows Synchronous Slave mode operation.

The SPI must be in Slave mode with SS pin control

enabled (SSPM<3:0> = 0100). The associated TRIS bit

for the SS pin must be set, making SS an input.

Note:

SSPSR must be reinitialized by writing to

the SSPBUF register before the data can

be clocked out of the slave again.

In Slave Select mode, when:

• SS = 0, The device operates as specified in

Section 17.1.2 “Slave Mode”.

• SS = 1, The SPI module is held in Reset and the

SDO pin will be tri-stated.

17.1.2.5

Sleep in Slave Mode

While in Sleep mode, the slave can transmit/receive

data. The SPI Transmit/Receive Shift register operates

asynchronously to the device on the externally supplied

clock source. This allows the device to be placed in

Sleep mode and data to be shifted into the SPI

Transmit/Receive Shift register. When all eight bits

have been received, the SSP Interrupt Flag bit will be

set and, if enabled, will wake the device from Sleep.

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPM<3:0> = 0100),

the SPI module will reset if the SS pin is

driven high.

2: If the SPI is used in Slave mode with CKE

set, the SS pin control must be enabled.

FIGURE 17-6:

SLAVE SELECT SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

SSPSR must be reinitialized by writing to

the SSPBUF register before the data can

be clocked out of the slave again.

bit 6

bit 7

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

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PIC16(L)F720/721

REGISTER 17-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

WCOL: Write Collision Detect bit

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

1= A new byte is received while the SSPBUF register is still holding the previous data. In case of

overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read

the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode the overflow

bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF

register.

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

1= Enables serial port and configures SCK, SDO and SDI as serial port pins⁽¹⁾

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level

0= Idle state for clock is a low level

bit 3-0

SSPM<3:0>: Synchronous Serial Port mode Select bits

0000= SPI Master mode, clock = FOSC/4

0001= SPI Master mode, clock = FOSC/16

0010= SPI Master mode, clock = FOSC/64

0011= SPI Master mode, clock = TMR2 output/2

0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.

Note 1: When enabled, these pins must be properly configured as input or output.

DS40001430E-page 144

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PIC16(L)F720/721

REGISTER 17-2: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

SMP: SPI Data Input Sample Phase bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

CKE: SPI Clock Edge Select bit

SPI mode, CKP = 0:

1= Data stable on rising edge of SCK

0= Data stable on falling edge of SCK

SPI mode, CKP = 1:

1= Data stable on falling edge of SCK

0= Data stable on rising edge of SCK

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D/A: Data/Address bit

Used in I²C mode only.

P: Stop bit

Used in I²C mode only.

S: Start bit

Used in I²C mode only.

R/W: Read/Write Information bit

Used in I²C mode only.

UA: Update Address bit

Used in I²C mode only.

BF: Buffer Full Status bit

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

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DS40001430E-page 145

PIC16(L)F720/721

TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELC

INTCON

PIE1

ANSC7

GIE

ANSC6

PEIE

—

ANSC3

RABIE

SSPIE

SSPIF

ANSC2

TMR0IF

ANSC1

INTF

ANSC0

RABIF

61

38

TMR0IE

RCIE

INTE

TXIE

TXIF

39

TMR1GIE

TMR1GIF

ADIE

ADIF

CCP1IE TMR2IE

CCP1IF TMR2IF

TMR1IE

TMR1IF

PIR1

40

RCIF

PR2

Timer2 module Period Register

Synchronous Serial Port Receive Buffer/Transmit Register

105

139

144

145

55

SSPBUF

SSPCON

SSPSTAT

TRISB

WCOL

SMP

SSPOV

CKE

SSPEN

D/A

CKP

P

SSPM3

S

SSPM2

R/W

SSPM1

UA

SSPM0

BF

TRISB7

TRISC7

—

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

—

TRISC

T2CON

TRISC3

TRISC2

TRISC1

TRISC0

61

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

106

Legend: x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used by the SSP in

SPI mode.

DS40001430E-page 146

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

2

FIGURE 17-8:

TYPICAL I²C™

CONNECTIONS

17.2 I C Mode

The SSP module, in I²C mode, implements all slave

functions except general call support. It provides

interrupts on Start and Stop bits in hardware to facilitate

firmware implementations of the master functions. The

SSP module implements the I²C Standard mode

specifications:

VDD VDD

Slave 1

Master

SDA

SCL

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

SDA

SCL

• Start and Stop bit interrupts enabled to support

firmware Master mode

Slave 2

• Address masking

SDA

Two pins are used for data transfer; the SCL pin (clock

line) and the SDA pin (data line). The user must

configure the two pin’s data direction bits as inputs in

the appropriate TRIS register. Upon enabling I²C

mode, the I²C slew rate limiters in the I/O pads are

controlled by the SMP bit of SSPSTAT register. The

SSP module functions are enabled by setting the

SSPEN bit of SSPCON register.

SCL

(optional)

The SSP module has six registers for I²C operation.

They are:

• SSP Control (SSPCON) register

Data is sampled on the rising edge and shifted out on

the falling edge of the clock. This ensures that the SDA

signal is valid during the SCL high time. The SCL clock

input must have minimum high and low times for proper

operation. Refer to Section 23.0 “Electrical

Specifications”.

• SSP Status (SSPSTAT) register

• Serial Receive/Transmit Buffer (SSPBUF) register

• SSP Shift Register (SSPSR), not directly

accessible

• SSP Address (SSPADD) register

• SSP Address Mask (SSPMSK) register

FIGURE 17-7:

I²C™ MODE BLOCK

DIAGRAM

17.2.1

HARDWARE SETUP

Selection of I²C mode, with the SSPEN bit of the

SSPCON register set, forces the SCL and SDA pins to

be open drain, provided these pins are programmed as

inputs by setting the appropriate TRISC bits. The SSP

module will override the input state with the output data,

when required, such as for Acknowledge and slave-

transmitter sequences.

Internal

Data Bus

Read

Write

SSPBUF Reg

SCL

SDA

Shift

Clock

Note:

Pull-up resistors must be provided

externally to the SCL and SDA pins for

proper operation of the I²C module.

SSPSR Reg

MSb

LSb

SSPMSK Reg

Match Detect

SSPADD Reg

Addr Match

Start and

Stop bit Detect

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PIC16(L)F720/721

Figure 17-9 shows the Start and Stop conditions. A

master device generates these conditions for starting

and terminating data transfer. Due to the definition of

the Start and Stop conditions, when data is being trans-

mitted, the SDA line can only change state when the

SCL line is low.

17.2.2

START AND STOP CONDITIONS

During times of no data transfer (Idle time), both the

clock line (SCL) and the data line (SDA) are pulled high

through external pull-up resistors. The Start and Stop

conditions determine the start and stop of data trans-

mission. The Start condition is defined as a high-to-low

transition of the SDA line while SCL is high. The Stop

condition is defined as a low-to-high transition of the

SDA line while SCL is high.

FIGURE 17-9:

START AND STOP CONDITIONS

SDA

SCL

S

P

Change of

Data Allowed

Start

Data Allowed

Stop

Condition

In such a case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF of the PIR1 register is

set. Table 17-2 shows the results of when a data

transfer byte is received, given the status of bits BF and

SSPOV. Flag bit BF is cleared by reading the SSPBUF

register, while bit SSPOV is cleared through software.

17.2.3

ACKNOWLEDGE

After the valid reception of an address or data byte, the

hardware automatically will generate the Acknowledge

(ACK) pulse and load the SSPBUF register with the

received value currently in the SSPSR register. There

are certain conditions that will cause the SSP module

not to generate this ACK pulse. They include any or all

of the following:

• The Buffer Full bit, BF of the SSPSTAT register,

was set before the transfer was received.

• The SSP Overflow bit, SSPOV of the SSPCON

register, was set before the transfer was received.

• The SSP module is being operated in Firmware

Master mode.

TABLE 17-2: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

Generate ACK

Transfer is Received

SSPSR  SSPBUF

Pulse

BF

SSPOV

0

1

0

1

Yes

No

Yes

No

Yes

Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.

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17.2.4

ADDRESSING

17.2.4.2

10-bit Addressing

Once the SSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition,

the 8 bits are shifted into the SSPSR register. All incom-

ing bits are sampled with the rising edge of the clock

line (SCL).

In 10-bit Address mode, two address bytes need to be

received by the slave (Figure 17-11). The five Most

Significant bits (MSbs) of the first address byte specify

if it is a 10-bit address. The R/W bit of the SSPSTAT

register must specify a write so the slave device will

receive the second address byte. For a 10-bit address,

the first byte would equal ‘1111 0 A9 A8 0’, where

A9 and A8 are the two MSbs of the address.

17.2.4.1

7-bit Addressing

In 7-bit Addressing mode (Figure 17-10), the value of

register SSPSR<7:1> is compared to the value of reg-

ister SSPADD<7:1>. The address is compared on the

falling edge of the eighth clock (SCL) pulse. If the

addresses match, and the BF and SSPOV bits are

clear, the following events occur:

The sequence of events for 10-bit address is as follows

for reception:

1. Load SSPADD register with high byte of address.

2. Receive first (high) byte of address (bits SSPIF,

BF and UA of the SSPSTAT register are set).

• The SSPSR register value is loaded into the

SSPBUF register.

3. Read the SSPBUF register (clears bit BF).

4. Clear the SSPIF flag bit.

• The BF bit is set.

5. Update the SSPADD register with second (low)

byte of address (clears UA bit and releases the

SCL line).

• An ACK pulse is generated.

• SSP Interrupt Flag bit, SSPIF of the PIR1 register,

is set (interrupt is generated if enabled) on the

falling edge of the ninth SCL pulse.

6. Receive low byte of address (bits SSPIF, BF and

UA are set).

7. Update the SSPADD register with the high byte

of address. If match releases SCL line, this will

clear bit UA.

8. Read the SSPBUF register (clears bit BF).

9. Clear flag bit SSPIF.

If data is requested by the master, once the slave has

been addressed:

1. Receive repeated Start condition.

2. Receive repeat of high byte address with R/W = 1,

indicating a read.

3. BF bit is set and the CKP bit is cleared, stopping

SCL and indicating a read request.

4. SSPBUF is written, setting BF, with the data to

send to the master device.

5. CKP is set in software, releasing the SCL line.

17.2.4.3

Address Masking

The Address Masking register (SSPMSK) is only

accessible while the SSPM bits of the SSPCON

register are set to ‘1001’. In this register, the user can

select which bits of a received address the hardware

will compare when determining an address match. Any

bit that is set to a zero in the SSPMSK register, the

corresponding bit in the received address byte and

SSPADD register are ignored when determining an

address match. By default, the register is set to all

ones, requiring a complete match of a 7-bit address or

the lower eight bits of a 10-bit address.

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17.2.5

RECEPTION

When the R/W bit of the received address byte is clear,

the master will write data to the slave. If an address

match occurs, the received address is loaded into the

SSPBUF register. An address byte overflow will occur

if that loaded address is not read from the SSPBUF

before the next complete byte is received.

An SSP interrupt is generated for each data transfer byte.

The BF, R/W and D/A bits of the SSPSTAT register are

used to determine the status of the last received byte.

FIGURE 17-10:

I²C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

R/W = 0

ACK

Receiving Address

A7 A6 A5 A4 A3 A2

Receiving Data

ACK

9

ACK

9

SDA

A1

7

D2 D1 D0

D4

D3

D7 D6 D5 D4 D3 D2 D1 D0

D7

1

D6 D5

1

2

3

4

5

6

8

9

1

2

3

4

5

6

7

8

2

3

4

5

6

7

8

P

SCL

S

SSPIF

Cleared in software

Bus Master

sends Stop

condition

BF

SSPBUF register is read

SSPOV

Bit SSPOV is set because the SSPBUF register is still full.

ACK is not sent.

DS40001430E-page 150

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FIGURE 17-11:

I²C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)

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DS40001430E-page 151

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Following the 8th falling clock edge, control of the SDA

line is released back to the master so that the master

can acknowledge or not acknowledge the response. If

the master sends a not acknowledge, the slave’s

transmission is complete and the slave must monitor for

the next Start condition. If the master acknowledges,

control of the bus is returned to the slave to transmit

another byte of data. Just as with the previous byte, the

clock is stretched by the slave, data must be loaded into

the SSPBUF and CKP must be set to release the clock

line (SCL).

17.2.6

TRANSMISSION

When the R/W bit of the received address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set and the slave will respond to

the master by reading out data. After the address match,

an ACK pulse is generated by the slave hardware and

the SCL pin is held low (clock is automatically stretched)

until the slave is ready to respond. See Section 17.2.7

“Clock Stretching”. The data the slave will transmit

must be loaded into the SSPBUF register, which sets

the BF bit. The SCL line is released by setting the CKP

bit of the SSPCON register.

An SSP interrupt is generated for each transferred data

byte. The SSPIF flag bit of the PIR1 register initiates an

SSP interrupt, and must be cleared by software before

the next byte is transmitted. The BF bit of the SSPSTAT

register is cleared on the falling edge of the 8th

received clock pulse. The SSPIF flag bit is set on the

falling edge of the ninth clock pulse.

FIGURE 17-12:

I²C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

Receiving Address

A7 A6 A5 A4 A3 A2 A1

R/W

Transmitting Data

ACK

9

SDA

SCL

ACK

D7 D6 D5 D4 D3 D2 D1 D0

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

S

P

SCL held low

while CPU

responds to SSPIF

Data in

sampled

Cleared in software

SSPIF

BF

Dummy read of SSPBUF

to clear BF flag

From SSP Interrupt

Service Routine

SSPBUF is written in software

CKP

Set bit after writing to SSPBUF

(the SSPBUF must be written to

before the CKP bit can be set)

DS40001430E-page 152

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2

FIGURE 17-13:

I C SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS)

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PIC16(L)F720/721

Refer to Application Note AN554, “Software

Implementation of I²C™ Bus Master” (DS00554) for more

information.

17.2.7

CLOCK STRETCHING

During any SCL low phase, any device on the I²C bus

may hold the SCL line low and delay, or pause, the

transmission of data. This “stretching” of a transmission

allows devices to slow down communication on the

bus. The SCL line must be constantly sampled by the

master to ensure that all devices on the bus have

released SCL for more data.

17.2.9

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allow the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I²C bus may be taken when the P bit of the

SSPSTAT register is set or when the bus is Idle, and

both the S and P bits are clear. When the bus is busy,

enabling the SSP Interrupt will generate the interrupt

when the Stop condition occurs.

Stretching usually occurs after an ACK bit of a

transmission, delaying the first bit of the next byte. The

SSP module hardware automatically stretches for two

conditions:

• After a 10-bit address byte is received (update

SSPADD register)

• Anytime the CKP bit of the SSPCON register is

cleared by hardware

In Multi-Master operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is expected and a low level

is present, the device needs to release the SDA and

SCL lines (set TRIS bits). There are two stages where

this arbitration of the bus can be lost. They are the

Address Transfer and Data Transfer stages.

The module will hold SCL low until the CKP bit is set.

This allows the user slave software to update SSPBUF

with data that may not be readily available. In 10-bit

addressing modes, the SSPADD register must be

updated after receiving the first and second address

bytes. The SSP module will hold the SCL line low until

the SSPADD has a byte written to it. The UA bit of the

SSPSTAT register will be set, along with SSPIF,

indicating an address update is needed.

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be

generated. If arbitration was lost during the data

transfer stage, the device will need to re-transfer the

data at a later time.

17.2.8

FIRMWARE MASTER MODE

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits of

the SSPSTAT register are cleared from a Reset or

when the SSP module is disabled (SSPEN cleared).

The Stop (P) and Start (S) bits will toggle based on the

Start and Stop conditions. Control of the I²C bus may

be taken when the P bit is set or the bus is Idle and both

the S and P bits are clear.

Refer to Application Note AN578, “Use of the SSP

Module in the I²C™ Multi-Master Environment”

(DS00578) for more information.

In Firmware Master mode, the SCL and SDA lines are

manipulated by setting/clearing the corresponding TRIS

bit(s). The output level is always low, irrespective of the

value(s) in the corresponding PORT register bit(s).

When transmitting a ‘1’, the TRIS bit must be set (input)

and a ‘0’, the TRIS bit must be clear (output).

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt will occur if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Firmware Master mode of operation can be done with

either the Slave mode Idle (SSPM<3:0> = 1011), or

with either of the Slave modes in which interrupts are

enabled. When both master and slave functionality is

enabled, the software needs to differentiate the

source(s) of the interrupt.

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17.2.10 CLOCK SYNCHRONIZATION

17.2.11 SLEEP OPERATION

When the CKP bit is cleared, the SCL output is held low

once it is sampled low. Therefore, the CKP bit will not

stretch the SCL line until an external I²C master device

has already asserted the SCL line low. The SCL output

will remain low until the CKP bit is set and all other

devices on the I²C bus have released SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (Figure 17-14).

While in Sleep mode, the I²C module can receive

addresses of data, and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if SSP interrupt is enabled).

FIGURE 17-14:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX-1

Master device

asserts clock

CKP

Master device

de-asserts clock

WR

SSPCON

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REGISTER 17-3: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I²C MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

WCOL: Write Collision Detect bit

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t

care” in Transmit mode. SSPOV must be cleared in software in either mode.

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

1= Enables the serial port and configures the SDA and SCL pins as serial port pins⁽²⁾

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

1= Release control of SCL

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

bit 3-0

SSPM<3:0>: Synchronous Serial Port mode Select bits

0110= I²C Slave mode, 7-bit address

0111= I²C Slave mode, 10-bit address

1000= Reserved

1001= Load SSPMSK register at SSPADD SFR Address⁽¹⁾

1010= Reserved

1011= I²C Firmware Controlled Master mode (Slave Idle)

1100= Reserved

1101= Reserved

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register.

2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.

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REGISTER 17-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I²C MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

SMP: SPI Data Input Sample Phase bit

1= Slew Rate Control (limiting) disabled. Operating in I²C Standard mode (100 kHz and 1 MHz).

0= Slew Rate Control (limiting) enabled. Operating in I²C Fast mode (400 kHz).

bit 6

bit 5

CKE: SPI Clock Edge Select bit

This bit must be maintained clear. Used in SPI mode only.

D/A: DATA/ADDRESS bit (I²C mode only)

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

bit 4

bit 3

bit 2

P: Stop bit

This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

S: Start bit

This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

R/W: READ/WRITE bit Information

This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or ACK bit.

1= Read

0= Write

bit 1

bit 0

UA: Update Address bit (10-bit I²C mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

Receive:

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Transmit:

1= Transmit in progress, SSPBUF is full

0= Transmit complete, SSPBUF is empty

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REGISTER 17-5: SSPMSK: SSP MASK REGISTER

R/W-1

MSK7

R/W-1

MSK6

R/W-1

MSK5

R/W-1

MSK4

R/W-1

MSK3

R/W-1

MSK2

R/W-1

MSK1

R/W-1

MSK0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

bit 0

MSK<7:1>: Mask bits

1= The received address bit n is compared to SSPADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK<0>: Mask bit for I²C Slave Mode, 10-bit Address

I²C Slave mode, 10-bit Address (SSPM<3:0> = 0111):

1= The received address bit ‘0’ is compared to SSPADD<0> to detect I²C address match

0= The received address bit ‘0’ is not used to detect I²C address match

All other SSP modes: this bit has no effect.

REGISTER 17-6: SSPADD: SSP I²C ADDRESS REGISTER

R/W-0

ADD7

R/W-0

ADD6

R/W-0

ADD5

R/W-0

ADD4

R/W-0

ADD3

R/W-0

ADD2

R/W-0

ADD1

R/W-0

ADD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADD<7:0>: Address bits

Received address

TABLE 17-3: REGISTERS ASSOCIATED WITH I²C OPERATION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE

PEIE

ADIF

ADIE

TMR0IE

RCIF

INTE

TXIF

TXIE

RABIE TMR0IF

SSPIF

SSPIE CCP1IE TMR2IE TMR1IE

INTF

RABIF

38

40

TMR1GIF

TMR1GIE

CCP1IF TMR2IF TMR1IF

PIE1

RCIE

39

SSPBUF

SSPADD

SSPCON

SSPMSK⁽²⁾

SSPSTAT

TRISB

Synchronous Serial Port Receive Buffer/Transmit Register

ADD<7:0>

139

158

156

158

145

55

WCOL

SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1

SSPM0

MSK<7:0>

P

SMP⁽¹⁾

CKE⁽¹⁾

D/A

S

R/W

—

UA

—

BF

—

TRISB7

TRISB6 TRISB5 TRISB4

—

Legend: x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by SSP

module in I²C mode.

Note 1: Maintain these bits clear in I²C mode.

2: Accessible only when SSPM<3:0> = 1001.

DS40001430E-page 158

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18.1 Program Memory Read Operation

18.0 FLASH PROGRAM MEMORY

SELF READ/SELF WRITE

CONTROL

To read a program memory location, the user must

write two bytes of the address to the PMADRH and

PMADRL registers, then set control bit RD

(PMCON1<0>). Once the read control bit is set, the

Program Memory Read (PMR) controller uses the two

instruction cycles to read the data. This causes the two

instructions immediately following the ‘BSF PMCON1,

RD’ instruction to be ignored.

The Flash Program Memory is readable and writable

during normal operation of the device. This memory is

not directly mapped in the register file space. Instead,

it is indirectly addressed through the Special Function

Registers. There are six SFRs used to read/write this

memory:

The data is available in the third cycle, following the set

of the RD bit, in the PMDATH and PMDATL registers.

PMDATL and PMDATH registers will hold this value

until another read is executed. See Example 18-1 and

Figure 18-1 for more information.

• PMCON1

• PMCON2

• PMDATL

• PMDATH

• PMADRL

• PMADRH

Note:

Interrupts must be disabled during the

time from setting PMCON1<0> (RD) to

the third instruction thereafter.

When interfacing the program memory block, the

PMDATL and PMDATH registers form a two byte word

which holds the 14-bit program data for reading, and

the PMADRL and PMADRH registers form a two byte

word which holds the 13-bit address of the program

Flash location being accessed. These devices have 2K

to 4K words of program memory with an address range

from 0000h to 0FFFh.

Devices without a full map of memory will shadow

accesses to unused blocks back to the implemented

memory.

EXAMPLE 18-1:

FLASH PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI: PROG_ADDR_LO

*

data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL PMADRL

; Select Bank 2

MOVLW

MOVWF

MOVLW

MOVWL

PROG_ADDR_LO

PMADRL

PROG_ADDR_HI

PMADRH

;

; Store LSB of address

;

; Store MSB of address

BANKSEL PMCON1

; Select Bank 3

BCF

BSF

NOP

BSF

INTCON,GIE

PMCON1,RD

; Disable interrupts

; Initiate read

; Ignored (Figure 18-1)

; Restore interrupts

INTCON,GIE

BANKSEL PMDATL

; Select Bank 2

MOVF

PMDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

PMDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

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FIGURE 18-1:

FLASH PROGRAM MEMORY READ CYCLE EXECUTION – NORMAL MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PMADRH, PMADRL

Flash ADDR

Flash DATA

PC

PC + 1

PC+3

PC + 4

PC + 5

INSTR (PC)

INSTR (PC + 1)

PMDATH, PMDATL

INSTR (PC + 3)

INSTR (PC + 4)

BSF PMCON1, RD

Executed here

INSTR (PC - 1)

Executed here

Forced NOP

Executed here

Forced NOP

Executed here

INSTR (PC + 3)

Executed here

INSTR (PC + 4)

Executed here

RD bit

PMDATH

PMDATL

Register

Force

NOP

Stop

PC

18.2 Code Protection

18.4 PMCON1 and PMCON2 Registers

When the device is code-protected, the CPU may

continue to read and write the Flash program memory.

Depending on the settings of the Flash program

memory enable (WRT<1:0>) bits, the device may or

may not be able to write certain blocks of the program

memory. However, reads of the program memory are

allowed.

PMCON1 is the control register for the data program

memory accesses.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, but only set

in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

premature termination of a write operation. Setting the

control bit WR initiates a write operation. For program

memory writes, WR initiates a write cycle if FREE = 0

and an erase cycle if FREE = 1.

When the Flash program memory Code Protection

(CP) bit in the Configuration Word register is enabled,

the program memory is code-protected, and the device

programmer (ICSP™) cannot access data or program

memory.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. PMCON2 is not a

physical register. Reading PMCON2 will read all ‘0’s.

The PMCON2 register is used exclusively in the Flash

memory write sequence.

Note:

Code-protect does not affect the CPU

from performing a read operation on the

program memory. For more information,

refer to Section 8.2 “Code Protection”.

18.3 PMADRH and PMADRL Registers

The PMADRH:PMADRL register pair can address up

to a maximum of 4K words of program Flash. The Most

Significant Byte (MSB) of the address is written to the

PMADRH register and the Least Significant Byte (LSB)

is written to the PMADRL register.

DS40001430E-page 160

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PIC16(L)F720/721

When the LWLO bit is ‘1’, the write sequence will only

load the buffer register and will not actually initiate the

write to program Flash:

18.5 Writing to Flash Program Memory

A word of the Flash program memory may only be

written to if the word is in an unprotected segment of

memory.

1. Set the WREN and LWLO bits of the PMCON1

register.

Flash program memory may only be written to if the

destination address is in a segment of memory that is

not write-protected, as defined in bits WRT<1:0> of the

Configuration Word Register 2. Flash program memory

must be written in 32-word rows. See Figure 18-2 for

more details. A row consists of 32 words with sequen-

tial addresses, with a lower boundary defined by an

address, where PMADR<4:0>= 00000. All row writes to

program memory are done as 32-word erase and one

to 32-word write operations. The write operation is

edge-aligned. Crossing boundaries is not recom-

mended, as the operation will only affect the new

boundary, wrapping the data values at the same time.

Once the write control bit is set, the Program Memory

(PM) controller will immediately write the data. Program

execution is stalled while the write is in progress.

2. Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

3. Set control bit WR of the PMCON1 register to

begin the write operation.

Note:

Self-write execution to Flash memory

cannot be done while running in low

power PFM and Voltage Regulator

modes. Therefore, executing a self-write

will put the PFM and voltage regulator into

High Power mode for the duration of the

sequence.

To transfer data from the buffer registers to the program

memory, the last word to be written should be written to

the PMDATH:PMDATL register pair. Then, the

following sequence of events must be executed:

To erase a program memory row, the address of the

row to erase must be loaded into the

PMADRH:PMADRL register pair. A row consists of 32

words so, when selecting a row, PMADR<4:0> are

ignored. After the Address has been set up, then the

following sequence of events must be executed:

1. Clear the LWLO bit of the PMCON1 Register.

2. Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

3. Set control bit WR of the PMCON1 register to

begin the write operation.

1. Set the WREN and FREE control bits of the

PMCON1 register.

4. Two NOPmust follow the setting of the WR bit.

2. Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

This is necessary to provide time for the address and to

be provided to the program Flash memory to be put in

the write latches.

3. Set the WR control bit of the PMCON1 register.

To write program data, it must first be loaded into the

buffer latches (see Figure 18-2). This is accomplished

by first writing the destination address to PMADRL and

PMADRH and then writing the data to PMDATA and

PMDATH. After the address and data have been set

up, then the following sequence of events must be

executed:

Note:

An ICD break that occurs during the 55h -

AAh – Set WR bit sequence will interrupt

the timing of the sequence and prevent

the unlock sequence from occurring. In

this case, no write will be initiated, as

there was no operation to complete.

1. Set the WREN control bit of the PMCON1

register.

No automatic erase occurs upon the initiation of the

write; if the program Flash needs to be erased before

writing, the row (32 words) must be previously erased.

2. Write 55h, then AAh, to PMCON2 (Flash

programming sequence).

3. Set the WR control bit of the PMCON1 register.

After the “BSF PMCON1, WR” instruction, the processor

requires two cycles to set up the erase/write operation.

All 32 buffer register locations should be written to with

correct data. If less than 32 words are being written to

in the block of 32 words, then a read from the program

memory location(s) not being written to must be

performed. This takes the data from the program

location(s) not being written and loads it into the

PMDATL and PMDATH registers. Then, the sequence

of events to transfer data to the buffer registers must be

executed.

The user must place two NOPinstructions after the WR

bit is set. These two instructions will also be forced in

hardware to NOP, but if an ICD break occurs at this

point, the forcing to NOPwill be lost.

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PIC16(L)F720/721

Since data is being written to buffer registers, the

writing of the first 31 words of the block appears to

occur immediately. The processor will halt internal

operations for the typical 2ms, only during the cycle in

which the erase takes place (i.e., the last word of the

32-word block erase). This is not Sleep mode as the

clocks and peripherals will continue to run. After the 32-

word write cycle, the processor will resume operation

with the third instruction after the PMCON1 write

instruction.

FIGURE 18-2:

BLOCK OF 32 WRITES TO FLASH PROGRAM MEMORY

7

5

0

0 7

PMDATH

6

PMDATL

8

14

PMADRL<4:0> = 00000

PMADRL<4:0> = 00001

PMADRL<4:0> = 00010

PMADRL<4:0> = 11111

Buffer Register

Program Memory

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PIC16(L)F720/721

18.6 Protection Against Spurious Write

18.7 Operation During Code-Protect

There are conditions when the device should not write

to the program memory. To protect against spurious

writes, various mechanisms have been built in. On

power-up, WREN is cleared. Also, the Power-up Timer

(64 ms duration) prevents program memory writes.

When the device is code-protected, the CPU is able to

read and write unscrambled data to the program

memory.

18.8 Operation During Write-Protect

The write initiates sequence and the WREN bit helps

prevent an accidental write during brown-out, power

glitch or software malfunction.

When the program memory is write-protected, the CPU

can read and execute from the program memory.

The portions of program memory that are

write-protected can be modified by the CPU using the

PMCON registers, but the protected program memory

cannot be modified using ICSP mode.

REGISTER 18-1: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-1

—

R/W-0/0

CFGS

R/W-0/0

LWLO

R/W/HC-0/0

FREE

U-0

—

R/W-0/0

WREN

R/S/HC-0/0 R/S/HC-0/0

WR RD

bit 7

bit 0

Legend:

S = Setable bit, cleared in hardware

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘1’

CFGS: Flash Program/Configuration Select bit

1= Accesses Configuration, user ID and device ID registers

0= Accesses Flash program

bit 5

bit 4

LWLO: Load Write Latches Only bit

1=

The next WR command does not initiate a write to the PFM; only the program memory

latches are updated.

0=

The next WR command writes a value from PMDATH:PMDATL into program memory latches

and initiates a write to the PFM of all the data stored in the program memory latches.

FREE: Program Flash Erase Enable bit

1=

Perform an program Flash erase operation on the next WR command (cleared by hardware

after completion of erase).

0=

Perform a program Flash write operation on the next WR command

bit 3

bit 2

Unimplemented: Read as ‘0’

WREN: Program/Erase Enable bit

1= Allows program/erase cycles

0= Inhibits programming/erasing of Program Flash

bit 1

bit 0

WR: Write Control bit

1= Initiates a program Flash program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

0= Program/erase operation to the Flash is complete and inactive

RD: Read Control bit

1= Initiates an program memory read (The RD is cleared in hardware; the RD bit can only be set

(not cleared) in software).

0= Does not initiate a program memory read

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PIC16(L)F720/721

REGISTER 18-2: PMDATH: PROGRAM MEMORY DATA HIGH REGISTER

U-0

—

U-0

—

R/W-x

PMD9

R/W-x

PMD8

PMD13

PMD12

PMD11

PMD10

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a

program memory read command.

REGISTER 18-3: PMDATL: PROGRAM MEMORY DATA LOW REGISTER

R/W-x

PMD7

R/W-x

PMD6

R/W-x

PMD5

R/W-x

PMD4

R/W-x

PMD3

R/W-x

PMD2

R/W-x

PMD1

R/W-x

PMD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a

program memory read command.

REGISTER 18-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

PMA9

R/W-x

PMA8

PMA12

PMA11

PMA10

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

PMA<12:8>: Program Memory Read Address bits

DS40001430E-page 164

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PIC16(L)F720/721

REGISTER 18-5: PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER

R/W-x

PMA7

R/W-x

PMA6

R/W-x

PMA5

R/W-x

PMA4

R/W-x

PMA3

R/W-x

PMA2

R/W-x

PMA1

R/W-x

PMA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

PMA<7:0>: Program Memory Read Address bits

TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PMCON1

PMCON2

PMADRH

PMADRL

PMDATH

PMDATL

—

CFGS

LWLO

FREE

—

WREN

WR

RD

163

—

Program Memory Control Register 2 (not a physical register)

—

Program Memory Read Address Register High Byte

164

165

164

Program Memory Read Address Register Low Byte

Program Memory Read Data Register High Byte

Program Memory Read Data Register Low Byte

Legend: x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used by the program

memory read.

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DS40001430E-page 165

PIC16(L)F720/721

NOTES:

DS40001430E-page 166

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

19.1 Wake-up from Sleep

19.0 POWER-DOWN MODE (SLEEP)

The device can wake-up from Sleep through one of the

following events:

The Power-down mode is entered by executing a

SLEEPinstruction.

1. External Reset input on MCLR pin.

If the Watchdog Timer is enabled:

2. Watchdog Timer wake-up (if WDT was

enabled).

• WDT will be cleared but keeps running.

• PD bit of the STATUS register is cleared.

• TO bit of the STATUS register is set.

• Oscillator driver is turned off.

3. Interrupt from RA2/INT pin, PORTB change or a

peripheral interrupt.

The first event will cause a device Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of a device Reset.

The PD bit, which is set on power-up, is cleared when

Sleep is invoked. TO bit is cleared if WDT wake-up

occurred.

• I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or high-

impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD or VSS, with no external

circuitry drawing current from the I/O pin. I/O pins that

are high-impedance inputs should be pulled high or low

externally to avoid switching currents caused by float-

ing inputs. The T0CKI input should also be at VDD or

VSS for lowest current consumption. The contribution

from on-chip pull-ups on PORTB should be considered.

The following peripheral interrupts can wake the device

from Sleep:

1. TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

2. USART Receive Interrupt (Synchronous Slave

mode only)

The MCLR pin must be at a logic high level when

external MCLR is enabled.

3. A/D conversion (when A/D clock source is RC)

4. Interrupt-on-change

Note:

A Reset generated by a WDT time-out

does not drive MCLR pin low.

5. External interrupt from INT pin

6. Capture event on CCP1

7. SSP interrupt in SPI or I²C Slave mode

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEPinstruction is completely executed.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

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PIC16(L)F720/721

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

19.2 Wake-up Using Interrupts

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will

complete as a NOP. Therefore, the WDT and WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

To ensure that the WDT is cleared, a CLRWDTinstruction

should be executed before a SLEEPinstruction.

• If the interrupt occurs during or after the

execution of a SLEEPinstruction, the device will

immediately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT prescaler

and postscaler (if enabled) will be cleared, the TO

bit will be set and the PD bit will be cleared.

FIGURE 19-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Oscillator

CLKOUT⁽²⁾

INT pin

INTF flag

(INTCON reg.)

Interrupt Latency⁽¹⁾

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Dummy Cycle

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

2:

GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

CLKOUT is not available in EC Oscillator mode, but shown here for timing reference.

TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IOCB

INTCON

PIE1

IOCB7

GIE

IOCB6

PEIE

ADIE

ADIF

IOCB5

TMR0IE

RCIE

IOCB4

INTE

TXIE

TXIF

—

56

38

39

40

RABIE

SSPIE

SSPIF

TMR0IF

INTF

RABIF

TMR1GIE

TMR1GIF

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIR1

RCIF

Legend: x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used in Power-Down

mode.

DS40001430E-page 168

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

The device is placed into Program/Verify mode by

holding the ICSPCLK and ICSPDAT pins low then

raising the voltage on MCLR/VPP from 0V to VPP. In

Program/Verify mode the program memory, user IDs and

the Configuration Words are programmed through serial

communications. The ICSPDAT pin is a bidirectional I/O

used for transferring the serial data and the ISCPCLK pin

is the clock input. For more information on ICSP™ refer

20.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process, allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP™

programming:

to

the

“PIC16F72x/PIC16LF72x

Programming

Specification” (DS41332).

• ICSPCLK

• ICSPDAT

• MCLR/VPP

• VDD

• VSS

FIGURE 20-1:

TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

External

Programming

Signals

Device to be

Programmed

VDD

10k

VPP

MCLR/VPP

VSS

GND

Data

ICSPDAT

ICSPCLK

Clock

*

To Normal Connections

Isolation devices (as required).

*

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DS40001430E-page 169

PIC16(L)F720/721

NOTES:

DS40001430E-page 170

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PIC16(L)F720/721

21.0 INSTRUCTION SET SUMMARY

TABLE 21-1: OPCODE FIELD

DESCRIPTIONS

The PIC16(L)F720/721 instruction set is highly

orthogonal and is comprised of three basic categories:

Field

Description

• Byte-oriented operations

• Bit-oriented operations

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

• Literal and control operations

Bit address within an 8-bit file register

Literal field, constant data or label

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 21-1, while the various opcode

fields are summarized in Table 21-1.

k

x

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

Table 21-2 lists the instructions recognized by the

MPASM^TMassembler.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

PC

TO

C

Program Counter

Time-out bit

Carry bit

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

DC

Z

Digit carry bit

Zero bit

PD

Power-down bit

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

FIGURE 21-1:

GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13

For literal and control operations, ‘k’ represents an 8-

bit or 11-bit constant, or literal value.

8

7

6

0

OPCODE

d

f (FILE #)

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a

nominal instruction execution time of 1 s. All

instructions are executed within a single instruction

cycle, unless a conditional test is true, or the program

counter is changed as a result of an instruction. When

this occurs, the execution takes two instruction cycles,

with the second cycle executed as a NOP.

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9

b (BIT #)

7

6

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

Literal and control operations

General

21.1 Read-Modify-Write Operations

13

8

7

0

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

OPCODE

k (literal)

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

k (literal)

For example, a CLRF PORTB instruction will read

PORTB, clear all the data bits, then write the result

back to PORTB. This example would have the unin-

tended consequence of clearing the condition that set

the RABIF flag.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 171

PIC16(L)F720/721

TABLE 21-2: PIC16(L)F720/721 INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Description

Operands

Status

Affected

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C, DC, Z

1, 2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

DECFSZ

INCF

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

Z

Move W to f

No Operation

–

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1, 2

00 0010 dfff ffff C, DC, Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1, 2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

–

k

–

k

–

k

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C, DC, Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

00 0000 0110 0100 TO, PD

10 1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

00 0000 0110 0011 TO, PD

11 110x kkkk kkkk C, DC, Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

DS40001430E-page 172

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21.2 Instruction Descriptions

BCF

Bit Clear f

ADDLW

Add literal and W

Syntax:

[ label ] BCF f,b

Syntax:

[ label ] ADDLW

0  k  255

k

Operands:

0  f  127

0  b  7

Operands:

Operation:

Status Affected:

Description:

(W) + k  (W)

C, DC, Z

Operation:

0 (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the

W register.

Bit ‘b’ in register ‘f’ is cleared.

BSF

Bit Set f

ADDWF

Add W and f

Syntax:

[ label ] BSF f,b

Syntax:

[ label ] ADDWF f,d

Operands:

0  f  127

0  b  7

Operands:

0  f  127

d 0,1

Operation:

1 (f<b>)

Operation:

(W) + (f)  (destination)

Status Affected:

Description:

None

Status Affected: C, DC, Z

Bit ‘b’ in register ‘f’ is set.

Description:

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC

Bit Test f, Skip if Clear

ANDLW

AND literal with W

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDLW

0  k  255

k

Operands:

0  f  127

0  b  7

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k)  (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’ in register ‘f’ is ‘0’ the next

instruction is discarded and a NOP

is executed instead, making this a

2-cycle instruction.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f,d

Operands:

0  f  127

d 0,1

Operation:

(W) .AND. (f)  (destination)

Status Affected:

Description:

Z

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

 2010-2013 Microchip Technology Inc.

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CLRWDT

Clear Watchdog Timer

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRWDT

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

None

Operands:

0  f  127

0  b < 7

00h  WDT

0 WDT prescaler,

1 TO

Operation:

skip if (f<b>) = 1

Status Affected: None

1 PD

Description:

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

Status Affected: TO, PD

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP

is executed instead, making this a

2-cycle instruction.

Status bits TO and PD are set.

CALL

Call Subroutine

COMF

Complement f

Syntax:

[ label ] CALL

0  k  2047

k

Syntax:

[ label ] COMF f,d

Operands:

Operation:

Operands:

0  f  127

d  [0,1]

(PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

Operation:

(f)  (destination)

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

CLRF

Clear f

DECF

Decrement f

Syntax:

[ label ] CLRF

0  f  127

f

Syntax:

[ label ] DECF f,d

Operands:

Operation:

Operands:

0  f  127

d  [0,1]

00h  (f)

1 Z

Operation:

(f) - 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h  (W)

1 Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

DS40001430E-page 174

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DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - 1  (destination);

skip if result = 0

Operation:

(f) + 1  (destination),

skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then a NOPis

executed instead, making it a

2-cycle instruction.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOPis executed

instead, making it a 2-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO k

0  k  2047

Syntax:

[ label ] IORLW k

0  k  255

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k  PC<10:0>

PCLATH<4:3>  PC<12:11>

(W) .OR. k  (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a

two-cycle instruction.

IORWF

Inclusive OR W with f

INCF

Increment f

Syntax:

[ label ] IORWF f,d

Syntax:

[ label ] INCF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(W) .OR. (f)  (destination)

Operation:

(f) + 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

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MOVWF

Move W to f

[ label ] MOVWF

0  f  127

(W)  (f)

MOVF

Move f

Syntax:

f

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

Operation:

Status Affected:

Description:

0  f  127

d  [0,1]

Operation:

(f)  (dest)

None

Status Affected:

Description:

Z

Move data from W register to

register ‘f’.

The contents of register f is

moved to a destination dependent

upon the status of d. If d = 0,

destination is W register. If d = 1,

the destination is file register f

itself. d = 1is useful to test a file

register since status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVW

F

OPTION

Before Instruction

OPTION = 0xFF

Words:

1

W

=

0x4F

After Instruction

Cycles:

Example:

OPTION = 0x4F

W

MOVF

FSR, 0

=

0x4F

After Instruction

W

=

value in FSR

register

Z

=

1

MOVLW

Syntax:

Move literal to W

NOP

No Operation

[ label ] MOVLW k

0  k  255

Syntax:

[ label ] NOP

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

Words:

None

k  (W)

No operation

Status Affected: None

None

Description:

The eight-bit literal ‘k’ is loaded into

W register. The “don’t cares” will

assemble as ‘0’s.

No operation.

1

Cycles:

1

Words:

1

NOP

Example:

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

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RETFIE

Return from Interrupt

[ label ] RETFIE

None

RETLW

Return with literal in W

Syntax:

[ label ] RETLW k

Operands:

Operation:

Operands:

Operation:

0  k  255

TOS  PC,

1 GIE

k  (W);

TOS  PC

Status Affected:

Description:

None

Status Affected:

Description:

None

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE

The W register is loaded with the

eight bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

(INTCON<7>). This is a two-cycle

instruction.

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains

table

Cycles:

Example:

2

RETFIE

;offset value

•

;W now has table value

TABLE

After Interrupt

PC = TOS

GIE =

1

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2

;

•

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS  PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

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RLF

Rotate Left f through Carry

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

0  f  127

d  [0,1]

Operands:

Operation:

00h  WDT,

0 WDT prescaler,

1 TO,

Operation:

See description below

C

Status Affected:

Description:

0 PD

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

C

Register f

Words:

1

Cycles:

Example:

RLF

REG1,0

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW k

0 k 255

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Operands:

0  f  127

d  [0,1]

k - (W) W)

Operation:

See description below

C

Status Affected: C, DC, Z

Status Affected:

Description:

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

C = 0

W  k

C = 1

W  k

DC = 0

DC = 1

W<3:0>  k<3:0>

W<3:0>  k<3:0>

C

Register f

DS40001430E-page 178

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SUBWF

Subtract W from f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SUBWF f,d

Syntax:

[ label ] XORLW k

Operands:

0 f 127

d  [0,1]

Operands:

0 k 255

Operation:

(W) .XOR. k W)

Operation:

(f) - (W) destination)

Status Affected:

Description:

Z

Status Affected: C, DC, Z

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

Description:

Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f.

C = 0

W  f

C = 1

W  f

DC = 0

DC = 1

W<3:0>  f<3:0>

W<3:0>  f<3:0>

SWAPF

Swap Nibbles in f

XORWF

Exclusive OR W with f

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORWF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Operation:

(W) .XOR. (f) destination)

Status Affected:

Description:

Z

Status Affected: None

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

 2010-2013 Microchip Technology Inc.

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NOTES:

DS40001430E-page 180

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PIC16(L)F720/721

22.1 MPLAB Integrated Development

Environment Software

22.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers and dsPIC^®digital signal

controllers are supported with a full range of software

and hardware development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• A single graphical interface to all debugging tools

- Simulator

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- Programmer (sold separately)

- HI-TECH C^®for Various Device Families

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Customizable data windows with direct edit of

contents

• Simulators

• High-level source code debugging

• Mouse over variable inspection

- MPLAB SIM Software Simulator

• Emulators

• Drag and drop variables from source to watch

windows

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 181

PIC16(L)F720/721

22.2 MPLAB C Compilers for Various

Device Families

22.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

22.3 HI-TECH C for Various Device

Families

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

22.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

22.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• MPLAB IDE compatibility

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

DS40001430E-page 182

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PIC16(L)F720/721

22.7 MPLAB SIM Software Simulator

22.9 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC^®Flash microcon-

trollers and dsPIC^®DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

22.10 PICkit 3 In-Circuit Debugger/

Programmer and

22.8 MPLAB REAL ICE In-Circuit

Emulator System

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC^®and dsPIC^®Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 183

PIC16(L)F720/721

22.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

22.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows^®programming interface supports baseline

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

(PIC10F,

PIC12F5xx,

PIC16F5xx),

midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Development Environment (IDE) the PICkit™

2

enables in-circuit debugging on most PIC^®microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

22.12 MPLAB PM3 Device Programmer

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS40001430E-page 184

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

23.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS, PIC16F720/721 ........................................................................ -0.3V to +6.5V

Voltage on VDD with respect to VSS, PIC16LF720/721 ...................................................................... -0.3V to +4.0V

Voltage on MCLR with respect to VSS ................................................................................................. -0.3V to +9.0V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾...............................................................................................................................800 mW

Maximum current out of VSS pin ...................................................................................................................... 95 mA

Maximum current into VDD pin ......................................................................................................................... 70 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sunk by all ports, -40°C  TA  +85°C for industrial............................................................ 200 mA

Maximum current sunk by all ports, -40°C  TA  +125°C for extended ........................................................... 90 mA

Maximum current sourced by all ports, 40°C  TA  +85°C for industrial....................................................... 140 mA

Maximum current sourced by all ports, -40°C  TA  +125°C for extended...................................................... 65 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 185

PIC16(L)F720/721

23.1 DC Characteristics: PIC16(L)F720/721-I/E (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

PIC16LF720/721

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F720/721

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param.

No.

Sym.

Characteristic

Supply Voltage

Min.

Typ† Max. Units

Conditions

D001

VDD

PIC16LF720/721

1.8

—

3.6

5.5

V

FOSC  16 MHz: HFINTOSC, EC

D001

PIC16F720/721

V

(1)

D002*

VDR

RAM Data Retention Voltage

PIC16LF720/721

1.5

1.7

—

V

Device in Sleep mode

D002*

PIC16F720/721

VPOR*

Power-on Reset Release Voltage

1.6

VPORR* Power-on Reset Rearm Voltage

PIC16LF720/721

—

-8

0.9

1.5

—

6

V

PIC16F720/721

D003

VFVR

SVDD

Fixed Voltage Reference Voltage,

Initial Accuracy

%

VFVR = 1.024V, VDD  2.5V

VFVR = 2.048V, VDD  2.5V

VFVR = 4.096V, VDD 4.75V;

D004*

VDD Rise Rate to ensure internal

0.05

—

V/ms See Section 3.2 “Power-on Reset

(POR)” for details.

Power-on Reset signal

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

DS40001430E-page 186

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 23-1:

POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR

POR REARM

VSS

(3)

(2)

TPOR

TVLOW

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 187

PIC16(L)F720/721

23.2 DC Characteristics: PIC16(L)F720/721-I/E (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

PIC16LF720/721

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F720/721

Param.

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Device

Min.

Typ†

Max.

Units

No.

Characteristics

VDD

Note

(1, 2)

Supply Current (IDD)

D013

—

100

210

120

220

250

220

420

250

450

500

105

130

120

145

160

600

1000

610

1010

1150

900

1450

910

1460

1700

180

270

A

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

FOSC = 1 MHz

EC mode

205

FOSC = 1 MHz

EC mode

320

410

D014

330

FOSC = 4 MHz

EC mode

500

430

FOSC = 4 MHz

EC mode

655

730

D015

203

FOSC = 500 kHz

MFINTOSC mode

235

219

FOSC = 500 kHz

MFINTOSC mode

284

348

D016

800

FOSC = 8 MHz

HFINTOSC mode

1200

850

FOSC = 8 MHz

HFINTOSC mode

1200

1500

1200

1850

1200

1900

2100

D017

FOSC = 16 MHz

HFINTOSC mode

FOSC = 16 MHz

HFINTOSC mode

Note 1: The test conditions for all IDD measurements in active EC Mode are: CLKIN = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

DS40001430E-page 188

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

23.3 DC Characteristics: PIC16(L)F720/721-I/E (Power-Down)

Standard Operating Conditions (unless otherwise stated)

PIC16LF720/721

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F720/721

Param.

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Note

Max.

Device Characteristics

Min.

Typ†

Units

No.

+85°C +125°C

VDD

(2)

Power-down Base Current (IPD)

D020

—

0.04

0.05

18

1

2

8

9

A

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

Base IPD

D020

47

58

60

4

55

72

84

9

20

23

D021

0.5

0.8

20

IPD LPWDT on (Note 1)

5

11

49

60

63

29

31

77

98

160

—

57

74

86

35

38

90

108

170

—

22

25

D021A

14

IPD FVR on (Note 1)

15

39

46

91

D022

—

IPD BOR on (Note 1)

7

15

—

26

—

26

64

67

4

78

91

10

11

29

D027

1.5

2

IPD ADC on (Note 1, Note 3)

non-convert

5

19

48

59

62

400

420

430

450

470

57

74

87

410

430

440

460

480

IPD ADC on (Note 1, Note 3)

non-convert

21

24

D027A

250

260

280

300

320

IPD ADC on (Note 1, Note 3)

convert

IPD ADC on (Note 1, Note 3)

convert

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: A/D oscillator source is FRC.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 189

PIC16(L)F720/721

23.4 DC Characteristics: PIC16(L)F720/721-I/E

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O PORT:

D030

D030A

D031

with TTL buffer

—

0.8

V

4.5V  VDD  5.5V

0.15 VDD

0.2 VDD

0.3 VDD

1.8V  VDD  4.5V

2.0V  VDD  5.5V

with Schmitt Trigger buffer

2

with I C™ levels

VIH

Input High Voltage

I/O ports:

—

D040

with TTL buffer

2.0

V

4.5V  VDD 5.5V

1.8V  VDD  4.5V

D040A

0.25 VDD +

0.8

D041

D042

D060

with Schmitt Trigger buffer

0.8 VDD

0.7 VDD

0.8 VDD

—

V

2.0V  VDD  5.5V

2

with I C™ levels

MCLR

(1)

IIL

Input Leakage Current

I/O ports

—

± 5

± 125

nA

VSS  VPIN  VDD, Pin at high-

impedance, 85°C

125°C

± 5

± 1000

± 200

nA

(2)

D061

MCLR

± 50

VSS  VPIN  VDD, 85°C

IPUR

VOL

PORTB Weak Pull-up Current

D070*

25

100

140

200

300

VDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS

A

Output Low Voltage

D080

I/O ports

IOL = 8mA, VDD = 5V

IOL = 6mA, VDD = 3.3V

IOL = 1.8mA, VDD = 1.8V

—

0.6

—

V

VOH

Output High Voltage

D090

I/O ports

IOH = 3.5mA, VDD = 5V

IOH = 3mA, VDD = 3.3V

IOH = 1mA, VDD = 1.8V

VDD - 0.7

V

CIO

EP

Capacitive Loading Specs on Output Pins

D101A*

All I/O pins

—

50

—

pF

Program Flash Memory

Cell Endurance

D130

D131

1k

10k

E/W Temperature during programming:

10°C  TA  40°C

VPR

VDD for Read

VMIN

8.0

—

V

Temperature during programming:

10°C  TA  40°C

VIHH

Voltage on MCLR/VPP during

Erase/Program

9.0

V

D132

VPEW

VDD for Write or Row Erase

1.8

—

5.5

3.6

V

PIC16F720/721

PIC16LF720/721

Temperature during programming:

10°C  TA  40°C

IPPPGM* Current on MCLR/VPP during

Erase/Write

—

1.0

—

mA

IDDPGM* Current on VDD during Erase/

Write

—

5.0

Temperature during programming:

10°C  TA  40°C

—

mA

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Negative current is defined as current sourced by the pin.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

DS40001430E-page 190

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

23.4 DC Characteristics: PIC16(L)F720/721-I/E (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

D133

D134*

D135

TPEW

Erase/Write cycle time

Characteristic Retention

High-Endurance Flash Cell

—

2.8

ms Temperature during programming:

10°C  TA  40°C

TRETD

EHEFC

—

40

—

Year Provided no other specifications

are violated

100K

E/W 0°C to +60°C

Lower byte,

Last 128 Addresses in Flash

memory

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Negative current is defined as current sourced by the pin.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 191

PIC16(L)F720/721

23.5 Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Operating temperature-40°C  TA  +125°C

Param.

No.

Sym.

Characteristic

Typ.

Units

Conditions

TH01

^JA

Thermal Resistance Junction to

Ambient

62.2

75.0

89.3

43.0

27.5

23.1

31.1

5.3

C/W 20-pin PDIP package

C/W 20-pin SOIC package

C/W 20-pin SSOP package

C/W 20-pin QFN 4x4mm package

C/W 20-pin PDIP package

C/W 20-pin SOIC package

C/W 20-pin SSOP package

C/W 20-pin QFN 4x4mm package

C

TH02

^JC

Thermal Resistance Junction to

Case

TH03

TH04

TH05

TH06

TJMAX

PD

Maximum Junction Temperature

Power Dissipation

150

—

W

PD = PINTERNAL + PI/O

PINTERNAL = IDD x VDD

(1)

PINTERNAL Internal Power Dissipation

—

PI/O

I/O Power Dissipation

—

PI/O =  (IOL * VOL) +  (IOH * (VDD -

VOH))

(2)

TH07

PDER

Derated Power

—

W

PDER = PDMAX (TJ - TA)/JA

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature; TJ = Junction Temperature

DS40001430E-page 192

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

23.6

Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

CLKIN

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O PORT

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 23-2:

LOAD CONDITIONS

Load Condition

CL

VSS

Legend: CL = 50 pF for all pins

 2010-2013 Microchip Technology Inc.

DS40001430E-page 193

PIC16(L)F720/721

23.7 AC Characteristics: PIC16F720/721-I/E

FIGURE 23-3:

PIC16F720/721 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

5.5

1.8

16

0

8

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

FIGURE 23-4:

PIC16LF720/721 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

3.6

1.8

16

0

8

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

DS40001430E-page 194

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 23-5:

HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

± 5%

85

60

25

0

± 3%

± 2%

± 5%

-40

1.8

2.0

2.5

3.5

4.0

VDD (V)

4.5

5.0

5.5

3.0

 2010-2013 Microchip Technology Inc.

DS40001430E-page 195

PIC16(L)F720/721

FIGURE 23-6:

CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

CLKIN

OS02

OS03

CLKOUT

TABLE 23-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param.

Sym.

No.

Characteristic

Min.

Typ†

Max.

Units

Conditions

(1)

DC

—

16

MHz EC Oscillator mode

OS01

OS02

OS03

FOSC

TOSC

TCY

External CLKIN Frequency

(1)

External CLKIN Period

63

—



ns

EC Oscillator mode

TCY = 4/FOSC

(1)

Instruction Cycle Time

250

TCY

DC

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

DS40001430E-page 196

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TABLE 23-2:

OSCILLATOR PARAMETERS⁽¹⁾

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No.

Freq.

Tolerance

Sym

Characteristic

Min. Typ† Max. Units

Conditions

OS08

HFOSC

Internal Calibrated HFINTOSC

Frequency^{(2, 3)}

2%

—

16.0

—

MHz 0°C  TA  +60°C,

VDD 2.5V

3%

MHz +60°C  TA  +85°C,

VDD 2.5V

5%

2%

—

16.0

500

—

MHz -40°C  TA  +125°C

MFOSC

Internal Calibrated MFINTOSC

Frequency^{(2, 3)}

kHz 0°C  TA  +60°C,

VDD 2.5V

3%

—

500

—

kHz +60°C  TA  +85°C,

VDD 2.5V

5%

—

500

5

—

8

kHz -40°C  TA  +125°C

s

OS10* TIOSC ST HFINTOSC 16 MHz and

MFINTOSC 500 kHz

—

Oscillator Wake-up from Sleep

Start-up Time

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption. All devices are tested to

operate at “min” values with an external clock applied to the CLKIN pin. When an external clock input is

used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 F and 0.01 F values in parallel are recommended.

3: The frequency tolerance of the internal oscillator is ±2% from 0-60°C and ±3% from 60-85°C

(see Figure 23-5).

 2010-2013 Microchip Technology Inc.

DS40001430E-page 197

PIC16(L)F720/721

FIGURE 23-7:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

FOSC

OS12

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS18

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

TABLE 23-3: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No.

Sym.

Characteristic

Min.

Typ† Max. Units Conditions

OS11*

OS12*

OS13*

TOSH2CKL FOSC to CLKOUT ⁽¹⁾

TOSH2CKH FOSC to CLKOUT ⁽¹⁾

—

70

72

20

ns VDD = 3.3-5.0V

ns

TCKL2IOV

CLKOUT to Port out valid⁽¹⁾

OS14*

OS15*

OS16*

TIOV2CKH Port input valid before CLKOUT⁽¹⁾

TOSH2IOV FOSC (Q1 cycle) to Port out valid

TOSC + 200 ns

—

50

—

70*

—

ns

—

ns VDD = 3.3-5.0V

TOSH2IOI

FOSC (Q2 cycle) to Port input invalid

50

(I/O in hold time)

OS17*

OS18*

OS19*

TIOV2OSH Port input valid to FOSC(Q2 cycle)

20

—

ns

(I/O in setup time)

TIOR

TIOF

Port output rise time

—

15

40

32

72

ns

VDD = 2.0V

VDD = 3.3-5.0V

Port output fall time

—

28

15

55

30

VDD = 2.0V

VDD = 3.3-5.0V

OS20*

OS21*

TINP

INT pin input high or low time

25

—

ns

TRBP

PORTB interrupt-on-change new input

level time

TCY

*

†

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC.

DS40001430E-page 198

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 23-8:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR + VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

TBORDC

Reset

(due to BOR)

(1)

TPWRT

Note 1: The additional delay of TPWRT, prior to releasing Reset, only occurs when the Power-up Timer is enabled (PWRTE = 0).

 2010-2013 Microchip Technology Inc.

DS40001430E-page 199

PIC16(L)F720/721

TABLE 23-4: RESET, WATCHDOG TIME, POWER-UP TIMER, AND BROWN-OUT RESET

PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No.

Sym.

TMCL

TWDT

Characteristic

Min. Typ† Max. Units

Conditions

30*

MCLR Pulse Width (low)

2

5

—

s VDD = 5V, -40°C to +85°C

s VDD = 5V⁽¹⁾

31

Standard Watchdog Timer Time-out

Period (No Prescaler)⁽²⁾

10

18

27

33

ms VDD = 3.3V-5V, -40°C to +85°C

ms VDD = 3.3V-5V⁽¹⁾

33*

34*

TPWRT Power-up Timer Period, PWRTE = 0

40

—

65

—

140

2.0

ms

TIOZ

I/O high-impedance from MCLR Low

or Watchdog Timer Reset

s

35

VBOR

Brown-out Reset Voltage

1.80

0

1.9

25

3

2.1

50

V

36*

37*

VHYST

Brown-out Reset Hysteresis

mV

TBORDC Brown-out Reset DC Response

Time

1

5

10

s VDD  VBOR, -40°C to +85°C

VDD  VBOR

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: Voltages above 3.6V require that the regulator be enabled.

2: Design Target. If unable to meet this target, the maximum can be increased, but the minimum cannot be

changed.

FIGURE 23-9:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

DS40001430E-page 200

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TABLE 23-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No.

Sym.

TT0H

Characteristic

Min.

Typ† Max. Units

Conditions

40*

T0CKI High Pulse

No

0.5 TCY + 20

—

ns

Width

Prescaler

With

Prescaler

10

0.5 TCY + 20

10

41*

TT0L

T0CKI Low Pulse

Width

No

Prescaler

With

Prescaler

42*

45*

TT0P

TT1H

T0CKI Period

Greater of:

20 or TCY + 40

N

N = prescale value

(2, 4, ..., 256)

T1CKI

High

Time

Synchronous, No

Prescaler

0.5 TCY + 20

—

ns

Synchronous, with

Prescaler

15

Asynchronous

30

—

ns

46*

TT1L

TT1P

T1CKI

Low Time Prescaler

Synchronous, No

0.5 TCY + 20

Synchronous, with

Prescaler

15

30

—

ns

Asynchronous

Synchronous

—

ns

47*

49*

T1CKI

Input

Period

Greater of:

30 or TCY + 40

N

N = prescale value

(1, 2, 4, 8)

Asynchronous

60

—

ns

—

TCKEZ Delay from External Clock Edge to

Timer Increment

These parameters are characterized but not tested.

2 TOSC

7 TOSC

Timers in Sync

mode

TMR1

*

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

FIGURE 23-10:

CAPTURE/COMPARE/PWM TIMINGS (CCP)

CCP

(Capture mode)

CC01

CC02

CC03

Note: Refer to Figure 23-2 for load conditions.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 201

PIC16(L)F720/721

TABLE 23-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C  TA  +125°C

Param.

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

CC01* TccL CCP Input Low Time

CC02* TccH CCP Input High Time

CC03* TccP CCP Input Period

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

—

ns

20

0.5TCY + 20

20

3TCY + 40

N

N = prescale value (1, 4 or 16)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

TABLE 23-7: PIC16F720/721 A/D CONVERTER (ADC) CHARACTERISTICS

Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA 25°C

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD01

AD02

AD03

NR

Resolution

—

8

bit

EIL

EDL

Integral Error

±1.7

±1

LSb VDD = 3.0V

Differential Error

LSb No missing codes

VDD = 3.0V

AD04

AD07

AD08*

EOFF Offset Error

EGN Gain Error

—

±2.2

±1.5

VDD

10

LSb VDD = 3.0V

VAIN Full-Scale Range

VSS

—

V

ZAIN Recommended Impedance of

Analog Voltage Source

k

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS40001430E-page 202

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TABLE 23-8: PIC16F720/721 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param.

Sym.

No.

Characteristic

Min.

Typ†

Max. Units

Conditions

(2)

AD130* TAD

A/D Clock Period

1.0

4.0

—

9.0

S

VDD  2.0V

VDD  2.0V

16.0

A/D Internal RC Oscillator

Period

(ADRC mode)

1.0

—

2.0

6.0

—

S

AD131 TCNV Conversion Time (not including

10.5

TAD Set GO/DONE bit to new data in A/D

Result register

(1)

Acquisition Time)

AD132* TACQ Acquisition Time

2

—

S

VDD = 3.0V, EC or INTOSC Clock

mode

(3)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The ADRES register may be read on the following TCY cycle.

2: Setting of 16.0 s TAD not recommended for temperature > 85°C.

3: If ADRC mode is selected for use with VDD 2.0V, longer acquisition times will be required (see Section 9.3 “A/D

Acquisition Requirements”)

FIGURE 23-11:

PIC16F720/721 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

AD134

Q4

1 TCY

(1)

(TOSC/2

)

AD131

AD130

A/D CLK

7

6

5

4

3

2

1

0

A/D Data

ADRES

NEW_DATA

1 TCY

OLD_DATA

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 203

PIC16(L)F720/721

FIGURE 23-12:

PIC16F720/721 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

AD134

Q4

(1)

(TOSC/2 + TCY

1 TCY

)

AD131

AD130

A/D CLK

A/D Data

7

6

5

3

2

1

0

4

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

FIGURE 23-13:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK

DT

US121

US122

US120

Refer to Figure 23-2 for load conditions.

Note:

TABLE 23-9: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param.

Symbol

No.

Characteristic

Min.

Max.

Units Conditions

US120* TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

—

80

100

45

ns

US121* TCKRF

Clock out rise time and fall time

(Master mode)

50

US122* TDTRF

Data-out rise time and fall time

45

50

*

These parameters are characterized but not tested.

DS40001430E-page 204

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 23-14:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK

DT

US125

US126

Note: Refer to Figure 23-2 for load conditions.

TABLE 23-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param.

Symbol

No.

Characteristic

Min.

Max. Units

Conditions

US125* TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK  (DT hold time)

10

15

—

ns

US126* TCKL2DTL Data-hold after CK  (DT hold time)

*

These parameters are characterized but not tested.

FIGURE 23-15:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

SP70

SCK

(CKP = 0)

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

LSb In

SP74

SP73

Note 1: Refer to Figure 23-2 for load conditions.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 205

PIC16(L)F720/721

FIGURE 23-16:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81

SCK

(CKP = 0)

SP71

SP73

SP72

SP79

SP78

SCK

(CKP = 1)

SP80

bit 6 - - - - - -1

LSb

MSb

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note 1: Refer to Figure 23-2 for load conditions.

FIGURE 23-17:

SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK

(CKP = 0)

SP83

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP79

SP80

MSb

SDO

SDI

bit 6 - - - - - -1

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

SP73

LSb In

Note 1: Refer to Figure 23-2 for load conditions.

DS40001430E-page 206

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 23-18:

SPI SLAVE MODE TIMING (CKE = 1)

SP82

SP70

SS

SP83

SCK

(CKP = 0)

SP72

SP71

SCK

(CKP = 1)

SP80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note 1: Refer to Figure 23-2 for load conditions.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 207

PIC16(L)F720/721

TABLE 23-11: SPI MODE REQUIREMENTS

Param.

Symbol

Characteristic

Min.

Typ† Max. Units Conditions

No.

SP70* TSSL2SCH, SS to SCK or SCK input

TCY

—

ns

TSSL2SCL

SP71* TSCH

SP72* TSCL

SCK input high time (Slave mode)

SCK input low time (Slave mode)

TCY + 20

100

—

ns

SP73* TDIV2SCH, Setup time of SDI data input to SCK edge

TDIV2SCL

SP74* TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge

100

—

ns

SP75* TDOR

SDO data output rise time

3.0-5.5V

1.8-5.5V

—

10

—

Tcy

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns

SP76* TDOF

SDO data output fall time

SP77* TSSH2DOZ

SP78* TSCR

SS to SDO output high-impedance

SCK output rise time

(Master mode)

3.0-5.5V

1.8-5.5V

SP79* TSCF

SCK output fall time (Master mode)

SP80* TSCH2DOV, SDO data output valid after

TSCL2DOV SCK edge

3.0-5.5V

1.8-5.5V

SP81* TDOV2SCH, SDO data output setup to SCK edge

TDOV2SCL

SP82* TSSL2DOV

SDO data output valid after SS edge

—

50

—

ns

SP83* TSCH2SSH, SS after SCK edge

1.5TCY +

40

TSCL2SSH

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS40001430E-page 208

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 23-19:

I²C™ BUS START/STOP BITS TIMING

SCL

SP93

SP91

SP90

SP92

SDA

Stop

Condition

Start

Condition

Note 1: Refer to Figure 23-2 for load conditions.

TABLE 23-12: I²C™ BUS START/STOP BITS REQUIREMENTS

Param.

Symbol

Characteristic

Min. Typ Max. Units

Conditions

No.

SP90* TSU:STA Start condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns Only relevant for Repeated

Start condition

SP91* THD:STA Start condition

Hold time

4000

600

ns After this period, the first

clock pulse is generated

SP92* TSU:STO Stop condition

Setup time

4700

600

ns

SP93 THD:STO Stop condition

Hold time

4000

600

ns

*

These parameters are characterized but not tested.

FIGURE 23-20:

I²C™ BUS DATA TIMING

SP100

SP103

SP102

SP101

SCL

SP90

SP106

SP107

SP92

SP91

SDA

In

SP110

SP109

SDA

Out

Note 1: Refer to Figure 23-2 for load conditions.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 209

PIC16(L)F720/721

TABLE 23-13: I²C™ BUS DATA REQUIREMENTS

Param.

Symbol

Characteristic

Min.

Max. Units

Conditions

No.

100*

THIGH

Clock high time

100 kHz mode

4.0

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY

4.7

—

101*

TLOW

Clock low time

100 kHz mode

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

SSP module

1.3

—

Device must operate at a

minimum of 10 MHz

1.5TCY

—

102*

103*

TR

TF

SDA and SCL rise 100 kHz mode

time

1000

300

ns

400 kHz mode

20 +

0.1CB

CB is specified to be from

10-400 pF

SDA and SCL fall

time

100 kHz mode

400 kHz mode

—

250

ns

20 +

0.1CB

CB is specified to be from

10-400 pF

90*

91*

TSU:STA Start condition

setup time

100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

0

—

s

ns

s

ns

s

ns

s

Only relevant for

Repeated Start condition

THD:STA Start condition hold 100 kHz mode

—

After this period the first

clock pulse is generated

time

400 kHz mode

—

106*

107*

92*

THD:DAT Data input hold

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

0

0.9

—

TSU:DAT Data input setup

time

250

100

4.7

0.6

—

(Note 2)

—

TSU:STO Stop condition

setup time

—

109*

110*

TAA

Output valid from

clock

3500

—

(Note 1)

—

TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmis-

sion can start

—

CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification), before the SCL line is released.

DS40001430E-page 210

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

24.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

FIGURE 24-1:

PIC16F720/721 MAX IDD vs. FOSC OVER VDD, EC MODE

1800

1600

1400

1200

1000

800

600

400

200

0

5.0V

3.6V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3ıꢀꢀꢀꢀ

(-40°C to 125°C)

3.0V

2.5V

1.8V

0

2

4

6

8

10

12

14

16

18

FOSC (MHz)

FIGURE 24-2:

PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, EC MODE

1800

1600

1400

1200

1000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3ıꢀꢀꢀꢀ

(-40°C to 125^°C)

5.0V

3.6V

3.0V

2.5V

1.8V

600

400

200

0

2

4

6

8

10

12

14

16

18

FOSC (MHz)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 211

PIC16(L)F720/721

FIGURE 24-3:

PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, EC MODE

2000

1800

1600

1400

1200

1000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3ıꢀꢀꢀꢀ

(-40°C to 125°C)

3.6V

3.3V

3.0V

2.5V

2.0V

1.8V

600

400

200

0

2

4

6

8

10

12

14

16

18

FOSC (MHz)

FIGURE 24-4:

PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, EC MODE

1800

1600

1400

1200

1000

800

600

400

200

0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3ıꢀꢀꢀꢀ

(-40°C to 125°C)

3.6V

3.3V

3.0V

2.5V

2.0V

1.8V

0

2

4

6

8

10

12

14

16

18

FOSC (MHz)

DS40001430E-page 212

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-5:

PIC16F720/721 MAX. IDD vs. FOSC OVER VDD, MFINTOSC

350

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

300

250

200

150

100

50

5V

3V

2.5V

1.8V

0

100

200

300

400

500

600

FOSC (kHZ)

FIGURE 24-6:

PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, MFINTOSC

350

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

300

250

200

150

100

50

5V

3V

2.5V

1.8V

0

100

200

300

FOSC (kHZ)

400

500

600

 2010-2013 Microchip Technology Inc.

DS40001430E-page 213

PIC16(L)F720/721

FIGURE 24-7:

PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, MFINTOSC

250

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

200

150

100

50

3.6V

3V

2.5V

1.8V

0

100

200

300

400

500

600

FOSC (kHZ)

FIGURE 24-8:

PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, MFINTOSC

250

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

200

150

100

50

3.6V

3V

2.5V

1.8V

0

100

200

300

400

500

600

FOSC (kHZ)

DS40001430E-page 214

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-9:

PIC16F720/721 MAX. IDD vs. FOSC OVER VDD, HFINTOSC

2000

5.0V

3.6V

1800

1600

1400

1200

1000

800

600

400

200

0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3ıꢀꢀꢀꢀ

(-40°C to 125°C)

2.5V

1.8V

0

2

4

6

8

10

12

14

16

18

FOSC (MHz)

FIGURE 24-10:

PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, HFINTOSC

2000

1800

1600

1400

1200

1000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3ıꢀꢀꢀꢀ

(-40°C to 125°C)

5.0V

3.6V

2.5V

1.8V

600

400

200

0

2

4

6

8

10

12

14

16

18

FOSC (MHz)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 215

PIC16(L)F720/721

FIGURE 24-11:

PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, HFINTOSC

2500

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3ıꢀꢀꢀꢀ

(-40°C to 125°C)

3.6V

2000

1500

1000

500

3.0V

2.5V

1.8V

0

2

4

6

8

10

12

14

16

18

FOSC (MHz)

FIGURE 24-12:

PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, HFINTOSC

2000

1800

1600

1400

1200

1000

800

3.6V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3ıꢀꢀꢀꢀ

(-40°C to 125°C)

3.0V

2.5V

1.8V

600

400

200

0

2

4

6

8

10

12

14

16

18

FOSC (MHz)

DS40001430E-page 216

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-13:

PIC16F720/721 BASE IPD vs. VDD

80

Typical: Statistical Mean @25°C

70

60

50

40

30

20

10

0

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

Max.125°C

Max. 85°C

Typ. 25°C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

VDD (V)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 217

PIC16(L)F720/721

FIGURE 24-14:

PIC16LF720/721 MAXIMUM BASE IPD vs. VDD

8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

7

6

5

4

3

2

1

Max. 125°C

Max. 85°C

0

1.5

2

2.5

3

3.5

4

VDD (V)

FIGURE 24-15:

PIC16LF720/721 TYPICAL BASE IPD vs. VDD

250

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

200

150

100

50

Typ.

0

1.5

2

2.5

3

3.5

4

VDD (V)

DS40001430E-page 218

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-16:

PIC16F720/721 WDT IPD vs. VDD

80

Typical: Statistical Mean @25°C

70

60

50

40

30

20

10

0

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typ. 25°C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

VDD (V)

FIGURE 24-17:

PIC16LF720/721 WDT IPD vs. VDD

14

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

12

10

8

Max. 125°C

6

Max. 85°C

Typ. 25°C

4

2

0

1.5

2

2.5

3

3.5

4

VDD (V)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 219

PIC16(L)F720/721

FIGURE 24-18:

PIC16F720/721 FIXED VOLTAGE REFERENCE IPD vs. VDD

300

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

250

200

150

100

50

Max. 125°C

Max. 85°C

Typ.

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

VDD (V)

FIGURE 24-19:

PIC16LF720/721 FIXED VOLTAGE REFERENCE IPD vs. VDD

40

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

35

30

25

20

15

10

5

Max. 125°C

Max. 85°C

Typ.

0

1.5

2

2.5

3

3.5

4

VDD (V)

DS40001430E-page 220

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-20:

PIC16F720/721 BOR IPD vs. VDD

80

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

70

60

50

40

30

20

10

Max. 125°C

Max. 85°C

Typ. 25°C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

VDD (V)

FIGURE 24-21:

PIC16LF720/721 BOR IPD vs. VDD

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) +3

(-40°C to 125°C)

25

20

15

10

5

Max. 125°C

Max. 85°C

Typ. 25°C

0

1.5

2

2.5

3

3.5

4

VDD (V)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 221

PIC16(L)F720/721

FIGURE 24-22:

TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

1.8

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

1.6

1.4

1.2

1

Minimum: Mean - 3 (-40°C to 125°C)

Max. -40°

Typ. 25°

Min. 125°

0.8

0.6

0.4

1.8

3.6

VDD (V)

5.5

FIGURE 24-23:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

3.5

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Minimum: Mean - 3 (-40°C to 125°C)

VIH Max. -40°C

VIH Min. 125°C

1.8

3.6

5.5

VDD (V)

DS40001430E-page 222

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-24:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

3.0

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

Minimum: Mean - 3 (-40°C to 125°C)

2.5

2.0

1.5

1.0

0.5

0.0

VIL Max. -40°C

VIL Min. 125°C

1.8

3.6

5.5

VDD (V)

FIGURE 24-25:

VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V

5.6

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

5.5

5.4

5.3

5.2

5.1

5

Minimum: Mean - 3 (-40°C to 125°C)

Max. -40°

Typ. 25°

Min. 125°

-0.2

-1.0

-1.8

-2.6

-3.4

-4.2

-5.0

IOH (mA)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 223

PIC16(L)F720/721

FIGURE 24-26:

VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V

3.8

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

Minimum: Mean - 3 (-40°C to 125°C)

3.6

3.4

3.2

3

Max. -40°

Typ. 25°

Min. 125°

2.8

2.6

-0.2

-1.0

-1.8

-2.6

-3.4

-4.2

-5.0

IOH (mA)

FIGURE 24-27:

VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V

2

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

1.8

1.6

1.4

1.2

1

Minimum: Mean - 3 (-40°C to 125°C)

Max. -40°

Typ. 25°

0.8

0.6

0.4

0.2

Min. 125°

0

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

-2.0

IOH (mA)

DS40001430E-page 224

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-28:

VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V

0.5

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

0.45

0.4

Minimum: Mean - 3 (-40°C to 125°C)

0.35

0.3

Max. 125°

0.25

0.2

Typ. 25°

0.15

0.1

Min. -40°

0.05

0

5.0

6.0

7.0

8.0

9.0

10.0

IOL (mA)

FIGURE 24-29:

VOL vs. IOL OVER TEMPERATURE, VDD = 3.6

0.9

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Minimum: Mean - 3 (-40°C to 125°C)

Max. 125°

Typ. 25°

Min. -40°

4.0

5.0

6.0

7.0

8.0

9.0

10.0

IOL (mA)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 225

PIC16(L)F720/721

FIGURE 24-30:

VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V

1.2

Maximum: Mean + 3 (-40°C to 125°C)

Typical: Mean @25°C

Minimum: Mean - 3 (-40°C to 125°C)

1

0.8

0.6

0.4

0.2

0

Max. 125°

Min. -40°

0.0

0.4

0.8

1.2

1.6

IOL (mA)

2.0

2.4

2.8

FIGURE 24-31:

PIC16F720/721 PWRT PERIOD

105

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

95

85

75

65

55

45

Max. -40°C

Typ. 25°C

Min. 125°C

1.8V

2V

2.2V

2.4V

3V

3.6V

4V

4.5V

5V

5.5V

VDD

DS40001430E-page 226

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-32:

PIC16F720/721 WDT TIME-OUT PERIOD

24.00

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

22.00

20.00

18.00

16.00

14.00

12.00

10.00

Max. -40°C

Typ. 25°C

Min. 125°C

1.8V

2V

2.2V

2.4V

3V

3.6V

4V

4.5V

5V

VDD

FIGURE 24-33:

PIC16F720/721 HFINTOSC WAKE-UP FROM SLEEP START-UP TIME

6.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

Max.

Typ.

1.8V

2V

3V

3.6V

4V

4.5V

5V

5.5V

VDD

 2010-2013 Microchip Technology Inc.

DS40001430E-page 227

PIC16(L)F720/721

FIGURE 24-34:

PIC16F720/721 A/D INTERNAL RC OSCILLATOR PERIOD

6.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

5.0

4.0

3.0

2.0

1.0

0.0

Max.

Min.

1.8V

3.6V

5.5V

VDD(V)

FIGURE 24-35:

TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V

1.5

1

0.5

0

-0.5

-1

-1.5

1.8

2.5

3

3.6

4.2

5.5

Voltage

DS40001430E-page 228

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

FIGURE 24-36:

TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C

1.5

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

-3

-40

0

45

85

125

Temperature (°C)

 2010-2013 Microchip Technology Inc.

DS40001430E-page 229

PIC16(L)F720/721

NOTES:

DS40001430E-page 230

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

25.0 PACKAGING INFORMATION

25.1 Package Marking Information

20-Lead PDIP (300 mil)

Example

PIC16F721-E/P

e

3

XXXXXXXXXXXXXXXXX

0810017

YYWWNNN

20-Lead QFN (4x4x0.9 mm)

Example

PIC16

F721

PIN 1

e

3

E/ML

810017

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro^®device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 231

PIC16(L)F720/721

25.1 Package Marking Information

20-Lead SOIC (7.50 mm)

Example

PIC16F720

-I/SO

e

3

0810017

20-Lead SSOP (5.30 mm)

Example

PIC16F720

-I/SS

e

3

0810017

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro^®device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

DS40001430E-page 232

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

25.2

Package Details

The following sections give the technical details of the packages.

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ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢁꢛ1

 2010-2013 Microchip Technology Inc.

DS40001430E-page 233

PIC16(L)F720/721

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ ꢏꢅꢆꢇ!ꢉꢅꢋ"ꢇꢛꢗꢇꢃꢄꢅꢆꢇꢈꢅꢍ#ꢅ$ꢄꢇꢒ%ꢃꢓꢇMꢇ&'&'ꢁ()ꢇꢕꢕꢇꢖꢗꢆꢘꢇꢙ !ꢛꢚ

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DS40001430E-page 234

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

ꢛꢗꢋꢄꢜ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ

ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ

 2010-2013 Microchip Technology Inc.

DS40001430E-page 235

PIC16(L)F720/721

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001430E-page 236

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010-2013 Microchip Technology Inc.

DS40001430E-page 237

PIC16(L)F720/721

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001430E-page 238

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ*+,ꢌꢑ#ꢇ*ꢕꢅꢉꢉꢇ-ꢏꢋꢉꢌꢑꢄꢇꢒ**ꢓꢇMꢇ.(ꢔꢁꢇꢕꢕꢇꢖꢗꢆꢘꢇꢙ**-ꢈꢚꢇ

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 2010-2013 Microchip Technology Inc.

DS40001430E-page 239

PIC16(L)F720/721

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001430E-page 240

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

APPENDIX A: DATA SHEET

REVISION HISTORY

APPENDIX B: MIGRATING FROM

OTHER PIC^®

DEVICES

Revision A (September 2010)

This shows a comparison of features in the migration

from another PIC^®device, the PIC16F720, to the

PIC16F721 device.

Original release of this document.

Revision B (March 2011)

B.1

TABLE B-1:

Feature

PIC16F690 to PIC16F721

Updated the Electrical Specifications section.

FEATURE COMPARISON

Revision C (September 2011)

PIC16F690

PIC16F721

Reviewed title; Updated Table 1 and Table 1-1;

Reviewed the Memory Organization section; Updated

Section 3.6, Figures 3-4 and 3-5, Register 4-1 and

Figure 4-2; Updated Registers 8-1 and 8-2; Reviewed

the Oscillator Module section; Updated Table 10-1,

Figures 11-1, 12-1 and Register 18-1; Updated the

Summary of Registers Tables; Updated the Electrical

Specifications section; Updated the DC and AC

Characteristics Graphs and Charts section; Updated

the Packaging Information section; Updated the

Product Identification System section.

Max. Operating Speed

20 MHz

4K

16 MHz

4K

Max. Program

Memory (Words)

Max. SRAM (Bytes)

A/D Resolution

256

10-bit

2/1

8

256

8-bit

2/1

4

Timers (8/16-bit)

Oscillator Modes

Brown-out Reset

Internal Pull-ups

Y

RA<5:0>,

RB<7:4>

RA<5:0>,

RB<7:4>

Revision D (February 2013)

Interrupt-on-change

RA<5:0>,

RB<7:4>

RA<5:0>,

RB<7:4>

Updated Table 1-1, Table 15-4 and Table 16-5;

Updated the Electrical Specifications section; Updated

the DC and AC Characteristics Graphs and Charts

section; Other minor corrections.

Comparator

EUSART

2

Y

0

Y

N

Extended WDT

Software Control

Option of WDT/BOR

Revision E (August 2013)

Deleted Example 18-2; Revised Table 23-7.

INTOSC Frequencies

Pin Count

31 kHz -

8 MHz

500 kHz -

16 MHz

20

Note:

This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process dif-

ferences in the manufacture of this device,

this device may have different perfor-

mance characteristics than its earlier ver-

sion. These differences may cause this

device to perform differently in your appli-

cation than the earlier version of this

device.

Note:

The user should verify that the device

oscillator starts and performs as

expected. Adjusting the loading capacitor

values and/or the oscillator mode may be

required.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 241

PIC16(L)F720/721

NOTES:

DS40001430E-page 242

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

INDEX

A

B

A/D

BF bit ........................................................................ 145, 157

Block Diagrams

Specifications.................................................... 202, 203

Absolute Maximum Ratings .............................................. 185

AC Characteristics

(CCP) Capture Mode Operation............................... 108

ADC............................................................................ 75

ADC Transfer Function............................................... 82

Analog Input Model..................................................... 82

AUSART Receive..................................................... 118

AUSART Transmit.................................................... 117

CCP PWM ................................................................ 112

Clock Source .............................................................. 65

Compare................................................................... 110

Interrupt Logic............................................................. 35

MCLR Circuit .............................................................. 27

On-Chip Reset Circuit................................................. 25

RA0 Pins..................................................................... 49

RA1 Pins..................................................................... 50

RA2 Pin ...................................................................... 51

RA4 Pin ...................................................................... 52

RA5 Pin ................................................................ 52, 53

RB0 Pin ...................................................................... 57

RB3 Pin ...................................................................... 58

RC0 Pin ...................................................................... 62

RC5 Pin ...................................................................... 63

RC6 Pin ...................................................................... 63

RC7 Pin ...................................................................... 63

SPI Mode.................................................................. 138

Industrial and Extended ............................................ 194

Load Conditions........................................................ 193

ADC .................................................................................... 75

Acquisition Requirements ........................................... 81

Associated registers.................................................... 83

Block Diagram............................................................. 75

Calculating Acquisition Time....................................... 81

Channel Selection....................................................... 76

Configuration............................................................... 76

Configuring Interrupt ................................................... 78

Conversion Clock........................................................ 76

Conversion Procedure ................................................ 78

Internal Sampling Switch (RSS) Impedance................ 81

Interrupts..................................................................... 77

Operation .................................................................... 77

Operation During Sleep .............................................. 78

Port Configuration....................................................... 76

Source Impedance...................................................... 81

Special Event Trigger.................................................. 78

ADCON0 Register......................................................... 16, 79

ADCON1 Register......................................................... 17, 80

Addressable Universal Synchronous Asynchronous

Receiver Transmitter (AUSART)............................... 117

ADRES Register ................................................................. 80

ADRESH Register............................................................... 16

Analog-to-Digital Converter. See ADC

2

SSP (I C Mode)........................................................ 147

Timer1 .................................................. 93, 99, 100, 101

Timer2 ...................................................................... 105

TMR0/WDT Prescaler ................................................ 89

Voltage Reference...................................................... 85

Brown-out Reset (BOR)...................................................... 29

Timing and Characteristics....................................... 199

ANSELA Register ............................................................... 47

ANSELB Register ............................................................... 56

Assembler

MPASM Assembler................................................... 182

AUSART ........................................................................... 117

Associated Registers

C

C Compilers

MPLAB C18.............................................................. 182

Capture Module. See Capture/Compare/PWM (CCP)

Capture/Compare/PWM (CCP) ........................................ 107

Associated registers w/ Capture............................... 109

Associated registers w/ Compare............................. 111

Associated registers w/ PWM................................... 115

Capture Mode........................................................... 108

CCPx Pin Configuration............................................ 108

Compare Mode......................................................... 110

CCPx Pin Configuration.................................... 110

Software Interrupt Mode........................... 108, 110

Special Event Trigger....................................... 110

Timer1 Mode Selection............................. 108, 110

Prescaler .................................................................. 108

PWM Mode............................................................... 112

Duty Cycle ........................................................ 113

Effects of Reset................................................ 114

Example PWM Frequencies and Resolutions

Baud Rate Generator........................................ 127

Asynchronous Mode ................................................. 119

Associated Registers

Receive..................................................... 124

Transmit.................................................... 121

Baud Rate Generator (BRG) ............................ 127

Receiver............................................................ 121

Setting up 9-bit Mode with Address Detect....... 123

Transmitter........................................................ 119

Baud Rate Generator (BRG)

Baud Rate Error, Calculating ............................ 127

Baud Rates, Asynchronous Modes .................. 128

Formulas........................................................... 127

High Baud Rate Select (BRGH Bit) .................. 127

Synchronous Master Mode............................... 130, 134

Associated Registers

Receive..................................................... 133

Transmit.................................................... 131

Reception.......................................................... 132

Transmission .................................................... 130

Synchronous Slave Mode

16 MHZ..................................................... 114

8 MHz....................................................... 114

Operation in Sleep Mode.................................. 114

Setup for Operation .......................................... 114

System Clock Frequency Changes .................. 114

PWM Period ............................................................. 113

Setup for PWM Operation ........................................ 114

Timer Resources ...................................................... 107

Associated Registers

Receive..................................................... 135

Transmit.................................................... 134

Reception.......................................................... 135

Transmission .................................................... 134

 2010-2013 Microchip Technology Inc.

DS40001430E-page 243

PIC16(L)F720/721

CCP. See Capture/Compare/PWM (CCP)

Instruction Set................................................................... 171

ADDLW..................................................................... 173

ADDWF..................................................................... 173

ANDLW..................................................................... 173

ANDWF..................................................................... 173

BCF .......................................................................... 173

BSF........................................................................... 173

BTFSC...................................................................... 173

BTFSS ...................................................................... 174

CALL......................................................................... 174

CLRF ........................................................................ 174

CLRW ....................................................................... 174

CLRWDT .................................................................. 174

COMF ....................................................................... 174

DECF........................................................................ 174

DECFSZ ................................................................... 175

GOTO ....................................................................... 175

INCF ......................................................................... 175

INCFSZ..................................................................... 175

IORLW...................................................................... 175

IORWF...................................................................... 175

MOVF ....................................................................... 176

MOVLW .................................................................... 176

MOVWF.................................................................... 176

NOP.......................................................................... 176

RETFIE..................................................................... 177

RETLW ..................................................................... 177

RETURN................................................................... 177

RLF........................................................................... 178

RRF .......................................................................... 178

SLEEP ...................................................................... 178

SUBLW..................................................................... 178

SUBWF..................................................................... 179

SWAPF..................................................................... 179

XORLW .................................................................... 179

XORWF .................................................................... 179

Summary Table ........................................................ 172

INTCON Register................................................................ 38

Internal Oscillator Block

CCP1CON Register ............................................................16

CCPR1H Register...............................................................16

CCPR1L Register................................................................16

CCPxCON Register ..........................................................107

CKE bit...................................................................... 145, 157

CKP bit...................................................................... 144, 156

Clock Sources

External Modes...........................................................69

EC.......................................................................69

Code Examples

A/D Conversion...........................................................78

Call of a Subroutine in Page 1 from Page 0................23

Changing Between Capture Prescalers....................108

Indirect Addressing .....................................................24

Initializing PORTA.......................................................45

Initializing PORTB.......................................................54

Initializing PORTC.......................................................60

Loading the SSPBUF (SSPSR) Register..................140

Saving W, STATUS and PCLATH Registers in

RAM....................................................................37

Comparators

C2OUT as T1 Gate .....................................................95

Compare Module. See Capture/Compare/PWM (CCP)

Customer Change Notification Service .............................249

Customer Notification Service...........................................249

Customer Support.............................................................249

D

D/A bit ...............................................................................157

Data Memory.......................................................................12

Data/Address bit (D/A) ......................................................157

DC and AC Characteristics ...............................................211

DC Characteristics

Extended and Industrial ............................................190

Industrial and Extended ............................................186

Development Support .......................................................181

Device Configuration...........................................................71

Code Protection ..........................................................74

Configuration Word .....................................................71

User ID........................................................................74

Device Overview ...................................................................7

INTOSC

Specifications ........................................... 197, 198

Internal Sampling Switch (RSS) Impedance........................ 81

Internet Address ............................................................... 249

Interrupts............................................................................. 35

ADC ............................................................................ 78

Associated registers w/ Interrupts............................... 41

Interrupt-on-Change ................................................... 54

TMR1.......................................................................... 98

INTOSC Specifications............................................. 197, 198

IOCB Register..................................................................... 56

E

Effects of Reset

PWM mode ...............................................................114

Electrical Specifications ....................................................185

Errata ....................................................................................6

F

Firmware Instructions........................................................171

Fixed Voltage Reference. See FVR

L

FSR Register................................................................. 16, 17

FVR.....................................................................................85

Associated registers....................................................86

FVRCON Register...............................................................86

Load Conditions................................................................ 193

M

M....................................................................................... 201

MCLR.................................................................................. 27

Internal........................................................................ 27

Memory Organization ......................................................... 11

Data ............................................................................ 12

Program...................................................................... 11

Microchip Internet Web Site.............................................. 249

Migrating from other PIC Microcontroller Devices ............ 241

MPLAB ASM30 Assembler, Linker, Librarian................... 182

MPLAB Integrated Development Environment Software.. 181

MPLAB PM3 Device Programmer .................................... 184

G

General Purpose Register File............................................13

I

2

I C Mode

Associated Registers ................................................158

INDF Register ............................................................... 16, 17

Indirect Addressing, INDF and FSR Registers....................24

Instruction Format .............................................................171

DS40001430E-page 244

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

MPLAB REAL ICE In-Circuit Emulator System................. 183

MPLINK Object Linker/MPLIB Object Librarian ................ 182

RC2 ............................................................................ 62

RC3 ............................................................................ 62

RC4 ............................................................................ 62

RC5 ............................................................................ 62

RC6 ............................................................................ 62

RC7 ............................................................................ 62

Specifications ........................................................... 198

PORTC Register................................................................. 60

Power-Down Mode (Sleep)............................................... 167

Associated Registers................................................ 168

Power-on Reset.................................................................. 27

Power-up Timer (PWRT).................................................... 27

Specifications ........................................................... 200

PR2 Register .............................................................. 17, 146

Precision Internal Oscillator Parameters .......................... 198

Prescaler

Shared WDT/Timer0................................................... 90

Product Identification System ........................................... 251

Program Memory................................................................ 11

Map and Stack (PIC16F720/LF720)........................... 11

Map and Stack (PIC16F721/LF721)........................... 11

Paging ........................................................................ 23

Program Memory Read (PMR)......................................... 159

Associated Registers................................................ 165

Programming, Device Instructions.................................... 171

O

OPCODE Field Descriptions............................................. 171

OPTION_REG Register ...................................................... 91

OSCCON Register.............................................................. 67

Oscillator

Associated registers............................................ 69, 104

Oscillator Module

EC............................................................................... 65

Oscillator Tuning......................................................... 68

Oscillator Parameters ....................................................... 197

Oscillator Specifications.................................................... 196

OSCTUNE Register ............................................................ 68

P

P (Stop) bit........................................................................ 157

Packaging ......................................................................... 231

Marking ............................................................. 231, 232

PDIP Details.............................................................. 233

Paging, Program Memory................................................... 23

PCL and PCLATH............................................................... 23

Computed GOTO........................................................ 23

Stack........................................................................... 23

PCL Register................................................................. 16, 17

PCLATH Register ......................................................... 16, 17

PCON Register ....................................................... 17, 22, 30

PIE1 Register................................................................ 17, 39

PIR1 Register................................................................ 16, 40

PMADRH Register ............................................................ 164

PMADRL Register............................................................. 165

PMCON1 Register .................................................... 163, 165

PMDATH Register ............................................................ 164

PMDATL Register............................................................. 164

PORTA................................................................................ 45

ANSELA Register ....................................................... 47

Associated Registers .................................................. 53

Pin Descriptions and Diagrams................................... 48

PORTA Register ......................................................... 16

RA0............................................................................. 48

RA1............................................................................. 48

RA2............................................................................. 48

RA3............................................................................. 48

RA4............................................................................. 48

RA5............................................................................. 48

RA6............................................................................. 48

Specifications............................................................ 198

PORTA Register ................................................................. 46

PORTB

R

R/W bit.............................................................................. 157

RCREG............................................................................. 123

RCSTA Register ......................................................... 16, 126

Read-Modify-Write Operations ......................................... 171

Receive Overflow Indicator bit (SSPOV) .................. 144, 156

Registers

ADCON0 (ADC Control 0).......................................... 79

ADCON1 (ADC Control 1).......................................... 80

ADRES (ADC Result)................................................. 80

ANSELA (PORTA Analog Select) .............................. 47

ANSELB (PORTB Analog Select) .............................. 56

CCPxCON (CCP Operation) .................................... 107

FVRCON (Fixed Voltage Reference Register)........... 86

INTCON (Interrupt Control) ........................................ 38

IOCB (Interrupt-on-Change PORTB).......................... 56

OPTION_REG (Option).............................................. 91

OSCCON (Oscillator Control)..................................... 67

OSCTUNE (Oscillator Tuning).................................... 68

PCON (Power Control Register)................................. 22

PCON (Power Control)............................................... 30

PIE1 (Peripheral Interrupt Enable 1) .......................... 39

PIR1 (Peripheral Interrupt Register 1)........................ 40

PMADRH (Program Memory Address High) ............ 164

PMADRL (Program Memory Address Low).............. 165

PMCON1 (Program Memory Control 1) ................... 163

PMDATH (Program Memory Data High) .................. 164

PMDATL (Program Memory Data Low).................... 164

PORTA ....................................................................... 46

PORTB ....................................................................... 55

PORTC....................................................................... 60

RCSTA (Receive Status and Control) ...................... 126

Reset Values .............................................................. 32

Reset Values (Special Registers)............................... 34

SSPCON (Sync Serial Port Control) Register .. 144, 156

SSPSTAT (Sync Serial Port Status) Register .. 145, 157

STATUS ..................................................................... 20

T1CON (Timer1 Control) .......................................... 102

T1GCON (Timer1 Gate Control)............................... 103

T2CON ..................................................................... 106

Additional Pin Functions

ANSELB Register ............................................... 54

Weak Pull-up ...................................................... 54

Associated Registers .................................................. 59

Interrupt-on-Change.................................................... 54

Pin Descriptions and Diagrams................................... 57

PORTB Register ......................................................... 16

RB0............................................................................. 57

RB4............................................................................. 57

RB5............................................................................. 57

RB6............................................................................. 57

RB7............................................................................. 57

PORTB Register ................................................................. 55

PORTC

PORTC Register......................................................... 16

RC0............................................................................. 62

 2010-2013 Microchip Technology Inc.

DS40001430E-page 245

PIC16(L)F720/721

TRISA (Tri-State PORTA)...........................................46

TRISB (Tri-State PORTB)...........................................55

TRISC (Tri-State PORTC) ..........................................61

TXSTA (Transmit Status and Control) ......................125

WPUB (Weak Pull-up PORTB)...................................55

Reset...................................................................................25

Resets

Modes of Operation .................................................... 94

Module On/Off (TMR1ON Bit)................................... 103

Operation During Sleep .............................................. 98

Prescaler .................................................................... 95

Specifications ........................................................... 201

Timer1 Gate

Selecting Source ................................................ 95

TMR1H Register......................................................... 93

TMR1L Register.......................................................... 93

Associated Registers ..................................................34

Revision History ................................................................241

Timer2

Associated registers ................................................. 106

Timers

Timer1

T1CON ............................................................. 102

T1GCON........................................................... 103

Timer2

T2CON ............................................................. 106

Timing Diagrams

S

S (Start) bit........................................................................157

SMP bit...................................................................... 145, 157

Software Simulator (MPLAB SIM).....................................183

SPBRG..............................................................................127

SPBRG Register .................................................................17

Special Event Trigger..........................................................78

Special Function Registers .................................................13

SPI Mode ..........................................................................143

Associated Registers ................................................146

Typical Master/Slave Connection .............................137

SSP...................................................................................137

A/D Conversion......................................................... 203

A/D Conversion (Sleep Mode).................................. 204

Asynchronous Reception.......................................... 124

Asynchronous Transmission..................................... 120

Asynchronous Transmission (Back-to-Back)............ 121

Brown-out Reset (BOR)............................................ 199

Brown-out Reset Situations ........................................ 29

CLKOUT and I/O ...................................................... 198

Clock Synchronization .............................................. 155

Clock Timing............................................................. 196

2

I C Mode...................................................................147

Acknowledge.....................................................148

Addressing........................................................149

Clock Stretching................................................154

Clock Synchronization ......................................155

Firmware Master Mode.....................................154

Hardware Setup................................................147

Multi-Master Mode ............................................154

Reception..........................................................150

Sleep Operation................................................155

2

I C Bus Data............................................................. 209

2

I C Bus Start/Stop Bits ............................................. 209

2

I C Reception (7-bit Address)................................... 150

2

I C Slave Mode with SEN = 0 (Reception,

Start/Stop Conditions........................................148

10-bit Address) ................................................. 151

I C Transmission (7-bit Address).............................. 152

2

Transmission.....................................................152

Master Mode.............................................................139

SPI Mode ..................................................................137

Slave Mode.......................................................141

Typical SPI Master/Slave Connection.......................137

SSPADD Register...............................................................17

SSPBUF Register ...............................................................16

SSPCON Register............................................... 16, 144, 156

SSPEN bit ................................................................. 144, 156

SSPM bits ................................................................. 144, 156

SSPOV bit................................................................. 144, 156

SSPSTAT Register ............................................. 17, 145, 157

STATUS Register................................................................20

Synchronous Serial Port Enable bit (SSPEN)........... 144, 156

Synchronous Serial Port Mode Select bits (SSPM) .. 144, 156

INT Pin Interrupt ......................................................... 36

Slave Select Synchronization ................................... 143

SPI Master Mode...................................................... 140

SPI Master Mode (CKE = 1, SMP = 1) ..................... 206

SPI Mode (Slave Mode with CKE = 0)...................... 142

SPI Mode (Slave Mode with CKE = 1)...................... 142

SPI Slave Mode (CKE = 0)....................................... 206

SPI Slave Mode (CKE = 1)....................................... 207

Synchronous Reception (Master Mode, SREN) ....... 133

Synchronous Transmission ...................................... 131

Synchronous Transmission (Through TXEN)........... 131

Time-out Sequence

Case 1 ................................................................ 30

Case 2 ................................................................ 31

Case 3 ................................................................ 31

Timer0 and Timer1 External Clock ........................... 200

Timer1 Incrementing Edge ......................................... 98

USART Synchronous Receive (Master/Slave) ......... 205

USART Synchronous Transmission (Master/Slave). 204

Wake-up from Interrupt............................................. 168

Timing Parameter Symbology .......................................... 193

Timing Requirements

T

T1CON Register.......................................................... 16, 102

TMR1ON Bit..............................................................103

T1GCON Register.............................................................103

T2CON Register.................................................. 16, 106, 146

Temperature Indicator Module............................................87

Thermal Considerations....................................................192

Time-out Sequence.............................................................30

Timer0.................................................................................89

Associated Registers ..................................................91

Operation .............................................................. 89, 94

Specifications............................................................201

Timer1.................................................................................93

Associated registers..................................................104

Asynchronous Counter Mode .....................................95

Reading and Writing ...........................................95

2

I C Bus Data............................................................. 210

I2C Bus Start/Stop Bits............................................. 209

SPI Mode.................................................................. 208

TMR0 Register.................................................................... 16

TMR1H Register................................................................. 16

TMR1L Register.................................................................. 16

TMR2 Register.................................................................... 16

TMRO Register................................................................... 18

TRISA ................................................................................. 45

Interrupt.......................................................................98

DS40001430E-page 246

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

TRISA Register ............................................................. 17, 46

TRISB ................................................................................. 54

TRISB Register ............................................................. 17, 55

TRISC ................................................................................. 60

TRISC Register............................................................. 17, 61

TXREG.............................................................................. 119

TXREG Register ................................................................. 16

TXSTA Register.......................................................... 17, 125

BRGH Bit .................................................................. 127

U

UA..................................................................................... 157

Update Address bit, UA .................................................... 157

USART

Synchronous Master Mode

Requirements, Synchronous Receive .............. 205

Requirements, Synchronous Transmission ...... 204

Timing Diagram, Synchronous Receive ........... 205

Timing Diagram, Synchronous Transmission ... 204

W

Wake-up Using Interrupts ................................................. 168

Watchdog Timer (WDT)...................................................... 27

Clock Source............................................................... 27

Modes ......................................................................... 28

Period.......................................................................... 27

Specifications............................................................ 200

WCOL bit .................................................................. 144, 156

WPUB Register................................................................... 55

Write Collision Detect bit (WCOL)............................. 144, 156

WWW Address.................................................................. 249

WWW, On-Line Support ....................................................... 6

 2010-2013 Microchip Technology Inc.

DS40001430E-page 247

PIC16(L)F720/721

NOTES:

DS40001430E-page 248

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers

should

contact

their

distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 249

PIC16(L)F720/721

NOTES:

DS40001430E-page 250

 2010-2013 Microchip Technology Inc.

PIC16(L)F720/721

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

X

/XX

XXX

PART NO.

Device

Examples:

Tape and Reel

Option

Temperature

Range

Package

Pattern

a)

PIC16F720-E/P 301 = Extended Temp., PDIP

package, QTP pattern #301

b)

PIC16F721T-I/SO = Tape and Reel, Industrial

Temp., SOIC package

Device:

PIC16F720, PIC16LF720, PIC16F721, PIC16LF721

Temperature

Range:

I

E

=

-40C to +85C

-40C to +125C

Package:

ML

P

SO

SS

=

Micro Lead Frame (QFN)

Plastic DIP

SOIC

SSOP

Pattern:

3-Digit Pattern Code for QTP (blank otherwise)

Note 1: T=

Available in tape and reel for all

industrial devices except PDIP.

2: Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes

and is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

 2010-2013 Microchip Technology Inc.

DS40001430E-page 251

PIC16(L)F720/721

NOTES:

DS40001430E-page 252

 2010-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

32

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Technology Germany II GmbH & Co. KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 9781620773970

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2010-2013 Microchip Technology Inc.

DS40001430E-page 253

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Korea - Seoul

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Fax: 886-7-330-9305

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

China - Xiamen

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

11/29/12

DS40001430E-page 254

 2010-2013 Microchip Technology Inc.


型号：	PIC16LF720T-E/SS
厂家：	MICROCHIP
描述：	8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO20, 5.30 MM, LEAD FREE, PLASTIC, SSOP-20 光电二极管
文件：	总254页 (文件大小：4219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16LF720T-E/SS [MICROCHIP]

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