PIC16LF84A-20/SOSQTP [MICROCHIP]
18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller; 18引脚增强型闪存/ EEPROM的8位微控制器
| 型号： | PIC16LF84A-20/SOSQTP |
| 厂家： | 
MICROCHIP |
| 描述： | 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller |
| 文件： | 总88页 (文件大小：1406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
PIC16F84A
Data Sheet
18-pin Enhanced FLASH/EEPROM
8-bit Microcontroller
2001 Microchip Technology Inc.
DS35007B
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL,
MPLAB and The Embedded Control Solutions Company are reg-
istered trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Total Endurance, ICSP, In-Circuit Serial Programming, Filter-
Lab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM,
MPLINK, MPLIB, PICC, PICDEM, PICDEM.net, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR, Select
Mode and microPort are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2001, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
DS35007B - page ii
2001 Microchip Technology Inc.
PIC16F84A
M
18-pin Enhanced FLASH/EEPROM 8-Bit Microcontroller
High Performance RISC CPU Features:
Pin Diagrams
PDIP, SOIC
• Only 35 single word instructions to learn
• All instructions single-cycle except for program
branches which are two-cycle
•1
2
3
4
5
6
7
8
9
RA2
RA3
18
17
16
15
14
13
12
11
10
RA1
RA0
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
RA4/T0CKI
MCLR
VSS
OSC1/CLKIN
OSC2/CLKOUT
VDD
• 1024 words of program memory
• 68 bytes of Data RAM
RB0/INT
RB1
RB7
RB6
• 64 bytes of Data EEPROM
• 14-bit wide instruction words
• 8-bit wide data bytes
RB2
RB5
RB3
RB4
• 15 Special Function Hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Four interrupt sources:
SSOP
- External RB0/INT pin
RA2
RA3
•1
2
3
4
5
6
7
8
9
RA1
RA0
20
19
18
17
16
15
14
13
12
11
- TMR0 timer overflow
- PORTB<7:4> interrupt-on-change
- Data EEPROM write complete
RA4/T0CKI
MCLR
OSC1/CLKIN
OSC2/CLKOUT
VSS
VDD
VDD
RB7
RB6
RB5
RB4
Peripheral Features:
VSS
RB0/INT
RB1
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
RB2
10
RB3
- 25 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features:
CMOS Enhanced FLASH/EEPROM
Technology:
• 10,000 erase/write cycles Enhanced FLASH
Program memory typical
• Low power, high speed technology
• Fully static design
• 10,000,000 typical erase/write cycles EEPROM
Data memory typical
• Wide operating voltage range:
- Commercial: 2.0V to 5.5V
• EEPROM Data Retention > 40 years
• In-Circuit Serial Programming™ (ICSP™) - via
two pins
- Industrial:
2.0V to 5.5V
• Low power consumption:
• Power-on Reset (POR), Power-up Timer (PWRT),
Oscillator Start-up Timer (OST)
- < 2 mA typical @ 5V, 4 MHz
- 15 µA typical @ 2V, 32 kHz
- < 0.5 µA typical standby current @ 2V
• Watchdog Timer (WDT) with its own On-Chip RC
Oscillator for reliable operation
• Code protection
• Power saving SLEEP mode
• Selectable oscillator options
2001 Microchip Technology Inc.
DS35007B-page 1
PIC16F84A
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 3
2.0 Memory Organization................................................................................................................................................................... 5
3.0 Data EEPROM Memory ............................................................................................................................................................. 13
4.0 I/O Ports ..................................................................................................................................................................................... 15
5.0 Timer0 Module ........................................................................................................................................................................... 19
6.0 Special Features of the CPU...................................................................................................................................................... 21
7.0 Instruction Set Summary ............................................................................................................................................................ 35
8.0 Development Support................................................................................................................................................................. 43
9.0 Electrical Characteristics ............................................................................................................................................................ 49
10.0 DC/AC Characteristic Graphs .................................................................................................................................................... 61
11.0 Packaging Information................................................................................................................................................................ 71
Appendix A: Revision History .............................................................................................................................................................. 75
Appendix B: Conversion Considerations.............................................................................................................................................. 76
Appendix C: Migration from Baseline to Mid-Range Devices .............................................................................................................. 78
Index .................................................................................................................................................................................................... 79
On-Line Support................................................................................................................................................................................... 83
Reader Response ................................................................................................................................................................................ 84
PIC16F84A Product Identification System........................................................................................................................................... 85
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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We welcome your feedback.
Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS35007B-page 2
2001 Microchip Technology Inc.
PIC16F84A
The program memory contains 1K words, which trans-
lates to 1024 instructions, since each 14-bit program
memory word is the same width as each device instruc-
tion. The data memory (RAM) contains 68 bytes. Data
EEPROM is 64 bytes.
1.0
DEVICE OVERVIEW
This document contains device specific information for
the operation of the PIC16F84A device. Additional
information may be found in the PICmicro™ Mid-
Range Reference Manual, (DS33023), which may be
downloaded from the Microchip website. The Refer-
ence Manual should be considered a complementary
document to this data sheet, and is highly recom-
mended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are also 13 I/O pins that are user-configured on
a pin-to-pin basis. Some pins are multiplexed with other
device functions. These functions include:
• External interrupt
• Change on PORTB interrupt
• Timer0 clock input
The PIC16F84A belongs to the mid-range family of the
PICmicro® microcontroller devices. A block diagram of
the device is shown in Figure 1-1.
Table 1-1 details the pinout of the device with descrip-
tions and details for each pin.
FIGURE 1-1:
PIC16F84A BLOCK DIAGRAM
Data Bus
13
8
Program Counter
EEPROM Data Memory
FLASH
Program
Memory
EEPROM
Data Memory
64 x 8
RAM
8 Level Stack
EEDATA
1K x 14
File Registers
(13-bit)
68 x 8
Program
Bus
14
7
RAM Addr
EEADR
Addr Mux
Instruction Register
TMR0
7
Indirect
Addr
Direct Addr
5
FSR reg
RA4/T0CKI
STATUS reg
MUX
8
Power-up
Timer
I/O Ports
8
Instruction
Decode &
Control
Oscillator
Start-up Timer
ALU
Power-on
Reset
RA3:RA0
RB7:RB1
Watchdog
Timer
Timing
Generation
W reg
RB0/INT
MCLR
OSC2/CLKOUT
OSC1/CLKIN
VDD, VSS
2001 Microchip Technology Inc.
DS35007B-page 3
PIC16F84A
TABLE 1-1:
PIC16F84A PINOUT DESCRIPTION
PDIP SOIC SSOP I/O/P
Buffer
Type
Pin Name
Description
No.
No.
No.
Type
OSC1/CLKIN
16
16
15
18
19
I
ST/CMOS(3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 15
O
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. In RC mode,
OSC2 pin outputs CLKOUT, which has 1/4 the
frequency of OSC1 and denotes the instruction
cycle rate.
MCLR
4
4
4
I/P
ST
Master Clear (Reset) input/programming voltage
input. This pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
RA0
17
18
1
17
18
1
19
20
1
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA1
RA2
RA3
2
2
2
RA4/T0CKI
3
3
3
Can also be selected to be the clock input to the
TMR0 timer/counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on
all inputs.
RB0/INT
6
6
7
I/O
TTL/ST(1)
RB0/INT can also be selected as an external
interrupt pin.
RB1
RB2
RB3
RB4
RB5
RB6
7
8
7
8
8
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
9
9
9
10
11
12
13
TTL
10
11
12
10
11
12
TTL
Interrupt-on-change pin.
Interrupt-on-change pin.
TTL
TTL/ST(2)
Interrupt-on-change pin.
Serial programming clock.
RB7
13
13
14
I/O
TTL/ST(2)
Interrupt-on-change pin.
Serial programming data.
VSS
5
5
5,6
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
14
14
15,16
Legend: I= input
O = Output
— = Not used
I/O = Input/Output
TTL = TTL input
P = Power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS35007B-page 4
2001 Microchip Technology Inc.
PIC16F84A
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK - PIC16F84A
2.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC16F84A.
These are the program memory and the data memory.
Each block has its own bus, so that access to each
block can occur during the same oscillator cycle.
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
•
•
•
Stack Level 8
0000h
0004h
RESET Vector
Peripheral Interrupt Vector
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 3.0.
Additional information on device memory may be found
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
3FFh
2.1
Program Memory Organization
The PIC16FXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16F84A, the first 1K x 14 (0000h-03FFh) are
physically implemented (Figure 2-1). Accessing a loca-
tion above the physically implemented address will
cause a wraparound. For example, for locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h,
the instruction will be the same.
1FFFh
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
2001 Microchip Technology Inc.
DS35007B-page 5
PIC16F84A
FIGURE 2-2:
REGISTER FILE MAP -
PIC16F84A
2.2
Data Memory Organization
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
File Address
File Address
80h
(1)
(1)
00h
Indirect addr.
Indirect addr.
01h
02h
TMR0
PCL
OPTION_REG
PCL
81h
82h
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register.
Figure 2-2 shows the data memory map organization.
03h
04h
05h
06h
STATUS
FSR
STATUS
FSR
83h
84h
85h
86h
PORTA
TRISA
PORTB
TRISB
—
—
07h
08h
09h
87h
88h
89h
Instructions MOVWF and MOVF can move values from
the W register to any location in the register file (“F”),
and vice-versa.
EEDATA
EEADR
EECON1
(1)
EECON2
0Ah
PCLATH
INTCON
PCLATH
INTCON
8Ah
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
(Section 2.5). Indirect addressing uses the present
value of the RP0 bit for access into the banked areas of
data memory.
0Bh
0Ch
8Bh
8Ch
68
General
Purpose
Registers
(SRAM)
Mapped
(accesses)
in Bank 0
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers, implemented as static RAM.
4Fh
50h
CFh
D0h
2.2.1
GENERAL PURPOSE REGISTER
FILE
Each General Purpose Register (GPR) is 8-bits wide
and is accessed either directly or indirectly through the
FSR (Section 2.5).
7Fh
FFh
The GPR addresses in Bank 1 are mapped to
addresses in Bank 0. As an example, addressing loca-
tion 0Ch or 8Ch will access the same GPR.
Bank 0
Bank 1
Unimplemented data memory location, read as ’0’.
Note 1: Not a physical register.
DS35007B-page 6
2001 Microchip Technology Inc.
PIC16F84A
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
2.3
Special Function Registers
The Special Function Registers (Figure 2-2 and
Table 2-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
TABLE 2-1:
SPECIAL FUNCTION REGISTER FILE SUMMARY
Value on
Details
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
RESET
on page
Bank 0
00h INDF
01h TMR0
02h PCL
Uses contents of FSR to address Data Memory (not a physical register)
8-bit Real-Time Clock/Counter
---- ----
xxxx xxxx
0000 0000
11
20
11
8
Low Order 8 bits of the Program Counter (PC)
(2)
03h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---x xxxx
04h FSR
Indirect Data Memory Address Pointer 0
11
16
18
—
(4)
05h PORTA
06h PORTB
—
—
—
RA4/T0CKI
RB4
RA3
RB3
RA2
RB2
RA1
RA0
(5)
RB7
RB6
RB5
RB1 RB0/INT xxxx xxxx
07h
—
Unimplemented location, read as '0'
EEPROM Data Register
—
08h EEDATA
09h EEADR
xxxx xxxx 13,14
xxxx xxxx 13,14
EEPROM Address Register
(1)
0Ah
11
PCLATH
—
—
—
Write Buffer for upper 5 bits of the PC
INTE RBIE T0IF INTF
---0 0000
0Bh INTCON
Bank 1
GIE
EEIE
T0IE
RBIF
0000 000x
10
80h INDF
Uses Contents of FSR to address Data Memory (not a physical register)
---- ----
11
9
81h
82h PCL
83h
OPTION_REG RBPU INTEDG
Low order 8 bits of Program Counter (PC)
IRP RP1 RP0 TO
Indirect data memory address pointer 0
PORTA Data Direction Register
PORTB Data Direction Register
Unimplemented location, read as '0'
EEIF
EEPROM Control Register 2 (not a physical register)
T0CS
T0SE
PSA
PS2
PS1
PS0
C
1111 1111
0000 0000
11
8
(2)
STATUS
PD
Z
DC
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
—
84h FSR
85h TRISA
86h TRISB
87h
11
16
18
—
13
14
—
—
—
—
88h EECON1
—
—
—
WRERR WREN
WR
RD
---0 x000
89h
0Ah
EECON2
PCLATH
---- ----
(1)
11
10
—
—
—
Write buffer for upper 5 bits of the PC
INTE RBIE T0IF
---0 0000
0000 000x
0Bh INTCON
GIE
EEIE
T0IE
INTF
RBIF
Legend: x= unknown, u= unchanged. -= unimplemented, read as '0', q= value depends on condition
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> are never trans-
ferred to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR Reset.
3: Other (non power-up) RESETS include: external RESET through MCLR and the Watchdog Timer Reset.
4: On any device RESET, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
2001 Microchip Technology Inc.
DS35007B-page 7
PIC16F84A
2.3.1
STATUS REGISTER
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16F84A and
should be programmed as cleared. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bit for
data memory.
As with any register, the STATUS register can be the
destination for any instruction. If the STATUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
3: When the STATUS register is the
destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 7-2),
because these instructions do not affect any status bit.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7-6
Unimplemented: Maintain as ‘0’
bit 5
RP0: Register Bank Select bits (used for direct addressing)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow, the polarity
is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is
reversed)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note: A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
DS35007B-page 8
2001 Microchip Technology Inc.
PIC16F84A
2.3.2
OPTION REGISTER
Note: When the prescaler is assigned to
the WDT (PSA = ’1’), TMR0 has a 1:1
prescaler assignment.
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
REGISTER 2-2:
OPTION REGISTER (ADDRESS 81h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
2001 Microchip Technology Inc.
DS35007B-page 9
PIC16F84A
2.3.3
INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON register is a readable and writable
register that contains the various enable bits for all
interrupt sources.
REGISTER 2-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
EEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
EEIE: EE Write Complete Interrupt Enable bit
1= Enables the EE Write Complete interrupts
0= Disables the EE Write Complete interrupt
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS35007B-page 10
2001 Microchip Technology Inc.
PIC16F84A
2.4
PCL and PCLATH
2.5
Indirect Addressing; INDF and
FSR Registers
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. If the pro-
gram counter (PC) is modified or a conditional test is
true, the instruction requires two cycles. The second
cycle is executed as a NOP. All updates to the PCH reg-
ister go through the PCLATH register.
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
EXAMPLE 2-1:
INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
2.4.1
STACK
• A read of the INDF register will return the value
of 10h
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah.
Mid-range devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
EXAMPLE 2-2:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw
movwf
0x20
;initialize pointer
;to RAM
FSR
NEXT
clrf
incf
btfss
goto
INDF
FSR
FSR,4
NEXT
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
:
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-3. However, IRP is not used in the
PIC16F84A.
2001 Microchip Technology Inc.
DS35007B-page 11
PIC16F84A
FIGURE 2-3:
DIRECT/INDIRECT ADDRESSING
Indirect Addressing
Direct Addressing
From Opcode
(FSR)
RP1 RP0
6
0
IRP
7
0
(2)
(2)
Bank Select
Location Select
Location Select
Bank Select
00
01
00h
80h
0Bh
0Ch
Addresses
map back to
Bank 0
Data
(1)
Memory
4Fh
50h
(3)
(3)
7Fh
FFh
Bank 0
Note 1: For memory map detail, see Figure 2-2.
Bank 1
2: Maintain as clear for upward compatibility with future products.
3: Not implemented.
DS35007B-page 12
2001 Microchip Technology Inc.
PIC16F84A
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
3.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
• EECON1
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
• EECON2 (not a physically implemented register)
• EEDATA
• EEADR
Additional information on the Data EEPROM is avail-
able in the PICmicro™ Mid-Range Reference Manual
(DS33023).
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC16F84A devices have 64 bytes of
data EEPROM with an address range from 0h to 3Fh.
REGISTER 3-1:
EECON1 REGISTER (ADDRESS 88h)
U-0
—
U-0
—
U-0
—
R/W-0
EEIF
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
WRERR
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR Reset or any WDT Reset during normal operation)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
WR: Write Control bit
1= Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2001 Microchip Technology Inc.
DS35007B-page 13
PIC16F84A
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental writes
to data EEPROM due to errant (unexpected) code exe-
cution (i.e., lost programs). The user should keep the
WREN bit clear at all times, except when updating
EEPROM. The WREN bit is not cleared by hardware.
3.1
Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore, it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 3-1:
DATA EEPROM READ
BCF
STATUS, RP0 ; Bank 0
MOVLW
MOVWF
BSF
BSF
BCF
CONFIG_ADDR
EEADR
STATUS, RP0 ; Bank 1
EECON1, RD ; EE Read
STATUS, RP0 ; Bank 0
;
; Address to read
3.3
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 3-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
MOVF
EEDATA, W
; W = EEDATA
3.2
Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
Generally, the EEPROM write failure will be a bit which
was written as a ’0’, but reads back as a ’1’ (due to
leakage off the bit).
EXAMPLE 3-3:
WRITE VERIFY
EXAMPLE 3-2:
DATA EEPROM WRITE
BCF STATUS,RP0 ; Bank 0
:
:
MOVF EEDATA,W
BSF STATUS,RP0 ; Bank 1
BSF
BCF
BSF
STATUS, RP0 ; Bank 1
INTCON, GIE ; Disable INTs.
EECON1, WREN ; Enable Write
; Any code
; can go here
; Must be in Bank 0
MOVLW
55h
;
MOVWF
MOVLW
MOVWF
BSF
EECON2
AAh
EECON2
EECON1,WR
; Write 55h
;
; Write AAh
; Set WR bit
READ
BSF EECON1,RD ; YES, Read the
; value written
BCF STATUS,RP0 ; Bank 0
;
;
begin write
BSF
INTCON, GIE ; Enable INTs.
; Is the value written
; (in W reg) and
; read (in EEDATA)
; the same?
;
;
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
SUBWFEEDATA,W
BTFSSSTATUS,Z
; Is difference 0?
GOTO WRITE_ERR ; NO, Write error
TABLE 3-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on
Power-on
Reset
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
09h
88h
89h
EEDATA EEPROM Data Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 x000 ---0 q000
---- ---- ---- ----
EEADR
EEPROM Address Register
EECON1
—
—
—
EEIF WRERR WREN
WR
RD
EECON2 EEPROM Control Register 2
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0', q= value depends upon condition.
Shaded cells are not used by data EEPROM.
DS35007B-page 14
2001 Microchip Technology Inc.
PIC16F84A
FIGURE 4-1:
BLOCK DIAGRAM OF
PINS RA3:RA0
4.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
D
Q
VDD
P
WR
Additional information on I/O ports may be found in the
PICmicro™ Mid-Range Reference Manual (DS33023).
Port
Q
CK
Data Latch
4.1
PORTA and TRISA Registers
I/O pin
N
PORTA is a 5-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
D
Q
WR
TRIS
VSS
Q
CK
TRIS Latch
TTL
Input
Buffer
Note: On a Power-on Reset, these pins are con-
figured as inputs and read as '0'.
RD TRIS
Q
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read. This value is modified and then written to the port
data latch.
D
EN
RD Port
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Note: I/O pins have protection diodes to VDD and VSS.
FIGURE 4-2:
BLOCK DIAGRAM OF PIN
RA4
EXAMPLE 4-1:
INITIALIZING PORTA
Data
Bus
BCF
CLRF
STATUS,RP0 ;
PORTA
D
Q
; Initialize PORTA by
; clearing output
; data latches
WR
Port
Q
CK
RA4 pin
N
BSF
STATUS,RP0 ; Select Bank 1
Data Latch
MOVLW
0x0F
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA4 as output
VSS
D
Q
Q
WR
TRIS
MOVWF
TRISA
CK
; TRISA<7:5> are always
; read as ’0’.
TRIS Latch
Schmitt
Trigger
Input
Buffer
RD TRIS
Q
D
EN
RD Port
TMR0 Clock Input
Note: I/O pins have protection diodes to VDD and VSS.
2001 Microchip Technology Inc.
DS35007B-page 15
PIC16F84A
TABLE 4-1:
PORTA FUNCTIONS
Name
Bit0
Buffer Type
Function
RA0
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Input/output
Input/output
Input/output
Input/output
RA1
RA2
RA3
RA4/T0CKI
Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
Power-on
Reset
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
PORTA
—
—
—
—
—
—
RA4/T0CKI
RA3
RA2
RA1
RA0
---x xxxx ---u uuuu
85h
TRISA
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are unimplemented, read as '0'.
DS35007B-page 16
2001 Microchip Technology Inc.
PIC16F84A
FIGURE 4-3:
BLOCK DIAGRAM OF
PINS RB7:RB4
4.2
PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
VDD
RBPU(1)
Weak
P
Pull-up
Data Latch
Data Bus
WR Port
D
Q
I/O pin(2)
CK
TRIS Latch
EXAMPLE 4-2:
BCF
CLRF
INITIALIZING PORTB
D
Q
STATUS,RP0 ;
PORTB
; Initialize PORTB by
; clearing output
; data latches
WR TRIS
TTL
Input
Buffer
CK
BSF
STATUS,RP0 ; Select Bank 1
MOVLW
0xCF
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
RD TRIS
RD Port
Latch
Q
D
MOVWF
TRISB
EN
Set RBIF
Q
D
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset.
From other
RB7:RB4 pins
EN
RD Port
Note 1: TRISB = ’1’ enables weak pull-up
(if RBPU = ’0’ in the OPTION_REG register).
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
2: I/O pins have diode protection to VDD and VSS.
FIGURE 4-4:
BLOCK DIAGRAM OF
PINS RB3:RB0
VDD
RBPU(1)
Weak
P
Pull-up
Data Latch
Data Bus
WR Port
D
Q
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
I/O pin(2)
CK
TRIS Latch
a) Any read or write of PORTB. This will end the
mismatch condition.
D
Q
TTL
Input
Buffer
WR TRIS
CK
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
RD TRIS
RD Port
D
Q
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
EN
RB0/INT
Schmitt Trigger
Buffer
RD Port
Note 1: TRISB = ’1’ enables weak pull-up
(if RBPU = ’0’ in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
DS35007B-page 17
PIC16F84A
TABLE 4-3:
PORTB FUNCTIONS
Name
Bit
Buffer Type
I/O Consistency Function
Input/output pin or external interrupt input.
RB0/INT
bit0
TTL/ST(1)
Internal software programmable weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial programming clock.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 4-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
Power-on
Reset
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h
86h
81h
PORTB
TRISB
OPTION_REG RBPU INTEDG T0CS
GIE EEIE T0IE
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT xxxx xxxx uuuu uuuu
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
T0SE
INTE
PSA
PS2
T0IF
PS1
PS0
1111 1111 1111 1111
0000 000x 0000 000u
0Bh,8Bh INTCON
RBIE
INTF
RBIF
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS35007B-page 18
2001 Microchip Technology Inc.
PIC16F84A
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
Additional information on external clock requirements
is available in the PICmicro™ Mid-Range Reference
Manual, (DS33023).
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt-on-overflow from FFh to 00h
5.2
Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module, or as a postscaler for the Watchdog Timer,
respectively (Figure 5-2). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet. Note that there is only one prescaler available
which is mutually exclusively shared between the Timer0
module and the Watchdog Timer. Thus, a prescaler
assignment for the Timer0 module means that there is no
prescaler for the Watchdog Timer, and vice-versa.
Figure 5-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual
(DS33023).
5.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler is not readable or writable.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
Setting bit PSA will assign the prescaler to the Watchdog
Timer (WDT). When the prescaler is assigned to the
WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,etc.) will clear the prescaler. When assigned to
WDT, a CLRWDT instruction will clear the prescaler
along with the WDT.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
FIGURE 5-1:
TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
1
PSOUT
8
1
0
Sync with
Internal
Clocks
TMR0
Programmable
Prescaler
RA4/T0CKI
pin
PSOUT
(2 Cycle Delay)
T0SE
3
Set Interrupt
Flag bit T0IF
on Overflow
PS2, PS1, PS0
PSA
T0CS
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).
2001 Microchip Technology Inc.
DS35007B-page 19
PIC16F84A
5.2.1
SWITCHING PRESCALER
ASSIGNMENT
5.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut-off during SLEEP.
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on the fly” during program
execution).
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range Reference Man-
ual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
FIGURE 5-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT (= FOSC/4)
Data Bus
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
TMR0 reg
2
Cycles
T0SE
T0CS
Set Flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1 MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
POR,
BOR
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
INTCON
Timer0 Module Register
GIE EEIE T0IE
xxxx xxxx uuuu uuuu
RBIF 0000 000x 0000 000u
0Bh,8Bh
81h
INTE
RBIE
PSA
T0IF
PS2
INTF
PS1
OPTION_REG RBPU INTEDG T0CS T0SE
TRISA
PS0
1111 1111 1111 1111
---1 1111 ---1 1111
85h
—
—
—
PORTA Data Direction Register
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS35007B-page 20
2001 Microchip Technology Inc.
PIC16F84A
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay of 72 ms (nominal) on power-up
only. This design keeps the device in RESET while the
power supply stabilizes. With these two timers on-chip,
most applications need no external RESET circuitry.
6.0
SPECIAL FEATURES OF THE
CPU
What sets
a
microcontroller apart from other
processors are special circuits to deal with the needs of
real time applications. The PIC16F84A has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These features are:
SLEEP mode offers a very low current power-down
mode. The user can wake-up from SLEEP through
external RESET, Watchdog Timer Time-out or through
an interrupt. Several oscillator options are provided to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select the various options.
• OSC Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
Additional information on special features is available
in the PICmicro™ Mid-Range Reference Manual
(DS33023).
• Watchdog Timer (WDT)
• SLEEP
6.1
Configuration Bits
• Code Protection
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in
program memory location 2007h.
• ID Locations
• In-Circuit Serial Programming™ (ICSP™)
The PIC16F84A has a Watchdog Timer which can be
shut-off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
Address 2007h is beyond the user program memory
space and it belongs to the special test/configuration
memory space (2000h - 3FFFh). This space can only
be accessed during programming.
REGISTER 6-1:
PIC16F84A CONFIGURATION WORD
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u
R/P-u R/P-u
R/P-u
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP PWRTE WDTE F0SC1 F0SC0
bit0
bit13
bit 13-4
bit 3
CP: Code Protection bit
1= Code protection disabled
0= All program memory is code protected
PWRTE: Power-up Timer Enable bit
1= Power-up Timer is disabled
0= Power-up Timer is enabled
bit 2
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
2001 Microchip Technology Inc.
DS35007B-page 21
PIC16F84A
FIGURE 6-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
6.2
Oscillator Configurations
OSCILLATOR TYPES
6.2.1
CONFIGURATION)
The PIC16F84A can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
OSC1
Clock from
Ext. System
PIC16FXX
• LP
• XT
• HS
• RC
Low Power Crystal
Open
OSC2
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
TABLE 6-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
6.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
Ranges Tested:
Mode
In XT, LP, or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 6-1).
Freq
OSC1/C1
OSC2/C2
XT
455 kHz
2.0 MHz
4.0 MHz
47 - 100 pF 47 - 100 pF
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
FIGURE 6-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP OSC
CONFIGURATION)
HS
8.0 MHz
15 - 33 pF 15 - 33 pF
15 - 33 pF 15 - 33 pF
10.0 MHz
Note: Recommended values of C1 and C2 are
identical to the ranges tested in this table.
Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for the
appropriate values of external compo-
nents.
C1(1)
OSC1
To
Internal
Logic
XTAL
(3)
RF
OSC2
SLEEP
PIC16FXX
(2)
RS
C2(1)
Note 1: See Table 6-1 for recommended values
of C1 and C2.
2: A series resistor (RS) may be required
Note: When using resonators with frequencies
above 3.5 MHz, the use of HS mode rather
than XT mode, is recommended. HS mode
may be used at any VDD for which the
controller is rated.
for AT strip cut crystals.
The PIC16F84A oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a
frequency out of the crystal manufacturers
specifications. When in XT, LP, or HS modes, the
device can have an external clock source to drive the
OSC1/CLKIN pin (Figure 6-2).
DS35007B-page 22
2001 Microchip Technology Inc.
PIC16F84A
TABLE 6-2:
CAPACITOR SELECTION
6.2.3
RC OSCILLATOR
FOR CRYSTAL OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) values, capacitor (CEXT) values, and
the operating temperature. In addition to this, the oscil-
lator frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types also affects the oscillation frequency, especially
for low CEXT values. The user needs to take into
account variation, due to tolerance of the external
R and C components. Figure 6-3 shows how an R/C
combination is connected to the PIC16F84A.
Mode
Freq
OSC1/C1
OSC2/C2
LP
32 kHz
200 kHz
68 - 100 pF
15 - 33 pF
68 - 100 pF
15 - 33 pF
XT
HS
100 kHz
2 MHz
4 MHz
100 - 150 pF 100 - 150 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
4 MHz
20 MHz
15 - 33 pF
15 - 33 pF
15 - 33 pF
15 - 33 pF
Note: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode, as well as XT mode, to avoid over-
driving crystals with low drive level specifi-
cation. Since each crystal has its own
characteristics, the user should consult the
crystal manufacturer for appropriate
values of external components.
FIGURE 6-3:
RC OSCILLATOR MODE
VDD
REXT
Internal
OSC1
Clock
For VDD > 4.5V, C1 = C2 ≈ 30 pF is recom-
mended.
CEXT
VSS
PIC16FXX
OSC2/CLKOUT
FOSC/4
Recommended values: 5 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
2001 Microchip Technology Inc.
DS35007B-page 23
PIC16F84A
Some registers are not affected in any RESET condition;
their status is unknown on a POR and unchanged in any
other RESET. Most other registers are reset to a “RESET
state” on POR, MCLR or WDT Reset during normal oper-
ation and on MCLR during SLEEP. They are not affected
by a WDT Reset during SLEEP, since this RESET is
viewed as the resumption of normal operation.
6.3
RESET
The PIC16F84A differentiates between various kinds
of RESET:
• Power-on Reset (POR)
• MCLR during normal operation
• MCLR during SLEEP
Table 6-3 gives a description of RESET conditions for
the program counter (PC) and the STATUS register.
Table 6-4 gives a full description of RESET states for all
registers.
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
Figure 6-4 shows a simplified block diagram of the
On-Chip RESET Circuit. The MCLR Reset path has a
noise filter to ignore small pulses. The electrical speci-
fications state the pulse width requirements for the
MCLR pin.
The TO and PD bits are set or cleared differently in dif-
ferent RESET situations (Section 6.7). These bits are
used in software to determine the nature of the RESET.
FIGURE 6-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
SLEEP
WDT
Time-out
Reset
WDT
Module
VDD Rise
Detect
S
Power-on Reset
VDD
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
Q
R
OSC1/
CLKIN
PWRT
10-bit Ripple Counter
On-Chip
(1)
RC Osc
See Table 6-5
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 6-5.
TABLE 6-3:
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition
Program Counter
STATUS Register
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
uuu1 0uuu
Power-on Reset
000h
000h
MCLR during normal operation
MCLR during SLEEP
000h
WDT Reset (during normal operation)
WDT Wake-up
000h
PC + 1
PC + 1(1)
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
DS35007B-page 24
2001 Microchip Technology Inc.
PIC16F84A
TABLE 6-4:
Register
RESET CONDITIONS FOR ALL REGISTERS
MCLR during:
– normal operation
– SLEEP
Wake-up from SLEEP:
– through interrupt
Address
Power-on Reset
WDT Reset during
normal operation
– through WDT Time-out
W
—
xxxx xxxx
---- ----
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---0 0000
0000 000x
---- ----
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
---0 x000
---- ----
---0 0000
0000 000x
uuuu uuuu
---- ----
uuuu uuuu
0000 0000
000q quuu(3)
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---0 0000
0000 000u
---- ----
1111 1111
0000 0000
000q quuu(3)
uuuu uuuu
---1 1111
1111 1111
---0 q000
---- ----
---0 0000
0000 000u
uuuu uuuu
---- ----
uuuu uuuu
PC + 1(2)
INDF
00h
01h
02h
03h
04h
05h
06h
08h
09h
0Ah
0Bh
80h
81h
82h
83h
84h
85h
86h
88h
89h
8Ah
8Bh
TMR0
PCL
STATUS
uuuq quuu(3)
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu(1)
---- ----
uuuu uuuu
PC + 1(2)
uuuq quuu(3)
uuuu uuuu
---u uuuu
uuuu uuuu
---0 uuuu
---- ----
---u uuuu
uuuu uuuu(1)
FSR
PORTA(4)
PORTB(5)
EEDATA
EEADR
PCLATH
INTCON
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
EECON1
EECON2
PCLATH
INTCON
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: Table 6-3 lists the RESET value for each specific condition.
4: On any device RESET, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
2001 Microchip Technology Inc.
DS35007B-page 25
PIC16F84A
6.4
Power-on Reset (POR)
6.6
Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for VDD
must be met for this to operate properly. See Electrical
Specifications for details.
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 6-6, Figure 6-7, Figure 6-8
and Figure 6-9). This ensures the crystal oscillator or
resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case
(Figure 6-9), an external Power-on Reset circuit may
be necessary (Figure 6-5).
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
FIGURE 6-5:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
The POR circuit does not produce an internal RESET
when VDD declines.
VDD
D
VDD
6.5
Power-up Timer (PWRT)
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (TPWRT) from POR (Figures 6-6
through 6-9). The Power-up Timer operates on an
internal RC oscillator. The chip is kept in RESET as
long as the PWRT is active. The PWRT delay allows
the VDD to rise to an acceptable level (possible excep-
tion shown in Figure 6-9).
R
R1
MCLR
PIC16FXX
C
Note 1: External Power-on Reset circuit is required
only if VDD power-up rate is too slow. The
A configuration bit, PWRTE, can enable/disable the
PWRT. See Register 6-1 for the operation of the
PWRTE bit for a particular device.
diode
D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 µA). A larger voltage drop will
degrade VIH level on the MCLR pin.
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
3: R1 = 100Ω to 1 kΩ will limit any current flow-
ing into MCLR from external capacitor C, in
the event of a MCLR pin breakdown due to
ESD or EOS.
DS35007B-page 26
2001 Microchip Technology Inc.
PIC16F84A
FIGURE 6-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 6-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 6-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
2001 Microchip Technology Inc.
DS35007B-page 27
PIC16F84A
FIGURE 6-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD):
SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high, execution will begin immediately
6.7
Time-out Sequence and
Power-down Status Bits (TO/PD)
On power-up (Figures 6-6 through 6-9), the time-out
sequence is as follows:
(Figure 6-6). This is useful for testing purposes or to
synchronize more than one PIC16F84A device when
operating in parallel.
1. PWRT time-out is invoked after a POR has
expired.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the RESET conditions for some special
registers, while Table 6-4 lists the RESET conditions
for all the registers.
2. Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and PWRTE configuration bit status. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
TABLE 6-6:
STATUS BITS AND THEIR
SIGNIFICANCE
TABLE 6-5:
TIME-OUT IN VARIOUS
SITUATIONS
TO PD
Condition
1
0
x
0
0
1
1
1
x
0
1
0
1
0
Power-on Reset
Power-up
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset (during normal operation)
WDT Wake-up
Wake-up
Oscillator
Configuration
from
PWRT
Enabled
PWRT
Disabled
SLEEP
72 ms +
1024TOSC
XT, HS, LP
RC
1024TOSC 1024TOSC
MCLR during normal operation
MCLR during SLEEP or interrupt
wake-up from SLEEP
72 ms
—
—
DS35007B-page 28
2001 Microchip Technology Inc.
PIC16F84A
6.8.1
INT INTERRUPT
6.8
Interrupts
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the Interrupt Service
Routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 6.11) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
The PIC16F84A has 4 sources of interrupt:
• External interrupt RB0/INT pin
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
• Data EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on RESET.
6.8.2
TMR0 INTERRUPT
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
An overflow (FFh → 00h) in TMR0 will set flag bit T0IF
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 5.0).
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
6.8.3
PORTB INTERRUPT
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The
exact latency depends when the interrupt event occurs.
The latency is the same for both one and two cycle
instructions. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 4.2).
Note: For a change on the I/O pin to be
recognized, the pulse width must be at
least TCY wide.
6.8.4
DATA EEPROM INTERRUPT
At the completion of a data EEPROM write cycle, flag
bit EEIF (EECON1<4>) will be set. The interrupt can be
enabled/disabled by setting/clearing enable bit EEIE
(INTCON<6>) (Section 3.0).
Note: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
FIGURE 6-10:
INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt to CPU
RBIF
RBIE
EEIF
EEIE
GIE
2001 Microchip Technology Inc.
DS35007B-page 29
PIC16F84A
Example 6-1 does the following:
6.9
Context Saving During Interrupts
a) Stores the W register.
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and
STATUS register). This is implemented in software.
b) Stores the STATUS register in STATUS_TEMP.
c) Executes the Interrupt Service Routine code.
d) Restores the STATUS (and bank select bit)
register.
The code in Example 6-1 stores and restores the
STATUS and W register’s values. The user defined
registers, W_TEMP and STATUS_TEMP are the tem-
porary storage locations for the W and STATUS
registers values.
e) Restores the W register.
EXAMPLE 6-1:
SAVING STATUS AND W REGISTERS IN RAM
PUSH
MOVWF
W_TEMP
; Copy W to TEMP register,
SWAPF
MOVWF
:
STATUS,
STATUS_TEMP
W
; Swap status to be saved into W
; Save status to STATUS_TEMP register
:
ISR
:
:
:
; Interrupt Service Routine
; should configure Bank as required
;
POP
SWAPF
STATUS_TEMP,W
STATUS
; Swap nibbles in STATUS_TEMP register
; and place result into W
; Move W into STATUS register
; (sets bank to original state)
; Swap nibbles in W_TEMP and place result in W_TEMP
; Swap nibbles in W_TEMP and place result into W
MOVWF
SWAPF
SWAPF
W_TEMP,
W_TEMP,
F
W
6.10.1
WDT PERIOD
6.10 Watchdog Timer (WDT)
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
The Watchdog Timer is a free running On-Chip RC
Oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation, a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a '0' (Section 6.1).
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out and generating a device
RESETcondition.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
DS35007B-page 30
2001 Microchip Technology Inc.
PIC16F84A
6.10.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., Max.
WDT Prescaler), it may take several seconds before a
WDT time-out occurs.
FIGURE 6-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-2)
0
M
Postscaler
8
1
U
WDT Timer
•
X
PS2:PS0
8 - to -1 MUX
PSA
WDT
Enable Bit
•
To TMR0 (Figure 5-2)
1
0
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 6-7:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on Value on all
Addr
Name
Bit 7
(2)
Bit 6
(2)
Bit 5
(2)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
Reset
other
RESETS
(1)
2007h Config. bits
(2)
PWRTE
PSA
WDTE FOSC1 FOSC0
PS2 PS1 PS0
(2)
81h
OPTION_REG RBPU INTEDG T0CS
T0SE
1111 1111 1111 1111
Legend: x= unknown. Shaded cells are not used by the WDT.
Note 1: See Register 6-1 for operation of the PWRTE bit.
2: See Register 6-1 and Section 6.12 for operation of the code and data protection bits.
2001 Microchip Technology Inc.
DS35007B-page 31
PIC16F84A
6.11.2
WAKE-UP FROM SLEEP
6.11 Power-down Mode (SLEEP)
The device can wake-up from SLEEP through one of
the following events:
A device may be powered down (SLEEP) and later
powered up (wake-up from SLEEP).
1. External RESET input on MCLR pin.
2. WDT wake-up (if WDT was enabled).
6.11.1
SLEEP
The Power-down mode is entered by executing the
SLEEPinstruction.
3. Interrupt from RB0/INT pin, RB port change, or
data EEPROM write complete.
If enabled, the Watchdog Timer is cleared (but keeps
running), the PD bit (STATUS<3>) is cleared, the TO bit
(STATUS<4>) is set, and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEPinstruction was executed (driving high, low,
or hi-impedance).
Peripherals cannot generate interrupts during SLEEP,
since no on-chip Q clocks are present.
The first event (MCLR Reset) will cause a device
RESET. The two latter events are considered a contin-
uation of program execution. The TO and PD bits can
be used to determine the cause of a device RESET.
The PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The TO bit is cleared if a WDT
time-out occurred (and caused wake-up).
For the lowest current consumption in SLEEP mode,
place all I/O pins at either VDD or VSS, with no external
circuitry drawing current from the I/O pins, and disable
external clocks. I/O pins that are hi-impedance inputs
should be pulled high or low externally to avoid switch-
ing currents caused by floating inputs. The T0CKI input
should also be at VDD or VSS. The contribution from
on-chip pull-ups on PORTB should be considered.
While the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEPinstruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEPinstruction.
The MCLR pin must be at a logic high level (VIHMC).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
FIGURE 6-12:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTF Flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC+2
PC + 2
PC
PC+1
PC+2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(PC + 1)
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(0005h)
Inst(0004h)
Fetched
Instruction
Executed
Dummy cycle
SLEEP
Dummy cycle
Note 1: XT, HS, or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
DS35007B-page 32
2001 Microchip Technology Inc.
PIC16F84A
6.11.3
WAKE-UP USING INTERRUPTS
6.12 Program Verification/Code
Protection
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
6.13 ID Locations
Four memory locations (2000h - 2004h) are designated
as ID locations to store checksum or other code
identification numbers. These locations are not
accessible during normal execution but are readable
and writable only during program/verify. Only the
four Least Significant bits of ID location are usable.
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
6.14 In-Circuit Serial Programming
PIC16F84A microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. Customers can manufacture boards with
unprogrammed devices, and then program the
microcontroller just before shipping the product,
allowing the most recent firmware or custom firmware
to be programmed.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
For complete details of Serial Programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Guide, (DS30277).
2001 Microchip Technology Inc.
DS35007B-page 33
PIC16F84A
NOTES:
DS35007B-page 34
2001 Microchip Technology Inc.
PIC16F84A
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
7.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word, divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 7-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 7-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
Table 7-2 lists the instructions recognized by the
MPASM™ Assembler.
Figure 7-1 shows the general formats that the instruc-
tions can have.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTIONand TRISinstructions.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the address of the
file in which the bit is located.
All examples use the following format to represent a
hexadecimal number:
0xhh
For literal and control operations, ’k’ represents an
where h signifies a hexadecimal digit.
eight or eleven bit constant or literal value.
FIGURE 7-1:
GENERAL FORMAT FOR
INSTRUCTIONS
TABLE 7-1:
OPCODE FIELD
DESCRIPTIONS
Byte-oriented file register operations
13
8
7
6
0
Field
Description
OPCODE
d
f (FILE #)
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit address within an 8-bit file register
Literal field, constant data or label
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
Don't care location (= 0or 1)
OPCODE
f (FILE #)
The assembler will generate code with x = 0.
It is the recommended form of use for compat-
ibility with all Microchip software tools.
b = 3-bit bit address
f = 7-bit file register address
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Literal and control operations
General
PC
TO
PD
Program Counter
Time-out bit
13
8
7
0
0
OPCODE
k (literal)
Power-down bit
k = 8-bit immediate value
The instruction set is highly orthogonal and is grouped
into three basic categories:
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
• Byte-oriented operations
• Bit-oriented operations
k (literal)
• Literal and control operations
A description of each instruction is available in the
PICmicro™ Mid-Range Reference Manual (DS33023).
2000 Microchip Technology Inc.
DS35007B-page 35
PIC16F84A
TABLE 7-2:
PIC16CXXX INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1 (2)
1
1 (2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
1,2
1,2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
DS35007B-page 36
2000 Microchip Technology Inc.
PIC16F84A
7.1
Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[label] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[label] BCF f,b
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
(W) + k → (W)
C, DC, Z
Operation:
0 → (f<b>)
Status Affected:
Description:
None
The contents of the W register
are added to the eight-bit literal ’k’
and the result is placed in the W
register.
Bit 'b' in register 'f' is cleared.
BSF
Bit Set f
ADDWF
Add W and f
Syntax:
[label] BSF f,b
Syntax:
[label] ADDWF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
d
[0,1]
Operation:
1 → (f<b>)
Operation:
(W) + (f) → (destination)
Status Affected:
Description:
None
Status Affected: C, DC, Z
Bit 'b' in register 'f' is set.
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in
register ’f’.
ANDLW
AND Literal with W
BTFSS
Bit Test f, Skip if Set
Syntax:
[label] ANDLW
k
Syntax:
[label] BTFSS f,b
Operands:
Operation:
Status Affected:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
(W) .AND. (k) → (W)
Operation:
skip if (f<b>) = 1
Z
Status Affected: None
The contents of W register are
AND’ed with the eight-bit literal
'k'. The result is placed in the W
register.
Description: If bit 'b' in register 'f' is '0', the next
instruction is executed.
If bit 'b' is '1', then the next instruc-
tion is discarded and a NOPis exe-
cuted instead, making this a 2TCY
instruction.
ANDWF
AND W with f
Syntax:
[label] ANDWF f,d
0 ≤ f ≤ 127
Operands:
d
[0,1]
Operation:
(W) .AND. (f) → (destination)
Status Affected:
Description:
Z
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
2000 Microchip Technology Inc.
DS35007B-page 37
PIC16F84A
BTFSC
Bit Test, Skip if Clear
CLRWDT
Clear Watchdog Timer
Syntax:
[label] BTFSC f,b
Syntax:
[ label ] CLRWDT
None
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
skip if (f<b>) = 0
Status Affected: None
1 → PD
Description:
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
Status Affected: TO, PD
If bit ’b’ in register ’f’ is ’0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
2TCY instruction.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
Syntax:
[ label ] COMF f,d
Operands:
Operation:
0 ≤ k ≤ 2047
Operands:
0 ≤ f ≤ 127
d
[0,1]
(PC)+ 1→ TOS,
k → PC<10:0>,
Operation:
(f) → (destination)
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Description:
Z
Status Affected: None
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two-cycle instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[label] DECF f,d
Syntax:
[label] CLRF
f
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
0 ≤ f ≤ 127
d
[0,1]
00h → (f)
1 → Z
Operation:
(f) - 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
The contents of register ’f’ are
cleared and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
None
Operands:
Operation:
00h → (W)
1 → Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
DS35007B-page 38
2000 Microchip Technology Inc.
PIC16F84A
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(f) - 1 → (destination);
Operation:
(f) + 1 → (destination),
skip if result = 0
skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ’f’ are
Description:
The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in
register ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead,
making it a 2TCY instruction.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOPis executed instead, making
it a 2TCY instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR Literal with W
Syntax:
[ label ] GOTO k
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Operands:
Operation:
0 ≤ k ≤ 2047
Operands:
Operation:
Status Affected:
Description:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
(W) .OR. k → (W)
Z
Status Affected: None
The contents of the W register are
OR’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
Description:
GOTOis an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two-
cycle instruction.
IORWF
Inclusive OR W with f
INCF
Increment f
Syntax:
[ label ] IORWF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] INCF f,d
Operands:
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .OR. (f) → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Inclusive OR the W register with
register 'f'. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in
register 'f'.
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
2000 Microchip Technology Inc.
DS35007B-page 39
PIC16F84A
MOVF
Move f
RETFIE
Return from Interrupt
Syntax:
[ label ] MOVF f,d
Syntax:
[ label ] RETFIE
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
None
d
[0,1]
TOS → PC,
1 → GIE
Operation:
(f) → (destination)
Status Affected:
Description:
Z
Status Affected: None
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
RETLW
Return with Literal in W
MOVLW
Move Literal to W
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → (W)
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k → (W);
TOS → PC
None
Status Affected: None
The eight-bit literal ’k’ is loaded
into W register. The don’t cares
will assemble as 0’s.
Description:
The W register is loaded with the
eight-bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
RETURN
Return from Subroutine
MOVWF
Move W to f
Syntax:
[ label ] RETURN
None
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
TOS → PC
Status Affected: None
None
Description: Return from subroutine. The stack
Move data from W register to
register 'f'.
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
NOP
No Operation
Syntax:
[ label ] NOP
None
Operands:
Operation:
No operation
Status Affected: None
Description:
No operation.
DS35007B-page 40
2000 Microchip Technology Inc.
PIC16F84A
RLF
Rotate Left f through Carry
SUBLW
Subtract W from Literal
Syntax:
[ label ] RLF f,d
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
d
[0,1]
k - (W) → (W)
Operation:
See description below
C
Status Affected: C, DC, Z
Status Affected:
Description:
Description:
The W register is subtracted (2’s
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
C
Register f
RRF
Rotate Right f through Carry
SUBWF
Subtract W from f
Syntax:
[ label ] RRF f,d
Syntax:
[ label ] SUBWF f,d
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
Operands:
d
[0,1]
d
[0,1]
Operation:
See description below
C
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
Status Affected: C, DC, Z
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
C
Register f
SWAPF
Swap Nibbles in f
SLEEP
Syntax:
[ label ] SWAPF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] SLEEP
None
Operands:
Operands:
Operation:
d
[0,1]
00h → WDT,
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected: None
Status Affected:
Description:
TO, PD
Description: The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the result is placed in
register 'f'.
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
2000 Microchip Technology Inc.
DS35007B-page 41
PIC16F84A
XORLW
Exclusive OR Literal with W
XORWF
Exclusive OR W with f
Syntax:
[label] XORLW k
0 ≤ k ≤ 255
Syntax:
[label] XORWF f,d
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Description:
Operands:
d
[0,1]
(W) .XOR. k → (W)
Z
Operation:
(W) .XOR. (f) → (destination)
Status Affected:
Description:
Z
The contents of the W register
are XOR’ed with the eight-bit lit-
eral 'k'. The result is placed in
the W register.
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
DS35007B-page 42
2000 Microchip Technology Inc.
PIC16F84A
The MPLAB IDE allows you to:
8.0
DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
8.2
MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
8.1
MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
8.3
MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2001 Microchip Technology Inc.
DS35007B-page 43
PIC16F84A
8.4
MPLINK Object Linker/
MPLIB Object Librarian
8.6
MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows® environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
8.7
ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
8.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS35007B-page 44
2001 Microchip Technology Inc.
PIC16F84A
8.8
MPLAB ICD In-Circuit Debugger
8.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the FLASH devices. This feature, along
with Microchip’s In-Circuit Serial ProgrammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, single-stepping and setting break points.
Running at full speed enables testing hardware in real-
time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
8.9
PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
8.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM
bus and separate headers for connection to an LCD
module and a keypad.
8.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2001 Microchip Technology Inc.
DS35007B-page 45
PIC16F84A
8.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
8.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
8.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS35007B-page 46
2001 Microchip Technology Inc.
PIC16F84A
TABLE 8-1:
DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X X F 8 C 1 P I
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t l K a i E d v n a s d r a B o o m D e
2001 Microchip Technology Inc.
DS35007B-page 47
PIC16F84A
NOTES:
DS35007B-page 48
2001 Microchip Technology Inc.
PIC16F84A
9.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V
Voltage on MCLR with respect to VSS(1) .......................................................................................................-0.3 to +14V
Voltage on RA4 with respect to VSS ........................................................................................................... -0.3 to +8.5V
Total power dissipation(2) .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA..........................................................................................................................80 mA
Maximum current sourced by PORTA.....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB ..................................................................................................................100 mA
Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than
pulling this pin directly to VSS.
2: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2001 Microchip Technology Inc.
DS35007B-page 49
PIC16F84A
FIGURE 9-1:
PIC16F84A-20 VOLTAGE-FREQUENCY GRAPH
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
20 MHz
Frequency
FIGURE 9-2:
PIC16LF84A-04 VOLTAGE-
FREQUENCY GRAPH
FIGURE 9-3:
PIC16F84A-04 VOLTAGE-
FREQUENCY GRAPH
6.0V
5.5V
6.0V
5.5V
5.0V
4.5V
4.0V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
3.5V
3.0V
2.5V
2.0V
2.0V
4 MHz
10 MHz
Frequency
4 MHz
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz
Frequency
Note 1: VDDAPPMIN is the minimum voltage of the
®
PICmicro device in the application.
2: FMAX has a maximum frequency of 10 MHz.
DS35007B-page 50
2001 Microchip Technology Inc.
PIC16F84A
9.1
DC Characteristics
Standard Operating Conditions (unless otherwise stated)
PIC16LF84A-04
(Commercial, Industrial)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
PIC16F84A-04
Standard Operating Conditions (unless otherwise stated)
(Commercial, Industrial, Extended)
PIC16F84A-20
(Commercial, Industrial, Extended)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
VDD
Supply Voltage
D001
16LF84A 2.0
—
5.5
V
XT, RC, and LP osc configuration
D001
D001A
16F84A 4.0
4.5
—
—
5.5
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002 VDR
RAM Data Retention
Voltage (Note 1)
1.5
—
—
V
Device in SLEEP mode
D003 VPOR
VDD Start Voltage to ensure
internal Power-on Reset
signal
—
Vss
—
V
See section on Power-on Reset for details
D004 SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05
—
—
4
V/ms
IDD
Supply Current (Note 2)
D010
16LF84A
—
1
mA RC and XT osc configuration (Note 4)
FOSC = 2.0 MHz, VDD = 5.5V
D010
16F84A
—
—
1.8
3
4.5
10
mA RC and XT osc configuration (Note 4)
FOSC = 4.0 MHz, VDD = 5.5V
mA RC and XT osc configuration (Note 4)
FOSC = 4.0 MHz, VDD = 5.5V
D010A
(During FLASH programming)
D013
D014
—
—
10
15
20
45
mA HS osc configuration (PIC16F84A-20)
FOSC = 20 MHz, VDD = 5.5V
16LF84A
µA LP osc configuration
FOSC = 32 kHz, VDD = 2.0V, WDT disabled
Legend: Rows with standard voltage device data only are shaded for improved readability.
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
NR Not rated for operation.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD,
T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula IR = VDD/2REXT (mA) with REXT in kOhm.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD measurement.
2001 Microchip Technology Inc.
DS35007B-page 51
PIC16F84A
9.1
DC Characteristics (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF84A-04
(Commercial, Industrial)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
PIC16F84A-04
Standard Operating Conditions (unless otherwise stated)
(Commercial, Industrial, Extended)
PIC16F84A-20
(Commercial, Industrial, Extended)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
IPD
Power-down Current (Note 3)
D020
D020
16LF84A
16F84A-20
16F84A-04
D021A
16LF84A
—
0.4
1.0
µA VDD = 2.0V, WDT disabled, industrial
D021A
16F84A-20
16F84A-04
—
—
1.5
1.0
3.5
3.0
µA VDD = 4.5V, WDT disabled, industrial
µA VDD = 4.0V, WDT disabled, industrial
D021B
16F84A-20
16F84A-04
—
—
1.5
1.0
5.5
5.0
µA VDD = 4.5V, WDT disabled, extended
µA VDD = 4.0V, WDT disabled, extended
Module Differential Current
(Note 5)
D022 ∆IWDT
Watchdog Timer
—
—
—
—
—
.20
3.5
3.5
4.8
4.8
16
20
28
25
30
µA VDD = 2.0V, Industrial, Commercial
µA VDD = 4.0V, Commercial
µA VDD = 4.0V, Industrial, Extended
µA VDD = 4.5V, Commercial
µA VDD = 4.5V, Industrial, Extended
Legend: Rows with standard voltage device data only are shaded for improved readability.
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
NR Not rated for operation.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD,
T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula IR = VDD/2REXT (mA) with REXT in kOhm.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD measurement.
DS35007B-page 52
2001 Microchip Technology Inc.
PIC16F84A
9.2
DC Characteristics:
PIC16F84A-04 (Commercial, Industrial)
PIC16F84A-20 (Commercial, Industrial)
PIC16LF84A-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C
≤ TA ≤ +70°C (commercial)
DC Characteristics
All Pins Except Power Supply Pins
-40°C ≤ TA ≤ +85°C (industrial)
Operating voltage VDD range as described in DC specifications
(Section 9.1)
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
D030
D030A
D031
D032
D033
D034
with TTL buffer
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.8
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V (Note 4)
Entire range (Note 4)
Entire range
0.16VDD
0.2VDD
0.2VDD
0.3VDD
0.1VDD
with Schmitt Trigger buffer
MCLR, RA4/T0CKI
OSC1 (XT, HS and LP modes)
OSC1 (RC mode)
(Note 1)
VIH
Input High Voltage
I/O ports:
—
D040
D040A
with TTL buffer
2.0
0.25VDD+0.8
—
—
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V (Note 4)
Entire range (Note 4)
D041
with Schmitt Trigger buffer
MCLR,
0.8 VDD
0.8 VDD
0.8 VDD
0.8 VDD
0.9 VDD
—
—
—
—
—
VDD
VDD
8.5
Entire range
D042
V
V
V
V
V
D042A
D043
RA4/T0CKI
OSC1 (XT, HS and LP modes)
OSC1 (RC mode)
VDD
VDD
—
(Note 1)
D043A
D050 VHYS
Hysteresis of Schmitt Trigger
Inputs
0.1
D070 IPURB
IIL
PORTB Weak Pull-up Current
50
—
250
400
µA VDD = 5.0V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060
I/O ports
—
±1
µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
—
—
—
—
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS
and LP osc configuration
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F84A with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.
2001 Microchip Technology Inc.
DS35007B-page 53
PIC16F84A
9.2
DC Characteristics:
PIC16F84A-04 (Commercial, Industrial)
PIC16F84A-20 (Commercial, Industrial)
PIC16LF84A-04 (Commercial, Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C
≤ TA ≤ +70°C (commercial)
DC Characteristics
All Pins Except Power Supply Pins
-40°C ≤ TA ≤ +85°C (industrial)
Operating voltage VDD range as described in DC specifications
(Section 9.1)
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
VOL
Output Low Voltage
I/O ports
D080
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V
D083
OSC2/CLKOUT
IOL = 1.6 mA, VDD = 4.5V,
(RC mode only)
VOH
VOD
Output High Voltage
I/O ports (Note 3)
D090
D092
VDD-0.7
VDD-0.7
—
—
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V
OSC2/CLKOUT (Note 3)
IOH = -1.3 mA, VDD = 4.5V
(RC mode only)
Open Drain High Voltage
D150
RA4 pin
—
—
8.5
V
Capacitive Loading Specs on
Output Pins
D100 COSC2 OSC2 pin
—
—
—
—
15
50
pF In XT, HS and LP modes
when external clock is used
to drive OSC1
D101 CIO
All I/O pins and OSC2
pF
(RC mode)
Data EEPROM Memory
Endurance
D120 ED
1M
10M
—
—
E/W 25°C at 5V
D121 VDRW
VDD for read/write
VMIN
5.5
V
VMIN = Minimum operating
voltage
D122 TDEW
Erase/Write cycle time
Program FLASH Memory
Endurance
—
4
8
ms
D130 EP
1000
10K
—
—
E/W
V
D131 VPR
VDD for read
VMIN
5.5
VMIN = Minimum operating
voltage
D132 VPEW
D133 TPEW
VDD for erase/write
4.5
—
—
4
5.5
8
V
Erase/Write cycle time
ms
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F84A with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.
DS35007B-page 54
2001 Microchip Technology Inc.
PIC16F84A
9.3
AC (Timing) Characteristics
9.3.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
2
to
os, osc
ost
OSC1
ck
cy
io
CLKOUT
cycle time
I/O port
INT pin
MCLR
oscillator start-up timer
power-up timer
RBx pins
pwrt
rbt
inp
mp
t0
T0CKI
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (high impedance)
Low
Valid
L
High Impedance
2001 Microchip Technology Inc.
DS35007B-page 55
PIC16F84A
9.3.2
TIMING CONDITIONS
The temperature and voltages specified in Table 9-1
apply to all timing specifications unless otherwise
noted. All timings are measured between high and low
measurement points as indicated in Figure 9-4.
Figure 9-5 specifies the load conditions for the timing
specifications.
TABLE 9-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
AC CHARACTERISTICS
Operating voltage VDD range as described in DC specifications (Section 9.1)
FIGURE 9-4:
PARAMETER MEASUREMENT INFORMATION
0.7 VDD XTAL
0.8 VDD RC
(High)
0.9 VDD (High)
0.1 VDD (Low)
0.3 VDD XTAL
0.15 VDD RC
(Low)
OSC1 Measurement Points
I/O Port Measurement Points
FIGURE 9-5:
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
VSS
RL =
CL =
464Ω
50 pF
15 pF
for all pins except OSC2
for OSC2 output
DS35007B-page 56
2001 Microchip Technology Inc.
PIC16F84A
9.3.3
TIMING DIAGRAMS AND SPECIFICATIONS
EXTERNAL CLOCK TIMING
FIGURE 9-6:
Q4
Q3
Q4
Q1
Q1
Q2
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 9-2:
EXTERNAL CLOCK TIMING REQUIREMENTS
Param No. Sym
Characteristic
Min
Typ†
Max
Units
Conditions
FOSC External CLKIN Frequency(1)
DC
DC
DC
DC
DC
DC
0.1
0.1
1.0
DC
500
250
50
—
—
2
4
MHz XT, RC osc
MHz XT, RC osc
MHz HS osc
kHz LP osc
MHz RC osc
MHz RC osc
MHz XT osc
MHz XT osc
MHz HS osc
kHz LP osc
ns XT, RC osc
ns XT, RC osc
ns HS osc
µs LP osc
ns RC osc
ns RC osc
ns XT osc
ns XT osc
ns HS osc
µs LP osc
µs
(-04, LF)
(-04)
—
20
200
2
(-20)
—
(-04, LF)
(-04, LF)
(-04)
Oscillator Frequency(1)
—
—
4
—
2
(-04, LF)
(-04)
—
4
—
20
200
—
(-20)
—
(-04, LF)
(-04, LF)
(-04)
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
—
—
—
—
—
(-20)
5.0
500
250
500
250
50
—
—
(-04, LF)
(-04, LF)
(-04)
—
—
—
—
—
10,000
10,000
1,000
—
(-04, LF)
(-04)
—
—
(-20)
5.0
0.2
60
—
(-04, LF)
2
3
TCY
Instruction Cycle Time(1)
4/FOSC
—
DC
—
TosL, Clock in (OSC1) High or Low
TosH Time
ns XT osc
ns XT osc
µs LP osc
ns HS osc
ns XT osc
ns LP osc
ns HS osc
(-04, LF)
(-04)
50
—
—
2.0
17.5
25
—
—
(-04, LF)
(-20)
—
—
4
TosR, Clock in (OSC1) Rise or Fall
—
—
(-04)
TosF
Time
50
—
—
(-04, LF)
(-20)
7.5
—
—
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator opera-
tion and/or higher than expected current consumption. All devices are tested to operate at "Min." values
with an external clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
2001 Microchip Technology Inc.
DS35007B-page 57
PIC16F84A
FIGURE 9-7:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
CLKOUT
13
12
19
18
14
16
I/O Pin
(Input)
15
17
I/O Pin
(Output)
new value
old value
20, 21
Note:
All tests must be done with specified capacitive loads (Figure 9-5) 50 pF on I/O pins and CLKOUT.
TABLE 9-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10
TosH2ckL OSC1↑ to CLKOUT↓
Standard
—
15
15
15
15
15
15
15
15
—
—
—
—
—
—
—
—
—
—
10
10
10
10
—
—
—
—
30
120
30
ns (Note 1)
10A
11
Extended (LF)
Standard
—
ns (Note 1)
TosH2ckH OSC1↑ to CLKOUT↑
—
ns (Note 1)
11A
12
Extended (LF)
Standard
—
120
30
ns (Note 1)
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
ns (Note 1)
12A
13
Extended (LF)
Standard
—
100
30
ns (Note 1)
—
ns (Note 1)
13A
14
Extended (LF)
—
100
0.5TCY +20
—
ns (Note 1)
TckL2ioV CLKOUT ↓ to Port out valid
—
ns (Note 1)
15
TioV2ckH Port in valid before
Standard
0.30TCY + 30
ns (Note 1)
CLKOUT ↑
Extended (LF)
0.30TCY + 80
—
ns (Note 1)
16
17
TckH2ioI Port in hold after CLKOUT ↑
0
—
—
ns (Note 1)
TosH2ioV OSC1↑ (Q1 cycle) to
Standard
125
250
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Port out valid
Extended (LF)
Standard
—
18
19
TosH2ioI OSC1↑ (Q2 cycle) to Port
10
input invalid (I/O in hold time)
Extended (LF)
Standard
10
—
TioV2osH Port input valid to OSC1↑
-75
-175
—
—
(I/O in setup time)
Extended (LF)
Standard
—
20
TioR
TioF
TINP
TRBP
Port output rise time
35
20A
21
Extended (LF)
Standard
—
70
Port output fall time
—
35
21A
22
Extended (LF)
Standard
—
70
INT pin high
or low time
20
—
22A
23
Extended (LF)
Standard
55
—
RB7:RB4 change INT
high or low time
TOSC§
TOSC§
—
23A
Extended (LF)
—
†
§
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
By design.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS35007B-page 58
2001 Microchip Technology Inc.
PIC16F84A
FIGURE 9-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
TABLE 9-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
µs VDD = 5.0V
ms VDD = 5.0V
30
TmcL
MCLR Pulse Width (low)
2
—
—
Watchdog Timer Time-out
Period (No Prescaler)
31
TWDT
7
18
33
Oscillation Start-up Timer
Period
32
33
TOST
1024TOSC
ms TOSC = OSC1 period
ms VDD = 5.0V
TPWRT Power-up Timer Period
28
—
72
132
100
I/O hi-impedance from MCLR
Low or RESET
34
TIOZ
—
ns
† Data in "Typ" column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
2001 Microchip Technology Inc.
DS35007B-page 59
PIC16F84A
FIGURE 9-9:
TIMER0 CLOCK TIMINGS
RA4/T0CKI
40
41
42
TABLE 9-5:
TIMER0 CLOCK REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
40
41
42
Tt0H T0CKI High Pulse
No Prescaler
0.5TCY + 20
—
—
ns
Width
With Prescaler
50
30
—
—
—
—
ns 2.0V ≤ VDD ≤ 3.0V
ns 3.0V ≤ VDD ≤ 6.0V
Tt0L T0CKI Low Pulse
Width
No Prescaler
0.5TCY + 20
—
—
ns
With Prescaler
50
20
—
—
—
—
ns 2.0V ≤ VDD ≤ 3.0V
ns 3.0V ≤ VDD ≤ 6.0V
Tt0P T0CKI Period
TCY + 40
—
—
ns N = prescale value
(2, 4, ..., 256)
N
† Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS35007B-page 60
2001 Microchip Technology Inc.
PIC16F84A
10.0 DC/AC CHARACTERISTIC GRAPHS
The graphs provided in this section are for design guidance and are not tested.
In some graphs, the data presented are outside specified operating range (i.e., outside specified VDD range). This is
for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. ‘Typical’ represents the mean of the distribution at 25°C. ‘Max’ or ‘Min’ represents
(mean + 3σ) or (mean - 3σ), respectively, where σ is a standard deviation over the whole temperature range.
2001 Microchip Technology Inc.
DS35007B-page 61
PIC16F84A
FIGURE 10-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE, 25°C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
0.0
4
6
8
10
12
14
16
18
20
FOSC (MHz)
FIGURE 10-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE, -40° TO +125°C)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
0.0
4
6
8
10
12
14
16
18
20
FOSC (MHz)
DS35007B-page 62
© 2001 Microchip Technology Inc.
PIC16F84A
FIGURE 10-3:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE, 25°C)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 10-4:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE, -40° TO +125°C)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
2001 Microchip Technology Inc.
DS35007B-page 63
PIC16F84A
FIGURE 10-5:
TYPICAL IDD vs. FOSC OVER VDD (LP MODE, 25°C)
80
70
60
50
40
30
20
10
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
0
25
50
75
100
125
150
175
200
FOSC (kHz)
FIGURE 10-6:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE, -40° TO +125°C)
250
5.5 V
200
150
100
50
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
0
25
50
75
100
125
150
175
200
FOSC (kHz)
DS35007B-page 64
© 2001 Microchip Technology Inc.
PIC16F84A
FIGURE 10-7:
AVERAGE FOSC vs. VDD FOR R (RC MODE, C = 22 pF, 25°C)
16.0
14.0
12.0
10.0
8.0
3.3 kΩ
5.1 kΩ
10 kΩ
6.0
4.0
2.0
100 kΩ
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 10-8:
AVERAGE FOSC vs. VDD FOR R (RC MODE, C = 100 pF, 25°C)
2000
1800
1600
1400
1200
1000
800
3.3 kΩ
5.1 kΩ
10 kΩ
600
400
200
100 kΩ
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2001 Microchip Technology Inc.
DS35007B-page 65
PIC16F84A
FIGURE 10-9:
AVERAGE FOSC vs. VDD FOR R (RC MODE, C = 300 pF, 25°C)
900
800
700
600
500
400
300
200
100
3.3 kΩ
5.1 kΩ
10 kΩ
100 kΩ
0
VDD (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FIGURE 10-10:
IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
10.0
Max
1.0
Typ
0.1
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS35007B-page 66
© 2001 Microchip Technology Inc.
PIC16F84A
FIGURE 10-11:
IPD vs. VDD (WDT MODE)
15
Typical:
statistical mean @ 25°C
14
13
12
11
10
9
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Max
8
7
6
5
Typ
4
3
2
1
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 10-12:
TYPICAL, MINIMUM, AND MAXIMUM WDT PERIOD vs. VDD OVER TEMP
60
50
40
30
20
Max
Typ
Min
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2001 Microchip Technology Inc.
DS35007B-page 67
PIC16F84A
FIGURE 10-13:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
Ma
Typ
Min
1.0
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.5
0.0
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
IOH (mA)
FIGURE 10-14:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C)
3.0
2.5
2.0
1.5
1.0
Max
Typ
Min
0.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
0
5
10
15
20
25
IOH (mA)
DS35007B-page 68
© 2001 Microchip Technology Inc.
PIC16F84A
FIGURE 10-15:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C)
1.0
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Max
Typ
Min
0
5
10
15
20
25
IOL (mA)
FIGURE 10-16:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C)
1.8
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Max
Typ
Min
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
IOL (mA)
2001 Microchip Technology Inc.
DS35007B-page 69
PIC16F84A
FIGURE 10-17:
MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO +125°C)
2.00
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
VTH
VTH
VTH
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 10-18:
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C)
3.50
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
VIH Typ
VIH Max
VIH Min
VIL Typ
VIL Max
VIL Min
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS35007B-page 70
© 2001 Microchip Technology Inc.
PIC16F84A
11.0 PACKAGING INFORMATION
11.1 Package Marking Information
18-Lead PDIP
Example
PIC16F84A-04I/P
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
0110017
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F84A-04
/SO
YYWWNNN
0110017
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC16F84A-
20/SS
0110017
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip sales office. For QTP devices, any special marking adders are included in QTP
price.
2001 Microchip Technology Inc.
DS35007B-page 71
PIC16F84A
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
L
A
c
A1
B1
β
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
DS35007B-page 72
2001 Microchip Technology Inc.
PIC16F84A
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
18
18
1.27
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
2.24
0.10
10.01
7.39
11.33
0.25
0.41
0
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
2001 Microchip Technology Inc.
DS35007B-page 73
PIC16F84A
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
§
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
DS35007B-page 74
2001 Microchip Technology Inc.
PIC16F84A
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
9/98
This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16F8X Data Sheet, DS30430.
B
8/01
Added DC and AC Characteristics Graphs and Tables to Section 10.
2001 Microchip Technology Inc.
DS35007B-page 75
PIC16F84A
APPENDIX B: CONVERSION CONSIDERATIONS
Considerations for converting from one PIC16X8X
device to another are listed in Table 1.
TABLE 1:
CONVERSION CONSIDERATIONS - PIC16C84, PIC16F83/F84, PIC16CR83/CR84,
PIC16F84A
PIC16CR83/
CR84
Difference
PIC16C84
PIC16F83/F84
PIC16F84A
Program Memory Size
Data Memory Size
Voltage Range
1K x 14
36 x 8
512 x 14 / 1K x 14
36 x 8 / 68 x 8
512 x 14 / 1K x 14
36 x 8 / 68 x 8
1K x 14
68 x 8
2.0V - 6.0V
2.0V - 6.0V
2.0V - 6.0V
2.0V - 5.5V
(-40°C to +85°C)
(-40°C to +85°C)
(-40°C to +85°C)
(-40°C to +125°C)
Maximum Operating Fre- 10 MHz
quency
10 MHz
10 MHz
20 MHz
Supply Current (IDD).
See parameter # D014 in IDD (max) = 400 µA
IDD (typ) = 60 µA
IDD (typ) = 15 µA
IDD (max) = 45 µA
IDD (typ) = 15 µA
IDD (max) = 45 µA
IDD (typ) = 15 µA
IDD (max) = 45 µA
the electrical specs for
more detail.
(LP osc, FOSC = 32 kHz, (LP osc, FOSC = 32 kHz, (LP osc, FOSC = 32 kHz, (LP osc, FOSC = 32 kHz,
VDD = 2.0V,
VDD = 2.0V,
VDD = 2.0V,
VDD = 2.0V,
WDT disabled)
WDT disabled)
WDT disabled)
WDT disabled)
Power-down Current
(IPD). See parameters # IPD (max) = 100 µA
D020, D021, and D021A (VDD = 2.0V,
IPD (typ) = 26 µA
IPD (typ) = 0.4 µA
IPD (max) = 9 µA
(VDD = 2.0V,
IPD (typ) = 0.4 µA
IPD (max) = 6 µA
(VDD = 2.0V,
IPD (typ) = 0.4 µA
IPD (max) = 1 µA
(VDD = 2.0V,
in the electrical specs for WDT disabled, industrial) WDT disabled, industrial) WDT disabled, industrial) WDT disabled, industrial)
more detail.
Input Low Voltage (VIL). VIL (max) = 0.2VDD
See parameters # D032 (OSC1, RC mode)
and D034 in the electrical
VIL (max) = 0.1VDD
(OSC1, RC mode)
VIL (max) = 0.1VDD
(OSC1, RC mode)
VIL (max) = 0.1VDD
(OSC1, RC mode)
specs for more detail.
Input High Voltage (VIH). VIH (min) = 0.36VDD
See parameter # D040 in (I/O Ports with TTL,
VIH (min) = 2.4V
(I/O Ports with TTL,
4.5V ≤ VDD ≤ 5.5V)
VIH (min) = 2.4V
(I/O Ports with TTL,
4.5V ≤ VDD ≤ 5.5V)
VIH (min) = 2.4V
(I/O Ports with TTL,
4.5V ≤ VDD ≤ 5.5V)
the electrical specs for
more detail.
4.5V ≤ VDD ≤ 5.5V)
Data EEPROM Memory TDEW (typ) = 10 ms
TDEW (typ) = 10 ms
TDEW (max) = 20 ms
TDEW (typ) = 10 ms
TDEW (max) = 20 ms
TDEW (typ) = 4 ms
TDEW (max) = 8 ms
Erase/Write cycle time
(TDEW). See parameter #
D122 in the electrical
specs for more detail.
TDEW (max) = 20 ms
Port Output Rise/Fall
time (TioR, TioF). See
parameters #20, 20A,
TioR, TioF (max) = 25 ns TioR, TioF (max) = 35 ns TioR, TioF (max) = 35 ns TioR, TioF (max) = 35 ns
(C84) (C84) (C84) (C84)
TioR, TioF (max) = 60 ns TioR, TioF (max) = 70 ns TioR, TioF (max) = 70 ns TioR, TioF (max) = 70 ns
21, and 21A in the elec- (LC84)
trical specs for more
detail.
(LC84)
(LC84)
(LC84)
MCLR on-chip filter. See No
parameter #30 in the
electrical specs for more
detail.
Yes
Yes
Yes
PORTA and crystal oscil- For crystal oscillator con- N/A
N/A
N/A
lator values less than
500 kHz
figurations operating
below 500 kHz, the device
may generate a spurious
internal Q-clock when
PORTA<0> switches
state.
RB0/INT pin
TTL
TTL/ST*
TTL/ST*
TTL/ST*
(*Schmitt Trigger)
(*Schmitt Trigger)
(*Schmitt Trigger)
DS35007B-page 76
2001 Microchip Technology Inc.
PIC16F84A
TABLE 1:
CONVERSION CONSIDERATIONS - PIC16C84, PIC16F83/F84, PIC16CR83/CR84,
PIC16F84A (CONTINUED)
PIC16CR83/
Difference
PIC16C84
PIC16F83/F84
PIC16F84A
CR84
EEADR<7:6> and IDD
It is recommended that
the EEADR<7:6> bits be
cleared. When either of
these bits is set, the maxi-
mum IDD for the device is
higher than when both are
cleared.
N/A
N/A
N/A
The polarity of the
PWRTE bit
PWRTE
PWRTE
PWRTE
PWRTE
Recommended value of REXT = 3kΩ - 100kΩ
REXT = 5kΩ - 100kΩ
REXT = 5kΩ - 100kΩ
REXT = 3kΩ - 100kΩ
REXT for RC oscillator
circuits
GIE bit unintentional
enable
If an interrupt occurs while N/A
the Global Interrupt
N/A
N/A
Enable (GIE) bit is being
cleared, the GIE bit may
unintentionally be re-
enabled by the user’s
Interrupt Service Routine
(the RETFIEinstruction).
Packages
PDIP, SOIC
14V
PDIP, SOIC
12V
PDIP, SOIC
12V
PDIP, SOIC, SSOP
8.5V
Open Drain High
Voltage (VOD)
2001 Microchip Technology Inc.
DS35007B-page 77
PIC16F84A
To convert code written for PIC16C5X to PIC16F84A,
the user should take the following steps:
APPENDIX C: MIGRATION FROM
BASELINE TO
1. Remove any program memory page select
MID-RANGE DEVICES
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a mid-range device (i.e.,
PIC16CXXX).
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
The following is the list of feature improvements over
the PIC16C5X microcontroller family:
3. Eliminate any data memory page switching.
Redefine data variables for reallocation.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
1. Instruction word length is increased to 14-bits.
This allows larger page sizes, both in program
memory (2K now as opposed to 512K before)
and the register file (128 bytes now versus
32 bytes before).
5. Change RESET vector to 0000h.
2. A PC latch register (PCLATH) is added to han-
dle program memory paging. PA2, PA1 and PA0
bits are removed from the STATUS register and
placed in the OPTION register.
3. Data memory paging is redefined slightly. The
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW. Two
instructions, TRIS and OPTION, are being
phased out, although they are kept for
compatibility with PIC16C5X.
5. OPTION and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to eight-deep.
8. RESET vector is changed to 0000h.
9. RESET of all registers is revisited. Five different
RESET (and wake-up) types are recognized.
Registers are reset differently.
10. Wake-up from SLEEP through interrupt is
added.
11. Two separate timers, the Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT), are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt-on-
change features.
13. T0CKI pin is also a port pin (RA4/T0CKI).
14. FSR is a full 8-bit register.
15. "In system programming" is made possible. The
user can program PIC16CXX devices using only
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).
DS35007B-page 78
2001 Microchip Technology Inc.
PIC16F84A
INDEX
A
E
Absolute Maximum Ratings ................................................ 49
AC (Timing) Characteristics ................................................ 55
Architecture, Block Diagram ................................................. 3
Assembler
EECON1 Register
EEIF Bit ...................................................................... 29
Electrical Characteristics .................................................... 49
Load Conditions.......................................................... 56
Parameter Measurement Information......................... 56
PIC16F84A-04 Voltage-Frequency Graph ................. 50
PIC16F84A-20 Voltage-Frequency Graph ................. 50
PIC16LF84A-04 Voltage-Frequency Graph ............... 50
Temperature and Voltage Specifications - AC ........... 56
Endurance ............................................................................ 1
Errata.................................................................................... 2
External Clock Input (RA4/T0CKI). See Timer0
MPASM Assembler..................................................... 43
B
Banking, Data Memory ......................................................... 6
Block Diagrams
Crystal/Ceramic Resonator Operation........................ 22
External Clock Input Operation................................... 22
External Power-on Reset Circuit................................. 26
Interrupt Logic............................................................. 29
On-Chip Reset ............................................................ 24
PIC16F84A ................................................................... 3
PORTA
External Interrupt Input (RB0/INT). See Interrupt Sources
External Power-on Reset Circuit......................................... 26
F
RA3:RA0 Pins..................................................... 15
RA4 Pins............................................................. 15
PORTB
Firmware Instructions ......................................................... 35
I
I/O Ports ............................................................................. 15
ICEPIC In-Circuit Emulator................................................. 44
ID Locations..................................................................21, 33
In-Circuit Serial Programming (ICSP)...........................21, 33
INDF Register....................................................................... 7
Indirect Addressing............................................................. 11
FSR Register.............................................. 6, 7, 11, 25
INDF Register.................................................. 7, 11, 25
Instruction Format............................................................... 35
Instruction Set..................................................................... 35
ADDLW....................................................................... 37
ADDWF ...................................................................... 37
ANDLW....................................................................... 37
ANDWF ...................................................................... 37
BCF ............................................................................ 37
BSF............................................................................. 37
BTFSC........................................................................ 38
BTFSS........................................................................ 37
CALL........................................................................... 38
CLRF .......................................................................... 38
CLRW......................................................................... 38
CLRWDT .................................................................... 38
COMF......................................................................... 38
DECF.......................................................................... 38
DECFSZ ..................................................................... 39
GOTO......................................................................... 39
INCF ........................................................................... 39
INCFSZ....................................................................... 39
IORLW........................................................................ 39
IORWF........................................................................ 39
MOVF ......................................................................... 40
MOVLW...................................................................... 40
MOVWF...................................................................... 40
NOP............................................................................ 40
RETFIE....................................................................... 40
RETLW....................................................................... 40
RETURN..................................................................... 40
RLF............................................................................. 41
RRF ............................................................................ 41
SLEEP........................................................................ 41
SUBLW....................................................................... 41
SUBWF....................................................................... 41
SWAPF....................................................................... 41
XORLW ...................................................................... 42
RB3:RB0 Pins..................................................... 17
RB7:RB4 Pins..................................................... 17
RC Oscillator Mode..................................................... 23
Timer0......................................................................... 19
Timer0/WDT Prescaler ............................................... 20
Watchdog Timer (WDT).............................................. 31
C
C (Carry) bit .......................................................................... 8
CLKIN Pin ............................................................................. 4
CLKOUT Pin ......................................................................... 4
Code Examples
Clearing RAM Using Indirect Addressing.................... 11
Data EEPOM Write Verify........................................... 14
Indirect Addressing ..................................................... 11
Initializing PORTA....................................................... 15
Initializing PORTB....................................................... 17
Reading Data EEPROM ............................................. 14
Saving STATUS and W Registers in RAM ................. 30
Writing to Data EEPROM............................................ 14
Code Protection ........................................................... 21, 33
Configuration Bits................................................................ 21
Configuration Word ............................................................. 21
Conversion Considerations................................................. 76
D
Data EEPROM Memory...................................................... 13
Associated Registers .................................................. 14
EEADR Register ..............................................7, 13, 25
EECON1 Register............................................7, 13, 25
EECON2 Register............................................7, 13, 25
EEDATA Register ............................................7, 13, 25
Write Complete Enable (EEIE Bit) .............................. 29
Write Complete Flag (EEIF Bit)................................... 29
Data EEPROM Write Complete .......................................... 29
Data Memory ........................................................................ 6
Bank Select (RP0 Bit) ................................................... 6
Banking......................................................................... 6
DC Bit.................................................................................... 8
DC Characteristics ....................................................... 51, 53
Development Support ......................................................... 43
Device Overview ................................................................... 3
2001 Microchip Technology Inc.
DS35007B-page 79
PIC16F84A
XORWF.......................................................................42
Summary Table...........................................................36
INT Interrupt (RB0/INT).......................................................29
INTCON Register....................................... 7, 10, 20, 25, 29
EEIE Bit.......................................................................29
GIE Bit.................................................................. 10, 29
INTE Bit................................................................ 10, 29
INTF Bit................................................................ 10, 29
PEIE Bit.......................................................................10
RBIE Bit ............................................................... 10, 29
RBIF Bit..........................................................10, 17, 29
T0IE Bit ................................................................ 10, 29
T0IF Bit ..........................................................10, 20, 29
Interrupt Sources.......................................................... 21, 29
Block Diagram.............................................................29
Data EEPROM Write Complete ........................... 29, 32
Interrupt-on-Change (RB7:RB4) ...............4, 17, 29, 32
RB0/INT Pin, External...............................4, 18, 29, 32
TMR0 Overflow .................................................... 20, 29
Interrupts, Context Saving During.......................................30
Interrupts, Enable Bits
T0CS Bit ....................................................................... 9
T0SE Bit ....................................................................... 9
OPTION_REG Register.................................... 7, 18, 20, 25
INTEDG Bit................................................................. 29
PS2:PS0 Bits .............................................................. 19
PSA Bit ....................................................................... 19
OSC1 Pin.............................................................................. 4
OSC2 Pin.............................................................................. 4
Oscillator Configuration ................................................21, 22
Block Diagram ......................................................22, 23
Capacitor Selection for Ceramic Resonators.............. 22
Capacitor Selection for Crystal Oscillator ................... 23
Crystal Oscillator/Ceramic Resonators....................... 22
HS.........................................................................22, 28
LP .........................................................................22, 28
Oscillator Types.......................................................... 22
RC .................................................................22, 23, 28
XT .........................................................................22, 28
P
Packaging Information........................................................ 71
Marking....................................................................... 71
PD Bit.................................................................................... 8
PICDEM 1 Low Cost PICmicro
Demonstration Board.................................................. 45
PICDEM 17 Demonstration Board...................................... 46
PICDEM 2 Low Cost PIC16CXX
Demonstration Board.................................................. 45
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board.................................................. 46
PICSTART Plus Entry Level Development
Data EEPROM Write Complete Enable
(EEIE Bit) ............................................................29
Global Interrupt Enable (GIE Bit) ................................10
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit)............................................................10
Peripheral Interrupt Enable (PEIE Bit) ........................10
RB0/INT Enable (INTE Bit) .........................................10
TMR0 Overflow Enable (T0IE Bit)...............................10
Interrupts, Flag Bits.............................................................29
Data EEPROM Write Complete Flag
Programmer................................................................ 45
Pinout Descriptions............................................................... 4
Pointer, FSR ....................................................................... 11
POR. See Power-on Reset
(EEIF Bit) ............................................................29
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ............................................................10
RB0/INT Flag (INTF Bit)..............................................10
TMR0 Overflow Flag (T0IF Bit) ...................................10
IRP bit ...................................................................................8
PORTA ...........................................................................4, 15
Associated Registers.................................................. 16
Functions .................................................................... 16
Initializing.................................................................... 15
PORTA Register....................................... 7, 15, 16, 25
RA3:RA0 Block Diagram ............................................ 15
RA4 Block Diagram .................................................... 15
RA4/T0CKI Pin ................................................4, 15, 19
TRISA Register...................................7, 15, 16, 20, 25
PORTB ...........................................................................4, 17
Associated Registers.................................................. 18
Functions .................................................................... 18
Initializing.................................................................... 17
PORTB Register....................................... 7, 17, 18, 25
Pull-up Enable Bit (RBPU Bit)....................................... 9
RB0/INT Edge Select (INTEDG Bit) ............................. 9
RB0/INT Pin, External......................................4, 18, 29
RB3:RB0 Block Diagram ............................................ 17
RB7:RB4 Block Diagram ............................................ 17
RB7:RB4 Interrupt-on-Change ........................4, 17, 29
RB7:RB4 Interrupt-on-Change
K
KEELOQ Evaluation and Programming Tools ......................46
M
Master Clear (MCLR)
MCLR Pin......................................................................4
MCLR Reset, Normal Operation .................................24
MCLR Reset, SLEEP........................................... 24, 32
Memory Organization............................................................5
Data EEPROM Memory..............................................13
Data Memory ................................................................6
Program Memory ..........................................................5
Migration from Baseline to Mid-Range Devices..................78
MPLAB C17 and MPLAB C18 C Compilers........................43
MPLAB ICD In-Circuit Debugger.........................................45
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPLAB IDE..........................................44
MPLAB Integrated Development Environment
Software......................................................................43
MPLINK Object Linker/MPLIB Object Librarian ..................44
Enable (RBIE Bit) ............................................... 10
RB7:RB4 Interrupt-on-Change
Flag (RBIF Bit)..............................................10, 17
TRISB Register......................................... 7, 17, 18, 25
Postscaler, WDT
Assignment (PSA Bit) ................................................... 9
Rate Select (PS2:PS0 Bits) .......................................... 9
Postscaler. See Prescaler
O
OPCODE Field Descriptions...............................................35
OPTION Register..................................................................9
INTEDG Bit ...................................................................9
PS2:PS0 Bits ................................................................9
PSA Bit..........................................................................9
RBPU Bit.......................................................................9
Power-down (PD) Bit. See Power-on Reset (POR)
Power-down Mode. See SLEEP
DS35007B-page 80
2001 Microchip Technology Inc.
PIC16F84A
Power-on Reset (POR) ..........................................21, 24, 26
Oscillator Start-up Timer (OST) ........................... 21, 26
PD Bit................................................. 8, 24, 28, 32, 33
Power-up Timer (PWRT) ..................................... 21, 26
Time-out Sequence..................................................... 28
Time-out Sequence on Power-up ........................ 27, 28
TO Bit...........................................8, 24, 28, 30, 32, 33
Prescaler............................................................................. 19
Assignment (PSA Bit) ................................................. 19
Block Diagram............................................................. 20
Rate Select (PS2:PS0 Bits) ........................................ 19
Switching Prescaler Assignment................................. 20
Prescaler, Timer0
Assignment (PSA Bit) ................................................... 9
Rate Select (PS2:PS0 Bits) .......................................... 9
PRO MATE II Universal Device Programmer ..................... 45
Program Counter ................................................................ 11
PCL Register....................................................7, 11, 25
PCLATH Register ............................................7, 11, 25
Reset Conditions......................................................... 24
Program Memory .................................................................. 5
General Purpose Registers........................................... 6
Interrupt Vector ...................................................... 5, 29
RESET Vector............................................................... 5
Special Function Registers ...................................... 6, 7
Programming, Device Instructions ...................................... 35
T
Time-out (TO) Bit. See Power-on Reset (POR)
Timer0 ................................................................................ 19
Associated Registers.................................................. 20
Block Diagram ............................................................ 19
Clock Source Edge Select (T0SE Bit) .......................... 9
Clock Source Select (T0CS Bit) ................................... 9
Overflow Enable (T0IE Bit)...................................10, 29
Overflow Flag (T0IF Bit) ................................ 10, 20, 29
Overflow Interrupt.................................................20, 29
Prescaler. See Prescaler
RA4/T0CKI Pin, External Clock.................................. 19
TMR0 Register ................................................ 7, 20, 25
Timing Conditions............................................................... 56
Timing Diagrams
CLKOUT and I/O ........................................................ 58
Diagrams and Specifications...................................... 57
CLKOUT and I/O Requirements......................... 58
External Clock Requirements............................. 57
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up
Timer Requirements................................... 59
Timer0 Clock Requirements............................... 60
External Clock ............................................................ 57
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer................................. 59
Time-out Sequence on Power-up.........................27, 28
Timer0 Clock .............................................................. 60
Wake-up From SLEEP Through Interrupt .................. 32
Timing Parameter Symbology ............................................ 55
TO bit.................................................................................... 8
R
RAM. See Data Memory
Register File.......................................................................... 6
Register File Map.................................................................. 6
Registers
Configuration Word..................................................... 21
EECON1 (EEPROM Control)...................................... 13
INTCON ...................................................................... 10
OPTION ........................................................................ 9
STATUS........................................................................ 8
Reset............................................................................ 21, 24
Block Diagram...................................................... 24, 26
MCLR Reset. See MCLR
W
W Register....................................................................25, 30
Wake-up from SLEEP...............................21, 26, 28, 29, 32
Interrupts ..............................................................32, 33
MCLR Reset............................................................... 32
WDT Reset................................................................. 32
Watchdog Timer (WDT)................................................21, 30
Block Diagram ............................................................ 31
Postscaler. See Prescaler
Programming Considerations..................................... 31
RC Oscillator .............................................................. 30
Time-out Period.......................................................... 30
WDT Reset, Normal Operation................................... 24
WDT Reset, SLEEP .............................................24, 32
WWW, On-Line Support ....................................................... 2
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for All Registers .............................. 25
Reset Conditions for Program Counter....................... 24
Reset Conditions for STATUS Register...................... 24
WDT Reset. See Watchdog Timer (WDT)
Revision History .................................................................. 75
RP1:RP0 (Bank Select) bits.................................................. 8
S
Z
Saving W Register and STATUS in RAM ........................... 30
SLEEP ............................................................21, 24, 29, 32
Software Simulator (MPLAB SIM)....................................... 44
Special Features of the CPU .............................................. 21
Special Function Registers .............................................. 6, 7
Speed, Operating.............................................. 1, 22, 23, 57
Stack ................................................................................... 11
STATUS Register ............................................... 7, 8, 25, 30
C Bit .............................................................................. 8
DC Bit............................................................................ 8
PD Bit................................................. 8, 24, 28, 32, 33
RESET Conditions...................................................... 24
RP0 Bit.......................................................................... 6
TO Bit...........................................8, 24, 28, 30, 32, 33
Z Bit............................................................................... 8
Z (Zero) bit............................................................................ 8
2001 Microchip Technology Inc.
DS35007B-page 81
PIC16F84A
NOTES:
DS35007B-page 82
2001 Microchip Technology Inc.
PIC16F84A
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ConnectingtotheMicrochipInternetWebSite
013001
The Microchip web site is available by using your
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2001 Microchip Technology Inc.
DS35007B-page 83
PIC16F84A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
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Literature Number:
DS35007B
Device:
PIC16F84A
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
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DS35007B-page 84
2001 Microchip Technology Inc.
PIC16F84A
PIC16F84A PRODUCT IDENTIFICATION SYSTEM
To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
-XX
Examples:
a) PIC16F84A -04/P 301 = Commercial
temp., PDIP package, 4 MHz, normal VDD
limits, QTP pattern #301.
Frequency Temperature Package
Pattern
Range
Range
b) PIC16LF84A - 04I/SO = Industrial temp.,
SOIC package, 200 kHz, Extended VDD
limits.
(1)
(2)
Device
PIC16F84A , PIC16F84AT
(1)
(2)
PIC16LF84A , PIC16LF84AT
c) PIC16F84A - 20I/P = Industrial temp.,
Frequency Range 04
20
=
=
4 MHz
20 MHz
PDIP package, 20 MHz, normal VDD limits.
Temperature
Range
-
I
=
=
0°C to +70°C
-40°C to +85°C
Note 1:
2:
F
= Standard VDD range
Package
P
=
PDIP
LF = Extended VDD range
T
SO =
SS
SOIC (Gull Wing, 300 mil body)
SSOP
= in tape and reel - SOIC and
SSOP packages only.
=
Pattern
QTP, SQTP, ROM Code (factory specified) or
Special Requirements . Blank for OTP and
Windowed devices.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
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2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
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Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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2001 Microchip Technology Inc.
DS35007B-page85
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DS35007B-page 86
2001 Microchip Technology Inc.
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