PIC17C43-16/PT [MICROCHIP]
High-Performance 8-Bit CMOS EPROM/ROM Microcontroller; 高性能8位CMOS EPROM / ROM微控制器
| 型号： | PIC17C43-16/PT |
| 厂家： | 
MICROCHIP |
| 描述： | High-Performance 8-Bit CMOS EPROM/ROM Microcontroller |
| 文件： | 总240页 (文件大小：1141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC17C4X
High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
Devices included in this data sheet:
Pin Diagram
• PIC17CR42
• PIC17C42A
• PIC17C43
• PIC17CR43
• PIC17C44
• PIC17C42†
PDIP, CERDIP, Windowed CERDIP
VDD
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
VSS
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
MCLR/VPP
VSS
RE0/ALE
RE1/OE
RE2/WR
TEST
RA0/INT
RA1/T0CKI
RA2
9
10
11
12
13
14
15
16
17
18
19
20
Microcontroller Core Features:
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6
• Only 58 single word instructions to learn
• All single cycle instructions (121 ns) except for
program branches and table reads/writes which
are two-cycle
RB7
RA3
RA4/RX/DT
RA5/TX/CK
OSC1/CLKIN
OSC2/CLKOUT
• Operating speed:
- DC - 33 MHz clock input
- DC - 121 ns instruction cycle
✯
✯
• TMR2: 8-bit timer/counter
• TMR3: 16-bit timer/counter
Program Memory
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
Device
Data Memory
EPROM
ROM
PIC17CR42
PIC17C42A
PIC17C43
PIC17CR43
PIC17C44
PIC17C42†
-
2K
232
232
454
454
454
232
Special Microcontroller Features:
2K
4K
-
-
-
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
4K
-
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
8K
2K
-
• Code-protection
• Hardware Multiplier
(Not available on the PIC17C42)
• Power saving SLEEP mode
• Selectable oscillator options
• Interrupt capability
CMOS Technology:
• 16 levels deep hardware stack
• Low-power, high-speed CMOS EPROM/ROM
technology
• Direct, indirect and relative addressing modes
• Internal/External program memory execution
• 64K x 16 addressable program memory space
• Fully static design
• Wide operating voltage range (2.5V to 6.0V)
• Commercial and Industrial Temperature Range
• Low-power consumption
Peripheral Features:
• 33 I/O pins with individual direction control
• High current sink/source for direct LED drive
- < 5 mA @ 5V, 4 MHz
- RA2 and RA3 are open drain, high voltage
(12V), high current (60 mA), I/O
- 100 µA typical @ 4.5V, 32 kHz
- < 1 µA typical standby current @ 5V
• Two capture inputs and two PWM outputs
- Captures are 16-bit, max resolution 160 ns
- PWM resolution is 1- to 10-bit
• TMR0: 16-bit timer/counter with 8-bit programma-
ble prescaler
• TMR1: 8-bit timer/counter
†NOT recommended for new designs, use 17C42A.
1996 Microchip Technology Inc.
DS30412C-page 1
PIC17C4X
Pin Diagrams Cont.’d
PLCC
MQFP
TQFP
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
VSS
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
MCLR/VPP
VSS
7
8
9
39
38
37
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
TEST
RB4/TCLK12
RB3/PWM2
RB2/PWM1
RB1/CAP2
RB0/CAP1
VSS
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
RE2/WR
RE1/OE
RE0/ALE
VSS
VSS
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
VSS
RE0/ALE
RE1/OE
RE2/WR
TEST
VSS
MCLR/VPP
RD7/AD15
RD6/AD14
RD5/AD13
RD4/AD12
VSS
RC7/AD7
RC6/AD6
RC5/AD5
RC4/AD4
9
10
11
All devices are available in all package types, listed in Section 21.0, with the following exceptions:
• ROM devices are not available in Windowed CERDIP Packages
• TQFP is not available for the PIC17C42.
DS30412C-page 2
1996 Microchip Technology Inc.
PIC17C4X
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
Overview ..............................................................................................................................................................5
PIC17C4X Device Varieties .................................................................................................................................7
Architectural Overview .........................................................................................................................................9
Reset..................................................................................................................................................................15
Interrupts ............................................................................................................................................................21
Memory Organization.........................................................................................................................................29
Table Reads and Table Writes...........................................................................................................................43
Hardware Multiplier ............................................................................................................................................49
I/O Ports .............................................................................................................................................................53
10.0 Overview of Timer Resources............................................................................................................................65
11.0 Timer0 ................................................................................................................................................................67
12.0 Timer1, Timer2, Timer3, PWMs and Captures...................................................................................................71
13.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module................................................83
14.0 Special Features of the CPU..............................................................................................................................99
15.0 Instruction Set Summary..................................................................................................................................107
16.0 Development Support.......................................................................................................................................143
17.0 PIC17C42 Electrical Characteristics ................................................................................................................147
18.0 PIC17C42 DC and AC Characteristics.............................................................................................................163
19.0 PIC17CR42/42A/43/R43/44 Electrical Characteristics.....................................................................................175
20.0 PIC17CR42/42A/43/R43/44 DC and AC Characteristics .................................................................................193
21.0 Packaging Information......................................................................................................................................205
Appendix A: Modifications ..........................................................................................................................................211
Appendix B: Compatibility...........................................................................................................................................211
Appendix C: What’s New ............................................................................................................................................212
Appendix D: What’s Changed.....................................................................................................................................212
Appendix E: PIC16/17 Microcontrollers......................................................................................................................213
Appendix F: Errata for PIC17C42 Silicon ...................................................................................................................223
Index ............................................................................................................................................................................226
PIC17C4X Product Identification System ....................................................................................................................237
For register and module descriptions in this data sheet, device legends show which devices apply to those sections.
For example, the legend below shows that some features of only the PIC17C43, PIC17CR43, PIC17C44 are described
in this section.
Applicable Devices
42 R42 42A 43 R43 44
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an excep-
tional amount of time to ensure that these documents are correct. However, we realize that we may have
missed a few things. If you find any information that is missing or appears in error from the previous version of
the PIC17C4X Data Sheet (Literature Number DS30412B), please use the reader response form in the back
of this data sheet to inform us. We appreciate your assistance in making this a better document.
To assist you in the use of this document, Appendix C contains a list of new information in this data sheet,
while Appendix D contains information that has changed
1996 Microchip Technology Inc.
DS30412C-page 3
PIC17C4X
NOTES:
DS30412C-page 4
1996 Microchip Technology Inc.
PIC17C4X
power saving. The user can wake-up the chip from
SLEEP through several external and internal interrupts
and device resets.
1.0
OVERVIEW
This data sheet covers the PIC17C4X group of the
PIC17CXX family of microcontrollers. The following
devices are discussed in this data sheet:
There are four configuration options for the device oper-
ational modes:
• PIC17C42
• PIC17CR42
• PIC17C42A
• PIC17C43
• PIC17CR43
• PIC17C44
• Microprocessor
• Microcontroller
• Extended microcontroller
• Protected microcontroller
The microprocessor and extended microcontroller
modes allow up to 64K-words of external program
memory.
The
PIC17CR42,
PIC17C42A,
PIC17C43,
PIC17CR43, and PIC17C44 devices include architec-
tural enhancements over the PIC17C42. These
enhancements will be discussed throughout this data
sheet.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software mal-
function.
Table 1-1 lists the features of the PIC17C4X devices.
The
PIC17C4X
devices
are
40/44-Pin,
EPROM/ROM-based members of the versatile
PIC17CXX family of low-cost, high-performance,
CMOS, fully-static, 8-bit microcontrollers.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC17CXX has enhanced core
features, 16-level deep stack, and multiple internal and
external interrupt sources.The separate instruction and
data buses of the Harvard architecture allow a 16-bit
wide instruction word with a separate 8-bit wide data.
The two stage instruction pipeline allows all instructions
to execute in a single cycle, except for program
branches (which require two cycles). A total of 55
instructions (reduced instruction set) are available in
the PIC17C42 and 58 instructions in all the other
devices. Additionally, a large register set gives some of
the architectural innovations used to achieve a very
high performance. For mathematical intensive applica-
tions all devices, except the PIC17C42, have a single
cycle 8 x 8 Hardware Multiplier.
The PIC17C4X fits perfectly in applications ranging
from precise motor control and industrial process con-
trol to automotive, instrumentation, and telecom appli-
cations. Other applications that require extremely fast
execution of complex software programs or the flexibil-
ity of programming the software code as one of the last
steps of the manufacturing process would also be well
suited. The EPROM technology makes customization
of application programs (with unique security codes,
combinations, model numbers, parameter storage,
etc.) fast and convenient. Small footprint package
options make the PIC17C4X ideal for applications with
space limitations that require high performance. High
speed execution, powerful peripheral features, flexible
I/O, and low power consumption all at low cost make
the PIC17C4X ideal for a wide range of embedded con-
trol applications.
PIC17CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
1.1
Family and Upward Compatibility
PIC17C4X devices have up to 454 bytes of RAM and
33 I/O pins. In addition, the PIC17C4X adds several
peripheral features useful in many high performance
applications including:
Those users familiar with the PIC16C5X and
PIC16CXX families of microcontrollers will see the
architectural enhancements that have been imple-
mented. These enhancements allow the device to be
more efficient in software and hardware requirements.
Please refer to Appendix A for a detailed list of
enhancements and modifications. Code written for
PIC16C5X or PIC16CXX can be easily ported to
PIC17CXX family of devices (Appendix B).
• Four timer/counters
• Two capture inputs
• Two PWM outputs
• A Universal Synchronous Asynchronous Receiver
Transmitter (USART)
These special features reduce external components,
thus reducing cost, enhancing system reliability and
reducing power consumption. There are four oscillator
options, of which the single pin RC oscillator provides a
low-cost solution, the LF oscillator is for low frequency
crystals and minimizes power consumption, XT is a
standard crystal, and the EC is for external clock input.
The SLEEP (power-down) mode offers additional
1.2
Development Support
The PIC17CXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a universal programmer, a “C” compiler, and
fuzzy logic support tools.
1996 Microchip Technology Inc.
DS30412C-page 5
PIC17C4X
TABLE 1-1:
PIC17CXX FAMILY OF DEVICES
Features
PIC17C42
PIC17CR42
PIC17C42A
PIC17C43
PIC17CR43
PIC17C44
Maximum Frequency of Operation
Operating Voltage Range
25 MHz
4.5 - 5.5V
2K
33 MHz
2.5 - 6.0V
-
33 MHz
2.5 - 6.0V
2K
33 MHz
2.5 - 6.0V
4K
33 MHz
2.5 - 6.0V
-
33 MHz
2.5 - 6.0V
8K
Program Memory x16
(EPROM)
(ROM)
-
2K
-
-
4K
-
Data Memory (bytes)
232
-
232
Yes
Yes
Yes
Yes
Yes
2
232
Yes
Yes
Yes
Yes
Yes
2
454
Yes
Yes
Yes
Yes
Yes
2
454
Yes
Yes
Yes
Yes
Yes
2
454
Yes
Yes
Yes
Yes
Yes
2
Hardware Multiplier (8 x 8)
Timer0 (16-bit + 8-bit postscaler)
Timer1 (8-bit)
Yes
Yes
Yes
Yes
2
Timer2 (8-bit)
Timer3 (16-bit)
Capture inputs (16-bit)
PWM outputs (up to 10-bit)
USART/SCI
2
2
2
2
2
2
Yes
Yes
Yes
Yes
11
Yes
Yes
Yes
Yes
11
Yes
Yes
Yes
Yes
11
Yes
Yes
Yes
Yes
11
Yes
Yes
Yes
Yes
11
Yes
Yes
Yes
Yes
11
Power-on Reset
Watchdog Timer
External Interrupts
Interrupt Sources
Program Memory Code Protect
I/O Pins
Yes
33
Yes
33
Yes
33
Yes
33
Yes
33
Yes
33
I/O High Current Capabil- Source
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
ity
(1)
(1)
(1)
(1)
(1)
(1)
Sink
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
Package Types
40-pin DIP
40-pin DIP
40-pin DIP
40-pin DIP
40-pin DIP
40-pin DIP
44-pin PLCC 44-pin PLCC 44-pin PLCC 44-pin PLCC 44-pin PLCC 44-pin PLCC
44-pin MQFP 44-pin MQFP 44-pin MQFP 44-pin MQFP 44-pin MQFP 44-pin MQFP
44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP
Note 1: Pins RA2 and RA3 can sink up to 60 mA.
DS30412C-page 6
1996 Microchip Technology Inc.
PIC17C4X
2.3
Quick-Turnaround-Production (QTP)
Devices
2.0
PIC17C4X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC17C4X Product Selec-
tion System section at the end of this data sheet. When
placing orders, please use the “PIC17C4X Product
Identification System” at the back of this data sheet to
specify the correct part number.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
For the PIC17C4X family of devices, there are four
device “types” as indicated in the device number:
1. C, as in PIC17C42. These devices have
EPROM type memory and operate over the
standard voltage range.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
2. LC, as in PIC17LC42. These devices have
EPROM type memory, operate over an
extended voltage range, and reduced frequency
range.
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with different serial numbers.The serial num-
bers may be random, pseudo-random or sequential.
3. CR, as in PIC17CR42. These devices have
ROM type memory and operate over the stan-
dard voltage range.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
4. LCR, as in PIC17LCR42. These devices have
ROM type memory, operate over an extended
voltage range, and reduced frequency range.
ROM devices do not allow serialization information in
the program memory space.
For information on submitting ROM code, please con-
tact your regional sales office.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot pro-
grams.
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, thus giving customers a low
cost option for high volume, mature products.
The UV erasable version can be erased and repro-
grammed to any of the configuration modes.
Microchip's PRO MATE programmer supports pro-
gramming of the PIC17C4X. Third party programmers
also are available; refer to the Third Party Guide for a
list of sources.
For information on submitting ROM code, please con-
tact your regional sales office.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1996 Microchip Technology Inc.
DS30412C-page 7
PIC17C4X
NOTES:
DS30412C-page 8
1996 Microchip Technology Inc.
PIC17C4X
The PIC17CXX devices contain an 8-bit ALU and work-
ing register. The ALU is a general purpose arithmetic
unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC17C4X can be attrib-
uted to a number of architectural features commonly
found in RISC microprocessors. To begin with, the
PIC17C4X uses a modified Harvard architecture. This
architecture has the program and data accessed from
separate memories. So the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions to
be sized differently than the 8-bit wide data word.
PIC17C4X opcodes are 16-bits wide, enabling single
word instructions.The full 16-bit wide program memory
bus fetches a 16-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions. Consequently, all instructions execute in a single
cycle (121 ns @ 33 MHz), except for program branches
and two special instructions that transfer data between
program and data memory.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift, and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature.
The WREG register is an 8-bit working register used for
ALU operations.
All PIC17C4X devices (except the PIC17C42) have an
8 x 8 hardware multiplier. This multiplier generates a
16-bit result in a single cycle.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register.The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
Although the ALU does not perform signed arithmetic,
the Overflow bit (OV) can be used to implement signed
math. Signed arithmetic is comprised of a magnitude
and a sign bit. The overflow bit indicates if the magni-
tude overflows and causes the sign bit to change state.
Signed math can have greater than 7-bit values (mag-
nitude), if more than one byte is used. The use of the
overflow bit only operates on bit6 (MSb of magnitude)
and bit7 (sign bit) of the value in the ALU. That is, the
overflow bit is not useful if trying to implement signed
math where the magnitude, for example, is 11-bits. If
the signed math values are greater than 7-bits (15-, 24-
or 31-bit), the algorithm must ensure that the low order
bytes ignore the overflow status bit.
The PIC17C4X can address up to 64K x 16 of program
memory space.
The PIC17C42 and PIC17C42A integrate 2K x 16 of
EPROM program memory on-chip, while the
PIC17CR42 has 2K x 16 of ROM program memory on-
chip.
The PIC17C43 integrates 4K x 16 of EPROM program
memory, while the PIC17CR43 has 4K x 16 of ROM
program memory.
The PIC17C44 integrates 8K x 16 EPROM program
memory.
Program execution can be internal only (microcontrol-
ler or protected microcontroller mode), external only
(microprocessor mode) or both (extended microcon-
troller mode). Extended microcontroller mode does not
allow code protection.
Care should be taken when adding and subtracting
signed numbers to ensure that the correct operation is
executed. Example 3-1 shows an item that must be
taken into account when doing signed arithmetic on an
ALU which operates as an unsigned machine.
The PIC17CXX can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the Program Counter (PC) and Working
Register (WREG), are mapped in the data memory.
The PIC17CXX has an orthogonal (symmetrical)
instruction set that makes it possible to carry out any
operation on any register using any addressing mode.
This symmetrical nature and lack of ‘special optimal sit-
uations’ make programming with the PIC17CXX simple
yet efficient. In addition, the learning curve is reduced
significantly.
EXAMPLE 3-1: SIGNED MATH
Hex Value
Signed Value
Math
Unsigned Value
Math
FFh
-127
255
+ 01h
+
1
+
=
1
=
?
= -126 (FEh)
0 (00h);
Carry bit = 1
Signed math requires the result in REG to
be FEh (-126). This would be accomplished
by subtracting one as opposed to adding
one.
One of the PIC17CXX family architectural enhance-
ments from the PIC16CXX family allows two file regis-
ters to be used in some two operand instructions. This
allows data to be moved directly between two registers
without going through the WREG register. This
increases performance and decreases program mem-
ory usage.
Simplified block diagrams are shown in Figure 3-1 and
Figure 3-2. The descriptions of the device pins are
listed in Table 3-1.
1996 Microchip Technology Inc.
DS30412C-page 9
PIC17C4X
FIGURE 3-1: PIC17C42 BLOCK DIAGRAM
U S B A < T 8 A > D
DS30412C-page 10
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 3-2: PIC17CR42/42A/43/R43/44 BLOCK DIAGRAM
U S B A < T 8 A > D
1996 Microchip Technology Inc.
DS30412C-page 11
PIC17C4X
TABLE 3-1: PINOUT DESCRIPTIONS
DIP PLCC QFP I/O/P Buffer
Name
Description
No.
No.
No. Type Type
OSC1/CLKIN
19
21
37
38
I
ST
—
Oscillator input in crystal/resonator or RC oscillator mode.
External clock input in external clock mode.
OSC2/CLKOUT
20
32
22
35
O
Oscillator output. Connects to crystal or resonator in crystal
oscillator mode. In RC oscillator or external clock modes
OSC2 pin outputs CLKOUT which has one fourth the fre-
quency of OSC1 and denotes the instruction cycle rate.
MCLR/VPP
7
I/P
ST
Master clear (reset) input/Programming Voltage (VPP) input.
This is the active low reset input to the chip.
PORTA is a bi-directional I/O Port except for RA0 and RA1
which are input only.
RA0/INT
26
25
28
27
44
43
I
I
ST
ST
RA0/INT can also be selected as an external interrupt
input. Interrupt can be configured to be on positive or
negative edge.
RA1/T0CKI
RA1/T0CKI can also be selected as an external interrupt
input, and the interrupt can be configured to be on posi-
tive or negative edge. RA1/T0CKI can also be selected
to be the clock input to the Timer0 timer/counter.
RA2
24
23
22
26
25
24
42
41
40
I/O
I/O
I/O
ST
ST
ST
High voltage, high current, open drain input/output port
pins.
RA3
High voltage, high current, open drain input/output port
pins.
RA4/RX/DT
RA4/RX/DT can also be selected as the USART (SCI)
Asynchronous Receive or USART (SCI) Synchronous
Data.
RA5/TX/CK
21
23
39
I/O
ST
RA5/TX/CK can also be selected as the USART (SCI)
Asynchronous Transmit or USART (SCI) Synchronous
Clock.
PORTB is a bi-directional I/O Port with software configurable
weak pull-ups.
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
11
12
13
14
15
13
14
15
16
17
29
30
31
32
33
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RB0/CAP1 can also be the CAP1 input pin.
RB1/CAP2 can also be the CAP2 input pin.
RB2/PWM1 can also be the PWM1 output pin.
RB3/PWM2 can also be the PWM2 output pin.
RB4/TCLK12 can also be the external clock input to
Timer1 and Timer2.
RB5/TCLK3
16
18
34
I/O
ST
RB5/TCLK3 can also be the external clock input to
Timer3.
RB6
RB7
17
18
19
20
35
36
I/O
I/O
ST
ST
PORTC is a bi-directional I/O Port.
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
2
3
4
5
6
7
8
9
3
4
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
This is also the lower half of the 16-bit wide system bus
in microprocessor mode or extended microcontroller
mode. In multiplexed system bus configuration, these
pins are address output as well as data input or output.
5
6
7
8
9
10
Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;
ST = Schmitt Trigger input.
DS30412C-page 12
1996 Microchip Technology Inc.
PIC17C4X
TABLE 3-1: PINOUT DESCRIPTIONS
DIP PLCC QFP I/O/P Buffer
Name
Description
No.
No.
No. Type Type
PORTD is a bi-directional I/O Port.
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
40
39
38
37
36
35
34
33
43
42
41
40
39
38
37
36
15
14
13
12
11
10
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
This is also the upper byte of the 16-bit system bus in
microprocessor mode or extended microprocessor mode
or extended microcontroller mode. In multiplexed system
bus configuration these pins are address output as well
as data input or output.
8
PORTE is a bi-directional I/O Port.
RE0/ALE
30
32
4
I/O
TTL
In microprocessor mode or extended microcontroller
mode, it is the Address Latch Enable (ALE) output.
Address should be latched on the falling edge of ALE
output.
RE1/OE
RE2/WR
TEST
29
28
27
31
30
29
11,
3
2
I/O
I/O
I
TTL
TTL
ST
In microprocessor or extended microcontroller mode, it is
the Output Enable (OE) control output (active low).
In microprocessor or extended microcontroller mode, it is
the Write Enable (WR) control output (active low).
1
Test mode selection control input. Always tie to VSS for nor-
mal operation.
VSS
10,
31
5, 6,
P
Ground reference for logic and I/O pins.
12, 27, 28
33, 34
VDD
1
1, 44 16, 17
P
Positive supply for logic and I/O pins.
Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;
ST = Schmitt Trigger input.
1996 Microchip Technology Inc.
DS30412C-page 13
PIC17C4X
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3, and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 3-3.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g.GOTO) then
two cycles are required to complete the instruction
(Example 3-2).
A fetch cycle begins with the program counter incre-
menting in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-2: INSTRUCTION PIPELINE FLOW
Tcy0
Tcy1
Tcy2
Tcy3
Tcy4
Tcy5
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30412C-page 14
1996 Microchip Technology Inc.
PIC17C4X
4.1
Power-on Reset (POR), Power-up
Timer (PWRT), and Oscillator Start-up
Timer (OST)
4.0
RESET
The PIC17CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
4.1.1
POWER-ON RESET (POR)
• MCLR reset during normal operation
• WDT Reset (normal operation)
The Power-on Reset circuit holds the device in reset
until VDD is above the trip point (in the range of 1.4V -
2.3V). The PIC17C42 does not produce an internal
reset when VDD declines. All other devices will produce
an internal reset for both rising and falling VDD. To take
advantage of the POR, just tie the MCLR/VPP pin
directly (or through a resistor) to VDD.This will eliminate
external RC components usually needed to create
Power-on Reset. A minimum rise time for VDD is
required. See Electrical Specifications for details.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are forced to a “reset
state” on Power-on Reset (POR), on MCLR or WDT
Reset and on MCLR reset during SLEEP. They are not
affected by a WDT Reset during SLEEP, since this reset
is viewed as the resumption of normal operation. The
TO and PD bits are set or cleared differently in different
reset situations as indicated in Table 4-3.These bits are
used in software to determine the nature of reset. See
Table 4-4 for a full description of reset states of all reg-
isters.
4.1.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from rising edge of
the POR signal and after the first rising edge of MCLR
(detected high). The Power-up Timer operates on an
internal RC oscillator. The chip is kept in RESET as
long as the PWRT is active. In most cases the PWRT
delay allows the VDD to rise to an acceptable level.
Note: While the device is in a reset state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
The power-up time delay will vary from chip to chip and
to VDD and temperature. See DC parameters for
details.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 4-1.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
WDT
Time_Out
Reset
VDD rise
detect
S
R
Power_On_Reset
VDD
OST/PWRT
Chip_Reset
Q
OST
10-bit Ripple counter
OSC1
PWRT
On-chip
RC OSC†
10-bit Ripple counter
Power_Up
(Enable the PWRT timer
only during Power_Up)
(Power_Up + Wake_Up) (XT + LF)
(Enable the OST if it is Power_Up or Wake_Up
from SLEEP and OSC type is XT or LF)
† This RC oscillator is shared with the WDT
when not in a power-up sequence.
1996 Microchip Technology Inc.
DS30412C-page 15
PIC17C4X
4.1.3
OSCILLATOR START-UP TIMER (OST)
TABLE 4-1:
TIME-OUT IN VARIOUS
SITUATIONS
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024TOSC) delay after MCLR is
detected high or a wake-up from SLEEP event occurs.
Oscillator
Configuration
Power-up
Wake up
from
MCLR
Reset
SLEEP
The OST time-out is invoked only for XT and LF oscilla-
tor modes on a Power-on Reset or a Wake-up from
SLEEP.
XT, LF
Greater of:
96 ms or
1024TOSC
—
—
1024TOSC
The OST counts the oscillator pulses on the
OSC1/CLKIN pin.The counter only starts incrementing
after the amplitude of the signal reaches the oscillator
input thresholds. This delay allows the crystal oscillator
or resonator to stabilize before the device exits reset.
The length of time-out is a function of the crystal/reso-
nator frequency.
EC, RC
Greater of:
96 ms or
1024TOSC
—
The time-out sequence begins from the first rising edge
of MCLR.
Table 4-3 shows the reset conditions for some special
registers, while Table 4-4 shows the initialization condi-
tions for all the registers. The shaded registers (in
Table 4-4) are for all devices except the PIC17C42. In
the PIC17C42, the PRODH and PRODL registers are
general purpose RAM.
4.1.4
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resona-
tors. The total time-out also varies based on oscillator
configuration. Table 4-1 shows the times that are asso-
ciated with the oscillator configuration. Figure 4-2 and
Figure 4-3 display these time-out sequences.
TABLE 4-2:
STATUS BITS AND THEIR
SIGNIFICANCE
TO PD
Event
1
1
1
0
Power-on Reset, MCLR Reset during normal
operation, or CLRWDTinstruction executed
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/VPP pin must be
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
MCLR Reset during SLEEP or interrupt wake-up
from SLEEP
0
0
1
0
WDT Reset during normal operation
WDT Reset during SLEEP
In Figure 4-2, Figure 4-3 and Figure 4-4, TPWRT >
TOST, as would be the case in higher frequency crys-
tals. For lower frequency crystals, (i.e., 32 kHz) TOST
would be greater.
TABLE 4-3:
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
PCH:PCL
CPUSTA
OST Active
Event
Power-on Reset
0000h
0000h
0000h
--11 11--
--11 11--
--11 10--
Yes
No
MCLR Reset during normal operation
MCLR Reset during SLEEP
(2)
Yes
WDT Reset during normal operation
0000h
0000h
--11 01--
--11 00--
No
(3)
(2)
WDT Reset during SLEEP
Yes
(2)
Interrupt wake-up from SLEEP GLINTD is set
GLINTD is clear
PC + 1
--11 10--
--10 10--
Yes
(1)
(2)
PC + 1
Yes
Legend: u= unchanged, x= unknown, -= unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is the device branches to the reset vector. This is different from the
mid-range devices.
DS30412C-page 16
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 4-2: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4: SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1996 Microchip Technology Inc.
DS30412C-page 17
PIC17C4X
FIGURE 4-5: OSCILLATORSTART-UPTIME
FIGURE 4-8: PIC17C42 EXTERNAL
POWER-ON RESET CIRCUIT
(FOR SLOW VDD
POWER-UP)
VDD
VDD
VDD
MCLR
OSC2
D
R
R1
MCLR
TOSC1
TOST
PIC17C42
C
OST TIME_OUT
PWRT TIME_OUT
Note 1: An external Power-on Reset circuit is
required only if VDD power-up time is too
slow. The diode D helps discharge the
capacitor quickly when VDD powers
down.
TPWRT
INTERNAL RESET
This figure shows in greater detail the timings involved
with the oscillator start-up timer. In this example the
low frequency crystal start-up time is larger than
power-up time (TPWRT).
Tosc1 = time for the crystal oscillator to react to an
oscillation level detectable by the Oscillator Start-up
Timer (ost).
2: R < 40 kΩ is recommended to ensure
that the voltage drop across R does not
exceed 0.2V (max. leakage current spec.
on the MCLR/VPP pin is 5 µA). A larger
voltage drop will degrade VIH level on the
MCLR/VPP pin.
TOST = 1024TOSC.
FIGURE 4-6: USING ON-CHIP POR
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capaci-
tor C in the event of MCLR/VPP pin
breakdown due to Electrostatic Dis-
charge (ESD) or (Electrical Overstress)
EOS.
VDD
VDD
MCLR
PIC17CXX
FIGURE 4-9: BROWN-OUT PROTECTION
CIRCUIT 2
FIGURE 4-7: BROWN-OUT PROTECTION
CIRCUIT 1
VDD
VDD
R1
VDD
Q1
VDD
MCLR
33k
R2
40 kΩ
PIC17CXX
10k
MCLR
40 kΩ
PIC17CXX
This brown-out circuit is less expensive, albeit less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
R1
This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
= 0.7V
VDD •
R1 + R2
DS30412C-page 18
1996 Microchip Technology Inc.
PIC17C4X
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Address
Power-on Reset
Unbanked
INDF0
FSR0
00h
01h
02h
0000 0000
xxxx xxxx
0000h
0000 0000
uuuu uuuu
0000h
0000 0000
uuuu uuuu
PC + 1(2)
uuuu uuuu
1111 uuuu
0000 000-
--uu qq--
PCL
PCLATH
ALUSTA
T0STA
03h
04h
05h
06h
0000 0000
1111 xxxx
0000 000-
--11 11--
0000 0000
1111 uuuu
0000 000-
--11 qq--
CPUSTA(3)
uuuu uuuu(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
INTSTA
07h
0000 0000
0000 0000
INDF1
FSR1
08h
09h
0Ah
0Bh
0Ch
0Dh
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WREG
TMR0L
TMR0H
TBLPTRL (4)
TBLPTRH (4)
TBLPTRL (5)
0Eh
0Dh
0Eh
0Fh
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLPTRH (5)
BSR
Bank 0
PORTA
DDRB
10h
11h
12h
13h
14h
15h
16h
17h
0-xx xxxx
1111 1111
xxxx xxxx
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
xxxx xxxx
0-uu uuuu
1111 1111
uuuu uuuu
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu --uu
uuuu uuuu
uuuu uuuu
PORTB
RCSTA
RCREG
TXSTA
TXREG
SPBRG
Bank 1
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
PIR
10h
11h
12h
13h
14h
15h
16h
1111 1111
xxxx xxxx
1111 1111
xxxx xxxx
---- -111
---- -xxx
0000 0010
1111 1111
uuuu uuuu
1111 1111
uuuu uuuu
---- -111
---- -uuu
0000 0010
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---- -uuu
uuuu uuuu(1)
PIE
17h
0000 0000
0000 0000
uuuu uuuu
Legend: u= unchanged, x= unknown, -= unimplemented read as '0', q= value depends on condition.
Note 1: One or more bits in INTSTA, PIR will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 4-3 for reset value of specific condition.
4: Only applies to the PIC17C42.
5: Does not apply to the PIC17C42.
1996 Microchip Technology Inc.
DS30412C-page 19
PIC17C4X
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Address
Power-on Reset
Bank 2
TMR1
10h
11h
12h
13h
14h
15h
16h
17h
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR2
TMR3L
TMR3H
PR1
PR2
PR3/CA1L
PR3/CA1H
Bank 3
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
10h
11h
12h
13h
14h
15h
16h
17h
xx-- ----
xx-- ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
uu-- ----
uu-- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uu-- ----
uu-- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
CA2H
TCON1
TCON2
Unbanked
PRODL (5)
PRODH (5)
18h
19h
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Legend: u= unchanged, x= unknown, -= unimplemented read as '0', q= value depends on condition.
Note 1: One or more bits in INTSTA, PIR will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 4-3 for reset value of specific condition.
4: Only applies to the PIC17C42.
5: Does not apply to the PIC17C42.
DS30412C-page 20
1996 Microchip Technology Inc.
PIC17C4X
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address.There are four
interrupt vectors. Each vector address is for a specific
interrupt source (except the peripheral interrupts which
have the same vector address). These sources are:
5.0
INTERRUPTS
The PIC17C4X devices have 11 sources of interrupt:
• External interrupt from the RA0/INT pin
• Change on RB7:RB0 pins
• TMR0 Overflow
• TMR1 Overflow
• TMR2 Overflow
• TMR3 Overflow
• USART Transmit buffer empty
• USART Receive buffer full
• Capture1
• External interrupt from the RA0/INT pin
• TMR0 Overflow
• T0CKI edge occurred
• Any peripheral interrupt
When program execution vectors to one of these inter-
rupt vector addresses (except for the peripheral inter-
rupt address), the interrupt flag bit is automatically
cleared. Vectoring to the peripheral interrupt vector
address does not automatically clear the source of the
interrupt. In the peripheral interrupt service routine, the
source(s) of the interrupt can be determined by testing
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
• Capture2
• T0CKI edge occurred
There are four registers used in the control and status
of interrupts. These are:
• CPUSTA
• INTSTA
• PIE
• PIR
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Memory Orga-
nization section.
All of the individual interrupt flag bits will be set regard-
less of the status of their corresponding mask bit or the
GLINTD bit.
For external interrupt events, there will be an interrupt
latency. For two cycle instructions, the latency could be
one instruction cycle longer.
The “return from interrupt” instruction, RETFIE, can be
used to mark the end of the interrupt service routine.
When this instruction is executed, the stack is
“POPed”, and the GLINTD bit is cleared (to re-enable
interrupts).
FIGURE 5-1: INTERRUPT LOGIC
TMR1IF
TMR1IE
Wake-up (If in SLEEP mode)
or terminate long write
TMR2IF
TMR2IE
T0IF
T0IE
TMR3IF
TMR3IE
INTF
INTE
Interrupt to CPU
CA1IF
CA1IE
T0CKIF
T0CKIE
CA2IF
CA2IE
PEIF
PEIE
TXIF
TXIE
GLINTD
RCIF
RCIE
RBIF
RBIE
1996 Microchip Technology Inc.
DS30412C-page 21
PIC17C4X
5.1
Interrupt Status Register (INTSTA)
Note: T0IF, INTF, T0CKIF, or PEIF will be set by
the specified condition, even if the corre-
sponding interrupt enable bit is clear (inter-
rupt disabled) or the GLINTD bit is set (all
interrupts disabled).
The Interrupt Status/Control register (INTSTA) records
the individual interrupt requests in flag bits, and con-
tains the individual interrupt enable bits (not for the
peripherals).
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is
cleared, the device will vector to the reset address
(0x00).
The PEIF bit is a read only, bit wise OR of all the periph-
eral flag bits in the PIR register (Figure 5-4).
When disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
FIGURE 5-2: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R - 0
PEIF
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin
PEIE: Peripheral Interrupt Enable bit
This bit enables all peripheral interrupts that have their corresponding enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
bit 2:
bit 1:
bit 0:
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin
DS30412C-page 22
1996 Microchip Technology Inc.
PIC17C4X
5.2
Peripheral Interrupt Enable Register
(PIE)
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 5-3: PIE REGISTER (ADDRESS: 17h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TXIE
RCIE
bit7
bit0
bit 7:
RBIE: PORTB Interrupt on Change Enable bit
1 = Enable PORTB interrupt on change
0 = Disable PORTB interrupt on change
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TMR3IE: Timer3 Interrupt Enable bit
1 = Enable Timer3 interrupt
0 = Disable Timer3 interrupt
TMR2IE: Timer2 Interrupt Enable bit
1 = Enable Timer2 interrupt
0 = Disable Timer2 interrupt
TMR1IE: Timer1 Interrupt Enable bit
1 = Enable Timer1 interrupt
0 = Disable Timer1 interrupt
CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture interrupt on RB1/CAP2 pin
0 = Disable Capture interrupt on RB1/CAP2 pin
CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture interrupt on RB2/CAP1 pin
0 = Disable Capture interrupt on RB2/CAP1 pin
TXIE: USART Transmit Interrupt Enable bit
1 = Enable Transmit buffer empty interrupt
0 = Disable Transmit buffer empty interrupt
RCIE: USART Receive Interrupt Enable bit
1 = Enable Receive buffer full interrupt
0 = Disable Receive buffer full interrupt
1996 Microchip Technology Inc.
DS30412C-page 23
PIC17C4X
5.3
Peripheral Interrupt Request Register
(PIR)
Note: These bits will be set by the specified con-
dition, even if the corresponding interrupt
enable bit is cleared (interrupt disabled), or
the GLINTD bit is set (all interrupts dis-
abled). Before enabling an interrupt, the
user may wish to clear the interrupt flag to
ensure that the program does not immedi-
ately branch to the peripheral interrupt ser-
vice routine.
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 5-4: PIR REGISTER (ADDRESS: 16h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R - 1 R - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
RBIF TMR3IF TMR2IF TMR1IF CA2IF
CA1IF
TXIF RCIF
bit7
bit0
bit 7:
bit 6:
RBIF: PORTB Interrupt on Change Flag bit
1 = One of the PORTB inputs changed (Software must end the mismatch condition)
0 = None of the PORTB inputs have changed
TMR3IF: Timer3 Interrupt Flag bit
If Capture1 is enabled (CA1/PR3 = 1)
1 = Timer3 overflowed
0 = Timer3 did not overflow
If Capture1 is disabled (CA1/PR3 = 0)
1 = Timer3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value
0 = Timer3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L) value
bit 5:
bit 4:
TMR2IF: Timer2 Interrupt Flag bit
1 = Timer2 value has rolled over to 0000h from equalling the period register (PR2) value
0 = Timer2 value has not rolled over to 0000h from equalling the period register (PR2) value
TMR1IF: Timer1 Interrupt Flag bit
If Timer1 is in 8-bit mode (T16 = 0)
1 = Timer1 value has rolled over to 0000h from equalling the period register (PR) value
0 = Timer1 value has not rolled over to 0000h from equalling the period register (PR2) value
If Timer1 is in 16-bit mode (T16 = 1)
1 = TMR1:TMR2 value has rolled over to 0000h from equalling the period register (PR1:PR2) value
0 = TMR1:TMR2 value has not rolled over to 0000h from equalling the period register (PR1:PR2) value
bit 3:
bit 2:
bit 1:
bit 0:
CA2IF: Capture2 Interrupt Flag bit
1 = Capture event occurred on RB1/CAP2 pin
0 = Capture event did not occur on RB1/CAP2 pin
CA1IF: Capture1 Interrupt Flag bit
1 = Capture event occurred on RB0/CAP1 pin
0 = Capture event did not occur on RB0/CAP1 pin
TXIF: USART Transmit Interrupt Flag bit
1 = Transmit buffer is empty
0 = Transmit buffer is full
RCIF: USART Receive Interrupt Flag bit
1 = Receive buffer is full
0 = Receive buffer is empty
DS30412C-page 24
1996 Microchip Technology Inc.
PIC17C4X
5.4
Interrupt Operation
Note 1: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GLINTD bit.
Global Interrupt Disable bit, GLINTD (CPUSTA<4>),
enables all unmasked interrupts (if clear) or disables all
interrupts (if set). Individual interrupts can be disabled
through their corresponding enable bits in the INTSTA
register. Peripheral interrupts need either the global
peripheral enable PEIE bit disabled, or the specific
peripheral enable bit disabled. Disabling the peripher-
als via the global peripheral enable bit, disables all
peripheral interrupts. GLINTD is set on reset (interrupts
disabled).
Note 2: When disabling any of the INTSTA enable
bits, the GLINTD bit should be set
(disabled).
Note 3: For the PIC17C42 only:
If an interrupt occurs while the Global Inter-
rupt Disable (GLINTD) bit is being set, the
GLINTD bit may unintentionally be re-
enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
The RETFIEinstruction allows returning from interrupt
and re-enable interrupts at the same time.
1. An interrupt occurs simultaneously
with an instruction that sets the
GLINTD bit.
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with interrupt vector. There are four interrupt
vectors to reduce interrupt latency.
2. The program branches to the Interrupt
vector and executes the Interrupt Ser-
vice Routine.
The peripheral interrupt vector has multiple interrupt
sources. Once in the peripheral interrupt service rou-
tine, the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The peripheral interrupt
flag bit(s) must be cleared in software before re-
enabling interrupts to avoid continuous interrupts.
3. The Interrupt Service Routine com-
pletes with the execution of the RET-
FIE instruction. This causes the
GLINTD bit to be cleared (enables
interrupts), and the program returns to
the instruction after the one which was
meant to disable interrupts.
The PIC17C4X devices have four interrupt vectors.
These vectors and their hardware priority are shown in
Table 5-1. If two enabled interrupts occur “at the same
time”, the interrupt of the highest priority will be ser-
viced first. This means that the vector address of that
interrupt will be loaded into the program counter (PC).
The method to ensure that interrupts are
globally disabled is:
1. Ensure that the GLINTD bit was set by
the instruction, as shown in the follow-
ing code:
TABLE 5-1:
INTERRUPT VECTORS/
PRIORITIES
LOOP
BSF
CPUSTA, GLINTD ; Disable Global
; Interrupt
BTFSS CPUSTA, GLINTD ; Global Interrupt
; Disabled?
Address
Vector
Priority
GOTO
LOOP
; NO, try again
; YES, continue
; with program
; low
0008h
0010h
0018h
0020h
External Interrupt on RA0/
INT pin (INTF)
1 (Highest)
TMR0 overflow interrupt
(T0IF)
2
3
External Interrupt on T0CKI
(T0CKIF)
Peripherals (PEIF)
4 (Lowest)
1996 Microchip Technology Inc.
DS30412C-page 25
PIC17C4X
5.5
RA0/INT Interrupt
5.7
T0CKI Interrupt
The external interrupt on the RA0/INT pin is edge trig-
gered. Either the rising edge, if INTEDG bit
(T0STA<7>) is set, or the falling edge, if INTEDG bit is
clear. When a valid edge appears on the RA0/INT pin,
the INTF bit (INTSTA<4>) is set. This interrupt can be
disabled by clearing the INTE control bit (INTSTA<0>).
The INT interrupt can wake the processor from SLEEP.
See Section 14.4 for details on SLEEP operation.
The external interrupt on the RA1/T0CKI pin is edge
triggered. Either the rising edge, if the T0SE bit
(T0STA<6>) is set, or the falling edge, if the T0SE bit is
clear. When a valid edge appears on the RA1/T0CKI
pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt
can be disabled by clearing the T0CKIE control bit
(INTSTA<2>). The T0CKI interrupt can wake up the
processor from SLEEP. See Section 14.4 for details on
SLEEP operation.
5.6
TMR0 Interrupt
5.8
Peripheral Interrupt
An overflow (FFFFh → 0000h) in TMR0 will set the
T0IF (INTSTA<5>) bit. The interrupt can be enabled/
disabled by setting/clearing the T0IE control bit
(INTSTA<1>). For operation of the Timer0 module, see
Section 11.0.
The peripheral interrupt flag indicates that at least one
of the peripheral interrupts occurred (PEIF is set). The
PEIF bit is a read only bit, and is a bit wise OR of all the
flag bits in the PIR register AND’ed with the corre-
sponding enable bits in the PIE register. Some of the
peripheral interrupts can wake the processor from
SLEEP. See Section 14.4 for details on SLEEP opera-
tion.
FIGURE 5-5: INT PIN / T0CKI PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OSC2
RA0/INT or
RA1/T0CKI
INTF or
T0CKIF
GLINTD
PC
PC
PC + 1
Addr (Vector)
YY
YY + 1
PC + 1
System Bus
Instruction
Fetched
Addr
Addr
Addr
Addr
Addr
Inst (YY + 1)
PC Inst (PC)
Inst (PC+1)
Inst (Vector)
Inst (PC+1)
RETFIE
Instruction
executed
Dummy
Inst (PC)
Dummy
Dummy
RETFIE
DS30412C-page 26
1996 Microchip Technology Inc.
PIC17C4X
Example 5-1 shows the saving and restoring of infor-
mation for an interrupt service routine. The PUSH and
POP routines could either be in each interrupt service
routine or could be subroutines that were called.
Depending on the application, other registers may also
need to be saved, such as PCLATH.
5.9
Context Saving During Interrupts
During an interrupt, only the returned PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt; e.g. WREG, ALUSTA and the
BSR registers. This requires implementation in soft-
ware.
EXAMPLE 5-1: SAVING STATUS AND WREG IN RAM
;
; The addresses that are used to store the CPUSTA and WREG values
; must be in the data memory address range of 18h - 1Fh. Up to
; 8 locations can be saved and restored using
; the MOVFP instruction. This instruction neither affects the status
; bits, nor corrupts the WREG register.
;
;
PUSH
MOVFP
MOVFP
MOVFP
WREG, TEMP_W
ALUSTA, TEMP_STATUS ; Save ALUSTA
; Save WREG
BSR, TEMP_BSR
TEMP_W, WREG
; Save BSR
ISR
POP
:
:
; This is the interrupt service routine
; Restore WREG
MOVFP
MOVFP
MOVFP
RETFIE
TEMP_STATUS, ALUSTA ; Restore ALUSTA
TEMP_BSR, BSR
; Restore BSR
; Return from Interrupts enabled
1996 Microchip Technology Inc.
DS30412C-page 27
PIC17C4X
NOTES:
DS30412C-page 28
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 6-1: PROGRAM MEMORY MAP
AND STACK
6.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC17C4X; pro-
gram memory and data memory. Each block has its
own bus, so that access to each block can occur during
the same oscillator cycle.
PC<15:0>
16
CALL, RETURN
RETFIE, RETLW
Stack Level 1
The data memory can further be broken down into Gen-
eral Purpose RAM and the Special Function Registers
(SFRs). The operation of the SFRs that control the
“core” are described here. The SFRs used to control
the peripheral modules are described in the section dis-
cussing each individual peripheral module.
•
•
•
Stack Level 16
Reset Vector
0000h
INT Pin Interrupt Vector
Timer0 Interrupt Vector
T0CKI Pin Interrupt Vector
Peripheral Interrupt Vector
0008h
0010h
0018h
6.1
Program Memory Organization
PIC17C4X devices have a 16-bit program counter
capable of addressing a 64K x 16 program memory
space. The reset vector is at 0000h and the interrupt
vectors are at 0008h, 0010h, 0018h, and 0020h
(Figure 6-1).
0020h
0021h
7FFh
(PIC17C42,
PIC17CR42,
PIC17C42A)
6.1.1
PROGRAM MEMORY OPERATION
The PIC17C4X can operate in one of four possible pro-
gram memory configurations. The configuration is
selected by two configuration bits. The possible modes
are:
FFFh
(PIC17C43
PIC17CR43)
• Microprocessor
• Microcontroller
1FFFh
(PIC17C44)
• Extended Microcontroller
• Protected Microcontroller
The microcontroller and protected microcontroller
modes only allow internal execution. Any access
beyond the program memory reads unknown data.
The protected microcontroller mode also enables the
code protection feature.
FDFFh
FE00h
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
Reserved
PM1
Reserved
FE01h
FE02h
FE03h
FE04h
FE05h
FE06h
FE07h
The extended microcontroller mode accesses both the
internal program memory as well as external program
memory. Execution automatically switches between
internal and external memory. The 16-bits of address
allow a program memory range of 64K-words.
FE08h
Reserved
FE0Eh
The microprocessor mode only accesses the external
program memory. The on-chip program memory is
ignored. The 16-bits of address allow a program mem-
ory range of 64K-words. Microprocessor mode is the
default mode of an unprogrammed device.
(2)
PM2
FE0Fh
FE10h
Test EPROM
Boot ROM
FF5Fh
FF60h
FFFFh
The different modes allow different access to the con-
figuration bits, test memory, and boot ROM. Table 6-1
lists which modes can access which areas in memory.
Test Memory and Boot Memory are not required for
normal operation of the device. Care should be taken to
ensure that no unintended branches occur to these
areas.
Note 1: User memory space may be internal, external, or
both. The memory configuration depends on the
processor mode.
2: This location is reserved on the PIC17C42.
1996 Microchip Technology Inc.
DS30412C-page 29
PIC17C4X
The PIC17C4X can operate in modes where the pro-
gram memory is off-chip. They are the microprocessor
and extended microcontroller modes. The micropro-
cessor mode is the default for an unprogrammed
device.
TABLE 6-1:
MODE MEMORY ACCESS
Internal
Program
Memory
Configuration Bits,
Test Memory,
Boot ROM
Operating
Mode
Regardless of the processor mode, data memory is
always on-chip.
Microprocessor
Microcontroller
No Access
Access
No Access
Access
Extended
Microcontroller
Access
Access
No Access
Access
Protected
Microcontroller
FIGURE 6-2: MEMORY MAP IN DIFFERENT MODES
Extended
Microcontroller
Mode
Microcontroller
Modes
Microprocessor
Mode
PIC17C42,
PIC17CR42,
PIC17C42A
0000h
0000h
0000h
On-chip
Program
Memory
On-chip
Program
Memory
07FFh
0800h
07FFh
0800h
External
Program
Memory
External
Program
Memory
Config. Bits
Test Memory
Boot ROM
FE00h
FFFFh
FFFFh
FFFFh
OFF-CHIP
OFF-CHIP
ON-CHIP
00h
OFF-CHIP
ON-CHIP
OFF-CHIP
OFF-CHIP
ON-CHIP
00h
00h
FFh
FFh
ON-CHIP
FFh
ON-CHIP
OFF-CHIP
ON-CHIP
PIC17C43,
PIC17CR43,
PIC17C44
0000h
0000h
0000h
On-chip
Program
Memory
On-chip
Program
Memory
0FFFh/1FFFh
0FFFh/1FFFh
1000h/2000h
1000h/
2000h
External
Program
Memory
External
Program
Memory
Config. Bits
Test Memory
Boot ROM
FE00h
FFFFh
FFFFh
FFFFh
OFF-CHIP
ON-CHIP
120h
OFF-CHIP
ON-CHIP
OFF-CHIP
ON-CHIP
00h
00h
00h
FFh
120h
1FFh
120h
FFh
1FFh
FFh
1FFh
OFF-CHIP
ON-CHIP
OFF-CHIP
ON-CHIP
OFF-CHIP
ON-CHIP
DS30412C-page 30
1996 Microchip Technology Inc.
PIC17C4X
6.1.2
EXTERNAL MEMORY INTERFACE
In extended microcontroller mode, when the device is
executing out of internal memory, the control signals
will continue to be active. That is, they indicate the
action that is occurring in the internal memory. The
external memory access is ignored.
When either microprocessor or extended microcontrol-
ler mode is selected, PORTC, PORTD and PORTE are
configured as the system bus. PORTC and PORTD are
the multiplexed address/data bus and PORTE is for the
control signals. External components are needed to
demultiplex the address and data. This can be done as
shown in Figure 6-4. The waveforms of address and
data are shown in Figure 6-3. For complete timings,
please refer to the electrical specification section.
This following selection is for use with Microchip
EPROMs. For interfacing to other manufacturers mem-
ory, please refer to the electrical specifications of the
desired PIC17C4X device, as well as the desired mem-
ory device to ensure compatibility.
TABLE 6-2:
EPROM MEMORY ACCESS
TIME ORDERING SUFFIX
FIGURE 6-3: EXTERNAL PROGRAM
MEMORY ACCESS
WAVEFORMS
EPROM Suffix
Q1 Q2
Q4 Q1 Q2
Q4 Q1
Data out
Q3
Q3
PIC17C4X Instruction
Oscillator Cycle
Frequency Time (TCY) PIC17C42 PIC17C44
AD
<15:0>
PIC17C43
Address out Data in
Address out
ALE
OE
8 MHz
16 MHz
20 MHz
25 MHz
33 MHz
500 ns
250 ns
200 ns
160 ns
121 ns
-25
-12
-25
-15
-10
-70
(1)
'1'
WR
Read cycle
Write cycle
-90
The system bus requires that there is no bus conflict
(minimal leakage), so the output value (address) will be
capacitively held at the desired value.
N.A.
N.A.
As the speed of the processor increases, external
EPROM memory with faster access time must be used.
Table 6-2 lists external memory speed requirements for
a given PIC17C4X device frequency.
Note 1: The access times for this requires the use of
fast SRAMS.
Note: The external memory interface is not sup-
ported for the LC devices.
FIGURE 6-4: TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM
AD15-AD0
Memory
(LSB)
Memory
(MSB)
A15-A0
AD7-AD0
PIC17C4X
373
373
Ax-A0
D7-D0
Ax-A0
D7-D0
CE
CE
(2)
(2)
OE WR
OE WR
AD15-AD8
ALE
(1)
138
(1)
I/O
OE
WR
Note 1: Use of I/O pins is only required for paged memory.
2: This signal is unused for ROM and EPROM devices.
1996 Microchip Technology Inc.
DS30412C-page 31
PIC17C4X
6.2.1
GENERAL PURPOSE REGISTER (GPR)
6.2
Data Memory Organization
All devices have some amount of GPR area.The GPRs
are 8-bits wide. When the GPR area is greater than
232, it must be banked to allow access to the additional
memory space.
Data memory is partitioned into two areas. The first is
the General Purpose Registers (GPR) area, while the
second is the Special Function Registers (SFR) area.
The SFRs control the operation of the device.
Only the PIC17C43 and PIC17C44 devices have
banked memory in the GPR area.To facilitate switching
between these banks, the MOVLR bankinstruction has
been added to the instruction set. GPRs are not initial-
ized by a Power-on Reset and are unchanged on all
other resets.
Portions of data memory are banked, this is for both
areas. The GPR area is banked to allow greater than
232 bytes of general purpose RAM. SFRs are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the Bank Select Reg-
ister (BSR). If an access is made to a location outside
this banked region, the BSR bits are ignored.
Figure 6-5 shows the data memory map organization
for the PIC17C42 and Figure 6-6 for all of the other
PIC17C4X devices.
6.2.2
SPECIAL FUNCTION REGISTERS (SFR)
The SFRs are used by the CPU and peripheral func-
tions to control the operation of the device (Figure 6-5
and Figure 6-6). These registers are static RAM.
Instructions MOVPF and MOVFP provide the means to
move values from the peripheral area (“P”) to any loca-
tion in the register file (“F”), and vice-versa. The defini-
tion of the “P” range is from 0h to 1Fh, while the “F”
range is 0h to FFh. The “P” range has six more loca-
tions than peripheral registers (eight locations for the
PIC17C42 device) which can be used as General Pur-
pose Registers.This can be useful in some applications
where variables need to be copied to other locations in
the general purpose RAM (such as saving status infor-
mation during an interrupt).
The SFRs can be classified into two sets, those associ-
ated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described here, while those related to a
peripheral feature are described in the section for each
peripheral feature.
The peripheral registers are in the banked portion of
memory, while the core registers are in the unbanked
region. To facilitate switching between the peripheral
banks, the MOVLB bankinstruction has been provided.
The entire data memory can be accessed either directly
or indirectly through file select registers FSR0 and
FSR1 (Section 6.4). Indirect addressing uses the
appropriate control bits of the BSR for accesses into the
banked areas of data memory.The BSR is explained in
greater detail in Section 6.8.
DS30412C-page 32
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 6-5: PIC17C42 REGISTER FILE
MAP
FIGURE 6-6: PIC17CR42/42A/43/R43/44
REGISTER FILE MAP
Addr Unbanked
Addr Unbanked
INDF0
FSR0
INDF0
FSR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PCL
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
(1)
(1)
(1)
(1)
(1)
(1)
Bank 0 Bank 1
Bank 2
Bank 3
Bank 0
Bank 1
Bank 2
Bank 3
PORTA
DDRB
DDRC
TMR1
TMR2
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
PORTA
DDRB
DDRC
TMR1
TMR2
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
10h
11h
12h
13h
14h
15h
16h
17h
18h
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
PORTC
DDRD
PORTD
DDRE
PORTE
PIR
PORTC
DDRD
PORTD
DDRE
PORTE
PIR
PORTB
RCSTA
RCREG
TXSTA
TXREG
SPBRG
TMR3L
TMR3H
PR1
PORTB
RCSTA
RCREG
TXSTA
TXREG
SPBRG
PRODL
PRODH
TMR3L
TMR3H
PR1
PR2
CA2H
PR2
CA2H
PR3L/CA1L
PR3H/CA1H
TCON1
TCON2
PR3L/CA1L
PR3H/CA1H
TCON1
TCON2
PIE
PIE
1Fh
20h
General
Purpose
RAM
1Fh
20h
General
Purpose
General
Purpose
(2)
RAM
(2)
FFh
RAM
Note 1: SFR file locations 10h - 17h are banked. All
other SFRs ignore the Bank Select Register
(BSR) bits.
FFh
Note 1: SFR file locations 10h - 17h are banked. All
other SFRs ignore the Bank Select Register
(BSR) bits.
2: General Purpose Registers (GPR) locations
20h - FFh and 120h - 1FFh are banked. All
other GPRs ignore the Bank Select Register
(BSR) bits.
1996 Microchip Technology Inc.
DS30412C-page 33
PIC17C4X
TABLE 6-3:
SPECIAL FUNCTION REGISTERS
Value on
Power-on
Reset
Value on all
other
resets (3)
Address Name
Unbanked
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
01h
02h
INDF0
FSR0
Uses contents of FSR0 to address data memory (not a physical register)
Indirect data memory address pointer 0
Low order 8-bits of PC
---- ---- ---- ----
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
PCL
03h(1)
04h
PCLATH
ALUSTA
T0STA
Holding register for upper 8-bits of PC
FS3
FS2
FS1
FS0
PS3
OV
Z
DC
C
1111 xxxx 1111 uuuu
0000 000- 0000 000-
05h
INTEDG
T0SE
T0CS
PS2
PS1
PS0
—
06h(2)
07h
—
—
STKAV
T0IF
GLINTD
INTF
TO
PD
—
—
--11 11-- --11 qq--
CPUSTA
INTSTA
INDF1
PEIF
T0CKIF
PEIE
T0CKIE
T0IE
INTE
0000 0000 0000 0000
---- ---- ---- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
08h
Uses contents of FSR1 to address data memory (not a physical register)
Indirect data memory address pointer 1
Working register
09h
FSR1
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
TMR0 register; low byte
TMR0 register; high byte
Low byte of program memory table pointer
High byte of program memory table pointer
Bank select register
(4)
(4)
(4)
(4)
0000 0000 0000 0000
Bank 0
10h
PORTA
DDRB
RBPU
—
RA5
RA4
RA3
RA2
RA1/T0CKI RA0/INT 0-xx xxxx 0-uu uuuu
1111 1111 1111 1111
11h
Data direction register for PORTB
PORTB data latch
12h
PORTB
RCSTA
RCREG
TXSTA
TXREG
SPBRG
xxxx xxxx uuuu uuuu
13h
SPEN
Serial port receive register
CSRC TX9 TXEN
RX9
SREN
CREN
SYNC
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x 0000 -00u
xxxx xxxx uuuu uuuu
0000 --1x 0000 --1u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h
15h
16h
Serial port transmit register
Baud rate generator register
17h
Bank 1
10h
DDRC
PORTC
DDRD
PORTD
DDRE
Data direction register for PORTC
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- -111 ---- -111
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
11h
12h
13h
Data direction register for PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
14h
15h
16h
17h
Data direction register for PORTE
PORTE
PIR
—
—
—
—
—
RE2/WR
CA1IF
RE1/OE
TXIF
RE0/ALE ---- -xxx ---- -uuu
RBIF
RBIE
TMR3IF
TMR2IF
TMR1IF
TMR1IE
CA2IF
CA2IE
RCIF
RCIE
0000 0010 0000 0010
0000 0000 0000 0000
PIE
TMR3IE TMR2IE
CA1IE
TXIE
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
2:
3:
4:
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
The following values are for both TBLPTRL and TBLPTRH:
All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000)
except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu)
The PRODL and PRODH registers are not implemented on the PIC17C42.
5:
DS30412C-page 34
1996 Microchip Technology Inc.
PIC17C4X
TABLE 6-3:
SPECIAL FUNCTION REGISTERS (Cont.’d)
Value on
Power-on
Reset
Value on all
other
resets (3)
Address Name
Bank 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10h
11h
12h
13h
14h
15h
16h
17h
TMR1
Timer1
Timer2
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR2
TMR3L
TMR3H
PR1
TMR3 register; low byte
TMR3 register; high byte
Timer1 period register
Timer2 period register
PR2
PR3L/CA1L
Timer3 period register, low byte/capture1 register; low byte
PR3H/CA1H Timer3 period register, high byte/capture1 register; high byte
Bank 3
10h
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
DC1
DC1
DC9
DC9
DC0
DC0
DC8
DC8
—
TM2PW2
DC7
—
—
—
—
—
—
—
—
—
—
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
11h
12h
DC6
DC6
DC5
DC5
DC4
DC4
DC3
DC3
DC2
DC2
13h
DC7
14h
Capture2 low byte
Capture2 high byte
15h
CA2H
16h
TCON1
CA2ED1 CA2ED0 CA1ED1
CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Unbanked
18h(5)
19h(5)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PRODL
PRODH
Low Byte of 16-bit Product (8 x 8 Hardware Multiply)
High Byte of 16-bit Product (8 x 8 Hardware Multiply)
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
2:
3:
4:
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
The following values are for both TBLPTRL and TBLPTRH:
All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000)
except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu)
The PRODL and PRODH registers are not implemented on the PIC17C42.
5:
1996 Microchip Technology Inc.
DS30412C-page 35
PIC17C4X
6.2.2.1
ALU STATUS REGISTER (ALUSTA)
It is recommended, therefore, that onlyBCF, BSF, SWAPF
and MOVWF instructions be used to alter the ALUSTA
register because these instructions do not affect any
status bit. To see how other instructions affect the sta-
tus bits, see the “Instruction Set Summary.”
The ALUSTA register contains the status bits of the
Arithmetic and Logic Unit and the mode control bits for
the indirect addressing register.
As with all the other registers, the ALUSTA register can
be the destination for any instruction. If the ALUSTA
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Therefore, the result of an instruction with
the ALUSTA register as destination may be different
than intended.
Note 1: The C and DC bits operate as a borrow
out bit in subtraction. See the SUBLWand
SUBWFinstructions for examples.
Note 2: The overflow bit will be set if the 2’s com-
plement result exceeds +127 or is less
than -128.
Arithmetic and Logic Unit (ALU) is capable of carrying
out arithmetic or logical operations on two operands or
a single operand. All single operand instructions oper-
ate either on the WREG register or a file register. For
two operand instructions, one of the operands is the
WREG register and the other one is either a file register
or an 8-bit immediate constant.
For example, CLRF ALUSTAwill clear the upper four bits
and set the Z bit. This leaves the ALUSTA register as
0000u1uu(where u= unchanged).
FIGURE 6-7: ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)
R/W - 1 R/W - 1 R/W - 1 R/W - 1 R/W - x R/W - x R/W - x R/W - x
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
FS3
FS2
FS1
FS0
OV
Z
DC
C
bit7
bit0
bit 7-6: FS3:FS2: FSR1 Mode Select bits
00 = Post auto-decrement FSR1 value
01 = Post auto-increment FSR1 value
1x = FSR1 value does not change
bit 5-4: FS1:FS0: FSR0 Mode Select bits
00 = Post auto-decrement FSR0 value
01 = Post auto-increment FSR0 value
1x = FSR0 value does not change
bit 3:
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic, (in this arithmetic operation)
0 = No overflow occurred
bit 2:
bit 1:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The results of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWFand ADDLWinstructions.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow the polarity is reversed.
bit 0:
C: carry/borrow bit
For ADDWFand ADDLWinstructions.
1 = A carry-out from the most significant bit of the result occurred
Note that a subtraction is executed by adding the two’s complement of the second operand. For rotate
(RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the source register.
0 = No carry-out from the most significant bit of the result
Note: For borrow the polarity is reversed.
DS30412C-page 36
1996 Microchip Technology Inc.
PIC17C4X
6.2.2.2
CPU STATUS REGISTER (CPUSTA)
The CPUSTA register contains the status and control
bits for the CPU. This register is used to globally
enable/disable interrupts. If only a specific interrupt is
desired to be enabled/disabled, please refer to the
INTerrupt STAtus (INTSTA) register and the Peripheral
Interrupt Enable (PIE) register. This register also indi-
cates if the stack is available and contains the
Power-down (PD) and Time-out (TO) bits. The TO, PD,
and STKAV bits are not writable.These bits are set and
cleared according to device logic. Therefore, the result
of an instruction with the CPUSTA register as destina-
tion may be different than intended.
FIGURE 6-8: CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U - 0
—
U - 0
—
R - 1
STKAV GLINTD
R/W - 1
R - 1
TO
R - 1
PD
U - 0
—
U - 0
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5:
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh→ 0h (stack overflow).
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a
stack overflow, only a device reset will set this bit)
bit 4:
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
bit 3:
bit 2:
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDTinstruction
0 = A Watchdog Timer time-out occurred
PD: Power-down Status bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
bit 1-0: Unimplemented: Read as '0'
1996 Microchip Technology Inc.
DS30412C-page 37
PIC17C4X
6.2.2.3
TMR0 STATUS/CONTROL REGISTER
(T0STA)
This register contains various control bits. Bit7
(INTEDG) is used to control the edge upon which a sig-
nal on the RA0/INT pin will set the RB0/INT interrupt
flag. The other bits configure the Timer0 prescaler and
clock source. (Figure 11-1).
FIGURE 6-9: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
U - 0
—
R = Readable bit
W = Writable bit
U = Unimplemented,
reads as ‘0’
INTEDG
T0SE
T0CS
PS3
PS2
PS1
PS0
bit7
bit0
-n = Value at POR reset
bit 7:
bit 6:
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
When T0CS = 1
Don’t care
bit 5:
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for Timer0.
1 = Internal instruction clock cycle (TCY)
0 = T0CKI pin
bit 4-1: PS3:PS0: Timer0 Prescale Selection bits
These bits select the prescale value for Timer0.
PS3:PS0
Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
bit 0:
Unimplemented: Read as '0'
DS30412C-page 38
1996 Microchip Technology Inc.
PIC17C4X
6.3
Stack Operation
6.4
Indirect Addressing
The PIC17C4X devices have a 16 x 16-bit wide hard-
ware stack (Figure 6-1). The stack is not part of either
the program or data memory space, and the stack
pointer is neither readable nor writable. The PC is
“PUSHed” onto the stack when a CALL instruction is
executed or an interrupt is acknowledged. The stack is
“POPed” in the event of a RETURN, RETLW, or a RETFIE
instruction execution. PCLATH is not affected by a
“PUSH” or a “POP” operation.
Indirect addressing is a mode of addressing data
memory where the data memory address in the
instruction is not fixed. That is, the register that is to be
read or written can be modified by the program. This
can be useful for data tables in the data memory.
Figure 6-10 shows the operation of indirect address-
ing. This shows the moving of the value to the data
memory address specified by the value of the FSR
register.
The stack operates as a circular buffer, with the stack
pointer initialized to '0' after all resets. There is a stack
available bit (STKAV) to allow software to ensure that
the stack has not overflowed.The STKAV bit is set after
a device reset. When the stack pointer equals Fh,
STKAV is cleared. When the stack pointer rolls over
from Fh to 0h, the STKAV bit will be held clear until a
device reset.
Example 6-1 shows the use of indirect addressing to
clear RAM in a minimum number of instructions. A
similar concept could be used to move a defined num-
ber of bytes (block) of data to the USART transmit reg-
ister (TXREG). The starting address of the block of
data to be transmitted could easily be modified by the
program.
FIGURE 6-10: INDIRECT ADDRESSING
Note 1: There is not a status bit for stack under-
flow. The STKAV bit can be used to detect
the underflow which results in the stack
pointer being at the top of stack.
RAM
Instruction
Executed
Note 2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
tions, or the vectoring to an interrupt vec-
tor.
Opcode
Address
File = INDFx
Instruction
Fetched
Note 3: After a reset, if a “POP” operation occurs
before a “PUSH” operation, the STKAV bit
will be cleared. This will appear as if the
stack is full (underflow has occurred). If a
“PUSH” operation occurs next (before
another “POP”), the STKAV bit will be
locked clear. Only a device reset will
cause this bit to set.
FSR
Opcode
File
After the device is “PUSHed” sixteen times (without a
“POP”), the seventeenth push overwrites the value
from the first push. The eighteenth push overwrites the
second push (and so on).
1996 Microchip Technology Inc.
DS30412C-page 39
PIC17C4X
6.4.1
INDIRECT ADDRESSING REGISTERS
A simple program to clear RAM from 20h - FFh is
shown in Example 6-1.
The PIC17C4X has four registers for indirect address-
ing. These registers are:
EXAMPLE 6-1: INDIRECT ADDRESSING
• INDF0 and FSR0
• INDF1 and FSR1
MOVLW
MOVWF
BCF
BSF
BCF
0x20
FSR0
;
; FSR0 = 20h
ALUSTA, FS1 ; Increment FSR
ALUSTA, FS0 ; after access
ALUSTA, C
END_RAM + 1
INDF0
Registers INDF0 and INDF1 are not physically imple-
mented. Reading or writing to these registers activates
indirect addressing, with the value in the correspond-
ing FSR register being the address of the data. The
FSR is an 8-bit register and allows addressing any-
where in the 256-byte data memory address range.
For banked memory, the bank of memory accessed is
specified by the value in the BSR.
; C = 0
;
MOVLW
LP CLRF
CPFSEQ
GOTO
:
; Addr(FSR) = 0
; FSR0 = END_RAM+1?
; NO, clear next
; YES, All RAM is
; cleared
FSR0
LP
:
If file INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if
INDF0 (or INDF1) is written to indirectly, the operation
will be equivalent to a NOP, and the status bits are not
affected.
6.5
Table Pointer (TBLPTRL and
TBLPTRH)
File registers TBLPTRL and TBLPTRH form a 16-bit
pointer to address the 64K program memory space.
The table pointer is used by instructions TABLWTand
TABLRD.
6.4.2
INDIRECT ADDRESSING OPERATION
The TABLRDand the TABLWTinstructions allow trans-
fer of data between program and data space. The table
pointer serves as the 16-bit address of the data word
within the program memory. For a more complete
description of these registers and the operation of Table
Reads and Table Writes, see Section 7.0.
The indirect addressing capability has been enhanced
over that of the PIC16CXX family. There are two con-
trol bits associated with each FSR register. These two
bits configure the FSR register to:
• Auto-decrement the value (address) in the FSR
after an indirect access
• Auto-increment the value (address) in the FSR
after an indirect access
6.6
Table Latch (TBLATH,TBLATL)
• No change to the value (address) in the FSR after
an indirect access
The table latch (TBLAT) is a 16-bit register, with
TBLATH and TBLATL referring to the high and low
bytes of the register. It is not mapped into data or pro-
gram memory. The table latch is used as a temporary
holding latch during data transfer between program and
data memory (see descriptions of instructionsTABLRD,
TABLWT, TLRD and TLWT). For a more complete
description of these registers and the operation of Table
Reads and Table Writes, see Section 7.0.
These control bits are located in the ALUSTA register.
The FSR1 register is controlled by the FS3:FS2 bits
and FSR0 is controlled by the FS1:FS0 bits.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
ALUSTA register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
If the FSR register contains a value of 0h, an indirect
read will read 0h (Zero bit is set) while an indirect write
will be equivalent to a NOP (status bits are not
affected).
Indirect addressing allows single cycle data transfers
within the entire data space. This is possible with the
use of the MOVPFand MOVFPinstructions, where either
'p' or 'f' is specified as INDF0 (or INDF1).
If the source or destination of the indirect address is in
banked memory, the location accessed will be deter-
mined by the value in the BSR.
DS30412C-page 40
1996 Microchip Technology Inc.
PIC17C4X
Using Figure 6-11, the operations of the PC and
PCLATH for different instructions are as follows:
6.7
Program Counter Module
The Program Counter (PC) is a 16-bit register. PCL, the
low byte of the PC, is mapped in the data memory. PCL
is readable and writable just as is any other register.
PCH is the high byte of the PC and is not directly
addressable. Since PCH is not mapped in data or pro-
gram memory, an 8-bit register PCLATH (PC high latch)
is used as a holding latch for the high byte of the PC.
PCLATH is mapped into data memory. The user can
read or write PCH through PCLATH.
a) LCALLinstructions:
An 8-bit destination address is provided in the
instruction (opcode). PCLATH is unchanged.
PCLATH → PCH
Opcode<7:0> → PCL
b) Read instructions on PCL:
Any instruction that reads PCL.
PCL → data bus → ALU or destination
PCH → PCLATH
The 16-bit wide PC is incremented after each instruc-
tion fetch during Q1 unless:
c) Write instructions on PCL:
Any instruction that writes to PCL.
8-bit data → data bus → PCL
PCLATH → PCH
• Modified by GOTO, CALL, LCALL, RETURN, RETLW,
or RETFIEinstruction
• Modified by an interrupt response
• Due to destination write to PCL by an instruction
d) Read-Modify-Write instructions on PCL:
“Skips” are equivalent to a forced NOP cycle at the
skipped address.
Any instruction that does a read-write-modify
operation on PCL, such as ADDWF PCL.
Figure 6-11 and Figure 6-12 show the operation of the
program counter for various situations.
Read: PCL → data bus → ALU
Write: 8-bit result → data bus → PCL
PCLATH → PCH
FIGURE 6-11: PROGRAM COUNTER
OPERATION
e) RETURNinstruction:
PCH → PCLATH
Stack<MRU> → PC<15:0>
Internal data bus <8>
Using Figure 6-12, the operation of the PC and
PCLATH for GOTOand CALLinstructions is a follows:
8
CALL, GOTOinstructions:
PCLATH
8
A 13-bit destination address is provided in the
instruction (opcode).
8
Opcode<12:0> → PC <12:0>
PC<15:13> → PCLATH<7:5>
Opcode<12:8> → PCLATH <4:0>
PCH
PCL
FIGURE 6-12: PROGRAM COUNTER USING
THE CALL AND GOTO
The read-modify-write only affects the PCL with the
result. PCH is loaded with the value in the PCLATH.
For example, ADDWF PCLwill result in a jump within the
current page. If PC = 03F0h, WREG = 30h and
PCLATH = 03h before instruction, PC = 0320h after the
instruction.To accomplish a true 16-bit computed jump,
the user needs to compute the 16-bit destination
address, write the high byte to PCLATH and then write
the low value to PCL.
INSTRUCTIONS
15
13 12
8 7
Opcode
0
Last write
to PCLATH
5
3
8
4
5
7
0
The following PC related operations do not change
PCLATH:
PCLATH
8
a) LCALL, RETLW, and RETFIEinstructions.
15
0
8 7
b) Interrupt vector is forced onto the PC.
PCL
PCH
c) Read-modify-write instructions on PCL (e.g.BSF
PCL).
1996 Microchip Technology Inc.
DS30412C-page 41
PIC17C4X
For the PIC17C43, PIC17CR43, and PIC17C44
devices, the need for a large general purpose memory
space dictated a general purpose RAM banking
scheme. The upper nibble of the BSR selects the cur-
rently active general purpose RAM bank. To assist this,
a MOVLR bank instruction has been provided in the
instruction set.
6.8
Bank Select Register (BSR)
The BSR is used to switch between banks in the data
memory area (Figure 6-13). In the PIC17C42,
PIC17CR42, and PIC17C42A only the lower nibble is
implemented. While in the PIC17C43, PIC17CR43,
and PIC17C44 devices, the entire byte is implemented.
The lower nibble is used to select the peripheral regis-
ter bank. The upper nibble is used to select the general
purpose memory bank.
If the currently selected bank is not implemented (such
as Bank 13), any read will read all '0's. Any write is com-
pleted to the bit bucket and the ALU status bits will be
set/cleared as appropriate.
All the Special Function Registers (SFRs) are mapped
into the data memory space. In order to accommodate
the large number of registers, a banking scheme has
been used. A segment of the SFRs, from address 10h
to address 17h, is banked.The lower nibble of the bank
select register (BSR) selects the currently active
“peripheral bank.” Effort has been made to group the
peripheral registers of related functionality in one bank.
However, it will still be necessary to switch from bank
to bank in order to address all peripherals related to a
single task. To assist this, a MOVLB bankinstruction is
in the instruction set.
Note: Registers in Bank 15 in the Special Func-
tion Register area, are reserved for
Microchip use. Reading of registers in this
bank may cause random values to be read.
FIGURE 6-13: BSR OPERATION (PIC17C43/R43/44)
BSR
7
4 3
0
(2)
(1)
Address
Range
0
1
2
3
4
15
SFR
Banks
10h
17h
• • •
Bank 0
0
Bank 1
1
Bank 2
2
Bank 3
Bank 4
Bank 15
15
20h
FFh
GPR
Banks
• • •
• • •
Bank 0
Bank 1
Bank 2
Bank 15
Note 1: Only Banks 0 through Bank 3 are implemented. Selection of an unimplemented bank is not recommended.
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
2: Only Banks 0 and Bank 1 are implemented. Selection of an unimplemented bank is not recommended.
DS30412C-page 42
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 7-2: TABLWT INSTRUCTION
OPERATION
7.0
TABLE READS AND TABLE
WRITES
The PIC17C4X has four instructions that allow the pro-
cessor to move data from the data memory space to
the program memory space, and vice versa. Since the
program memory space is 16-bits wide and the data
memory space is 8-bits wide, two operations are
required to move 16-bit values to/from the data mem-
ory.
TABLE POINTER
TBLPTRH
TBLPTRL
TABLATL
TABLE LATCH (16-bit)
TABLATH
The TLWT t,fand TABLWT t,i,finstructions are
used to write data from the data memory space to the
program memory space. The TLRD t,fand TABLRD
t,i,finstructions are used to write data from the pro-
gram memory space to the data memory space.
3
3
TABLWT 1,i,f
TABLWT 0,i,f
DATA
MEMORY
PROGRAM MEMORY
The program memory can be internal or external. For
the program memory access to be external, the device
needs to be operating in extended microcontroller or
microprocessor mode.
f
Figure 7-1 through Figure 7-4 show the operation of
these four instructions.
1
Prog-Mem
FIGURE 7-1: TLWT INSTRUCTION
OPERATION
(TBLPTR)
2
TABLE POINTER
TBLPTRH
TBLPTRL
TABLATL
TABLE LATCH (16-bit)
TABLATH
Note 1: 8-bit value, from register 'f', loaded into
the high or low byte in TABLAT (16-bit).
2: 16-bit TABLAT value written to address
Program Memory (TBLPTR).
TLWT 1,f
TLWT 0,f
PROGRAM MEMORY
DATA
MEMORY
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
f
1
Note 1: 8-bit value, from register 'f', loaded into the
high or low byte in TABLAT (16-bit).
1996 Microchip Technology Inc.
DS30412C-page 43
PIC17C4X
FIGURE 7-3: TLRD INSTRUCTION
OPERATION
FIGURE 7-4: TABLRD INSTRUCTION
OPERATION
TABLE POINTER
TABLE POINTER
TBLPTRH
TBLPTRL
TABLATL
TBLPTRH
TBLPTRL
TABLATL
TABLE LATCH (16-bit)
TABLATH
TABLE LATCH (16-bit)
TABLATH
TLRD 1,f
TLRD 0,f
3
3
TABLRD 1,i,f
TABLRD 0,i,f
DATA
MEMORY
PROGRAM MEMORY
DATA
MEMORY
PROGRAM MEMORY
f
1
f
1
Prog-Mem
(TBLPTR)
2
Note 1: 8-bit value, from TABLAT (16-bit) high or
low byte, loaded into register 'f'.
Note 1: 8-bit value, from TABLAT (16-bit) high or
low byte, loaded into register 'f'.
2: 16-bit value at Program Memory (TBLPTR)
loaded into TABLAT register.
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
DS30412C-page 44
1996 Microchip Technology Inc.
PIC17C4X
7.1.1
TERMINATING LONG WRITES
7.1
Table Writes to Internal Memory
An interrupt source or reset are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the inter-
rupt enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execu-
tion is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specifi-
cation #D114 ). Having only one interrupt enabled to
terminate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write; the interrupt flag, of
the highest priority enabled interrupt, will terminate the
long write and automatically be cleared.
The sequence of events for programming an internal
program memory location should be:
Note 1: If an interrupt is pending, the TABLWT is
aborted (an NOP is executed). The
highest priority pending interrupt, from
the T0CKI, RA0/INT, or TMR0 sources
that is enabled, has its flag cleared.
1. Disable all interrupt sources, except the source
to terminate EPROM program write.
2. Raise MCLR/VPP pin to the programming volt-
age.
Note 2: If the interrupt is not being used for the
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it termi-
nate the long write prematurely.
3. Clear the WDT.
4. Do the table write. The interrupt will terminate
the long write.
5. Verify the memory location (table read).
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
Note: Programming requirements must be met.
See timing specification in electrical spec-
ifications for the desired device. Violating
these specifications (including tempera-
ture) may result in EPROM locations that
are not fully programmed and may lose
their state over time.
If the GLINTD bit is cleared prior to the long write,
when the long write is terminated, the program will
branch to the interrupt vector.
If the GLINTD bit is set prior to the long write, when
the long write is terminated, the program will not vector
to the interrupt address.
TABLE 7-1:
INTERRUPT - TABLE WRITE INTERACTION
Interrupt
Source
Enable
Bit
Flag
Bit
GLINTD
Action
RA0/INT, TMR0,
T0CKI
0
1
1
Terminate long table write (to internal program
memory), branch to interrupt vector (branch clears
flag bit).
0
1
1
1
0
1
0
x
1
None
None
Terminate table write, do not branch to interrupt
vector (flag is automatically cleared).
Peripheral
0
0
1
1
1
1
0
1
1
0
x
1
Terminate table write, branch to interrupt vector.
None
None
Terminate table write, do not branch to interrupt
vector (flag is set).
1996 Microchip Technology Inc.
DS30412C-page 45
PIC17C4X
7.2.2
TABLE WRITE CODE
7.2
Table Writes to External Memory
The “i” operand of the TABLWTinstruction can specify
that the value in the 16-bit TBLPTR register is auto-
matically incremented for the next write. In
Example 7-1, the TBLPTR register is not automatically
incremented.
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
EXAMPLE 7-1: TABLE WRITE
Note: If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or T0CKI
interrupt flag is automatically cleared or
the pending peripheral interrupt is
acknowledged.
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
; Clear WDT
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
HIGH (DATA)
1, WREG
;
;
;
address
; Load HI byte
in TABLATCH
; Load LO byte
;
MOVLW
LOW (DATA)
TABLWT 0,0,WREG
;
;
;
;
in TABLATCH
and write to
program memory
(Ext. SRAM)
FIGURE 7-5: TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
PC+1
TBL
Data out
PC+2
Instruction
fetched
TABLWT
INST (PC+1)
INST (PC+2)
INST (PC+1)
Instruction
executed
INST (PC-1)
TABLWT cycle1
TABLWT cycle2
Data write cycle
ALE
OE
'1'
WR
Note: If external write GLINTD = '1', Enable bit = '1', '1' → Flag bit, Do table write. The highest pending interrupt is cleared.
DS30412C-page 46
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 7-6: CONSECUTIVE TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TBL1
Data out 1
Data out 2
PC
PC+2
PC+3
AD15:AD0
PC+1
TBL2
Instruction
fetched
TABLWT1
TABLWT2
INST (PC+2)
INST (PC+3)
INST (PC+2)
Instruction
executed
TABLWT1 cycle1
TABLWT2 cycle2
Data write cycle
INST (PC-1)
TABLWT1 cycle2 TABLWT2 cycle1
Data write cycle
ALE
OE
WR
1996 Microchip Technology Inc.
DS30412C-page 47
PIC17C4X
7.3
Table Reads
EXAMPLE 7-2: TABLE READ
MOVLW
MOVWF
MOVLW
MOVWF
TABLRD 0,0,DUMMY
TLRD 1, INDF0
TABLRD 0,1,INDF0
HIGH (TBL_ADDR) ; Load the Table
The table read allows the program memory to be read.
This allows constant data to be stored in the program
memory space, and retrieved into data memory when
needed. Example 7-2 reads the 16-bit value at pro-
gram memory address TBLPTR. After the dummy byte
has been read from the TABLATH, the TABLATH is
loaded with the 16-bit data from program memory
address TBLPTR + 1. The first read loads the data into
the latch, and can be considered a dummy read
(unknown data loaded into 'f'). INDF0 should be con-
figured for either auto-increment or auto-decrement.
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
;
;
;
address
; Dummy read,
Updates TABLATCH
; Read HI byte
of TABLATCH
; Read LO byte
;
;
;
;
of TABLATCH and
Update TABLATCH
FIGURE 7-7: TABLRD TIMING
Q4
Q4
Q4
Q1 Q2
Q3
Q4
Q1 Q2
Q1 Q2
Q1 Q2
Q3
Q3
Q3
AD15:AD0
PC
PC+1
TBL
Data in
PC+2
Instruction
fetched
INST (PC+2)
TABLRD
INST (PC+1)
Instruction
executed
INST (PC-1)
TABLRD cycle2
Data read cycle
INST (PC+1)
TABLRD cycle1
ALE
OE
'1'
WR
FIGURE 7-8: TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Data in 1
PC
TBL1
PC+2
TBL2 Data in 2
AD15:AD0
PC+1
PC+3
Instruction
fetched
TABLRD1
INST (PC+2)
INST (PC+3)
INST (PC+2)
TABLRD2
Instruction
executed
INST (PC-1) TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1
Data read cycle
TABLRD2 cycle2
Data read cycle
ALE
OE
'1'
WR
DS30412C-page 48
1996 Microchip Technology Inc.
PIC17C4X
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
8.0
HARDWARE MULTIPLIER
All PIC17C4X devices except the PIC17C42, have an
8 x 8 hardware multiplier included in the ALU of the
device. By making the multiply a hardware operation, it
completes in a single instruction cycle. This is an
unsigned multiply that gives a 16-bit result. The result
is stored into the 16-bit PRODuct register
(PRODH:PRODL). The multiplier does not affect any
flags in the ALUSTA register.
EXAMPLE 8-1: 8 x 8 MULTIPLY ROUTINE
MOVFP
MULWF
ARG1, WREG
ARG2
; ARG1 * ARG2 ->
PRODH:PRODL
;
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
MOVFP
MULWF
ARG1, WREG
ARG2
; ARG1 * ARG2 ->
PRODH:PRODL
;
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
BTFSC
SUBWF
ARG2, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
MOVFP
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH, F
Table 8-1 shows a performance comparison between
the PIC17C42 and all other PIC17CXX devices, which
have the single cycle hardware multiply.
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
TABLE 8-1:
PERFORMANCE COMPARISON
Time
@ 25 MHz @ 33 MHz
Program Memory
Routine
Device
Cycles (Max)
(Words)
8 x 8 unsigned
PIC17C42
13
1
69
1
11.04 µs
160 ns
—
N/A
121 ns
N/A
All other PIC17CXX devices
PIC17C42
8 x 8 signed
—
6
—
All other PIC17CXX devices
6
960 ns
38.72 µs
3.84 µs
40.64 µs
5.76 µs
727 ns
N/A
16 x 16 unsigned PIC17C42
All other PIC17CXX devices
PIC17C42
All other PIC17CXX devices
21
24
52
36
242
24
254
36
2.91 µs
N/A
16 x 16 signed
4.36 µs
1996 Microchip Technology Inc.
DS30412C-page 49
PIC17C4X
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EXAMPLE 8-3: 16 x 16 MULTIPLY ROUTINE
MOVFP
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
PRODH:PRODL
;
MOVPF
MOVPF
PRODH, RES1 ;
PRODL, RES0 ;
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
;
;
MOVFP
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
PRODH:PRODL
;
RES3:RES0
=
=
ARG1H:ARG1L * ARG2H:ARG2L
MOVPF
MOVPF
PRODH, RES3 ;
PRODL, RES2 ;
16
(ARG1H * ARG2H * 2 ) +
8
(ARG1H * ARG2L * 2 )
+
+
MOVFP
MULWF
ARG1L, WREG
8
(ARG1L * ARG2H * 2 )
ARG2H
; ARG1L * ARG2H ->
;
PRODH:PRODL
(ARG1L * ARG2L)
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
; Add cross
PRODH, WREG ;
RES1, F
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
;
MOVFP
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
DS30412C-page 50
1996 Microchip Technology Inc.
PIC17C4X
Example 8-4 shows the sequence to do an 16 x 16
signed multiply. Equation 8-2 shows the algorithm that
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY
ROUTINE
MOVFP
ARG1L, WREG
MULWF
ARG2L
; ARG1L * ARG2L ->
PRODH:PRODL
;
MOVPF
MOVPF
PRODH, RES1 ;
PRODL, RES0 ;
;
;
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
MOVFP
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
PRODH:PRODL
;
MOVPF
MOVPF
PRODH, RES3 ;
PRODL, RES2 ;
RES3:RES0
= ARG1H:ARG1L * ARG2H:ARG2L
MOVFP
MULWF
ARG1L, WREG
ARG2H
16
= (ARG1H * ARG2H * 2 )
+
+
+
+
; ARG1L * ARG2H ->
8
;
PRODH:PRODL
(ARG1H * ARG2L * 2 )
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
PRODH, WREG ;
RES2, F
WREG, F
RES3, F
8
(ARG1L * ARG2H * 2 )
; Add cross
products
(ARG1L * ARG2L)
;
;
;
16
(-1 * ARG2H<7> * ARG1H:ARG1L * 2 ) +
16
ADDWFC
(-1 * ARG1H<7> * ARG2H:ARG2L * 2 )
;
MOVFP
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
;
;
BTFSS
GOTO
MOVFP
SUBWF
MOVFP
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG ;
RES2
ARG1H, WREG ;
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
SIGN_ARG1
BTFSS
GOTO
ARG1H, 7
CONT_CODE
; ARG1H:ARG1L neg?
; no, done
MOVFP
SUBWF
MOVFP
SUBWFB
;
ARG2L, WREG ;
RES2
ARG2H, WREG ;
RES3
;
CONT_CODE
:
1996 Microchip Technology Inc.
DS30412C-page 51
PIC17C4X
NOTES:
DS30412C-page 52
1996 Microchip Technology Inc.
PIC17C4X
9.1
PORTA Register
9.0
I/O PORTS
The PIC17C4X devices have five I/O ports, PORTA
through PORTE. PORTB through PORTE have a corre-
sponding Data Direction Register (DDR), which is used
to configure the port pins as inputs or outputs. These
five ports are made up of 33 I/O pins. Some of these
ports pins are multiplexed with alternate functions.
PORTA is a 6-bit wide latch. PORTA does not have a
corresponding Data Direction Register (DDR).
Reading PORTA reads the status of the pins.
The RA1 pin is multiplexed with TMR0 clock input, and
RA4 and RA5 are multiplexed with the USART func-
tions. The control of RA4 and RA5 as outputs is auto-
matically configured by the USART module.
PORTC, PORTD, and PORTE are multiplexed with the
system bus. These pins are configured as the system
bus when the device’s configuration bits are selected to
Microprocessor or Extended Microcontroller modes. In
the two other microcontroller modes, these pins are
general purpose I/O.
9.1.1
USING RA2, RA3 AS OUTPUTS
The RA2 and RA3 pins are open drain outputs. To use
the RA2 or the RA3 pin(s) as output(s), simply write to
the PORTA register the desired value. A '0' will cause
the pin to drive low, while a '1' will cause the pin to float
(hi-impedance). An external pull-up resistor should be
used to pull the pin high.Writes to PORTA will not affect
the other pins.
PORTA and PORTB are multiplexed with the peripheral
features of the device. These peripheral features are:
• Timer modules
• Capture module
• PWM module
Note: When using the RA2 or RA3 pin(s) as out-
put(s), read-modify-write instructions (such
as BCF, BSF, BTG) on PORTA are not rec-
ommended.
• USART/SCI module
• External Interrupt pin
When some of these peripheral modules are turned on,
the port pin will automatically configure to the alternate
function. The modules that do this are:
Such operations read the port pins, do the
desired operation, and then write this value
to the data latch. This may inadvertently
cause the RA2 or RA3 pins to switch from
input to output (or vice-versa).
It is recommended to use a shadow regis-
ter for PORTA. Do the bit operations on this
shadow register and then move it to
PORTA.
• PWM module
• USART/SCI module
When a pin is automatically configured as an output by
a peripheral module, the pins data direction (DDR) bit
is unknown. After disabling the peripheral module, the
user should re-initialize the DDR bit to the desired con-
figuration.
FIGURE 9-1: RA0 AND RA1 BLOCK
DIAGRAM
The other peripheral modules (which require an input)
must have their data direction bit configured appropri-
ately.
Note: A pin that is a peripheral input, can be con-
figured as an output (DDRx<y> is cleared).
The peripheral events will be determined
by the action output on the port pin.
DATA BUS
RD_PORTA
(Q2)
Note: I/O pins have protection diodes to VDD and VSS.
1996 Microchip Technology Inc.
DS30412C-page 53
PIC17C4X
FIGURE 9-2: RA2 AND RA3 BLOCK
DIAGRAM
FIGURE 9-3: RA4 AND RA5 BLOCK
DIAGRAM
Data Bus
Serial port input signal
Data Bus
Q
Q
D
RD_PORTA
(Q2)
RD_PORTA
(Q2)
CK
Serial port output signals
WR_PORTA
(Q4)
OE = SPEN,SYNC,TXEN, CREN, SREN for RA4
OE = SPEN (SYNC+SYNC,CSRC) for RA5
Note: I/O pins have protection diodes to VSS.
Note: I/O pins have protection diodes to VDD and VSS.
TABLE 9-1:
PORTA FUNCTIONS
Bit0 Buffer Type
Name
Function
RA0/INT
RA1/T0CKI
RA2
bit0
bit1
bit2
bit3
bit4
bit5
bit7
ST
ST
ST
ST
ST
ST
—
Input or external interrupt input.
Input or clock input to the TMR0 timer/counter, and/or an external interrupt input.
Input/Output. Output is open drain type.
RA3
Input/Output. Output is open drain type.
RA4/RX/DT
RA5/TX/CK
RBPU
Input or USART Asynchronous Receive or USART Synchronous Data.
Input or USART Asynchronous Transmit or USART Synchronous Clock.
Control bit for PORTB weak pull-ups.
Legend: ST = Schmitt Trigger input.
TABLE 9-2:
REGISTERS/BITS ASSOCIATED WITH PORTA
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10h, Bank 0
PORTA
RBPU
INTEDG
SPEN
—
RA5
T0CS
SREN
TXEN
RA4
PS3
RA3
PS2
—
RA2
PS1
FERR
—
RA1/T0CKI RA0/INT
0-xx xxxx
0000 000-
0000 -00x
0000 --1x
0-uu uuuu
0000 000-
0000 -00u
0000 --1u
05h, Unbanked T0STA
T0SE
RC9
TX9
PS0
—
13h, Bank 0
15h, Bank 0
RCSTA
TXSTA
CREN
SYNC
OERR
TRMT
RC9D
TX9D
CSRC
—
Legend: x= unknown, u= unchanged, -= unimplemented reads as '0'. Shaded cells are not used by PORTA.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30412C-page 54
1996 Microchip Technology Inc.
PIC17C4X
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt by:
9.2
PORTB and DDRB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRB. A '1' in DDRB
configures the corresponding port pin as an input. A '0'
in the DDRB register configures the corresponding port
pin as an output. Reading PORTB reads the status of
the pins, whereas writing to it will write to the port latch.
a) Read-Write PORTB (such as; MOVPF PORTB,
PORTB). This will end mismatch condition.
b) Then, clear the RBIF bit.
A mismatch condition will continue to set the RBIF bit.
Reading then writing PORTB will end the mismatch
condition, and allow the RBIF bit to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (PORTA<7>) bit. The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are enabled on
any reset.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on this port, allows easy
interface to a key pad and make it possible for wake-up
on key-depression. For an example, refer to AN552 in
the Embedded Control Handbook.
PORTB also has an interrupt on change feature. Only
pins configured as inputs can cause this interrupt to
occur (i.e. any RB7:RB0 pin configured as an output is
excluded from the interrupt on change comparison).
The input pins (of RB7:RB0) are compared with the
value in the PORTB data latch.The “mismatch” outputs
of RB7:RB0 are OR’ed together to generate the
PORTB Interrupt Flag RBIF (PIR<7>).
The interrupt on change feature is recommended for
wake-up on operations where PORTB is only used for
the interrupt on change feature and key depression
operation.
FIGURE 9-4: BLOCK DIAGRAM OF RB<7:4> AND RB<1:0> PORT PINS
Peripheral Data in
RBPU
(PORTA<7>)
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
WR_PORTB (Q4)
CK
D
Port
Q
Data
CK
Note: I/O pins have protection diodes to VDD and VSS.
1996 Microchip Technology Inc.
DS30412C-page 55
PIC17C4X
FIGURE 9-5: BLOCK DIAGRAM OF RB3 AND RB2 PORT PINS
Peripheral Data in
(PORTA<7>)
RBPU
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
WR_PORTB (Q4)
CK
R
D
Port
Q
Data
CK
PWM_output
PWM_select
Note: I/O pins have protection diodes to VDD and Vss.
DS30412C-page 56
1996 Microchip Technology Inc.
PIC17C4X
Example 9-1 shows the instruction sequence to initial-
ize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized.
EXAMPLE 9-1: INITIALIZING PORTB
MOVLB 0
; Select Bank 0
; Initialize PORTB by clearing
output data latches
; Value used to initialize
CLRF PORTB
;
MOVLW 0xCF
MOVWF DDRB
;
;
;
;
data direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
TABLE 9-3:
PORTB FUNCTIONS
Name
Bit
Buffer Type
Function
RB0/CAP1
bit0
ST
Input/Output or the RB0/CAP1 input pin. Software programmable weak pull-
up and interrupt on change features.
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
Input/Output or the RB1/CAP2 input pin. Software programmable weak pull-
up and interrupt on change features.
Input/Output or the RB2/PWM1 output pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the RB3/PWM2 output pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the external clock input to Timer1 and Timer2. Software pro-
grammable weak pull-up and interrupt on change features.
Input/Output or the external clock input to Timer3. Software programmable
weak pull-up and interrupt on change features.
Input/Output pin. Software programmable weak pull-up and interrupt on
change features.
RB7
Input/Output pin. Software programmable weak pull-up and interrupt on
change features.
Legend: ST = Schmitt Trigger input.
TABLE 9-4:
REGISTERS/BITS ASSOCIATED WITH PORTB
Value on all
Value on
other
resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
Reset
12h, Bank 0
11h, Bank 0
PORTB
DDRB
PORTB data latch
Data direction register for PORTB
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
10h, Bank 0
PORTA
RBPU
—
RA5
RA4
RA3
RA2
RA1/T0CKI RA0/INT 0-xx xxxx 0-uu uuuu
06h, Unbanked CPUSTA
07h, Unbanked INTSTA
—
—
STKAV
T0IF
GLINTD
INTF
TO
PD
—
—
--11 11-- --11 qq--
0000 0000 0000 0000
0000 0010 0000 0010
0000 0000 0000 0000
PEIF
RBIF
RBIE
T0CKIF
TMR3IF
TMR3IE
PEIE
CA2IF
CA2IE
T16
T0CKIE
CA1IF
CA1IE
T0IE
TXIF
TXIE
INTE
RCIF
RCIE
16h, Bank 1
17h, Bank 1
16h, Bank 3
PIR
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CA1ED0
PIE
TCON1
CA2ED1 CA2ED0 CA1ED1
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Legend: x= unknown, u= unchanged, - = unimplemented read as '0', q = Value depends on condition.
Shaded cells are not used by PORTB.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 57
PIC17C4X
Example 9-2 shows the instruction sequence to initial-
ize PORTC. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized.
9.3
PORTC and DDRC Registers
PORTC is an 8-bit bi-directional port. The correspond-
ing data direction register is DDRC. A '1' in DDRC con-
figures the corresponding port pin as an input. A '0' in
the DDRC register configures the corresponding port
pin as an output. Reading PORTC reads the status of
the pins, whereas writing to it will write to the port latch.
PORTC is multiplexed with the system bus. When
operating as the system bus, PORTC is the low order
byte of the address/data bus (AD7:AD0). The timing for
the system bus is shown in the Electrical Characteris-
tics section.
EXAMPLE 9-2: INITIALIZING PORTC
MOVLB
CLRF
1
;
;
;
;
;
;
;
;
;
;
Select Bank 1
PORTC
Initialize PORTC data
latches before setting
the data direction
register
Value used to initialize
data direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
MOVLW 0xCF
MOVWF DDRC
Note: This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a gen-
eral purpose I/O.
FIGURE 9-6: BLOCK DIAGRAM OF RC<7:0> PORT PINS
to D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTC
WR_PORTC
Port
D
D
0
1
Q
Data
CK
RD_DDRC
WR_DDRC
Q
R
CK
S
EX_EN
DATA/ADDR_OUT
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30412C-page 58
1996 Microchip Technology Inc.
PIC17C4X
TABLE 9-5:
Name
PORTC FUNCTIONS
Bit
Buffer Type
Function
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Legend: TTL = TTL input.
TABLE 9-6:
REGISTERS/BITS ASSOCIATED WITH PORTC
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
11h, Bank 1 PORTC
10h, Bank 1 DDRC
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
Data direction register for PORTC
Legend: x= unknown, u= unchanged.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 59
PIC17C4X
Example 9-3 shows the instruction sequence to initial-
ize PORTD. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized.
9.4
PORTD and DDRD Registers
PORTD is an 8-bit bi-directional port. The correspond-
ing data direction register is DDRD. A '1' in DDRD con-
figures the corresponding port pin as an input. A '0' in
the DDRC register configures the corresponding port
pin as an output. Reading PORTD reads the status of
the pins, whereas writing to it will write to the port latch.
PORTD is multiplexed with the system bus. When
operating as the system bus, PORTD is the high order
byte of the address/data bus (AD15:AD8). The timing
for the system bus is shown in the Electrical Character-
istics section.
EXAMPLE 9-3: INITIALIZING PORTD
MOVLB
CLRF
1
;
;
;
;
;
;
;
;
;
;
Select Bank 1
PORTD
Initialize PORTD data
latches before setting
the data direction
register
Value used to initialize
data direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
MOVLW 0xCF
MOVWF DDRD
Note: This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a gen-
eral purpose I/O.
FIGURE 9-7: PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
to D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTD
WR_PORTD
Port
D
D
0
1
Q
Data
CK
RD_DDRD
WR_DDRD
Q
R
CK
S
EX_EN
DATA/ADDR_OUT
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30412C-page 60
1996 Microchip Technology Inc.
PIC17C4X
TABLE 9-7:
Name
PORTD FUNCTIONS
Bit
Buffer Type
Function
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Legend: TTL = TTL input.
TABLE 9-8:
REGISTERS/BITS ASSOCIATED WITH PORTD
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
13h, Bank 1 PORTD
12h, Bank 1 DDRD
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
Data direction register for PORTD
Legend: x= unknown, u= unchanged.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 61
PIC17C4X
9.4.1
PORTE AND DDRE REGISTER
Example 9-4 shows the instruction sequence to initial-
ize PORTE. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized.
PORTE is a 3-bit bi-directional port.The corresponding
data direction register is DDRE. A '1' in DDRE config-
ures the corresponding port pin as an input. A '0' in the
DDRE register configures the corresponding port pin
as an output. Reading PORTE reads the status of the
pins, whereas writing to it will write to the port latch.
PORTE is multiplexed with the system bus. When
operating as the system bus, PORTE contains the con-
trol signals for the address/data bus (AD15:AD0).
These control signals are Address Latch Enable (ALE),
Output Enable (OE), and Write (WR). The control sig-
nals OE and WR are active low signals. The timing for
the system bus is shown in the Electrical Characteris-
tics section.
EXAMPLE 9-4: INITIALIZING PORTE
MOVLB
CLRF
1
;
;
;
;
;
;
;
;
;
;
;
Select Bank 1
PORTE
Initialize PORTE data
latches before setting
the data direction
register
Value used to initialize
data direction
Set RE<1:0> as inputs
RE<2> as outputs
RE<7:3> are always
read as '0'
MOVLW 0x03
MOVWF DDRE
Note: This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a gen-
eral purpose I/O.
FIGURE 9-8: PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
Data Bus
TTL
Input
Buffer
RD_PORTE
WR_PORTE
Port
D
D
0
1
Q
Data
CK
RD_DDRE
WR_DDRE
Q
R
CK
S
EX_EN
CNTL
SYS BUS
Control
DRV_SYS
Note: I/O pins have protection diodes to VDD and Vss.
DS30412C-page 62
1996 Microchip Technology Inc.
PIC17C4X
TABLE 9-9:
Name
PORTE FUNCTIONS
Bit
Buffer Type
Function
RE0/ALE
RE1/OE
RE2/WR
bit0
bit1
bit2
TTL
TTL
TTL
Input/Output or system bus Address Latch Enable (ALE) control pin.
Input/Output or system bus Output Enable (OE) control pin.
Input/Output or system bus Write (WR) control pin.
Legend: TTL = TTL input.
TABLE 9-10: REGISTERS/BITS ASSOCIATED WITH PORTE
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15h, Bank 1 PORTE
14h, Bank 1 DDRE
—
—
—
—
—
RE2/WR RE1/OE RE0/ALE ---- -xxx
---- -uuu
---- -111
Data direction register for PORTE
---- -111
Legend: x= unknown, u= unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 63
PIC17C4X
9.5
I/O Programming Considerations
EXAMPLE 9-5: READ MODIFY WRITE
INSTRUCTIONS ON AN
I/O PORT
9.5.1
BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. For example, the
BCF and BSF instructions read the register into the
CPU, execute the bit operation, and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g. bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this particu-
lar pin, overwriting the previous content. As long as the
pin stays in the input mode, no problem occurs. How-
ever, if bit0 is switched into output mode later on, the
content of the data latch may now be unknown.
; Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
; PORTB<7:6> have pull-ups and are
; not connected to other circuitry
;
;
;
;
PORT latch PORT pins
---------- ---------
BCF
BCF
PORTB, 7
PORTB, 6
01pp pppp
10pp pppp
11pp pppp
11pp pppp
;
;
BCF
BCF
DDRB, 7
DDRB, 6
10pp pppp
10pp pppp
11pp pppp
10pp pppp
; Note that the user may have expected the
; pin values to be 00pp pppp. The 2nd BCF
; caused RB7 to be latched as the pin value
; (High).
Note: A pin actively outputting a Low or High
should not be driven from external devices
in order to change the level on this pin (i.e.
“wired-or”, “wired-and”). The resulting high
output currents may damage the device.
Reading a port reads the values of the port pins.Writing
to the port register writes the value to the port latch.
When using read-modify-write instructions (BCF, BSF,
BTG, etc.) on a port, the value of the port pins is read,
the desired operation is performed with this value, and
the value is then written to the port latch.
9.5.2
SUCCESSIVE OPERATIONS ON I/O PORTS
Example 9-5 shows the effect of two sequential
read-modify-write instructions on an I/O port.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 9-
9).Therefore, care must be exercised if a write followed
by a read operation is carried out on the same I/O port.
The sequence of instructions should be such to allow
the pin voltage to stabilize (load dependent) before
executing the instruction that reads the values on that
I/O port. Otherwise, the previous state of that pin may
be read into the CPU rather than the “new” state. When
in doubt, it is better to separate these instructions with
a NOPor another instruction not accessing this I/O port.
FIGURE 9-9: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q1 Q2
Q4
Q3
Q3
Q3
Q3
Q1 Q2
Q1 Q2
Q1 Q2
Note:
PC + 3
NOP
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle.
TPD = propagation delay
Therefore, at higher clock
frequencies, a write followed by a
read may be problematic.
PC
PC + 1
PC + 2
NOP
Instruction
fetched
MOVWF PORTB MOVF PORTB,W
write to
PORTB
RB7:RB0
Port pin
sampled here
Instruction
executed
MOVWF PORTB MOVF PORTB,W
NOP
write to
PORTB
DS30412C-page 64
1996 Microchip Technology Inc.
PIC17C4X
10.3
Timer2 Overview
10.0 OVERVIEW OF TIMER
RESOURCES
The PIC17C4X has four timer modules. Each module
can generate an interrupt to indicate that an event has
occurred. These timers are called:
The TMR2 module is an 8-bit timer/counter with an 8-
bit period register (PR2). When the TMR2 value rolls
over from the period match value to 0h, the TMR2IF
flag is set, and an interrupt will be generated when
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also be selected to be the
clock for the TMR1 module.
• Timer0 - 16-bit timer with programmable 8-bit
prescaler
• Timer1 - 8-bit timer
TMR1 can be concatenated to TMR2 to form a 16-bit
timer. The TMR2 register is the MSB and TMR1 is the
LSB. When in the 16-bit timer mode, there is a corre-
sponding 16-bit period register (PR2:PR1). When the
TMR2:TMR1 value rolls over from the period match
value to 0h, the TMR1IF flag is set, and an interrupt
will be generated when enabled.
• Timer2 - 8-bit timer
• Timer3 - 16-bit timer
For enhanced time-base functionality, two input Cap-
tures and two Pulse Width Modulation (PWM) outputs
are possible. The PWMs use the TMR1 and TMR2
resources and the input Captures use the TMR3
resource.
10.4
Timer3 Overview
10.1
Timer0 Overview
The TImer3 module is a 16-bit timer/counter with a 16-
bit period register. When the TMR3H:TMR3L value
rolls over to 0h, the TMR3IF bit is set and an interrupt
will be generated when enabled. In counter mode, the
clock comes from the RB5/TCLK3 pin.
The Timer0 module is a simple 16-bit overflow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock.
The Timer0 module also has a programmable pres-
caler option. The PS3:PS0 bits (T0STA<4:1>) deter-
mine the prescaler value. TMR0 can increment at the
following rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64,
1:128, 1:256.
When operating in the dual capture mode, the period
registers become the second 16-bit capture register.
10.5
Role of the Timer/Counters
When TImer0’s clock source is an external clock, the
Timer0 module can be selected to increment on either
the rising or falling edge.
The timer modules are general purpose, but have ded-
icated resources associated with them. TImer1 and
Timer2 are the time-bases for the two Pulse Width
Modulation (PWM) outputs, while Timer3 is the time-
base for the two input captures.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s fre-
quency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.
10.2
Timer1 Overview
The TImer0 module is an 8-bit timer/counter with an 8-
bit period register (PR1). When the TMR1 value rolls
over from the period match value to 0h, the TMR1IF
flag is set, and an interrupt will be generated when
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also be selected to be the
clock for the Timer2 module.
TMR1 can be concatenated to TMR2 to form a 16-bit
timer. The TMR1 register is the LSB and TMR2 is the
MSB. When in the 16-bit timer mode, there is a corre-
sponding 16-bit period register (PR2:PR1). When the
TMR2:TMR1 value rolls over from the period match
value to 0h, the TMR1IF flag is set, and an interrupt
will be generated when enabled.
1996 Microchip Technology Inc.
DS30412C-page 65
PIC17C4X
NOTES:
DS30412C-page 66
1996 Microchip Technology Inc.
PIC17C4X
11.0 TIMER0
The Timer0 module consists of a 16-bit timer/counter,
TMR0. The high byte is TMR0H and the low byte is
TMR0L. A software programmable 8-bit prescaler
makes an effective 24-bit overflow timer. The clock
source is also software programmable as either the
internal instruction clock or the RA1/T0CKI pin. The
control bits for this module are in register T0STA
(Figure 11-1).
FIGURE 11-1: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
U - 0
—
R = Readable bit
W = Writable bit
U = Unimplemented,
Read as '0'
INTEDG
T0SE
T0CS
PS3
PS2
PS1
PS0
bit7
bit0
-n = Value at POR reset
bit 7:
bit 6:
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment
When T0CS = 0
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
When T0CS = 1
Don’t care
bit 5:
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for TMR0.
1 = Internal instruction clock cycle (TCY)
0 = T0CKI pin
bit 4-1: PS3:PS0: Timer0 Prescale Selection bits
These bits select the prescale value for TMR0.
PS3:PS0
Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
bit 0:
Unimplemented: Read as '0'
1996 Microchip Technology Inc.
DS30412C-page 67
PIC17C4X
11.1
Timer0 Operation
11.2
Using Timer0 with External Clock
When the T0CS (T0STA<5>) bit is set, TMR0 incre-
ments on the internal clock.When T0CS is clear, TMR0
increments on the external clock (RA1/T0CKI pin). The
external clock edge can be configured in software.
When the T0SE (T0STA<6>) bit is set, the timer will
increment on the rising edge of the RA1/T0CKI pin.
When T0SE is clear, the timer will increment on the fall-
ing edge of the RA1/T0CKI pin. The prescaler can be
programmed to introduce a prescale of 1:1 to 1:256.
The timer increments from 0000h to FFFFh and rolls
over to 0000h. On overflow, the TMR0 Interrupt Flag bit
(T0IF) is set. The TMR0 interrupt can be masked by
clearing the corresponding TMR0 Interrupt Enable bit
(T0IE). The TMR0 Interrupt Flag bit (T0IF) is automati-
cally cleared when vectoring to the TMR0 interrupt vec-
tor.
When the external clock input is used for Timer0, it is
synchronized with the internal phase clocks.
Figure 11-3 shows the synchronization of the external
clock. This synchronization is done after the prescaler.
The output of the prescaler (PSOUT) is sampled twice
in every instruction cycle to detect a rising or a falling
edge. The timing requirements for the external clock
are detailed in the electrical specification section for the
desired device.
11.2.1 DELAY FROM EXTERNAL CLOCK EDGE
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time TMR0 is actually
incremented. Figure 11-3 shows that this delay is
between 3TOSC and 7TOSC. Thus, for example, mea-
suring the interval between two edges (e.g. period) will
be accurate within ±4TOSC (±121 ns @ 33 MHz).
FIGURE 11-2: TIMER0 MODULE BLOCK DIAGRAM
Interrupt on overflow
sets T0IF
(INTSTA<5>)
Prescaler
0
(8 stage
Synchronization
TMR0H<8> TMR0L<8>
RA1/T0CKI
async ripple
counter)
Fosc/4
1
PSOUT
T0SE
(T0STA<6>)
4
Q2
Q4
PS3:PS0
(T0STA<4:1>)
T0CS
(T0STA<5>)
FIGURE 11-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler
output
(PSOUT)
(note 3)
(note 2)
Sampled
Prescaler
output
(note 1)
Increment
TMR0
T0
T0 + 1
T0 + 2
TMR0
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
2: ↑ = PSOUT is sampled here.
3: The PSOUT high time is too short and is missed by the sampling circuit.
DS30412C-page 68
1996 Microchip Technology Inc.
PIC17C4X
11.3.2 WRITING A 16-BIT VALUE TO TMR0
11.3
Read/Write Consideration for TMR0
Since writing to either TMR0L or TMR0H will effectively
inhibit increment of that half of the TMR0 in the next
cycle (following write), but not inhibit increment of the
other half, the user must write to TMR0L first and
TMR0H next in two consecutive instructions, as shown
in Example 11-2. The interrupt must be disabled. Any
write to either TMR0L or TMR0H clears the prescaler.
Although TMR0 is a 16-bit timer/counter, only 8-bits at
a time can be read or written during a single instruction
cycle. Care must be taken during any read or write.
11.3.1 READING 16-BIT VALUE
The problem in reading the entire 16-bit value is that
after reading the low (or high) byte, its value may
change from FFh to 00h.
EXAMPLE 11-2: 16-BIT WRITE
Example 11-1 shows a 16-bit read. To ensure a proper
read, interrupts must be disabled during this routine.
BSF
CPUSTA, GLINTD ; Disable interrupt
MOVFP RAM_L, TMR0L
MOVFP RAM_H, TMR0H
BCF
;
;
EXAMPLE 11-1: 16-BIT READ
CPUSTA, GLINTD ; Done, enable interrupt
MOVPF
MOVPF
MOVFP
CPFSLT TMR0L
RETURN
MOVPF
MOVPF
RETURN
TMR0L, TMPLO
TMR0H, TMPHI
TMPLO, WREG
;read low tmr0
;read high tmr0
;tmplo −> wreg
;tmr0l < wreg?
;no then return
;read low tmr0
;read high tmr0
;return
11.4
Prescaler Assignments
Timer0 has an 8-bit prescaler. The prescaler assign-
ment is fully under software control; i.e., it can be
changed “on the fly” during program execution. When
changing the prescaler assignment, clearing the pres-
caler is recommended before changing assignment.
The value of the prescaler is “unknown,” and assigning
a value that is less then the present value makes it dif-
ficult to take this unknown time into account.
TMR0L, TMPLO
TMR0H, TMPHI
FIGURE 11-4: TMR0 TIMING: WRITE HIGH OR LOW BYTE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
PC+1
PC+2
PC+3
PC+4
PC
T0
T0+1
New T0 (NT0)
New T0+1
TMR0L
Fetch
MOVFP W,TMR0L MOVFP TMR0L,W MOVFP TMR0L,W MOVFP TMR0L,W
Instruction
executed
Write to TMR0L
Read TMR0L
(Value = NT0)
Read TMR0L
(Value = NT0)
Read TMR0L
(Value = NT0 +1)
TMR0H
1996 Microchip Technology Inc.
DS30412C-page 69
PIC17C4X
FIGURE 11-5: TMR0 READ/WRITE IN TIMER MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
WR_TRM0L
WR_TMR0H
RD_TMR0L
12
AB
12
13
56
TMR0H
57
58
TMR0L
FE
FF
MOVFP
MOVFP
MOVPF
MOVPF
TMR0L,W
MOVPF
MOVPF
DATAL,TMR0L DATAH,TMR0H
TMR0L,W
TMR0L,W
TMR0L,W
Instruction
fetched
Write TMR0L Write TMR0H Read TMR0L Read TMR0L Read TMR0L Read TMR0L
Previously
Fetched
Instruction
MOVFP
MOVFP
MOVPF
MOVPF
MOVPF
Instruction
executed
DATAL,TMR0L DATAH,TMR0H
TMR0L,W
TMR0L,W
TMR0L,W
Write TMR0L Write TMR0H Read TMR0L Read TMR0L Read TMR0L
In this example, old TMR0 value is 12FEh, new value of AB56h is written.
TABLE 11-1: REGISTERS/BITS ASSOCIATED WITH TIMER0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h, Unbanked
06h, Unbanked
07h, Unbanked
0Bh, Unbanked
0Ch, Unbanked
T0STA
INTEDG
—
T0SE
—
T0CS
STKAV
T0IF
PS3
GLINTD
INTF
PS2
TO
PS1
PD
PS0
—
—
—
0000 000-
--11 11--
0000 0000
xxxx xxxx
xxxx xxxx
0000 000-
--11 qq--
0000 0000
uuuu uuuu
uuuu uuuu
CPUSTA
INTSTA
TMR0L
TMR0H
PEIF
T0CKIF
PEIE
T0CKIE
T0IE
INTE
TMR0 register; low byte
TMR0 register; high byte
Legend:
x= unknown, u= unchanged, -= unimplemented read as a '0', q- value depends on condition, Shaded cells are not used by Timer0.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30412C-page 70
1996 Microchip Technology Inc.
PIC17C4X
Timer3 is a 16-bit timer/counter consisting of the
TMR3H and TMR3L registers.This timer has four other
associated registers.Two registers are used as a 16-bit
12.0 TIMER1, TIMER2,TIMER3,
PWMS AND CAPTURES
The PIC17C4X has a wealth of timers and time-based
functions to ease the implementation of control applica-
tions.These time-base functions include two PWM out-
puts and two Capture inputs.
period register or
a
16-bit Capture1 register
(PR3H/CA1H:PR3L/CA1L).The other two registers are
strictly the Capture2 registers (CA2H:CA2L). Timer3 is
the time-base for the two 16-bit captures.
Timer1 and Timer2 are two 8-bit incrementing timers,
each with a period register (PR1 and PR2 respectively)
and separate overflow interrupt flags. Timer1 and
Timer2 can operate either as timers (increment on
internal Fosc/4 clock) or as counters (increment on fall-
ing edge of external clock on pin RB4/TCLK12). They
are also software configurable to operate as a single
16-bit timer. These timers are also used as the
time-base for the PWM (pulse width modulation) mod-
ule.
TMR3 can be software configured to increment from
the internal system clock or from an external signal on
the RB5/TCLK3 pin.
Figure 12-1 and Figure 12-2 are the control registers
for the operation of Timer1, Timer2, and Timer3, as well
as PWM1, PWM2, Capture1, and Capture2.
FIGURE 12-1: TCON1 REGISTER (ADDRESS: 16h, BANK 3)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
bit7
bit0
bit 7-6: CA2ED1:CA2ED0: Capture2 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 5-4: CA1ED1:CA1ED0: Capture1 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 3:
bit 2:
bit 1:
bit 0:
T16: Timer1:Timer2 Mode Select bit
1 = Timer1 and Timer2 form a 16-bit timer
0 = Timer1 and Timer2 are two 8-bit timers
TMR3CS: Timer3 Clock Source Select bit
1 = TMR3 increments off the falling edge of the RB5/TCLK3 pin
0 = TMR3 increments off the internal clock
TMR2CS: Timer2 Clock Source Select bit
1 = TMR2 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR2 increments off the internal clock
TMR1CS: Timer1 Clock Source Select bit
1 = TMR1 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR1 increments off the internal clock
1996 Microchip Technology Inc.
DS30412C-page 71
PIC17C4X
FIGURE 12-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3)
R - 0
R - 0
R/W - 0
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
bit7
bit0
bit 7:
CA2OVF: Capture2 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L)
before the next capture event occurred.The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the Timer3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture2 register
0 = No overflow occurred on Capture2 register
bit 6:
CA1OVF: Capture1 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(PR3H/CA2H:PR3L/CA2L) before the next capture event occurred. The capture register retains the old-
est unread capture value (last capture before overflow). Subsequent capture events will not update the
capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture1 register
0 = No overflow occurred on Capture1 register
bit 5:
bit 4:
bit 3:
PWM2ON: PWM2 On bit
1 = PWM2 is enabled (The RB3/PWM2 pin ignores the state of the DDRB<3> bit)
0 = PWM2 is disabled (The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction)
PWM1ON: PWM1 On bit
1 = PWM1 is enabled (The RB2/PWM1 pin ignores the state of the DDRB<2> bit)
0 = PWM1 is disabled (The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction)
CA1/PR3: CA1/PR3 Register Mode Select bit
1 = Enables Capture1 (PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without
a period register)
0 = Enables the Period register (PR3H/CA1H:PR3L/CA1L is the Period register for Timer3)
bit 2:
bit 1:
TMR3ON: Timer3 On bit
1 = Starts Timer3
0 = Stops Timer3
TMR2ON: Timer2 On bit
This bit controls the incrementing of the Timer2 register. When Timer2:Timer1 form the 16-bit timer (T16
is set), TMR2ON must be set. This allows the MSB of the timer to increment.
1 = Starts Timer2 (Must be enabled if the T16 bit (TCON1<3>) is set)
0 = Stops Timer2
bit 0:
TMR1ON: Timer1 On bit
When T16 is set (in 16-bit Timer Mode)
1 = Starts 16-bit Timer2:Timer1
0 = Stops 16-bit Timer2:Timer1
When T16 is clear (in 8-bit Timer Mode)
1 = Starts 8-bit Timer1
0 = Stops 8-bit Timer1
DS30412C-page 72
1996 Microchip Technology Inc.
PIC17C4X
12.1.1.1 EXTERNAL CLOCK INPUT FOR TIMER1
OR TIMER2
12.1
Timer1 and Timer2
12.1.1 TIMER1, TIMER2 IN 8-BIT MODE
When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the timer will increment on every
falling edge on the RB4/TCLK12 pin.The TCLK12 input
is synchronized with internal phase clocks.This causes
a delay from the time a falling edge appears on TCLK12
to the time TMR1 or TMR2 is actually incremented. For
the external clock input timing requirements, see the
Electrical Specification section.
Both Timer1 and Timer2 will operate in 8-bit mode
when the T16 bit is clear.These two timers can be inde-
pendently configured to increment from the internal
instruction cycle clock or from an external clock source
on the RB4/TCLK12 pin.The timer clock source is con-
figured by the TMRxCS bit (x = 1 for Timer1 or = 2 for
Timer2). When TMRxCS is clear, the clock source is
internal and increments once every instruction cycle
(Fosc/4). When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the timer will increment on every
falling edge of the RB4/TCLK12 pin.
The timer increments from 00h until it equals the Period
register (PRx). It then resets to 00h at the next incre-
ment cycle.The timer interrupt flag is set when the timer
is reset. TMR1 and TMR2 have individual interrupt flag
bits. The TMR1 interrupt flag bit is latched into TMR1IF,
and the TMR2 interrupt flag bit is latched into TMR2IF.
Each timer also has a corresponding interrupt enable
bit (TMRxIE).The timer interrupt can be enabled by set-
ting this bit and disabled by clearing this bit. For periph-
eral interrupts to be enabled, the Peripheral Interrupt
Enable bit must be enabled (PEIE is set) and global
interrupts must be enabled (GLINTD is cleared).
The timers can be turned on and off under software
control. When the Timerx On control bit (TMRxON) is
set, the timer increments from the clock source. When
TMRxON is cleared, the timer is turned off and cannot
cause the timer interrupt flag to be set.
FIGURE 12-3: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE
0
1
Fosc/4
Reset
Equal
TMR1
Comparatorx8
PR1
Set TMR1IF
(PIR<4>)
TMR1ON
(TCON2<0>)
TMR1CS
(TCON1<0>)
RB4/TCLK12
1
0
Reset
Equal
TMR2
Comparatorx8
PR2
Set TMR2IF
(PIR<5>)
Fosc/4
TMR2ON
(TCON2<1>)
TMR2CS
(TCON1<1>)
1996 Microchip Technology Inc.
DS30412C-page 73
PIC17C4X
12.1.2 TIMER1 & TIMER2 IN 16-BIT MODE
12.1.2.1 EXTERNAL CLOCK INPUT FOR
TMR1:TMR2
To select 16-bit mode, the T16 bit must be set. In this
mode TMR1 and TMR2 are concatenated to form a
16-bit timer (TMR2:TMR1). The 16-bit timer incre-
ments until it matches the 16-bit period register
(PR2:PR1). On the following timer clock, the timer
value is reset to 0h, and the TMR1IF bit is set.
When TMR1CS is set, the 16-bit TMR2:TMR1 incre-
ments on the falling edge of clock input TCLK12. The
input on the RB4/TCLK12 pin is sampled and synchro-
nized by the internal phase clocks twice every instruc-
tion cycle. This causes a delay from the time a falling
edge appears on RB4/TCLK12 to the time
TMR2:TMR1 is actually incremented. For the external
clock input timing requirements, see the Electrical
Specification section.
When selecting the clock source for the16-bit timer, the
TMR1CS bit controls the entire 16-bit timer and
TMR2CS is a “don’t care.” When TMR1CS is clear, the
timer increments once every instruction cycle (Fosc/4).
When TMR1CS is set, the timer increments on every
falling edge of the RB4/TCLK12 pin. For the 16-bit timer
to increment, both TMR1ON and TMR2ON bits must be
set (Table 12-1).
TABLE 12-1: TURNING ON 16-BIT TIMER
TMR2ON
TMR1ON
Result
16-bit timer
1
1
(TMR2:TMR1) ON
Only TMR1 increments
16-bit timer OFF
0
x
1
0
FIGURE 12-4: TMR1 AND TMR2 IN 16-BIT TIMER/COUNTER MODE
1
Reset
TMR2 x 8
TMR1 x 8
RB4/TCLK12
Set Interrupt TMR1IF
(PIR<4>)
0
Fosc/4
TMR1ON
(TCON2<0>)
Comparator x16
Equal
TMR1CS
(TCON1<0>)
PR2 x 8
PR1 x 8
TABLE 12-2: SUMMARY OF TIMER1 AND TIMER2 REGISTERS
Value on
Power-on other resets
Reset (Note1)
Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 3
17h, Bank 3
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
TCON1
TCON2
TMR1
TMR2
PIR
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Timer1 register
Timer2 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0010 0000 0010
0000 0000 0000 0000
0000 0000 0000 0000
RBIF
RBIE
PEIF
TMR3IF
TMR2IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
CA1IF
CA1IE
TXIF
TXIE
T0IE
RCIF
RCIE
INTE
PIE
TMR3IE TMR2IE
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIF
—
T0IF
T0CKIE
—
STKAV
GLINTD
TO
PD
—
—
--11 11-- --11 qq--
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
12h, Bank 3
13h, Bank 3
PR1
Timer1 period register
Timer2 period register
PR2
PW1DCL
PW2DCL
PW1DCH
PW2DCH
DC1
DC1
DC9
DC9
DC0
DC0
DC8
DC8
—
TM2PW2
DC7
—
—
—
—
—
—
—
—
—
—
DC6
DC6
DC5
DC5
DC4
DC4
DC3
DC3
DC2
DC2
DC7
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', q - value depends on condition,
shaded cells are not used by Timer1 or Timer2.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
DS30412C-page 74
1996 Microchip Technology Inc.
PIC17C4X
12.1.3 USING PULSE WIDTH MODULATION
(PWM) OUTPUTS WITH TMR1 AND TMR2
FIGURE 12-5: SIMPLIFIED PWM BLOCK
DIAGRAM
PWxDCL<7:6>
Two high speed pulse width modulation (PWM) outputs
are provided. The PWM1 output uses Timer1 as its
time-base, while PWM2 may be software configured to
use either Timer1 or Timer2 as the time-base. The
PWM outputs are on the RB2/PWM1 and RB3/PWM2
pins.
Duty Cycle registers
Write
PWxDCH
Read
(Slave)
RCy/PWMx
Comparator
R
S
Q
Each PWM output has a maximum resolution of
10-bits. At 10-bit resolution, the PWM output frequency
is 24.4 kHz (@ 25 MHz clock) and at 8-bit resolution the
PWM output frequency is 97.7 kHz. The duty cycle of
the output can vary from 0% to 100%.
TMR2
(Note 1)
PWMxON
Comparator
Clear Timer,
PWMx pin and
Latch D.C.
PRy
Figure 12-5 shows a simplified block diagram of the
PWM module. The duty cycle register is double buff-
ered for glitch free operation. Figure 12-6 shows how a
glitch could occur if the duty cycle registers were not
double buffered.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
The user needs to set the PWM1ON bit (TCON2<4>)
to enable the PWM1 output. When the PWM1ON bit is
set, the RB2/PWM1 pin is configured as PWM1 output
and forced as an output irrespective of the data direc-
tion bit (DDRB<2>). When the PWM1ON bit is clear,
the pin behaves as a port pin and its direction is con-
trolled by its data direction bit (DDRB<2>). Similarly,
the PWM2ON (TCON2<5>) bit controls the configura-
tion of the RB3/PWM2 pin.
FIGURE 12-6: PWM OUTPUT
0
10
20
30
40
0
PWM
output
Timer
interrupt
Write new
PWM value
Timer interrupt
new PWM value
transferred to slave
Note The dotted line shows PWM output if duty cycle registers were not double buffered.
If the new duty cycle is written after the timer has passed that value, then the PWM does
not reset at all during the current cycle causing a “glitch”.
In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.
1996 Microchip Technology Inc.
DS30412C-page 75
PIC17C4X
12.1.3.1 PWM PERIODS
The user should also avoid any "read-modify-write"
operations on the duty cycle registers, such as:ADDWF
PW1DCH. This may cause duty cycle outputs that are
unpredictable.
The period of the PWM1 output is determined by
Timer1 and its period register (PR1). The period of the
PWM2 output can be software configured to use either
Timer1 or Timer2 as the time-base. When TM2PW2 bit
(PW2DCL<5>) is clear, the time-base is determined by
TMR1 and PR1. When TM2PW2 is set, the time-base
is determined by Timer2 and PR2.
TABLE 12-3: PWM FREQUENCY vs.
RESOLUTION AT 25 MHz
Frequency (kHz)
PWM
Running two different PWM outputs on two different
timers allows different PWM periods. Running both
PWMs from Timer1 allows the best use of resources by
freeing Timer2 to operate as an 8-bit timer. Timer1 and
Timer2 can not be used as a 16-bit timer if either PWM
is being used.
Frequency
24.4 48.8 65.104 97.66 390.6
PRx Value 0xFF 0x7F 0x5F
0x3F
0x0F
6-bit
High
Resolution
10-bit 9-bit 8.5-bit 8-bit
Standard
8-bit
7-bit 6.5-bit 6-bit
4-bit
The PWM periods can be calculated as follows:
period of PWM1 =[(PR1) + 1] x 4TOSC
Resolution
12.1.3.2 PWM INTERRUPTS
period of PWM2 =[(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
The PWM module makes use of TMR1 or TMR2 inter-
rupts. A timer interrupt is generated when TMR1 or
TMR2 equals its period register and is cleared to zero.
This interrupt also marks the beginning of a PWM
cycle. The user can write new duty cycle values before
the timer roll-over. The TMR1 interrupt is latched into
the TMR1IF bit and the TMR2 interrupt is latched into
the TMR2IF bit. These flags must be cleared in soft-
ware.
The duty cycle of PWMx is determined by the 10-bit
value DCx<9:0>. The upper 8-bits are from register
PWxDCH and the lower 2-bits are from PWxDCL<7:6>
(PWxDCH:PWxDCL<7:6>). Table 12-3 shows the
maximum PWM frequency (FPWM) given the value in
the period register.
The number of bits of resolution that the PWM can
achieve depends on the operation frequency of the
device as well as the PWM frequency (FPWM).
12.1.3.3 EXTERNAL CLOCK SOURCE
Maximum PWM resolution (bits) for a given PWM fre-
quency:
The PWMs will operate regardless of the clock source
of the timer. The use of an external clock has ramifica-
tions that must be understood. Because the external
TCLK12 input is synchronized internally (sampled once
per instruction cycle), the time TCLK12 changes to the
time the timer increments will vary by as much as TCY
(one instruction cycle). This will cause jitter in the duty
cycle as well as the period of the PWM output.
FOSC
log ( FPWM )
=
bits
log (2)
The PWMx duty cycle is as follows:
This jitter will be ±TCY, unless the external clock is syn-
chronized with the processor clock. Use of one of the
PWM outputs as the clock source to the TCLKx input,
will supply a synchronized clock.
PWMx Duty Cycle = (DCx) x TOSC
where DCx represents the 10-bit value from
PWxDCH:PWxDCL.
If DCx = 0, then the duty cycle is zero. If PRx =
PWxDCH, then the PWM output will be low for one to
four Q-clock (depending on the state of the
PWxDCL<7:6> bits). For a Duty Cycle to be 100%, the
PWxDCH value must be greater then the PRx value.
In general, when using an external clock source for
PWM, its frequency should be much less than the
device frequency (Fosc).
The duty cycle registers for both PWM outputs are dou-
ble buffered. When the user writes to these registers,
they are stored in master latches. When TMR1 (or
TMR2) overflows and a new PWM period begins, the
master latch values are transferred to the slave latches
and the PWMx pin is forced high.
Note: For PW1DCH, PW1DCL, PW2DCH and
PW2DCL registers,
a write operation
writes to the "master latches" while a read
operation reads the "slave latches". As a
result, the user may not read back what
was just written to the duty cycle registers.
DS30412C-page 76
1996 Microchip Technology Inc.
PIC17C4X
12.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR
EXTERNAL CLOCK INPUT
Timer3 has two modes of operation, depending on the
CA1/PR3 bit (TCON2<3>). These modes are:
• One capture and one period register mode
• Dual capture register mode
The use of an external clock for the PWM time-base
(Timer1 or Timer2) limits the PWM output to a maxi-
mum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when inter-
nal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, is shown in Table 12-3 (standard res-
olution mode).
The PIC17C4X has up to two 16-bit capture registers
that capture the 16-bit value of TMR3 when events are
detected on capture pins. There are two capture pins
(RB0/CAP1 and RB1/CAP2), one for each capture reg-
ister. The capture pins are multiplexed with PORTB
pins. An event can be:
• a rising edge
• a falling edge
• every 4th rising edge
• every 16th rising edge
12.2
Timer3
Each 16-bit capture register has an interrupt flag asso-
ciated with it. The flag is set when a capture is made.
The capture module is truly part of the Timer3 block.
Figure 12-7 and Figure 12-8 show the block diagrams
for the two modes of operation.
Timer3 is a 16-bit timer consisting of the TMR3H and
TMR3L registers. TMR3H is the high byte of the timer
and TMR3L is the low byte. This timer has an associ-
ated 16-bit period register (PR3H/CA1H:PR3L/CA1L).
This period register can be software configured to be a
second 16-bit capture register.
When the TMR3CS bit (TCON1<2>) is clear, the timer
increments every instruction cycle (Fosc/4). When
TMR3CS is set, the timer increments on every falling
edge of the RB5/TCLK3 pin. In either mode, the
TMR3ON bit must be set for the timer to increment.
When TMR3ON is clear, the timer will not increment or
set the TMR3IF bit.
TABLE 12-4: REGISTERS/BITS ASSOCIATED WITH PWM
Value on all
other
resets
Value on
Power-on
Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Note1)
16h, Bank 3
TCON1
CA2ED1
CA2OVF
CA2ED0
CA1ED1
CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
TCON2
TMR1
TMR2
PIR
CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Timer1 register
Timer2 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0010 0000 0010
0000 0000 0000 0000
0000 0000 0000 0000
RBIF
RBIE
PEIF
TMR3IF
TMR2IF
TMR2IE
T0IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
CA1IF
CA1IE
TXIF
TXIE
T0IE
RCIF
RCIE
INTE
PIE
TMR3IE
T0CKIF
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIE
—
—
STKAV
—
GLINTD
—
TO
—
PD
—
—
—
—
—
--11 11-- --11 qq--
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
10h, Bank 3
11h, Bank 3
12h, Bank 3
13h, Bank 3
PW1DCL
PW2DCL
PW1DCH
PW2DCH
DC1
DC1
DC9
DC9
DC0
DC0
DC8
DC8
TM2PW2
DC7
—
—
—
—
—
DC6
DC6
DC5
DC5
DC4
DC4
DC3
DC3
DC2
DC2
DC7
Legend: x= unknown, u= unchanged, -= unimplemented read as '0', q= value depends on conditions,
shaded cells are not used by PWM.
1996 Microchip Technology Inc.
DS30412C-page 77
PIC17C4X
12.2.1 ONE CAPTURE AND ONE PERIOD
REGISTER MODE
Capture pin RB1/CAP2 is a multiplexed pin.When used
as a port pin, Capture2 is not disabled. However, the
user can simply disable the Capture2 interrupt by clear-
ing CA2IE. If RB1/CAP2 is used as an output pin, the
user can activate a capture by writing to the port pin.
This may be useful during development phase to emu-
late a capture interrupt.
In this mode registers PR3H/CA1H and PR3L/CA1L
constitute a 16-bit period register. A block diagram is
shown in Figure 12-7. The timer increments until it
equals the period register and then resets to 0000h.
TMR3 Interrupt Flag bit (TMR3IF) is set at this point.
This interrupt can be disabled by clearing the TMR3
Interrupt Enable bit (TMR3IE). TMR3IF must be
cleared in software.
The input on capture pin RB1/CAP2 is synchronized
internally to internal phase clocks.This imposes certain
restrictions on the input waveform (see the Electrical
Specification section for timing).
This mode is selected if control bit CA1/PR3 is clear. In
this mode, the Capture1 register, consisting of high
byte (PR3H/CA1H) and low byte (PR3L/CA1L), is con-
figured as the period control register for TMR3.
Capture1 is disabled in this mode, and the correspond-
ing Interrupt bit CA1IF is never set. TMR3 increments
until it equals the value in the period register and then
resets to 0000h.
The Capture2 overflow status flag bit is double buff-
ered. The master bit is set if one captured word is
already residing in the Capture2 register and another
“event” has occurred on the RB1/CA2 pin. The new
event will not transfer the Timer3 value to the capture
register, protecting the previous unread capture value.
When the user reads both the high and the low bytes (in
any order) of the Capture2 register, the master overflow
bit is transferred to the slave overflow bit (CA2OVF) and
then the master bit is reset. The user can then read
TCON2 to determine the value of CA2OVF.
Capture2 is active in this mode. The CA2ED1 and
CA2ED0 bits determine the event on which capture will
occur. The possible events are:
• Capture on every falling edge
• Capture on every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
The recommended sequence to read capture registers
and capture overflow flag bits is shown in
Example 12-1.
EXAMPLE 12-1: SEQUENCE TO READ
CAPTURE REGISTERS
When a capture takes place, an interrupt flag is latched
into the CA2IF bit.This interrupt can be enabled by set-
ting the corresponding mask bit CA2IE. The Peripheral
Interrupt Enable bit (PEIE) must be set and the Global
Interrupt Disable bit (GLINTD) must be cleared for the
interrupt to be acknowledged. The CA2IF interrupt flag
bit must be cleared in software.
MOVLB 3
;Select Bank 3
MOVPF CA2L,LO_BYTE
;Read Capture2 low
;byte, store in LO_BYTE
;Read Capture2 high
;byte, store in HI_BYTE
MOVPF CA2H,HI_BYTE
MOVPF TCON2,STAT_VAL ;Read TCON2 into file
;STAT_VAL
When the capture prescale select is changed, the pres-
caler is not reset and an event may be generated.
Therefore, the first capture after such a change will be
ambiguous. However, it sets the time-base for the next
capture. The prescaler is reset upon chip reset.
FIGURE 12-7: TIMER3 WITH ONE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
TMR3CS
PR3H/CA1H
PR3L/CA1L
(TCON1<2>)
Set TMR3IF
(PIR<6>)
Comparatorx16
Equal
Reset
0
Fosc/4
TMR3H
TMR3L
1
TMR3ON
(TCON2<2>)
RB5/TCLK3
RB1/CAP2
Capture1 Enable
CA2H
CA2L
Edge select
prescaler select
Set CA2IF
(PIR<3>)
2
CA2ED1: CA2ED0
(TCON1<7:6>)
DS30412C-page 78
1996 Microchip Technology Inc.
PIC17C4X
12.2.2 DUAL CAPTURE REGISTER MODE
The Capture2 overflow status flag bit is double buff-
ered. The master bit is set if one captured word is
already residing in the Capture2 register and another
“event” has occurred on the RB1/CA2 pin. The new
event will not transfer the TMR3 value to the capture
register which protects the previous unread capture
value. When the user reads both the high and the low
bytes (in any order) of the Capture2 register, the master
overflow bit is transferred to the slave overflow bit
(CA2OVF) and then the master bit is reset. The user
can then read TCON2 to determine the value of
CA2OVF.
This mode is selected by setting CA1/PR3. A block dia-
gram is shown in Figure 12-8. In this mode, TMR3 runs
without a period register and increments from 0000h to
FFFFh and rolls over to 0000h. The TMR3 interrupt
Flag (TMR3IF) is set on this roll over. The TMR3IF bit
must be cleared in software.
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set on the capture event.The corresponding
interrupt mask bit is CA1IE. The Capture1 Overflow
Status bit is CA1OVF.
The operation of the Capture1 feature is identical to
Capture2 (as described in Section 12.2.1).
FIGURE 12-8: TIMER3 WITH TWO CAPTURE REGISTERS BLOCK DIAGRAM
CA1ED1, CA1ED0
(TCON1<5:4>)
2
Set CA1IF
(PIR<2>)
PR3H/CA1H
Capture Enable
PR3L/CA1L
TMR3L
Edge Select
Prescaler Select
RB0/CAP1
Set TMR3IF
(PIR<6>)
Fosc/4
0
1
TMR3H
TMR3ON
(TCON2<2>)
RB5/TCLK3
RB1/CAP2
Capture Enable
TMR3CS
(TCON1<2>)
Edge Select
Set CA2IF
(PIR<3>)
Prescaler Select
CA2H
CA2L
2
CA2ED1, CA2ED0
(TCON1<7:6>)
TABLE 12-5: REGISTERS ASSOCIATED WITH CAPTURE
Value on
Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on other resets
Reset (Note1)
16h, Bank 3
17h, Bank 3
12h, Bank 2
13h, Bank 2
16h, Bank 1
17h, Bank 1
TCON1
TCON2
TMR3L
TMR3H
PIR
CA2ED1 CA2ED0 CA1ED1
CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
TMR3 register; low byte
TMR3 register; high byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0010 0000 0010
0000 0000 0000 0000
0000 0000 0000 0000
--11 11-- --11 qq--
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RBIF
RBIE
PEIF
—
TMR3IF
TMR3IE
T0CKIF
—
TMR2IF
TMR2IE
T0IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
TO
CA1IF
CA1IE
T0CKIE
PD
TXIF
TXIE
T0IE
—
RCIF
RCIE
INTE
—
PIE
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
STKAV
GLINTD
16h, Bank 2
17h, Bank 2
14h, Bank 3
15h, Bank 3
PR3L/CA1L Timer3 period register, low byte/capture1 register, low byte
PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte
CA2L
CA2H
Capture2 low byte
Capture2 high byte
Legend: x= unknown, u= unchanged, -= unimplemented read as '0', q- value depends on condition,
shaded cells are not used by Capture.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 79
PIC17C4X
12.2.3 EXTERNAL CLOCK INPUT FOR TIMER3
EXAMPLE 12-2: WRITING TO TMR3
BSF
CPUSTA, GLINTD ;Disable interrupt
When TMR3CS is set, the 16-bit TMR3 increments on
the falling edge of clock input TCLK3. The input on the
RB5/TCLK3 pin is sampled and synchronized by the
internal phase clocks twice every instruction cycle.This
causes a delay from the time a falling edge appears on
TCLK3 to the time TMR3 is actually incremented. For
the external clock input timing requirements, see the
Electrical Specification section. Figure 12-9 shows the
timing diagram when operating from an external clock.
MOVFP RAM_L, TMR3L
MOVFP RAM_H, TMR3H
BCF
;
;
CPUSTA, GLINTD ;Done,enable interrupt
EXAMPLE 12-3: READING FROM TMR3
MOVPF
MOVPF
MOVFP
CPFSLT TMR3L, WREG
RETURN
MOVPF
MOVPF
RETURN
TMR3L, TMPLO
TMR3H, TMPHI
TMPLO, WREG
;read low tmr0
;read high tmr0
;tmplo −> wreg
;tmr0l < wreg?
;no then return
;read low tmr0
;read high tmr0
;return
12.2.4 READING/WRITING TIMER3
TMR3L, TMPLO
TMR3H, TMPHI
Since Timer3 is a 16-bit timer and only 8-bits at a time
can be read or written, care should be taken when
reading or writing while the timer is running. The best
method to read or write the timer is to stop the timer,
perform any read or write operation, and then restart
Timer3 (using the TMR3ON bit). However, if it is neces-
sary to keep Timer3 free-running, care must be taken.
For writing to the 16-bit TMR3, Example 12-2 may be
used. For reading the 16-bit TMR3, Example 12-3 may
be used. Interrupts must be disabled during this rou-
tine.
FIGURE 12-9: TMR1,TMR2, AND TMR3 OPERATION IN EXTERNAL CLOCK MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TCLK12
34h
35h
A8h
A9h
00h
TMR1, TMR2, or TMR3
PR1, PR2, or PR3H:PR3L
WR_TMR
'A9h'
'A9h'
Read_TMR
TMRxIF
MOVWF
TMRx
MOVFP
MOVFP
TMRx,W
TMRx,W
Instruction
executed
Write to TMRx
Read TMRx
Read TMRx
Note 1: TCLK12 is sampled in Q2 and Q4.
2: ↓ indicates a sampling point.
3: The latency from TCLK12 ↓ to timer increment is between 2Tosc and 6Tosc.
DS30412C-page 80
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 12-10: TMR1,TMR2, AND TMR3 OPERATION IN TIMER MODE
Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4
AD15:AD0
ALE
BCF
TCON2, 0
Start TMR1
MOVF
BSF
MOVWF
TMR1
MOVF
NOP
07h
NOP
NOP
NOP
00h
Instruction
fetched
MOVLB 3
NOP
06h
TMR1, W
Read TMR1
TCON2, 0
Stop TMR1
TMR1, W
Write TMR1 Read TMR1
TMR1
PR1
04h
05h
03h
04h
05h
08h
TMR1ON
WR_TMR1
WR_TCON2
TMR1IF
RD_TMR1
TMR1
reads 03h
TMR1
reads 04h
TABLE 12-6: SUMMARY OF TMR1,TMR2, AND TMR3 REGISTERS
Value on
Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on other resets
Reset (Note1)
16h, Bank 3
TCON1
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3
10h, Bank 2
11h, Bank 2
12h, Bank 2
13h, Bank 2
16h, Bank 1
17h, Bank 1
TCON2
TMR1
TMR2
TMR3L
TMR3H
PIR
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Timer1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0010 0000 0010
0000 0000 0000 0000
0000 0000 0000 0000
Timer2 register
TMR3 register; low byte
TMR3 register; high byte
RBIF
RBIE
PEIF
TMR3IF
TMR2IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
CA1IF
CA1IE
TXIF
TXIE
T0IE
RCIF
RCIE
INTE
PIE
TMR3IE TMR2IE
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIF
—
T0IF
T0CKIE
—
STKAV
GLINTD
TO
PD
—
—
--11 11-- --11 qq--
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h, Bank 2
15h, Bank 2
16h, Bank 2
17h, Bank 2
10h, Bank 3
11h, Bank 3
12h, Bank 3
13h, Bank 3
14h, Bank 3
15h, Bank 3
PR1
PR2
Timer1 period register
Timer2 period register
PR3L/CA1L Timer3 period/capture1 register; low byte
PR3H/CA1H Timer3 period/capture1 register; high byte
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
DC1
DC1
DC9
DC9
DC0
DC0
DC8
DC8
—
TM2PW2
DC7
—
—
—
—
—
—
—
—
—
—
DC6
DC6
DC5
DC5
DC4
DC4
DC3
DC3
DC2
DC2
DC7
Capture2 low byte
Capture2 high byte
CA2H
Legend: x= unknown, u= unchanged, -= unimplemented read as '0', q- value depends on condition,
shaded cells are not used by TMR1, TMR2 or TMR3.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 81
PIC17C4X
NOTES:
DS30412C-page 82
1996 Microchip Technology Inc.
PIC17C4X
The SPEN (RCSTA<7>) bit has to be set in order to
configure RA4 and RA5 as the Serial Communication
Interface.
13.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
The USART module is a serial I/O module.The USART
can be configured as a full duplex asynchronous sys-
tem that can communicate with peripheral devices such
as CRT terminals and personal computers, or it can be
configured as a half duplex synchronous system that
can communicate with peripheral devices such as A/D
or D/A integrated circuits, Serial EEPROMs etc. The
USART can be configured in the following modes:
The USART module will control the direction of the
RA4/RX/DT and RA5/TX/CK pins, depending on the
states of the USART configuration bits in the RCSTA
and TXSTA registers. The bits that control I/O direction
are:
• SPEN
• TXEN
• SREN
• CREN
• CSRC
• Asynchronous (full duplex)
The Transmit Status And Control Register is shown in
Figure 13-1, while the Receive Status And Control
Register is shown in Figure 13-2.
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
FIGURE 13-1: TXSTA REGISTER (ADDRESS: 15h, BANK 0)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
CSRC TX9 TXEN SYNC
bit7
U - 0
—
U - 0
—
R - 1
TRMT
R/W - x
TX9D
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit0
bit 7:
CSRC: Clock Source Select bit
Synchronous mode:
1 = Master Mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
Asynchronous mode:
Don’t care
bit 6:
bit 5:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SREN/CREN overrides TXEN in SYNC mode
bit 4:
SYNC: USART mode Select bit
(Synchronous/Asynchronous)
1 = Synchronous mode
0 = Asynchronous mode
bit 3-2: Unimplemented: Read as '0'
bit 1:
TRMT: Transmit Shift Register (TSR) Empty bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data (can be used to calculated the parity in software)
1996 Microchip Technology Inc.
DS30412C-page 83
PIC17C4X
FIGURE 13-2: RCSTA REGISTER (ADDRESS: 13h, BANK 0)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN RX9 SREN CREN
bit7
U - 0
—
R - 0
FERR
R - 0
OERR
R - x
RX9D
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 0
bit 7:
bit 6:
bit 5:
SPEN: Serial Port Enable bit
1 = Configures RA5/RX/DT and RA4/TX/CK pins as serial port pins
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
bit 4:
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable reception
0 = Disables reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
bit 3:
bit 2:
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
bit 1:
bit 0:
OERR: Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
RX9D: 9th bit of receive data (can be the software calculated parity bit)
DS30412C-page 84
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 13-3: USART TRANSMIT
Sync
Master/Slave
BRG
÷ 4
Sync/Async
CK/TX
Sync/Async
Sync/Async
TSR
÷ 16
Clock
• • •
Start 0 1
7 8 Stop
DT
Load
Bit Count
TXEN/
Write to TXREG
8
• • •
0 1
7
TXREG
Interrupt
TXSTA<0>
Data Bus
TXIE
FIGURE 13-4: USART RECEIVE
Interrupt
RCIE
OSC
÷ 4
BRG
Master/Slave
Sync
Sync/Async
Async/Sync
enable
Buffer
Logic
Bit Count
÷ 16
CK
RX
START
Detect
SPEN
SREN/
CREN/
Start_Bit
RSR
Majority
Detect
Buffer
Logic
Clock
Data
MSb
LSb
1 0
• • •
Stop 8 7
FIFO
Logic
RX9
Async/Sync
RCREG
Clk
FIFO
• • •
• • •
RX9D
RX9D
7
7
1 0
1 0
FERR
FERR
Data Bus
1996 Microchip Technology Inc.
DS30412C-page 85
PIC17C4X
Example 13-1 shows the calculation of the baud rate
error for the following conditions:
13.1
USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. Table 13-1 shows
the formula for computation of the baud rate for differ-
ent USART modes.These only apply when the USART
is in synchronous master mode (internal clock) and
asynchronous mode.
FOSC = 16 MHz
Desired Baud Rate = 9600
SYNC = 0
EXAMPLE 13-1: CALCULATING BAUD
RATE ERROR
Desired Baud rate=Fosc / (64 (X + 1))
Given the desired baud rate and Fosc, the nearest inte-
ger value between 0 and 255 can be calculated using
the formula below. The error in baud rate can then be
determined.
9600 =
16000000 /(64 (X + 1))
25.042 = 25
X
=
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
=
9615
TABLE 13-1: BAUD RATE FORMULA
Error
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
SYNC
Mode
Baud Rate
=
=
(9615 - 9600) / 9600
0.16%
0
1
Asynchronous
Synchronous
FOSC/(64(X+1))
FOSC/(4(X+1))
X = value in SPBRG (0 to 255)
Writing a new value to the SPBRG, causes the BRG
timer to be reset (or cleared), this ensures that the BRG
does not wait for a timer overflow before outputting the
new baud rate.
TABLE 13-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
13h, Bank 0
RCSTA
SPEN
CSRC
RX9
TX9
SREN
TXEN
CREN
SYNC
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x
0000 -00u
15h, Bank 0
17h, Bank 0
TXSTA
0000 --1x
xxxx xxxx
0000 --1u
uuuu uuuu
SPBRG
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used by the Baud Rate Generator.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 86
1996 Microchip Technology Inc.
PIC17C4X
TABLE 13-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
SPBRG
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
0.3
1.2
NA
NA
—
—
—
—
NA
NA
—
—
—
—
—
—
—
80
64
20
12
0
NA
NA
—
—
—
—
NA
NA
—
—
—
—
2.4
NA
—
—
NA
—
NA
—
—
NA
—
—
9.6
NA
—
—
NA
—
NA
—
—
NA
—
—
19.2
76.8
96
NA
—
—
NA
—
19.53
76.92
96.15
294.1
500
+1.73
+0.16
+0.16
-1.96
0
255
64
51
16
9
19.23
76.92
95.24
307.69
500
+0.16
+0.16
-0.79
+2.56
0
207
51
41
12
7
77.10
95.93
294.64
485.29
8250
32.22
+0.39
-0.07
-1.79
-2.94
—
106
85
27
16
0
77.16
96.15
297.62
480.77
6250
24.41
+0.47
+0.16
-0.79
-3.85
—
300
500
HIGH
LOW
5000
19.53
—
0
4000
15.625
—
0
—
255
—
255
—
255
—
255
FOSC = 10 MHz
KBAUD
FOSC = 7.159 MHz
FOSC = 5.068 MHz
BAUD
RATE
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
NA
—
—
—
—
NA
NA
—
—
—
—
NA
NA
—
—
—
0
—
—
NA
2.4
NA
—
—
NA
—
—
NA
—
9.6
9.766
19.23
75.76
96.15
312.5
500
+1.73
+0.16
-1.36
+0.16
+4.17
0
255
129
32
25
7
9.622
19.24
77.82
94.20
298.3
NA
+0.23
+0.23
+1.32
-1.88
-0.57
—
185
92
22
18
5
9.6
131
65
15
12
3
19.2
76.8
96
19.2
79.2
97.48
316.8
NA
0
+3.13
+1.54
+5.60
—
300
500
HIGH
LOW
4
—
—
2500
9.766
—
0
1789.8
6.991
—
0
1267
4.950
—
0
—
255
—
255
—
255
FOSC = 1 MHz
FOSC = 32.768 kHz
FOSC = 3.579 MHz
BAUD
RATE
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
KBAUD
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
NA
—
—
—
—
—
92
46
11
8
NA
1.202
2.404
9.615
19.24
83.34
NA
—
+0.16
+0.16
+0.16
+0.16
+8.51
—
—
207
103
25
12
2
0.303
1.170
NA
+1.14
-2.48
—
26
6
NA
2.4
NA
—
—
—
—
—
—
—
—
0
9.6
9.622
19.04
74.57
99.43
298.3
NA
+0.23
-0.83
-2.90
_3.57
-0.57
—
NA
—
19.2
76.8
96
NA
—
NA
—
—
NA
—
300
500
HIGH
LOW
2
NA
—
—
NA
—
—
0
NA
—
—
NA
—
894.9
3.496
—
250
—
0
8.192
0.032
—
—
255
0.976
—
255
—
255
1996 Microchip Technology Inc.
DS30412C-page 87
PIC17C4X
TABLE 13-4: BAUD RATES FOR ASYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
0.3
1.2
NA
—
—
—
—
214
53
26
6
NA
NA
—
—
—
—
162
40
19
4
NA
—
—
255
129
32
15
3
NA
1.202
2.404
9.615
19.23
83.33
NA
—
+0.16
+0.16
+0.16
+0.16
+8.51
—
—
207
103
25
12
2
NA
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
—
2.4
2.398
9.548
19.09
73.66
103.12
257.81
515.62
-0.07
-0.54
-0.54
-4.09
+7.42
-14.06
+3.13
—
2.396
9.53
19.53
78.13
97.65
390.63
NA
0.14
-0.76
+1.73
+1.73
+1.73
+30.21
—
9.6
19.2
76.8
96
4
3
2
—
300
500
1
0
0
NA
—
—
0
—
0
—
0
NA
—
—
HIGH 515.62
LOW 2.014
0
—
—
312.5
1.221
—
250
—
0
—
255
1.53
—
255
—
255
0.977
—
255
FOSC = 7.159 MHz
FOSC = 5.068 MHz
FOSC = 10 MHz
KBAUD
BAUD
RATE
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
+3.13
0.3
1.2
NA
—
+0.16
+0.16
+1.73
+1.73
+1.73
—
—
129
64
15
7
NA
1.203
2.380
9.322
18.64
NA
—
_0.23
-0.83
-2.90
-2.90
—
—
92
46
11
5
0.31
1.2
255
65
32
7
1.202
2.404
9.766
19.53
78.13
NA
0
0
2.4
2.4
9.6
9.9
-3.13
+3.13
+3.13
—
19.2
76.8
96
19.8
79.2
NA
3
1
—
—
—
—
0
0
—
—
—
0
NA
—
—
—
—
0
300
500
HIGH
LOW
NA
—
NA
—
NA
—
NA
—
NA
—
NA
—
156.3
0.610
—
111.9
0.437
—
79.2
0.309
—
—
255
—
255
—
255
FOSC = 1 MHz
FOSC = 32.768 kHz
FOSC = 3.579 MHz
BAUD
RATE
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
KBAUD
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
0.301
1.190
2.432
9.322
18.64
NA
+0.23
-0.83
+1.32
-2.90
-2.90
—
185
46
22
5
0.300
1.202
2.232
NA
+0.16
+0.16
-6.99
—
51
12
6
0.256
NA
-14.67
—
1
—
—
—
—
—
—
—
—
0
2.4
NA
—
9.6
—
—
—
—
—
—
0
NA
—
19.2
76.8
96
2
NA
—
NA
—
—
—
—
—
0
NA
—
NA
—
NA
—
NA
—
NA
—
300
500
HIGH
LOW
NA
—
NA
—
NA
—
NA
—
NA
—
NA
—
55.93
0.218
—
15.63
0.061
—
0.512
0.002
—
—
255
—
255
—
255
DS30412C-page 88
1996 Microchip Technology Inc.
PIC17C4X
Transmission
is
enabled
by
setting
the
13.2
USART Asynchronous Mode
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 13-5). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 13-6). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the
RA5/TX/CK pin will revert to hi-impedance.
In this mode, the USART uses standard nonre-
turn-to-zero (NRZ) format (one start bit, eight or nine
data bits, and one stop bit).The most common data for-
mat is 8-bits. An on-chip dedicated 8-bit baud rate gen-
erator can be used to derive standard baud rate
frequencies from the oscillator. The USART’s transmit-
ter and receiver are functionally independent but use
the same data format and baud rate. The baud rate
generator produces a clock x64 of the bit shift rate. Par-
ity is not supported by the hardware, but can be imple-
mented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to the
TXREG. This is because a data write to TXREG can
result in an immediate transfer of the data to the TSR
(if the TSR is empty).
The asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
Steps to follow when setting up an Asynchronous
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate.
13.2.1 USART ASYNCHRONOUS TRANSMITTER
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG).TXREG is
loaded with data in software. The TSR is not loaded
until the stop bit has been transmitted from the previous
load. As soon as the stop bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), the
TXREG is empty and an interrupt bit, TXIF (PIR<1>) is
set. This interrupt can be enabled or disabled by the
TXIE bit (PIE<1>). TXIF will be set regardless of TXIE
and cannot be reset in software. It will reset only when
new data is loaded into TXREG. While TXIF indicates
the status of the TXREG, the TRMT (TXSTA<1>) bit
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty.
3. If interrupts are desired, then set the TXIE bit.
4. If 9-bit transmission is desired, then set the TX9
bit.
5. Load data to the TXREG register.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
7. Enable the transmission by setting TXEN (starts
transmission).
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the opposite
order.
Note: To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
Note: The TSR is not mapped in data memory,
so it is not available to the user.
1996 Microchip Technology Inc.
DS30412C-page 89
PIC17C4X
FIGURE 13-5: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
TX
Start Bit
Bit 0
Bit 1
Word 1
Bit 7/8
(RA5/TX/CK pin)
Stop Bit
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
FIGURE 13-6: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
TX
Start Bit
Start Bit
Word 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Stop Bit
(RA5/TX/CK pin)
Word 1
TXIF bit
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
Note: This timing diagram shows two consecutive transmissions.
TABLE 13-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
13h, Bank 0
16h, Bank 0
17h, Bank 1
15h, Bank 0
17h, Bank 0
PIR
RBIF
TMR3IF TMR2IF TMR1IF CA2IF CA1IF
RX9 SREN CREN FERR
TXIF
RCIF
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
RCSTA
TXREG
PIE
SPEN
—
OERR
RX9D
Serial port transmit register
RBIE
TMR3IE TMR2IE TMR1IE CA2IE CA1IE
TX9 TXEN SYNC
TXIE
RCIE
TX9D
TXSTA
SPBRG
CSRC
—
—
TRMT
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for asynchronous
transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 90
1996 Microchip Technology Inc.
PIC17C4X
13.2.2 USART ASYNCHRONOUS RECEIVER
Note: The FERR and the 9th receive bit are buff-
ered the same way as the receive data.
Reading the RCREG register will allow the
RX9D and FERR bits to be loaded with val-
ues for the next received Received data;
therefore, it is essential for the user to read
the RCSTA register before reading
RCREG in order not to lose the old FERR
and RX9D information.
The receiver block diagram is shown in Figure 13-4.
The data comes in the RA4/RX/DT pin and drives the
data recovery block.The data recovery block is actually
a high speed shifter operating at 16 times the baud
rate, whereas the main receive serial shifter operates
at the bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
13.2.3 SAMPLING
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the stop bit, the received
data in the RSR is transferred to the RCREG (if it is
empty). If the transfer is complete, the interrupt bit
RCIF (PIR<0>) is set. The actual interrupt can be
enabled/disabled by setting/clearing the RCIE
(PIE<0>) bit. RCIF is a read only bit which is cleared by
the hardware. It is cleared when RCREG has been
read and is empty. RCREG is a double buffered regis-
ter; (i.e. it is a two deep FIFO). It is possible for two
bytes of data to be received and transferred to the
RCREG FIFO and a third byte begin shifting to the
RSR. On detection of the stop bit of the third byte, if the
RCREG is still full, then the overrun error bit,
OERR (RCSTA<1>) will be set. The word in the RSR
will be lost. RCREG can be read twice to retrieve the
two bytes in the FIFO. The OERR bit has to be cleared
in software which is done by resetting the receive logic
(CREN is set). If the OERR bit is set, transfers from the
RSR to RCREG are inhibited, so it is essential to clear
the OERR bit if it is set. The framing error bit
FERR (RCSTA<2>) is set if a stop bit is not detected.
The data on the RA4/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RA4/RX/DT pin. The sam-
pling is done on the seventh, eighth and ninth falling
edges of a x16 clock (Figure 11-3).
The x16 clock is a free running clock, and the three
sample points occur at a frequency of every 16 falling
edges.
FIGURE 13-7: RX PIN SAMPLING SCHEME
Start bit
Bit0
RX
(RA4/RX/DT pin)
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
Samples
1996 Microchip Technology Inc.
DS30412C-page 91
PIC17C4X
Steps to follow when setting up an Asynchronous
Reception:
7. Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
1. Initialize the SPBRG register for the appropriate
baud rate.
8. Read RCREG for the 8-bit received data.
9. If an overrun error occurred, clear the error by
clearing the OERR bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. Enable the reception by setting the CREN bit.
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
6. The RCIF bit will be set when reception com-
pletes and an interrupt will be generated if the
RCIE bit was set.
FIGURE 13-8: ASYNCHRONOUS RECEPTION
Start
RX
Start
bit
Start
bit
bit
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
(RA4/RX/DT pin)
Rcv shift
reg
Rcv buffer reg
Word 3
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 13-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
13h, Bank 0
14h, Bank 0
17h, Bank 1
15h, Bank 0
17h, Bank 0
PIR
RBIF
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
CA1IF
FERR
RX2
TXIF
OERR
RX1
RCIF
RX9D
RX0
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
RCSTA
RCREG
PIE
RX9
RX6
SREN
RX5
CREN
RX4
—
RX3
RBIE
CSRC
TMR3IE TMR2IE TMR1IE CA2IE
TX9 TXEN SYNC
CA1IE
—
TXIE
RCIE
TX9D
TXSTA
SPBRG
—
TRMT
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for asynchronous reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 92
1996 Microchip Technology Inc.
PIC17C4X
RA4/RX/DT pin reverts to a hi-impedance state (for a
reception). The RA5/TX/CK pin will remain an output if
the CSRC bit is set (internal clock). The transmitter
logic is not reset, although it is disconnected from the
pins. In order to reset the transmitter, the user has to
clear the TXEN bit. If the SREN bit is set (to interrupt an
ongoing transmission and receive a single word), then
after the single word is received, SREN will be cleared
and the serial port will revert back to transmitting, since
the TXEN bit is still set. The DT line will immediately
switch from hi-impedance receive mode to transmit
and start driving. To avoid this, TXEN should be
cleared.
13.3
USART Synchronous Master Mode
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e. transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchro-
nous mode is entered by setting the SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit
is set in order to configure the RA5 and RA4 I/O ports
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting the CSRC (TXSTA<7>) bit.
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
13.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
(serial) shift register (TSR).The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), TXREG
is empty and the TXIF (PIR<1>) bit is set.This interrupt
can be enabled/disabled by setting/clearing the TXIE
bit (PIE<1>). TXIF will be set regardless of the state of
bit TXIE and cannot be cleared in software. It will reset
only when new data is loaded into TXREG. While TXIF
indicates the status of TXREG, TRMT (TXSTA<1>)
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty. The TSR is not
mapped in data memory, so it is not available to the
user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
2. Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
3. Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
4. If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
5. If 9-bit transmission is desired, then set the TX9
bit.
6. Start transmission by loading data to the
TXREG register.
Transmission is enabled by setting the TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The first data
bit will be shifted out on the next available rising edge
of the clock on the RA5/TX/CK pin. Data out is stable
around the falling edge of the synchronous clock
(Figure 13-10). The transmission can also be started
by first loading TXREG and then setting TXEN. This is
advantageous when slow baud rates are selected,
since BRG is kept in RESET when the TXEN, CREN,
and SREN bits are clear. Setting the TXEN bit will start
the BRG, creating a shift clock immediately. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to the TSR, resulting in an empty TXREG.
Back-to-back transfers are possible.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
8. Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the reverse
order.
Note: To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. The RA4/RX/DT and RA5/TX/CK pins will revert to
hi-impedance. If either CREN or SREN are set during
a transmission, the transmission is aborted and the
1996 Microchip Technology Inc.
DS30412C-page 93
PIC17C4X
TABLE 13-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
13h, Bank 0
16h, Bank 0
17h, Bank 1
15h, Bank 0
17h, Bank 0
PIR
RBIF
SPEN
TX7
TMR3IF TMR2IF TMR1IF CA2IF
CA1IF
FERR
TX2
TXIF
OERR
TX1
RCIF
RX9D
TX0
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
RCSTA
TXREG
PIE
RX9
TX6
SREN
TX5
CREN
TX4
—
TX3
RBIE
CSRC
TMR3IE TMR2IE TMR1IE CA2IE
TX9 TXEN SYNC
CA1IE
—
TXIE
RCIE
TX9D
TXSTA
SPBRG
—
TRMT
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
master transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
FIGURE 13-9: SYNCHRONOUS TRANSMISSION
Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit1
bit2
bit0
DT
bit0
bit7
(RA4/RX/DT pin)
Word 1
Word 2
CK
(RA5/TX/CK pin)
Write to
TXREG
Write word 2
Write word 1
TXIF
Interrupt flag
TRMT
'1'
TXEN
Note: Sync master mode; BRG = 0. Continuous transmission of two 8-bit words.
FIGURE 13-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
DT
bit0
bit2
bit1
bit6
bit7
(RA4/RX/DT pin)
CK
(RA5/TX/CK pin)
Write to
TXREG
TXIF bit
TRMT bit
DS30412C-page 94
1996 Microchip Technology Inc.
PIC17C4X
13.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. See Section 13.1 for details.
Once synchronous mode is selected, reception is
enabled by setting either the SREN (RCSTA<5>) bit or
the CREN (RCSTA<4>) bit. Data is sampled on the
RA4/RX/DT pin on the falling edge of the clock. If
SREN is set, then only a single word is received. If
CREN is set, the reception is continuous until CREN is
reset. If both bits are set, then CREN takes prece-
dence. After clocking the last bit, the received data in
the Receive Shift Register (RSR) is transferred to
RCREG (if it is empty). If the transfer is complete, the
interrupt bit RCIF (PIR<0>) is set. The actual interrupt
can be enabled/disabled by setting/clearing the
RCIE (PIE<0>) bit. RCIF is a read only bit which is
RESET by the hardware. In this case it is reset when
RCREG has been read and is empty. RCREG is a dou-
ble buffered register; i.e., it is a two deep FIFO. It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin
shifting into the RSR. On the clocking of the last bit of
the third byte, if RCREG is still full, then the overrun
error bit OERR (RCSTA<1>) is set. The word in the
RSR will be lost. RCREG can be read twice to retrieve
the two bytes in the FIFO. The OERR bit has to be
cleared in software. This is done by clearing the CREN
bit. If OERR bit is set, transfers from RSR to RCREG
are inhibited, so it is essential to clear OERR bit if it is
set.The 9th receive bit is buffered the same way as the
receive data. Reading the RCREG register will allow
the RX9D and FERR bits to be loaded with values for
the next received data; therefore, it is essential for the
user to read the RCSTA register before reading
RCREG in order not to lose the old FERR and RX9D
information.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
6. The RCIF bit will be set when reception is com-
plete and an interrupt will be generated if the
RCIE bit was set.
7. Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
8. Read the 8-bit received data by reading
RCREG.
9. If any error occurred, clear the error by clearing
CREN.
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
FIGURE 13-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
DT
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
(RA4/RX/DT pin)
CK
(RA5/TX/CK pin)
Write to the
SREN bit
SREN bit
CREN bit
'0'
'0'
RCIF bit
Read
RCREG
Note: Timing diagram demonstrates SYNC master mode with SREN = 1.
1996 Microchip Technology Inc.
DS30412C-page 95
PIC17C4X
TABLE 13-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
13h, Bank 0
14h, Bank 0
17h, Bank 1
15h, Bank 0
17h, Bank 0
PIR
RBIF
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
CA1IF
FERR
RX2
TXIF
OERR
RX1
RCIF
RX9D
RX0
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
RCSTA
RCREG
PIE
RX9
RX6
SREN
RX5
CREN
RX4
—
RX3
RBIE
CSRC
TMR3IE TMR2IE TMR1IE CA2IE
TX9 TXEN SYNC
CA1IE
—
TXIE
RCIE
TX9D
TXSTA
SPBRG
—
TRMT
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
master reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 96
1996 Microchip Technology Inc.
PIC17C4X
13.4.2 USART SYNCHRONOUS SLAVE
13.4
USART Synchronous Slave Mode
RECEPTION
The synchronous slave mode differs from the master
mode in the fact that the shift clock is supplied exter-
nally at the RA5/TX/CK pin (instead of being supplied
internally in the master mode). This allows the device
to transfer or receive data in the SLEEP mode. The
Operation of the synchronous master and slave modes
are identical except in the case of the SLEEP mode.
Also, SREN is a don't care in slave mode.
If receive is enabled (CREN) prior to theSLEEPinstruc-
tion, then a word may be received during SLEEP. On
completely receiving the word, the RSR will transfer the
data to RCREG (setting RCIF) and if the RCIE bit is set,
the interrupt generated will wake the chip from SLEEP.
If the global interrupt is enabled, the program will
branch to the interrupt vector (0020h).
slave
mode
is
entered
by
clearing
the
CSRC (TXSTA<7>) bit.
13.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the sync master and slave modes are
identical except in the case of the SLEEP mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to TXREG and then the SLEEP
instruction executes, the following will occur. The first
word will immediately transfer to the TSR and will trans-
mit as the shift clock is supplied. The second word will
remain in TXREG. TXIF will not be set. When the first
word has been shifted out of TSR, TXREG will transfer
the second word to the TSR and the TXIF flag will now
be set. If TXIE is enabled, the interrupt will wake the
chip from SLEEP and if the global interrupt is enabled,
then the program will branch to interrupt vector
(0020h).
1. Enable the synchronous master serial port by
setting the SYNC and SPEN bits and clearing
the CSRC bit.
2. If interrupts are desired, then set the RCIE bit.
3. If 9-bit reception is desired, then set the RX9 bit.
4. To enable reception, set the CREN bit.
5. The RCIF bit will be set when reception is com-
plete and an interrupt will be generated if the
RCIE bit was set.
6. Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
Steps to follow when setting up a Synchronous Slave
Transmission:
7. Read the 8-bit received data by reading
RCREG.
1. Enable the synchronous slave serial port by set-
ting the SYNC and SPEN bits and clearing the
CSRC bit.
8. If any error occurred, clear the error by clearing
the CREN bit.
2. Clear the CREN bit.
3. If interrupts are desired, then set the TXIE bit.
4. If 9-bit transmission is desired, then set the TX9
bit.
Note: To abort reception, either clear the SPEN
bit, the SREN bit (when in single receive
mode), or the CREN bit (when in continu-
ous receive mode). This will reset the
receive logic, so that it will be in the proper
state when receive is re-enabled.
5. Start transmission by loading data to TXREG.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
7. Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the reverse
order.
Note: To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
1996 Microchip Technology Inc.
DS30412C-page 97
PIC17C4X
TABLE 13-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
13h, Bank 0
16h, Bank 0
17h, Bank 1
15h, Bank 0
17h, Bank 0
PIR
RBIF
SPEN
TX7
TMR3IF TMR2IF TMR1IF CA2IF
CA1IF
FERR
TX2
TXIF
OERR
TX1
RCIF
RX9D
TX0
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
RCSTA
TXREG
PIE
RX9
TX6
SREN
TX5
CREN
TX4
—
TX3
RBIE
CSRC
TMR3IE TMR2IE TMR1IE CA2IE
TX9 TXEN SYNC
CA1IE
—
TXIE
RCIE
TX9D
TXSTA
SPBRG
—
TRMT
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
slave transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
TABLE 13-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank1
13h, Bank0
14h, Bank0
17h, Bank1
15h, Bank 0
17h, Bank0
PIR
RBIF
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
CA1IF
FERR
RX2
TXIF
OERR
RX1
RCIF
RX9D
RX0
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
RCSTA
RCREG
PIE
RX9
RX6
SREN
RX5
CREN
RX4
—
RX3
RBIE
CSRC
TMR3IE TMR2IE TMR1IE CA2IE
TX9 TXEN SYNC
CA1IE
—
TXIE
RCIE
TX9D
TXSTA
SPBRG
—
TRMT
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
slave reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 98
1996 Microchip Technology Inc.
PIC17C4X
The PIC17CXX has a Watchdog Timer which can be
shut off only through EPROM bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the Oscil-
lator Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay of 96 ms (nominal) on power-up only, designed to
keep the part in RESET while the power supply stabi-
lizes. With these two timers on-chip, most applications
need no external reset circuitry.
14.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real
time applications. The PIC17CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
• OSC selection
The SLEEP mode is designed to offer a very low cur-
rent power-down mode. The user can wake from
SLEEP through external reset, Watchdog Timer Reset
or through an interrupt. Several oscillator options are
also made available to allow the part to fit the applica-
tion. The RC oscillator option saves system cost while
the LF crystal option saves power. Configuration bits
are used to select various options. This configuration
word has the format shown in Figure 14-1.
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
FIGURE 14-1: CONFIGURATION WORD
R/P - 1
PM2
U - x
—
U - x
—
U - x
—
U - x
—
U - x
—
U - x
—
U - x
—
(1)
bit15-7
bit0
U - x
—
R/P - 1
PM1
U - x
—
R/P - 1 R/P - 1 R/P - 1 R/P - 1 R/P - 1
PM0 WDTPS1 WDTPS0 FOSC1 FOSC0
R = Readable bit
P = Programmable bit
U = Unimplemented
- n = Value for Erased Device
(x = unknown)
bit15-7
bit0
bit 15-9: Unimplemented: Read as a '1'
bit 15,6,4:PM2, PM1, PM0, Processor Mode Select bits
111 = Microprocessor Mode
110 = Microcontroller mode
101 = Extended microcontroller mode
000 = Code protected microcontroller mode
bit 7, 5: Unimplemented: Read as a '0'
bit 3-2: WDTPS1:WDTPS0, WDT Postscaler Select bits
11 = WDT enabled, postscaler = 1
10 = WDT enabled, postscaler = 256
01 = WDT enabled, postscaler = 64
00 = WDT disabled, 16-bit overflow timer
bit 1-0: FOSC1:FOSC0, Oscillator Select bits
11 = EC oscillator
10 = XT oscillator
01 = RC oscillator
00 = LF oscillator
Note 1: This bit does not exist on the PIC17C42. Reading this bit will return an unknown value (x).
1996 Microchip Technology Inc.
DS30412C-page 99
PIC17C4X
14.1
Configuration Bits
14.2
Oscillator Configurations
The PIC17CXX has up to seven configuration locations
(Table 14-1). These locations can be programmed
(read as '0') or left unprogrammed (read as '1') to select
various device configurations. Any write to a configura-
tion location, regardless of the data, will program that
configuration bit. A TABLWT instruction is required to
write to program memory locations. The configuration
bits can be read by using the TABLRD instructions.
Reading any configuration location between FE00h
and FE07h will read the low byte of the configuration
word (Figure 14-1) into the TABLATL register. The TAB-
LATH register will be FFh. Reading a configuration
location between FE08h and FE0Fh will read the high
byte of the configuration word into the TABLATL regis-
ter. The TABLATH register will be FFh.
14.2.1
OSCILLATOR TYPES
The PIC17CXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
• LF:
• XT:
• EC:
• RC:
Low Power Crystal
Crystal/Resonator
External Clock Input
Resistor/Capacitor
14.2.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT or LF modes, a crystal or ceramic resonator is
connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 14-2). The
PIC17CXX Oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions.
Addresses FE00h thorough FE0Fh are only in the pro-
gram memory space for microcontroller and code pro-
tected microcontroller modes. A device programmer
will be able to read the configuration word in any pro-
cessor mode. See programming specifications for more
detail.
For frequencies above 20 MHz, it is common for the
crystal to be an overtone mode crystal. Use of overtone
mode crystals require a tank circuit to attenuate the
gain at the fundamental frequency. Figure 14-3 shows
an example of this.
TABLE 14-1: CONFIGURATION
LOCATIONS
Bit
Address
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
FE00h
FE01h
FE02h
FE03h
FE04h
FE06h
FIGURE 14-2: CRYSTAL OR CERAMIC
RESONATOR OPERATION
(XT OR LF OSC
CONFIGURATION)
OSC1
PM1
C1
(1)
(1)
PM2
FE0Fh
XTAL
SLEEP
Note 1: This location does not exist on the
PIC17C42.
RF
OSC2
Note1
To internal
logic
C2
Note: When programming the desired configura-
tion locations, they must be programmed in
ascending order. Starting with address
FE00h.
PIC17CXX
See Table 14-2 and Table 14-3 for recommended
values of C1 and C2.
Note 1: A series resistor may be required for AT strip
cut crystals.
DS30412C-page 100
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 14-3: CRYSTAL OPERATION,
OVERTONE CRYSTALS (XT
OSC CONFIGURATION)
TABLE 14-3: CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
Osc
Freq
C1
C2
C1
Type
OSC1
(1)
LF
32 kHz
100-150 pF
10-33 pF
10-33 pF
100-150 pF
10-33 pF
10-33 pF
1 MHz
2 MHz
SLEEP
C2
OSC2
XT
2 MHz
4 MHz
8 MHz
16 MHz
25 MHz
47-100 pF
15-68 pF
15-47 pF
TBD
47-100 pF
15-68 pF
15-47 pF
TBD
(2)
PIC17C42
0.1 µF
15-47 pF
15-47 pF
To filter the fundamental frequency
1
(3)
(3)
(3)
32 MHz
0
0
(2πf)2
=
LC2
Higher capacitance increases the stability of the
oscillator but also increases the start-up time and the
oscillator current. These values are for design guid-
ance only. RS may be required in XT mode to avoid
overdriving the crystals with low drive level specifica-
tion. Since each crystal has its own characteristics,
the user should consult the crystal manufacturer for
appropriate values for external components.
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recom-
mended.
Where f = tank circuit resonant frequency. This should be
midway between the fundamental and the 3rd overtone
frequencies of the crystal.
TABLE 14-2: CAPACITOR SELECTION
FOR CERAMIC
RESONATORS
Oscillator
Type
Resonator
Frequency
Capacitor Range
C1 = C2
2: RS of 330Ω is required for a capacitor com-
LF
455 kHz
2.0 MHz
15 - 68 pF
10 - 33 pF
bination of 15/15 pF.
3: Only the capacitance of the board was present.
XT
4.0 MHz
8.0 MHz
16.0 MHz
22 - 68 pF
33 - 100 pF
33 - 100 pF
Crystals Used:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
1.0 MHz
2.0 MHz
4.0 MHz
8.0 MHz
ECS-10-13-1
ECS-20-20-1
ECS-40-20-1
± 50 PPM
± 50 PPM
± 50 PPM
± 50 PPM
Higher capacitance increases the stability of the
oscillator but also increases the start-up time. These
values are for design guidance only. Since each reso-
nator has its own characteristics, the user should
consult the resonator manufacturer for appropriate
values of external components.
ECS ECS-80-S-4
ECS-80-18-1
16.0 MHz
25 MHz
32 MHz
ECS-160-20-1
CTS CTS25M
CRYSTEK HF-2
TBD
Resonators Used:
± 50 PPM
± 50 PPM
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
14.2.3 EXTERNAL CLOCK OSCILLATOR
In the EC oscillator mode, the OSC1 input can be
driven by CMOS drivers. In this mode, the
OSC1/CLKIN pin is hi-impedance and the OSC2/CLK-
OUT pin is the CLKOUT output (4 TOSC).
16.0 MHz Murata Erie CSA16.00MX
Resonators used did not have built-in capacitors.
FIGURE 14-4: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC17CXX
CLKOUT
(FOSC/4)
1996 Microchip Technology Inc.
DS30412C-page 101
PIC17C4X
14.2.4 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
14.2.5 RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. RC oscillator fre-
quency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operating
temperature. In addition to this, oscillator frequency will
vary from unit to unit due to normal process parameter
variation. Furthermore, the difference in lead frame
capacitance between package types will also affect
oscillation frequency, especially for low Cext values.
The user also needs to take into account variation due
to tolerance of external R and C components used.
Figure 14-6 shows how the R/C combination is con-
nected to the PIC17CXX. For Rext values below 2.2 kΩ,
the oscillator operation may become unstable, or stop
completely. For very high Rext values (e.g. 1 MΩ), the
oscillator becomes sensitive to noise, humidity and
leakage.Thus, we recommend to keep Rext between 3
kΩ and 100 kΩ.
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepack-
aged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates.Two types of
crystal oscillator circuits can be used: one with series
resonance, or one with parallel resonance.
Figure 14-5 shows implementation of a parallel reso-
nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a par-
allel oscillator requires.The 4.7 kΩ resistor provides the
negative feedback for stability.The 10 kΩ potentiometer
biases the 74AS04 in the linear region. This could be
used for external oscillator designs.
FIGURE 14-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, oscillation frequency can
vary dramatically due to changes in external capaci-
tances, such as PCB trace capacitance or package
lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
PIC17CXX
4.7k
OSC1
74AS04
See Section 18.0 for RC frequency variation from part
to part due to normal process variation. The variation
is larger for larger R (since leakage current variation will
affect RC frequency more for large R) and for smaller C
(since variation of input capacitance will affect RC fre-
quency more).
10k
XTAL
10k
See Section 18.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values as well as fre-
quency variation due to operating temperature for given
R, C, and VDD values.
20 pF
20 pF
Figure 14-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental fre-
quency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 kΩ resistors provide the negative feed-
back to bias the inverters in their linear region.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (see Figure 3-2 for
waveform).
FIGURE 14-7: RC OSCILLATOR MODE
FIGURE 14-6: EXTERNAL SERIES
RESONANT CRYSTAL
VDD
OSCILLATOR CIRCUIT
Rext
Internal
clock
OSC1
To Other
Devices
330 kΩ
330 kΩ
PIC17CXX
Cext
VSS
74AS04
74AS04
74AS04
PIC17CXX
OSC2/CLKOUT
OSC1
Fosc/4
0.1 µF
XTAL
DS30412C-page 102
1996 Microchip Technology Inc.
PIC17C4X
14.3.2 CLEARING THE WDT AND POSTSCALER
The WDT and postscaler are cleared when:
14.3
Watchdog Timer (WDT)
The Watchdog Timer’s function is to recover from soft-
ware malfunction. The WDT uses an internal free run-
ning on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1/CLKIN and OSC2/CLK-
OUT pins of the device has been stopped, for example,
by execution of a SLEEP instruction. During normal
operation and SLEEP mode, a WDT time-out gener-
ates a device RESET. The WDT can be permanently
disabled by programming the configuration bits
WDTPS1:WDTPS0 as '00' (Section 14.1).
• The device is in the reset state
• A SLEEPinstruction is executed
• A CLRWDTinstruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the reset state.
14.3.3 WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
Under normal operation, the WDT must be cleared on
a regular interval. This time is less the minimum WDT
overflow time. Not clearing the WDT in this time frame
will cause the WDT to overflow and reset the device.
The WDT and postscaler is the Power-up Timer during
the Power-on Reset sequence.
14.3.4 WDT AS NORMAL TIMER
14.3.1 WDT PERIOD
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 TOSC cycles. On overflow, the TO bit
is cleared (device is not reset). The CLRWDTinstruction
can be used to set the TO bit. This allows the WDT to
be a simple overflow timer. When in sleep, the WDT
does not increment.
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1). The time-out periods vary with temper-
DD
ature, V and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
postscaler with a division ratio of up to 1:256 can be
assigned to the WDT. Thus, typical time-out periods up
to 3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out thus generating a device RESET
condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
1996 Microchip Technology Inc.
DS30412C-page 103
PIC17C4X
FIGURE 14-8: WATCHDOG TIMER BLOCK DIAGRAM
Postscaler
On-chip RC
Oscillator
WDT
(1)
WDTPS1:WDTPS0
4 - to - 1 MUX
WDT Overflow
WDT Enable
Note 1: This oscillator is separate from the external
RC oscillator on the OSC1 pin.
TABLE 14-4: REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
Config
—
—
PM1
—
—
PM0
WDTPS1 WDTPS0 FOSC1
TO PD
FOSC0
—
(Note 2)
(Note 2)
06h, Unbanked CPUSTA
STKAV
GLINTD
—
--11 11-- --11 qq--
Legend: -= unimplemented read as '0', q- value depends on condition, shaded cells are not used by the WDT.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
2: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
DS30412C-page 104
1996 Microchip Technology Inc.
PIC17C4X
PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The TO bit is cleared if WDT
time-out occurred (and caused wake-up).
14.4
Power-down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEPinstruction.This clears the Watchdog Timer and
postscaler (if enabled). The PD bit is cleared and the
TO bit is set (in the CPUSTA register). In SLEEP mode,
the oscillator driver is turned off.The I/O ports maintain
their status (driving high, low, or hi-impedance).
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GLINTD bit. If the GLINTD
bit is set (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the
GLINTD bit is clear (enabled), the device executes the
instruction after the SLEEP instruction and then
branches to the interrupt vector address. In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEPinstruction.
The MCLR/VPP pin must be at a logic high level
(VIHMC). A WDT time-out RESET does not drive the
MCLR/VPP pin low.
14.4.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
• A POR reset
Note: If the global interrupts are disabled
(GLINTD is set), but any interrupt source
has both its interrupt enable bit and the cor-
responding interrupt flag bits set, the
device will immediately wake-up from
sleep. The TO bit is set, and the PD bit is
cleared.
• External reset input on MCLR/VPP pin
• WDT Reset (if WDT was enabled)
• Interrupt from RA0/INT pin, RB port change,
T0CKI interrupt, or some Peripheral Interrupts
The following peripheral interrupts can wake-up from
SLEEP:
• Capture1 interrupt
The WDT is cleared when the device wake from
SLEEP, regardless of the source of wake-up.
• Capture2 interrupt
• USART synchronous slave transmit interrupt
• USART synchronous slave receive interrupt
14.4.1.1 WAKE-UP DELAY
When the oscillator type is configured in XT or LF
mode, the Oscillator Start-up Timer (OST) is activated
on wake-up. The OST will keep the device in reset for
1024TOSC. This needs to be taken into account when
considering the interrupt response time when coming
out of SLEEP.
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
Any reset event will cause a device reset. Any interrupt
event is considered a continuation of program execu-
tion. The TO and PD bits in the CPUSTA register can
be used to determine the cause of device reset. The
FIGURE 14-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Tost(2)
CLKOUT(4)
INT
(RA0/INT pin)
Interrupt Latency (2)
INTF flag
GLINTD bit
Processor
in SLEEP
INSTRUCTION FLOW
0004h
PC
PC+1
PC+2
0005h
PC
Instruction
Inst (PC) = SLEEP
Inst (PC-1)
Inst (PC+1)
SLEEP
Inst (PC+2)
Inst (PC+1)
fetched
Instruction
executed
Dummy Cycle
Note 1: XT or LF oscillator mode assumed.
2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.
3: When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
1996 Microchip Technology Inc.
DS30412C-page 105
PIC17C4X
14.4.2 MINIMIZING CURRENT CONSUMPTION
14.5
Code Protection
To minimize current consumption, all I/O pins should be
either at VDD, or VSS, with no external circuitry drawing
current from the I/O pin. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should be at VDD or VSS.The contributions
from on-chip pull-ups on PORTB should also be con-
sidered, and disabled when possible.
The code in the program memory can be protected by
selecting the microcontroller in code protected mode
(PM2:PM0 = '000').
Note: PM2 does not exist on the PIC17C42. To
select code protected microcontroller
mode, PM1:PM0 = '00'.
In this mode, instructions that are in the on-chip pro-
gram memory space, can continue to read or write the
program memory. An instruction that is executed out-
side of the internal program memory range will be inhib-
ited from writing to or reading from program memory.
Note: Microchip does not recommend code pro-
tecting windowed devices.
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
DS30412C-page 106
1996 Microchip Technology Inc.
PIC17C4X
TABLE 15-1: OPCODE FIELD
15.0 INSTRUCTION SET SUMMARY
DESCRIPTIONS
The PIC17CXX instruction set consists of 58 instruc-
tions. Each instruction is a 16-bit word divided into an
OPCODE and one or more operands. The opcode
specifies the instruction type, while the operand(s) fur-
ther specify the operation of the instruction. The
PIC17CXX instruction set can be grouped into three
types:
Field
Description
f
p
i
Register file address (00h to FFh)
Peripheral register file address (00h to 1Fh)
Table pointer control i = '0' (do not change)
i = '1' (increment after instruction execution)
t
Table byte select t = '0' (perform operation on lower
byte)
t = '1' (perform operation on upper byte literal field,
constant data)
• byte-oriented
• bit-oriented
• literal and control operations.
These formats are shown in Figure 15-1.
WREG Working register (accumulator)
b
k
x
Bit address within an 8-bit file register
Literal field, constant data or label
Table 15-1 shows the field descriptions for the
opcodes. These descriptions are useful for under-
standing the opcodes in Table 15-2 and in each spe-
cific instruction descriptions.
Don't care location (= '0' or '1')
The assembler will generate code with x = '0'. It is
the recommended form of use for compatibility with
all Microchip software tools.
byte-oriented instructions, 'f' represents a file regis-
ter designator and 'd' represents a destination designa-
tor. The file register designator specifies which file
register is to be used by the instruction.
d
Destination select
0 = store result in WREG
1 = store result in file register f
Default is d = '1'
The destination designator specifies where the result of
the operation is to be placed. If 'd' = '0', the result is
placed in the WREG register. If 'd' = '1', the result is
placed in the file register specified by the instruction.
u
s
Unused, encoded as '0'
Destination select
0 = store result in file register f and in the WREG
1 = store result in file register f
Default is s = '1'
bit-oriented instructions, 'b' represents a bit field des-
ignator which selects the number of the bit affected by
the operation, while 'f' represents the number of the file
in which the bit is located.
label Label name
C,DC, ALU status bits Carry, Digit Carry, Zero, Overflow
Z,OV
literal and control operations, 'k' represents an 8- or
11-bit constant or literal value.
GLINTD Global Interrupt Disable bit (CPUSTA<4>)
TBLPTR Table Pointer (16-bit)
The instruction set is highly orthogonal and is grouped
into:
TBLAT Table Latch (16-bit) consists of high byte (TBLATH)
and low byte (TBLATL)
• byte-oriented operations
• bit-oriented operations
• literal and control operations
TBLATL Table Latch low byte
TBLATH Table Latch high byte
TOS Top of Stack
All instructions are executed within one single instruc-
tion cycle, unless:
PC
Program Counter
BSR Bank Select Register
• a conditional test is true
• the program counter is changed as a result of an
instruction
• a table read or a table write instruction is exe-
cuted (in this case, the execution takes two
instruction cycles with the second cycle executed
as a NOP)
WDT Watchdog Timer Counter
TO
PD
Time-out bit
Power-down bit
dest Destination either the WREG register or the speci-
fied register file location
[ ]
( )
→
Options
Contents
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 25 MHz, the normal
instruction execution time is 160 ns. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 320 ns.
Assigned to
Register bit field
In the set of
< >
User defined term (font is courier)
italics
1996 Microchip Technology Inc.
DS30412C-page 107
PIC17C4X
Table 15-2 lists the instructions recognized by the
MPASM assembler.
15.1
Special Function Registers as
Source/Destination
Note 1: Any unused opcode is Reserved. Use of
any reserved opcode may cause unex-
pected operation.
The PIC17C4X’s orthogonal instruction set allows read
and write of all file registers, including special function
registers. There are some special situations the user
should be aware of:
Note 2: The shaded instructions are not available
in the PIC17C42
15.1.1 ALUSTA AS DESTINATION
All instruction examples use the following format to rep-
resent a hexadecimal number:
If an instruction writes to ALUSTA, the Z, C, DC and OV
bits may be set or cleared as a result of the instruction
and overwrite the original data bits written. For exam-
0xhh
where h signifies a hexadecimal digit.
To represent a binary number:
0000 0100b
ple, executing CLRF
ALUSTA will clear register
ALUSTA, and then set the Z bit leaving 0000 0100bin
the register.
where b signifies a binary string.
15.1.2 PCL AS SOURCE OR DESTINATION
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Read, write or read-modify-write on PCL may have the
following results:
Byte-oriented file register operations
Read PC:
PCH → PCLATH; PCL → dest
15
9
8
7
0
Write PCL:
PCLATH → PCH;
8-bit destination value → PCL
OPCODE
d
f (FILE #)
d = 0 for destination WREG
d = 1 for destination f
f = 8-bit file register address
Read-Modify-Write: PCL→ ALU operand
PCLATH → PCH;
8-bit result → PCL
Byte to Byte move operations
15 13 12
OPCODE p (FILE #)
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
8
7
0
0
f (FILE #)
p = peripheral register file address
f = 8-bit file register address
15.1.3 BIT MANIPULATION
All bit manipulation instructions are done by first read-
ing the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
should keep this in mind when operating on special
function registers, such as ports.
Bit-oriented file register operations
15 11 10
b (BIT #)
8
7
OPCODE
f (FILE #)
b = 3-bit address
f = 8-bit file register address
Literal and control operations
15
8
7
0
0
OPCODE
k (literal)
k = 8-bit immediate value
Call and GOTO operations
15 13 12
OPCODE
k (literal)
k = 13-bit immediate value
DS30412C-page 108
1996 Microchip Technology Inc.
PIC17C4X
The 4 Q cycles that make up an instruction cycle (Tcy)
can be generalized as:
15.2
Q Cycle Activity
Each instruction cycle (Tcy) is comprised of four Q
cycles (Q1-Q4). The Q cycles provide the timing/desig-
nation for the Decode, Read, Execute, Write etc., of
each instruction cycle. The following diagram shows
the relationship of the Q cycles to the instruction cycle.
Q1: Instruction Decode Cycle or forced NOP
Q2: Instruction Read Cycle or NOP
Q3: Instruction Execute
Q4: Instruction Write Cycle or NOP
Each instruction will show the detailed Q cycle opera-
tion for the instruction.
FIGURE 15-2: Q CYCLE ACTIVITY
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Tosc
Tcy1
Tcy2
Tcy3
1996 Microchip Technology Inc.
DS30412C-page 109
PIC17C4X
TABLE 15-2: PIC17CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
f,d
f,d
f,d
f,s
f,d
f
ADD WREG to f
1
1
1
1
1
0000 111d ffff ffff
0001 000d ffff ffff
0000 101d ffff ffff
0010 100s ffff ffff
0001 001d ffff ffff
OV,C,DC,Z
ADD WREG and Carry bit to f
AND WREG with f
OV,C,DC,Z
Z
None
Z
Clear f, or Clear f and Clear WREG
Complement f
3
COMF
CPFSEQ
CPFSGT
CPFSLT
DAW
Compare f with WREG, skip if f = WREG
Compare f with WREG, skip if f > WREG
Compare f with WREG, skip if f < WREG
Decimal Adjust WREG Register
Decrement f
1 (2) 0011 0001 ffff ffff
1 (2) 0011 0010 ffff ffff
1 (2) 0011 0000 ffff ffff
None 6,8
f
None 2,6,8
None 2,6,8
f
f,s
f,d
f,d
f,d
f,d
f,d
f,d
f,d
f,p
p,f
f
1
1
0010 111s ffff ffff
0000 011d ffff ffff
C
3
DECF
OV,C,DC,Z
DECFSZ
DCFSNZ
INCF
Decrement f, skip if 0
Decrement f, skip if not 0
Increment f
1 (2) 0001 011d ffff ffff
1 (2) 0010 011d ffff ffff
None 6,8
None 6,8
1
0001 010d ffff ffff
OV,C,DC,Z
INCFSZ
INFSNZ
IORWF
MOVFP
MOVPF
MOVWF
MULWF
NEGW
NOP
Increment f, skip if 0
Increment f, skip if not 0
Inclusive OR WREG with f
Move f to p
1 (2) 0001 111d ffff ffff
1 (2) 0010 010d ffff ffff
None 6,8
None 6,8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000 100d ffff ffff
011p pppp ffff ffff
010p pppp ffff ffff
0000 0001 ffff ffff
0011 0100 ffff ffff
0010 110s ffff ffff
0000 0000 0000 0000
0001 101d ffff ffff
0010 001d ffff ffff
0001 100d ffff ffff
0010 000d ffff ffff
0010 101s ffff ffff
0000 010d ffff ffff
0000 001d ffff ffff
0001 110d ffff ffff
Z
None
Z
Move p to f
Move WREG to f
None
f
Multiply WREG with f
Negate WREG
None
9
f,s
—
f,d
f,d
f,d
f,d
f,s
f,d
f,d
f,d
OV,C,DC,Z 1,3
No Operation
None
C
RLCF
Rotate left f through Carry
Rotate left f (no carry)
Rotate right f through Carry
Rotate right f (no carry)
Set f
RLNCF
RRCF
None
C
RRNCF
SETF
None
None
OV,C,DC,Z
OV,C,DC,Z
None
3
1
1
SUBWF
SUBWFB
SWAPF
TABLRD
Subtract WREG from f
Subtract WREG from f with Borrow
Swap f
t,i,f Table Read
2 (3) 1010 10ti ffff ffff
None
7
Legend: Refer to Table 15-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working
register (WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC andkkkk kkkkis loaded into
the LSB of the PC (PCL)
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruc-
tion is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruc-
tion.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRDto PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
9: These instructions are not available on the PIC17C42.
DS30412C-page 110
1996 Microchip Technology Inc.
PIC17C4X
TABLE 15-2: PIC17CXX INSTRUCTION SET (Cont.’d)
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
Affected
Notes
MSb
LSb
TABLWT
TLRD
t,i,f Table Write
2
1
1
1010 11ti ffff ffff
1010 00tx ffff ffff
1010 01tx ffff ffff
None
5
t,f
t,f
f
Table Latch Read
None
None
TLWT
Table Latch Write
TSTFSZ
XORWF
Test f, skip if 0
1 (2) 0011 0011 ffff ffff
None 6,8
Z
f,d
Exclusive OR WREG with f
1
0000 110d ffff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f,b
f,b
f,b
f,b
f,b
Bit Clear f
1
1
1000 1bbb ffff ffff
1000 0bbb ffff ffff
None
BSF
Bit Set f
None
BTFSC
BTFSS
BTG
Bit test, skip if clear
Bit test, skip if set
Bit Toggle f
1 (2) 1001 1bbb ffff ffff
1 (2) 1001 0bbb ffff ffff
None 6,8
None 6,8
None
1
0011 1bbb ffff ffff
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
k
ADD literal to WREG
1
1
2
1
2
1
2
1
1
1
1
2
2
2
1
1
1
1011 0001 kkkk kkkk
1011 0101 kkkk kkkk
111k kkkk kkkk kkkk
0000 0000 0000 0100
110k kkkk kkkk kkkk
1011 0011 kkkk kkkk
1011 0111 kkkk kkkk
1011 1000 uuuu kkkk
1011 101x kkkk uuuu
1011 0000 kkkk kkkk
1011 1100 kkkk kkkk
0000 0000 0000 0101
1011 0110 kkkk kkkk
0000 0000 0000 0010
0000 0000 0000 0011
1011 0010 kkkk kkkk
1011 0100 kkkk kkkk
OV,C,DC,Z
k
AND literal with WREG
Subroutine Call
Z
None
TO,PD
None
Z
k
7
7
CLRWDT
GOTO
—
k
Clear Watchdog Timer
Unconditional Branch
IORLW
LCALL
MOVLB
MOVLR
MOVLW
MULLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
Inclusive OR literal with WREG
Long Call
k
None 4,7
None
k
Move literal to low nibble in BSR
Move literal to high nibble in BSR
Move literal to WREG
k
None
None
9
k
k
Multiply literal with WREG
Return from interrupt (and enable interrupts)
Return literal to WREG
Return from subroutine
Enter SLEEP Mode
None
9
7
7
7
—
k
GLINTD
None
—
—
k
None
TO, PD
OV,C,DC,Z
Z
Subtract WREG from literal
Exclusive OR literal with WREG
k
Legend: Refer to Table 15-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working
register (WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC andkkkk kkkkis loaded into
the LSB of the PC (PCL)
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruc-
tion is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruc-
tion.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRDto PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
9: These instructions are not available on the PIC17C42.
1996 Microchip Technology Inc.
DS30412C-page 111
PIC17C4X
ADDLW
ADD Literal to WREG
ADDWF
Syntax:
ADD WREG to f
[ label ] ADDWF f,d
0 ≤ f ≤ 255
Syntax:
[ label ] ADDLW
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
d
[0,1]
(WREG) + k → (WREG)
Operation:
(WREG) + (f) → (dest)
OV, C, DC, Z
Status Affected:
Encoding:
OV, C, DC, Z
1011
0001
kkkk
kkkk
0000
111d
ffff
ffff
The contents of WREG are added to the
8-bit literal 'k' and the result is placed in
WREG.
Add WREG to register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Execute
Write to
WREG
literal 'k'
Decode
Read
Execute
Write to
register 'f'
destination
ADDLW
0x15
Example:
ADDWF
REG, 0
Example:
Before Instruction
WREG = 0x10
Before Instruction
WREG
REG
=
=
0x17
0xC2
After Instruction
WREG = 0x25
After Instruction
WREG
REG
=
=
0xD9
0xC2
DS30412C-page 112
1996 Microchip Technology Inc.
PIC17C4X
ADDWFC
Syntax:
ADD WREG and Carry bit to f
[ label ] ADDWFC f,d
0 ≤ f ≤ 255
ANDLW
And Literal with WREG
Syntax:
[ label ] ANDLW
k
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
d
[0,1]
(WREG) .AND. (k) → (WREG)
Operation:
(WREG) + (f) + C → (dest)
Z
Status Affected:
Encoding:
OV, C, DC, Z
1011
0101
kkkk
kkkk
0001
000d
ffff
ffff
The contents of WREG are AND’ed with
the 8-bit literal 'k'.The result is placed in
WREG.
Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result is
placed in data memory location 'f'.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
'k'
Execute
Write to
WREG
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write to
destination
ANDLW
0x5F
Example:
Before Instruction
ADDWFC
REG
0
Example:
WREG
=
0xA3
0x03
Before Instruction
After Instruction
Carry bit =
1
WREG
=
REG
WREG
=
=
0x02
0x4D
After Instruction
Carry bit =
0
REG
WREG
=
=
0x02
0x50
1996 Microchip Technology Inc.
DS30412C-page 113
PIC17C4X
ANDWF
Syntax:
AND WREG with f
BCF
Bit Clear f
[ label ] ANDWF f,d
Syntax:
Operands:
[ label ] BCF f,b
Operands:
0 ≤ f ≤ 255
0 ≤ f ≤ 255
0 ≤ b ≤ 7
d
[0,1]
Operation:
(WREG) .AND. (f) → (dest)
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Status Affected:
Encoding:
Z
None
0000
101d
ffff
ffff
1000
1bbb
ffff
ffff
The contents of WREG are AND’ed with
register 'f'. If 'd' is 0 the result is stored
in WREG. If 'd' is 1 the result is stored
back in register 'f'.
Bit 'b' in register 'f' is cleared.
Description:
1
1
Cycles:
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write
register 'f'
Q Cycle Activity:
Q1
Q2
Q3
Q4
BCF
FLAG_REG,
7
Example:
Decode
Read
Execute
Write to
register 'f'
destination
Before Instruction
FLAG_REG = 0xC7
ANDWF
REG, 1
Example:
After Instruction
Before Instruction
FLAG_REG = 0x47
WREG
=
0x17
0xC2
REG
=
After Instruction
WREG
REG
=
=
0x17
0x02
DS30412C-page 114
1996 Microchip Technology Inc.
PIC17C4X
BSF
Bit Set f
BTFSC
Bit Test, skip if Clear
Syntax:
Operands:
[ label ] BSF f,b
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 255
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
1000
0bbb
ffff
ffff
1001
1bbb
ffff
ffff
Bit 'b' in register 'f' is set.
If bit 'b' in register ’f' is 0 then the next
instruction is skipped.
Description:
1
1
If bit 'b' is 0 then the next instruction
fetched during the current instruction exe-
cution is discarded, and a NOPis exe-
cuted instead, making this a two-cycle
instruction.
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write
register 'f'
Words:
Cycles:
1
1(2)
BSF
FLAG_REG, 7
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
FLAG_REG= 0x0A
Decode
Read
Execute
NOP
After Instruction
register 'f'
FLAG_REG= 0x8A
If skip:
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
HERE
FALSE
TRUE
BTFSC
:
:
FLAG,1
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
If FLAG<1>
PC
1996 Microchip Technology Inc.
DS30412C-page 115
PIC17C4X
BTFSS
Bit Test, skip if Set
BTG
Bit Toggle f
Syntax:
[ label ] BTFSS f,b
Syntax:
Operands:
[ label ] BTG f,b
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
0 ≤ f ≤ 255
0 ≤ b < 7
Operation:
skip if (f<b>) = 1
None
Operation:
(f<b>) → (f<b>)
Status Affected:
Encoding:
Status Affected:
Encoding:
None
1001
0bbb
ffff
ffff
0011
1bbb
ffff
ffff
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
Bit 'b' in data memory location 'f' is
inverted.
Description:
Description:
If bit 'b' is 1, then the next instruction
fetched during the current instruction exe-
cution, is discarded and an NOPis exe-
cuted instead, making this a two-cycle
instruction.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
Execute
Write
register 'f'
register 'f'
1(2)
Q Cycle Activity:
Q1
BTG
PORTC,
4
Example:
Q2
Q3
Q4
Before Instruction:
Decode
Read
Execute
NOP
PORTC
=
0111 0101[0x75]
register 'f'
After Instruction:
If skip:
Q1
PORTC
=
0110 0101[0x65]
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
HERE
FALSE
TRUE
BTFSS
:
:
FLAG,1
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
If FLAG<1>
PC
DS30412C-page 116
1996 Microchip Technology Inc.
PIC17C4X
CALL
Subroutine Call
[ label ] CALL k
0 ≤ k ≤ 4095
CLRF
Clear f
Syntax:
Syntax:
[label] CLRF f,s
Operands:
Operation:
Operands:
Operation:
0 ≤ f ≤ 255
PC+ 1→ TOS, k → PC<12:0>,
k<12:8> → PCLATH<4:0>;
PC<15:13> → PCLATH<7:5>
00h → f, s [0,1]
00h → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
100s
ffff
ffff
111k
kkkk
kkkk
kkkk
Clears the contents of the specified reg-
ister(s).
s = 0: Data memory location 'f' and
WREG are cleared.
s = 1: Data memory location 'f' is
cleared.
Description:
Subroutine call within 8K page. First,
return address (PC+1) is pushed onto
the stack.The 13-bit value is loaded into
PC bits<12:0>. Then the upper-eight
bits of the PC are copied into PCLATH.
Callis a two-cycle instruction.
Description:
Words:
Cycles:
1
1
See LCALLfor calls outside 8K memory
space.
Q Cycle Activity:
Q1
Words:
Cycles:
1
2
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write
Q Cycle Activity:
Q1
register 'f'
and other
specified
register
Q2
Q3
Q4
Decode
Read literal
'k'<7:0>
Execute
NOP
Forced NOP
Example:
NOP
Execute
NOP
CLRF
FLAG_REG
Example:
Before Instruction
HERE
CALL THERE
FLAG_REG
=
=
0x5A
0x00
Before Instruction
After Instruction
FLAG_REG
PC
=
Address(HERE)
After Instruction
PC
=
Address(THERE)
TOS =
Address (HERE + 1)
1996 Microchip Technology Inc.
DS30412C-page 117
PIC17C4X
CLRWDT
Syntax:
Clear Watchdog Timer
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 255
[ label ] CLRWDT
None
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
00h → WDT
0 → WDT postscaler,
1 → TO
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
1 → PD
0001
001d
ffff
ffff
Status Affected:
Encoding:
TO, PD
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
Description:
0000
0000
0000
0100
CLRWDTinstruction resets the watchdog
timer. It also resets the prescaler of the
WDT. Status bits TO and PD are set.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Execute
Write
register 'f'
register 'f'
Decode
Read
Execute
NOP
register
ALUSTA
COMF
REG1,0
Example:
Before Instruction
CLRWDT
Example:
REG1
=
0x13
Before Instruction
After Instruction
WDT counter
=
?
REG1
=
0x13
WREG
=
0xEC
After Instruction
WDT counter
WDT Postscaler
TO
=
=
=
=
0x00
0
1
1
PD
DS30412C-page 118
1996 Microchip Technology Inc.
PIC17C4X
Compare f with WREG,
skip if f = WREG
Compare f with WREG,
CPFSEQ
CPFSGT
skip if f > WREG
[ label ] CPFSGT
0 ≤ f ≤ 255
Syntax:
[ label ] CPFSEQ
f
Syntax:
f
Operands:
Operation:
0 ≤ f ≤ 255
Operands:
Operation:
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
(f) − (WREG),
skip if (f) > (WREG)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
0010
ffff
ffff
0011
0001
ffff
ffff
Compares the contents of data memory
location 'f' to the contents of the WREG
by performing an unsigned subtraction.
Description:
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
Description:
If the contents of 'f' > the contents of
WREG then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruc-
tion.
If 'f' = WREG then the fetched instruc-
tion is discarded and an NOP is exe-
cuted instead making this a two-cycle
instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1 (2)
1 (2)
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Execute
NOP
Decode
Read
Execute
NOP
register 'f'
register 'f'
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Forced NOP
NOP
Execute
NOP
HERE
NEQUAL
EQUAL
CPFSEQ REG
:
:
Example:
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Example:
Before Instruction
Before Instruction
PC Address
=
=
=
HERE
PC
WREG
=
=
Address (HERE)
WREG
REG
?
?
?
After Instruction
After Instruction
If REG
>
=
≤
WREG;
Address (GREATER)
WREG;
If REG
=
=
≠
=
WREG;
Address (EQUAL)
WREG;
PC
If REG
PC
PC
If REG
PC
=
Address (NGREATER)
Address (NEQUAL)
1996 Microchip Technology Inc.
DS30412C-page 119
PIC17C4X
Compare f with WREG,
DAW
Decimal Adjust WREG Register
[label] DAW f,s
CPFSLT
skip if f < WREG
[ label ] CPFSLT
0 ≤ f ≤ 255
Syntax:
Operands:
Syntax:
f
0 ≤ f ≤ 255
Operands:
Operation:
s
[0,1]
(f) – (WREG),
skip if (f) < (WREG)
(unsigned comparison)
If [WREG<3:0> >9] .OR. [DC = 1] then
WREG<3:0> + 6 → f<3:0>, s<3:0>;
else
Operation:
WREG<3:0> → f<3:0>, s<3:0>;
Status Affected:
Encoding:
None
If [WREG<7:4> >9] .OR. [C = 1] then
WREG<7:4> + 6 → f<7:4>, s<7:4>
else
0011
0000
ffff
ffff
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
Description:
WREG<7:4> → f<7:4>, s<7:4>
Status Affected:
Encoding:
C
If the contents of 'f' < the contents of
WREG, then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruc-
tion.
0010
111s
ffff
ffff
DAW adjusts the eight bit value in
WREG resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
Description:
Words:
Cycles:
1
1 (2)
s = 0: Result is placed in Data
memory location 'f' and
Q Cycle Activity:
Q1
WREG.
Q2
Q3
Q4
s = 1: Result is placed in Data
memory location 'f'.
Decode
Read
register 'f'
Execute
NOP
Words:
Cycles:
1
1
If skip:
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Q Cycle Activity:
Q1
Q2
Q3
Q4
HERE
NLESS
LESS
CPFSLT REG
Example:
Decode
Read
Execute
Write
:
:
register 'f'
register 'f'
and other
specified
register
Before Instruction
PC
W
=
=
Address (HERE)
?
DAW
REG1, 0
Example1:
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
WREG;
Address (LESS)
WREG;
Before Instruction
WREG
REG1
C
=
=
=
=
0xA5
??
0
Address (NLESS)
DC
0
After Instruction
WREG
REG1
C
=
=
=
=
0x05
0x05
1
DC
0
Example 2:
Before Instruction
WREG
REG1
C
=
=
=
=
0xCE
??
0
DC
0
After Instruction
WREG
REG1
C
=
=
=
=
0x24
0x24
1
DC
0
DS30412C-page 120
1996 Microchip Technology Inc.
PIC17C4X
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 255
DECFSZ
Syntax:
Decrement f, skip if 0
Syntax:
Operands:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 255
d
[0,1]
d
[0,1]
Operation:
(f) – 1 → (dest)
Operation:
(f) – 1 → (dest);
skip if result = 0
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
None
0000
011d
ffff
ffff
0001
011d
ffff
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Description:
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Words:
Cycles:
1
1
If the result is 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead mak-
ing it a two-cycle instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
Execute
Write to
Words:
Cycles:
1
register 'f'
destination
1(2)
DECF
CNT,
1
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
CNT
=
0x01
0
Z
=
Decode
Read
Execute
Write to
register 'f'
destination
After Instruction
CNT
Z
=
=
0x00
1
HERE
DECFSZ
GOTO
CNT, 1
LOOP
Example:
CONTINUE
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+1)
1996 Microchip Technology Inc.
DS30412C-page 121
PIC17C4X
DCFSNZ
Syntax:
Decrement f, skip if not 0
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 8191
[label] DCFSNZ f,d
Syntax:
Operands:
0 ≤ f ≤ 255
Operands:
Operation:
d
[0,1]
k → PC<12:0>;
Operation:
(f) – 1 → (dest);
skip if not 0
k<12:8> → PCLATH<4:0>,
PC<15:13> → PCLATH<7:5>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
011d
ffff
ffff
110k
kkkk
kkkk
kkkk
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
GOTOallows an unconditional branch
anywhere within an 8K page boundary.
The thirteen bit immediate value is
loaded into PC bits <12:0>. Then the
upper eight bits of PC are loaded into
PCLATH. GOTOis always a two-cycle
instruction.
Description:
Description:
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead mak-
ing it a two-cycle instruction.
Words:
Cycles:
1
2
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'k'<7:0>
Execute
NOP
Decode
Read
Execute
Write to
register 'f'
destination
Forced NOP
Example:
NOP
Execute
NOP
If skip:
Q1
GOTO THERE
Q2
Q3
Q4
After Instruction
Forced NOP
NOP
Execute
NOP
PC
=
Address (THERE)
HERE
ZERO
NZERO
DCFSNZ TEMP, 1
:
:
Example:
Before Instruction
TEMP_VALUE
=
?
After Instruction
TEMP_VALUE
If TEMP_VALUE
PC
=
=
=
≠
=
TEMP_VALUE - 1,
0;
Address (ZERO)
0;
Address (NZERO)
If TEMP_VALUE
PC
DS30412C-page 122
1996 Microchip Technology Inc.
PIC17C4X
INCF
Increment f
INCFSZ
Syntax:
Increment f, skip if 0
Syntax:
Operands:
[ label ] INCF f,d
[ label ] INCFSZ f,d
0 ≤ f ≤ 255
Operands:
0 ≤ f ≤ 255
d
[0,1]
d
[0,1]
Operation:
(f) + 1 → (dest)
Operation:
(f) + 1 → (dest)
skip if result = 0
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
None
0001
010d
ffff
ffff
0001
111d
ffff
ffff
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Words:
Cycles:
1
1
If the result is 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making
it a two-cycle instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register 'f'
Execute
Write to
destination
1(2)
INCF
CNT, 1
Example:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Before Instruction
CNT
=
0xFF
Decode
Read
Execute
Write to
Z
C
=
=
0
?
register 'f'
destination
If skip:
Q1
After Instruction
Q2
Q3
Q4
CNT
Z
C
=
=
=
0x00
1
1
Forced NOP
NOP
Execute
NOP
HERE
NZERO
ZERO
INCFSZ
CNT, 1
Example:
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
1996 Microchip Technology Inc.
DS30412C-page 123
PIC17C4X
INFSNZ
Syntax:
Increment f, skip if not 0
IORLW
Inclusive OR Literal with WREG
[ label ] IORLW k
0 ≤ k ≤ 255
[label] INFSNZ f,d
Syntax:
Operands:
0 ≤ f ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(WREG) .OR. (k) → (WREG)
Z
Operation:
(f) + 1 → (dest), skip if not 0
Status Affected:
Encoding:
None
1011
0011
kkkk
kkkk
0010
010d
ffff
ffff
The contents of WREG are OR’ed with
the eight bit literal 'k'. The result is
placed in WREG.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Words:
Cycles:
1
1
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making
it a two-cycle instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Execute
Write to
WREG
Words:
Cycles:
1
1(2)
IORLW
0x35
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WREG
=
0x9A
Decode
Read
register 'f'
Execute
Write to
destination
After Instruction
WREG
=
0xBF
If skip:
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
HERE
ZERO
NZERO
INFSNZ REG, 1
Example:
Before Instruction
REG
=
REG
After Instruction
REG
If REG
PC
If REG
PC
=
=
=
=
=
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
DS30412C-page 124
1996 Microchip Technology Inc.
PIC17C4X
IORWF
Inclusive OR WREG with f
[ label ] IORWF f,d
0 ≤ f ≤ 255
LCALL
Long Call
Syntax:
Syntax:
[ label ] LCALL
0 ≤ k ≤ 255
k
Operands:
Operands:
Operation:
d
[0,1]
PC + 1 → TOS;
Operation:
(WREG) .OR. (f) → (dest)
k → PCL, (PCLATH) → PCH
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
0000
100d
ffff
ffff
1011
0111
kkkk
kkkk
Inclusive OR WREG with register 'f'. If
'd' is 0 the result is placed in WREG. If
'd' is 1 the result is placed back in regis-
ter 'f'.
LCALLallows an unconditional subrou-
tine call to anywhere within the 64k pro-
gram memory space.
Description:
Description:
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit desti-
nation address is then loaded into the
program counter. The lower 8-bits of
the destination address is embedded in
the instruction. The upper 8-bits of PC
is loaded from PC high holding latch,
PCLATH.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
Execute
Write to
register 'f'
destination
Words:
Cycles:
1
2
IORWF RESULT, 0
Example:
Before Instruction
Q Cycle Activity:
Q1
RESULT =
0x13
0x91
Q2
Q3
Q4
WREG
=
Decode
Read
literal 'k'
Execute
Write
register PCL
After Instruction
RESULT =
0x13
0x93
Forced NOP
Example:
NOP
Execute
NOP
WREG
=
MOVLW HIGH(SUBROUTINE)
MOVPF WREG, PCLATH
LCALL LOW(SUBROUTINE)
Before Instruction
SUBROUTINE =
16-bit Address
?
PC
=
After Instruction
PC
=
Address (SUBROUTINE)
1996 Microchip Technology Inc.
DS30412C-page 125
PIC17C4X
MOVFP
Syntax:
Move f to p
MOVLB
Move Literal to low nibble in BSR
[ label ] MOVLB k
0 ≤ k ≤ 15
[label] MOVFP f,p
Syntax:
Operands:
0 ≤ f ≤ 255
0 ≤ p ≤ 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (BSR<3:0>)
None
Operation:
(f) → (p)
Status Affected:
Encoding:
None
1011
1000
uuuu
kkkk
011p
pppp
ffff
ffff
The four bit literal 'k' is loaded in the
Bank Select Register (BSR). Only the
low 4-bits of the Bank Select Register
are affected. The upper half of the BSR
is unchanged. The assembler will
encode the “u” fields as '0'.
Move data from data memory location 'f'
to data memory location 'p'. Location 'f'
can be anywhere in the 256 word data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Description:
Either ’p' or 'f' can be WREG (a useful
special situation).
Words:
Cycles:
1
1
MOVFPis particularly useful for transfer-
ring a data memory location to a periph-
eral register (such as the transmit buffer
or an I/O port). Both 'f' and 'p' can be
indirectly addressed.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
Execute
Write literal
'k' to
literal 'u:k'
Words:
Cycles:
1
1
BSR<3:0>
MOVLB
0x5
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
BSR register
=
=
0x22
Decode
Read
register 'f'
Execute
Write
register 'p'
After Instruction
BSR register
0x25
MOVFP
REG1, REG2
Example:
Note: For the PIC17C42, only the low four bits of
the BSR register are physically imple-
mented. The upper nibble is read as '0'.
Before Instruction
REG1
REG2
=
=
0x33,
0x11
After Instruction
REG1
=
=
0x33,
0x33
REG2
DS30412C-page 126
1996 Microchip Technology Inc.
PIC17C4X
Move Literal to high nibble in
BSR
MOVLW
Move Literal to WREG
MOVLR
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
[ label ] MOVLR k
0 ≤ k ≤ 15
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
k → (WREG)
None
k → (BSR<7:4>)
None
1011
0000
kkkk
kkkk
1011
101x
kkkk
uuuu
The eight bit literal 'k' is loaded into
WREG.
The 4-bit literal 'k' is loaded into the
most significant 4-bits of the Bank
Select Register (BSR). Only the high
4-bits of the Bank Select Register
are affected. The lower half of the
BSR is unchanged. The assembler
will encode the “u” fields as 0.
Description:
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Execute
Write to
WREG
Words:
Cycles:
1
1
MOVLW
0x5A
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
WREG
=
0x5A
Decode
Read literal
'k:u'
Execute
Write
literal 'k' to
BSR<7:4>
MOVLR
5
Example:
Before Instruction
BSR register
=
=
0x22
0x52
After Instruction
BSR register
Note: This instruction is not available in the
PIC17C42 device.
1996 Microchip Technology Inc.
DS30412C-page 127
PIC17C4X
MOVPF
Syntax:
Move p to f
MOVWF
Move WREG to f
[ label ] MOVWF
0 ≤ f ≤ 255
[label] MOVPF p,f
Syntax:
f
Operands:
0 ≤ f ≤ 255
0 ≤ p ≤ 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
(WREG) → (f)
None
Operation:
(p) → (f)
Status Affected:
Encoding:
Z
0000
0001
ffff
ffff
010p
pppp
ffff
ffff
Move data from WREG to register 'f'.
Location 'f' can be anywhere in the 256
word data space.
Move data from data memory location
'p' to data memory location 'f'. Location
'f' can be anywhere in the 256 byte data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Description:
Words:
Cycles:
1
1
Either 'p' or 'f' can be WREG (a useful
special situation).
Q Cycle Activity:
Q1
Q2
Q3
Q4
MOVPFis particularly useful for transfer-
ring a peripheral register (e.g. the timer
or an I/O port) to a data memory loca-
tion. Both 'f' and 'p' can be indirectly
addressed.
Decode
Read
register 'f'
Execute
Write
register 'f'
MOVWF
REG
Example:
Before Instruction
Words:
Cycles:
1
1
WREG
REG
=
=
0x4F
0xFF
After Instruction
Q Cycle Activity:
Q1
WREG
=
0x4F
0x4F
Q2
Q3
Q4
REG
=
Decode
Read
Execute
Write
register 'p'
register 'f'
MOVPF
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x11
0x33
After Instruction
REG1
=
=
0x11
0x11
REG2
DS30412C-page 128
1996 Microchip Technology Inc.
PIC17C4X
MULLW
Multiply Literal with WREG
MULWF
Multiply WREG with f
Syntax:
[ label ] MULLW
k
Syntax:
[ label ] MULWF
f
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
Operation:
0 ≤ f ≤ 255
(k x WREG) → PRODH:PRODL
(WREG x f) → PRODH:PRODL
Status Affected: None
Status Affected: None
1011
1100
kkkk
kkkk
0011
0100
ffff
ffff
Encoding:
Encoding:
An unsigned multiplication is carried
out between the contents of WREG
and the 8-bit literal 'k'. The 16-bit
result is placed in PRODH:PRODL
register pair. PRODH contains the
high byte.
An unsigned multiplication is carried
out between the contents of WREG
and the register file location 'f'. The
16-bit result is stored in the
PRODH:PRODL register pair.
PRODH contains the high byte.
Description:
Description:
WREG is unchanged.
Both WREG and 'f' are unchanged.
None of the status flags are affected.
None of the status flags are affected.
Note that neither overflow nor carry
is possible in this operation. A zero
result is possible but not detected.
Note that neither overflow nor carry
is possible in this operation. A zero
result is possible but not detected.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Execute
Write
Decode
Read
Execute
Write
literal 'k'
registers
PRODH:
PRODL
register 'f'
registers
PRODH:
PRODL
MULLW
0xC4
MULWF
REG
Example:
Example:
Before Instruction
Before Instruction
WREG
PRODH
PRODL
=
=
=
0xE2
?
?
WREG
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
After Instruction
WREG
After Instruction
WREG
=
=
=
0xC4
0xAD
0x08
PRODH
PRODL
=
=
=
=
0xC4
0xB5
0x8A
0x94
REG
PRODH
PRODL
Note: This instruction is not available in the
PIC17C42 device.
Note: This instruction is not available in the
PIC17C42 device.
1996 Microchip Technology Inc.
DS30412C-page 129
PIC17C4X
NEGW
Negate W
NOP
No Operation
[ label ] NOP
None
Syntax:
[label] NEGW f,s
Syntax:
Operands:
0 ≤ F ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
s
[0,1]
No operation
None
Operation:
WREG + 1 → (f);
WREG + 1 → s
0000
0000
0000
0000
Status Affected:
Encoding:
OV, C, DC, Z
No operation.
0010
110s
ffff
ffff
1
1
WREG is negated using two’s comple-
ment. If 's' is 0 the result is placed in
WREG and data memory location 'f'. If
's' is 1 the result is placed only in data
memory location 'f'.
Description:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
NOP
Execute
NOP
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
Execute
Write
register 'f'
register 'f'
and other
specified
register
NEGW
REG,0
Example:
Before Instruction
WREG
REG
=
=
0011 1010[0x3A],
1010 1011[0xAB]
After Instruction
WREG
REG
=
=
1100 0111[0xC6]
1100 0111[0xC6]
DS30412C-page 130
1996 Microchip Technology Inc.
PIC17C4X
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RETLW
Return Literal to WREG
Syntax:
Syntax:
[ label ] RETLW k
Operands:
Operation:
Operands:
Operation:
0 ≤ k ≤ 255
TOS → (PC);
k → (WREG); TOS → (PC);
0 → GLINTD;
PCLATH is unchanged
PCLATH is unchanged.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
GLINTD
1011
0110
kkkk
kkkk
0000
0000
0000
0101
WREG is loaded with the eight bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Description:
Return from Interrupt. Stack is POP’ed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
Description:
Words:
Cycles:
1
2
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Execute
Write to
WREG
literal 'k'
Decode
Read
register
T0STA
Execute
NOP
Forced NOP
Example:
NOP
Execute
NOP
CALL TABLE ; WREG contains table
Forced NOP
NOP
Execute
NOP
;
;
;
offset value
WREG now has
table value
RETFIE
Example:
:
After Interrupt
TABLE
ADDWF PC
; WREG = offset
; Begin table
;
PC
GLINTD
=
=
TOS
0
RETLW k0
RETLW k1
:
:
RETLW kn
; End of table
Before Instruction
WREG
=
0x07
After Instruction
WREG
=
value of k7
1996 Microchip Technology Inc.
DS30412C-page 131
PIC17C4X
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
[ label ] RLCF f,d
0 ≤ f ≤ 255
Syntax:
[ label ] RETURN
None
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
TOS → PC;
None
Operation:
f<n> → d<n+1>;
f<7> → C;
C → d<0>
0000
0000
0000
0010
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter.
Status Affected:
Encoding:
C
0001
101d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
C
Decode
Read
register
PCL*
Execute
NOP
Words:
Cycles:
1
1
Forced NOP
NOP
Execute
NOP
* Remember reading PCL causes PCLATH to be updated.
This will be the high address of where the RETURNinstruc-
tion is located.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write to
destination
RETURN
Example:
After Interrupt
RLCF
REG,0
Example:
PC = TOS
Before Instruction
REG
=
1110 0110
C
=
0
After Instruction
REG
WREG
C
=
=
=
1110 0110
1100 1100
1
DS30412C-page 132
1996 Microchip Technology Inc.
PIC17C4X
RLNCF
Rotate Left f (no carry)
[ label ] RLNCF f,d
0 ≤ f ≤ 255
RRCF
Rotate Right f through Carry
[ label ] RRCF f,d
0 ≤ f ≤ 255
Syntax:
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
f<n> → d<n+1>;
f<7> → d<0>
Operation:
f<n> → d<n-1>;
f<0> → C;
C → d<7>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
C
0010
001d
ffff
ffff
0001
100d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
stored back in register 'f'.
Description:
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Execute
Write to
destination
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write to
destination
RLNCF
REG, 1
Example:
Before Instruction
RRCF
REG1,0
Example:
C
=
0
REG
=
1110 1011
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
C
=
REG
=
1101 0111
After Instruction
REG1
WREG
C
=
=
=
1110 0110
0111 0011
0
1996 Microchip Technology Inc.
DS30412C-page 133
PIC17C4X
RRNCF
Syntax:
Rotate Right f (no carry)
SETF
Set f
[ label ] RRNCF f,d
Syntax:
Operands:
[ label ] SETF f,s
Operands:
0 ≤ f ≤ 255
0 ≤ f ≤ 255
d
[0,1]
s
[0,1]
Operation:
f<n> → d<n-1>;
f<0> → d<7>
Operation:
FFh → f;
FFh → d
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
000d
ffff
ffff
0010
101s
ffff
ffff
The contents of register 'f' are rotated
one bit to the right. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed back in register 'f'.
If 's' is 0, both the data memory location
'f' and WREG are set to FFh. If 's' is 1
only the data memory location 'f' is set
to FFh.
Description:
Description:
Words:
Cycles:
1
1
register f
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Execute
Write
register 'f'
and other
specified
register
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write to
destination
RRNCF
REG, 1
Example 1:
SETF
REG, 0
Example1:
Before Instruction
Before Instruction
WREG
REG
=
=
?
REG
WREG
=
=
0xDA
0x05
1101 0111
After Instruction
After Instruction
WREG
REG
=
=
0
REG
WREG
=
=
0xFF
0xFF
1110 1011
Example2:
SETF
REG, 1
RRNCF
REG, 0
Example 2:
Before Instruction
Before Instruction
REG
WREG
=
=
0xDA
0x05
WREG
REG
=
=
?
1101 0111
After Instruction
After Instruction
REG
WREG
=
=
0xFF
0x05
WREG
REG
=
=
1110 1011
1101 0111
DS30412C-page 134
1996 Microchip Technology Inc.
PIC17C4X
SLEEP
SUBLW
Subtract WREG from Literal
[ label ] SUBLW k
0 ≤ k ≤ 255
Enter SLEEP mode
Syntax:
Syntax:
[ label ] SLEEP
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
k – (WREG) → (WREG)
OV, C, DC, Z
00h → WDT;
0 → WDT postscaler;
1 → TO;
1011
0010
kkkk
kkkk
0 → PD
WREG is subtracted from the eight bit
literal 'k'. The result is placed in
WREG.
Status Affected:
Encoding:
TO, PD
0000
0000
0000
0011
Words:
Cycles:
1
1
The power down status bit (PD) is
cleared.The time-out status bit (TO) is
set. Watchdog Timer and its prescaler
are cleared.
Description:
Q Cycle Activity:
Q1
The processor is put into SLEEP
mode with the oscillator stopped.
Q2
Q3
Q4
Decode
Read
Execute
Write to
WREG
literal 'k'
Words:
Cycles:
1
1
SUBLW 0x02
Example 1:
Q Cycle Activity:
Q1
Before Instruction
WREG
=
1
?
Q2
Q3
Q4
C
=
Decode
Read
Execute
NOP
register
PCLATH
After Instruction
WREG
=
=
=
1
1
0
C
Z
; result is positive
SLEEP
Example:
Example 2:
Before Instruction
TO
PD
=
=
?
?
Before Instruction
WREG
C
=
=
2
?
After Instruction
TO
PD
=
=
1 †
0
After Instruction
WREG
=
=
=
0
1
1
† If WDT causes wake-up, this bit is cleared
C
Z
; result is zero
Example 3:
Before Instruction
WREG
C
=
=
3
?
After Instruction
WREG
C
Z
=
=
=
FF ; (2’s complement)
0
1
; result is negative
1996 Microchip Technology Inc.
DS30412C-page 135
PIC17C4X
SUBWF
Syntax:
Subtract WREG from f
Subtract WREG from f with
Borrow
SUBWFB
[ label ] SUBWF f,d
Syntax:
[ label ] SUBWFB f,d
Operands:
0 ≤ f ≤ 255
d
[0,1]
Operands:
0 ≤ f ≤ 255
d
[0,1]
Operation:
(f) – (W) → (dest)
Operation:
(f) – (W) – C → (dest)
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
OV, C, DC, Z
0000
010d
ffff
ffff
0000
001d
ffff
ffff
Subtract WREG from register 'f' (2’s
complement method). If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s comple-
ment method). If 'd' is 0 the result is
stored in WREG. If 'd' is 1 the result is
stored back in register 'f'.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
Execute
Write to
Q2
Q3
Q4
register 'f'
destination
Decode
Read
register 'f'
Execute
Write to
destination
SUBWF
REG1, 1
Example 1:
Before Instruction
SUBWFB REG1, 1
Example 1:
REG1
WREG
C
=
=
=
3
2
?
Before Instruction
REG1
WREG
C
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
After Instruction
REG1
WREG
C
=
=
=
=
1
2
1
0
After Instruction
; result is positive
REG1
WREG
C
=
=
=
=
0x0C
0x0D
1
(0000 1011)
(0000 1101)
; result is positive
Z
Example 2:
Before Instruction
Z
0
Example2:
SUBWFB REG1,0
REG1
WREG
C
=
=
=
2
2
?
Before Instruction
REG1
WREG
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
After Instruction
REG1
WREG
C
=
=
=
=
0
2
1
1
After Instruction
; result is zero
REG1
WREG
C
=
=
=
=
0x1B
0x00
1
(0001 1011)
Z
; result is zero
Example 3:
Before Instruction
Z
1
Example3:
SUBWFB REG1,1
REG1
WREG
C
=
=
=
1
2
?
Before Instruction
REG1
WREG
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
After Instruction
REG1
WREG
C
=
=
=
=
FF
2
0
After Instruction
; result is negative
REG1
WREG
C
=
=
=
=
0xF5
0x0E
0
(1111 0100) [2’s comp]
(0000 1101)
; result is negative
Z
0
Z
0
DS30412C-page 136
1996 Microchip Technology Inc.
PIC17C4X
SWAPF
Syntax:
Swap f
TABLRD
Syntax:
Table Read
[ label ] SWAPF f,d
[ label ] TABLRD t,i,f
Operands:
0 ≤ f ≤ 255
Operands:
0 ≤ f ≤ 255
d
[0,1]
i
t
[0,1]
[0,1]
Operation:
f<3:0> → dest<7:4>;
f<7:4> → dest<3:0>
Operation:
If t = 1,
TBLATH → f;
If t = 0,
TBLATL → f;
Prog Mem (TBLPTR) → TBLAT;
If i = 1,
TBLPTR + 1 → TBLPTR
Status Affected:
Encoding:
None
0001
110d
ffff
ffff
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed in register 'f'.
Description:
Status Affected:
Encoding:
None
Words:
Cycles:
1
1
1010
10ti
ffff
ffff
1. A byte of the table latch (TBLAT)
is moved to register file 'f'.
Description:
Q Cycle Activity:
Q1
If t = 0: the high byte is moved;
If t = 1: the low byte is moved
Q2
Q3
Q4
Decode
Read
Execute
Write to
2. Then the contents of the program
memory location pointed to by
register 'f'
destination
SWAPF
REG,
0
Example:
the
16-bit
Table
Pointer
(TBLPTR) is loaded into the
16-bit Table Latch (TBLAT).
Before Instruction
REG
=
0x53
0x35
3. If i = 1: TBLPTR is incremented;
If i = 0: TBLPTR is not
incremented
After Instruction
REG
=
Words:
Cycles:
1
2 (3 cycle if f = PCL)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
Execute
Write
register 'f'
TBLATH or
TBLATL
1996 Microchip Technology Inc.
DS30412C-page 137
PIC17C4X
TABLRD
Table Read
Table Write
TABLWT
Syntax:
TABLRD 1, 1, REG ;
Example1:
[ label ] TABLWT t,i,f
0 ≤ f ≤ 255
Before Instruction
Operands:
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
i
t
[0,1]
[0,1]
Operation:
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH;
TBLAT → Prog Mem (TBLPTR);
If i = 1,
TBLPTR + 1 → TBLPTR
MEMORY(TBLPTR)
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0xAA
0x12
0x34
0xA357
0x5678
MEMORY(TBLPTR)
Status Affected:
Encoding:
None
TABLRD 0, 0, REG ;
Example2:
1010
11ti
ffff
ffff
Before Instruction
1. Load value in ’f’ into 16-bit table
latch (TBLAT)
Description:
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
If t = 0: load into low byte;
If t = 1: load into high byte
2. The contents of TBLAT is written
to the program memory location
pointed to by TBLPTR
MEMORY(TBLPTR)
After Instruction (table write completion)
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle
If TBLPTR points to an internal
EPROM location, then the
instruction is terminated when
an interrupt is received.
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x55
0x12
0x34
0xA356
0x1234
MEMORY(TBLPTR)
Note: The MCLR/VPP pin must be at the programming
voltage for successful programming of internal
memory.
If MCLR/VPP = VDD
the programming sequence of internal memory
will be executed, but will not be successful
(although the internal memory location may be
disturbed)
3. The TBLPTR can be automati-
cally incremented
If i = 0; TBLPTR is not
incremented
If i = 1; TBLPTR is incremented
Words:
1
Cycles:
2 (many if write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
Write
register
TBLATH or
TBLATL
DS30412C-page 138
1996 Microchip Technology Inc.
PIC17C4X
TLRD
Table Latch Read
Table Write
TABLWT
TABLWT 0, 1, REG
Syntax:
Operands:
[ label ] TLRD t,f
Example1:
0 ≤ f ≤ 255
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0xFFFF
t
[0,1]
If t = 0,
TBLATL → f;
If t = 1,
TBLATH → f
None
Operation:
MEMORY(TBLPTR)
After Instruction (table write completion)
Status Affected:
Encoding:
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0x53
0x55
0xA357
0x5355
1010
00tx
ffff
ffff
Read data from 16-bit table latch
(TBLAT) into file register 'f'. Table Latch
is unaffected.
Description:
MEMORY(TBLPTR - 1)
TABLWT 1, 0, REG
Example 2:
If t = 1; high byte is read
If t = 0; low byte is read
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0xFFFF
This instruction is used in conjunction
with TABLRDto transfer data from pro-
gram memory to data memory.
Words:
Cycles:
1
1
MEMORY(TBLPTR)
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x53
0xA356
0xAA53
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
Execute
Write
register 'f'
MEMORY(TBLPTR)
TBLATH or
TBLATL
Program
Memory
Data
Memory
TLRD
t, RAM
Example:
15
15
0
0
Before Instruction
TBLPTR
t
=
=
=
0
?
RAM
TBLAT
8
7
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
16 bits
8 bits
After Instruction
TBLAT
RAM
=
0xAF
TBLAT
=
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
Before Instruction
t
=
=
=
1
?
RAM
TBLAT
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
After Instruction
RAM
=
0x00
TBLAT
=
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
Program
Memory
Data
Memory
15
15
0
0
TBLPTR
8
7
16 bits
8 bits
TBLAT
1996 Microchip Technology Inc.
DS30412C-page 139
PIC17C4X
TLWT
Table Latch Write
TSTFSZ
Test f, skip if 0
[ label ] TSTFSZ f
0 ≤ f ≤ 255
Syntax:
Operands:
[ label ] TLWT t,f
Syntax:
0 ≤ f ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
t
[0,1]
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH
None
skip if f = 0
Operation:
None
0011
0011
ffff
ffff
If 'f' = 0, the next instruction, fetched
during the current instruction execution,
is discarded and an NOP is executed
making this a two-cycle instruction.
Status Affected:
Encoding:
1010
01tx
ffff
ffff
Data from file register 'f' is written into
the 16-bit table latch (TBLAT).
Description:
Words:
Cycles:
1
1 (2)
If t = 1; high byte is written
If t = 0; low byte is written
Q Cycle Activity:
Q1
Q2
Q3
Q4
This instruction is used in conjunction
with TABLWTto transfer data from data
memory to program memory.
Decode
Read
Execute
NOP
register 'f'
If skip:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Q Cycle Activity:
Q1
HERE
NZERO
ZERO
TSTFSZ CNT
:
Example:
Q2
Q3
Q4
Decode
Read
Execute
Write
register
:
register 'f'
TBLATH or
TBLATL
Before Instruction
PC = Address(HERE)
After Instruction
TLWT
t, RAM
Example:
If CNT
PC
If CNT
PC
=
=
≠
=
0x00,
Address (ZERO)
0x00,
Before Instruction
t
=
0
RAM
TBLAT
=
=
0xB7
Address (NZERO)
0x0000 (TBLATH = 0x00)
(TBLATL = 0x00)
After Instruction
RAM
=
0xB7
TBLAT
=
0x00B7 (TBLATH = 0x00)
(TBLATL = 0xB7)
Before Instruction
t
=
=
=
1
RAM
TBLAT
0xB7
0x0000 (TBLATH = 0x00)
(TBLATL = 0x00)
After Instruction
RAM
=
0xB7
TBLAT
=
0xB700 (TBLATH = 0xB7)
(TBLATL = 0x00)
DS30412C-page 140
1996 Microchip Technology Inc.
PIC17C4X
Exclusive OR Literal with
WREG
XORWF
Syntax:
Exclusive OR WREG with f
[ label ] XORWF f,d
0 ≤ f ≤ 255
XORLW
Syntax:
[ label ] XORLW k
Operands:
d
[0,1]
Operands:
Operation:
Status Affected:
Encoding:
0 ≤ k ≤ 255
Operation:
(WREG) .XOR. (f) → (dest)
(WREG) .XOR. k → (WREG)
Status Affected:
Encoding:
Z
Z
0000
110d
ffff
ffff
1011
0100
kkkk
kkkk
Exclusive OR the contents of WREG
with register 'f'. If 'd' is 0 the result is
stored in WREG. If 'd' is 1 the result is
stored back in the register 'f'.
Description:
The contents of WREG are XOR’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
literal 'k'
Execute
Write to
WREG
Decode
Read
Execute
Write to
register 'f'
destination
XORLW 0xAF
Example:
XORWF
REG, 1
Before Instruction
Example:
WREG
= 0xB5
Before Instruction
After Instruction
REG
WREG
=
=
0xAF
0xB5
WREG
=
0x1A
After Instruction
REG
WREG
=
=
0x1A
0xB5
1996 Microchip Technology Inc.
DS30412C-page 141
PIC17C4X
NOTES:
DS30412C-page 142
1996 Microchip Technology Inc.
PIC17C4X
16.3
ICEPIC: Low-cost PIC16CXXX
In-Circuit Emulator
16.0 DEVELOPMENT SUPPORT
16.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXXX families of 8-bit
OTP microcontrollers.
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
16.4
PRO MATE II: Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
gram PIC16C5X, PIC16CXXX, PIC17CXX and
PIC14000 devices. It can also set configuration and
code-protect bits in this mode.
• MPLAB-SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy logic development system (fuzzyTECH −MP)
16.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
16.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip micro-
controllers.
PICSTART Plus supports all PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
The PICMASTER Emulator System has been
designed as
a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1996 Microchip Technology Inc.
DS30412C-page 143
PIC17C4X
include an RS-232 interface, push-button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM-3 board is an LCD panel, with 4 commons
and 12 segments, that is capable of displaying time,
temperature and day of the week. The PICDEM-3 pro-
vides an additional RS-232 interface and Windows 3.1
software for showing the demultiplexed LCD signals on
a PC. A simple serial interface allows the user to con-
struct a hardware demultiplexer for the LCD signals.
PICDEM-3 will be available in the 3rd quarter of 1996.
16.6
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on
a PRO MATE II or
PICSTART-16B programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
16.9
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
16.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
16.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features
16.10 Assembler (MPASM)
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
DS30412C-page 144
1996 Microchip Technology Inc.
PIC17C4X
MPASM allow full symbolic debugging from the
Microchip Universal Emulator System
(PICMASTER).
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
MPASM has the following features to assist in develop-
ing software for specific use applications.
16.14 MP-DriveWay – Application Code
Generator
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
MP-DriveWay is an easy-to-use Windows-based Appli-
cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Micro-
chip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal
source and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source
code shorter and more maintainable.
16.15 SEEVAL Evaluation and
Programming System
16.11 Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break,
or in a trace mode.
16.16 TrueGauge Intelligent Battery
Management
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out-
side of the laboratory environment making it an excel-
lent multi-project software development tool.
The TrueGauge development tool supports system
development with the MTA11200B TrueGauge Intelli-
gent Battery Management IC. System design verifica-
tion can be accomplished before hardware prototypes
are built. User interface is graphically-oriented and
measured data can be saved in a file for exporting to
Microsoft Excel.
16.12 C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC16/17 family of micro-
controllers. The compiler provides powerful integration
capabilities and ease of use not found with other
compilers.
16.17 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display (PICMASTER emulator
software versions 1.13 and later).
16.13 Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for imple-
menting more complex systems.
1996 Microchip Technology Inc.
DS30412C-page 145
PIC17C4X
TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP
DS30412C-page 146
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.0 PIC17C42 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias..................................................................................................................-55 to +125˚C
Storage temperature............................................................................................................................... -65˚C to +150˚C
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ..........................................................................................-0.6V to +14V
Voltage on RA2 and RA3 with respect to VSS..............................................................................................-0.6V to +12V
Voltage on all other pins with respect to VSS ..................................................................................... -0.6V to VDD + 0.6V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin(s) - Total .............................................................................................................250 mA
Maximum current into VDD pin(s) - Total ................................................................................................................200 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin (except RA2 and RA3)......................................................................35 mA
Maximum output current sunk by RA2 or RA3 pins.................................................................................................60 mA
Maximum output current sourced by any I/O pin .....................................................................................................20 mA
Maximum current sunk by PORTA and PORTB (combined)..................................................................................150 mA
Maximum current sourced by PORTA and PORTB (combined).............................................................................100 mA
Maximum current sunk by PORTC, PORTD and PORTE (combined)...................................................................150 mA
Maximum current sourced by PORTC, PORTD and PORTE (combined)..............................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather than
pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1996 Microchip Technology Inc.
DS30412C-page 147
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
TABLE 17-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
OSC
PIC17C42-16
VDD: 4.5V to 5.5V
IDD: 6 mA max.
PIC17C42-25
RC
VDD: 4.5V to 5.5V
IDD: 6 mA max.
IPD: 5 µA max. at 5.5V (WDT disabled)
Freq: 4 MHz max.
IPD: 5 µA max. at 5.5V (WDT disabled)
Freq: 4 MHz max.
XT
EC
LF
VDD: 4.5V to 5.5V
IDD: 24 mA max.
IPD: 5 µA max. at 5.5V (WDT disabled)
Freq: 16 MHz max.
VDD: 4.5V to 5.5V
IDD: 38 mA max.
IPD: 5 µA max. at 5.5V (WDT disabled)
Freq: 25 MHz max.
VDD: 4.5V to 5.5V
IDD: 24 mA max.
IPD: 5 µA max. at 5.5V (WDT disabled)
Freq: 16 MHz max.
VDD: 4.5V to 5.5V
IDD: 38 mA max.
IPD: 5 µA max. at 5.5V (WDT disabled)
Freq: 25 MHz max.
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 150 µA max. at 32 kHz (WDT enabled) IDD: 150 µA max. at 32 kHz (WDT enabled)
IPD: 5 µA max. at 5.5V (WDT disabled)
IPD: 5 µA max. at 5.5V (WDT disabled)
Freq: 2 MHz max.
Freq: 2 MHz max.
DS30412C-page 148
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.1
DC CHARACTERISTICS:
PIC17C42-16 (Commercial, Industrial)
PIC17C42-25 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
DC CHARACTERISTICS
Parameter
-40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
D001
D002
VDD
VDR
Supply Voltage
4.5
–
–
5.5
–
V
V
RAM Data Retention
Voltage (Note 1)
1.5 *
Device in SLEEP mode
D003
D004
VPOR VDD start voltage to
ensure internal
–
VSS
–
–
–
V
See section on Power-on Reset for
details
Power-on Reset signal
SVDD VDD rise rate to
ensure internal
0.060*
mV/ms See section on Power-on Reset for
details
Power-on Reset signal
D010
D011
D012
D013
D014
IDD
Supply Current
(Note 2)
–
–
–
–
–
3
6
11
19
95
6
mA
mA
mA
mA
µA
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
FOSC = 16 MHz
FOSC = 25 MHz
FOSC = 32 kHz
12 *
24 *
38
150
WDT enabled (EC osc configuration)
D020
D021
IPD
Power-down Current
(Note 3)
–
–
10
< 1
40
5
µA
µA
VDD = 5.5V, WDT enabled
VDD = 5.5V, WDT disabled
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads need to be con-
sidered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, The current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency on the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
1996 Microchip Technology Inc.
DS30412C-page 149
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.2
DC CHARACTERISTICS:
PIC17C42-16 (Commercial, Industrial)
PIC17C42-25 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 17.1
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
Min
Typ†
Max Units
Conditions
VIL
D030
D031
VSS
VSS
–
–
0.8
V
V
with Schmitt Trigger buffer
0.2VDD
D032
MCLR, OSC1 (in EC and RC
mode)
OSC1 (in XT, and LF mode)
Input High Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR
Vss
–
0.2VDD
V
Note1
Note1
D033
–
0.5VDD
–
V
VIH
–
–
–
D040
D041
D042
D043
D050
2.0
0.8VDD
0.8VDD
–
VDD
VDD
VDD
–
V
V
V
V
V
–
0.5VDD
–
OSC1 (XT, and LF mode)
VHYS Hysteresis of
Schmitt Trigger inputs
0.15VDD*
–
Input Leakage Current
(Notes 2, 3)
D060
IIL
I/O ports (except RA2, RA3)
–
–
±1
µA Vss ≤ VPIN ≤ VDD,
I/O Pin at hi-impedance
PORTB weak pull-ups dis-
abled
D061
D062
D063
D064
MCLR
–
–
±2
±2
±1
10
µA VPIN = Vss or VPIN = VDD
µA Vss ≤ VRA2, VRA3 ≤ 12V
µA Vss ≤ VPIN ≤ VDD
RA2, RA3
OSC1, TEST
MCLR
–
–
–
–
µA VMCLR = VPP = 12V
(when not programming)
D070
IPURB PORTB weak pull-up current
60
200
400
µA VPIN = VSS, RBPU = 0
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
‡
††
These parameters are for design guidance only and are not tested, nor characterized.
Design guidance to attain the AC timing specifications. These loads are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
5: The MCLR/Vpp pin may be kept in this range at times other than programming, but this is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
DS30412C-page 150
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 17.1
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Output Low Voltage
I/O ports (except RA2 and RA3)
with TTL buffer
D080
D081
VOL
–
–
–
–
0.1VDD
0.4
V
V
IOL = 4 mA
IOL = 6 mA, VDD = 4.5V
Note 6
D082
D083
RA2 and RA3
OSC2/CLKOUT
–
–
–
–
3.0
0.4
V
V
IOL = 60.0 mA, VDD = 5.5V
IOL = 2 mA, VDD = 4.5V
(RC and EC osc modes)
Output High Voltage (Note 3)
D090
D091
VOH
I/O ports (except RA2 and RA3) 0.9VDD
–
–
–
–
V
V
IOH = -2 mA
IOH = -6.0 mA, VDD = 4.5V
Note 6
with TTL buffer
2.4
D092
D093
RA2 and RA3
–
–
–
12
–
V
V
Pulled-up to externally applied
voltage
IOH = -5 mA, VDD = 4.5V
OSC2/CLKOUT
2.4
(RC and EC osc modes)
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2 pin
–
–
25 ††
pF In EC or RC osc modes when
OSC2 pin is outputting
CLKOUT.
External clock is used to drive
OSC1.
D101
D102
CIO
All I/O pins and OSC2
(in RC mode)
System Interface Bus
(PORTC, PORTD and PORTE)
–
–
–
–
50 ††
pF
CAD
100 †† pF In Microprocessor or
Extended Microcontroller
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
‡
††
These parameters are for design guidance only and are not tested, nor characterized.
Design guidance to attain the AC timing specifications. These loads are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
5: The MCLR/Vpp pin may be kept in this range at times other than programming, but this is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
1996 Microchip Technology Inc.
DS30412C-page 151
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +40˚C
Operating voltage VDD range as described in Section 17.1
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Internal Program Memory
Programming Specs (Note 4)
D110
D111
VPP
Voltage on MCLR/VPP pin
12.75
4.75
–
5.0
13.25
5.25
V
V
Note 5
VDDP Supply voltage during
programming
D112
D113
IPP
Current into MCLR/VPP pin
–
–
25 ‡
–
50 ‡
30 ‡
mA
mA
IDDP Supply current during
programming
D114
TPROG Programming pulse width
10
100
1000
µs Terminated via internal/exter-
nal interrupt or a reset
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
Note: When using the Table Write for internal programming, the device temperature must be less than 40˚C.
DS30412C-page 152
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.3
Timing Parameter Symbology
The timing parameter symbols have been created using one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
ad
T
Time
Address/Data
ALE
ost
pwrt
rb
Oscillator Start-up Timer
Power-up Timer
PORTB
al
cc
ck
dt
Capture1 and Capture2
CLKOUT or clock
Data in
rd
RD
rw
RD or WR
in
INT pin
t0
T0CKI
io
I/O port
t123
wdt
wr
TCLK12 and TCLK3
Watchdog Timer
WR
mc
oe
os
MCLR
OE
OSC1
Uppercase symbols and their meanings:
S
D
E
F
H
I
Driven
L
Low
Edge
P
R
V
Z
Period
Rise
Fall
High
Valid
Invalid (Hi-impedance)
Hi-impedance
1996 Microchip Technology Inc.
DS30412C-page 153
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-1: PARAMETER MEASUREMENT INFORMATION
All timings are measure between high and low measurement points as indicated in the figures below.
INPUT LEVEL CONDITIONS
PORTC, D and E pins
VIH = 2.4V
VIL = 0.4V
Data in valid
All other input pins
Data in invalid
VIH = 0.9VDD
VIL = 0.1VDD
Data in valid
Data in invalid
OUTPUT LEVEL CONDITIONS
0.25V
0.25V
VOH = 0.7VDD
VDD/2
VOL = 0.3VDD
0.25V
0.25V
Data out valid
Data out invalid
Output
driven
Output
hi-impedance
0.9VDD
Fall Time
0.1VDD
Rise Time
LOAD CONDITIONS
Load Condition 1
VDD/2
Load Condition 2
RL
Pin
CL
CL
Pin
VSS
VSS
RL = 464
CL ≤ 50 pF
DS30412C-page 154
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.4
Timing Diagrams and Specifications
FIGURE 17-2: EXTERNAL CLOCK TIMING
Q4
Q3
Q4
Q1
Q1
Q2
OSC1
1
3
3
4
4
2
OSC2 †
† In EC and RC modes only.
TABLE 17-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min Typ†
Max
Units
Conditions
DC
DC
—
—
16
25
MHz EC osc mode - PIC17C42-16
Fosc External CLKIN Frequency
MHz
- PIC17C42-25
(Note 1)
Oscillator Frequency
(Note 1)
DC
1
1
—
—
—
—
4
16
25
2
MHz RC osc mode
MHz XT osc mode - PIC17C42-16
MHz
- PIC17C42-25
DC
MHz LF osc mode
1
Tosc External CLKIN Period
62.5
40
—
—
—
—
ns
ns
EC osc mode - PIC17C42-16
- PIC17C42-25
(Note 1)
Oscillator Period
(Note 1)
250
62.5
40
—
—
—
—
—
ns
ns
ns
ns
RC osc mode
XT osc mode - PIC17C42-16
- PIC17C42-25
1,000
1,000
—
500
LF osc mode
2
3
TCY
Instruction Cycle Time (Note 1)
160
4/Fosc
—
DC
—
ns
ns
TosL, Clock in (OSC1) High or Low Time 10 ‡
TosH
EC oscillator
EC oscillator
4
TosR, Clock in (OSC1) Rise or Fall Time
—
—
5 ‡
ns
TosF
†
‡
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in unstable oscillator operation and/or higher than expected current consump-
tion. All devices are tested to operate at “min.” values with an external clock applied to the OSC1 pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
1996 Microchip Technology Inc.
DS30412C-page 155
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
OSC2 †
12
13
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
† In EC and RC modes only.
TABLE 17-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10
11
12
13
14
15
16
17
20
21
22
23
TosH2ckL
OSC1↑ to CLKOUT↓
—
15 ‡
15 ‡
5 ‡
5 ‡
—
30 ‡
30 ‡
15 ‡
15 ‡
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
TosH2ckH OSC1↑ to CLKOUT↑
—
TckR
CLKOUT rise time
—
TckF
CLKOUT fall time
—
TckH2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TioR
CLKOUT↑ to Port out valid
Port in valid before CLKOUT↑
Port in hold after CLKOUT↑
OSC1↑ (Q1 cycle) to Port out valid
Port output rise time
—
0.5TCY + 20‡
0.25TCY + 25 ‡
—
—
—
0 ‡
—
—
—
100 ‡
35 ‡
35 ‡
—
—
10 ‡
10 ‡
—
TioF
Port output fall time
—
TinHL
INT pin high or low time
RB7:RB0 change INT high or low time
25 *
25 *
TrbHL
—
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Measurements are taken in EC Mode where OSC2 output = 4 x TOSC = TCY.
DS30412C-page 156
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
35
Address /
Data
TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL
Twdt
MCLR Pulse Width (low)
100 *
5 *
—
—
ns
Watchdog Timer Time-out Period
(Prescale = 1)
12
25 *
ms
32
33
Tost
Oscillation Start-up Timer Period
Power-up Timer Period
1024 TOSC §
96
ms TOSC = OSC1 period
ms
Tpwrt
40 *
—
200 *
100 *
35
TmcL2adI MCLR to System Interface bus
(AD15:AD0) invalid
—
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
§
These parameters are for design guidance only and are not tested, nor characterized.
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 157
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-5: TIMER0 CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 17-5: TIMER0 CLOCK REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20 §
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
42
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
0.5TCY + 20 §
10*
TCY + 40 §
N
ns N = prescale value
(1, 2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 17-6: TIMER1,TIMER2, AND TIMER3 CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 17-6: TIMER1,TIMER2, AND TIMER3 CLOCK REQUIREMENTS
Parameter
No.
Typ
†
Sym
Characteristic
Min
Max Units Conditions
45
46
47
Tt123H TCLK12 and TCLK3 high time
Tt123L TCLK12 and TCLK3 low time
Tt123P TCLK12 and TCLK3 input period
0.5 TCY + 20 §
0.5 TCY + 20 §
—
—
—
—
—
—
ns
ns
TCY + 40 §
N
ns N = prescale value
(1, 2, 4, 8)
48
TckE2tmrI Delay from selected External Clock Edge to
Timer increment
2TOSC §
—
6 Tosc §
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
DS30412C-page 158
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-7: CAPTURE TIMINGS
CAP1
and CAP2
(Capture Mode)
50
51
52
TABLE 17-7: CAPTURE REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ† Max Units Conditions
50
51
TccL Capture1 and Capture2 input low time
10 *
10 *
—
—
—
—
ns
ns
TccH
TccP
Capture1 and Capture2 input high time
Capture1 and Capture2 input period
52
2 TCY §
N
—
—
ns N = prescale value
(4 or 16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 17-8: PWM TIMINGS
PWM1
and PWM2
(PWM Mode)
53
54
TABLE 17-8: PWM REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ† Max Units Conditions
53
54
TccR PWM1 and PWM2 output rise time
TccF PWM1 and PWM2 output fall time
—
—
10 * 35 *§ ns
10 * 35 *§ ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 159
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RA5/TX/CK
pin
121
121
RA4/RX/DT
pin
120
122
TABLE 17-9: SERIAL PORT SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
120
TckH2dtV
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
—
—
—
65
35
ns
ns
121
122
TckRF
TdtRF
Clock out rise time and fall time (Master
Mode)
10
Data out rise time and fall time
—
10
35
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 17-10: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RA5/TX/CK
125
pin
RA4/RX/DT
pin
126
TABLE 17-10: SERIAL PORT SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
15
—
—
ns
Data hold before CK↓ (DT hold time)
126
TckL2dtl
Data hold after CK↓ (DT hold time)
15
—
—
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30412C-page 160
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-11: MEMORY INTERFACE WRITE TIMING
Q1
Q2
Q3
Q4
Q2
Q1
OSC1
ALE
OE
151
WR
150
addr out
154
data out
AD<15:0>
addr out
152
153
TABLE 17-11: MEMORY INTERFACE WRITE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units Conditions
150
TadV2alL
AD<15:0> (address) valid to ALE↓
0.25Tcy - 30
—
—
ns
(address setup time)
151
152
153
154
TalL2adI
TadV2wrL
TwrH2adI
TwrL
ALE↓ to address out invalid
(address hold time)
0
—
—
—
ns
Data out valid to WR↓
(data setup time)
0.25Tcy - 40
—
—
—
ns
ns
ns
WR↑ to data out invalid
(data hold time)
—
—
0.25TCY §
0.25TCY §
WR pulse width
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification is guaranteed by design.
1996 Microchip Technology Inc.
DS30412C-page 161
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-12: MEMORY INTERFACE READ TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
OE
164
168
160
165
Data in
161
AD<15:0>
WR
Addr out
Addr out
150
162
151
163
167
'1'
'1'
TABLE 17-12: MEMORY INTERFACE READ REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
150
TadV2alL
TalL2adI
TadZ2oeL
AD<15:0> (address) valid to ALE↓
(address setup time)
0.25Tcy - 30
5*
—
—
—
—
ns
ns
151
ALE↓ to address out invalid
(address hold time)
160
161
162
AD<15:0> high impedance to OE↓
0*
0.25Tcy - 15
35
—
—
—
—
—
—
ns
ns
ns
ToeH2adD OE↑ to AD<15:0> driven
TadV2oeH Data in valid before OE↑
(data setup time)
163
164
ToeH2adI
TalH
OE↑to data in invalid (data hold time)
0
—
—
—
ns
ns
ALE pulse width
—
0.25TCY §
165
166
167
ToeL
OE pulse width
0.5Tcy - 35 §
—
TCY §
—
—
—
ns
ns
ns
TalH2alH
Tacc
ALE↑ to ALE↑ (cycle time)
Address access time
—
—
0.75 TCY-40
0.5 TCY - 60
168
Toe
Output enable access time
(OE low to Data Valid)
—
—
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification guaranteed by design.
DS30412C-page 162
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
18.0 PIC17C42 DC AND AC CHARACTERISTICS
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs
or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for infor-
mation only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3σ) and (mean - 3σ)
respectively where σ is standard deviation.
TABLE 18-1: PIN CAPACITANCE PER PACKAGE TYPE
Typical Capacitance (pF)
Pin Name
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
All pins, except MCLR,
VDD, and VSS
10
10
10
10
MCLR pin
20
20
20
20
FIGURE 18-1: TYPICAL RC OSCILLATOR FREQUENCY vs.TEMPERATURE
FOSC
Frequency normalized to +25°C
FOSC (25°C)
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0
10
20
25
30
40
50
60
70
T(°C)
1996 Microchip Technology Inc.
DS30412C-page 163
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 10k
3.0
2.5
2.0
1.5
Cext = 22 pF, T = 25°C
1.0
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
FIGURE 18-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 3.3k
3.0
2.5
R = 5.1k
2.0
1.5
R = 10k
1.0
Cext = 100 pF, T = 25°C
0.5
0.0
R = 100k
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
DS30412C-page 164
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
R = 3.3k
R = 5.1k
R = 10k
0.4
0.2
Cext = 300 pF, T = 25°C
R = 160k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
TABLE 18-2: RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5V, 25°C
Cext
Rext
22 pF
10k
100k
3.3k
5.1k
10k
3.33 MHz
353 kHz
3.54 MHz
2.43 MHz
1.30 MHz
129 kHz
1.54 MHz
980 kHz
564 kHz
35 kHz
± 12%
± 13%
± 10%
± 14%
± 17%
± 10%
± 14%
± 12%
± 16%
± 18%
100 pF
300 pF
100k
3.3k
5.1k
10k
160k
1996 Microchip Technology Inc.
DS30412C-page 165
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD
500
450
400
350
Max @ -40°C
300
Typ @ 25°C
250
200
150
Min @ 85°C
100
50
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 18-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
20
18
Max @ -40°C
16
14
12
10
8
Typ @ 25°C
6
Min @ 85°C
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30412C-page 166
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-7: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C)
100000
10000
1000
100
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
4.0V
10
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
FIGURE 18-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125°C TO -40°C)
100000
10000
7.0V
6.5V
6.0V
5.5V
1000
100
5.0V
4.5V
4.0V
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
1996 Microchip Technology Inc.
DS30412C-page 167
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-9: TYPICAL IPD vs. VDD WATCHDOG DISABLED 25°C
12
10
8
6
4
2
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 18-10: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Temp. = 85°C
Temp. = 70°C
Temp. = 0°C
Temp. = -40°C
6.5 7.0
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30412C-page 168
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-11: TYPICAL IPD vs. VDD WATCHDOG ENABLED 25°C
30
25
20
15
10
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 18-12: MAXIMUM IPD vs. VDD WATCHDOG ENABLED
60
50
40
-40°C
0°C
70°C
85°C
30
20
10
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
1996 Microchip Technology Inc.
DS30412C-page 169
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-13: WDT TIMER TIME-OUT PERIOD vs. VDD
30
25
Max. 85°C
20
Max. 70°C
Min. 0°C
15
10
Typ. 25°C
Min. -40°C
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 18-14: IOH vs. VOH, VDD = 3V
0
-2
-4
-6
Min @ 85°C
-8
Typ @ 25°C
-10
-12
-14
Max @ -40°C
-16
-18
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD (Volts)
DS30412C-page 170
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-15: IOH vs. VOH, VDD = 5V
0
-5
-10
-15
-20
Min @ 85°C
Max @ -40°C
-25
Typ @ 25°C
-30
-35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (Volts)
FIGURE 18-16: IOL vs. VOL, VDD = 3V
30
Max. -40°C
25
20
Typ. 25°C
15
10
Min. +85°C
5
0
0.0
0.5
1.0
1.5
VDD (Volts)
2.0
2.5
3.0
1996 Microchip Technology Inc.
DS30412C-page 171
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-17: IOL vs. VOL, VDD = 5V
90
80
70
60
50
40
30
Max @ -40°C
Typ @ 25°C
Min @ +85°C
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD (Volts)
FIGURE 18-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD
2.0
1.8
Max (-40°C to +85°C)
1.6
Typ @ 25°C
1.4
1.2
1.0
Min (-40°C to +85°C)
0.8
0.6
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
5.5
6.0
DS30412C-page 172
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-19: VTH, VIL of I/O PINS (SCHMITT TRIGGER) VS. VDD
5.0
4.5
4.0
VIH, max (-40°C to +85°C)
VIH, typ (25°C)
VIH, min (-40°C to +85°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIL, max (-40°C to +85°C)
VIL, typ (25°C)
VIL, min (-40°C to +85°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 18-20: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT AND LF MODES) vs. VDD
3.4
3.2
Typ (25°C)
3.0
Max (-40°C to +85°C)
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
Min (-40°C to +85°C)
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
5.5
6.0
1996 Microchip Technology Inc.
DS30412C-page 173
PIC17C4X
NOTES:
DS30412C-page 174
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.0 PIC17CR42/42A/43/R43/44 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias..................................................................................................................-55 to +125˚C
Storage temperature............................................................................................................................... -65˚C to +150˚C
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ..........................................................................................-0.6V to +14V
Voltage on RA2 and RA3 with respect to VSS..............................................................................................-0.6V to +14V
Voltage on all other pins with respect to VSS ..................................................................................... -0.6V to VDD + 0.6V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin(s) - total..............................................................................................................250 mA
Maximum current into VDD pin(s) - total.................................................................................................................200 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin (except RA2 and RA3)......................................................................35 mA
Maximum output current sunk by RA2 or RA3 pins.................................................................................................60 mA
Maximum output current sourced by any I/O pin .....................................................................................................20 mA
Maximum current sunk by PORTA and PORTB (combined)..................................................................................150 mA
Maximum current sourced by PORTA and PORTB (combined).............................................................................100 mA
Maximum current sunk by PORTC, PORTD and PORTE (combined)...................................................................150 mA
Maximum current sourced by PORTC, PORTD and PORTE (combined)..............................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather than
pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1996 Microchip Technology Inc.
DS30412C-page 175
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
TABLE 19-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
DS30412C-page 176
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.1
DC CHARACTERISTICS:
PIC17CR42/42A/43/R43/44-16 (Commercial, Industrial)
PIC17CR42/42A/43/R43/44-25 (Commercial, Industrial)
PIC17CR42/42A/43/R43/44-33 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
DC CHARACTERISTICS
Parameter
-40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
No.
Sym
Characteristic
Min
4.5
Typ† Max Units
Conditions
D001
D002
VDD
Supply Voltage
–
–
6.0
–
V
V
VDR
RAM Data Retention
Voltage (Note 1)
1.5 *
Device in SLEEP mode
D003
D004
VPOR VDD start voltage to
ensure internal
–
VSS
–
–
–
V
See section on Power-on Reset for
details
Power-on Reset signal
SVDD VDD rise rate to
ensure internal
0.060 *
mV/ms See section on Power-on Reset for
details
Power-on Reset signal
D010
D011
D012
D013
D015
D014
IDD
Supply Current
(Note 2)
–
–
–
–
–
–
3
6
11
19
25
95
6
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
FOSC = 16 MHz
FOSC = 25 MHz
FOSC = 33 MHz
12 *
24 *
38
50
150
FOSC = 32 kHz,
WDT enabled (EC osc configuration)
D020
D021
IPD
Power-down
Current (Note 3)
–
–
10
< 1
40
5
µA
µA
VDD = 5.5V, WDT enabled
VDD = 5.5V, WDT disabled
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be con-
sidered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
1996 Microchip Technology Inc.
DS30412C-page 177
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.2
DC CHARACTERISTICS:
PIC17LC42A/43/LC44 (Commercial, Industrial)
PIC17LCR42/43 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
DC CHARACTERISTICS
Parameter
-40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
D001
D002
VDD
VDR
Supply Voltage
2.5
–
–
6.0
–
V
V
RAM Data Retention
Voltage (Note 1)
1.5 *
Device in SLEEP mode
D003
D004
VPOR VDD start voltage to
ensure internal
–
VSS
–
–
–
V
See section on Power-on Reset for
details
Power-on Reset signal
SVDD VDD rise rate to
ensure internal
0.060 *
mV/ms See section on Power-on Reset for
details
Power-on Reset signal
D010
D011
D014
IDD
Supply Current
(Note 2)
–
–
–
3
6
95
6
12 *
150
mA
mA
µA
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
FOSC = 32 kHz,
WDT disabled (EC osc configuration)
D020
D021
IPD
Power-down
Current (Note 3)
–
–
10
< 1
40
5
µA
µA
VDD = 5.5V, WDT enabled
VDD = 5.5V, WDT disabled
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD, MCLR
= VDD; WDT enabled/disabled as specified.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be con-
sidered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30412C-page 178
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.3
DC CHARACTERISTICS:
PIC17CR42/42A/43/R43/44-16 (Commercial, Industrial)
PIC17CR42/42A/43/R43/44-25 (Commercial, Industrial)
PIC17CR42/42A/43/R43/44-33 (Commercial, Industrial)
PIC17LCR42/42A/43/R43/44-08 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 19.1
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
Min
Typ†
Max Units
Conditions
VIL
D030
VSS
VSS
VSS
–
–
–
0.8
0.2VDD
0.2VDD
V
V
V
4.5V ≤ VDD ≤ 5.5V
2.5V ≤ VDD ≤ 4.5V
D031
D032
with Schmitt Trigger buffer
MCLR, OSC1 (in EC and RC
mode)
OSC1 (in XT, and LF mode)
Input High Voltage
I/O ports
Vss
–
0.2VDD
–
V
Note1
D033
–
0.5VDD
V
VIH
D040
D041
with TTL buffer
2.0
1 + 0.2VDD
0.8VDD
–
–
–
VDD
VDD
VDD
V
V
V
4.5V ≤ VDD ≤ 5.5V
2.5V ≤ VDD ≤ 4.5V
with Schmitt Trigger buffer
D042
D043
D050
MCLR
OSC1 (XT, and LF mode)
VHYS Hysteresis of
Schmitt Trigger inputs
0.8VDD
–
0.15VDD *
–
0.5VDD
–
VDD
–
–
V
V
V
Note1
Input Leakage Current
(Notes 2, 3)
D060
IIL
I/O ports (except RA2, RA3)
–
–
±1
µA Vss ≤ VPIN ≤ VDD,
I/O Pin at hi-impedance
PORTB weak pull-ups
disabled
D061
D062
D063
D063B
MCLR
RA2, RA3
OSC1, TEST (EC, RC modes)
OSC1, TEST (XT, LF modes)
–
–
±2
±2
±1
µA VPIN = Vss or VPIN = VDD
µA Vss ≤ VRA2, VRA3 ≤ 12V
µA Vss ≤ VPIN ≤ VDD
–
–
–
–
VPIN
µA RF ≥ 1 MΩ, see Figure 14.2
D064
MCLR
–
–
10
µA VMCLR = VPP = 12V
(when not programming)
D070
IPURB PORTB weak pull-up current
60
200
400
µA VPIN = VSS, RBPU = 0
4.5V ≤ VDD ≤ 6.0V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
1996 Microchip Technology Inc.
DS30412C-page 179
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 19.1
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Output Low Voltage
D080
VOL
I/O ports (except RA2 and RA3)
IOL = VDD/1.250 mA
4.5V ≤ VDD ≤ 6.0V
VDD = 2.5V
IOL = 6 mA, VDD = 4.5V
Note 6
–
–
–
–
–
–
0.1VDD
0.1VDD *
0.4
V
V
V
D081
with TTL buffer
D082
D083
D084
RA2 and RA3
OSC2/CLKOUT
(RC and EC osc modes)
–
–
–
–
–
–
3.0
0.4
0.1VDD *
V
V
V
IOL = 60.0 mA, VDD = 6.0V
IOL = 1 mA, VDD = 4.5V
IOL = VDD/5 mA
(PIC17LC43/LC44 only)
Output High Voltage (Note 3)
D090
VOH I/O ports (except RA2 and RA3)
IOH = -VDD/2.500 mA
4.5V ≤ VDD ≤ 6.0V
VDD = 2.5V
IOH = -6.0 mA, VDD=4.5V
Note 6
0.9VDD
0.9VDD *
2.4
–
–
–
–
–
–
V
V
V
D091
D092
with TTL buffer
RA2 and RA3
–
–
12
V
Pulled-up to externally
applied voltage
D093
D094
OSC2/CLKOUT
(RC and EC osc modes)
2.4
0.9VDD *
–
–
–
–
V
V
IOH = -5 mA, VDD = 4.5V
IOH = -VDD/5 mA
(PIC17LC43/LC44 only)
Capacitive Loading Specs
on Output Pins
D100
COSC2 OSC2/CLKOUT pin
–
–
25
pF In EC or RC osc modes
when OSC2 pin is outputting
CLKOUT.
external clock is used to
drive OSC1.
D101
D102
CIO
All I/O pins and OSC2
(in RC mode)
–
–
–
–
50
50
pF
CAD System Interface Bus
(PORTC, PORTD and PORTE)
pF In Microprocessor or
Extended Microcontroller
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
DS30412C-page 180
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +40˚C
Operating voltage VDD range as described in Section 19.1
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Internal Program Memory
Programming Specs (Note 4)
D110
D111
VPP
Voltage on MCLR/VPP pin
12.75
4.75
–
5.0
13.25
5.25
V
V
Note 5
VDDP Supply voltage during
programming
D112
D113
IPP
Current into MCLR/VPP pin
–
–
25 ‡
–
50 ‡
30 ‡
mA
mA
IDDP Supply current during
programming
D114
TPROG Programming pulse width
10
100
1000
µs Terminated via internal/
external interrupt or a reset
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as coming out of the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
Note: When using the Table Write for internal programming, the device temperature must be less than 40˚C.
1996 Microchip Technology Inc.
DS30412C-page 181
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I C specifications only)
2
(I C specifications only)
T
F
Frequency
T
Time
Lowercase symbols (pp) and their meanings:
pp
ad
Address/Data
ALE
ost
pwrt
rb
Oscillator Start-Up Timer
Power-Up Timer
PORTB
al
cc
ck
dt
Capture1 and Capture2
CLKOUT or clock
Data in
rd
RD
rw
RD or WR
in
INT pin
t0
T0CKI
io
I/O port
t123
wdt
wr
TCLK12 and TCLK3
Watchdog Timer
WR
mc
oe
os
MCLR
OE
OSC1
Uppercase symbols and their meanings:
S
D
E
F
H
I
Driven
L
Low
Edge
P
R
V
Z
Period
Rise
Fall
High
Valid
Invalid (Hi-impedance)
Hi-impedance
DS30412C-page 182
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-1: PARAMETER MEASUREMENT INFORMATION
All timings are measure between high and low measurement points as indicated in the figures below.
INPUT LEVEL CONDITIONS
PORTC, D and E pins
VIH = 2.4V
VIL = 0.4V
Data in valid
All other input pins
Data in invalid
VIH = 0.9VDD
VIL = 0.1VDD
Data in valid
Data in invalid
OUTPUT LEVEL CONDITIONS
0.25V
0.25V
VOH = 0.7VDD
VDD/2
VOL = 0.3VDD
0.25V
0.25V
Data out valid
Data out invalid
Output
driven
Output
hi-impedance
0.9 VDD
Fall Time
0.1 VDD
Rise Time
LOAD CONDITIONS
Load Condition 1
Pin
CL
VSS
50 pF ≤ CL
1996 Microchip Technology Inc.
DS30412C-page 183
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.5
Timing Diagrams and Specifications
FIGURE 19-2: EXTERNAL CLOCK TIMING
Q4
Q3
3
Q4
3
Q1
4
Q1
Q2
OSC1
1
4
2
OSC2 †
† In EC and RC modes only.
TABLE 19-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ†
Max Units
Conditions
DC
DC
DC
DC
—
—
—
—
8
MHz EC osc mode - 08 devices (8 MHz devices)
Fosc External CLKIN Frequency
16
25
33
MHz
MHz
MHz
- 16 devices (16 MHz devices)
- 25 devices (25 MHz devices)
- 33 devices (33 MHz devices)
(Note 1)
Oscillator Frequency
(Note 1)
DC
1
1
1
1
—
—
—
—
—
—
4
8
16
25
33
2
MHz RC osc mode
MHz XT osc mode - 08 devices (8 MHz devices)
MHz
MHz
- 16 devices (16 MHz devices)
- 25 devices (25 MHz devices)
- 33 devices (33 MHz devices)
MHz
DC
MHz LF osc mode
1
Tosc External CLKIN Period
125
62.5
40
—
—
—
—
—
—
—
—
ns
ns
ns
ns
EC osc mode - 08 devices (8 MHz devices)
- 16 devices (16 MHz devices)
(Note 1)
- 25 devices (25 MHz devices)
- 33 devices (33 MHz devices)
30.3
Oscillator Period
(Note 1)
250
125
62.5
40
30.3
500
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
RC osc mode
1,000
1,000
1,000
1,000
—
XT osc mode - 08 devices (8 MHz devices)
- 16 devices (16 MHz devices)
- 25 devices (25 MHz devices)
- 33 devices (33 MHz devices)
LF osc mode
2
3
4
TCY
Instruction Cycle Time
(Note 1)
121.2 4/Fosc
DC
ns
ns
ns
TosL, Clock in (OSC1)
TosH high or low time
10 ‡
—
—
—
—
EC oscillator
EC oscillator
TosR, Clock in (OSC1)
TosF rise or fall time
5 ‡
†
‡
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS30412C-page 184
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
OSC2 †
13
12
18
16
14
19
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
† In EC and RC modes only.
TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10
11
12
13
14
TosH2ckL OSC1↓ to CLKOUT↓
TosH2ckH OSC1↓ to CLKOUT↑
—
—
—
—
—
15 ‡
15 ‡
5 ‡
30 ‡
30 ‡
15 ‡
15 ‡
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
TckR
TckF
CLKOUT rise time
CLKOUT fall time
5 ‡
TckH2ioV CLKOUT ↑ to Port PIC17CR42/42A/43/
—
0.5TCY + 20 ‡
out valid
R43/44
PIC17LCR42/42A/43/
R43/44
—
—
—
—
0.5TCY + 50 ‡
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
15
TioV2ckH Port in valid before PIC17CR42/42A/43/
CLKOUT↑ R43/44
0.25TCY + 25 ‡
—
—
PIC17LCR42/42A/43/ 0.25TCY + 50 ‡
R43/44
16
17
18
TckH2ioI
Port in hold after CLKOUT↑
0 ‡
—
—
—
—
—
100 ‡
—
ns
ns
ns
TosH2ioV OSC1↓ (Q1 cycle) to Port out valid
TosH2ioI
OSC1↓ (Q2 cycle) to Port input invalid
0 ‡
(I/O in hold time)
19
TioV2osH Port input valid to OSC1↓
30 ‡
—
—
ns
(I/O in setup time)
20
21
22
23
TioR
Port output rise time
—
—
10 ‡
10 ‡
—
35 ‡
35 ‡
—
ns
ns
ns
ns
TioF
Port output fall time
TinHL
TrbHL
INT pin high or low time
RB7:RB0 change INT high or low time
25 *
25 *
—
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Measurements are taken in EC Mode where CLKOUT output is 4 x TOSC.
1996 Microchip Technology Inc.
DS30412C-page 185
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
35
Address /
Data
TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL
Twdt
MCLR Pulse Width (low)
100 *
5 *
—
—
ns
VDD = 5V
VDD = 5V
Watchdog Timer Time-out Period
(Prescale = 1)
12
25 *
ms
32
33
Tost
Oscillation Start-up Timer Period
Power-up Timer Period
—
1024TOSC§
96
—
ms TOSC = OSC1 period
Tpwrt
40 *
200 *
ms
ns
VDD = 5V
PIC17CR42/42A/
43/R43/44
35
TmcL2adI MCLR to System Inter-
face bus (AD15:AD0>)
invalid
—
—
—
—
100 *
120 *
PIC17LCR42/
42A/43/R43/44
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
§
These parameters are for design guidance only and are not tested, nor characterized.
This specification ensured by design.
DS30412C-page 186
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-5: TIMER0 CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 19-5: TIMER0 CLOCK REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width No Prescaler
0.5TCY + 20 §
—
—
ns
With Prescaler
Tt0L T0CKI Low Pulse Width No Prescaler
With Prescaler
10*
0.5TCY + 20 §
10*
—
—
—
—
—
—
—
—
ns
ns
ns
41
42
Tt0P T0CKI Period
Greater of:
ns N = prescale value
(1, 2, 4, ..., 256)
20 ns or Tcy + 40 §
N
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 19-6: TIMER1,TIMER2, AND TIMER3 CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 19-6: TIMER1,TIMER2, AND TIMER3 CLOCK REQUIREMENTS
Parameter
No.
Typ
†
Sym
Characteristic
Min
Max
Units Conditions
45
46
47
Tt123H TCLK12 and TCLK3 high time
Tt123L TCLK12 and TCLK3 low time
Tt123P TCLK12 and TCLK3 input period
0.5TCY + 20 §
0.5TCY + 20 §
—
—
—
—
—
—
ns
ns
TCY + 40 §
N
ns N = prescale value
(1, 2, 4, 8)
48
TckE2tmrI Delay from selected External Clock Edge to
Timer increment
2TOSC §
6Tosc §
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 187
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-7: CAPTURE TIMINGS
CAP1
and CAP2
(Capture Mode)
50
51
52
TABLE 19-7: CAPTURE REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ† Max Units Conditions
50
51
TccL Capture1 and Capture2 input low time
10 *
10 *
—
—
—
—
ns
ns
TccH
TccP
Capture1 and Capture2 input high time
Capture1 and Capture2 input period
52
2TCY §
N
—
—
ns N = prescale value
(4 or 16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 19-8: PWM TIMINGS
PWM1
and PWM2
(PWM Mode)
53
54
TABLE 19-8: PWM REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ† Max Units Conditions
53
54
TccR PWM1 and PWM2 output rise time
TccF PWM1 and PWM2 output fall time
—
—
10 * 35 *§ ns
10 * 35 *§ ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
DS30412C-page 188
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RA5/TX/CK
pin
121
121
RA4/RX/DT
pin
122
120
TABLE 19-9: SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ† Max Units Conditions
120
TckH2dtV SYNC XMIT (MASTER &
SLAVE)
PIC17CR42/42A/43/R43/44
PIC17LCR42/42A/43/R43/44
—
—
—
—
—
—
—
—
—
—
—
—
50
75
25
40
25
40
ns
ns
ns
ns
ns
ns
Clock high to data out valid
121
122
†
TckRF
TdtRF
Clock out rise time and fall time PIC17CR42/42A/43/R43/44
(Master Mode)
PIC17LCR42/42A/43/R43/44
Data out rise time and fall time PIC17CR42/42A/43/R43/44
PIC17LCR42/42A/43/R43/44
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 19-10: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RA5/TX/CK
125
pin
RA4/RX/DT
pin
126
TABLE 19-10: SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
15
—
—
ns
Data hold before CK↓ (DT hold time)
126
TckL2dtl
Data hold after CK↓ (DT hold time)
15
—
—
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1996 Microchip Technology Inc.
DS30412C-page 189
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-11: MEMORY INTERFACE WRITETIMING (NOT SUPPORTED IN PIC17LC4X DEVICES)
Q1
Q2
Q3
Q4
Q2
Q1
OSC1
ALE
OE
151
WR
150
addr out
154
data out
AD<15:0>
addr out
152
153
TABLE 19-11: MEMORY INTERFACE WRITE REQUIREMENTS (NOT SUPPORTED IN PIC17LC4X
DEVICES)
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
150
TadV2alL AD<15:0> (address) valid to ALE↓
0.25Tcy - 10
—
—
ns
(address setup time)
151
152
153
154
TalL2adI
ALE↓ to address out invalid
(address hold time)
0
—
—
—
—
—
ns
ns
ns
ns
TadV2wrL Data out valid to WR↓
0.25Tcy - 40
—
(data setup time)
TwrH2adI WR↑ to data out invalid
—
—
0.25TCY §
0.25TCY §
(data hold time)
TwrL
WR pulse width
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
DS30412C-page 190
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-12: MEMORY INTERFACE READ TIMING (NOT SUPPORTED IN PIC17LC4X DEVICES)
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
OE
164
168
160
165
161
Data in
162
AD<15:0>
WR
Addr out
150
Addr out
151
163
167
'1'
'1'
TABLE 19-12: MEMORY INTERFACE READ REQUIREMENTS (NOT SUPPORTED IN PIC17LC4X
DEVICES)
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
150
TadV2alL
AD15:AD0 (address) valid to ALE↓
0.25Tcy - 10
—
—
ns
(address setup time)
151
TalL2adI
ALE↓ to address out invalid
5*
—
—
ns
(address hold time)
160
161
162
TadZ2oeL
AD15:AD0 hi-impedance to OE↓
0*
0.25Tcy - 15
35
—
—
—
—
—
—
ns
ns
ns
ToeH2adD OE↑ to AD15:AD0 driven
TadV2oeH Data in valid before OE↑
(data setup time)
163
164
ToeH2adI
TalH
OE↑to data in invalid (data hold time)
0
—
—
—
ns
ns
ALE pulse width
—
0.25TCY §
165
166
167
ToeL
OE pulse width
0.5Tcy - 35 §
—
TCY §
—
—
—
ns
ns
ns
TalH2alH
Tacc
ALE↑ to ALE↑(cycle time)
Address access time
—
—
0.75TCY - 30
168
Toe
Output enable access time
(OE low to Data Valid)
—
—
0.5TCY - 45
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 191
PIC17C4X
NOTES:
DS30412C-page 192
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
20.0 PIC17CR42/42A/43/R43/44 DC AND AC CHARACTERISTICS
The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some
graphs or tables the data presented is outside specified operating range (e.g. outside specified VDD range). This is for
information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3σ) and (mean - 3σ)
respectively where σ is standard deviation.
TABLE 20-1: PIN CAPACITANCE PER PACKAGE TYPE
Typical Capacitance (pF)
Pin Name
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
All pins, except MCLR,
VDD, and VSS
10
10
10
10
MCLR pin
20
20
20
20
FIGURE 20-1: TYPICAL RC OSCILLATOR FREQUENCY vs.TEMPERATURE
FOSC
Frequency normalized to +25°C
FOSC (25°C)
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0
10
20
25
30
40
50
60
70
T(°C)
1996 Microchip Technology Inc.
DS30412C-page 193
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 10k
3.0
2.5
2.0
1.5
Cext = 22 pF, T = 25°C
1.0
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
FIGURE 20-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 3.3k
3.0
2.5
R = 5.1k
2.0
1.5
R = 10k
1.0
Cext = 100 pF, T = 25°C
0.5
0.0
R = 100k
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
DS30412C-page 194
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
R = 3.3k
R = 5.1k
R = 10k
0.4
0.2
Cext = 300 pF, T = 25°C
R = 160k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
TABLE 20-2: RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5V, 25°C
Cext
Rext
22 pF
10k
100k
3.3k
5.1k
10k
3.33 MHz
353 kHz
3.54 MHz
2.43 MHz
1.30 MHz
129 kHz
1.54 MHz
980 kHz
564 kHz
35 kHz
± 12%
± 13%
± 10%
± 14%
± 17%
± 10%
± 14%
± 12%
± 16%
± 18%
100 pF
300 pF
100k
3.3k
5.1k
10k
160k
1996 Microchip Technology Inc.
DS30412C-page 195
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD
500
450
400
350
Max @ -40°C
300
Typ @ 25°C
250
200
150
Min @ 85°C
100
50
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 20-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
20
18
Max @ -40°C
16
14
12
10
8
Typ @ 25°C
6
Min @ 85°C
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30412C-page 196
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-7: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C)
100000
10000
1000
100
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
4.0V
10
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
FIGURE 20-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125°C TO -40°C)
100000
10000
1000
100
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
4.0V
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
1996 Microchip Technology Inc.
DS30412C-page 197
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-9: TYPICAL IPD vs. VDD WATCHDOG DISABLED 25°C
12
10
8
6
4
2
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 20-10: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Temp. = 85°C
Temp. = 70°C
Temp. = 0°C
Temp. = -40°C
6.5 7.0
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30412C-page 198
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-11: TYPICAL IPD vs. VDD WATCHDOG ENABLED 25°C
30
25
20
15
10
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 20-12: MAXIMUM IPD vs. VDD WATCHDOG ENABLED
60
50
40
-40°C
0°C
70°C
85°C
30
20
10
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
1996 Microchip Technology Inc.
DS30412C-page 199
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-13: WDT TIMER TIME-OUT PERIOD vs. VDD
30
25
Max. 85°C
20
Max. 70°C
Min. 0°C
15
10
Typ. 25°C
Min. -40°C
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 20-14: IOH vs. VOH, VDD = 3V
0
-2
-4
-6
Min @ 85°C
-8
Typ @ 25°C
-10
-12
-14
Max @ -40°C
-16
-18
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD (Volts)
DS30412C-page 200
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-15: IOH vs. VOH, VDD = 5V
0
-5
-10
-15
-20
Min @ 85°C
Max @ -40°C
-25
Typ @ 25°C
-30
-35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (Volts)
FIGURE 20-16: IOL vs. VOL, VDD = 3V
30
Max. -40°C
25
20
Typ. 25°C
15
10
Min. +85°C
5
0
0.0
0.5
1.0
1.5
VDD (Volts)
2.0
2.5
3.0
1996 Microchip Technology Inc.
DS30412C-page 201
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-17: IOL vs. VOL, VDD = 5V
90
80
70
60
50
40
30
Max @ -40°C
Typ @ 25°C
Min @ +85°C
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD (Volts)
FIGURE 20-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD
2.0
1.8
Max (-40°C to +85°C)
1.6
Typ @ 25°C
1.4
1.2
1.0
Min (-40°C to +85°C)
0.8
0.6
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
5.5
6.0
DS30412C-page 202
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-19: VTH, VIL of I/O PINS (SCHMITT TRIGGER) VS. VDD
5.0
4.5
4.0
VIH, max (-40°C to +85°C)
VIH, typ (25°C)
VIH, min (-40°C to +85°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIL, max (-40°C to +85°C)
VIL, typ (25°C)
VIL, min (-40°C to +85°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 20-20: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT AND LF MODES) vs. VDD
3.4
3.2
Typ (25°C)
3.0
Max (-40°C to +85°C)
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
Min (-40°C to +85°C)
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
5.5
6.0
1996 Microchip Technology Inc.
DS30412C-page 203
PIC17C4X
NOTES:
DS30412C-page 204
1996 Microchip Technology Inc.
PIC17C4X
21.0 PACKAGING INFORMATION
21.1
40-Lead Ceramic CERDIP Dual In-line, and CERDIP Dual In-line with Window (600 mil)
N
E1
E
α
C
Pin No. 1
Indicator
Area
eA
eB
D
S
S1
e1
Base
Plane
Seating
Plane
L
B1
B
A
A3
A2
A1
D1
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Inches
Max
Symbol
Min
Max
Notes
Min
Notes
α
0°
10°
0°
10°
A
4.318
0.381
3.810
3.810
0.355
1.270
0.203
5.715
1.778
4.699
4.445
0.585
1.651
0.381
52.705
48.260
15.875
15.240
2.540
16.002
18.034
3.810
40
0.170
0.015
0.150
0.150
0.014
0.050
0.008
2.025
1.900
0.600
0.510
0.100
0.590
0.600
0.125
40
0.225
0.070
0.185
0.175
0.023
0.065
0.015
2.075
1.900
0.625
0.600
0.100
0.630
0.710
0.150
40
A1
A2
A3
B
B1
C
Typical
Typical
Typical
Typical
D
51.435
48.260
15.240
12.954
2.540
14.986
15.240
3.175
40
D1
E
Reference
Reference
E1
e1
eA
eB
L
Reference
Typical
Reference
Typical
N
S
1.016
0.381
2.286
1.778
0.040
0.015
0.090
0.070
S1
1996 Microchip Technology Inc.
DS30412C-page 205
PIC17C4X
21.2
40-Lead Plastic Dual In-line (600 mil)
N
α
E1
E
C
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
e1
Base
Plane
Seating
Plane
L
B1
B
A
A2
A1
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Inches
Symbol
Min
Max
Notes
Min
Max
Notes
α
0°
10°
5.080
–
0°
10°
0.200
–
A
–
–
A1
A2
B
0.381
3.175
0.355
1.270
0.203
0.015
0.125
0.014
0.050
0.008
2.015
1.900
0.600
0.530
0.098
0.600
0.600
0.115
40
4.064
0.559
1.778
0.381
52.197
48.260
15.875
13.970
2.591
15.240
17.272
3.683
40
0.160
0.022
0.070
0.015
2.055
1.900
0.625
0.550
0.102
0.600
0.680
0.145
40
B1
C
Typical
Typical
Typical
Typical
D
51.181
48.260
15.240
13.462
2.489
15.240
15.240
2.921
40
D1
E
Reference
Reference
E1
e1
eA
eB
L
Typical
Typical
Reference
Reference
N
S
1.270
0.508
–
0.050
0.020
–
S1
–
–
DS30412C-page 206
1996 Microchip Technology Inc.
PIC17C4X
21.3
44-Lead Plastic Leaded Chip Carrier (Square)
D
0.812/0.661
N Pics
.032/.026
1.27
.050
2 Sides
0.177
.007
S
B D-E S
-A-
0.177
.007
2 Sides
-H-
B A S
9
S
A
D1
A1
-D-
3
D3/E3
D2
0.101
.004
Seating
Plane
D
0.38
.015
-C-
F-G
E2
S
S
3
-G-
4
4
3
-F-
8
E1
E
0.38
.015
F-G
-B-
-E-
3
0.177
.007
A F-G S
S
10
0.812/0.661
.032/.026
3
0.254
.010
0.254
.010
11
Max
Max
11
1.524
.060
0.508
.020
0.508
.020
Min
-H-
2
-H-
2
6
6
-C-
5
1.651
.065
1.651
.065
0.64
.025
0.533/0.331
.021/.013
Min
R
R
1.14/0.64
.045/.025
1.14/0.64
.045/.025
0.177
.007
D-E
S
F-G S ,
A
M
Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Inches
Max
Symbol
Min
Max
Notes
Min
Notes
A
A1
D
4.191
2.413
17.399
16.510
15.494
12.700
17.399
16.510
15.494
12.700
44
4.572
2.921
0.165
0.095
0.685
0.650
0.610
0.500
0.685
0.650
0.610
0.500
44
0.180
0.115
0.695
0.656
0.630
0.500
0.695
0.656
0.630
0.500
44
17.653
16.663
16.002
12.700
17.653
16.663
16.002
12.700
44
D1
D2
D3
E
Reference
Reference
Reference
Reference
E1
E2
E3
N
CP
LT
–
0.102
–
0.004
0.015
0.203
0.381
0.008
1996 Microchip Technology Inc.
DS30412C-page 207
PIC17C4X
21.4
44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form)
0.20 M C A-B S D S
D
4
5
0.20 M H A-B S D S
0.05 mm/mm A-B
D1
7
0.20 min.
D3
0.13 R min.
Index
area
6
PARTING
LINE
0.13/0.30 R
b
α
9
L
C
E3
E1
E
1.60 Ref.
0.20 M C A-B S D S
4
TYP 4x
10
0.20 M H A-B S D S
5
7
e
B
0.05 mm/mm
D
A2
A
Base
Plane
Seating
Plane
A1
Package Group: Plastic MQFP
Millimeters
Max
Inches
Max
Symbol
Min
Notes
Min
Notes
α
A
0°
7°
0°
7°
2.000
0.050
1.950
0.300
0.150
12.950
9.900
8.000
12.950
9.900
8.000
0.800
0.730
44
2.350
0.250
2.100
0.450
0.180
13.450
10.100
8.000
13.450
10.100
8.000
0.800
1.030
44
0.078
0.002
0.768
0.011
0.006
0.510
0.390
0.315
0.510
0.390
0.315
0.031
0.028
44
0.093
0.010
0.083
0.018
0.007
0.530
0.398
0.315
0.530
0.398
0.315
0.032
0.041
44
A1
A2
b
Typical
Typical
C
D
D1
D3
E
Reference
Reference
Reference
Reference
E1
E3
e
L
N
CP
0.102
–
0.004
–
DS30412C-page 208
1996 Microchip Technology Inc.
PIC17C4X
21.5
44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form)
D
D1
1.0ø (0.039ø) Ref.
11°/13°(4x)
0° Min
Pin#1
2
Pin#1
2
E
E1
Θ
11°/13°(4x)
Detail B
e
3.0ø (0.118ø) Ref.
R 1 0.08 Min
R 0.08/0.20
Option 1 (TOP side)
Option 2 (TOP side)
Gage Plane
0.250
A1
Base Metal
Lead Finish
b
A2
A
S
0.20
Min
L
L
c
c1
L1
Detail A
Detail B
1.00 Ref
1.00 Ref.
b1
Detail A
Detail B
Package Group: Plastic TQFP
Millimeters
Max
Inches
Max
Symbol
Min
Notes
Min
Notes
A
A1
A2
D
1.00
0.05
0.95
11.75
9.90
11.75
9.90
0.45
1.20
0.15
0.039
0.002
0.037
0.463
0.390
0.463
0.390
0.018
0.047
0.006
0.041
0.482
0.398
0.482
0.398
0.030
1.05
12.25
10.10
12.25
10.10
0.75
D1
E
E1
L
e
0.80 BSC
0.031 BSC
b
0.30
0.30
0.09
0.09
44
0.45
0.40
0.20
0.16
44
0.012
0.012
0.004
0.004
44
0.018
0.016
0.008
0.006
44
b1
c
c1
N
Θ
0°
7°
0°
7°
Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per
side. D1 and E1 dimensions including mold mismatch.
2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m
(0.003”)max.
3: This outline conforms to JEDEC MS-026.
1996 Microchip Technology Inc.
DS30412C-page 209
PIC17C4X
21.6
Package Marking Information
40-Lead PDIP/CERDIP
Example
PIC17C43-25I/P
L006
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
AABBCDE
9441CCA
40 Lead CERDIP Windowed
Example
XXXXXXXXXXX
PIC17C44
XXXXXXXXXXX
XXXXXXXXXXX
/JW
L184
AABBCDE
9444CCT
44-Lead PLCC
Example
XXXXXXXXXX
PIC17C42
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
-16I/L
L013
9445CCN
44-Lead MQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
PIC17C44
-25/PT
L247
AABBCDE
9450CAT
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
PIC17C44
-25/TQ
L247
AABBCDE
9450CAT
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A.
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales
Office. For QTP devices, any special marking adders are included in QTP
price.
DS30412C-page 210
1996 Microchip Technology Inc.
PIC17C4X
APPENDIX A:MODIFICATIONS
APPENDIX B:COMPATIBILITY
The following is the list of modifications over the
PIC16CXX microcontroller family:
To convert code written for PIC16CXX to PIC17CXX,
the user should take the following steps:
1. Instruction word length is increased to 16-bit.
This allows larger page sizes both in program
memory (8 Kwords verses 2 Kwords) and regis-
ter file (256 bytes versus 128 bytes).
1. Remove any TRIS and OPTION instructions,
and implement the equivalent code.
2. Separate the interrupt service routine into its
four vectors.
2. Four modes of operation: microcontroller, pro-
tected microcontroller, extended microcontroller,
and microprocessor.
3. Replace:
MOVF
with:
REG1, W
3. 22 new instructions.
MOVFP
REG1, WREG
The MOVF, TRISand OPTIONinstructions have
been removed.
4. Replace:
MOVF
REG1, W
REG2
4. 4 new instructions for transferring data between
data memory and program memory.This can be
used to “self program” the EPROM program
memory.
MOVWF
with:
MOVPF
or
REG1, REG2 ; Addr(REG1)<20h
MOVFP
REG1, REG2 ; Addr(REG2)<20h
5. Single cycle data memory to data memory trans-
fers possible (MOVPF and MOVFP instructions).
These instructions do not affect the Working reg-
ister (WREG).
Note: If REG1 and REG2 are both at addresses
greater then 20h, two instructions are
required.
6. W register (WREG) is now directly addressable.
MOVFP
MOVPF
REG1, WREG ;
WREG, REG2 ;
7. A PC high latch register (PCLATH) is extended
to 8-bits. The PCLATCH register is now both
readable and writable.
5. Ensure that all bit names and register names are
updated to new data memory map location.
8. Data memory paging is redefined slightly.
6. Verify data memory banking.
9. DDR registers replaces function of TRIS regis-
ters.
7. Verify mode of operation for indirect addressing.
8. Verify peripheral routines for compatibility.
9. Weak pull-ups are enabled on reset.
10. Multiple Interrupt vectors added. This can
decrease the latency for servicing the interrupt.
To convert code from the PIC17C42 to all the other
PIC17C4X devices, the user should take the following
steps.
11. Stack size is increased to 16 deep.
12. BSR register for data memory paging.
13. Wake up from SLEEP operates slightly differ-
ently.
1. If the hardware multiply is to be used, ensure
that any variables at address 18h and 19h are
moved to another address.
14. The Oscillator Start-Up Timer (OST) and
Power-Up Timer (PWRT) operate in parallel and
not in series.
2. Ensure that the upper nibble of the BSR was not
written with a non-zero value. This may cause
unexpected operation since the RAM bank is no
longer 0.
15. PORTB interrupt on change feature works on all
eight port pins.
16. TMR0 is 16-bit plus 8-bit prescaler.
3. The disabling of global interrupts has been
enhanced so there is no additional testing of the
GLINTD bit after a BSF CPUSTA, GLINTD
instruction.
17. Second indirect addressing register added
(FSR1 and FSR2). Configuration bits can select
the FSR registers to auto-increment, auto-dec-
rement, remain unchanged after an indirect
address.
18. Hardware multiplier added (8 x 8 → 16-bit)
(PIC17C43 and PIC17C44 only).
19. Peripheral modules operate slightly differently.
20. Oscillator modes slightly redefined.
21. Control/Status bits and registers have been
placed in different registers and the control bit
for globally enabling interrupts has inverse
polarity.
22. Addition of a test mode pin.
23. In-circuit serial programming is not imple-
mented.
1996 Microchip Technology Inc.
DS30412C-page 211
PIC17C4X
APPENDIX C:WHAT’S NEW
APPENDIX D:WHAT’S CHANGED
The structure of the document has been made consis-
tent with other data sheets.This ensures that important
topics are covered across all PIC16/17 families. Here is
an overview of new features.
To make software more portable across the different
PIC16/17 families, the name of several registers and
control bits have been changed.This allows control bits
that have the same function, to have the same name
(regardless of processor family). Care must still be
taken, since they may not be at the same special func-
tion register address. The following shows the register
and bit names that have been changed:
Added the following devices:
PIC17CR42
PIC17C42A
PIC17CR43
Old Name
New Name
A 33 MHz option is now available.
TX8/9
RC8/9
RCD8
TXD8
TX9
RX9
RX9D
TX9D
Instruction DECFSNZ corrected to DCFSNZ
Instruction INCFSNZ corrected to INFSNZ
Enhanced discussion on PWM to include equation for
determining bits of PWM resolution.
Section 13.2.2 and 13.3.2 have had the description of
updating the FERR and RX9 bits enhanced.
The location of configuration bit PM2 was changed
(Figure 6-1 and Figure 14-1).
Enhanced description of the operation of the INTSTA
register.
Added note to discussion of interrupt operation.
Tightened electrical spec D110.
Corrected steps for setting up USART Asynchronous
Reception.
DS30412C-page 212
1996 Microchip Technology Inc.
PIC17C4X
APPENDIX E: PIC16/17 MICROCONTROLLERS
E.1
PIC14000 Devices
1996 Microchip Technology Inc.
DS30412C-page 213
PIC17C4X
E.2
PIC16C5X Family of Devices
DS30412C-page 214
1996 Microchip Technology Inc.
PIC17C4X
E.3
PIC16CXXX Family of Devices
1996 Microchip Technology Inc.
DS30412C-page 215
PIC17C4X
E.4
PIC16C6X Family of Devices
DS30412C-page 216
1996 Microchip Technology Inc.
PIC17C4X
E.5
PIC16C7X Family of Devices
1996 Microchip Technology Inc.
DS30412C-page 217
PIC17C4X
E.6
PIC16C8X Family of Devices
DS30412C-page 218
1996 Microchip Technology Inc.
PIC17C4X
E.7
PIC16C9XX Family Of Devices
1996 Microchip Technology Inc.
DS30412C-page 219
PIC17C4X
E.8
PIC17CXX Family of Devices
DS30412C-page 220
1996 Microchip Technology Inc.
PIC17C4X
PIN COMPATIBILITY
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE E-1:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC12C508, PIC12C509
8-pin
PIC16C54, PIC16C54A,
PIC16CR54A,
18-pin
20-pin
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622,
PIC16C710, PIC16C71, PIC16C711,
PIC16F83, PIC16CR83,
PIC16C84, PIC16F84A, PIC16CR84
PIC16C55,
PIC16C57, PIC16CR57B
28-pin
28-pin
40-pin
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63,
PIC16C72, PIC16C73, PIC16C73A
PIC16C64, PIC16CR64, PIC16C64A,
PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
PIC17C42, PIC17CR42, PIC17C42A,
PIC17C43, PIC17CR43, PIC17C44
40-pin
PIC16C923, PIC16C924
64/68-pin
1996 Microchip Technology Inc.
DS30412C-page 221
PIC17C4X
NOTES:
DS30412C-page 222
1996 Microchip Technology Inc.
PIC17C4X
Design considerations
APPENDIX F: ERRATA FOR
PIC17C42 SILICON
The PIC17C42 devices that you have received have the
following anomalies. At present there is no intention for
future revisions to the present PIC17C42 silicon. If
these cause issues for the application, it is recom-
mended that you select the PIC17C42A device.
The device must not be operated outside of the speci-
fied voltage range. An external reset circuit must be
used to ensure the device is in reset when a brown-out
occurs or the VDD rise time is too long. Failure to
ensure that the device is in reset when device voltage
is out of specification may cause the device to lock-up
and ignore the MCLR pin.
Note: New designs should use the PIC17C42A.
1. When the Oscillator Start-Up Timer (OST) is
enabled (in LF or XT oscillator modes), any inter-
rupt that wakes the processor may cause a WDT
reset.This occurs when the WDT is greater than
or equal to 50% time-out period when theSLEEP
instruction is executed. This will not occur in
either the EC or RC oscillator modes.
Work-arounds
a) Always ensure that the CLRWDT instruction is
executed before the WDT increments past 50%
of the WDT period. This will keep the “false”
WDT reset from occurring.
b) When using the WDT as a normal timer (WDT
disabled), ensure that the WDT is less than or
equal to 50% time-out period when the SLEEP
instruction is executed. This can be done by
monitoring the TO bit for changing state from set
to clear. Example 1 shows putting the PIC17C42
to sleep.
EXAMPLE F-1: PIC17C42 TO SLEEP
BTFSS
CLRWDT
LOOP BTFSC
GOTO
CPUSTA, TO ; TO = 0?
; YES, WDT = 0
CPUSTA, TO ; WDT rollover?
LOOP
; NO, Wait
SLEEP
; YES, goto Sleep
2. When the clock source of Timer1 or Timer2 is
selected to external clock, the overflow interrupt
flag will be set twice, once when the timer equals
the period, and again when the timer value is
reset to 0h. If the latency to clear TMRxIF is
greater than the time to the next clock pulse, no
problems will be noticed. If the latency is less
than the time to the next timer clock pulse, the
interrupt will be serviced twice.
Work-arounds
a) Ensure that the timer has rolled over to 0h before
clearing the flag bit.
b) Clear the timer in software. Clearing the timer in
software causes the period to be one count less
than expected.
1996 Microchip Technology Inc.
DS30412C-page 223
PIC17C4X
NOTES:
DS30412C-page 224
1996 Microchip Technology Inc.
PIC17C4X
CA1IE .................................................................................23
CA1IF .................................................................................24
CA1OVF .............................................................................72
CA2ED0 ..............................................................................71
CA2ED1 ..............................................................................71
CA2H ............................................................................20, 35
CA2IE ...........................................................................23, 78
CA2IF ...........................................................................24, 78
CA2L .............................................................................20, 35
CA2OVF .............................................................................72
Calculating Baud Rate Error ...............................................86
CALL ...........................................................................39, 117
Capacitor Selection
Ceramic Resonators .................................................101
Crystal Oscillator ......................................................101
Capture .........................................................................71, 78
Capture Sequence to Read Example .................................78
Capture1
Mode ...........................................................................71
Overflow .....................................................................72
Capture2
Mode ...........................................................................71
Overflow .....................................................................72
Carry (C) ...............................................................................9
Ceramic Resonators .........................................................100
Circular Buffer .....................................................................39
Clearing the Prescaler ......................................................103
Clock/Instruction Cycle (Figure) .........................................14
Clocking Scheme/Instruction Cycle (Section) .....................14
CLRF ................................................................................117
CLRWDT ..........................................................................118
Code Protection ..........................................................99, 106
COMF ...............................................................................118
Configuration
Bits ............................................................................100
Locations ..................................................................100
Oscillator ...................................................................100
Word ...........................................................................99
CPFSEQ ...........................................................................119
CPFSGT ...........................................................................119
CPFSLT ............................................................................120
CPU STATUS Register (CPUSTA) ....................................37
CPUSTA ...............................................................34, 37, 105
CREN .................................................................................84
Crystal Operation, Overtone Crystals ...............................101
Crystal or Ceramic Resonator Operation .........................100
Crystal Oscillator ..............................................................100
CSRC .................................................................................83
INDEX
A
ADDLW ............................................................................ 112
ADDWF ............................................................................ 112
ADDWFC ......................................................................... 113
ALU ...................................................................................... 9
ALU STATUS Register (ALUSTA) ..................................... 36
ALUSTA ............................................................... 34, 36, 108
ALUSTA Register ............................................................... 36
ANDLW ............................................................................ 113
ANDWF ............................................................................ 114
Application Notes
AN552 ........................................................................ 55
Assembler ........................................................................ 144
Asynchronous Master Transmission .................................. 90
Asynchronous Transmitter ................................................. 89
B
Bank Select Register (BSR) ............................................... 42
Banking .............................................................................. 42
Baud Rate Formula ............................................................ 86
Baud Rate Generator (BRG) .............................................. 86
Baud Rates
Asynchronous Mode .................................................. 88
Synchronous Mode .................................................... 87
BCF .................................................................................. 114
Bit Manipulation ............................................................... 108
Block Diagrams
On-chip Reset Circuit ................................................. 15
PIC17C42 .................................................................. 10
PORTD ...................................................................... 60
PORTE ....................................................................... 62
PWM .......................................................................... 75
RA0 and RA1 ............................................................. 53
RA2 and RA3 ............................................................. 54
RA4 and RA5 ............................................................. 54
RB3:RB2 Port Pins .................................................... 56
RB7:RB4 and RB1:RB0 Port Pins ............................. 55
RC7:RC0 Port Pins .................................................... 58
Timer3 with One Capture and One Period Register .. 78
TMR1 and TMR2 in 16-bit Timer/Counter Mode ........ 74
TMR1 and TMR2 in Two 8-bit Timer/Counter Mode .. 73
TMR3 with Two Capture Registers ............................ 79
WDT ......................................................................... 104
BORROW ............................................................................ 9
BRG ................................................................................... 86
Brown-out Protection ......................................................... 18
BSF .................................................................................. 115
BSR .............................................................................. 34, 42
BSR Operation ................................................................... 42
BTFSC ............................................................................. 115
BTFSS ............................................................................. 116
BTG .................................................................................. 116
D
Data Memory
GPR ......................................................................29, 32
Indirect Addressing .....................................................39
Organization ...............................................................32
SFR ......................................................................29, 32
Transfer to Program Memory .....................................43
DAW .................................................................................120
DC ..................................................................................9, 36
DDRB .....................................................................19, 34, 55
DDRC .....................................................................19, 34, 58
DDRD .....................................................................19, 34, 60
DDRE .....................................................................19, 34, 62
DECF ................................................................................121
DECFSNZ .........................................................................122
DECFSZ ...........................................................................121
C
C .................................................................................... 9, 36
C Compiler (MP-C) .......................................................... 145
CA1/PR3 ............................................................................ 72
CA1ED0 ............................................................................. 71
CA1ED1 ............................................................................. 71
1996 Microchip Technology Inc.
DS30412C-page 225
PIC17C4X
Delay From External Clock Edge ....................................... 68
Development Support ...................................................... 143
Development Tools .......................................................... 143
Device Drawings
FOSC1 ............................................................................... 99
FS0 .................................................................................... 36
FS1 .................................................................................... 36
FS2 .................................................................................... 36
FS3 .................................................................................... 36
FSR0 ............................................................................ 34, 40
FSR1 ............................................................................ 34, 40
Fuzzy Logic Dev. System (fuzzyTECH -MP) .......... 143, 145
44-Lead Plastic Surface Mount (MQFP
10x10 mm Body 1.6/0.15 mm Lead Form) .............. 209
DIGIT BORROW .................................................................. 9
Digit Carry (DC) .................................................................... 9
Duty Cycle .......................................................................... 75
G
E
General Format for Instructions ....................................... 108
General Purpose RAM ....................................................... 29
General Purpose RAM Bank ............................................. 42
General Purpose Register (GPR) ...................................... 32
GLINTD .......................................................... 25, 37, 78, 105
GOTO .............................................................................. 122
GPR (General Purpose Register) ...................................... 32
Graphs
Electrical Characteristics
PIC17C42
Absolute Maximum Ratings ............................. 147
Capture Timing ................................................ 159
CLKOUT and I/O Timing .................................. 156
DC Characteristics ........................................... 149
External Clock Timing ...................................... 155
Memory Interface Read Timing ........................ 162
Memory Interface Write Timing ........................ 161
PWM Timing .................................................... 159
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer .............................. 157
Timer0 Clock Timings ...................................... 158
Timer1, Timer2 and Timer3 Clock Timing ........ 158
USART Module, Synchronous Receive ........... 160
USART Module, Synchronous Transmission ... 160
PIC17C43/44
IOH vs. VOH, VDD = 3V ..................................... 170, 200
IOH vs. VOH, VDD = 5V ..................................... 171, 201
IOL vs. VOL, VDD = 3V ...................................... 171, 201
IOL vs. VOL, VDD = 5V ...................................... 172, 202
Maximum IDD vs. Frequency
(External Clock 125°C to -40°C) ...................... 167, 197
Maximum IPD vs. VDD Watchdog Disabled ...... 168, 198
Maximum IPD vs. VDD Watchdog Enabled ...... 169, 199
RC Oscillator Frequency vs.
VDD (Cext = 100 pF) ........................................ 164, 194
RC Oscillator Frequency vs.
VDD (Cext = 22 pF) .......................................... 164, 194
RC Oscillator Frequency vs.
VDD (Cext = 300 pF) ........................................ 165, 195
Transconductance of LF Oscillator vs.VDD ...... 166, 196
Transconductance of XT Oscillator vs. VDD .... 166, 196
Typical IDD vs. Frequency
(External Clock 25°C) ...................................... 167, 197
Typical IPD vs. VDD Watchdog Disabled 25°C . 168, 198
Typical IPD vs. VDD Watchdog Enabled 25°C .. 169, 199
Typical RC Oscillator vs. Temperature ............ 163, 193
VTH (Input Threshold Voltage) of I/O Pins vs.
Absolute Maximum Ratings ............................. 175
Capture Timing ................................................ 188
CLKOUT and I/O Timing .................................. 185
DC Characteristics ........................................... 177
External Clock Timing ...................................... 184
Memory Interface Read Timing ........................ 191
Memory Interface Write Timing ........................ 190
Parameter Measurement Information .............. 183
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing .................. 186
Timer0 Clock Timing ........................................ 187
Timer1, Timer2 and Timer3 Clock Timing ........ 187
Timing Parameter Symbology .......................... 182
USART Module Synchronous Receive
VDD .................................................................. 172, 202
VTH (Input Threshold Voltage) of OSC1 Input
Timing .............................................................. 189
USART Module Synchronous Transmission
(In XT, HS, and LP Modes) vs. VDD ................ 173, 203
VTH, VIL of MCLR, T0CKI and OSC1
Timing .............................................................. 189
EPROM Memory Access Time Order Suffix ...................... 31
Extended Microcontroller ................................................... 29
Extended Microcontroller Mode ......................................... 31
External Memory Interface ................................................. 31
External Program Memory Waveforms .............................. 31
(In RC Mode) vs. VDD ...................................... 173, 203
WDT Timer Time-Out Period vs. VDD .............. 170, 200
H
Hardware Multiplier ............................................................ 49
F
I
Family of Devices ................................................................. 6
PIC14000.................................................................. 213
PIC16C5X ................................................................ 214
PIC16CXXX .............................................................. 215
PIC16C6X ................................................................ 216
PIC16C7X ................................................................ 217
PIC16C8X ................................................................ 218
PIC16C9XX............................................................... 219
PIC17CXX ................................................................ 220
FERR ........................................................................... 84, 91
FOSC0 ............................................................................... 99
I/O Ports
Bi-directional .............................................................. 64
I/O Ports .................................................................... 53
Programming Considerations .................................... 64
Read-Modify-Write Instructions ................................. 64
Successive Operations .............................................. 64
INCF ................................................................................ 123
INCFSNZ ......................................................................... 124
INCFSZ ............................................................................ 123
INDF0 .......................................................................... 34, 40
INDF1 .......................................................................... 34, 40
DS30412C-page 226
1996 Microchip Technology Inc.
PIC17C4X
Indirect Addressing
Indirect Addressing .................................................... 39
TSTFSZ ....................................................................140
XORLW ....................................................................141
XORWF ....................................................................141
Instruction Set Summary ..................................................107
INT Pin ................................................................................26
INTE ...................................................................................22
INTEDG ........................................................................38, 67
Interrupt on Change Feature ..............................................55
Interrupt Status Register (INTSTA) ....................................22
Interrupts
Operation ................................................................... 40
Registers .................................................................... 40
Initialization Conditions For Special Function Registers .... 19
Initializing PORTB .............................................................. 57
Initializing PORTC .............................................................. 58
Initializing PORTD .............................................................. 60
Initializing PORTE .............................................................. 62
Instruction Flow/Pipelining ................................................. 14
Instruction Set .................................................................. 110
ADDLW .................................................................... 112
ADDWF .................................................................... 112
ADDWFC ................................................................. 113
ANDLW .................................................................... 113
ANDWF .................................................................... 114
BCF .......................................................................... 114
BSF .......................................................................... 115
BTFSC ..................................................................... 115
BTFSS ..................................................................... 116
BTG .......................................................................... 116
CALL ........................................................................ 117
CLRF ........................................................................ 117
CLRWDT .................................................................. 118
COMF ...................................................................... 118
CPFSEQ .................................................................. 119
CPFSGT .................................................................. 119
CPFSLT ................................................................... 120
DAW ......................................................................... 120
DECF ....................................................................... 121
DECFSNZ ................................................................ 122
DECFSZ ................................................................... 121
GOTO ...................................................................... 122
INCF ......................................................................... 123
INCFSNZ ................................................................. 124
INCFSZ .................................................................... 123
IORLW ..................................................................... 124
IORWF ..................................................................... 125
LCALL ...................................................................... 125
MOVFP .................................................................... 126
MOVLB .................................................................... 126
MOVLR .................................................................... 127
MOVLW ................................................................... 127
MOVPF .................................................................... 128
MOVWF ................................................................... 128
MULLW .................................................................... 129
MULWF .................................................................... 129
NEGW ...................................................................... 130
NOP ......................................................................... 130
RETFIE .................................................................... 131
RETLW .................................................................... 131
RETURN .................................................................. 132
RLCF ........................................................................ 132
RLNCF ..................................................................... 133
RRCF ....................................................................... 133
RRNCF .................................................................... 134
SETF ........................................................................ 134
SLEEP ..................................................................... 135
SUBLW .................................................................... 135
SUBWF .................................................................... 136
SUBWFB .................................................................. 136
SWAPF .................................................................... 137
TABLRD ........................................................... 137, 138
TABLWT .......................................................... 138, 139
TLRD ........................................................................ 139
TLWT ....................................................................... 140
Context Saving ...........................................................27
Flag bits
TMR1IE ..............................................................21
TMR1IF ..............................................................21
TMR2IE ..............................................................21
TMR2IF ..............................................................21
TMR3IE ..............................................................21
TMR3IF ..............................................................21
Interrupts ....................................................................21
Logic ...........................................................................21
Operation ....................................................................25
Peripheral Interrupt Enable .........................................23
Peripheral Interrupt Request ......................................24
PWM ...........................................................................76
Status Register ...........................................................22
Table Write Interaction ...............................................45
Timing .........................................................................26
Vectors
Peripheral Interrupt .............................................26
RA0/INT Interrupt ...............................................26
T0CKI Interrupt ...................................................26
TMR0 Interrupt ...................................................26
Vectors/Priorities ........................................................25
Wake-up from SLEEP ..............................................105
INTF ....................................................................................22
INTSTA ...............................................................................34
INTSTA Register ................................................................22
IORLW ..............................................................................124
IORWF ..............................................................................125
L
LCALL ...............................................................................125
Long Writes ........................................................................45
M
Memory
External Interface .......................................................31
External Memory Waveforms .....................................31
Memory Map (Different Modes) ..................................30
Mode Memory Access ................................................30
Organization ...............................................................29
Program Memory ........................................................29
Program Memory Map ................................................29
Microcontroller ....................................................................29
Microprocessor ...................................................................29
Minimizing Current Consumption .....................................106
MOVFP .............................................................................126
MOVLB .............................................................................126
MOVLR .............................................................................127
MOVLW ............................................................................127
MOVPF .............................................................................128
MOVWF ............................................................................128
MPASM Assembler ..................................................143, 144
1996 Microchip Technology Inc.
DS30412C-page 227
PIC17C4X
MP-C C Compiler ............................................................. 145
MPSIM Software Simulator ...................................... 143, 145
MULLW ............................................................................ 129
Multiply Examples
16 x 16 Routine .......................................................... 50
16 x 16 Signed Routine .............................................. 51
8 x 8 Routine .............................................................. 49
8 x 8 Signed Routine .................................................. 49
MULWF ............................................................................ 129
PORTD .................................................................. 19, 34, 60
PORTE .................................................................. 19, 34, 62
Power-down Mode ........................................................... 105
Power-on Reset (POR) ................................................ 15, 99
Power-up Timer (PWRT) ............................................. 15, 99
PR1 .............................................................................. 20, 35
PR2 .............................................................................. 20, 35
PR3/CA1H ......................................................................... 20
PR3/CA1L .......................................................................... 20
PR3H/CA1H ....................................................................... 35
PR3L/CA1L ........................................................................ 35
Prescaler Assignments ...................................................... 69
PRO MATE Universal Programmer ............................... 143
PRODH .............................................................................. 20
PRODL .............................................................................. 20
Program Counter (PC) ....................................................... 41
Program Memory
N
NEGW .............................................................................. 130
NOP ................................................................................. 130
O
External Access Waveforms ...................................... 31
External Connection Diagram .................................... 31
Map ............................................................................ 29
Modes
OERR ................................................................................. 84
Opcode Field Descriptions ............................................... 107
OSC Selection .................................................................... 99
Oscillator
Extended Microcontroller ................................... 29
Microcontroller ................................................... 29
Microprocessor .................................................. 29
Protected Microcontroller ................................... 29
Configuration ............................................................ 100
Crystal ...................................................................... 100
External Clock .......................................................... 101
External Crystal Circuit ............................................ 102
External Parallel Resonant Crystal Circuit ............... 102
External Series Resonant Crystal Circuit ................. 102
RC ............................................................................ 102
RC Frequencies ............................................... 165, 195
Oscillator Start-up Time (Figure) ........................................ 18
Oscillator Start-up Timer (OST) ................................... 15, 99
OST .............................................................................. 15, 99
OV .................................................................................. 9, 36
Overflow (OV) ...................................................................... 9
Operation ................................................................... 29
Organization .............................................................. 29
Transfers from Data Memory ..................................... 43
Protected Microcontroller ................................................... 29
PS0 .............................................................................. 38, 67
PS1 .............................................................................. 38, 67
PS2 .............................................................................. 38, 67
PS3 .............................................................................. 38, 67
PUSH ........................................................................... 27, 39
PW1DCH ..................................................................... 20, 35
PW1DCL ...................................................................... 20, 35
PW2DCH ..................................................................... 20, 35
PW2DCL ...................................................................... 20, 35
PWM ............................................................................ 71, 75
Duty Cycle ................................................................. 76
External Clock Source ............................................... 76
Frequency vs. Resolution .......................................... 76
Interrupts ................................................................... 76
Max Resolution/Frequency for External
Clock Input ................................................................. 77
Output ........................................................................ 75
Periods ...................................................................... 76
PWM1 ................................................................................ 72
PWM1ON ..................................................................... 72, 75
PWM2 ................................................................................ 72
PWM2ON ..................................................................... 72, 75
PWRT .......................................................................... 15, 99
P
Package Marking Information .......................................... 210
Packaging Information ..................................................... 205
Parameter Measurement Information .............................. 154
PC (Program Counter) ....................................................... 41
PCH .................................................................................... 41
PCL ...................................................................... 34, 41, 108
PCLATH ....................................................................... 34, 41
PD .............................................................................. 37, 105
PEIE ............................................................................. 22, 78
PEIF ................................................................................... 22
Peripheral Bank .................................................................. 42
Peripheral Interrupt Enable ................................................ 23
Peripheral Interrupt Request (PIR) ..................................... 24
PICDEM-1 Low-Cost PIC16/17 Demo Board ........... 143, 144
PICDEM-2 Low-Cost PIC16CXX Demo Board ........ 143, 144
PICDEM-3 Low-Cost PIC16C9XXX Demo Board ............ 144
PICMASTER RT In-Circuit Emulator ............................. 143
PICSTART Low-Cost Development System .................. 143
PIE .............................................................19, 34, 92, 96, 98
Pin Compatible Devices ................................................... 221
PIR .............................................................19, 34, 92, 96, 98
PM0 ............................................................................ 99, 106
PM1 ............................................................................ 99, 106
POP .............................................................................. 27, 39
POR ............................................................................. 15, 99
PORTA ................................................................... 19, 34, 53
PORTB ................................................................... 19, 34, 55
PORTC ................................................................... 19, 34, 58
R
RA1/T0CKI pin ................................................................... 67
RBIE .................................................................................. 23
RBIF ................................................................................... 24
RBPU ................................................................................. 55
RC Oscillator .................................................................... 102
RC Oscillator Frequencies ....................................... 165, 195
RCIE .................................................................................. 23
RCIF .................................................................................. 24
RCREG ................................................ 19, 34, 91, 92, 96, 97
RCSTA ....................................................... 19, 34, 92, 96, 98
Reading 16-bit Value ......................................................... 69
DS30412C-page 228
1996 Microchip Technology Inc.
PIC17C4X
Receive Status and Control Register ................................. 83
Register File Map ............................................................... 33
Registers
SWAPF .............................................................................137
SYNC ..................................................................................83
Synchronous Master Mode .................................................93
Synchronous Master Reception .........................................95
Synchronous Master Transmission ....................................93
Synchronous Slave Mode ...................................................97
ALUSTA ............................................................... 27, 36
BRG ........................................................................... 86
BSR ............................................................................ 27
CPUSTA .................................................................... 37
File Map ..................................................................... 33
FSR0 .......................................................................... 40
FSR1 .......................................................................... 40
INDF0 ......................................................................... 40
INDF1 ......................................................................... 40
INTSTA ...................................................................... 22
PIE ............................................................................. 23
PIR ............................................................................. 24
RCSTA ....................................................................... 84
Special Function Table .............................................. 34
T0STA .................................................................. 38, 67
TCON1 ....................................................................... 71
TCON2 ....................................................................... 72
TMR1 ......................................................................... 81
TMR2 ......................................................................... 81
TMR3 ......................................................................... 81
TXSTA ....................................................................... 83
WREG ........................................................................ 27
Reset
Section ....................................................................... 15
Status Bits and Their Significance ............................. 16
Time-Out in Various Situations .................................. 16
Time-Out Sequence ................................................... 16
RETFIE ............................................................................ 131
RETLW ............................................................................ 131
RETURN .......................................................................... 132
RLCF ................................................................................ 132
RLNCF ............................................................................. 133
RRCF ............................................................................... 133
RRNCF ............................................................................ 134
RX Pin Sampling Scheme .................................................. 91
RX9 .................................................................................... 84
RX9D ................................................................................. 84
T
T0CKI Pin ...........................................................................26
T0CKIE ...............................................................................22
T0CKIF ...............................................................................22
T0CS ............................................................................38, 67
T0IE ....................................................................................22
T0IF ....................................................................................22
T0SE .............................................................................38, 67
T0STA ..........................................................................34, 38
T16 .....................................................................................71
Table Latch .........................................................................40
Table Pointer ......................................................................40
Table Read
Example ......................................................................48
Section ........................................................................43
Table Reads Section ..................................................48
TABLRD Operation .....................................................44
Timing .........................................................................48
TLRD ..........................................................................48
TLRD Operation .........................................................44
Table Write
Code ...........................................................................46
Interaction ...................................................................45
Section ........................................................................43
TABLWT Operation ....................................................43
Terminating Long Writes ............................................45
Timing .........................................................................46
TLWT Operation .........................................................43
To External Memory ...................................................46
To Internal Memory ....................................................45
TABLRD .............................................................44, 137, 138
TABLWT .............................................................43, 138, 139
TBLATH ..............................................................................40
TBLATL ..............................................................................40
TBLPTRH .....................................................................34, 40
TBLPTRL ......................................................................34, 40
TCLK12 ..............................................................................71
TCLK3 ................................................................................71
TCON1 .........................................................................20, 35
TCON2 .........................................................................20, 35
Terminating Long Writes ....................................................45
Time-Out Sequence ...........................................................16
Timer Resources ................................................................65
Timer0 ................................................................................67
Timer1
S
Sampling ............................................................................ 91
Saving STATUS and WREG in RAM ................................. 27
SETF ................................................................................ 134
SFR .................................................................................. 108
SFR (Special Function Registers) ................................ 29, 32
SFR As Source/Destination ............................................. 108
Signed Math ......................................................................... 9
SLEEP ............................................................... 99, 105, 135
Software Simulator (MPSIM) ........................................... 145
SPBRG ...................................................... 19, 34, 92, 96, 98
Special Features of the CPU ............................................. 99
Special Function Registers ............................ 29, 32, 34, 108
SPEN ................................................................................. 84
SREN ................................................................................. 84
Stack
16-bit Mode .................................................................74
Clock Source Select ...................................................71
On bit ..........................................................................72
Section ..................................................................71, 73
Timer2
Operation ................................................................... 39
Pointer ........................................................................ 39
Stack .......................................................................... 29
STKAL ................................................................................ 39
STKAV ............................................................................... 37
SUBLW ............................................................................ 135
SUBWF ............................................................................ 136
SUBWFB .......................................................................... 136
16-bit Mode .................................................................74
Clock Source Select ...................................................71
On bit ..........................................................................72
Section ..................................................................71, 73
Timer3
Clock Source Select ...................................................71
On bit ..........................................................................72
Section ..................................................................71, 77
1996 Microchip Technology Inc.
DS30412C-page 229
PIC17C4X
Timing Diagrams
Using with PWM ........................................................ 75
TMR1CS ............................................................................ 71
TMR1IE .............................................................................. 23
TMR1IF .............................................................................. 24
TMR1ON ............................................................................ 72
TMR2 ........................................................................... 20, 35
8-bit Mode .................................................................. 73
External Clock Input .................................................. 73
In Timer Mode ........................................................... 81
Timing in External Clock Mode .................................. 80
Two 8-bit Timer/Counter Mode .................................. 73
Using with PWM ........................................................ 75
TMR2CS ............................................................................ 71
TMR2IE .............................................................................. 23
TMR2IF .............................................................................. 24
TMR2ON ............................................................................ 72
TMR3
Asynchronous Master Transmission .......................... 90
Asynchronous Reception ........................................... 92
Back to Back Asynchronous Master Transmission .... 90
Interrupt (INT, TMR0 Pins) ......................................... 26
PIC17C42 Capture ................................................... 159
PIC17C42 CLKOUT and I/O .................................... 156
PIC17C42 Memory Interface Read .......................... 162
PIC17C42 Memory Interface Write .......................... 161
PIC17C42 PWM Timing ........................................... 159
PIC17C42 RESET, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer ........................ 157
PIC17C42 Timer0 Clock .......................................... 158
PIC17C42 Timer1, Timer2 and Timer3 Clock .......... 158
PIC17C42 USART Module, Synchronous
Receive .................................................................... 160
PIC17C42 USART Module, Synchronous
Transmission ............................................................ 160
PIC17C43/44 Capture Timing .................................. 188
PIC17C43/44 CLKOUT and I/O ............................... 185
PIC17C43/44 External Clock ................................... 184
PIC17C43/44 Memory Interface Read ..................... 191
PIC17C43/44 Memory Interface Write ..................... 190
PIC17C43/44 PWM Timing ...................................... 188
PIC17C43/44 RESET, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer ........................ 186
PIC17C43/44 Timer0 Clock ..................................... 187
PIC17C43/44 Timer1, Timer2 and Timer3 Clock ..... 187
PIC17C43/44 USART Module Synchronous
Dual Capture1 Register Mode ................................... 79
Example, Reading From ............................................ 80
Example, Writing To .................................................. 80
External Clock Input .................................................. 80
In Timer Mode ........................................................... 81
One Capture and One Period Register Mode ........... 78
Overview .................................................................... 65
Reading/Writing ......................................................... 80
Timing in External Clock Mode .................................. 80
TMR3CS ...................................................................... 71, 77
TMR3H ........................................................................ 20, 35
TMR3IE .............................................................................. 23
TMR3IF ........................................................................ 24, 77
TMR3L ......................................................................... 20, 35
TMR3ON ...................................................................... 72, 77
TO ...................................................................... 37, 103, 105
Transmit Status and Control Register ................................ 83
TRMT ................................................................................. 83
TSTFSZ ........................................................................... 140
Turning on 16-bit Timer ..................................................... 74
TX9 .................................................................................... 83
TX9d .................................................................................. 83
TXEN ................................................................................. 83
TXIE ................................................................................... 23
TXIF ................................................................................... 24
TXREG ................................................ 19, 34, 89, 93, 97, 98
TXSTA ....................................................... 19, 34, 92, 96, 98
Receive .................................................................... 189
PIC17C43/44 USART Module Synchronous
Transmission ............................................................ 189
Synchronous Reception ............................................. 95
Synchronous Transmission ........................................ 94
Table Read ................................................................ 48
Table Write ................................................................. 46
TMR0 ................................................................... 68, 69
TMR0 Read/Write in Timer Mode .............................. 70
TMR1, TMR2, and TMR3 in External Clock Mode ..... 80
TMR1, TMR2, and TMR3 in Timer Mode ................... 81
Wake-Up from SLEEP ............................................. 105
Timing Diagrams and Specifications ................................ 155
Timing Parameter Symbology .......................................... 153
TLRD .......................................................................... 44, 139
TLWT ......................................................................... 43, 140
TMR0
16-bit Read ................................................................ 69
16-bit Write ................................................................. 69
Clock Timing ............................................................ 158
Module ....................................................................... 68
Operation ................................................................... 68
Overview .................................................................... 65
Prescaler Assignments .............................................. 69
Read/Write Considerations ........................................ 69
Read/Write in Timer Mode ......................................... 70
Timing .................................................................. 68, 69
TMR0 STATUS/Control Register (T0STA) ......................... 38
TMR0H ............................................................................... 34
TMR0L ............................................................................... 34
TMR1 ........................................................................... 20, 35
8-bit Mode .................................................................. 73
External Clock Input ................................................... 73
Overview .................................................................... 65
Timer Mode ................................................................ 81
Timing in External Clock Mode .................................. 80
Two 8-bit Timer/Counter Mode .................................. 73
U
Upward Compatibility ........................................................... 5
USART
Asynchronous Master Transmission ......................... 90
Asynchronous Mode .................................................. 89
Asynchronous Receive .............................................. 91
Asynchronous Transmitter ......................................... 89
Baud Rate Generator ................................................ 86
Synchronous Master Mode ........................................ 93
Synchronous Master Reception ................................ 95
Synchronous Master Transmission ........................... 93
Synchronous Slave Mode .......................................... 97
Synchronous Slave Transmit ..................................... 97
W
Wake-up from SLEEP ...................................................... 105
Wake-up from SLEEP Through Interrupt ......................... 105
Watchdog Timer ........................................................ 99, 103
DS30412C-page 230
1996 Microchip Technology Inc.
PIC17C4X
WDT ........................................................................... 99, 103
Clearing the WDT .................................................... 103
Normal Timer ........................................................... 103
Period ....................................................................... 103
Programming Considerations .................................. 103
WDTPS0 ............................................................................ 99
WDTPS1 ............................................................................ 99
WREG ................................................................................ 34
LIST OF EXAMPLES
Example 3-1: Signed Math ..................................................9
Example 3-2: Instruction Pipeline Flow .............................14
Example 5-1: Saving STATUS and WREG in RAM ..........27
Example 6-1: Indirect Addressing......................................40
Example 7-1: Table Write..................................................46
Example 7-2: Table Read..................................................48
Example 8-1: 8 x 8 Multiply Routine..................................49
Example 8-2: 8 x 8 Signed Multiply Routine......................49
Example 8-3: 16 x 16 Multiply Routine..............................50
Example 8-4: 16 x 16 Signed Multiply Routine..................51
Example 9-1: Initializing PORTB .......................................57
Example 9-2: Initializing PORTC.......................................58
Example 9-3: Initializing PORTD.......................................60
Example 9-4: Initializing PORTE .......................................62
Example 9-5: Read Modify Write Instructions on an
X
XORLW ............................................................................ 141
XORWF ............................................................................ 141
Z
I/O Port........................................................64
Z ..................................................................................... 9, 36
Zero (Z) ................................................................................ 9
Example 11-1: 16-Bit Read .................................................69
Example 11-2: 16-Bit Write..................................................69
Example 12-1: Sequence to Read Capture Registers.........78
Example 12-2: Writing to TMR3 ..........................................80
Example 12-3: Reading from TMR3....................................80
Example 13-1: Calculating Baud Rate Error........................86
Example F-1: PIC17C42 to Sleep....................................223
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
PIC17C42 Block Diagram ...........................10
PIC17CR42/42A/43/R43/44 Block
Diagram.......................................................11
Clock/Instruction Cycle................................14
Simplified Block Diagram of On-chip
Figure 3-3:
Figure 4-1:
Reset Circuit................................................15
Time-Out Sequence on Power-Up
(MCLR Tied to VDD) ....................................17
Time-Out Sequence on Power-Up
Figure 4-2:
Figure 4-3:
(MCLR NOT Tied to VDD)............................17
Slow Rise Time (MCLR Tied to VDD) ..........17
Oscillator Start-Up Time..............................18
Using On-Chip POR....................................18
Brown-out Protection Circuit 1.....................18
PIC17C42 External Power-On Reset
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Circuit (For Slow VDD Power-Up)................18
Brown-out Protection Circuit 2.....................18
Interrupt Logic .............................................21
INTSTA Register (Address: 07h,
Figure 4-9:
Figure 5-1:
Figure 5-2:
Unbanked)...................................................22
PIE Register (Address: 17h, Bank 1) ..........23
PIR Register (Address: 16h, Bank 1) ..........24
INT Pin / T0CKI Pin Interrupt Timing...........26
Program Memory Map and Stack................29
Memory Map in Different Modes .................30
External Program Memory Access
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Waveforms ..................................................31
Typical External Program Memory
Figure 6-4:
Connection Diagram....................................31
PIC17C42 Register File Map.......................33
PIC17CR42/42A/43/R43/44 Register
Figure 6-5:
Figure 6-6:
File Map.......................................................33
ALUSTA Register (Address: 04h,
Unbanked)...................................................36
CPUSTA Register (Address: 06h,
Unbanked)...................................................37
T0STA Register (Address: 05h,
Figure 6-7:
Figure 6-8:
Figure 6-9:
Unbanked)...................................................38
Figure 6-10: Indirect Addressing......................................39
Figure 6-11: Program Counter Operation........................41
1996 Microchip Technology Inc.
DS30412C-page 231
PIC17C4X
Figure 6-12: Program Counter using The CALL and
GOTO Instructions...................................... 41
Figure 14-3: Crystal Operation, Overtone Crystals
(XT OSC Configuration) ........................... 101
Figure 6-13: BSR Operation (PIC17C43/R43/44)........... 42
Figure 14-4: External Clock Input Operation
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
TLWT Instruction Operation........................ 43
TABLWT Instruction Operation................... 43
TLRD Instruction Operation........................ 44
TABLRD Instruction Operation ................... 44
TABLWT Write Timing
(EC OSC Configuration)........................... 101
Figure 14-5: External Parallel Resonant Crystal
Oscillator Circuit ....................................... 102
Figure 14-6: External Series Resonant Crystal
Oscillator Circuit ....................................... 102
(External Memory) ...................................... 46
Consecutive TABLWT Write Timing
Figure 14-7: RC Oscillator Mode .................................. 102
Figure 14-8: Watchdog Timer Block Diagram............... 104
Figure 14-9: Wake-up From Sleep Through Interrupt... 105
Figure 15-1: General Format for Instructions................ 108
Figure 15-2: Q Cycle Activity ........................................ 109
Figure 17-1: Parameter Measurement Information....... 154
Figure 17-2: External Clock Timing .............................. 155
Figure 17-3: CLKOUT and I/O Timing .......................... 156
Figure 17-4: Reset, Watchdog Timer,
Oscillator Start-Up Timer and
Power-Up Timer Timing ........................... 157
Figure 17-5: Timer0 Clock Timings............................... 158
Figure 17-6: Timer1, Timer2, And Timer3 Clock
Timings..................................................... 158
Figure 7-6:
(External Memory) ...................................... 47
TABLRD Timing.......................................... 48
TABLRD Timing (Consecutive TABLRD
Instructions) ................................................ 48
RA0 and RA1 Block Diagram ..................... 53
RA2 and RA3 Block Diagram ..................... 54
RA4 and RA5 Block Diagram ..................... 54
Block Diagram of RB<7:4> and RB<1:0>
Port Pins ..................................................... 55
Block Diagram of RB3 and RB2 Port Pins.. 56
Block Diagram of RC<7:0> Port Pins ......... 58
PORTD Block Diagram
Figure 7-7:
Figure 7-8:
Figure 9-1:
Figure 9-2:
Figure 9-3:
Figure 9-4:
Figure 9-5:
Figure 9-6:
Figure 9-7:
(in I/O Port Mode) ....................................... 60
PORTE Block Diagram
(in I/O Port Mode) ....................................... 62
Successive I/O Operation........................... 64
Figure 17-7: Capture Timings....................................... 159
Figure 17-8: PWM Timings........................................... 159
Figure 17-9: USART Module: Synchronous
Figure 9-8:
Figure 9-9:
Transmission (Master/Slave) Timing........ 160
Figure 11-1: T0STA Register (Address: 05h,
Unbanked) .................................................. 67
Figure 17-10: USART Module: Synchronous Receive
(Master/Slave) Timing .............................. 160
Figure 11-2: Timer0 Module Block Diagram ................... 68
Figure 11-3: TMR0 Timing with External Clock
Figure 17-11: Memory Interface Write Timing ................ 161
Figure 17-12: Memory Interface Read Timing................ 162
Figure 18-1: Typical RC Oscillator Frequency
vs. Temperature ....................................... 163
Figure 18-2: Typical RC Oscillator Frequency
vs. VDD ..................................................... 164
(Increment on Falling Edge) ....................... 68
Figure 11-4: TMR0 Timing: Write High or Low Byte ....... 69
Figure 11-5: TMR0 Read/Write in Timer Mode............... 70
Figure 12-1: TCON1 Register (Address: 16h, Bank 3) ... 71
Figure 12-2: TCON2 Register (Address: 17h, Bank 3) ... 72
Figure 12-3: Timer1 and Timer2 in Two 8-bit
Figure 18-3: Typical RC Oscillator Frequency
vs. VDD ..................................................... 164
Timer/Counter Mode................................... 73
Figure 12-4: TMR1 and TMR2 in 16-bit Timer/Counter
Mode........................................................... 74
Figure 12-5: Simplified PWM Block Diagram.................. 75
Figure 12-6: PWM Output ............................................... 75
Figure 12-7: Timer3 with One Capture and One
Period Register Block Diagram................... 78
Figure 12-8: Timer3 with Two Capture Registers
Block Diagram ............................................ 79
Figure 18-4: Typical RC Oscillator Frequency
vs. VDD ..................................................... 165
Figure 18-5: Transconductance (gm) of LF Oscillator
vs. VDD ..................................................... 166
Figure 18-6: Transconductance (gm) of XT Oscillator
vs. VDD ..................................................... 166
Figure 18-7: Typical IDD vs. Frequency (External
Clock 25°C) .............................................. 167
Figure 18-8: Maximum IDD vs. Frequency (External
Clock 125°C to -40°C).............................. 167
Figure 18-9: Typical IPD vs. VDD Watchdog
Figure 12-9: TMR1, TMR2, and TMR3 Operation in
External Clock Mode................................... 80
Figure 12-10: TMR1, TMR2, and TMR3 Operation in
Timer Mode................................................. 81
Disabled 25°C .......................................... 168
Figure 18-10: Maximum IPD vs. VDD Watchdog
Disabled ................................................... 168
Figure 13-1: TXSTA Register (Address: 15h, Bank 0).... 83
Figure 13-2: RCSTA Register (Address: 13h, Bank 0) ... 84
Figure 13-3: USART Transmit......................................... 85
Figure 13-4: USART Receive.......................................... 85
Figure 13-5: Asynchronous Master Transmission........... 90
Figure 13-6: Asynchronous Master Transmission
(Back to Back) ............................................ 90
Figure 13-7: RX Pin Sampling Scheme .......................... 91
Figure 13-8: Asynchronous Reception............................ 92
Figure 13-9: Synchronous Transmission ........................ 94
Figure 13-10: Synchronous Transmission
Figure 18-11: Typical IPD vs. VDD Watchdog
Enabled 25°C ........................................... 169
Figure 18-12: Maximum IPD vs. VDD Watchdog
Enabled .................................................... 169
Figure 18-13: WDT Timer Time-Out Period vs. VDD ...... 170
Figure 18-14: IOH vs. VOH, VDD = 3V.............................. 170
Figure 18-15: IOH vs. VOH, VDD = 5V.............................. 171
Figure 18-16: IOL vs. VOL, VDD = 3V............................... 171
Figure 18-17: IOL vs. VOL, VDD = 5V............................... 172
Figure 18-18: VTH (Input Threshold Voltage) of
I/O Pins (TTL) VS. VDD ............................. 172
(Through TXEN) ......................................... 94
Figure 13-11: Synchronous Reception (Master Mode,
SREN)......................................................... 95
Figure 18-19: VTH, VIL of I/O Pins (Schmitt Trigger) VS.
VDD........................................................... 173
Figure 14-1: Configuration Word..................................... 99
Figure 14-2: Crystal or Ceramic Resonator Operation
(XT or LF OSC Configuration) .................. 100
Figure 18-20: VTH (Input Threshold Voltage) of OSC1
Input (In XT and LF Modes) vs. VDD ........ 173
Figure 19-1: Parameter Measurement Information....... 183
DS30412C-page 232
1996 Microchip Technology Inc.
PIC17C4X
Figure 19-2: External Clock Timing............................... 184
Figure 19-3: CLKOUT and I/O Timing........................... 185
Figure 19-4: Reset, Watchdog Timer,
Table 6-2:
EPROM Memory Access Time
Ordering Suffix ............................................31
Special Function Registers..........................34
Interrupt - Table Write Interaction................45
Performance Comparison ...........................49
PORTA Functions .......................................54
Registers/Bits Associated with PORTA.......54
PORTB Functions .......................................57
Registers/Bits Associated with PORTB.......57
PORTC Functions .......................................59
Registers/Bits Associated with PORTC.......59
PORTD Functions .......................................61
Registers/Bits Associated with PORTD.......61
PORTE Functions .......................................63
Registers/Bits Associated with PORTE.......63
Registers/Bits Associated with Timer0........70
Turning On 16-bit Timer ..............................74
Summary of Timer1 and Timer2
Registers .....................................................74
PWM Frequency vs. Resolution at
25 MHz........................................................76
Registers/Bits Associated with PWM ..........77
Registers Associated with Capture .............79
Summary of TMR1, TMR2, and TMR3
Registers .....................................................81
Baud Rate Formula .....................................86
Registers Associated with Baud Rate
Generator ....................................................86
Baud Rates for Synchronous Mode ............87
Baud Rates for Asynchronous Mode...........88
Registers Associated with Asynchronous
Transmission...............................................90
Registers Associated with Asynchronous
Reception ....................................................92
Registers Associated with Synchronous
Master Transmission...................................94
Registers Associated with Synchronous
Master Reception ........................................96
Registers Associated with Synchronous
Table 6-3:
Table 7-1:
Table 8-1:
Table 9-1:
Table 9-2:
Table 9-3:
Table 9-4:
Table 9-5:
Table 9-6:
Table 9-7:
Table 9-8:
Table 9-9:
Table 9-10:
Table 11-1:
Table 12-1:
Table 12-2:
Oscillator Start-Up Timer, and
Power-Up Timer Timing............................ 186
Figure 19-5: Timer0 Clock Timings............................... 187
Figure 19-6: Timer1, Timer2, and Timer3 Clock
Timings ..................................................... 187
Figure 19-7: Capture Timings ....................................... 188
Figure 19-8: PWM Timings ........................................... 188
Figure 19-9: USART Module: Synchronous
Transmission (Master/Slave) Timing ........ 189
Figure 19-10: USART Module: Synchronous
Receive (Master/Slave) Timing................. 189
Figure 19-11: Memory Interface Write Timing
(Not Supported in PIC17LC4X Devices)... 190
Figure 19-12: Memory Interface Read Timing
(Not Supported in PIC17LC4X Devices)... 191
Figure 20-1: Typical RC Oscillator Frequency vs.
Temperature ............................................. 193
Figure 20-2: Typical RC Oscillator Frequency
vs. VDD...................................................... 194
Figure 20-3: Typical RC Oscillator Frequency
vs. VDD...................................................... 194
Figure 20-4: Typical RC Oscillator Frequency
vs. VDD...................................................... 195
Figure 20-5: Transconductance (gm) of LF Oscillator
vs. VDD...................................................... 196
Figure 20-6: Transconductance (gm) of XT Oscillator
vs. VDD...................................................... 196
Figure 20-7: Typical IDD vs. Frequency (External
Clock 25°C)............................................... 197
Figure 20-8: Maximum IDD vs. Frequency (External
Clock 125°C to -40°C) .............................. 197
Figure 20-9: Typical IPD vs. VDD Watchdog
Disabled 25°C........................................... 198
Figure 20-10: Maximum IPD vs. VDD Watchdog
Disabled.................................................... 198
Figure 20-11: Typical IPD vs. VDD Watchdog
Enabled 25°C............................................ 199
Figure 20-12: Maximum IPD vs. VDD Watchdog
Enabled..................................................... 199
Figure 20-13: WDT Timer Time-Out Period vs. VDD....... 200
Figure 20-14: IOH vs. VOH, VDD = 3V.............................. 200
Figure 20-15: IOH vs. VOH, VDD = 5V.............................. 201
Figure 20-16: IOL vs. VOL, VDD = 3V............................... 201
Figure 20-17: IOL vs. VOL, VDD = 5V............................... 202
Figure 20-18: VTH (Input Threshold Voltage) of
I/O Pins (TTL) VS. VDD.............................. 202
Figure 20-19: VTH, VIL of I/O Pins (Schmitt Trigger)
VS. VDD ..................................................... 203
Figure 20-20: VTH (Input Threshold Voltage) of OSC1
Input (In XT and LF Modes) vs. VDD........ 203
Table 12-3:
Table 12-4:
Table 12-5:
Table 12-6:
Table 13-1:
Table 13-2:
Table 13-3:
Table 13-4:
Table 13-5:
Table 13-6:
Table 13-7:
Table 13-8:
Table 13-9:
Slave Transmission.....................................98
Table 13-10: Registers Associated with Synchronous
Slave Reception ..........................................98
Table 14-1:
Table 14-2:
Configuration Locations.............................100
Capacitor Selection for Ceramic
Resonators................................................101
Capacitor Selection for Crystal
OscillatoR..................................................101
Registers/Bits Associated with the
Watchdog Timer........................................104
Opcode Field Descriptions ........................107
PIC17CXX Instruction Set.........................110
development tools from microchip.............146
Cross Reference of Device Specs for
Table 14-3:
Table 14-4:
Table 15-1:
Table 15-2:
Table 16-1:
Table 17-1:
Oscillator Configurations and Frequencies
of Operation (Commercial Devices) ..........148
External Clock Timing Requirements........155
CLKOUT and I/O Timing Requirements....156
Reset, Watchdog Timer,
LIST OF TABLES
Table 1-1:
Table 3-1:
Table 4-1:
Table 4-2:
Table 4-3:
PIC17CXX Family of Devices....................... 6
Pinout Descriptions..................................... 12
Time-Out in Various Situations................... 16
STATUS Bits and Their Significance.......... 16
Reset Condition for the Program Counter
and the CPUSTA Register.......................... 16
Initialization Conditions For Special
Table 17-2:
Table 17-3:
Table 17-4:
Oscillator Start-Up Timer and
Power-Up Timer Requirements.................157
Timer0 Clock Requirements......................158
Timer1, Timer2, and Timer3 Clock
Table 17-5:
Table 17-6:
Table 4-4:
Function Registers...................................... 19
Interrupt Vectors/Priorities .......................... 25
Mode Memory Access ................................ 30
Requirements............................................158
Capture Requirements ..............................159
PWM Requirements ..................................159
Table 5-1:
Table 6-1:
Table 17-7:
Table 17-8:
1996 Microchip Technology Inc.
DS30412C-page 233
PIC17C4X
Table 17-9:
Serial Port Synchronous Transmission
Requirements ........................................... 160
Table 17-10: Serial Port Synchronous Receive
Requirements ........................................... 160
Table 17-11: Memory Interface Write Requirements..... 161
Table 17-12: Memory Interface Read Requirements..... 162
Table 18-1:
Table 18-2:
Table 19-1:
Pin Capacitance per Package Type ......... 163
RC Oscillator Frequencies........................ 165
Cross Reference of Device Specs for
Oscillator Configurations and Frequencies
of Operation (Commercial Devices).......... 176
External Clock Timing Requirements ....... 184
CLKOUT and I/O Timing Requirements ... 185
Reset, Watchdog Timer,
Table 19-2:
Table 19-3:
Table 19-4:
Oscillator Start-Up Timer and
Power-Up Timer Requirements ................ 186
Timer0 Clock Requirements ..................... 187
Timer1, Timer2, and Timer3 Clock
Table 19-5:
Table 19-6:
Requirements ........................................... 187
Capture Requirements.............................. 188
PWM Requirements.................................. 188
Synchronous Transmission
Table 19-7:
Table 19-8:
Table 19-9:
Requirements ........................................... 189
Table 19-10: Synchronous Receive Requirements ....... 189
Table 19-11: Memory Interface Write Requirements
(Not Supported in PIC17LC4X Devices)... 190
Table 19-12: Memory Interface read Requirements
(Not Supported in PIC17LC4X Devices)... 191
Table 20-1:
Table 20-2:
Table E-1:
Pin Capacitance per Package Type ......... 193
RC Oscillator Frequencies........................ 195
Pin Compatible Devices............................ 221
LIST OF EQUATIONS
Equation 8-1: 16 x 16 Unsigned Multiplication
Algorithm..................................................... 50
Equation 8-2: 16 x 16 Signed Multiplication
Algorithm..................................................... 51
DS30412C-page 234
1996 Microchip Technology Inc.
PIC17C4X
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DS30412C-page 235
PIC17C4X
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DS30412C-page 236
1996 Microchip Technology Inc.
PIC17C4X
PIC17C4X Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Examples
PART NO. – XX X /XX XXX
Pattern:
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices
a)
b)
c)
PIC17C42 – 16/P
Commercial Temp.,
PDIP
package,
16 MHZ,
normal VDD limits
Package:
P
= PDIP
JW
P
= Windowed CERDIP
= PDIP (600 mil)
= MQFP
PIC17LC44 – 08/PT
Commercial Temp.,
PQ
PT
L
= TQFP
= PLCC
TQFP
8MHz,
package,
Temperature
Range:
Frequency
Range:
–
I
= 0˚C to +70˚C
= –40˚C to +85˚C
extended VDD limits
08
16
25
33
= 8 MHz
= 16 MHz
= 25 Mhz
= 33 Mhz
PIC17C43
Industrial
PDIP
–
25I/P
Temp.,
package,
25 MHz,
normal VDD limits
Device:
PIC17C44
: Standard Vdd range
PIC17C44T : (Tape and Reel)
PIC17LC44 : Extended Vdd range
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1996 Microchip Technology Inc.
DS30412C-page 237
PIC17C4X
NOTES:
DS30412C-page 238
1996 Microchip Technology Inc.
PIC17C4X
NOTES:
DS30412C-page 239
1996 Microchip Technology Inc.
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Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
相关型号：
PIC17C43-16JW
8-BIT, UVPROM, 16 MHz, RISC MICROCONTROLLER, CDIP40, 0.600 INCH, WINDOWED, CERDIP-40
MICROCHIP
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