PIC17C752T-16/L [MICROCHIP]
High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D; 高性能8位CMOS微控制器的EPROM与10位A / D
| 型号： | PIC17C752T-16/L |
| 厂家： | 
MICROCHIP |
| 描述： | High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D |
| 文件： | 总328页 (文件大小：1886K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC17C7XX
High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
Microcontroller Core Features:
Pin Diagrams
84 LCC
• Only 58 single word instructions to learn
• All single cycle instructions (121 ns) except for
program branches and table reads/writes which
are two-cycle
11 10
9
8
7
6
5
4
3
2
1
84 83 82 81 75
80 797877 76
RH2
RH3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RJ5
74
73
72
71
70
69
68
67
66
• Operating speed:
RJ4
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
- DC - 33 MHz clock input
- DC - 121 ns instruction cycle
• 8 x 8 Single-Cycle Hardware Multiplier
• Interrupt capability
65
64
63
NC
VSS
VDD
NC
PIC17C76X
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RJ3
RJ2
62
61
60
59
• 16 level deep hardware stack
• Direct, indirect, and relative addressing modes
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
58
57
56
• Internal/external program memory execution,
Capable of addressing 64K x 16 program memory
space
55
54
33 3435 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Memory
Device
Program (x16)
Data (x8)
PIC17C752
PIC17C756A
PIC17C762
PIC17C766
8K
16K
8K
678
902
678
902
Special Microcontroller Features:
16K
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Peripheral Features:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Up to 66 I/O pins with individual direction control
• 10-bit, multi-channel analog-to-digital converter
• High current sink/source for direct LED drive
• Four capture input pins
• Brown-out Reset
• Code-protection
• Power saving SLEEP mode
• Selectable oscillator options
- Captures are 16-bit, max resolution 121 ns
• Three PWM outputs (resolution is 1- to 10-bits)
CMOS Technology:
• TMR0: 16-bit timer/counter with
8-bit programmable prescaler
• Low-power, high-speed CMOS EPROM
technology
• TMR1: 8-bit timer/counter
• TMR2: 8-bit timer/counter
• TMR3: 16-bit timer/counter
• Fully static design
• Wide operating voltage range (3.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption
• Two Universal Synchronous Asynchronous
Receiver Transmitters (USART/SCI) with Indepen-
dent baud rate generators
- < 5 mA @ 5V, 4 MHz
• Synchronous Serial Port (SSP) with SPI™ and
I C™ modes (including I C master mode)
- 100 µA typical @ 4.5V, 32 kHz
- < 1 µA typical standby current @ 5V
2
2
1998 Microchip Technology Inc.
DS30289A-page 1
PIC17C7XX
Pin Diagrams cont.’d
68-Pin LCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RA0/INT
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
MCLR
/VPP
TEST
NC
VSS
PIC17C75X
NC
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
64-Pin TQFP
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RA0/INT
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
2
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
3
4
5
6
7
PIC17C75X
8
9
VSS
OSC2/CLKOUT
OSC1/CLKIN
VDD
10
11
12
13
14
15
16
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
DS30289A-page 2
1998 Microchip Technology Inc.
PIC17C7XX
PIN DIAGRAMS cont.’d
84-pin LCC
83828180
1110 9
8
7
6
5
4
3
2
1 84
7978777675
RH2
RH3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RJ5
RJ4
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
RA0/INT
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
PIC17C76X
NC
VSS
VDD
NC
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
55
54
RJ3
RJ2
333435363738394041424344
454647484950515253
80-Pin QFP
807978777675 747372717069 68676665 64636261
1
2
60
RH2
RH3
RJ5
RJ4
RA0/INT
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RJ3
PIC17C76X
VSS
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
RJ2
212223242526272829303132 3334353637383940
1998 Microchip Technology Inc.
DS30289A-page 3
PIC17C7XX
Table of Contents
1.0
Overview...........................................................................................................................................................5
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
Device Varieties................................................................................................................................................7
Architectural Overview......................................................................................................................................9
On-chip Oscillator Circuit ................................................................................................................................15
Reset...............................................................................................................................................................21
Interrupts.........................................................................................................................................................31
Memory Organization......................................................................................................................................41
Table Reads and Table Writes .......................................................................................................................57
Hardware Multiplier.........................................................................................................................................65
I/O Ports..........................................................................................................................................................69
Overview of Timer Resources.........................................................................................................................93
Timer0.............................................................................................................................................................95
Timer1, Timer2, Timer3, PWMs and Captures ...............................................................................................99
Universal Synchronous Asynchronous Receiver Transmitter (USART) Modules.........................................115
Master Synchronous Serial Port (MSSP) Module.........................................................................................131
Analog-to-Digital Converter (A/D) Module ....................................................................................................177
Special Features of the CPU ........................................................................................................................189
Instruction Set Summary...............................................................................................................................195
Development Support ...................................................................................................................................231
PIC17C7XX Electrical Characteristics ..........................................................................................................235
PIC17C7XX DC and AC Characteristics.......................................................................................................265
Packaging Information ..................................................................................................................................277
Appendix A: Modifications..........................................................................................................................................283
Appendix B: Compatibility ..........................................................................................................................................283
Appendix C: What’s New............................................................................................................................................284
Appendix D: What’s Changed ....................................................................................................................................284
2
Appendix E: I C Overview.......................................................................................................................................285
Appendix F: Status and Control Registers.................................................................................................................291
On-Line Support..........................................................................................................................................................321
Reader Response .......................................................................................................................................................322
PIC17C7XX Product Identification System .................................................................................................................323
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet.The errata will specify the revi-
sion of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
•
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The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-
erature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
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We appreciate your assistance in making this a better document.
DS30289A-page 4
1998 Microchip Technology Inc.
PIC17C7XX
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software mal-
function.
1.0
OVERVIEW
This data sheet covers the PIC17C7XX group of the
PIC17CXXX family of microcontrollers. The following
devices are discussed in this data sheet:
There are four configuration options for the device
operational mode:
• PIC17C752
• PIC17C756A
• PIC17C762
• PIC17C766
• Microprocessor
• Microcontroller
• Extended microcontroller
• Protected microcontroller
The
PIC17C7XX
devices
are
68/84-pin,
The microprocessor and extended microcontroller
modes allow up to 64K-words of external program
memory.
EPROM-based members of the versatile PIC17CXXX
family of low-cost, high-performance, CMOS,
fully-static, 8-bit microcontrollers.
The device also has Brown-out Reset circuitry. This
allows a device reset to occur if the device VDD falls
below the Brown-out voltage trip point (BVDD). The
chip will remain in Brown-out Reset until VDD rises
above BVDD.
All PICmicro™ microcontrollers employ an advanced
RISC architecture. The PIC17CXXX has enhanced
core features, 16-level deep stack, and multiple internal
and external interrupt sources. The separate instruc-
tion and data buses of the Harvard architecture allow a
16-bit wide instruction word with a separate 8-bit wide
data path. The two stage instruction pipeline allows all
instructions to execute in a single cycle, except for pro-
gram branches (which require two cycles). A total of 58
instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance. For mathematical intensive applications
all devices have a single cycle 8 x 8 Hardware Multi-
plier.
A UV-erasable CERQUAD-packaged version (compat-
ible with PLCC) is ideal for code development while the
cost-effective One-Time Programmable (OTP) version
is suitable for production in any volume.
The PIC17C7XX fits perfectly in applications that
require extremely fast execution of complex software
programs. These include applications ranging from
precise motor control and industrial process control to
automotive, instrumentation, and telecom applications.
The EPROM technology makes customization of appli-
cation programs (with unique security codes, combina-
tions, model numbers, parameter storage, etc.) fast and
convenient. Small footprint package options (including
die sales) make the PIC17C7XX ideal for applications
with space limitations that require high performance.
PIC17CXXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
PIC17C7XX devices have up to 902 bytes of RAM and
66 I/O pins. In addition, the PIC17C7XX adds several
peripheral features useful in many high performance
applications including:
High speed execution, powerful peripheral features,
flexible I/O, and low power consumption all at low cost
make the PIC17C7XX ideal for a wide range of embed-
ded control applications.
• Four timer/counters
• Four capture inputs
• Three PWM outputs
1.1
Family and Upward Compatibility
• Two independent Universal Synchronous Asyn-
chronous Receiver Transmitters (USARTs)
The PIC17CXXX family of microcontrollers have archi-
tectural enhancements over the PIC16C5X and
PIC16CXX families. These enhancements allow the
device to be more efficient in software and hardware
requirements. Refer to Appendix A for a detailed list of
enhancements and modifications. Code written for
PIC16C5X or PIC16CXX can be easily ported to
PIC17CXXX devices (Appendix B).
• An A/D converter (multi-channel, 10-bit resolu-
tion)
• A Synchronous Serial Port
2
(SPI and I C w/ Master mode)
These special features reduce external components,
thus reducing cost, enhancing system reliability and
reducing power consumption.
1.2
Development Support
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LF oscil-
lator is for low frequency crystals and minimizes power
consumption, XT is a standard crystal, and the EC is for
external clock input.
The PIC17CXXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a universal programmer, a “C” compiler, and
fuzzy logic support tools. For additional information
see Section 19.0.
The SLEEP (power-down) mode offers additional
power saving. Wake-up from SLEEP can occur
through several external and internal interrupts and
device resets.
1998 Microchip Technology Inc.
DS30289A-page 5
PIC17C7XX
TABLE 1-1:
PIC17CXXX FAMILY OF DEVICES
Features
PIC17C42A
PIC17C43
PIC17C44
PIC17C752 PIC17C756A PIC17C762 PIC17C766
Maximum Frequency
of Operation
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
Operating Voltage Range
2.5 - 6.0V
2K
2.5 - 6.0V
4K
2.5 - 6.0V
8K
3.0 - 5.5V
8K
3.0 - 5.5V
16K
3.0 - 5.5V
8K
3.0 - 5.5V
16K
Program
(EPROM)
(ROM)
Memory ( x16)
—
—
—
—
—
—
—
Data Memory (bytes)
232
454
454
678
902
678
902
Hardware Multiplier (8 x 8)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Timer0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(16-bit + 8-bit postscaler)
Timer1 (8-bit)
Yes
Yes
Yes
2
Yes
Yes
Yes
2
Yes
Yes
Yes
2
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Timer2 (8-bit)
Timer3 (16-bit)
Capture inputs (16-bit)
PWM outputs (up to 10-bit)
USART/SCI
2
2
2
3
3
3
3
1
1
1
2
2
2
2
A/D channels (10-bit)
—
—
—
—
—
—
12
Yes
12
Yes
16
Yes
16
Yes
2
SSP (SPI/I C w/Master
mode)
Power-on Reset
Watchdog Timer
External Interrupts
Interrupt Sources
Code Protect
Yes
Yes
Yes
11
Yes
Yes
Yes
11
Yes
Yes
Yes
11
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
—
Yes
—
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
In-circuit Serial Program-
ming
—
—
—
I/O Pins
33
33
33
50
50
66
66
I/O High Cur-
rent Capability
Source
Sink
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
(1)
(1)
(1)
(1)
(1)
(1)
(1)
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
Package Types
40-pin DIP
40-pin DIP
40-pin DIP
64-pin DIP
64-pin DIP 80-pin QFP 80-pin QFP
44-pin PLCC 44-pin PLCC 44-pin PLCC 68-pin LCC
68-pin LCC
84-pin
PLCC
84-pin
PLCC
44-pin
MQFP
44-pin
MQFP
44-pin
MQFP
68-pin TQFP 68-pin TQFP
44-pin TQFP 44-pin TQFP 44-pin TQFP
Note 1: Pins RA2 and RA3 can sink up to 60 mA.
DS30289A-page 6
1998 Microchip Technology Inc.
PIC17C7XX
2.1
UV Erasable Devices
2.0
DEVICE VARIETIES
Each device has a variety of frequency ranges and
packaging options. Depending on application and pro-
duction requirements, the proper device option can be
selected using the information in the PIC17C7XX Prod-
uct Selection System section at the end of this data
sheet. When placing orders, please use the
“PIC17C7XX Product Identification System” at the back
of this data sheet to specify the correct part number.
When discussing the functionality of the device, mem-
ory technology and voltage range does not matter.
The UV erasable version, offered in CERQUAD pack-
age, is optimal for prototype development and pilot pro-
grams.
The UV erasable version can be erased and repro-
grammed to any of the configuration modes. Third
party programmers also are available; refer to the Third
Party Guide for a list of sources.
2.2
One-Time-Programmable (OTP)
Devices
There are three memory type options. These are spec-
ified in the middle characters of the part number.
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
1. C, as in PIC17C756A. These devices have
EPROM type memory.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must be pro-
grammed.
2. CR, as in PIC17CR756A. These devices have
ROM type memory.
3. F, as in PIC17F756A.These devices have Flash
type memory.
2.3
Quick-Turnaround-Production (QTP)
Devices
All these devices operate over the standard voltage
range. Devices are also offered which operate over an
extended voltage range (and reduced frequency
range). Table 2-1 shows all possible memory types
and voltage range designators for a particular device.
These designators are in bold typeface.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
TABLE 2-1:
DEVICE MEMORY
VARIETIES
Voltage Range
Memory Type
Standard
Extended
EPROM
ROM
PIC17CXXX
PIC17CRXXX
PIC17FXXX
PIC17LCXXX
PIC17LCRXXX
PIC17LFXXX
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Flash
Note: Not all memory technologies are available
for a particular device.
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with different serial numbers. The serial
numbers may be random, pseudo-random or sequen-
tial.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
1998 Microchip Technology Inc.
DS30289A-page 7
PIC17C7XX
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, thus giving customers a low
cost option for high volume, mature products.
ROM devices do not allow serialization information in
the program memory space.
For information on submitting ROM code, please con-
tact your regional sales office.
Note: Presently, NO ROM versions of the
PIC17C7XX devices are available.
2.6
Flash Memory Devices
These devices are electrically erasable and, therefore,
can be offered in the low cost plastic package. Being
electrically erasable, these devices can be erased and
reprogrammed in-circuit. These devices are the same
for prototype development, pilot programs, as well as
production.
Note: Presently, NO Flash versions of the
PIC17C7XX devices are available.
DS30289A-page 8
1998 Microchip Technology Inc.
PIC17C7XX
The WREG register is an 8-bit working register used for
ALU operations.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC17CXXX can be attrib-
uted to a number of architectural features commonly
found in RISC microprocessors. To begin with, the
PIC17CXXX uses a modified Harvard architecture.
This architecture has the program and data accessed
from separate memories. So, the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions
to be sized differently than the 8-bit wide data word.
PIC17CXXX opcodes are 16-bits wide, enabling single
word instructions. The full 16-bit wide program mem-
ory bus fetches a 16-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of
instructions. Consequently, all instructions execute in a
single cycle (121 ns @ 33 MHz), except for program
branches and two special instructions that transfer data
between program and data memory.
All PIC17CXXX devices have an 8 x 8 hardware multi-
plier.This multiplier generates a 16-bit result in a single
cycle.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift, and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
Zero (Z) and overflow (OV) bits in the ALUSTA register.
The C and DC bits operate as a borrow and digit borrow
out bit, respectively, in subtraction. See the SUBLWand
SUBWFinstructions for examples.
Signed arithmetic is comprised of a magnitude and a
sign bit. The overflow bit indicates if the magnitude
overflows and causes the sign bit to change state. That
is if the result of 8-bit signed operations is greater than
127 (7Fh) or less than -128 (80h).
Signed math can have greater than 7-bit values (mag-
nitude), if more than one byte is used. The overflow bit
only operates on bit6 (MSb of magnitude) and bit7 (sign
bit) of each byte value in the ALU. That is, the overflow
bit is not useful if trying to implement signed math
where the magnitude, for example, is 11-bits.
The PIC17CXXX can address up to 64K x 16 of pro-
gram memory space.
The PIC17C752 and PIC17C762 integrate 8K x 16 of
EPROM program memory on-chip.
The PIC17C756A and PIC17C766 integrate 16K x 16
EPROM program memory on-chip.
If the signed math values are greater than 7-bits (such
as 15-, 24- or 31-bit), the algorithm must ensure that
the low order bytes of the signed value ignore the over-
flow status bit.
A simplified block diagram is shown in Figure 3-1. The
descriptions of the device pins are listed in Table 3-1.
Program execution can be internal only (microcontrol-
ler or protected microcontroller mode), external only
(microprocessor mode) or both (extended microcon-
troller mode). Extended microcontroller mode does not
allow code protection.
Example 3-1 shows an two cases of doing signed arith-
metic. The Carry (C) bit and the Overflow (OV) bit are
the most important status bits for signed math opera-
tions.
The PIC17CXXX can directly or indirectly address its
register files or data memory. All special function reg-
isters, including the Program Counter (PC) and Work-
ing Register (WREG), are mapped in data memory.
The PIC17CXXX has an orthogonal (symmetrical)
instruction set that makes it possible to carry out any
operation on any register using any addressing mode.
This symmetrical nature and lack of ‘special optimal sit-
uations’ make programming with the PIC17CXXX sim-
ple yet efficient. In addition, the learning curve is
reduced significantly.
EXAMPLE 3-1: 8-BIT MATH ADDITION
Hex Value
Signed Values
Unsigned Values
FFh
-1
255
+
=
01h
00h
+
=
1
+
1
0 (FEh)
= 256 → 00h
C bit = 1
C bit = 1
C bit = 1
OV bit = 0
OV bit = 0
OV bit = 0
DC bit = 1
Z bit = 1
DC bit = 1
Z bit = 1
DC bit = 1
Z bit = 1
One of the PIC17CXXX family architectural enhance-
ments from the PIC16CXX family allows two file regis-
ters to be used in some two operand instructions. This
allows data to be moved directly between two registers
without going through the WREG register. Thus
increasing performance and decreasing program
memory usage.
Hex Value
Signed Values
Unsigned Values
7Fh
127
127
+
=
01h
80h
+
=
1
+
1
128 → 00h
= 128
C bit = 0
C bit = 0
C bit = 0
The PIC17CXXX devices contain an 8-bit ALU and
working register. The ALU is a general purpose arith-
metic unit. It performs arithmetic and Boolean func-
tions between data in the working register and any
register file.
OV bit = 1
OV bit = 1
OV bit = 1
DC bit = 1
Z bit = 0
DC bit = 1
Z bit = 0
DC bit = 1
Z bit = 0
1998 Microchip Technology Inc.
DS30289A-page 9
PIC17C7XX
FIGURE 3-1: PIC17C752/756A BLOCK DIAGRAM
PORTA
Clock
Generator
OSC1,
OSC2
Q1, Q2,
Q3, Q4
RA0/INT
RA1/T0CKI
IR<16>
Power-on
Reset
BITOP
WREG<8>
RA2/SS/SCL
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
Brown-out
Reset
VDD, VSS
Chip_reset
& Other
Control
Watchdog
Timer
MCLR, VPP
Test
PORTB
PORTC
PORTD
8 x 8 mult
ALU
Signals
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
Test Mode
Select
PRODH PRODL
Shifter
IR Latch <16>
8
8
RB7/SDO
8
BSR <7:4>
IR <7:0>
16
F1
F9
Decode
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
12
Read/write
Decode
for
Instruction
Decode
RAM
Address
Buffer
Data RAM
17C756A
902 x 8
Registers
ROM Latch <16>
Mapped
in Data
Space
8
Control Outputs
17C752
678 x 8
RD0/AD8
RD1/AD9
AD<15:0>
PORTC,
PORTD
Data Latch
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
Literal
BSR
Table
Latch <16>
Data Latch
Program
Memory
(EPROM)
17C756A
16K x 16
PORTE
17C752
8K x 16
RE0/ALE
RE1/OE
RE2/WR
ALE,
WR,
OE,
Address
Latch
Table Pointer<16>
Stack
PCLATH<8>
RE3/CAP4
PORTE
16
16
PORTF
PCH
PCL
16
16 x 16
16
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
Data Bus<8>
10-bit
A/D
Timer0
Timer2
Timer3
PWM1
PWM2
PWM3
Capture2
SSP
USART1
USART2
PORTG
RG0/AN3
RG1/AN2
RG2/AN1/VREF-
RG3/AN0/VREF+
RG4/CAP3
Interrupt
Module
Timer1
Capture1 Capture3 Capture4
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
DS30289A-page 10
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 3-2: PIC17C762/766 BLOCK DIAGRAM
PORTA
Clock
Generator
RA0/INT
RA1/T0CKI
RA2/SS/SCL
Q1, Q2,
Q3, Q4
OSC1,
OSC2
Power-on
Reset
IR<16>
BITOP
WREG<8>
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
VDD, VSS
Watchdog
Timer
Chip_reset
& Other
Control
Test Mode
Select
PORTB
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
MCLR, VPP
Signals
Brown-out
Reset
8 x 8 mult
ALU
Test
AVDD, AVSS
PRODH PRODL
Shifter
IR Latch <16>
RB7/SDO
PORTC
8
8
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
BSR <7:4>
IR <7:0>
8
16
FSR0
FSR1
Decode
12
Read/write
Decode
for
Instruction
Decode
RAM
Address
Buffer
Registers
ROM Latch <16>
PORTD
Mapped
in Data
Space
8
RD0/AD8
RD1/AD9
Data RAM
Control Outputs
17C766
902 x 8
and
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
17C762
678 x 8
Data Latch
AD<15:0>
PORTC,
PORTD
PORTE
PORTF
Literal
BSR
Table
Data Latch
RE0/ALE
RE1/OE
RE2/WR
Latch <16>
Program
Memory
(EPROM)
17C766
16K x 16,
and
17C762
8K x 16
RE3/CAP4
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
ALE,
WR,
OE,
Address
Latch
Table Pointer<16>
Stack
PCLATH<8>
PORTE
16
PORTG
RG0/AN3
RG1/AN2
RG2/AN1/VREF-
RG3/AN0/VREF+
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
16
PCH
PCL
16
16 x 16
16
Data Bus<8>
PORTJ
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
PORTH
Timer0
Timer2
Timer3
PWM1
PWM2
PWM3
USART1
USART2
RH0
RH1
RH2
RH3
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
Timer1
Capture1
10-bit
A/D
Interrupt
Module
SSP
Capture2 Capture3
Capture4
1998 Microchip Technology Inc.
DS30289A-page 11
PIC17C7XX
TABLE 3-1:
PINOUT DESCRIPTIONS
PIC17C75X
PIC17C76X
Name
DIP
No.
PLCC TQFP PLCC QFP I/O/P Buffer
Description
No.
No.
No.
No.
Type Type
OSC1/CLKIN
47
50
39
62
49
I
ST
Oscillator input in crystal/resonator or RC oscillator
mode. External clock input in external clock mode.
OSC2/CLKOUT
48
51
40
63
50
O
—
Oscillator output. Connects to crystal or resonator in
crystal oscillator mode. In RC oscillator or external
clock modes OSC2 pin outputs CLKOUT which has
one fourth the frequency (FOSC/4) of OSC1 and
denotes the instruction cycle rate.
MCLR/VPP
15
16
7
20
9
I/P
ST
Master clear (reset) input or Programming Voltage
(VPP) input. This is the active low reset input to the
device.
PORTA pins have individual differentiations that are
listed in the following descriptions:
RA0/INT
56
41
60
44
48
33
72
56
58
43
I
I
ST
ST
RA0 can also be selected as an external inter-
rupt input. Interrupt can be configured to be on
positive or negative edge. Input only pin.
RA1/T0CKI
RA1 can also be selected as an external inter-
rupt input, and the interrupt can be configured
to be on positive or negative edge. RA1 can
also be selected to be the clock input to the
Timer0 timer/counter. Input only pin.
(2)
RA2/SS/SCL
RA3/SDI/SDA
RA4/RX1/DT1
42
43
40
45
46
43
34
35
32
57
58
51
44
45
38
ST
ST
ST
RA2 can also be used as the slave select input
for the SPI or the clock input for the I C bus.
High voltage, high current, open drain port pin.
I/O
I/O
I/O
2
(2)
(1)
RA3 can also be used as the data input for the
2
SPI or the data for the I C bus.
High voltage, high current, open drain port pin.
RA4 can also be selected as the USART1 (SCI)
Asynchronous Receive or USART1 (SCI)
Synchronous Data.
Output available from USART only.
(1)
RA5/TX1/CK1
39
42
31
50
37
ST
RA5 can also be selected as the USART1 (SCI)
Asynchronous Transmit or USART1 (SCI)
Synchronous Clock.
I/O
Output available from USART only.
PORTB is a bi-directional I/O Port with software
configurable weak pull-ups.
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
55
54
50
53
52
59
58
54
57
56
47
46
42
45
44
71
70
66
69
68
57
56
52
55
54
I/O
ST
ST
ST
ST
ST
RB0 can also be the Capture1 input pin.
RB1 can also be the Capture2 input pin.
RB2 can also be the PWM1 output pin.
RB3 can also be the PWM2 output pin.
I/O
I/O
I/O
I/O
RB4 can also be the external clock input to
Timer1 and Timer2.
RB5/TCLK3
RB6/SCK
RB7/SDO
51
44
45
55
47
48
43
36
37
67
59
60
53
46
47
I/O
I/O
I/O
ST
ST
ST
RB5 can also be the external clock input to
Timer3.
RB6 can also be used as the master/slave clock
for the SPI.
RB7 can also be used as the data output for the
SPI.
Legend: I = Input only;
P = Power;
O = Output only;
— = Not Used;
I/O = Input/Output;
TTL = TTL input;
ST = Schmitt Trigger input.
Note 1: The output is only available by the peripheral operation.
2: Open Drain input/output pin. Pin forced to input upon any device reset.
DS30289A-page 12
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 3-1:
PINOUT DESCRIPTIONS
PIC17C75X
PIC17C76X
Name
DIP
No.
PLCC TQFP PLCC QFP I/O/P Buffer
Description
No.
No.
No.
No.
Type Type
PORTC is a bi-directional I/O Port.
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
2
3
58
55
54
53
52
51
50
49
3
72
69
68
67
66
65
64
63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
This is also the least significant byte (LSB) of
the 16-bit wide system bus in microprocessor
mode or extended microcontroller mode. In
multiplexed system bus configuration, these
pins are address output as well as data input or
output.
63
62
61
60
58
58
57
67
66
65
64
63
62
61
83
82
81
80
79
78
77
PORTD is a bi-directional I/O Port.
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
10
9
11
10
9
2
15
14
9
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
This is also the most significant byte (MSB) of
the 16-bit system bus in microprocessor mode
or extended microcontroller mode. In multi-
plexed system bus configuration these pins are
address output as well as data input or output.
1
3
8
64
63
62
61
60
59
78
77
76
75
74
73
7
8
8
6
7
7
5
6
6
4
5
5
3
4
4
PORTE is a bi-directional I/O Port.
RE0/ALE
11
12
3
16
5
I/O
TTL
In microprocessor mode or extended microcon-
troller mode, RE0 is the Address Latch Enable
(ALE) output. Address should be latched on the
falling edge of ALE output.
RE1/OE
12
13
14
13
14
15
4
5
6
17
18
19
6
7
8
I/O
I/O
I/O
TTL
TTL
ST
In microprocessor or extended microcontroller
mode, RE1 is the Output Enable (OE) control
output (active low).
RE2/WR
RE3/CAP4
In microprocessor or extended microcontroller
mode, RE2 is the Write Enable (WR) control
output (active low).
RE3 can also be the Capture4 input pin.
PORTF is a bi-directional I/O Port.
RF0 can also be analog input 4.
RF1 can also be analog input 5.
RF2 can also be analog input 6.
RF3 can also be analog input 7.
RF4 can also be analog input 8.
RF5 can also be analog input 9.
RF6 can also be analog input 10.
RF7 can also be analog input 11.
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
26
25
24
23
22
21
20
19
28
27
26
25
24
23
22
21
18
17
16
15
14
13
12
11
36
35
30
29
28
27
26
25
24
23
18
17
16
15
14
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Legend: I = Input only;
P = Power;
O = Output only;
— = Not Used;
I/O = Input/Output;
TTL = TTL input;
ST = Schmitt Trigger input.
Note 1: The output is only available by the peripheral operation.
2: Open Drain input/output pin. Pin forced to input upon any device reset.
1998 Microchip Technology Inc.
DS30289A-page 13
PIC17C7XX
TABLE 3-1:
PINOUT DESCRIPTIONS
PIC17C75X
PIC17C76X
Name
DIP
No.
PLCC TQFP PLCC QFP I/O/P Buffer
Description
No.
No.
No.
No.
Type Type
PORTG is a bi-directional I/O Port.
RG0 can also be analog input 3.
RG1 can also be analog input 2.
RG0/AN3
32
31
30
34
33
32
24
23
22
42
41
40
30
29
28
I/O
I/O
I/O
ST
ST
ST
RG1/AN2
RG2/AN1/VREF-
RG2 can also be analog input 1, or
the ground reference voltage
RG3/AN0/VREF+
29
31
21
39
27
I/O
ST
RG3 can also be analog input 0, or
the positive reference voltage
RG4/CAP3
35
36
38
38
39
41
27
28
30
46
47
49
33
34
36
I/O
I/O
I/O
ST
ST
ST
RG4 can also be the Capture3 input pin.
RG5 can also be the PWM3 output pin.
RG5/PWM3
RG6/RX2/DT2
RG6 can also be selected as the USART2 (SCI)
Asynchronous Receive or USART2 (SCI)
Synchronous Data.
RG7/TX2/CK2
37
40
29
48
35
I/O
ST
RG7 can also be selected as the USART2 (SCI)
Asynchronous Transmit or USART2 (SCI)
Synchronous Clock.
PORTH is a bi-directional I/O Port. PORTH is only
available on the PIC17C76X devices
RH0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
11
12
13
31
32
33
34
79
80
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
RH1
RH2
RH3
2
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
19
20
21
22
RH4 can also be analog input 12.
RH5 can also be analog input 13.
RH6 can also be analog input 14.
RH7 can also be analog input 15.
PORTJ is a bi-directional I/O Port. PORTJ is only
available on the PIC17C76X devices.
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
TEST
—
—
—
—
—
—
—
—
16
—
—
—
—
—
—
—
—
17
—
—
—
—
—
—
—
—
8
52
53
54
55
73
74
75
76
21
39
40
41
42
59
60
61
62
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Test mode selection control input. Always tie to VSS
for normal operation.
VSS
17, 33, 19, 36, 9, 25, 23, 44, 11, 31,
49, 64 53, 68 41, 56 65, 84 51, 70
P
P
P
P
Ground reference for logic and I/O pins.
VDD
AVSS
AVDD
NC
1, 18, 2, 20, 10, 26, 24, 45, 12, 32,
34, 46 37, 49, 38, 57 61, 2 48, 71
Positive supply for logic and I/O pins.
28
27
—
30
20
19
—
38
26
25
—
Ground reference for A/D converter.
This pin MUST be at the same potential as VSS.
29
37
Positive supply for A/D converter.
This pin MUST be at the same potential as VDD.
1, 18,
1, 22,
No Connect. Leave these pins unconnected.
35, 52
43, 64
Legend: I = Input only;
P = Power;
O = Output only;
— = Not Used;
I/O = Input/Output;
TTL = TTL input;
ST = Schmitt Trigger input.
Note 1: The output is only available by the peripheral operation.
2: Open Drain input/output pin. Pin forced to input upon any device reset.
DS30289A-page 14
1998 Microchip Technology Inc.
PIC17C7XX
4.1.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
4.0
ON-CHIP OSCILLATOR
CIRCUIT
In XT or LF modes, a crystal or ceramic resonator is
connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 4-2). The
PIC17CXXX oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions.
The internal oscillator circuit is used to generate the
device clock. Four device clock periods generate an
internal instruction clock (TCY).
There are four modes that the oscillator can operate in.
They are selected by the device configuration bits dur-
ing device programming. These modes are:
• LF
• XT
Low Frequency (FOSC <= 2 MHz)
For frequencies above 20 MHz, it is common for the
crystal to be an overtone mode crystal. Use of over-
tone mode crystals require a tank circuit to attenuate
the gain at the fundamental frequency. Figure 4-3
shows an example circuit.
Standard Crystal/Resonator Frequency
(2 MHz <= FOSC <= 33 MHz)
• EC
• RC
External Clock Input
(Default oscillator configuration)
External Resistor/Capacitor
(FOSC <= 4 MHz)
4.1.2.1
OSCILLATOR / RESONATOR START-UP
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 96 ms (nomi-
nal) on POR and BOR. The PWRT is designed to keep
the part in RESET while the power supply stabilizes.
With these two timers on-chip, most applications need
no external reset circuitry.
As the device voltage increases from Vss, the oscillator
will start its oscillations. The time required for the oscil-
lator to start oscillating depends on many factors.
These include:
• Crystal / resonator frequency
• Capacitor values used (C1 and C2)
• Device VDD rise time.
• System temperature
• Series resistor value (and type) if used
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake from SLEEP
through external reset, Watchdog Timer Reset or
through an interrupt.
• Oscillator mode selection of device (which selects
the gain of the internal oscillator inverter)
Figure 4-1 shows an example of a typical oscillator/
resonator start-up. The peak-to-peak voltage of the
oscillator waveform can be quite low (less than 50% of
device VDD) when the waveform is centered at VDD/2
(refer to parameter #D033 and parameter #D043 in the
electrical specification section).
Several oscillator options are made available to allow
the part to better fit the application. The RC oscillator
option saves system cost while the LF crystal option
saves power. Configuration bits are used to select var-
ious options.
FIGURE 4-1: OSCILLATOR / RESONATOR
START-UP
4.1
Oscillator Configurations
4.1.1
OSCILLATOR TYPES
CHARACTERISTICS
The PIC17CXXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
• LF
• XT
• EC
• RC
Low Power Crystal
Crystal/Resonator
External Clock Input
Resistor/Capacitor
The main difference between the LF and XT modes is
the gain of the internal inverter of the oscillator circuit
which allows the different frequency ranges.
For more details on the device configuration bits, see
Section 17.0.
Crystal Start-up Time
Time
1998 Microchip Technology Inc.
DS30289A-page 15
PIC17C7XX
FIGURE 4-3: CRYSTAL OPERATION,
OVERTONE CRYSTALS (XT
OSC CONFIGURATION)
FIGURE 4-2: CRYSTAL OR CERAMIC
RESONATOR OPERATION (XT
ORLFOSCCONFIGURATION)
C1
OSC1
OSC1
SLEEP
C1
C2
XTAL
SLEEP
RF
OSC2
OSC2
Note1
C3
To internal
logic
PIC17CXXX
C2
0.1 µF
PIC17CXXX
To filter the fundamental frequency
1
See Table 4-1 and Table 4-2 for recommended values of
C1 and C2.
(2πf)2
=
L*C2
Where f = tank circuit resonant frequency. This should be
midway between the fundamental and the 3rd overtone
frequencies of the crystal.
Note 1: A series resistor (Rs) may be required for
AT strip cut crystals.
C3 handles current during charging of tank circuit.
TABLE 4-1:
CAPACITOR SELECTION
FOR CERAMIC
RESONATORS
TABLE 4-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc
Type
(3)
(3)
Freq
C1
C2
Capacitor Range
Oscillator
Type
Resonator
Frequency
(1)
(1)
C1 = C2
LF
32 kHz
100-150 pF
10-33 pF
10-33 pF
100-150 pF
10-33 pF
10-33 pF
1 MHz
2 MHz
LF
455 kHz
2.0 MHz
15 - 68 pF
10 - 33 pF
XT
2 MHz
4 MHz
8 MHz
16 MHz
25 MHz
47-100 pF
15-68 pF
15-47 pF
TBD
15-47 pF
10 pF
47-100 pF
15-68 pF
15-47 pF
TBD
15-47 pF
10 pF
XT
4.0 MHz
8.0 MHz
16.0 MHz
22 - 68 pF
33 - 100 pF
33 - 100 pF
(2)
Higher capacitance increases the stability of the oscillator
but also increases the start-up time. These values are for
design guidance only. Since each resonator has its own
characteristics, the user should consult the resonator manu-
facturer for appropriate values of external components.
Note 1: These values include all board capacitances
on this pin. Actual capacitor value depends
on board capacitance
(3)
32 MHz
Higher capacitance increases the stability of the oscillator
but also increases the start-up time and the oscillator cur-
rent. These values are for design guidance only. RS may be
required in XT mode to avoid overdriving the crystals with
low drive level specification. Since each crystal has its own
characteristics, the user should consult the crystal manufac-
turer for appropriate values for external components.
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recom-
mended.
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
2: RS of 330Ω is required for a capacitor com-
bination of 15/15 pF.
3: These values include all board capacitances
on this pin. Actual capacitor value depends
on board capacitance
16.0 MHz Murata Erie CSA16.00MX
Resonators used did not have built-in capacitors.
Crystals Used:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
1.0 MHz
2.0 MHz
4.0 MHz
8.0 MHz
ECS-10-13-1
ECS-20-20-1
ECS-40-20-1
± 50 PPM
± 50 PPM
± 50 PPM
± 50 PPM
ECS ECS-80-S-4
ECS-80-18-1
16.0 MHz
25 MHz
32 MHz
ECS-160-20-1
CTS CTS25M
CRYSTEK HF-2
TBD
± 50 PPM
± 50 PPM
DS30289A-page 16
1998 Microchip Technology Inc.
PIC17C7XX
4.1.3
EXTERNAL CLOCK OSCILLATOR
4.1.4
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
In the EC oscillator mode, the OSC1 input can be
driven by CMOS drivers. In this mode, the
OSC1/CLKIN pin is hi-impedance and the
OSC2/CLKOUT pin is the CLKOUT output (4 TOSC).
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepack-
aged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types
of crystal oscillator circuits can be used: one with series
resonance, or one with parallel resonance.
FIGURE 4-4: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Figure 4-5 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fun-
damental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a par-
allel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ potenti-
ometer biases the 74AS04 in the linear region. This
could be used for external oscillator designs.
Clock from
ext. system
OSC1
OSC2
PIC17CXXX
CLKOUT
(FOSC/4)
FIGURE 4-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10 kΩ
74AS04
PIC17CXXX
4.7 kΩ
OSC1
74AS04
10 kΩ
XTAL
10kΩ
20 pF
20 pF
Figure 4-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental fre-
quency of the crystal. The inverter performs
a
180-degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative feed-
back to bias the inverters in their linear region.
FIGURE 4-6: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
To Other
Devices
330 Ω
330 Ω
74AS04
74AS04
74AS04
PIC17CXXX
OSC1
0.1 µF
XTAL
1998 Microchip Technology Inc.
DS30289A-page 17
PIC17C7XX
4.1.5
RC OSCILLATOR
4.1.5.1
RC START-UP
For timing insensitive applications, the RC device
option offers additional cost savings. RC oscillator fre-
quency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operating
temperature. In addition to this, oscillator frequency
will vary from unit to unit due to normal process param-
eter variation. Furthermore, the difference in lead
frame capacitance between package types will also
affect oscillation frequency, especially for low Cext val-
ues. The user also needs to take into account variation
due to tolerance of external R and C components used.
Figure 4-7 shows how the R/C combination is con-
nected to the PIC17CXXX. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values (e.g.
1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 kΩ and 100 kΩ.
As the device voltage increases, the RC will immedi-
ately start its oscillations once the pin voltage levels
meet the input threshold specifications (parameter
#D032 and parameter #D042 in the electrical specifica-
tion section). The time required for the RC to start
oscillating depends on many factors. These include:
• Resistor value used
• Capacitor value used
• Device VDD rise time
• System temperature
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, oscillation frequency can
vary dramatically due to changes in external capaci-
tances, such as PCB trace capacitance or package
lead frame capacitance.
See Section 21.0 for RC frequency variation from part
to part due to normal process variation. The variation
is larger for larger R (since leakage current variation
will affect RC frequency more for large R) and for
smaller C (since variation of input capacitance will
affect RC frequency more).
See Section 21.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values as well as fre-
quency variation due to operating temperature for given
R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (see Figure 4-8 for
waveform).
FIGURE 4-7: RC OSCILLATOR MODE
VDD
PIC17CXXX
Rext
Internal
OSC1
clock
Cext
VSS
OSC2/CLKOUT
Fosc/4
DS30289A-page 18
1998 Microchip Technology Inc.
PIC17C7XX
4.2
Clocking Scheme/Instruction Cycle
4.3
Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3, and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-8.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 4-1).
A fetch cycle begins with the program counter incre-
menting in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during
Q2 (operand read) and written during Q4 (destination
write).
FIGURE 4-8: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 4-1: INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
Flush
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetched
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1998 Microchip Technology Inc.
DS30289A-page 19
PIC17C7XX
NOTES:
DS30289A-page 20
1998 Microchip Technology Inc.
PIC17C7XX
When the device enters the "reset state" the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impendance inputs. The reset state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
5.0
RESET
The PIC17CXXX differentiates between various kinds
of reset:
• Power-on Reset (POR)
• Brown-out Reset
• MCLR Reset
Note: While the device is in a reset state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
• WDT Reset
Some registers are not affected in any reset condition,
their status is unknown on POR and unchanged in any
other reset. Most other registers are forced to a “reset
state”. The TO and PD bits are set or cleared differently
in different reset situations as indicated in Table 5-3.
These bits, in conjunction with the POR and BOR bits,
are used in software to determine the nature of the
reset. See Table 5-4 for a full description of the reset
states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 5-1.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
BOR
Module
Brown-out
Reset
WDT
Module
WDT
Time_Out
Reset
VDD rise
detect
S
R
Power_On_Reset
VDD
OST/PWRT
Chip_Reset
Q
OST
10-bit Ripple counter
OSC1
PWRT
On-chip
RC OSC†
10-bit Ripple counter
(Enable the PWRT timer
only during POR or BOR)
(If PWRT is invoked, or a Wake-up from
SLEEP and OSC type is XT or LF)
† This RC oscillator is shared with the WDT
when not in a power-up sequence.
1998 Microchip Technology Inc.
DS30289A-page 21
PIC17C7XX
5.1.2
POWER-UP TIMER (PWRT)
5.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST), and Brown-out Reset
(BOR)
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from the rising
edge of the internal POR signal if VDD and MCLR are
tied, or after the first rising edge of MCLR (detected
high). The Power-up Timer operates on an internal RC
oscillator. The chip is kept in RESET as long as the
PWRT is active. In most cases the PWRT delay allows
VDD to rise to an acceptable level.
5.1.1
POWER-ON RESET (POR)
The Power-on Reset circuit holds the device in reset
until VDD is above the trip point (in the range of 1.4V -
2.3V). The devices produce an internal reset for both
rising and falling VDD. To take advantage of the POR,
just tie the MCLR/VPP pin directly (or through a resistor)
to VDD. This will eliminate external RC components
usually needed to create Power-on Reset. A minimum
rise time for VDD is required. See Electrical Specifica-
tions for details.
The power-up time delay will vary from chip to chip and
with VDD and temperature. See DC parameters for
details.
5.1.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024TOSC) delay whenever the PWRT
is invoked or a wake-up from SLEEP event occurs in XT
or LF mode. The PWRT and OST operate in parallel.
Figure 5-2 and Figure 5-3 show two possible POR cir-
cuits.
FIGURE 5-2: USING ON-CHIP POR
The OST counts the oscillator pulses on the
OSC1/CLKIN pin.The counter only starts incrementing
after the amplitude of the signal reaches the oscillator
input thresholds.This delay allows the crystal oscillator
or resonator to stabilize before the device exits reset.
The length of the time-out is a function of the crys-
tal/resonator frequency.
VDD
VDD
MCLR
PIC17CXXX
Figure 5-4 shows the operation of the OST circuit. In
this figure the oscillator is of such a low frequency that
although enabled simultaneously, the OST does not
time-out until after the Power-up Timer time-out.
FIGURE 5-3: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 5-4: OSCILLATOR START-UP
TIME (LOW FREQ)
VDD
VDD
POR or BOR Trip Point
D
R
VDD
R1
MCLR
PIC17CXXX
C
MCLR
OSC2
TOSC1
TOST
Note 1: An external Power-on Reset circuit is
required only if VDD power-up time is too
slow. The diode D helps discharge the
capacitor quickly when VDD powers
down.
OST TIME_OUT
PWRT TIME_OUT
TPWRT
2: R < 40 kΩ is recommended to ensure
that the voltage drop across R does not
exceed 0.2V (max. leakage current spec.
on the MCLR/VPP pin is 5 µA). A larger
voltage drop will degrade VIH level on the
MCLR/VPP pin.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capaci-
tor C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
INTERNAL RESET
This figure shows in greater detail the timings
involved with the oscillator start-up timer. In this
example the low frequency crystal start-up time is
larger than power-up time (TPWRT).
Tosc1 = time for the crystal oscillator to react to an
oscillation level detectable by the Oscillator
Start-up Timer (OST).
TOST = 1024TOSC.
DS30289A-page 22
1998 Microchip Technology Inc.
PIC17C7XX
5.1.4
TIME-OUT SEQUENCE
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/VPP pin must be
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resona-
tors. The total time-out also varies based on oscillator
configuration. Table 5-1 shows the times that are asso-
ciated with the oscillator configuration. Figure 5-5 and
Figure 5-6 display these time-out sequences.
The time-out sequence begins from the first rising edge
of MCLR.
Table 5-3 shows the reset conditions for some special
registers, while Table 5-4 shows the initialization condi-
tions for all the registers.
TABLE 5-1:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
POR, BOR
Wake up from
SLEEP
MCLR Reset
XT, LF
Greater of: 96 ms or 1024TOSC
Greater of: 96 ms or 1024TOSC
1024TOSC
—
—
—
EC, RC
TABLE 5-2:
STATUS BITS AND THEIR SIGNIFICANCE
(1)
POR
TO
PD
Event
BOR
0
1
1
1
1
1
0
0
x
0
1
1
1
1
0
0
0
x
1
1
0
0
1
1
0
x
1
1
0
1
0
1
1
x
0
1
Power-on Reset
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
MCLR Reset during normal operation
Brown-out Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
CLRWDTinstruction executed
Note 1: When BODEN is enabled, else the BOR status bit is unknown.
TABLE 5-3:
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
(4)
Event
PCH:PCL
CPUSTA
OST Active
Power-on Reset
Brown-out Reset
0000h
--11 1100
Yes
0000h
0000h
0000h
--11 1110
--11 1111
--11 1011
Yes
No
MCLR Reset during normal operation
MCLR Reset during SLEEP
(2)
Yes
WDT Reset during normal operation
0000h
0000h
--11 0111
--11 0011
No
(3)
(2)
WDT Wake-up during SLEEP
Yes
(2)
Interrupt wake-up from SLEEP GLINTD is set
GLINTD is clear
PC + 1
--11 1011
--10 1011
Yes
(1)
(2)
PC + 1
Yes
Legend: u= unchanged, x= unknown, -= unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active (on wake-up) when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is, the device branches to the reset vector. This is different from the
mid-range devices.
4: When BODEN is enabled, else the BOR status bit is unknown.
1998 Microchip Technology Inc.
DS30289A-page 23
PIC17C7XX
In Figure 5-5, Figure 5-6 and Figure 5-7, the TPWRT
timer timeout is greater then the TOST timer timeout, as
would be the case in higher frequency crystals. For
lower frequency crystals, (i.e., 32 kHz) TOST may be
greater.
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 5-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 5-7: SLOW RISE TIME (MCLR TIED TO VDD)
Minimum VDD operating voltage
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30289A-page 24
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Address
Unbanked
INDF0
FSR0
00h
01h
02h
N.A.
xxxx xxxx
0000h
N.A.
uuuu uuuu
0000h
N.A.
uuuu uuuu
(2)
PCL
PC + 1
PCLATH
ALUSTA
T0STA
03h
04h
05h
06h
0000 0000
1111 xxxx
0000 000-
--11 11qq
uuuu uuuu
1111 uuuu
0000 000-
--11 qquu
uuuu uuuu
1111 uuuu
0000 000-
--uu qquu
(3)
CPUSTA
(1)
INTSTA
07h
0000 0000
0000 0000
uuuu uuuu
INDF1
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
N.A.
N.A.
N.A.
FSR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
(4,6)
10h
0-xx 11xx
0-uu 11uu
u-uu uuuu
PORTA
DDRB
11h
12h
1111 1111
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
(4)
PORTB
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
13h
14h
15h
16h
17h
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
0000 0000
uuuu -uuu
uuuu uuuu
uuuu --uu
uuuu uuuu
uuuu uuuu
Legend: u= unchanged,
x= unknown,
-= unimplemented read as '0', q= value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this
port does not rely on these registers
6: On any device reset, these pins are configured as inputs.
1998 Microchip Technology Inc.
DS30289A-page 25
PIC17C7XX
TABLE 5-4:
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Register
Bank 1
Address
(5)
10h
11h
12h
13h
14h
15h
16h
17h
1111 1111
xxxx xxxx
1111 1111
xxxx xxxx
---- 1111
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
DDRC
(4, 5)
uuuu uuuu
1111 1111
uuuu uuuu
---- 1111
PORTC
(5)
DDRD
(4, 5)
PORTD
(5)
DDRE
(4, 5)
---- xxxx
---- uuuu
---- uuuu
PORTE
PIR1
(1)
x000 0010
0000 0000
u000 0010
0000 0000
uuuu uuuu
PIE1
uuuu uuuu
Bank 2
TMR1
TMR2
TMR3L
TMR3H
PR1
10h
11h
12h
13h
14h
15h
16h
17h
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PR2
PR3/CA1L
PR3/CA1H
Bank 3
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
10h
11h
12h
13h
14h
15h
16h
17h
xx-- ----
xx0- ----
uu-- ----
uu-- ----
uu0- ----
uuu- ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
CA2H
TCON1
TCON2
Legend: u= unchanged,
x= unknown,
-= unimplemented read as '0', q= value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this
port does not rely on these registers
6: On any device reset, these pins are configured as inputs.
DS30289A-page 26
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Address
Bank 4
(1)
PIR2
10h
000- 0010
000- 0010
uuu- uuuu
PIE2
11h
12h
13h
14h
15h
16h
17h
000- 0000
---- ----
000- 0000
---- ----
uuu- uuuu
---- ----
Unimplemented
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
0000 0000
uuuu -uuu
uuuu uuuu
uuuu --uu
uuuu uuuu
uuuu uuuu
Bank 5
DDRF
10h
11h
1111 1111
0000 0000
1111 1111
0000 0000
uuuu uuuu
uuuu uuuu
(4)
PORTF
DDRG
12h
13h
1111 1111
xxxx 0000
1111 1111
uuuu 0000
uuuu uuuu
uuuu uuuu
(4)
PORTG
ADCON0
ADCON1
ADRESL
ADRESH
14h
15h
16h
17h
0000 -0-0
000- 0000
xxxx xxxx
xxxx xxxx
0000 -0-0
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Bank 6
SSPADD
10h
11h
12h
13h
14h
15h
16h
17h
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
---- ----
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
---- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ----
SSPCON1
SSPCON2
SSPSTAT
SSPBUF
Unimplemented
Unimplemented
Unimplemented
---- ----
---- ----
---- ----
---- ----
---- ----
---- ----
Legend: u= unchanged,
x= unknown,
-= unimplemented read as '0', q= value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this
port does not rely on these registers
6: On any device reset, these pins are configured as inputs.
1998 Microchip Technology Inc.
DS30289A-page 27
PIC17C7XX
TABLE 5-4:
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Register
Address
Bank 7
PW3DCL
PW3DCH
CA3L
10h
11h
12h
13h
14h
15h
16h
17h
xx0- ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-000 0000
---- ----
uu0- ----
uuu- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-000 0000
---- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- ----
CA3H
CA4L
CA4H
TCON3
Unimplemented
Bank 8
DDRH
10h
11h
1111 1111
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
(4)
PORTH
DDRJ
12h
13h
1111 1111
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
(4)
PORTJ
Unbanked
PRODL
18h
19h
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PRODH
Legend: u= unchanged,
x= unknown,
-= unimplemented read as '0', q= value depends on condition.
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for reset value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or externded microcontroller mode, the operation of this
port does not rely on these registers
6: On any device reset, these pins are configured as inputs.
DS30289A-page 28
1998 Microchip Technology Inc.
PIC17C7XX
5.1.5
BROWN-OUT RESET (BOR)
FIGURE 5-8: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
PIC17C7XX devices have on-chip Brown-out Reset cir-
cuitry. This circuitry places the device into a reset when
the device voltage falls below a trip point (BVDD). This
ensures that the device does not continue program
execution outside the valid operation range of the
device. Brown-out resets are typically used in AC line
applications or large battery applications where large
loads may be switched in (such as automotive).
VDD
VDD
33k
10kΩ
MCLR
40 kΩ
PIC17CXXX
Note: Before using the on-chip brown-out for a
voltage supervisory function, please
review the electrical specifications to
ensure that they meet your requirements.
This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
The BODEN configuration bit can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below BVDD (Typically 4.0V,
parameter #D005 in electrical specification section), for
greater than parameter #35, the brown-out situation will
reset the chip. A reset is not guaranteed to occur if VDD
falls below BVDD for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer and Oscillator Start-up
Timer will then be invoked. This will keep the chip in
reset the greater of 96 ms and 1024 TOSC. If VDD drops
below BVDD while the Power-up Timer/Oscillator
Start-up Timer is running, the chip will go back into a
Brown-out Reset. The Power-up Timer/Oscillator
Start-up Timer will be initialized. Once VDD rises above
BVDD, the Power-up Timer/Oscillator Start-up Timer
will start their time delays. Figure 5-10 shows typical
Brown-out situations.
FIGURE 5-9: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
40 kΩ
PIC17CXXX
This brown-out circuit is less expensive, albeit less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
R1
= 0.7V
VDD •
R1 + R2
In some applications, the Brown-out reset trip point of
the device may not be at the desired level. Figure 5-8
and Figure 5-9 are two examples of external circuitry
that may be implemented. Each needs to be evaluated
to determine if they match the requirements of the
application.
FIGURE 5-10: BROWN-OUT SITUATIONS
VDD
BVDD Max.
BVDD Min.
Internal
Reset
Greater of 96 ms
and 1024 Tosc
VDD
BVDD Max.
BVDD Min.
Internal
Reset
< 96 ms
Greater of 96 ms
and 1024 Tosc
VDD
BVDD Max.
BVDD Min.
Internal
Reset
Greater of 96 ms
and 1024 Tosc
1998 Microchip Technology Inc.
DS30289A-page 29
PIC17C7XX
NOTES:
DS30289A-page 30
1998 Microchip Technology Inc.
PIC17C7XX
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupts, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. There are four
interrupt vectors. Each vector address is for a specific
interrupt source (except the peripheral interrupts which
all vector to the same address). These sources are:
6.0
INTERRUPTS
PIC17C7XX devices have 18 sources of interrupt:
• External interrupt from the RA0/INT pin
• Change on RB7:RB0 pins
• TMR0 Overflow
• TMR1 Overflow
• TMR2 Overflow
• TMR3 Overflow
• External interrupt from the RA0/INT pin
• TMR0 Overflow
• T0CKI edge occurred
• USART1 Transmit buffer empty
• USART1 Receive buffer full
• USART2 Transmit buffer empty
• USART2 Receive buffer full
• SSP Interrupt
• Any peripheral interrupt
When program execution vectors to one of these inter-
rupt vector addresses (except for the peripheral inter-
rupts), the interrupt flag bit is automatically cleared.
Vectoring to the peripheral interrupt vector address
does not automatically clear the source of the interrupt.
In the peripheral interrupt service routine, the source(s)
of the interrupt can be determined by testing the inter-
rupt flag bits. The interrupt flag bit(s) must be cleared
in software before re-enabling interrupts to avoid infi-
nite interrupt requests.
2
• SSP I C bus collision interrupt
• A/D conversion complete
• Capture1
• Capture2
• Capture3
• Capture4
• T0CKI edge occurred
There are six registers used in the control and status of
interrupts. These are:
When an interrupt condition is met, that individual inter-
rupt flag bit will be set regardless of the status of its cor-
responding mask bit or the GLINTD bit.
• CPUSTA
• INTSTA
• PIE1
• PIR1
• PIE2
For external interrupt events, there will be an interrupt
latency. For two cycle instructions, the latency could
be one instruction cycle longer.
• PIR2
The “return from interrupt” instruction, RETFIE, can be
used to mark the end of the interrupt service routine.
When this instruction is executed, the stack is “POPed”,
and the GLINTD bit is cleared (to re-enable interrupts).
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Section 6.4.
FIGURE 6-1: INTERRUPT LOGIC
RBIF
RBIE
TMR3IF
TMR3IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
INTSTA
Wake-up (If in SLEEP mode)
or terminate long write
CA2IF
CA2IE
T0IF
T0IE
CA1IF
CA1IE
TX1IF
TX1IE
INTF
INTE
Interrupt to CPU
T0CKIF
RC1IF
RC1IE
T0CKIE
PEIF
SSPIF
SSPIE
PEIE
BCLIF
BCLIE
GLINTD (CPUSTA<4>)
ADIF
ADIE
CA4IF
CA4IE
CA3IF
CA3IE
TX2IF
TX2IE
RC2IF
RC2IE
1998 Microchip Technology Inc.
DS30289A-page 31
PIC17C7XX
6.1
Interrupt Status Register (INTSTA)
Note: All interrupt flag bits get set by their speci-
fied condition, even if the corresponding
interrupt enable bit is clear (interrupt dis-
abled) or the GLINTD bit is set (all inter-
rupts disabled).
The Interrupt Status/Control register (INTSTA) contains
the flag and enable bits for non-peripheral interrupts.
The PEIF bit is a read only, bit wise OR of all the periph-
eral flag bits in the PIR registers (Figure 6-5 and
Figure 6-6).
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is
cleared, the device will vector to the reset address
(0x00).
Prior to disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
FIGURE 6-2: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R - 0
PEIF
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7
bit 7:
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits. The
interrupt logic forces program execution to address (20h) when a peripheral interrupt is pending.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
bit 6:
bit 5:
bit 4:
bit 3:
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin
PEIE: Peripheral Interrupt Enable bit
This bit acts as a global enable bit for the peripheral interrupts that have their corresponding enable bits
set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
bit 2:
bit 1:
bit 0:
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin
DS30289A-page 32
1998 Microchip Technology Inc.
PIC17C7XX
6.2
Peripheral Interrupt Enable Register1
(PIE1) and Register2 (PIE2)
These registers contains the individual enable bits for
the peripheral interrupts.
FIGURE 6-3: PIE1 REGISTER (ADDRESS: 17h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE
R = Readable bit
W = Writable bit
-n = Value at POR reset
bit7
bit0
bit 7:
RBIE: PORTB Interrupt on Change Enable bit
1 = Enable PORTB interrupt on change
0 = Disable PORTB interrupt on change
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TMR3IE: TMR3 Interrupt Enable bit
1 = Enable TMR3 interrupt
0 = Disable TMR3 interrupt
TMR2IE: TMR2 Interrupt Enable bit
1 = Enable TMR2 interrupt
0 = Disable TMR2 interrupt
TMR1IE: TMR1 Interrupt Enable bit
1 = Enable TMR1 interrupt
0 = Disable TMR1 interrupt
CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture2 interrupt
0 = Disable Capture2 interrupt
CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture1 interrupt
0 = Disable Capture1 interrupt
TX1IE: USART1 Transmit Interrupt Enable bit
1 = Enable USART1 Transmit buffer empty interrupt
0 = Disable USART1 Transmit buffer empty interrupt
RC1IE: USART1 Receive Interrupt Enable bit
1 = Enable USART1 Receive buffer full interrupt
0 = Disable USART1 Receive buffer full interrupt
1998 Microchip Technology Inc.
DS30289A-page 33
PIC17C7XX
FIGURE 6-4: PIE2 REGISTER (ADDRESS: 11h, BANK 4)
R/W - 0 R/W - 0 R/W - 0
U - 0
—
R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA4IE CA3IE TX2IE RC2IE
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
SSPIE BCLIE
ADIE
bit7
bit 7:
bit 6:
bit 5:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enable SSP Interrupt
0 = Disable SSP Interrupt
BCLIE: Bus Collision Interrupt Enable bit
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
ADIE: A/D Module Interrupt Enable bit
1 = Enable A/D Module Interrupt
0 = Disable A/D Module Interrupt
bit 4:
bit 3:
Unimplemented: Read as ‘0’
CA4IE: Capture4 Interrupt Enable bit
1 = Enable Capture4 Interrupt
0 = Disable Capture4 Interrupt
bit 2:
bit 1:
bit 0:
CA3IE: Capture3 Interrupt Enable bit
1 = Enable Capture3 Interrupt
0 = Disable Capture3 Interrupt
TX2IE: USART2 Transmit Interrupt Enable bit
1 = Enable USART2 Transmit Buffer Empty Interrupt
0 = Disable USART2 Transmit Buffer Empty Interrupt
RC2IE: USART2 Receive Interrupt Enable bit
1 = Enable USART2 Receive Buffer Full Interrupt
0 = Disable USART2 Receive Buffer Full Interrupt
DS30289A-page 34
1998 Microchip Technology Inc.
PIC17C7XX
6.3
Peripheral Interrupt Request
Register1 (PIR1) and Register2 (PIR2)
Note: These bits will be set by the specified con-
dition, even if the corresponding interrupt
enable bit is cleared (interrupt disabled), or
the GLINTD bit is set (all interrupts dis-
abled). Before enabling an interrupt, the
user may wish to clear the interrupt flag to
ensure that the program does not immedi-
ately branch to the peripheral interrupt ser-
vice routine.
These registers contains the individual flag bits for the
peripheral interrupts.
FIGURE 6-5: PIR1 REGISTER (ADDRESS: 16h, BANK 1)
R/W - x R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R - 1 R - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
RBIF TMR3IF TMR2IF TMR1IF CA2IF
CA1IF TX1IF RC1IF
bit7
bit0
bit 7:
bit 6:
RBIF: PORTB Interrupt on Change Flag bit
1 = One of the PORTB inputs changed (software must end the mismatch condition)
0 = None of the PORTB inputs have changed
TMR3IF: TMR3 Interrupt Flag bit
If Capture1 is enabled (CA1/PR3 = 1)
1 = TMR3 overflowed
0 = TMR3 did not overflow
If Capture1 is disabled (CA1/PR3 = 0)
1 = TMR3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value
0 = TMR3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L) value
bit 5:
bit 4:
TMR2IF: TMR2 Interrupt Flag bit
1 = TMR2 value has rolled over to 0000h from equalling the period register (PR2) value
0 = TMR2 value has not rolled over to 0000h from equalling the period register (PR2) value
TMR1IF: TMR1 Interrupt Flag bit
If TMR1 is in 8-bit mode (T16 = 0)
1 = TMR1 value has rolled over to 0000h from equalling the period register (PR1) value
0 = TMR1 value has not rolled over to 0000h from equalling the period register (PR1) value
If Timer1 is in 16-bit mode (T16 = 1)
1 = TMR2:TMR1 value has rolled over to 0000h from equalling the period register (PR2:PR1) value
0 = TMR2:TMR1 value has not rolled over to 0000h from equalling the period register (PR2:PR1) value
bit 3:
bit 2:
bit 1:
bit 0:
CA2IF: Capture2 Interrupt Flag bit
1 = Capture event occurred on RB1/CAP2 pin
0 = Capture event did not occur on RB1/CAP2 pin
CA1IF: Capture1 Interrupt Flag bit
1 = Capture event occurred on RB0/CAP1 pin
0 = Capture event did not occur on RB0/CAP1 pin
TX1IF: USART1 Transmit Interrupt Flag bit (State controlled by hardware)
1 = USART1 Transmit buffer is empty
0 = USART1 Transmit buffer is full
RC1IF: USART1 Receive Interrupt Flag bit (State controlled by hardware)
1 = USART1 Receive buffer is full
0 = USART1 Receive buffer is empty
1998 Microchip Technology Inc.
DS30289A-page 35
PIC17C7XX
FIGURE 6-6: PIR2 REGISTER (ADDRESS: 10h, BANK 4)
R/W - 0 R/W - 0 R/W - 0
U - 0
—
R/W - 0 R/W - 0
CA4IF CA3IF
R - 1
TX2IF
R - 0
RC2IF
R = Readable bit
SSPIF BCLIF
ADIF
W = Writable bit
-n = Value at POR reset
bit7
bit0
bit 7:
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the
interrupt service routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I C Slave / Master
2
A transmission/reception has taken place.
I C Master
2
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0 = An SSP interrupt condition has NOT occurred.
bit 6:
bit 5:
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I C master mode
0 = No bus collision has occurred
2
ADIF: A/D Module Interrupt Flag bit
1 = An A/D conversion is complete
0 = An A/D conversion is not complete
bit 4:
bit 3:
Unimplemented: Read as '0'
CA4IF: Capture4 Interrupt Flag bit
1 = Capture event occurred on RE3/CAP4 pin
0 = Capture event did not occur on RE3/CAP4 pin
bit 2:
bit 1:
bit 0:
CA3IF: Capture3 Interrupt Flag bit
1 = Capture event occurred on RG4/CAP3 pin
0 = Capture event did not occur on RG4/CAP3 pin
TX2IF:USART2 Transmit Interrupt Flag bit (State controlled by hardware)
1 = USART2 Transmit buffer is empty
0 = USART2 Transmit buffer is full
RC2IF: USART2 Receive Interrupt Flag bit (State controlled by hardware)
1 = USART2 Receive buffer is full
0 = USART2 Receive buffer is empty
DS30289A-page 36
1998 Microchip Technology Inc.
PIC17C7XX
6.4
Interrupt Operation
6.5
RA0/INT Interrupt
Global Interrupt Disable bit, GLINTD (CPUSTA<4>),
enables all unmasked interrupts (if clear) or disables all
interrupts (if set). Individual interrupts can be disabled
through their corresponding enable bits in the INTSTA
register. Peripheral interrupts need either the global
peripheral enable PEIE bit disabled, or the specific
peripheral enable bit disabled. Disabling the peripher-
als via the global peripheral enable bit, disables all
peripheral interrupts. GLINTD is set on reset (interrupts
disabled).
The external interrupt on the RA0/INT pin is edge trig-
gered. Either the rising edge, if the INTEDG bit
(T0STA<7>) is set, or the falling edge, if the INTEDG bit
is clear. When a valid edge appears on the RA0/INT
pin, the INTF bit (INTSTA<4>) is set. This interrupt can
be disabled by clearing the INTE control bit
(INTSTA<0>). The INT interrupt can wake the proces-
sor from SLEEP. See Section 17.4 for details on
SLEEP operation.
6.6
T0CKI Interrupt
The RETFIE instruction clears the GLINTD bit while
forcing the Program Counter (PC) to the value loaded
at the Top of Stack.
The external interrupt on the RA1/T0CKI pin is edge
triggered. Either the rising edge, if the T0SE bit
(T0STA<6>) is set, or the falling edge, if the T0SE bit is
clear. When a valid edge appears on the RA1/T0CKI
pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt
can be disabled by clearing the T0CKIE control bit
(INTSTA<2>). The T0CKI interrupt can wake up the
processor from SLEEP. See Section 17.4 for details on
SLEEP operation.
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector. There are four inter-
rupt vectors which help reduce interrupt latency.
The peripheral interrupt vector has multiple interrupt
sources. Once in the peripheral interrupt service rou-
tine, the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The peripheral interrupt
flag bit(s) must be cleared in software before
re-enabling interrupts to avoid continuous interrupts.
6.7
Peripheral Interrupt
The peripheral interrupt flag indicates that at least one
of the peripheral interrupts occurred (PEIF is set). The
PEIF bit is a read only bit, and is a bit wise OR of all the
flag bits in the PIR registers AND’ed with the corre-
sponding enable bits in the PIE registers. Some of the
peripheral interrupts can wake the processor from
SLEEP. See Section 17.4 for details on SLEEP opera-
tion.
The PIC17C7XX devices have four interrupt vectors.
These vectors and their hardware priority are shown in
Table 6-1. If two enabled interrupts occur “at the same
time”, the interrupt of the highest priority will be ser-
viced first. This means that the vector address of that
interrupt will be loaded into the program counter (PC).
6.8
Context Saving During Interrupts
TABLE 6-1:
INTERRUPT
VECTORS/PRIORITIES
During an interrupt, only the returned PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt; e.g. WREG, ALUSTA and the
BSR registers. This requires implementation in soft-
ware.
Address
Vector
Priority
0008h
0010h
0018h
0020h
External Interrupt on
RA0/INT pin (INTF)
1 (Highest)
TMR0 overflow interrupt
(T0IF)
2
3
Example 6-2 shows the saving and restoring of infor-
mation for an interrupt service routine. This is for a sim-
ple interrupt scheme, where only one interrupt may
occur at a time (no interrupt nesting). The SFRs are
stored in the non-banked GPR area.
External Interrupt on T0CKI
(T0CKIF)
Peripherals (PEIF)
4 (Lowest)
Example 6-2 shows the saving and restoring of infor-
mation for a more complex interrupt service routine.
This is useful where nesting of interrupts is required. A
maximum of 6 levels can be done by this example. The
BSR is stored in the non-banked GPR area, while the
other registers would be stored in a particular bank.
Therefore 6 saves may be done with this routine (since
there are 6 non-banked GPR registers). These rou-
tines require a dedicated indirect addressing register,
FSR0 to be selected for this.
Note 1: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GLINTD bit.
Note 2: Before disabling any of the INTSTA enable
bits, the GLINTD bit should be set
(disabled).
The PUSH and POP code segments could either be in
each interrupt service routine or could be subroutines
that were called. Depending on the application, other
registers may also need to be saved.
1998 Microchip Technology Inc.
DS30289A-page 37
PIC17C7XX
FIGURE 6-7: INT PIN / T0CKI PIN INTERRUPT TIMING
DS30289A-page 38
1998 Microchip Technology Inc.
PIC17C7XX
EXAMPLE 6-1: SAVING STATUS AND WREG IN RAM (SIMPLE)
; The addresses that are used to store the CPUSTA and WREG values must be in the data memory
; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP
; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.
;
UNBANK1
UNBANK2
UNBANK3
UNBANK4
UNBANK5
EQU
EQU
EQU
EQU
EQU
0x01A
0x01B
0x01C
0x01D
0x01E
; Address for 1st location to save
; Address for 2nd location to save
; Address for 3rd location to save
; Address for 4th location to save
; Address for 5th location to save
;
(Label Not used in program)
; Address for 6th location to save
(Label Not used in program)
UNBANK6
;
EQU
0x01F
;
:
; At Interrupt Vector Address
; Push ALUSTA value
; Push BSR value
; Push WREG value
; Push PCLATH value
PUSH
MOVFP
MOVFP
MOVFP
MOVFP
;
ALUSTA, UNBANK1
BSR, UNBANK2
WREG, UNBANK3
PCLATH, UNBANK4
:
; Interrupt Service Routine (ISR) code
;
POP
;
MOVFP
MOVFP
MOVFP
MOVFP
UNBANK4, PCLATH
UNBANK3, WREG
UNBANK2, BSR
; Restore PCLATH value
; Restore WREG value
; Restore BSR value
; Restore ALUSTA value
UNBANK1, ALUSTA
RETFIE
; Return from interrupt (enable interrupts)
1998 Microchip Technology Inc.
DS30289A-page 39
PIC17C7XX
EXAMPLE 6-2: SAVING STATUS AND WREG IN RAM (NESTED)
; The addresses that are used to store the CPUSTA and WREG values must be in the data memory
; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP
; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.
; This routine uses the FRS0, so it controls the FS1 and FS0 bits in the ALUSTA register.
;
Nobank_FSR
Bank_FSR
ALU_Temp
WREG_TEMP
BSR_S1
BSR_S2
BSR_S3
BSR_S4
BSR_S5
BSR_S6
;
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0x40
0x41
0x42
0x43
0x01A
0x01B
0x01C
0x01D
0x01E
0x01F
; 1st location to save BSR
; 2nd location to save BSR (Label Not used in program)
; 3rd location to save BSR (Label Not used in program)
; 4th location to save BSR (Label Not used in program)
; 5th location to save BSR (Label Not used in program)
; 6th location to save BSR (Label Not used in program)
INITIALIZATION
CALL
;
CLEAR_RAM
; Must Clear all Data RAM
;
INIT_POINTERS
CLRF
; Must Initialize the pointers for POP and PUSH
; Set All banks to 0
BSR, F
CLRF
BSF
CLRF
MOVLW
MOVWF
MOVWF
MOVLW
MOVWF
:
ALUSTA, F
ALUSTA, FS1
WREG, F
BSR_S1
FSR0
Nobank_FSR
0x20
; FSR0 post increment
; Clear WREG
; Load FSR0 with 1st address to save BSR
Bank_FSR
:
; Your code
:
:
; At Interrupt Vector Address
PUSH
BSF
ALUSTA, FS0
; FSR0 has auto-increment, does not affect status bits
BCF
ALUSTA, FS1
; does not affect status bits
MOVFP
CLRF
MOVPF
MOVPF
MOVPF
MOVFP
MOVFP
MOVFP
MOVFP
MOVPF
MOVFP
;
BSR, INDF0
BSR, F
; No Status bits are affected
; Peripheral and Data RAM Bank 0 No Status bits are affected
;
; Save the FSR for BSR values
;
; Restore FSR value for other values
; Push ALUSTA value
; Push WREG value
ALUSTA, ALU_Temp
FSR0, Nobank_FSR
WREG, WREG_TEMP
Bank_FSR, FSR0
ALU_Temp, INDF0
WREG_TEMP, INDF0
PCLATH, INDF0
FSR0, Bank_FSR
Nobank_FSR, FSR0
; Push PCLATH value
; Restore FSR value for other values
;
:
; Interrupt Service Routine (ISR) code
;
POP
CLRF
MOVFP
DECF
MOVFP
MOVFP
BSF
MOVPF
MOVPF
DECF
MOVFP
MOVFP
MOVFP
ALUSTA, F
Bank_FSR, FSR0
FSR0, F
INDF0, PCLATH
INDF0, WREG
ALUSTA, FS1
INDF0, ALU_Temp
FSR0, Bank_FSR
Nobank_FSR, F
Nobank_FSR, FSR0
ALU_Temp, ALUSTA
INDF0, BSR
; FSR0 has auto-decrement, does not affect status bits
; Restore FSR value for other values
;
; Pop PCLATH value
; Pop WREG value
; FSR0 does not change
; Pop ALUSTA value
; Restore FSR value for other values
;
; Save the FSR for BSR values
;
; No Status bits are affected
;
RETFIE
; Return from interrupt (enable interrupts)
DS30289A-page 40
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 7-1: PROGRAM MEMORY MAP
AND STACK
7.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC17C7XX; pro-
gram memory and data memory. Each block has its
own bus, so that access to each block can occur during
the same oscillator cycle.
PC<15:0>
16
CALL, RETURN
RETFIE, RETLW
Stack Level 1
The data memory can further be broken down into
General Purpose RAM and the Special Function Reg-
isters (SFRs). The operation of the SFRs that control
the “core” are described here. The SFRs used to con-
trol the peripheral modules are described in the section
discussing each individual peripheral module.
•
•
•
Stack Level 16
Reset Vector
0000h
INT Pin Interrupt Vector
Timer0 Interrupt Vector
T0CKI Pin Interrupt Vector
Peripheral Interrupt Vector
0008h
0010h
0018h
7.1
Program Memory Organization
PIC17C7XX devices have a 16-bit program counter
capable of addressing a 64K x 16 program memory
space. The reset vector is at 0000h and the interrupt
vectors are at 0008h, 0010h, 0018h, and 0020h
(Figure 7-1).
0020h
0021h
7.1.1
PROGRAM MEMORY OPERATION
The PIC17C7XX can operate in one of four possible
program memory configurations. The configuration is
selected by configuration bits. The possible modes
are:
1FFFh
(PIC17C752
PIC17C762)
• Microprocessor
• Microcontroller
3FFFh
(PIC17C756A
PIC17C766)
• Extended Microcontroller
• Protected Microcontroller
The microcontroller and protected microcontroller
modes only allow internal execution. Any access
beyond the program memory reads unknown data.
The protected microcontroller mode also enables the
code protection feature.
FDFFh
FE00h
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
Reserved
PM1
Reserved
FE01h
FE02h
FE03h
FE04h
FE05h
FE06h
FE07h
FE08h
FE0Dh
FE0Eh
The extended microcontroller mode accesses both
the internal program memory as well as external pro-
gram memory. Execution automatically switches
between internal and external memory. The 16-bits of
address allow a program memory range of 64K-words.
Reserved
BODEN
PM2
The microprocessor mode only accesses the exter-
nal program memory. The on-chip program memory is
ignored. The 16-bits of address allow a program mem-
ory range of 64K-words. Microprocessor mode is the
default mode of an unprogrammed device.
FE0Fh
FE10h
Test EPROM
FF5Fh
FF60h
Boot ROM
FFFFh
The different modes allow different access to the con-
figuration bits, test memory, and boot ROM. Table 7-1
lists which modes can access which areas in memory.
Test Memory and Boot Memory are not required for
normal operation of the device. Care should be taken
to ensure that no unintended branches occur to these
areas.
Note 1: User memory space may be internal, external, or
both. The memory configuration depends on the
processor mode.
1998 Microchip Technology Inc.
DS30289A-page 41
PIC17C7XX
The PIC17C7XX can operate in modes where the pro-
gram memory is off-chip. They are the microprocessor
and extended microcontroller modes. The micropro-
cessor mode is the default for an unprogrammed
device.
TABLE 7-1:
MODE MEMORY ACCESS
Internal
Program
Memory
Configuration Bits,
Test Memory,
Boot ROM
Operating
Mode
Regardless of the processor mode, data memory is
always on-chip.
Microprocessor
Microcontroller
No Access
Access
No Access
Access
Extended
Microcontroller
Access
Access
No Access
Access
Protected
Microcontroller
FIGURE 7-2: MEMORY MAP IN DIFFERENT MODES
Extended
Microcontroller
Mode
Microcontroller
Modes
Microprocessor
Mode
0000h
0000h
0000h
On-chip
Program
Memory
On-chip
Program
Memory
01FFFh
2000h
01FFFh
2000h
External
Program
Memory
External
Program
Memory
PIC17C752/762
Config. Bits
Test Memory
Boot ROM
FE00h
FFFFh
FFFFh
FFFFh
OFF-CHIP
ON-CHIP
00h
OFF-CHIP
ON-CHIP
00h
OFF-CHIP
ON-CHIP
00h
120h
120h
120h
FFh 1FFh
ON-CHIP
FFh 1FFh
ON-CHIP
FFh 1FFh
ON-CHIP
0000h
3FFFh
0000h
0000h
On-chip
Program
Memory
On-chip
Program
Memory
3FFFh
4000h
External
Program
Memory
4000h
External
Program
Memory
PIC17C756A/766
Config. Bits
Test Memory
Boot ROM
FE00h
FFFFh
FFFFh
FFFFh
OFF-CHIP
00h
ON-CHIP
OFF-CHIP
00h
ON-CHIP
OFF-CHIP
ON-CHIP
00h
120h
120h
120h
220h 320h
2FFh 3FFh
320h
320h
220h
2FFh
220h
2FFh
FFh 1FFh
FFh 1FFh
FFh 1FFh
3FFh
3FFh
ON-CHIP
ON-CHIP
ON-CHIP
DS30289A-page 42
1998 Microchip Technology Inc.
PIC17C7XX
7.1.2
EXTERNAL MEMORY INTERFACE
In extended microcontroller mode, when the device is
executing out of internal memory, the control signals
will continue to be active. That is, they indicate the
action that is occurring in the internal memory. The
external memory access is ignored.
When either microprocessor or extended microcontrol-
ler mode is selected, PORTC, PORTD and PORTE are
configured as the system bus. PORTC and PORTD are
the multiplexed address/data bus and PORTE<2:0> is
for the control signals. External components are
needed to demultiplex the address and data. This can
be done as shown in Figure 7-4. The waveforms of
address and data are shown in Figure 7-3. For com-
plete timings, please refer to the electrical specification
section.
This following selection is for use with Microchip
EPROMs. For interfacing to other manufacturers mem-
ory, please refer to the electrical specifications of the
desired PIC17C7XX device, as well as the desired
memory device to ensure compatibility.
TABLE 7-2:
EPROM MEMORY ACCESS
TIME ORDERING SUFFIX
FIGURE 7-3: EXTERNAL PROGRAM
MEMORY ACCESS
PIC17C7XX Instruction
Oscillator Cycle
Frequency Time (TCY)
WAVEFORMS
Q1 Q2
Q4 Q1 Q2
Q4 Q1
Data out
Q3
Q3
EPROM Suffix
AD
<15:0>
8 MHz
16 MHz
20 MHz
25 MHz
33 MHz
500 ns
250 ns
200 ns
160 ns
121 ns
-25
-15
-10
-70
(1)
Address out Data in
Address out
ALE
OE
'1'
WR
Read cycle
Write cycle
The system bus requires that there is no bus conflict
(minimal leakage), so the output value (address) will be
capacitively held at the desired value.
Note 1: The access times for this requires the use of
fast SRAMs.
As the speed of the processor increases, external
EPROM memory with faster access time must be used.
Table 7-2 lists external memory speed requirements for
a given PIC17C7XX device frequency.
The electrical specifications now include timing specifi-
cations for the memory interface with PIC17LCXXX
devices. These specifications reflect the capability of
the device by characterization. Please validate your
design with these timings.
FIGURE 7-4: TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM
AD15-AD0
(3)
(3)
Memory
(LSB)
Memory
(MSB)
A15-A0
(3)
AD7-AD0
373
373
Ax-A0
Ax-A0
PIC17CXXX
D7-D0
CE
D7-D0
CE
(2)
(2)
OE WR
OE WR
AD15-AD8
ALE
(3)
(1)
138
I/O(1)
OE
WR
Note 1: Use of I/O pins is only required for paged memory.
2: This signal is unused for ROM and EPROM devices.
3: 16-bit wide devices are now common and could be used instead of 8-bit wide devices.
1998 Microchip Technology Inc.
DS30289A-page 43
PIC17C7XX
7.2.1
GENERAL PURPOSE REGISTER (GPR)
7.2
Data Memory Organization
All devices have some amount of GPR area.The GPRs
are 8-bits wide. When the GPR area is greater than
232, it must be banked to allow access to the additional
memory space.
Data memory is partitioned into two areas. The first is
the General Purpose Registers (GPR) area, and the
second is the Special Function Registers (SFR) area.
The SFRs control and provide status of device opera-
tion.
All the PIC17C7XX devices have banked memory in
the GPR area. To facilitate switching between these
banks, the MOVLR bankinstruction has been added to
the instruction set. GPRs are not initialized by a
Power-on Reset and are unchanged on all other resets.
Portions of data memory are banked, this occurs in
both areas. The GPR area is banked to allow greater
than 232 bytes of general purpose RAM.
Banking requires the use of control bits for bank selec-
tion. These control bits are located in the Bank Select
Register (BSR). If an access is made to the unbanked
region, the BSR bits are ignored. Figure 7-5 shows the
data memory map organization.
7.2.2
SPECIAL FUNCTION REGISTERS (SFR)
The SFRs are used by the CPU and peripheral func-
tions to control the operation of the device (Figure 7-5).
These registers are static RAM.
Instructions MOVPF and MOVFP provide the means to
move values from the peripheral area (“P”) to any loca-
tion in the register file (“F”), and vice-versa. The defini-
tion of the “P” range is from 0h to 1Fh, while the “F”
range is 0h to FFh. The “P” range has six more loca-
tions than peripheral registers which can be used as
General Purpose Registers. This can be useful in
some applications where variables need to be copied
to other locations in the general purpose RAM (such as
saving status information during an interrupt).
The SFRs can be classified into two sets, those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described here, while those related to a
peripheral feature are described in the section for each
peripheral feature.
The peripheral registers are in the banked portion of
memory, while the core registers are in the unbanked
region. To facilitate switching between the peripheral
banks, the MOVLB bankinstruction has been provided.
The entire data memory can be accessed either
directly or indirectly (through file select registers FSR0
and FSR1) (Section 7.4). Indirect addressing uses the
appropriate control bits of the BSR for accesses into
the banked areas of data memory. The BSR is
explained in greater detail in Section 7.8.
DS30289A-page 44
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 7-5: PIC17C7XX REGISTER FILE MAP
Addr Unbanked
INDF0
FSR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1, 4)
Bank 0
PORTA
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
SSPADD
SSPCON1 PW3DCH
Bank 7
Bank 8
DDRH
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
PIR1
TMR1
TMR2
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
PIR2
PIE2
—
DDRF
PORTF
DDRG
PW3DCL
10h
11h
12h
13h
14h
15h
16h
17h
DDRB
PORTH
DDRJ
PORTJ
—
PORTB
TMR3L
TMR3H
PR1
SSPCON2
CA3L
CA3H
CA4L
CA4H
TCON3
—
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
Unbanked
PRODL
PRODH
RCSTA2
PORTG
SSPSTAT
RCREG2 ADCON0
SSPBUF
—
—
—
—
PR2
CA2H
TXSTA2
TXREG2
SPBRG2
ADCON1
ADRESL
ADRESH
—
PR3L/CA1L
PR3H/CA1H
TCON1
TCON2
—
PIE1
18h
19h
1Ah
General
Purpose
RAM
1Fh
20h
(2)
(2)
(2, 3)
(2, 3)
Bank 0
Bank 1
Bank 2
Bank 3
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked.The lower nibble of the BSR specifies the bank. All unbanked SFRs
ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh are
banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register
(BSR) bits.
3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented regis-
ter reads ‘0’s.
4: Bank 8 is only implemented on the PIC17C76X devices.
1998 Microchip Technology Inc.
DS30289A-page 45
PIC17C7XX
TABLE 7-3:
SPECIAL FUNCTION REGISTERS
Value on
POR,
BOR
MCLR,
WDT
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unbanked
00h
01h
02h
INDF0
FSR0
Uses contents of FSR0 to address data memory (not a physical register)
Indirect data memory address pointer 0
Low order 8-bits of PC
---- ---- ---- ----
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
PCL
03h(1)
04h
PCLATH
ALUSTA
T0STA
Holding register for upper 8-bits of PC
FS3
FS2
FS1
FS0
OV
Z
DC
C
1111 xxxx 1111 uuuu
0000 000- 0000 000-
05h
INTEDG
T0SE
T0CS
T0PS3
T0PS2
T0PS1
T0PS0
—
06h(2)
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
—
—
STKAV
T0IF
GLINTD
INTF
TO
PD
POR
T0IE
BOR
INTE
--11 11qq --11 qquu
CPUSTA
INTSTA
INDF1
PEIF
T0CKIF
PEIE
T0CKIE
0000 0000 0000 0000
---- ---- ---- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Uses contents of FSR1 to address data memory (not a physical register)
Indirect data memory address pointer 1
Working register
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
TMR0 register; low byte
TMR0 register; high byte
Low byte of program memory table pointer
High byte of program memory table pointer
Bank select register
Bank 0
RA5/TX1/ RA4/RX1/ RA3/SDI/ RA2/SS/
PORTA (4,6)
DDRB
10h
11h
12h
RBPU
—
RA1/T0CKI RA0/INT 0-xx 11xx 0-uu 11uu
CK1
Data direction register for PORTB
DT1
SDA
SCL
1111 1111 1111 1111
RB7/
SDO
RB6/
SCK
RB5/
RB4/
RB3/
RB2/
RB1/
CAP2
RB0/
CAP1
PORTB (4)
xxxx xxxx uuuu uuuu
TCLK3
TCLK12
PWM2
PWM1
13h
14h
15h
16h
17h
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
SPEN
RX9
SREN
CREN
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x 0000 -00u
xxxx xxxx uuuu uuuu
0000 --1x 0000 --1u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
Serial port receive register
CSRC TX9 TXEN
SYNC
Serial Port Transmit Register (for USART1)
Baud Rate Generator Register (for USART1)
Bank 1
DDRC (5)
1111 1111 1111 1111
10h
Data direction register for PORTC
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
PORTC (4, 5)
DDRD (5)
11h
12h
13h
14h
15h
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
Data direction register for PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
PORTD (4, 5)
DDRE (5)
xxxx xxxx uuuu uuuu
---- 1111 ---- 1111
Data direction register for PORTE
RE3/
CAP4
PORTE (4, 5)
—
—
—
—
RE2/WR
RE1/OE
RE0/ALE ---- xxxx ---- uuuu
16h
17h
PIR1
PIE1
RBIF
RBIE
TMR3IF
TMR2IF
TMR1IF
TMR1IE
CA2IF
CA2IE
CA1IF
CA1IE
TX1IF
TX1IE
RC1IF
RC1IE
x000 0010 u000 0010
0000 0000 0000 0000
TMR3IE TMR2IE
Legend: x = unknown, u = unchanged,- = unimplemented read as '0',q - value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8>
whose contents are updated from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or extended microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device reset, these pins are configured as inputs.
DS30289A-page 46
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 7-3:
SPECIAL FUNCTION REGISTERS (Cont.’d)
Value on
MCLR,
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
WDT
Bank 2
10h
11h
12h
13h
14h
15h
16h
17h
TMR1
Timer1’s register
Timer2’s register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR2
TMR3L
TMR3H
PR1
Timer3’s register; low byte
Timer3’s register; high byte
Timer1’s period register
Timer2’s period register
PR2
PR3L/CA1L
Timer3’s period register - low byte/capture1 register; low byte
PR3H/CA1H Timer3’s period register - high byte/capture1 register; high byte
Bank 3
10h
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
DC1
DC1
DC9
DC9
DC0
DC0
DC8
DC8
—
TM2PW2
DC7
—
—
—
—
—
—
—
—
—
—
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
11h
12h
DC6
DC6
DC5
DC5
DC4
DC4
DC3
DC3
DC2
DC2
13h
DC7
14h
Capture2 low byte
Capture2 high byte
15h
CA2H
16h
TCON1
CA2ED1 CA2ED0 CA1ED1
CA1ED0
T16
TMR3CS
TMR2CS TMR1CS 0000 0000 0000 0000
17h
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Bank 4:
10h
PIR2
PIE2
SSPIF
SSPIE
—
BCLIF
BCLIE
—
ADIF
ADIE
—
—
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
—
TX2IF
TX2IE
—
RC2IF
RC2IE
—
000- 0010 000- 0010
000- 0000 000- 0000
---- ---- ---- ----
11h
12h
Unimple-
mented
13h
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
SPEN
RX9
SREN
CREN
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x 0000 -00u
xxxx xxxx uuuu uuuu
0000 --1x 0000 --1u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
14h
Serial Port Receive Register for USART2
CSRC TX9 TXEN SYNC
15h
16h
Serial Port Transmit Register for USART2
Baud Rate Generator for USART2
17h
Bank 5:
10h
DDRF
Data Direction Register for PORTF
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
xxxx 0000 uuuu 0000
0000 -0-0 0000 -0-0
11h
PORTF (4)
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
12h
13h
DDRG
Data Direction Register for PORTG
PORTG (4)
RG7/
RG6/
RG5/
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
TX2/CK2 RX2/DT2
PWM3
14h
15h
16h
17h
ADCON0
ADCON1
ADRESL
ADRESH
CHS3
CHS2
CHS1
ADFM
CHS0
—
—
GO/DONE
PCFG2
—
ADON
ADCS1
ADCS0
PCFG3
PCFG1
PCFG0 000- 0000 000- 0000
xxxx xxxx uuuu uuuu
A/D Result Register low byte
A/D Result Register high byte
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged,- = unimplemented read as '0',q - value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8>
whose contents are updated from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or extended microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device reset, these pins are configured as inputs.
1998 Microchip Technology Inc.
DS30289A-page 47
PIC17C7XX
TABLE 7-3:
SPECIAL FUNCTION REGISTERS (Cont.’d)
Value on
POR,
BOR
MCLR,
WDT
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 6:
10h
11h
12h
13h
14h
15h
SSPADD
SSPCON1
SSPCON2
SSPSTAT
SSPBUF
SSP Address register in I2C slave mode. SSP baud rate reload register in I2C master mode.
0000 0000 0000 0000
WCOL
GCEN
SMP
SSPOV
AKSTAT
CKE
SSPEN
AKDT
D/A
CKP
AKEN
P
SSPM3
RCEN
S
SSPM2
PEN
SSPM1
RSEN
UA
SSPM0 0000 0000 0000 0000
SEN
BF
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
---- ---- ---- ----
R/W
Synchronous Serial Port Receive Buffer/Transmit Register
Unimple-
mented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16h
17h
Unimple-
mented
---- ---- ---- ----
---- ---- ---- ----
Unimple-
mented
Bank 7:
10h
PW3DCL
PW3DCH
CA3L
DC1
DC9
DC0
DC8
TM2PW3
DC7
-
-
-
-
-
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
11h
DC6
DC5
DC4
DC3
DC2
12h
Capture3 low byte
Capture3 high byte
Capture4 low byte
Capture4 high byte
13h
CA3H
14h
CA4L
15h
CA4H
16h
TCON3
—
—
CA4OVF CA3OVF
CA4ED1 CA4ED0 CA3ED1
CA3ED0 PWM3ON -000 0000 -000 0000
17h
Unimple-
mented
—
—
—
—
—
—
—
---- ---- ---- ----
Bank 8:(3)
10h(3)
DDRH
Data direction register for PORTH
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
11h(3)
PORTH (4)
RH7/
AN15
RH6/
AN14
RH5/
AN13
RH4/
AN12
RH3
RH2
RH1
RH0
12h(3)
13h(3)
14h(3)
DDRJ
Data direction register for PORTJ
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- ---- ---- ----
PORTJ (4)
RJ7
—
RJ6
—
RJ5
—
RJ4
—
RJ3
—
RJ2
—
RJ1
—
RJ0
—
Unimple-
mented
15h(3)
16h(3)
17h(3)
Unimple-
mented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
---- ---- ---- ----
---- ---- ---- ----
---- ---- ---- ----
Unimple-
mented
Unimple-
mented
Unbanked
18h
PRODL
PRODH
Low Byte of 16-bit Product (8 x 8 Hardware Multiply)
High Byte of 16-bit Product (8 x 8 Hardware Multiply)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
19h
Legend: x = unknown, u = unchanged,- = unimplemented read as '0',q - value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8>
whose contents are updated from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for microprocessor or extended microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device reset, these pins are configured as inputs.
DS30289A-page 48
1998 Microchip Technology Inc.
PIC17C7XX
7.2.2.1
ALU STATUS REGISTER (ALUSTA)
It is recommended, therefore, that only BCF, BSF, SWAPF
and MOVWF instructions be used to alter the ALUSTA
register because these instructions do not affect any
status bits. To see how other instructions affect the sta-
tus bits, see the “Instruction Set Summary.”
The ALUSTA register contains the status bits of the
Arithmetic and Logic Unit and the mode control bits for
the indirect addressing register.
As with all the other registers, the ALUSTA register can
be the destination for any instruction. If the ALUSTA
register is the destination for an instruction that affects
the Z, DC, C, or OV bits, then the write to these three
bits is disabled. These bits are set or cleared according
to the device logic. Therefore, the result of an instruc-
tion with the ALUSTA register as destination may be
different than intended.
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
Note 2: The overflow bit will be set if the 2’s com-
plement result exceeds +127 or is less
than -128.
The Arithmetic and Logic Unit (ALU) is capable of car-
rying out arithmetic or logical operations on two oper-
For example, the CLRF ALUSTA, Finstruction will clear
the upper four bits and set the Z bit. This leaves the
ALUSTA register as 0000u1uu(where u= unchanged).
ands or
a single operand. All single operand
instructions operate either on the WREG register or the
given file register. For two operand instructions, one of
the operands is the WREG register and the other is
either a file register or an 8-bit immediate constant.
FIGURE 7-6: ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)
R/W - 1 R/W - 1 R/W - 1 R/W - 1 R/W - x R/W - x R/W - x R/W - x
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
FS3
FS2
FS1
FS0
OV
Z
DC
C
bit7
bit0
bit 7-6: FS3:FS2: FSR1 Mode Select bits
00 = Post auto-decrement FSR1 value
01 = Post auto-increment FSR1 value
1x = FSR1 value does not change
bit 5-4: FS1:FS0: FSR0 Mode Select bits
00 = Post auto-decrement FSR0 value
01 = Post auto-increment FSR0 value
1x = FSR0 value does not change
bit 3:
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic, (in this arithmetic operation)
0 = No overflow occurred
bit 2:
bit 1:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The results of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWFand ADDLWinstructions.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow the polarity is reversed.
bit 0:
C: carry/borrow bit
For ADDWFand ADDLWinstructions. Note that a subtraction is executed by adding the two’s complement
of the second operand.
For rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the source
register.
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result
Note: For borrow the polarity is reversed.
1998 Microchip Technology Inc.
DS30289A-page 49
PIC17C7XX
7.2.2.2
CPU STATUS REGISTER (CPUSTA)
The POR bit allows the differentiation between a
Power-on Reset, external MCLR reset, or a WDT
Reset. The BOR bit indicates if a Brown-out Reset
occurred.
The CPUSTA register contains the status and control
bits for the CPU. This register has a bit that is used to
globally enable/disable interrupts. If only a specific
interrupt is desired to be enabled/disabled, please refer
to the INTerrupt STAtus (INTSTA) register and the
Peripheral Interrupt Enable (PIE) registers. The
CPUSTA register also indicates if the stack is available
and contains the Power-down (PD) and Time-out (TO)
bits. The TO, PD, and STKAV bits are not writable.
These bits are set and cleared according to device
logic. Therefore, the result of an instruction with the
CPUSTA register as destination may be different than
intended.
Note 1: The BOR status bit is a don’t care and is
not necessarily predictable if the
brown-out circuit is disabled (when the
BODEN bit in the Configuration word is
programmed).
FIGURE 7-7: CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U - 0
—
U - 0
—
R - 1
STKAV GLINTD
R/W - 1
R - 1
TO
R - 1
PD
R/W - 0 R/W - 1
POR BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5:
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh → 0h (stack overflow).
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a
stack overflow, only a device reset will set this bit)
bit 4:
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
bit 3:
bit 2:
bit 1:
bit 0:
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDTinstruction
0 = A Watchdog Timer time-out occurred
PD: Power-down Status bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set by software)
BOR: Brown-out Reset Status bit
When BODEN configuration bit is set (enabled):
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set by software)
When BODEN configuration bit is clear (disabled):
Don’t care
DS30289A-page 50
1998 Microchip Technology Inc.
PIC17C7XX
7.2.2.3
TMR0 STATUS/CONTROL REGISTER
(T0STA)
This register contains various control bits. Bit7
(INTEDG) is used to control the edge upon which a sig-
nal on the RA0/INT pin will set the RA0/INT interrupt
flag. The other bits configure Timer0, it’s prescaler and
clock source.
FIGURE 7-8: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
U - 0
—
R = Readable bit
W = Writable bit
U = Unimplemented,
reads as ‘0’
INTEDG
T0SE
T0CS
T0PS3
T0PS2
T0PS1
T0PS0
bit7
bit0
-n = Value at POR reset
bit 7:
bit 6:
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
T0SE: Timer0 External Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0 (External Clock)
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or sets a T0CKIF bit
When T0CS = 1 (Internal Clock)
Don’t care
bit 5:
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for Timer0.
1 = Internal instruction clock cycle (TCY)
0 = External clock input on the T0CKI pin
bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for Timer0.
T0PS3:T0PS0
Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
bit 0:
Unimplemented: Read as '0'
1998 Microchip Technology Inc.
DS30289A-page 51
PIC17C7XX
7.3
Stack Operation
Note 1: There is not a status bit for stack under-
flow.The STKAV bit can be used to detect
the underflow which results in the stack
pointer being at the top of stack.
PIC17C7XX devices have a 16 x 16-bit hardware stack
(Figure 7-1). The stack is not part of either the program
or data memory space, and the stack pointer is neither
readable nor writable. The PC (Program Counter) is
“PUSHed” onto the stack when a CALL or LCALL
instruction is executed or an interrupt is acknowledged.
The stack is “POPed” in the event of a RETURN, RETLW,
or a RETFIE instruction execution. PCLATH is not
affected by a “PUSH” or a “POP” operation.
Note 2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
tions, or the vectoring to an interrupt vec-
tor.
The stack operates as a circular buffer, with the stack
pointer initialized to '0' after all resets. There is a stack
available bit (STKAV) to allow software to ensure that
the stack will not overflow. The STKAV bit is set after a
device reset.When the stack pointer equals Fh, STKAV
is cleared. When the stack pointer rolls over from Fh to
0h, the STKAV bit will be held clear until a device reset.
Note 3: After a reset, if a “POP” operation occurs
before a “PUSH” operation, the STKAV bit
will be cleared. This will appear as if the
stack is full (underflow has occurred). If a
“PUSH” operation occurs next (before
another “POP”), the STKAV bit will be
locked clear. Only a device reset will
cause this bit to set.
After the device is “PUSHed” sixteen times (without a
“POP”), the seventeenth push overwrites the value
from the first push. The eighteenth push overwrites the
second push (and so on).
DS30289A-page 52
1998 Microchip Technology Inc.
PIC17C7XX
7.4.2
INDIRECT ADDRESSING OPERATION
7.4
Indirect Addressing
The indirect addressing capability has been enhanced
over that of the PIC16CXX family. There are two con-
trol bits associated with each FSR register. These two
bits configure the FSR register to:
Indirect addressing is a mode of addressing data
memory where the data memory address in the
instruction is not fixed. That is, the register that is to
be read or written can be modified by the program.
This can be useful for data tables in the data memory.
Figure 7-9 shows the operation of indirect addressing.
This depicts the moving of the value to the data mem-
ory address specified by the value of the FSR register.
• Auto-decrement the value (address) in the FSR
after an indirect access
• Auto-increment the value (address) in the FSR
after an indirect access
• No change to the value (address) in the FSR after
an indirect access
Example 7-1 shows the use of indirect addressing to
clear RAM in a minimum number of instructions. A
similar concept could be used to move a defined num-
ber of bytes (block) of data to the USART transmit reg-
ister (TXREG). The starting address of the block of
data to be transmitted could easily be modified by the
program.
These control bits are located in the ALUSTA register.
The FSR1 register is controlled by the FS3:FS2 bits
and FSR0 is controlled by the FS1:FS0 bits.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
ALUSTA register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
FIGURE 7-9: INDIRECT ADDRESSING
If the FSR register contains a value of 0h, an indirect
read will read 0h (Zero bit is set) while an indirect write
will be equivalent to a NOP (status bits are not
affected).
RAM
Instruction
Executed
Indirect addressing allows single cycle data transfers
within the entire data space. This is possible with the
use of the MOVPFand MOVFPinstructions, where either
'p' or 'f' is specified as INDF0 (or INDF1).
Opcode
Address
8
If the source or destination of the indirect address is in
banked memory, the location accessed will be deter-
mined by the value in the BSR.
File = INDFx
8
8
Instruction
Fetched
A simple program to clear RAM from 20h - FFh is
shown in Example 7-1.
FSR
Opcode
File
EXAMPLE 7-1: INDIRECT ADDRESSING
7.4.1
INDIRECT ADDRESSING REGISTERS
MOVLW 0x20
MOVWF FSR0
;
; FSR0 = 20h
The PIC17C7XX has four registers for indirect
addressing. These registers are:
BCF
BSF
BCF
ALUSTA, FS1 ; Increment FSR
ALUSTA, FS0 ; after access
ALUSTA, C
• INDF0 and FSR0
• INDF1 and FSR1
; C = 0
;
MOVLW END_RAM + 1
LP CLRF INDF0, F
CPFSEQ FSR0
; Addr(FSR) = 0
; FSR0 = END_RAM+1?
; NO, clear next
; YES, All RAM is
; cleared
Registers INDF0 and INDF1 are not physically imple-
mented. Reading or writing to these registers acti-
vates indirect addressing, with the value in the
corresponding FSR register being the address of the
data. The FSR is an 8-bit register and allows address-
ing anywhere in the 256-byte data memory address
range. For banked memory, the bank of memory
accessed is specified by the value in the BSR.
GOTO
LP
:
:
If file INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if
INDF0 (or INDF1) is written to indirectly, the operation
will be equivalent to a NOP, and the status bits are not
affected.
1998 Microchip Technology Inc.
DS30289A-page 53
PIC17C7XX
7.5
Table Pointer (TBLPTRL and
TBLPTRH)
File registers TBLPTRL and TBLPTRH form a 16-bit
pointer to address the 64K program memory space.
The table pointer is used by instructions TABLWT and
TABLRD.
The TABLRDand the TABLWTinstructions allow transfer
of data between program and data space. The table
pointer serves as the 16-bit address of the data word
within the program memory. For a more complete
description of these registers and the operation ofTable
Reads and Table Writes, see Section 8.0.
7.6
Table Latch (TBLATH,TBLATL)
The table latch (TBLAT) is a 16-bit register, with
TBLATH and TBLATL referring to the high and low
bytes of the register. It is not mapped into data or pro-
gram memory. The table latch is used as a temporary
holding latch during data transfer between program
and data memory (see TABLRD, TABLWT, TLRD and
TLWT instruction descriptions). For a more complete
description of these registers and the operation ofTable
Reads and Table Writes, see Section 8.0.
DS30289A-page 54
1998 Microchip Technology Inc.
PIC17C7XX
Using Figure 7-10, the operations of the PC and
PCLATH for different instructions are as follows:
7.7
Program Counter Module
The Program Counter (PC) is a 16-bit register. PCL, the
low byte of the PC, is mapped in the data memory. PCL
is readable and writable just as is any other register.
PCH is the high byte of the PC and is not directly
addressable. Since PCH is not mapped in data or pro-
gram memory, an 8-bit register PCLATH (PC high
latch) is used as a holding latch for the high byte of the
PC. PCLATH is mapped into data memory. The user
can read or write PCH through PCLATH.
a) LCALLinstructions:
An 8-bit destination address is provided in the
instruction (opcode). PCLATH is unchanged.
PCLATH → PCH
Opcode<7:0> → PCL
b) Read instructions on PCL:
Any instruction that reads PCL.
PCL → data bus → ALU or destination
PCH → PCLATH
The 16-bit wide PC is incremented after each instruc-
tion fetch during Q1 unless:
c) Write instructions on PCL:
Any instruction that writes to PCL.
8-bit data → data bus → PCL
PCLATH → PCH
• Modified by a GOTO, CALL, LCALL, RETURN, RETLW,
or RETFIEinstruction
• Modified by an interrupt response
• Due to destination write to PCL by an instruction
d) Read-Modify-Write instructions on PCL:
“Skips” are equivalent to a forced NOP cycle at the
skipped address.
Any instruction that does a read-write-modify
operation on PCL, such as ADDWF PCL.
Figure 7-10 and Figure 7-11 show the operation of the
program counter for various situations.
Read: PCL → data bus → ALU
Write: 8-bit result → data bus → PCL
PCLATH → PCH
FIGURE 7-10: PROGRAM COUNTER
OPERATION
e) RETURNinstruction:
Stack<MRU> → PC<15:0>
Internal data bus <8>
Using Figure 7-11, the operation of the PC and
PCLATH for GOTOand CALLinstructions is as follows:
8
CALL, GOTOinstructions:
PCLATH
8
A 13-bit destination address is provided in the
instruction (opcode).
8
Opcode<12:0> → PC<12:0>
PC<15:13> → PCLATH<7:5>
Opcode<12:8> → PCLATH<4:0>
PCH
PCL
FIGURE 7-11: PROGRAM COUNTER USING
THE CALLAND GOTO
The read-modify-write only affects the PCL with the
result. PCH is loaded with the value in the PCLATH.
For example, ADDWF PCLwill result in a jump within the
current page. If PC = 03F0h, WREG = 30h and
PCLATH = 03h before instruction, PC = 0320h after the
instruction. To accomplish a true 16-bit computed
jump, the user needs to compute the 16-bit destination
address, write the high byte to PCLATH and then write
the low value to PCL.
INSTRUCTIONS
15
13 12
8 7
0
From Instruction
5
PC<15:13>
3
8
The following PC related operations do not change
PCLATH:
4
5
7
0
PCLATH
a) LCALL, RETLW, and RETFIEinstructions.
8
b) Interrupt vector is forced onto the PC.
15
0
8 7
c) Read-modify-write instructions on PCL
PCL
PCH
(e.g. BSF PCL).
1998 Microchip Technology Inc.
DS30289A-page 55
PIC17C7XX
The need for a large general purpose memory space
dictated a general purpose RAM banking scheme. The
upper nibble of the BSR selects the currently active
general purpose RAM bank. To assist this, a MOVLR
bank instruction has been provided in the instruction
set.
7.8
Bank Select Register (BSR)
The BSR is used to switch between banks in the data
memory area (Figure 7-12). In the PIC17C7XX
devices, the entire byte is implemented. The lower nib-
ble is used to select the peripheral register bank. The
upper nibble is used to select the general purpose
memory bank.
If the currently selected bank is not implemented (such
as Bank 13), any read will read all '0's. Any write is
completed to the bit bucket and the ALU status bits will
be set/cleared as appropriate.
All the Special Function Registers (SFRs) are mapped
into the data memory space. In order to accommodate
the large number of registers, a banking scheme has
been used. A segment of the SFRs, from address 10h
to address 17h, is banked.The lower nibble of the bank
select register (BSR) selects the currently active
“peripheral bank.” Effort has been made to group the
peripheral registers of related functionality in one bank.
However, it will still be necessary to switch from bank to
bank in order to address all peripherals related to a sin-
gle task. To assist this, a MOVLB bankinstruction has
been included in the instruction set.
Note: Registers in Bank 15 in the Special Func-
tion Register area, are reserved for
Microchip use. Reading of registers in this
bank may cause random values to be read.
FIGURE 7-12: BSR OPERATION
BSR
7
4
3
0
(2)
(1)
Address
Range
4
5
6
7
0
1
2
3
8
15
(Peripheral)
Banks
SFR
10h
17h
• • •
Bank 4 Bank 5 Bank 6 Bank 7
Bank 0 Bank 1 Bank 2 Bank 3
Bank 8 Bank 15
15
0
1
2
3
4
(RAM)
GPR
Banks
20h
FFh
• • •
Bank 0 Bank 1 Bank 2
Bank 15
Bank 3
Bank 4
Note 1: For the SFRs only Banks 0 through 8 are implemented. Selection of an unimplemented bank is not recom-
mended. Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random
values to be read.
2: For the GPRs, bank 3 is unimplemented on the PIC17C752 and the PIC17C762. Selection of an unimple-
mented bank is not recommended.
3: SFR Bank 8 is only implemented on the PIC17C76X.
DS30289A-page 56
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 8-2: TABLWTINSTRUCTION
OPERATION
8.0
TABLE READS AND TABLE
WRITES
The PIC17C7XX has four instructions that allow the
processor to move data from the data memory space
to the program memory space, and vice versa. Since
the program memory space is 16-bits wide and the
data memory space is 8-bits wide, two operations are
required to move 16-bit values to/from the data mem-
ory.
TABLE POINTER
TBLPTRH
TBLPTRL
TABLATL
TABLE LATCH (16-bit)
TABLATH
The TLWT t,f and TABLWT t,i,f instructions are
used to write data from the data memory space to the
3
3
TABLWT 1,i,f
TABLWT 0,i,f
program memory space. The TLRD
t,f and
TABLRD t,i,f instructions are used to write data
from the program memory space to the data memory
space.
Data
Memory
Program Memory
The program memory can be internal or external. For
the program memory access to be external, the device
needs to be operating in microprocessor or extended
microcontroller mode.
f
1
Figure 8-1 through Figure 8-4 show the operation of
these four instructions. The steps show the sequence
of operation.
Prog-Mem
(TBLPTR)
2
FIGURE 8-1: TLWTINSTRUCTION
OPERATION
TABLE POINTER
TBLPTRH
TBLPTRL
TABLATL
Step 1: 8-bit value, from register 'f', loaded into the
high or low byte in TABLAT (16-bit).
TABLE LATCH (16-bit)
TABLATH
2: 16-bit TABLAT value written to address Pro-
gram Memory (TBLPTR).
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
TLWT 1,f
TLWT 0,f
Program Memory
Data
Memory
f
1
Step 1: 8-bit value, from register 'f', loaded into the
high or low byte in TABLAT (16-bit).
1998 Microchip Technology Inc.
DS30289A-page 57
PIC17C7XX
FIGURE 8-3: TLRDINSTRUCTION
FIGURE 8-4: TABLRDINSTRUCTION
OPERATION
OPERATION
TABLE POINTER
TABLE POINTER
TBLPTRH
TBLPTRL
TABLATL
TBLPTRH
TBLPTRL
TABLE LATCH (16-bit)
TABLATH
TABLE LATCH (16-bit)
TABLATH
TABLATL
TLRD 1,f
TLRD 0,f
3
3
TABLRD 0,i,f
Data
TABLRD 1,i,f
Memory
Program Memory
Data
Memory
Program Memory
f
1
f
1
Prog-Mem
(TBLPTR)
2
Step 1: 8-bit value, from TABLAT (16-bit) high or
low byte, loaded into register 'f'.
Step 1: 8-bit value, from TABLAT (16-bit) high or
low byte, loaded into register 'f'.
2: 16-bit value at Program Memory (TBLPTR)
loaded into TABLAT register.
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
DS30289A-page 58
1998 Microchip Technology Inc.
PIC17C7XX
8.1.1
TERMINATING LONG WRITES
8.1
Table Writes to Internal Memory
An interrupt source or reset are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the inter-
rupt enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execu-
tion is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specifi-
cation #D114). Having only one interrupt enabled to
terminate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write; the interrupt flag, of
the highest priority enabled interrupt, will terminate the
long write and automatically be cleared.
The sequence of events for programming an internal
program memory location should be:
Note 1: If an interrupt is pending, the TABLWTis
aborted (an NOP is executed). The
highest priority pending interrupt, from
the T0CKI, RA0/INT, or TMR0 sources
that is enabled, has its flag cleared.
1. Disable all interrupt sources, except the source
to terminate EPROM program write.
2. Raise MCLR/VPP pin to the programming volt-
age.
Note 2: If the interrupt is not being used for the
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it termi-
nate the long write prematurely.
3. Clear the WDT.
4. Do the table write. The interrupt will terminate
the long write.
5. Verify the memory location (table read).
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
Note 1: Programming requirements must be
met. See timing specification in electrical
specifications for the desired device.
Violating these specifications (including
temperature) may result in EPROM loca-
tions that are not fully programmed and
may lose their state over time.
The GLINTD bit determines whether the program will
branch to the interrupt vector when the long write is
terminated. If GLINTD is clear, the program will vec-
tor, if GLINTD is set, the program will not vector to the
interrupt address.
Note 2: If the VPP requirement is not met, the
table write is a 2 cycle write and the pro-
gram memory is unchanged.
TABLE 8-1:
INTERRUPT - TABLE WRITE INTERACTION
Interrupt
Source
Enable
Bit
Flag
Bit
GLINTD
Action
RA0/INT,
TMR0,
T0CKI
0
1
1
Terminate long table write (to internal program memory),
branch to interrupt vector (branch clears flag bit).
None
0
1
1
1
0
1
0
x
1
None
Terminate long table write, do not branch to interrupt vec-
tor (flag is automatically cleared).
Peripheral
0
0
1
1
1
1
0
1
1
0
x
1
Terminate long table write, branch to interrupt vector.
None
None
Terminate table write, do not branch to interrupt vector
(flag remains set).
1998 Microchip Technology Inc.
DS30289A-page 59
PIC17C7XX
8.2.2
TABLE WRITE CODE
8.2
Table Writes to External Memory
The “i” operand of the TABLWTinstruction can specify
that the value in the 16-bit TBLPTR register is auto-
matically incremented (for the next write). In
Example 8-1, the TBLPTR register is not automatically
incremented.
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
EXAMPLE 8-1: TABLE WRITE
Note: If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or
T0CKI interrupt flag is automatically
cleared or the pending peripheral inter-
rupt is acknowledged.
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
; Clear WDT
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
HIGH (DATA)
1, WREG
;
;
;
address
; Load HI byte
in TABLATH
; Load LO byte
;
MOVLW
LOW (DATA)
TABLWT 0,0,WREG
;
;
;
;
in TABLATL
and write to
program memory
(Ext. SRAM)
FIGURE 8-5: TABLWTWRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
PC+1
TBL
Data out
PC+2
Instruction
fetched
TABLWT
INST (PC+1)
INST (PC+2)
INST (PC+1)
Instruction
executed
INST (PC-1)
TABLWT cycle1
TABLWT cycle2
Data write cycle
ALE
OE
'1'
WR
Note: If external write, and GLINTD = '1', and Enable bit = '1', then when '1' → Flag bit, Do table write.
The highest pending interrupt is cleared.
DS30289A-page 60
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 8-6: CONSECUTIVE TABLWTWRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TBL1
Data out 1
Data out 2
PC
PC+2
PC+3
AD15:AD0
PC+1
TBL2
Instruction
fetched
TABLWT1
TABLWT2
INST (PC+2)
INST (PC+3)
INST (PC+2)
Instruction
executed
TABLWT1 cycle1
TABLWT2 cycle2
Data write cycle
INST (PC-1)
TABLWT1 cycle2 TABLWT2 cycle1
Data write cycle
ALE
OE
WR
1998 Microchip Technology Inc.
DS30289A-page 61
PIC17C7XX
8.3
Table Reads
EXAMPLE 8-2: TABLE READ
The table read allows the program memory to be read.
This allows constants to be stored in the program
memory space, and retrieved into data memory when
needed. Example 8-2 reads the 16-bit value at pro-
gram memory address TBLPTR. After the dummy
byte has been read from the TABLATH, the TABLATH
is loaded with the 16-bit data from program memory
address TBLPTR, and then increments the TBLPTR
value. The first read loads the data into the latch, and
can be considered a dummy read (unknown data
loaded into 'f'). INDF0 should be configured for either
auto-increment or auto-decrement.
MOVLW
MOVWF
MOVLW
MOVWF
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
;
;
;
address
TABLRD 0, 1, DUMMY ; Dummy read,
;
;
Updates TABLATH
Increments TBLPTR
TLRD
1, INDF0
; Read HI byte
of TABLATH
TABLRD 0, 1, INDF0 ; Read LO byte
;
;
;
;
of TABLATL and
Update TABLATH
Increment TBLPTR
FIGURE 8-7: TABLRDTIMING
Q4
Q4
Q4
Q1 Q2
Q3
Q4
Q1 Q2
Q1 Q2
Q1 Q2
Q3
Q3
Q3
AD15:AD0
PC
PC+1
TBL
Data in
PC+2
Instruction
fetched
INST (PC+2)
INST (PC+1)
TABLRD
INST (PC+1)
Instruction
executed
INST (PC-1)
TABLRD cycle2
Data read cycle
TABLRD cycle1
ALE
OE
'1'
WR
FIGURE 8-8: TABLRDTIMING (CONSECUTIVE TABLRDINSTRUCTIONS)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Data in 1
PC
TBL1
PC+2
TBL2 Data in 2
AD15:AD0
PC+1
PC+3
Instruction
fetched
TABLRD1
INST (PC+2)
INST (PC+3)
INST (PC+2)
TABLRD2
Instruction
executed
INST (PC-1) TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1
Data read cycle
TABLRD2 cycle2
Data read cycle
ALE
OE
'1'
WR
DS30289A-page 62
1998 Microchip Technology Inc.
PIC17C7XX
8.4
Operation with External Memory
Interface
When the table reads/writes are accessing external
memory (via the external system interface bus), the
table latch for the table reads is different from the table
latch for the table writes (see Figure 8-9).
This means that you cannot do a TABLRD instruction,
and use the values that were loaded into the table
latches for
a TABLWT instruction. Any table write
sequence should use both the TLWT and then the
TABLWTinstructions.
FIGURE 8-9: ACCESSING EXTERNAL MEMORY WITH TABLRDAND TABLWTINSTRUCTIONS
TABLPTR
Program Memory
(In External Memory Space)
TABLATH (for Table Reads)
TABLRD
TABLATH (for Table Writes)
TABLWT
1998 Microchip Technology Inc.
DS30289A-page 63
PIC17C7XX
NOTES:
DS30289A-page 64
1998 Microchip Technology Inc.
PIC17C7XX
Example 9-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
9.0
HARDWARE MULTIPLIER
All PIC17C7XX devices have an 8 x 8 hardware multi-
plier included in the ALU of the device. By making the
multiply a hardware operation, it completes in a single
instruction cycle. This is an unsigned multiply that
gives a 16-bit result. The result is stored into the 16-bit
PRODuct register (PRODH:PRODL). The multiplier
does not affect any flags in the ALUSTA register.
EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY
ROUTINE
MOVFP
MULWF
ARG1, WREG
ARG2
;
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
; ARG1 * ARG2 ->
;
PRODH:PRODL
• Higher computational throughput
• Reduces code size requirements for multiply algo-
rithms
EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
MOVFP
MULWF
ARG1, WREG
ARG2
; ARG1 * ARG2 ->
PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
Table 9-1 shows a performance comparison between
PIC17CXXX devices using the single cycle hardware
multiply, and performing the same function without the
hardware multiply.
;
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVFP
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH, F
Example 9-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
TABLE 9-1:
PERFORMANCE COMPARISON
Program
Time
@ 33 MHz @ 16 MHz @ 8 MHz
Cycles
(Max)
Routine
8 x 8 unsigned
8 x 8 signed
Multiply Method
Memory
(Words)
Without hardware multiply
Hardware multiply
13
1
69
1
8.364 µs
0.121 µs
—
17.25 µs
0.25 µs
—
34.50 µs
0.50 µs
—
Without hardware multiply
Hardware multiply
—
6
—
6
0.727 µs
29.333 µs
2.91 µs
30.788 µs
4.36 µs
1.50 µs
60.50 µs
6.0 µs
3.0 µs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
121.0 µs
12.0 µs
127.0 µs
18.0 µs
Without hardware multiply
Hardware multiply
63.50 µs
9.0 µs
1998 Microchip Technology Inc.
DS30289A-page 65
PIC17C7XX
Example 9-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 9-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EXAMPLE 9-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFP
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
PRODH:PRODL
;
EQUATION 9-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
MOVPF
MOVPF
PRODH, RES1 ;
PRODL, RES0 ;
;
;
MOVFP
MULWF
ARG1H, WREG
ARG2H
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
; ARG1H * ARG2H ->
PRODH:PRODL
16
;
(ARG1H • ARG2H • 2
)
+
+
+
MOVPF
MOVPF
PRODH, RES3 ;
PRODL, RES2 ;
8
(ARG1H • ARG2L • 2 )
8
(ARG1L • ARG2H • 2 )
MOVFP
MULWF
ARG1L, WREG
ARG2H
(ARG1L • ARG2L)
; ARG1L * ARG2H ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
;
MOVFP
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
DS30289A-page 66
1998 Microchip Technology Inc.
PIC17C7XX
Example 9-4 shows the sequence to do an 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 9-4: 16 x 16 SIGNED MULTIPLY
ROUTINE
MOVFP
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
PRODH:PRODL
;
MOVPF
MOVPF
PRODH, RES1 ;
PRODL, RES0 ;
EQUATION 9-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
MOVFP
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
PRODH:PRODL
;
RES3:RES0
MOVPF
MOVPF
PRODH, RES3 ;
PRODL, RES2 ;
= ARG1H:ARG1L • ARG2H:ARG2L
16
= (ARG1H • ARG2H • 2
)
+
+
+
+
+
MOVFP
MULWF
ARG1L, WREG
ARG2H
8
; ARG1L * ARG2H ->
(ARG1H • ARG2L • 2 )
;
PRODH:PRODL
8
(ARG1L • ARG2H • 2 )
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
(ARG1L • ARG2L)
PRODH, WREG ;
products
16
16
(-1 • ARG2H<7> • ARG1H:ARG1L • 2
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
)
)
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
;
MOVFP
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
;
;
BTFSS
GOTO
MOVFP
SUBWF
MOVFP
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG ;
RES2
ARG1H, WREG ;
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
SIGN_ARG1
BTFSS
GOTO
ARG1H, 7
CONT_CODE
; ARG1H:ARG1L neg?
; no, done
MOVFP
SUBWF
MOVFP
SUBWFB
;
ARG2L, WREG ;
RES2
ARG2H, WREG ;
RES3
;
CONT_CODE
:
1998 Microchip Technology Inc.
DS30289A-page 67
PIC17C7XX
NOTES:
DS30289A-page 68
1998 Microchip Technology Inc.
PIC17C7XX
When some of these peripheral modules are turned on,
the port pin will automatically configure to the alternate
function. The modules that do this are:
10.0 I/O PORTS
PIC17C75X devices have seven I/O ports, PORTA
through PORTG. PIC17C76X devices have nine I/O
ports, PORTA through PORTJ. PORTB through PORTJ
have a corresponding Data Direction Register (DDR),
which is used to configure the port pins as inputs or out-
puts. Some of these ports pins are multiplexed with
alternate functions.
• PWM module
• SSP module
• USART/SCI module
When a pin is automatically configured as an output by
a peripheral module, the pins data direction (DDR) bit
is unknown. After disabling the peripheral module, the
user should re-initialize the DDR bit to the desired con-
figuration.
PORTC, PORTD, and PORTE are multiplexed with the
system bus. These pins are configured as the system
bus when the device’s configuration bits are selected to
Microprocessor or Extended Microcontroller modes. In
the two other microcontroller modes, these pins are
general purpose I/O.
The other peripheral modules (which require an input)
must have their data direction bits configured appropri-
ately.
PORTA, PORTB, PORTE<3>, PORTF, PORTG and the
upper four bits of PORTH are multiplexed with the
peripheral features of the device. These peripheral fea-
tures are:
Note: A pin that is a peripheral input, can be con-
figured as an output (DDRx<y> is cleared).
The peripheral events will be determined
by the action output on the port pin.
• Timer modules
• Capture modules
• PWM modules
• USART/SCI modules
• SSP Module
When the device enters the "reset state" the Data
Direction registers (DDR) are forced set which will
make the I/O hi-impendance inputs. The reset state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
• A/D Module
• External Interrupt pin
1998 Microchip Technology Inc.
DS30289A-page 69
PIC17C7XX
10.1
PORTA Register
FIGURE 10-1: RA0 AND RA1 BLOCK
DIAGRAM
PORTA is a 6-bit wide latch. PORTA does not have a
corresponding Data Direction Register (DDR). Upon a
device reset, the PORTA pins are forced to be high
impedance inputs. For the RA4 and RA5 pins the
peripheral module controls the output. When a device
reset occurs, the peripheral module is disabled, so
these pins are force to be high impedance inputs.
DATA BUS
Reading PORTA reads the status of the pins.
The RA0 pin is multiplexed with the external interrupt,
INT. The RA1 pin is multiplexed with TMR0 clock input,
RA2 and RA3 are multiplexed with the SSP functions,
and RA4 and RA5 are multiplexed with the USART1
functions. The control of RA2, RA3, RA4 and RA5 as
outputs are automatically configured by their multi-
plexed peripheral module.
RD_PORTA
(Q2)
Note: Input pins have protection diodes to VDD and VSS.
FIGURE 10-2: RA2 BLOCK DIAGRAM
Peripheral data in
10.1.1 USING RA2, RA3 AS OUTPUTS
D
Q
Data Bus
The RA2 and RA3 pins are open drain outputs. To use
the RA2 and/or the RA3 pin(s) as output(s), simply
write to the PORTA register the desired value. A '0' will
cause the pin to drive low, while a '1' will cause the pin
to float (hi-impedance). An external pull-up resistor
should be used to pull the pin high. Writes to the RA2
and RA3 pins will not affect the other PORTA pins.
EN
Note: When using the RA2 or RA3 pin(s) as out-
RD_PORTA
(Q2)
put(s),
read-modify-write
instructions
(such as BCF, BSF, BTG) on PORTA are not
recommended.
Q
D
Such operations read the port pins, do the
desired operation, and then write this value
to the data latch. This may inadvertently
cause the RA2 or RA3 pins to switch from
input to output (or vice-versa).
WR_PORTA
(Q4)
1
0
Q
CK
SCL out
To avoid this possibility use a shadow reg-
ister for PORTA. Do the bit operations on
this shadow register and then move it to
PORTA.
2
I C Mode enable
Note: I/O pin has protection diodes to VSS.
Example 10-1 shows an instruction sequence to initial-
ize PORTA. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
EXAMPLE 10-1: INITIALIZING PORTA
MOVLB
MOVLW 0xF3
0
; Select Bank 0
;
MOVWF PORTA ; Initialize PORTA
;
;
;
;
RA<3:2> are output low
RA<5:4> and RA<1:0>
are inputs
(outputs floating)
DS30289A-page 70
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 10-3: RA3 BLOCK DIAGRAM
FIGURE 10-4: RA4 AND RA5 BLOCK
DIAGRAM
Peripheral data in
Serial port input signal
D
Q
Data Bus
EN
Data Bus
RD_PORTA
(Q2)
RD_PORTA
(Q2)
Q
D
Serial port output signals
WR_PORTA
(Q4)
OE = SPEN,SYNC,TXEN, CREN, SREN for RA4
OE = SPEN (SYNC+SYNC,CSRC) for RA5
Q
CK
SDA out
'1'
Note: I/O pins have protection diodes to VDD and VSS.
SSP Mode
Note: I/O pin has protection diodes to VSS.
TABLE 10-1: PORTA FUNCTIONS
Name
RA0/INT
Bit0 Buffer Type
Function
bit0
bit1
ST
ST
Input or external interrupt input.
RA1/T0CKI
Input or clock input to the TMR0 timer/counter, and/or an external interrupt
input.
2
RA2/SS/SCL
RA3/SDI/SDA
bit2
bit3
ST
ST
Input/Output or slave select input for the SPI or clock input for the I C bus.
Output is open drain type.
2
Input/Output or data input for the SPI or data for the I C bus.
Output is open drain type.
RA4/RX1/DT1
RA5/TX1/CK1
RBPU
bit4
bit5
bit7
ST
ST
—
Input or USART1 Asynchronous Receive or
USART1 Synchronous Data.
Input or USART1 Asynchronous Transmit or
USART1 Synchronous Clock.
Control bit for PORTB weak pull-ups.
Legend: ST = Schmitt Trigger input.
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH PORTA
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA5/
RA4/
RA3/
RA2/
0-xx 11xx 0-uu 11uu
PORTA (1)
10h, Bank 0
RBPU
—
RA1/T0CKI RA0/INT
TX1/CK1 RX1/DT1 SDI/SDA SS/SCL
05h, Unbanked T0STA
INTEDG T0SE
T0CS
SREN
TXEN
T0PS3
CREN
SYNC
T0PS2
—
T0PS1
FERR
—
T0PS0
OERR
TRMT
—
0000 000- 0000 000-
0000 -00x 0000 -00u
0000 --1x 0000 --1u
13h, Bank 0
15h, Bank 0
RCSTA1
TXSTA1
SPEN
CSRC
RX9
TX9
RX9D
TX9D
—
Legend:
Note 1:
x= unknown, u= unchanged, -= unimplemented reads as '0'. Shaded cells are not used by PORTA.
On any device reset, these pins are configured as inputs.
1998 Microchip Technology Inc.
DS30289A-page 71
PIC17C7XX
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt by:
10.2
PORTB and DDRB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRB. A '1' in DDRB
configures the corresponding port pin as an input. A '0'
in the DDRB register configures the corresponding port
pin as an output. Reading PORTB reads the status of
the pins, whereas writing to PORTB will write to the port
latch.
a) Read-Write PORTB (such as; MOVPF PORTB,
PORTB). This will end mismatch condition.
b) Then, clear the RBIF bit.
A mismatch condition will continue to set the RBIF bit.
Reading then writing PORTB will end the mismatch
condition, and allow the RBIF bit to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (PORTA<7>) bit. The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are enabled on
any reset.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on this port, allows easy
interface to a keypad and make it possible for wake-up
on key-depression. For an example, refer to Applica-
tion Note AN552, “Implementing Wake-up on Key-
stroke.”
PORTB also has an interrupt on change feature. Only
pins configured as inputs can cause this interrupt to
occur (i.e. any RB7:RB0 pin configured as an output is
excluded from the interrupt on change comparison).
The input pins (of RB7:RB0) are compared with the
value in the PORTB data latch. The “mismatch” out-
puts of RB7:RB0 are OR’ed together to set the PORTB
Interrupt Flag bit, RBIF (PIR1<7>).
The interrupt on change feature is recommended for
wake-up on operations where PORTB is only used for
the interrupt on change feature and key depression
operations.
Note: On a device reset, the RBIF bit is indeter-
minate since the value in the latch may be
different than the pin.
FIGURE 10-5: BLOCK DIAGRAM OF RB5:RB4 AND RB1:RB0 PORT PINS
Peripheral Data in
RBPU
(PORTA<7>)
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
WR_PORTB (Q4)
CK
D
Port
Q
Data
CK
Note: I/O pins have protection diodes to VDD and VSS.
DS30289A-page 72
1998 Microchip Technology Inc.
PIC17C7XX
Example 10-2 shows an instruction sequence to initial-
ize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
EXAMPLE 10-2: INITIALIZING PORTB
MOVLB
CLRF
0
; Select Bank 0
PORTB, F ; Init PORTB by clearing
output data latches
; Value used to initialize
data direction
; Set RB<3:0> as inputs
;
MOVLW 0xCF
MOVWF DDRB
;
;
;
RB<5:4> as outputs
RB<7:6> as inputs
FIGURE 10-6: BLOCK DIAGRAM OF RB3:RB2 PORT PINS
Peripheral Data in
(PORTA<7>)
RBPU
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
WR_PORTB (Q4)
CK
R
D
Port
Q
Data
CK
Peripheral_output
Peripheral_enable
Note: I/O pins have protection diodes to VDD and Vss.
1998 Microchip Technology Inc.
DS30289A-page 73
PIC17C7XX
FIGURE 10-7: BLOCK DIAGRAM OF RB6 PORT PIN
Peripheral Data in
(PORTA<7>)
RBPU
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
D
Q
Data Bus
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
P
N
0
1
Port
Data
Q
D
WR_PORTB (Q4)
CK
Q
SPI output
SPI output enable
Note: I/O pin has protection diodes to VDD and Vss.
FIGURE 10-8: BLOCK DIAGRAM OF RB7 PORT PIN
Peripheral Data in
(PORTA<7>)
RBPU
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
D
Q
Data Bus
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
D
Q
OE
WR_DDRB (Q4)
SS output disable
CK
P
N
0
1
Port
Data
Q
D
WR_PORTB (Q4)
CK
Q
SPI output
SPI output enable
Note: I/O pin has protection diodes to VDD and Vss.
DS30289A-page 74
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 10-3: PORTB FUNCTIONS
Name
Bit
Buffer Type
Function
RB0/CAP1
bit0
ST
Input/Output or the Capture1 input pin. Software programmable weak
pull-up and interrupt on change features.
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
Input/Output or the Capture2 input pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the PWM1 output pin. Software programmable weak pull-up
and interrupt on change features.
Input/Output or the PWM2 output pin. Software programmable weak pull-up
and interrupt on change features.
Input/Output or the external clock input to Timer1 and Timer2. Software pro-
grammable weak pull-up and interrupt on change features.
Input/Output or the external clock input to Timer3. Software programmable
weak pull-up and interrupt on change features.
Input/Output or the master/slave clock for the SPI. Software programmable
weak pull-up and interrupt on change features.
RB7/SDO
Input/Output or data output for the SPI. Software programmable weak
pull-up and interrupt on change features.
Legend: ST = Schmitt Trigger input.
TABLE 10-4: REGISTERS/BITS ASSOCIATED WITH PORTB
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7/
SDO
RB6/
SCK
RB5/
TCLK3
RB4/
TCLK12
RB3/
PWM2
RB2/
PWM1
RB1/
CAP2
RB0/
CAP1
xxxx xxxx uuuu uuuu
12h, Bank 0
11h, Bank 0
10h, Bank 0
PORTB
DDRB
Data direction register for PORTB
1111 1111 1111 1111
0-xx 11xx 0-uu 11uu
RA5/
RA4/
RA3/
RA2/
PORTA
RBPU
—
RA1/T0CKI RA0/INT
TX1/CK1 RX1/DT1 SDI/SDA SS/SCL
06h, Unbanked CPUSTA
07h, Unbanked INTSTA
—
—
STKAV
T0IF
GLINTD
INTF
TO
PD
POR
T0IE
BOR
INTE
--11 11qq --11 qquu
0000 0000 0000 0000
x000 0010 u000 0010
0000 0000 0000 0000
PEIF
RBIF
RBIE
T0CKIF
TMR3IF
TMR3IE
PEIE
CA2IF
CA2IE
T16
T0CKIE
CA1IF
CA1IE
16h, Bank 1
17h, Bank 1
16h, Bank 3
PIR1
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CA1ED0
TX1IF
TX1IE
RC1IF
RC1IE
PIE1
TCON1
CA2ED1 CA2ED0 CA1ED1
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3
Legend:
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
x= unknown, u= unchanged, - = unimplemented read as '0', q = Value depends on condition.
Shaded cells are not used by PORTB.
1998 Microchip Technology Inc.
DS30289A-page 75
PIC17C7XX
Example 10-3 shows an instruction sequence to initial-
ize PORTC. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.3
PORTC and DDRC Registers
PORTC is an 8-bit bi-directional port. The correspond-
ing data direction register is DDRC. A '1' in DDRC con-
figures the corresponding port pin as an input. A '0' in
the DDRC register configures the corresponding port
pin as an output. Reading PORTC reads the status of
the pins, whereas writing to PORTC will write to the
port latch. PORTC is multiplexed with the system bus.
When operating as the system bus, PORTC is the low
order byte of the address/data bus (AD7:AD0).The tim-
ing for the system bus is shown in the Electrical Speci-
fications section.
EXAMPLE 10-3: INITIALIZING PORTC
MOVLB
CLRF
1
; Select Bank 1
PORTC, F ; Initialize PORTC data
; latches before setting
; the data direction reg
MOVLW
MOVWF
0xCF
DDRC
; Value used to initialize
; data direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
Note: This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a gen-
eral purpose I/O.
FIGURE 10-9: BLOCK DIAGRAM OF RC7:RC0 PORT PINS
to D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTC
WR_PORTC
Port
D
D
0
1
Q
Data
CK
RD_DDRC
WR_DDRC
Q
R
CK
S
EX_EN
DATA/ADDR_OUT
SYS BUS
Control
DRV_SYS
Note: I/O pins have protection diodes to VDD and Vss.
DS30289A-page 76
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 10-5: PORTC FUNCTIONS
Name
Bit
Buffer Type
Function
RC0/AD0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
Legend: TTL = TTL input.
TABLE 10-6: REGISTERS/BITS ASSOCIATED WITH PORTC
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
11h, Bank 1 PORTC
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
10h, Bank 1 DDRC Data direction register for PORTC
Legend: x= unknown, u= unchanged.
1998 Microchip Technology Inc.
DS30289A-page 77
PIC17C7XX
Example 10-4 shows an instruction sequence to initial-
ize PORTD. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.4
PORTD and DDRD Registers
PORTD is an 8-bit bi-directional port. The correspond-
ing data direction register is DDRD. A '1' in DDRD con-
figures the corresponding port pin as an input. A '0' in
the DDRD register configures the corresponding port
pin as an output. Reading PORTD reads the status of
the pins, whereas writing to PORTD will write to the
port latch. PORTD is multiplexed with the system bus.
When operating as the system bus, PORTD is the high
order byte of the address/data bus (AD15:AD8). The
timing for the system bus is shown in the Electrical
Specifications section.
EXAMPLE 10-4: INITIALIZING PORTD
MOVLB
CLRF
1
; Select Bank 1
PORTD, F ; Initialize PORTD data
; latches before setting
; the data direction reg
MOVLW
MOVWF
0xCF
DDRD
; Value used to initialize
; data direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Note: This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a gen-
eral purpose I/O.
FIGURE 10-10: BLOCK DIAGRAM OF RD7:RD0 PORT PINS (IN I/O PORT MODE)
to D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTD
WR_PORTD
Port
D
D
0
1
Q
Data
CK
RD_DDRD
WR_DDRD
Q
R
CK
S
EX_EN
DATA/ADDR_OUT
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30289A-page 78
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 10-7: PORTD FUNCTIONS
Name
Bit
Buffer Type
Function
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Legend: TTL = TTL input.
TABLE 10-8: REGISTERS/BITS ASSOCIATED WITH PORTD
Value on
POR,
BOR
MCLR,
WDT
Address Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD7/
AD15
Data direction register for PORTD
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
13h, Bank 1 PORTD
12h, Bank 1 DDRD
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
Legend: x= unknown, u= unchanged.
1998 Microchip Technology Inc.
DS30289A-page 79
PIC17C7XX
Example 10-5 shows an instruction sequence to initial-
ize PORTE. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.5
PORTE and DDRE Register
PORTE is a 4-bit bi-directional port.The corresponding
data direction register is DDRE. A '1' in DDRE config-
ures the corresponding port pin as an input. A '0' in the
DDRE register configures the corresponding port pin
as an output. Reading PORTE reads the status of the
pins, whereas writing to PORTE will write to the port
latch. PORTE is multiplexed with the system bus.
When operating as the system bus, PORTE contains
the control signals for the address/data bus
(AD15:AD0). These control signals are Address Latch
Enable (ALE), Output Enable (OE), and Write (WR).
The control signals OE and WR are active low signals.
The timing for the system bus is shown in the Electrical
Specifications section.
EXAMPLE 10-5: INITIALIZING PORTE
MOVLB
CLRF
1
; Select Bank 1
PORTE, F ; Initialize PORTE data
; latches before setting
; the data direction
; register
MOVLW
MOVWF
0x03
; Value used to initialize
; data direction
; Set RE<1:0> as inputs
; RE<3:2> as outputs
; RE<7:4> are always
; read as '0'
DDRE
Note: Three pins of this port are configured as
the system bus when the device’s configu-
ration bits are selected to Microprocessor
or Extended Microcontroller modes. The
other pin is a general purpose I/O or
Capture4 pin. In the two other microcon-
troller modes, RE2:RE0 are general pur-
pose I/O pins.
FIGURE 10-11: BLOCK DIAGRAM OF RE2:RE0 (IN I/O PORT MODE)
Data Bus
TTL
Input
Buffer
RD_PORTE
WR_PORTE
Port
D
D
0
1
Q
Data
CK
RD_DDRE
WR_DDRE
Q
R
CK
S
EX_EN
CNTL
SYS BUS
Control
DRV_SYS
Note: I/O pins have protection diodes to VDD and Vss.
DS30289A-page 80
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 10-12: BLOCK DIAGRAM OF RE3/CAP4 PORT PIN
Peripheral In
Data Bus
D
Q
EN
VDD
RD_PORTE
WR_PORTE
P
Q
D
D
Port
Data
CK
Q
N
RD_DDRE
WR_DDRE
Q
CK
S
Q
Note: I/O pin has protection diodes to VDD and Vss.
TABLE 10-9: PORTE FUNCTIONS
Name
Bit
Buffer Type
Function
RE0/ALE
RE1/OE
bit0
bit1
bit2
bit3
TTL
TTL
TTL
ST
Input/Output or system bus Address Latch Enable (ALE) control pin.
Input/Output or system bus Output Enable (OE) control pin.
Input/Output or system bus Write (WR) control pin.
Input/Output or Capture4 input pin
RE2/WR
RE3/CAP4
Legend: TTL = TTL input.
ST = Schmitt Trigger input
TABLE 10-10: REGISTERS/BITS ASSOCIATED WITH PORTE
Value on
POR,
BOR
MCLR,
WDT
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15h, Bank 1 PORTE
14h, Bank 1 DDRE
—
—
—
—
RE3/CAP4 RE2/WR RE1/OE RE0/ALE ---- xxxx
---- uuuu
---- 1111
Data direction register for PORTE
Capture4 low byte
---- 1111
14h, Bank 7 CA4L
15h, Bank 7 CA4H
16h, Bank 7 TCON3
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
-000 0000
Capture4 high byte
—
CA4OVF CA3OVF CA4ED1 CA4ED0
CA3ED1 CA3ED0 PWM3ON -000 0000
Legend:
x= unknown, u= unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
1998 Microchip Technology Inc.
DS30289A-page 81
PIC17C7XX
Example 10-6 shows an instruction sequence to initial-
ize PORTF. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.6
PORTF and DDRF Registers
PORTF is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRF. A '1' in DDRF
configures the corresponding port pin as an input. A '0'
in the DDRF register configures the corresponding port
pin as an output. Reading PORTF reads the status of
the pins, whereas writing to PORTF will write to the
respective port latch.
EXAMPLE 10-6: INITIALIZING PORTF
MOVLB
MOVLW 0x0E
MOVPF ADCON1
5
; Select Bank 5
; Configure PORTF as
; Digital
All eight bits of PORTF are multiplexed with 8 channels
of the 10-bit A/D converter.
CLRF
PORTF, F ; Initialize PORTF data
;
;
;
latches before
the data direction
register
Upon reset the entire Port is automatically configured
as analog inputs, and must be configured in software to
be a digital I/O.
MOVLW
MOVWF
0x03
DDRF
; Value used to init
data direction
; Set RF<1:0> as inputs
;
;
RF<7:2> as outputs
FIGURE 10-13: BLOCK DIAGRAM OF RF7:RF0
Data bus
D
Q
Q
VDD
P
WR PORTF
CK
Data Latch
I/O pin
D
Q
Q
N
WR DDRF
CK
VSS
DDRF Latch
ST
input
buffer
RD DDRF
Q
D
EN
RD PORTF
VAIN
PCFG3:PCFG0
CHS3:CHS0
To other pads
To other pads
Note: I/O pins have protection diodes to VDD and VSS.
DS30289A-page 82
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 10-11: PORTF FUNCTIONS
Name
Bit
Buffer Type
Function
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
ST
ST
ST
ST
ST
ST
ST
ST
bit0
bit1
Input/Output or analog input 4
Input/Output or analog input 5
Input/Output or analog input 6
Input/Output or analog input 7
Input/Output or analog input 8
Input/Output or analog input 9
bit2
bit3
bit4
bit5
bit6
bit7
Input/Output or analog input 10
Input/Output or analog input 11
Legend: ST = Schmitt Trigger input.
TABLE 10-12: REGISTERS/BITS ASSOCIATED WITH PORTF
Value on
MCLR,
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
WDT
10h,
Bank 5
DDRF
Data Direction Register for PORTF
1111 1111 1111 1111
0000 0000 0000 0000
11h,
Bank 5
PORTF
RF7/
RF6/
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
AN11
AN10
15h,
ADCON1 ADCS1 ADCS0 ADFM
—
PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
Bank 5
Legend: x= unknown, u= unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTF.
1998 Microchip Technology Inc.
DS30289A-page 83
PIC17C7XX
Example 10-7 shows the instruction sequence to initial-
ize PORTG. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.7
PORTG and DDRG Registers
PORTG is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRG. A '1' in
DDRG configures the corresponding port pin as an
input. A '0' in the DDRG register configures the corre-
sponding port pin as an output. Reading PORTG
reads the status of the pins, whereas writing to
PORTG will write to the port latch.
EXAMPLE 10-7: INITIALIZING PORTG
MOVLB
MOVLW 0x0E
MOVPF ADCON1
5
; Select Bank 5
; Configure PORTG as
; digital
The lower four bits of PORTG are multiplexed with four
channels of the 10-bit A/D converter.
CLRF
PORTG, F ; Initialize PORTG data
;
;
;
latches before
the data direction
register
The remaining bits of PORTG are multiplexed with
peripheral output and inputs. RG4 is multiplexed with
the CAP3 input, RG5 is multiplexed with the PWM3
output, RG6 and RG7 are multiplexed with the
USART2 functions.
MOVLW
MOVWF
0x03
DDRG
; Value used to init
data direction
; Set RG<1:0> as inputs
;
;
RG<7:2> as outputs
Upon reset RG3:RG0 is automatically configured as
analog inputs, and must be configured in software to
be a digital I/O.
FIGURE 10-14: BLOCK DIAGRAM OF RG3:RG0
Data bus
D
Q
Q
VDD
P
WR PORTG
CK
Data Latch
I/O pin
D
Q
Q
N
WR DDRG
CK
VSS
DDRG Latch
ST
input
buffer
RD DDRG
Q
D
EN
RD PORTG
VAIN
PCFG3:PCFG0
To other pads
To other pads
CHS3:CHS0
Note: I/O pins have protection diodes to VDD and VSS.
DS30289A-page 84
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 10-15: RG4 BLOCK DIAGRAM
Peripheral Data In
Data Bus
Q
D
EN
RD_PORTG
WR_PORTG
D
D
VDD
CK
Q
P
RD_DDRG
WR_DDRG
Q
Q
N
CK
Note: I/O pin has protection diodes to VDD and Vss.
FIGURE 10-16: RG7:RG5 BLOCK DIAGRAM
Peripheral Data In
Data Bus
D
Q
EN
RD_PORTG
WR_PORTG
D
D
Q
Port
VDD
Data
CK
1
0
Q
P
RD_DDRG
WR_DDRG
Q
Q
N
CK
R
OUTPUT
OUTPUT ENABLE
Note: I/O pins have protection diodes to VDD and Vss.
1998 Microchip Technology Inc.
DS30289A-page 85
PIC17C7XX
TABLE 10-13: PORTG FUNCTIONS
Name
Bit
Buffer Type
Function
RG0/AN3
ST
ST
ST
ST
ST
ST
ST
bit0
bit1
Input/Output or analog input 3.
Input/Output or analog input 2.
RG1/AN2
RG2/AN1/VREF-
RG3/AN0/VREF+
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
bit2
bit3
bit4
bit5
bit6
Input/Output or analog input 1 or the ground reference voltage
Input/Output or analog input 0 or the positive reference voltage
Input/Output or the Capture3 input pin.
Input/Output or the PWM3 output pin.
Input/Output or the USART2 (SCI) Asynchronous Receive or USART2
(SCI) Synchronous Data.
RG7/TX2/CK2
bit7
ST
Input/Output or the USART2 (SCI) Asynchronous Transmit or USART2
(SCI) Synchronous Clock.
Legend: ST = Schmitt Trigger input.
TABLE 10-14: REGISTERS/BITS ASSOCIATED WITH PORTG
Value on
POR,
BOR
MCLR,
WDT
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12h, Bank 5
13h, Bank 5
DDRG
Data Direction Register for PORTG
1111 1111
xxxx 0000
1111 1111
uuuu 0000
PORTG
RG7/
RG6/
RG5/
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
TX2/CK2 RX2/DT2
PWM3
15h, Bank 5
ADCON1
ADCS1 ADCS0
ADFM
—
PCFG3
PCFG2
PCFG1 PCFG0
000- 0000
000- 0000
Legend: x= unknown, u= unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTG.
DS30289A-page 86
1998 Microchip Technology Inc.
PIC17C7XX
10.8
PORTH and DDRH Registers
(PIC17C76X only)
EXAMPLE 10-8: INITIALIZING PORTH
MOVLB
MOVLW 0x0E
MOVPF ADCON1
8
; Select Bank 8
; Configure PORTH as
; digital
PORTH is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRH. A '1' in
DDRH configures the corresponding port pin as an
input. A '0' in the DDRH register configures the corre-
sponding port pin as an output. Reading PORTH
reads the status of the pins, whereas writing to
PORTH will write to the respective port latch.
CLRF
PORTH, F ; Initialize PORTH data
;
;
;
latches before
the data direction
register
MOVLW
MOVWF
0x03
DDRH
; Value used to init
data direction
; Set RH<1:0> as inputs
;
The upper four bits of PORTH are multiplexed with
4 channels of the 10-bit A/D converter.
;
RH<7:2> as outputs
The remaining bits of PORTH are general purpose I/O.
Upon reset RH7:RH4 is automatically configured as
analog inputs, and must be configured in software to
be a digital I/O.
Figure 10-17: Block Diagram of RH7:RH4
Data bus
D
Q
VDD
P
WR PORTH
CK
Q
Data Latch
I/O pin
D
Q
Q
N
WR DDRH
CK
VSS
DDRH Latch
ST
input
buffer
RD DDRH
Q
D
EN
RD PORT
PCFG3:PCFG0
To other pads
VAIN
CHS3:CHS0
To other pads
Note: I/O pins have protection diodes to VDD and VSS.
1998 Microchip Technology Inc.
DS30289A-page 87
PIC17C7XX
Figure 10-18:RH3:RH0 Block Diagram
Data Bus
Q
D
EN
RD_PORTH
WR_PORTH
D
D
VDD
CK
Q
P
RD_DDRH
WR_DDRH
Q
Q
N
CK
Note: I/O pins have protection diodes to VDD and Vss.
TABLE 10-1: PORTH FUNCTIONS
Name
Bit
Buffer Type
Function
RH0
ST
ST
ST
ST
ST
ST
ST
ST
bit0
bit1
Input/Output
Input/Output
Input/Output
Input/Output
RH1
RH2
bit2
bit3
bit4
bit5
bit6
bit7
RH3
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
Input/Output or analog input 12
Input/Output or analog input 13
Input/Output or analog input 14
Input/Output or analog input 15
Legend: ST = Schmitt Trigger input.
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH PORTH
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
10h, Bank 8 DDRH
11h, Bank 8 PORTH
Data Direction Register for PORTH
1111 1111 1111 1111
0000 xxxx 0000 uuuu
RH7/
AN15
RH6/
AN14
RH5/
AN13
RH4/
AN12
RH3
RH2
RH1
RH0
15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM
—
PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
Legend: x= unknown, u= unchanged.
DS30289A-page 88
1998 Microchip Technology Inc.
PIC17C7XX
10.9
PORTJ and DDRJ Registers
(PIC17C76X only)
EXAMPLE 10-1: INITIALIZING PORTJ
MOVLB
CLRF
8
; Select Bank 8
PORTJ, F ; Initialize PORTJ data
; latches before setting
; the data direction
; register
PORTJ is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRJ. A '1' in
DDRJ configures the corresponding port pin as an
input. A '0' in the DDRJ register configures the corre-
sponding port pin as an output. Reading PORTJ
reads the status of the pins, whereas writing to PORTJ
will write to the respective port latch.
MOVLW
MOVWF
0xCF
; Value used to initialize
; data direction
; Set RJ<3:0> as inputs
; RJ<5:4> as outputs
; RJ<7:6> as inputs
DDRJ
PORTJ is a general purpose I/O port.
Figure 10-19:PORTJ Block Diagram
Data Bus
Q
D
EN
RD_PORTJ
WR_PORTJ
D
D
VDD
CK
Q
P
RD_DDRJ
WR_DDRJ
Q
Q
N
CK
Note: I/O pins have protection diodes to VDD and Vss.
1998 Microchip Technology Inc.
DS30289A-page 89
PIC17C7XX
TABLE 10-1: PORTJ FUNCTIONS
Name
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
Bit
Buffer Type
Function
ST
ST
ST
ST
ST
ST
ST
ST
bit0
bit1
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
bit2
bit3
bit4
bit5
bit6
bit7
Legend: ST = Schmitt Trigger input.
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH PORTJ
Value on,
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
12h, Bank 8 DDRJ Data Direction Register for PORTJ
13h, Bank 8 PORTJ RJ7 RJ6 RJ5 RJ4 RJ3
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
RJ2
RJ1
RJ0
Legend: x= unknown, u= unchanged.
DS30289A-page 90
1998 Microchip Technology Inc.
PIC17C7XX
10.10 I/O Programming Considerations
EXAMPLE 10-1: READ MODIFY WRITE
INSTRUCTIONS ON AN
I/O PORT
10.10.1 BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. For example, the
BCF and BSF instructions read the register into the
CPU, execute the bit operation, and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g. bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this particu-
lar pin, overwriting the previous content. As long as the
pin stays in the input mode, no problem occurs. How-
ever, if bit0 is switched into output mode later on, the
content of the data latch may now be unknown.
; Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
; PORTB<7:6> have pull-ups and are
; not connected to other circuitry
;
;
;
;
PORT latch PORT pins
---------- ---------
BCF
BCF
PORTB, 7
PORTB, 6
; 01pp pppp
; 10pp pppp
11pp pppp
11pp pppp
BCF
BCF
DDRB, 7
DDRB, 6
; 10pp pppp
; 10pp pppp
11pp pppp
10pp pppp
;
; Note that the user may have expected the
; pin values to be 00pp pppp. The 2nd BCF
; caused RB7 to be latched as the pin value
; (High).
Reading a port reads the values of the port pins. Writ-
ing to the port register writes the value to the port latch.
When using read-modify-write instructions (BCF, BSF,
BTG, etc.) on a port, the value of the port pins is read,
the desired operation is performed with this value, and
the value is then written to the port latch.
Note: A pin actively outputting a Low or High
should not be driven from external devices
in order to change the level on this pin (i.e.
“wired-or”, “wired-and”). The resulting high
output currents may damage the device.
Example 10-1 shows the possible effect of two sequen-
tial read-modify-write instructions on an I/O port.
1998 Microchip Technology Inc.
DS30289A-page 91
PIC17C7XX
10.10.2 SUCCESSIVE OPERATIONS ON I/O PORTS
Figure 10-21 shows the I/O model which causes this
situation. As the effective capacitance (C) becomes
larger, the rise/fall time of the I/O pin increases. As the
device frequency increases or the effective capaci-
tance increases, the possibility of this subsequent
PORTx read-modify-write instruction issue increases.
This effective capacitance includes the effects of the
board traces.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 10-20). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load depen-
dent) before executing the instruction that reads the
values on that I/O port. Otherwise, the previous state
of that pin may be read into the CPU rather than the
“new” state. When in doubt, it is better to separate
these instructions with a NOPor another instruction not
accessing this I/O port.
The best way to address this is to add an series resistor
at the I/O pin. This resistor allows the I/O pin to get to
the desired level before the next instruction.
The use of NOP instructions between the subsequent
PORTx read-modify-write instructions, is a lower cost
solution, but has the issue that the number of NOP
instructions is dependent on the effective capacitance
C and the frequency of the device.
FIGURE 10-20: SUCCESSIVE I/O OPERATION
Note:
Q4
Q4
Q4
Q4
Q3
Q1 Q2
Q3
Q3
Q3
Q1 Q2
Q1 Q2
Q1 Q2
This example shows a write to PORTB
followed by a read from PORTB.
PC + 3
NOP
PC
PC + 1
PC + 2
NOP
Instruction
fetched
MOVWF PORTB MOVF PORTB,W
write to
PORTB
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
Therefore, at higher clock frequencies,
a write followed by a read may be prob-
lematic.
Instruction
executed
MOVWF PORTB MOVF PORTB,W
NOP
write to
PORTB
FIGURE 10-21: I/O CONNECTION ISSUES
PIC17CXXX
BSF PORTx, PINy
Q2 Q3 Q4
BSF PORTx, PINz
Q1
Q2
Q3
Q4
Q1
I/O
VIL
(1)
C
PORTx, PINy
Read PORTx, PINy as low
BSF PORTx, PINz clears the value
Note 1: This is not a capacitor to ground, but the effective
capacitive loading on the trace.
to be driven on the PORTx, PINy pin.
DS30289A-page 92
1998 Microchip Technology Inc.
PIC17C7XX
11.3
Timer2 Overview
11.0 OVERVIEW OF TIMER
RESOURCES
The PIC17C7XX has four timer modules. Each module
can generate an interrupt to indicate that an event has
occurred. These timers are called:
The Timer2 module is an 8-bit timer/counter with an
8-bit period register (PR2). When the TMR2 value rolls
over from the period match value to 0h, the TMR2IF
flag is set, and an interrupt will be generated if
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also provide the clock for
the Timer1 module.
• Timer0 - 16-bit timer with programmable 8-bit
prescaler
• Timer1 - 8-bit timer
• Timer2 - 8-bit timer
• Timer3 - 16-bit timer
TMR2 can be concatenated with TMR1 to form a
16-bit timer. The TMR2 register is the MSB and TMR1
is the LSB. When in the 16-bit timer mode, there is a
corresponding 16-bit period register (PR2:PR1). When
the TMR2:TMR1 value rolls over from the period
match value to 0h, the TMR1IF flag is set, and an
interrupt will be generated if enabled.
For enhanced time-base functionality, four input Cap-
tures and three Pulse Width Modulation (PWM) out-
puts are possible. The PWMs use the Timer1 and
Timer2 resources and the input Captures use the
Timer3 resource.
11.4
Timer3 Overview
11.1
Timer0 Overview
The Timer3 module is a 16-bit timer/counter with a
16-bit period register. When the TMR3H:TMR3L value
rolls over to 0h, the TMR3IF bit is set and an interrupt
will be generated if enabled. In counter mode, the
clock comes from the RB5/TCLK3 pin.
The Timer0 module is a simple 16-bit overflow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock.
When Timer0 uses an external clock source, it has the
flexibility to allow user selection of the incrementing
edge, rising or falling.
When operating in the four capture mode, the period
registers become the second (of four) 16-bit capture
registers.
The Timer0 module also has a programmable pres-
caler. The T0PS3:T0PS0 bits (T0STA<4:1>) determine
the prescale value. TMR0 can increment at the follow-
ing rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128,
1:256.
11.5
Role of the Timer/Counters
The timer modules are general purpose, but have ded-
icated resources associated with them. TImer1 and
Timer2 are the time-bases for the three Pulse Width
Modulation (PWM) outputs, while Timer3 is the
time-base for the four input captures.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher than the device’s fre-
quency. The maximum external frequency, on the
T0CKI pin, is 50 MHz, given the high and low time
requirements of the clock.
11.2
Timer1 Overview
The Timer1 module is an 8-bit timer/counter with an
8-bit period register (PR1). When the TMR1 value rolls
over from the period match value to 0h, the TMR1IF
flag is set, and an interrupt will be generated if
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also be selected to be the
clock for the Timer2 module.
TMR1 can be concatenated with TMR2 to form a
16-bit timer. The TMR1 register is the LSB and TMR2
is the MSB. When in the 16-bit timer mode, there is a
corresponding 16-bit period register (PR2:PR1). When
the TMR2:TMR1 value rolls over from the period
match value to 0h, the TMR1IF flag is set, and an
interrupt will be generated if enabled.
1998 Microchip Technology Inc.
DS30289A-page 93
PIC17C7XX
NOTES:
DS30289A-page 94
1998 Microchip Technology Inc.
PIC17C7XX
12.0 TIMER0
The Timer0 module consists of a 16-bit timer/counter,
TMR0. The high byte is register TMR0H and the low
byte is register TMR0L. A software programmable 8-bit
prescaler makes Timer0 an effective 24-bit overflow
timer. The clock source is software programmable as
either the internal instruction clock or an external clock
on the RA1/T0CKI pin. The control bits for this module
are in register T0STA (Figure 12-1).
FIGURE 12-1: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
U - 0
R = Readable bit
W = Writable bit
U = Unimplemented,
Read as '0'
INTEDG
T0SE
T0CS
T0PS3
T0PS2
T0PS1
T0PS0
—
bit7
bit0
-n = Value at POR reset
bit 7:
bit 6:
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment
When T0CS = 0 (External Clock)
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit
When T0CS = 1 (Internal Clock)
Don’t care
bit 5:
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for TMR0.
1 = Internal instruction clock cycle (TCY)
0 = External Clock input on the T0CKI pin
bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for TMR0.
T0PS3:T0PS0 Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
bit 0:
Unimplemented: Read as '0'
1998 Microchip Technology Inc.
DS30289A-page 95
PIC17C7XX
12.1
Timer0 Operation
12.2
Using Timer0 with External Clock
When the T0CS (T0STA<5>) bit is set, TMR0 incre-
ments on the internal clock.When T0CS is clear, TMR0
increments on the external clock (RA1/T0CKI pin). The
external clock edge can be selected in software. When
the T0SE (T0STA<6>) bit is set, the timer will increment
on the rising edge of the RA1/T0CKI pin. When T0SE
is clear, the timer will increment on the falling edge of
the RA1/T0CKI pin. The prescaler can be programmed
to introduce a prescale of 1:1 to 1:256.The timer incre-
ments from 0000h to FFFFh and rolls over to 0000h.
On overflow, the TMR0 Interrupt Flag bit (T0IF) is set.
The TMR0 interrupt can be masked by clearing the cor-
responding TMR0 Interrupt Enable bit (T0IE). The
TMR0 Interrupt Flag bit (T0IF) is automatically cleared
when vectoring to the TMR0 interrupt vector.
When an external clock input is used for Timer0, it is
synchronized with the internal phase clocks.
Figure 12-3 shows the synchronization of the external
clock. This synchronization is done after the prescaler.
The output of the prescaler (PSOUT) is sampled twice
in every instruction cycle to detect a rising or a falling
edge. The timing requirements for the external clock
are detailed in the electrical specification section.
12.2.1 DELAY FROM EXTERNAL CLOCK EDGE
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time TMR0 is actually
incremented. Figure 12-3 shows that this delay is
between 3TOSC and 7TOSC. Thus, for example, mea-
suring the interval between two edges (e.g. period) will
be accurate within ±4TOSC (±121 ns @ 33 MHz).
FIGURE 12-2: TIMER0 MODULE BLOCK DIAGRAM
Interrupt on overflow
sets T0IF
(INTSTA<5>)
Prescaler
(8 stage
0
1
Synchronization
TMR0H<8> TMR0L<8>
RA1/T0CKI
Fosc/4
async ripple
PSOUT
counter)
T0SE
(T0STA<6>)
4
Q2
Q4
T0PS3:T0PS0
(T0STA<4:1>)
T0CS
(T0STA<5>)
FIGURE 12-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler
output
(PSOUT)
(note 3)
(note 2)
Sampled
Prescaler
output
(note 1)
Increment
TMR0
T0
T0 + 1
T0 + 2
TMR0
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
2: ↑ = PSOUT is sampled here.
3: The PSOUT high time is too short and is missed by the sampling circuit.
DS30289A-page 96
1998 Microchip Technology Inc.
PIC17C7XX
12.3.2 WRITING A 16-BIT VALUE TO TMR0
12.3
Read/Write Consideration for TMR0
Since writing to either TMR0L or TMR0H will effectively
inhibit increment of that half of the TMR0 in the next
cycle (following write), but not inhibit increment of the
other half, the user must write to TMR0L first and
TMR0H second in two consecutive instructions, as
shown in Example 12-2. The interrupt must be dis-
abled. Any write to either TMR0L or TMR0H clears the
prescaler.
Although TMR0 is a 16-bit timer/counter, only 8-bits at
a time can be read or written during a single instruction
cycle. Care must be taken during any read or write.
12.3.1 READING 16-BIT VALUE
The problem in reading the entire 16-bit value is that
after reading the low (or high) byte, its value may
change from FFh to 00h.
EXAMPLE 12-2: 16-BIT WRITE
Example 12-1 shows a 16-bit read. To ensure a proper
read, interrupts must be disabled during this routine.
BSF
CPUSTA, GLINTD ; Disable interrupts
MOVFP
MOVFP
BCF
RAM_L, TMR0L
RAM_H, TMR0H
CPUSTA, GLINTD ; Done, enable
interrupts
;
;
EXAMPLE 12-1: 16-BIT READ
MOVPF
MOVPF
MOVFP
TMR0L, TMPLO
TMR0H, TMPHI
TMPLO, WREG
;read low tmr0
;read high tmr0
;tmplo −> wreg
;tmr0l < wreg?
;no then return
;read low tmr0
;read high tmr0
;return
;
CPFSLT TMR0L
RETURN
12.4
Prescaler Assignments
MOVPF
MOVPF
RETURN
TMR0L, TMPLO
TMR0H, TMPHI
Timer0 has an 8-bit prescaler. The prescaler selection
is fully under software control; i.e., it can be changed
“on the fly” during program execution. Clearing the
prescaler is recommended before changing its setting.
The value of the prescaler is “unknown,” and assigning
a value that is less than the present value makes it dif-
ficult to take this unknown time into account.
FIGURE 12-4: TMR0 TIMING: WRITE HIGH OR LOW BYTE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
PC+1
PC+2
PC+3
PC+4
PC
T0
T0+1
New T0 (NT0)
New T0+1
TMR0L
Fetch
MOVFP W,TMR0L MOVFP TMR0L,W MOVFP TMR0L,W MOVFP TMR0L,W
Instruction
executed
Write to TMR0L
Read TMR0L
(Value = NT0)
Read TMR0L
(Value = NT0)
Read TMR0L
(Value = NT0 +1)
TMR0H
1998 Microchip Technology Inc.
DS30289A-page 97
PIC17C7XX
FIGURE 12-5: TMR0 READ/WRITE IN TIMER MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
WR_TRM0L
WR_TMR0H
RD_TMR0L
12
AB
12
13
56
TMR0H
57
58
TMR0L
FE
FF
MOVFP
MOVFP
MOVPF
MOVPF
TMR0L,W
MOVPF
MOVPF
DATAL,TMR0L DATAH,TMR0H
TMR0L,W
TMR0L,W
TMR0L,W
Instruction
fetched
Write TMR0L Write TMR0H Read TMR0L Read TMR0L Read TMR0L Read TMR0L
Previously
Fetched
Instruction
MOVFP
MOVFP
MOVPF
MOVPF
MOVPF
Instruction
executed
DATAL,TMR0L DATAH,TMR0H
TMR0L,W
TMR0L,W
TMR0L,W
Write TMR0L Write TMR0H Read TMR0L Read TMR0L Read TMR0L
In this example, old TMR0 value is 12FEh, new value of AB56h is written.
TABLE 12-1: REGISTERS/BITS ASSOCIATED WITH TIMER0
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
05h, Unbanked
06h, Unbanked
07h, Unbanked
0Bh, Unbanked
0Ch, Unbanked
T0STA
INTEDG
—
T0SE
—
T0CS
STKAV
T0IF
T0PS3
GLINTD
INTF
T0PS2
TO
T0PS1
PD
T0PS0
POR
—
0000 000-
--11 11qq
0000 0000
xxxx xxxx
xxxx xxxx
0000 000-
--11 qquu
0000 0000
uuuu uuuu
uuuu uuuu
CPUSTA
INTSTA
TMR0L
TMR0H
BOR
INTE
PEIF
T0CKIF
PEIE
T0CKIE
T0IE
TMR0 register; low byte
TMR0 register; high byte
Legend:
x= unknown, u= unchanged, -= unimplemented read as a '0', q- value depends on condition, Shaded cells are not used by Timer0.
DS30289A-page 98
1998 Microchip Technology Inc.
PIC17C7XX
Six other registers comprise the Capture2, Capture3,
and Capture4 registers (CA2H:CA2L, CA3H:CA3L,
and CA4H:CA4L).
13.0 TIMER1, TIMER2,TIMER3,
PWMS AND CAPTURES
The PIC17C7XX has a wealth of timers and time-based
functions to ease the implementation of control applica-
tions. These time-base functions include three PWM
outputs and four Capture inputs.
Figure 13-1, Figure 13-2, and Figure 13-3 are the con-
trol registers for the operation of Timer1, Timer2, and
Timer3, as well as PWM1, PWM2, PWM3, Capture1,
Capture2, Capture3, and Capture4.
Timer1 and Timer2 are two 8-bit incrementing timers,
each with an 8-bit period register (PR1 and PR2
respectively) and separate overflow interrupt flags.
Timer1 and Timer2 can operate either as timers (incre-
ment on internal Fosc/4 clock) or as counters (incre-
ment on falling edge of external clock on pin
RB4/TCLK12). They are also software configurable to
operate as a single 16-bit timer/counter. These timers
are also used as the time-base for the PWM (Pulse
Width Modulation) modules.
Table 13-1 shows the Timer resource requirements for
these time-base functions. Each timer is an open
resource so that multiple functions may operate with it.
TABLE 13-1: TIME-BASE FUNCTION /
RESOURCE
REQUIREMENTS
Time-base Function
PWM1
Timer Resource
Timer1
Timer3 is a 16-bit timer/counter which uses the TMR3H
and TMR3L registers. Timer3 also has two additional
registers (PR3H/CA1H: PR3L/CA1L) that are config-
urable as a 16-bit period register or a 16-bit capture
register. TMR3 can be software configured to incre-
ment from the internal system clock (FOSC/4) or from
an external signal on the RB5/TCLK3 pin.Timer3 is the
time-base for all of the 16-bit captures.
PWM2
Timer1 or Timer2
Timer1 or Timer2
Timer3
PWM3
Capture1
Capture2
Capture3
Capture4
Timer3
Timer3
Timer3
FIGURE 13-1: TCON1 REGISTER (ADDRESS: 16h, BANK 3)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
bit7
bit0
bit 7-6: CA2ED1:CA2ED0: Capture2 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 5-4: CA1ED1:CA1ED0: Capture1 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 3:
bit 2:
bit 1:
bit 0:
T16: Timer2:Timer1 Mode Select bit
1 = Timer2 and Timer1 form a 16-bit timer
0 = Timer2 and Timer1 are two 8-bit timers
TMR3CS: Timer3 Clock Source Select bit
1 = TMR3 increments off the falling edge of the RB5/TCLK3 pin
0 = TMR3 increments off the internal clock
TMR2CS: Timer2 Clock Source Select bit
1 = TMR2 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR2 increments off the internal clock
TMR1CS: Timer1 Clock Source Select bit
1 = TMR1 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR1 increments off the internal clock
1998 Microchip Technology Inc.
DS30289A-page 99
PIC17C7XX
FIGURE 13-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3)
R - 0
R - 0
R/W - 0
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
bit7
bit0
bit 7:
CA2OVF: Capture2 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L)
before the next capture event occurred.The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture2 register
0 = No overflow occurred on Capture2 register
bit 6:
CA1OVF: Capture1 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(PR3H/CA1H:PR3L/CA1L) before the next capture event occurred. The capture register retains the old-
est unread capture value (last capture before overflow). Subsequent capture events will not update the
capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture1 register
0 = No overflow occurred on Capture1 register
bit 5:
bit 4:
bit 3:
PWM2ON: PWM2 On bit
1 = PWM2 is enabled
(The RB3/PWM2 pin ignores the state of the DDRB<3> bit)
0 = PWM2 is disabled
(The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction)
PWM1ON: PWM1 On bit
1 = PWM1 is enabled
(The RB2/PWM1 pin ignores the state of the DDRB<2> bit)
0 = PWM1 is disabled
(The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction)
CA1/PR3: CA1/PR3 Register Mode Select bit
1 = Enables Capture1
(PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without a period register)
0 = Enables the Period register
(PR3H/CA1H:PR3L/CA1L is the Period register for Timer3)
bit 2:
bit 1:
TMR3ON: Timer3 On bit
1 = Starts Timer3
0 = Stops Timer3
TMR2ON: Timer2 On bit
This bit controls the incrementing of the TMR2 register. When TMR2:TMR1 form the 16-bit timer (T16 is
set), TMR2ON must be set. This allows the MSB of the timer to increment.
1 = Starts Timer2 (Must be enabled if the T16 bit (TCON1<3>) is set)
0 = Stops Timer2
bit 0:
TMR1ON: Timer1 On bit
When T16 is set (in 16-bit Timer Mode)
1 = Starts 16-bit TMR2:TMR1
0 = Stops 16-bit TMR2:TMR1
When T16 is clear (in 8-bit Timer Mode)
1 = Starts 8-bit Timer1
0 = Stops 8-bit Timer1
DS30289A-page 100
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7)
U-0
—
R - 0
R - 0
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Reads as ‘0’
CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
bit7
bit0
-n = Value at POR reset
bit 7:
bit 6:
Unimplemented: Read as ‘0’
CA4OVF: Capture4 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture4 registers
0 = No overflow occurred on Capture4 registers
bit 5:
CA3OVF: Capture3 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA3H:CA3L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture3 registers
0 = No overflow occurred on Capture3 registers
bit 4-3: CA4ED1:CA4ED0: Capture4 Mode Select bits
00= Capture on every falling edge
01= Capture on every rising edge
10= Capture on every 4th rising edge
11= Capture on every 16th rising edge
bit 2-1: CA3ED1:CA3ED0: Capture3 Mode Select bits
00= Capture on every falling edge
01= Capture on every rising edge
10= Capture on every 4th rising edge
11= Capture on every 16th rising edge
bit 0:
PWM3ON: PWM3 On bit
1 = PWM3 is enabled (The RG5/PWM3 pin ignores the state of the DDRG<5> bit)
0 = PWM3 is disabled (The RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)
1998 Microchip Technology Inc.
DS30289A-page 101
PIC17C7XX
13.1.1.1 EXTERNAL CLOCK INPUT FOR TIMER1
AND TIMER2
13.1
Timer1 and Timer2
13.1.1 TIMER1, TIMER2 IN 8-BIT MODE
When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the counter will increment on
every falling edge on the RB4/TCLK12 pin. The
TCLK12 input is synchronized with internal phase
clocks.This causes a delay from the time a falling edge
appears on TCLK12 to the time TMR1 or TMR2 is actu-
ally incremented. For the external clock input timing
requirements, see the Electrical Specification section.
Both Timer1 and Timer2 will operate in 8-bit mode
when the T16 bit is clear.These two timers can be inde-
pendently configured to increment from the internal
instruction cycle clock (TCY) or from an external clock
source on the RB4/TCLK12 pin.The timer clock source
is configured by the TMRxCS bit (x = 1 for Timer1 or =
2 for Timer2). When TMRxCS is clear, the clock source
is internal and increments once every instruction cycle
(Fosc/4). When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the counters will increment on
every falling edge of the RB4/TCLK12 pin.
The timer increments from 00h until it equals the Period
register (PRx). It then resets to 00h at the next incre-
ment cycle. The timer interrupt flag is set when the
timer is reset. TMR1 and TMR2 have individual inter-
rupt flag bits. The TMR1 interrupt flag bit is latched into
TMR1IF, and the TMR2 interrupt flag bit is latched into
TMR2IF.
Each timer also has a corresponding interrupt enable
bit (TMRxIE). The timer interrupt can be enabled/dis-
abled by setting/clearing this bit. For peripheral inter-
rupts to be enabled, the Peripheral Interrupt Enable bit
must be set (PEIE = '1') and global interrupt must be
enabled (GLINTD = '0').
The timers can be turned on and off under software
control.When the timer on control bit (TMRxON) is set,
the timer increments from the clock source. When
TMRxON is cleared, the timer is turned off and cannot
cause the timer interrupt flag to be set.
FIGURE 13-4: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE
0
1
Fosc/4
Reset
Equal
TMR1
Comparatorx8
PR1
Set TMR1IF
(PIR1<4>)
TMR1ON
(TCON2<0>)
TMR1CS
(TCON1<0>)
RB4/TCLK12
1
0
Reset
Equal
TMR2
Comparatorx8
PR2
Set TMR2IF
(PIR1<5>)
Fosc/4
TMR2ON
(TCON2<1>)
TMR2CS
(TCON1<1>)
DS30289A-page 102
1998 Microchip Technology Inc.
PIC17C7XX
13.1.2 TIMER1 AND TIMER2 IN 16-BIT MODE
13.1.2.1 EXTERNAL CLOCK INPUT FOR
TMR2:TMR1
To select 16-bit mode, set the T16 bit. In this mode
TMR2 and TMR1 are concatenated to form a 16-bit
timer (TMR2:TMR1). The 16-bit timer increments until
it matches the 16-bit period register (PR2:PR1). On
the following timer clock, the timer value is reset to 0h,
and the TMR1IF bit is set.
When TMR1CS is set, the 16-bit TMR2:TMR1 incre-
ments on the falling edge of clock input TCLK12. The
input on the RB4/TCLK12 pin is sampled and synchro-
nized by the internal phase clocks twice every instruc-
tion cycle. This causes a delay from the time a falling
edge appears on RB4/TCLK12 to the time
TMR2:TMR1 is actually incremented. For the external
clock input timing requirements, see the Electrical
Specification section.
When selecting the clock source for the 16-bit timer, the
TMR1CS bit controls the entire 16-bit timer and
TMR2CS is a “don’t care”, however ensure that
TMR2ON is set (allows TMR2 to increment). When
TMR1CS is clear, the timer increments once every
instruction cycle (Fosc/4). When TMR1CS is set, the
timer increments on every falling edge of the
RB4/TCLK12 pin. For the 16-bit timer to increment,
both TMR1ON and TMR2ON bits must be set
(Table 13-2).
TABLE 13-2: TURNING ON 16-BIT TIMER
T16 TMR2ON TMR1ON
Result
16-bit timer
1
1
1
(TMR2:TMR1) ON
Only TMR1 increments
16-bit timer OFF
1
1
0
0
x
1
1
0
1
Timers in 8-bit mode
FIGURE 13-5: TMR2 AND TMR1 IN 16-BIT TIMER/COUNTER MODE
1
RB4/TCLK12
0
Fosc/4
TMR1ON
(TCON2<0>)
MSB
LSB
TMR1CS
(TCON1<0>)
Reset
TMR2 x 8
TMR1 x 8
Comparatorx16
Equal
Set Interrupt TMR1IF
(PIR1<4>)
PR2 x 8
PR1 x 8
1998 Microchip Technology Inc.
DS30289A-page 103
PIC17C7XX
TABLE 13-3: SUMMARY OF TIMER1,TIMER2 AND TIMER3 REGISTERS
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 3
17h, Bank 3
TCON1
TCON2
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
0000 0000 0000 0000
0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
16h, Bank 7
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
TCON3
TMR1
TMR2
PIR1
—
CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
Timer1’s register
Timer2’s register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
x000 0010 u000 0010
0000 0000 0000 0000
0000 0000 0000 0000
RBIF
RBIE
PEIF
TMR3IF
TMR2IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
CA1IF
CA1IE
TX1IF
TX1IE
T0IE
RC1IF
RC1IE
INTE
PIE1
TMR3IE TMR2IE
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIF
—
T0IF
T0CKIE
—
STKAV
GLINTD
TO
PD
POR
BOR
--11 11qq --11 qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
10h, Bank 7
12h, Bank 3
13h, Bank 3
11h, Bank 7
Legend:
PR1
Timer1 period register
Timer2 period register
PR2
PW1DCL
PW2DCL
PW3DCL
PW1DCH
PW2DCH
PW3DCH
DC1
DC1
DC1
DC9
DC9
DC9
DC0
DC0
DC0
DC8
DC8
DC8
—
TM2PW2
TM2PW3
DC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC6
DC6
DC6
DC5
DC5
DC5
DC4
DC4
DC4
DC3
DC3
DC3
DC2
DC2
DC2
DC7
DC7
x= unknown, u= unchanged, -= unimplemented read as a '0', q - value depends on condition,
shaded cells are not used by Timer1 or Timer2.
DS30289A-page 104
1998 Microchip Technology Inc.
PIC17C7XX
13.1.3 USING PULSE WIDTH MODULATION
(PWM) OUTPUTS WITH TIMER1 AND
TIMER2
The user needs to set the PWM1ON bit (TCON2<4>)
to enable the PWM1 output. When the PWM1ON bit is
set, the RB2/PWM1 pin is configured as PWM1 output
and forced as an output irrespective of the data direc-
tion bit (DDRB<2>). When the PWM1ON bit is clear,
the pin behaves as a port pin and its direction is con-
trolled by its data direction bit (DDRB<2>). Similarly,
the PWM2ON (TCON2<5>) bit controls the configura-
tion of the RB3/PWM2 pin and the PWM3ON
(TCON3<0>) bit controls the configuration of the
RG5/PWM3 pin.
Three high speed pulse width modulation (PWM) out-
puts are provided. The PWM1 output uses Timer1 as
its time-base, while PWM2 and PWM3 may indepen-
dently be software configured to use either Timer1 or
Timer2 as the time-base. The PWM outputs are on the
RB2/PWM1, RB3/PWM2, and RG5/PWM3 pins.
Each PWM output has a maximum resolution of
10-bits. At 10-bit resolution, the PWM output frequency
is 32.2 kHz (@ 32 MHz clock) and at 8-bit resolution the
PWM output frequency is 128.9 kHz. The duty cycle of
the output can vary from 0% to 100%.
FIGURE 13-6: SIMPLIFIED PWM BLOCK
DIAGRAM
PWxDCL<7:6>
Write
Duty Cycle registers
PWxDCH
Figure 13-6 shows a simplified block diagram of a
PWM module.
The duty cycle registers are double buffered for glitch
free operation. Figure 13-7 shows how a glitch could
occur if the duty cycle registers were not double buff-
ered.
Read
(Slave)
PWMx
Comparator
R
S
Q
TMRx
(Note 1)
PWMxON
Comparator
Clear Timer,
PWMx pin and
Latch D.C.
PRy
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
FIGURE 13-7: PWM OUTPUT (NOT BUFFERED)
0
10
20
30
40
0
10
20
30
40
0
PWM
output
Timer
interrupt
Write new
PWM Duty Cycle value
Timer interrupt
new PWM Duty Cycle value
transferred to slave
Note The dotted line shows PWM output if duty cycle registers were not double buffered.
If the new duty cycle is written after the timer has passed that value, then the PWM does
not reset at all during the current cycle causing a “glitch”.
In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.
1998 Microchip Technology Inc.
DS30289A-page 105
PIC17C7XX
13.1.3.1 PWM PERIODS
If DCx = 0, then the duty cycle is zero. If PRx =
PWxDCH, then the PWM output will be low for one to
four Q-clock (depending on the state of the
PWxDCL<7:6> bits). For a Duty Cycle to be 100%, the
PWxDCH value must be greater then the PRx value.
The period of the PWM1 output is determined by
Timer1 and its period register (PR1). The period of the
PWM2 and PWM3 outputs can be individually software
configured to use either Timer1 or Timer2 as the
time-base. For PWM2, when TM2PW2 bit
(PW2DCL<5>) is clear, the time-base is determined by
TMR1 and PR1, and when TM2PW2 is set, the
time-base is determined by Timer2 and PR2. For
PWM3, when TM2PW3 bit (PW3DCL<5>) is clear, the
time-base is determined by TMR1 and PR1, and when
TM2PW3 is set, the time-base is determined by Timer2
and PR2.
The duty cycle registers for both PWM outputs are dou-
ble buffered. When the user writes to these registers,
they are stored in master latches. When TMR1 (or
TMR2) overflows and a new PWM period begins, the
master latch values are transferred to the slave latches
and the PWMx pin is forced high.
Note: For PW1DCH, PW1DCL, PW2DCH,
PW2DCL, PW3DCH and PW3DCL regis-
ters, a write operation writes to the "master
latches" while a read operation reads the
"slave latches". As a result, the user may
not read back what was just written to the
duty cycle registers (until transfered to
slave latch).
Running two different PWM outputs on two different
timers allows different PWM periods. Running all
PWMs from Timer1 allows the best use of resources by
freeing Timer2 to operate as an 8-bit timer. Timer1 and
Timer2 cannot be used as a 16-bit timer if any PWM is
being used.
The user should also avoid any "read-modify-write"
operations on the duty cycle registers, such as:
ADDWF PW1DCH. This may cause duty cycle outputs
that are unpredictable.
The PWM periods can be calculated as follows:
period of PWM1 = [(PR1) + 1] x 4TOSC
period of PWM2 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
TABLE 13-4: PWM FREQUENCY vs.
RESOLUTION AT 33 MHz
period of PWM3 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
Frequency (kHz)
PWM
The duty cycle of PWMx is determined by the 10-bit
value DCx<9:0>. The upper 8-bits are from register
PWxDCH and the lower 2-bits are from PWxDCL<7:6>
(PWxDCH:PWxDCL<7:6>). Table 13-4 shows the
maximum PWM frequency (FPWM) given the value in
the period register.
Frequency
32.2 64.5 90.66 128.9 515.6
PRx Value 0xFF 0x7F 0x5A
0x3F
0x0F
6-bit
High
10-bit 9-bit 8.5-bit 8-bit
Resolution
Standard
8-bit
7-bit 6.5-bit 6-bit
4-bit
The number of bits of resolution that the PWM can
achieve depends on the operation frequency of the
device as well as the PWM frequency (FPWM).
Resolution
13.1.3.2 PWM INTERRUPTS
Maximum PWM resolution (bits) for a given PWM fre-
quency:
The PWM modules makes use of the TMR1 and/or
TMR2 interrupts. A timer interrupt is generated when
TMR1 orTMR2 equals its period register and on the fol-
lowing increment is cleared to zero. This interrupt also
marks the beginning of a PWM cycle. The user can
write new duty cycle values before the timer roll-over.
The TMR1 interrupt is latched into the TMR1IF bit and
the TMR2 interrupt is latched into the TMR2IF bit.
These flags must be cleared in software.
FOSC
FPWM
log
(
)
=
bits
log (2)
where: FPWM = 1 / period of PWM
The PWMx duty cycle is as follows:
PWMx Duty Cycle =(DCx) x TOSC
where DCx represents the 10-bit value from
PWxDCH:PWxDCL.
DS30289A-page 106
1998 Microchip Technology Inc.
PIC17C7XX
13.1.3.3 EXTERNAL CLOCK SOURCE
13.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR
EXTERNAL CLOCK INPUT
The PWMs will operate regardless of the clock source
of the timer. The use of an external clock has ramifica-
tions that must be understood. Because the external
TCLK12 input is synchronized internally (sampled once
per instruction cycle), the time TCLK12 changes to the
time the timer increments will vary by as much as 1TCY
(one instruction cycle). This will cause jitter in the duty
cycle as well as the period of the PWM output.
The use of an external clock for the PWM time-base
(Timer1 or Timer2) limits the PWM output to a maxi-
mum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when inter-
nal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, as shown in Table 13-4 (standard
resolution mode).
This jitter will be ±1TCY, unless the external clock is
synchronized with the processor clock. Use of one of
the PWM outputs as the clock source to the TCLK12
input, will supply a synchronized clock.
In general, when using an external clock source for
PWM, its frequency should be much less than the
device frequency (Fosc).
TABLE 13-5: REGISTERS/BITS ASSOCIATED WITH PWM
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 3
17h, Bank 3
TCON1
TCON2
CA2ED1 CA2ED0
CA1ED1
CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
TCON3
TMR1
TMR2
PIR1
—
CA4OVF
CA3OVF
CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
xxxx xxxx uuuu uuuu
Timer1’s register
Timer2’s register
xxxx xxxx uuuu uuuu
RBIF
RBIE
PEIF
TMR3IF
TMR2IF
TMR2IE
T0IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
CA1IF
CA1IE
TX1IF
TX1IE
T0IE
RC1IF
RC1IE
INTE
x000 0010 u000 0010
0000 0000 0000 0000
0000 0000 0000 0000
PIE1
TMR3IE
T0CKIF
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIE
—
—
STKAV
GLINTD
TO
PD
POR
BOR
--11 11qq --11 qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
10h, Bank 7
12h, Bank 3
13h, Bank 3
11h, Bank 7
Legend:
PR1
Timer1 period register
Timer2 period register
PR2
PW1DCL
PW2DCL
PW3DCL
PW1DCH
PW2DCH
PW3DCH
DC1
DC1
DC1
DC9
DC9
DC9
DC0
DC0
DC0
DC8
DC8
DC8
—
TM2PW2
TM2PW3
DC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC6
DC6
DC6
DC5
DC5
DC5
DC4
DC4
DC4
DC3
DC3
DC3
DC2
DC2
DC2
DC7
DC7
x= unknown, u= unchanged, -= unimplemented read as '0', q= value depends on conditions,
shaded cells are not used by PWM Module.
1998 Microchip Technology Inc.
DS30289A-page 107
PIC17C7XX
(RB0/CAP1, RB1/CAP2, RG4/CAP3, and RE3/CAP4),
one for each capture register pair.The capture pins are
multiplexed with the I/O pins. An event can be:
13.2
Timer3
Timer3 is a 16-bit timer consisting of the TMR3H and
TMR3L registers. TMR3H is the high byte of the timer
and TMR3L is the low byte. This timer has an associ-
ated 16-bit period register (PR3H/CA1H:PR3L/CA1L).
This period register can be software configured to be a
another 16-bit capture register.
• A rising edge
• A falling edge
• Every 4th rising edge
• Every 16th rising edge
When the TMR3CS bit (TCON1<2>) is clear, the timer
increments every instruction cycle (Fosc/4). When
TMR3CS is set, the counter increments on every falling
edge of the RB5/TCLK3 pin. In either mode, the
TMR3ON bit must be set for the timer/counter to incre-
ment. When TMR3ON is clear, the timer will not incre-
ment or set flag bit TMR3IF.
Each 16-bit capture register has an interrupt flag asso-
ciated with it. The flag is set when a capture is made.
The capture modules are truly part of the Timer3 block.
Figure 13-8 and Figure 13-9 show the block diagrams
for the two modes of operation.
13.2.1 THREE CAPTURE AND ONE PERIOD
REGISTER MODE
Timer3 has two modes of operation, depending on the
CA1/PR3 bit (TCON2<3>). These modes are:
In this mode registers PR3H/CA1H and PR3L/CA1L
constitute a 16-bit period register. A block diagram is
shown in Figure 13-8. The timer increments until it
equals the period register and then resets to 0000h on
the next timer clock. TMR3 Interrupt Flag bit (TMR3IF)
is set at this point. This interrupt can be disabled by
clearing the TMR3 Interrupt Enable bit (TMR3IE).
TMR3IF must be cleared in software.
• Three capture and one period register mode
• Four capture register mode
The PIC17C7XX has up to four 16-bit capture registers
that capture the 16-bit value of TMR3 when events are
detected on capture pins. There are four capture pins
FIGURE 13-8: TIMER3 WITH THREE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
TMR3CS
(TCON1<2>)
PR3H/CA1H
PR3L/CA1L
TMR3L
Set TMR3IF
(PIR1<6>)
Comparatorx16
Equal
Reset
0
Fosc/4
TMR3H
1
TMR3ON
(TCON2<2>)
RB5/TCLK3
RB1/CAP2
Capture2
Enable
Edge select,
Prescaler select
CA2H
CA2L
2
Set CA2IF
(PIR1<3>)
CA2ED1: CA2ED0
(TCON1<7:6>)
Capture3
Enable
Edge select,
Prescaler select
RG4/CAP3
CA3H
CA3L
2
Set CA3IF
(PIR2<2>)
CA3ED1: CA3ED0
(TCON3<2:1>)
Capture4
Enable
Edge select,
Prescaler select
RE3/CAP4
CA4H
CA4L
2
Set CA4IF
(PIR2<3>)
CA4ED1: CA4ED0
(TCON3<4:3>)
DS30289A-page 108
1998 Microchip Technology Inc.
PIC17C7XX
This mode (3 Capture, 1 Period) is selected if control bit
CA1/PR3 is clear. In this mode, the Capture1 register,
consisting of high byte (PR3H/CA1H) and low byte
(PR3L/CA1L), is configured as the period control regis-
ter for TMR3. Capture1 is disabled in this mode, and
the corresponding Interrupt bit CA1IF is never set.
TMR3 increments until it equals the value in the period
register and then resets to 0000h on the next timer
clock.
The input on the capture pin CAPx is synchronized
internally to internal phase clocks.This imposes certain
restrictions on the input waveform (see the Electrical
Specification section for timing).
The capture overflow status flag bit is double buffered.
The master bit is set if one captured word is already
residing in the Capture register (CAxH:CAxL) and
another “event” has occurred on the CAPx pin.The new
event will not transfer the TMR3 value to the capture
register, protecting the previous unread capture value.
When the user reads both the high and the low bytes
(in any order) of the Capture register, the master
overflow bit is transferred to the slave overflow bit
(CAxOVF) and then the master bit is reset. The user
can then read TCONx to determine the value of
CAxOVF.
All other Captures are active in this mode.
13.2.1.1 CAPTURE OPERATION
The CAxED1 and CAxED0 bits determine the event on
which capture will occur. The possible events are:
• Capture on every falling edge
• Capture on every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
The recommended sequence to read capture registers
and capture overflow flag bits is shown in
Example 13-1.
When a capture takes place, an interrupt flag is latched
into the CAxIF bit.This interrupt can be enabled by set-
ting the corresponding mask bit CAxIE. The Peripheral
Interrupt Enable bit (PEIE) must be set and the Global
Interrupt Disable bit (GLINTD) must be cleared for the
interrupt to be acknowledged. The CAxIF interrupt flag
bit is cleared in software.
When the capture prescale select is changed, the pres-
caler is not reset and an event may be generated.
Therefore, the first capture after such a change will be
ambiguous. However, it sets the time-base for the next
capture. The prescaler is reset upon chip reset.
The capture pin, CAPx, is a multiplexed pin. When
used as a port pin, the capture is not disabled. How-
ever, the user can simply disable the Capture interrupt
by clearing CAxIE. If the CAPx pin is used as an output
pin, the user can activate a capture by writing to the
port pin.This may be useful during development phase
to emulate a capture interrupt.
1998 Microchip Technology Inc.
DS30289A-page 109
PIC17C7XX
13.2.2 FOUR CAPTURE MODE
All the captures operate in the same manner. Refer to
Section 13.2.1 for the operation of capture.
This mode is selected by setting bit CA1/PR3. A block
diagram is shown in Figure 13-9. In this mode, TMR3
runs without a period register and increments from
0000h to FFFFh and rolls over to 0000h. The TMR3
interrupt Flag (TMR3IF) is set on this rollover. The
TMR3IF bit must be cleared in software.
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set upon detection of the capture event.The
corresponding interrupt mask bit is CA1IE. The
Capture1 Overflow Status bit is CA1OVF.
FIGURE 13-9: TIMER3 WITH FOUR CAPTURES BLOCK DIAGRAM
Set TMR3IF
(PIR1<6>)
Fosc/4
0
TMR3H
TMR3L
1
TMR3ON
RB5/TCLK3
RB0/CAP1
TMR3CS
(TCON2<2>)
(TCON1<2>)
Capture1 Enable
Edge Select,
Prescaler Select
2
Set CA1IF
(PIR1<2>)
PR3H/CA1H
PR3L/CA1L
CA1ED1, CA1ED0
(TCON1<5:4>)
Capture2 Enable
Edge Select,
Prescaler Select
Set CA2IF
(PIR1<3>)
RB1/CAP2
RG4/CAP3
2
CA2H
CA2L
CA2ED1, CA2ED0
(TCON1<7:6>)
Capture3 Enable
Set CA3IF
(PIR2<2>)
Edge Select,
Prescaler Select
2
CA3H
CA3L
CA3ED1: CA3ED0
(TCON3<2:1>)
Capture4 Enable
Set CA4IF
(PIR2<3>)
Edge Select,
Prescaler Select
RE3/CAP4
2
CA4H
CA4L
CA4ED1: CA4ED0
(TCON3<4:3>)
DS30289A-page 110
1998 Microchip Technology Inc.
PIC17C7XX
13.2.3 READING THE CAPTURE REGISTERS
An example of an instruction sequence to read capture
registers and capture overflow flag bits is shown in
Example 13-1. Depending on the capture source, dif-
ferent registers will need to be read.
The Capture overflow status flag bits are double
buffered. The master bit is set if one captured word is
already residing in the Capture register and another
“event” has occurred on the CAPx pin. The new event
will not transfer the TMR3 value to the capture register,
protecting the previous unread capture value. When
the user reads both the high and the low bytes (in any
order) of the Capture register, the master overflow bit is
transferred to the slave overflow bit (CAxOVF) and then
the master bit is reset. The user can then read TCONx
to determine the value of CAxOVF.
EXAMPLE 13-1: SEQUENCE TO READ CAPTURE REGISTERS
MOVLB 3
; Select Bank 3
MOVPF CA2L, LO_BYTE
MOVPF CA2H, HI_BYTE
MOVPF TCON2, STAT_VAL
; Read Capture2 low byte, store in LO_BYTE
; Read Capture2 high byte, store in HI_BYTE
; Read TCON2 into file STAT_VAL
TABLE 13-6: REGISTERS ASSOCIATED WITH CAPTURE
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 3
17h, Bank 3
TCON1
TCON2
CA2ED1 CA2ED0 CA1ED1
CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000
16h, Bank 7
12h, Bank 2
13h, Bank 2
16h, Bank 1
17h, Bank 1
10h, Bank 4
11h, Bank 4
TCON3
TMR3L
TMR3H
PIR1
—
Holding register for the low byte of the 16-bit TMR3 register
Holding register for the high byte of the 16-bit TMR3 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
x000 0010 u000 0010
0000 0000 0000 0000
000- 0010 000- 0010
000- 0000 000- 0000
0000 0000 0000 0000
--11 11qq --11 qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RBIF
RBIE
SSPIF
SSPIE
PEIF
—
TMR3IF
TMR3IE
BCLIF
BCLIE
T0CKIF
—
TMR2IF
TMR2IE
ADIF
TMR1IF
TMR1IE
—
CA2IF
CA2IE
CA4IF
CA4IE
PEIE
CA1IF
CA1IE
CA3IF
CA3IE
T0CKIE
PD
TX1IF
TX1IE
TX2IF
TX2IE
T0IE
RC1IF
RC1IE
RC2IF
RC2IE
INTE
PIE1
PIR2
PIE2
ADIE
—
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0IF
INTF
STKAV
GLINTD
TO
POR
BOR
16h, Bank 2
17h, Bank 2
14h, Bank 3
15h, Bank 3
12h, Bank 7
13h, Bank 7
14h, Bank 7
15h, Bank 7
Legend:
PR3L/CA1L Timer3 period register, low byte/capture1 register, low byte
PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte
CA2L
CA2H
CA3L
CA3H
CA4L
CA4H
Capture2 low byte
Capture2 high byte
Capture3 low byte
Capture3 high byte
Capture4 low byte
Capture4 high byte
x= unknown, u= unchanged, -= unimplemented read as '0', q- value depends on condition,
shaded cells are not used by Capture.
1998 Microchip Technology Inc.
DS30289A-page 111
PIC17C7XX
13.2.4 EXTERNAL CLOCK INPUT FOR TIMER3
13.2.5 READING/WRITING TIMER3
When TMR3CS is set, the 16-bit TMR3 increments on
the falling edge of clock input TCLK3. The input on the
RB5/TCLK3 pin is sampled and synchronized by the
internal phase clocks twice every instruction cycle.This
causes a delay from the time a falling edge appears on
TCLK3 to the time TMR3 is actually incremented. For
the external clock input timing requirements, see the
Electrical Specification section. Figure 13-10 shows
the timing diagram when operating from an external
clock.
Since Timer3 is a 16-bit timer and only 8-bits at a time
can be read or written, care should be taken when
reading or writing while the timer is running. The best
method is to stop the timer, perform any read or write
operation, and then restart Timer3 (using the TMR3ON
bit). However, if it is necessary to keep Timer3 free-run-
ning, care must be taken. For writing to the 16-bit
TMR3, Example 13-2 may be used. For reading the
16-bit TMR3, Example 13-3 may be used. Interrupts
must be disabled during this routine.
EXAMPLE 13-2: WRITING TO TMR3
BSF
CPUSTA, GLINTD
RAM_L, TMR3L
RAM_H, TMR3H
CPUSTA, GLINTD
; Disable interrupts
;
;
MOVFP
MOVFP
BCF
; Done, enable interrupts
EXAMPLE 13-3: READING FROM TMR3
MOVPF
MOVPF
MOVFP
CPFSLT TMR3L
RETURN
MOVPF
MOVPF
RETURN
TMR3L, TMPLO
TMR3H, TMPHI
TMPLO, WREG
; read low TMR3
; read high TMR3
; tmplo −> wreg
; TMR3L < wreg?
; no then return
; read low TMR3
; read high TMR3
; return
TMR3L, TMPLO
TMR3H, TMPHI
FIGURE 13-10: TIMER1,TIMER2, AND TIMER3 OPERATION (IN COUNTER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TCLK12
or TCLK3
34h
35h
A8h
A9h
00h
TMR1, TMR2, or TMR3
PR1, PR2, or PR3H:PR3L
WR_TMR
'A9h'
'A9h'
RD_TMR
TMRxIF
MOVWF
TMRx
MOVFP
MOVFP
TMRx,W
TMRx,W
Instruction
executed
Write to TMRx
Read TMRx
Read TMRx
Note 1: TCLK12 is sampled in Q2 and Q4.
2: ↓ indicates a sampling point.
3: The latency from TCLK12 ↓ to timer increment is between 2Tosc and 6Tosc.
DS30289A-page 112
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 13-11: TIMER1,TIMER2, AND TIMER3 OPERATION (IN TIMER MODE)
Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4
AD15:AD0
ALE
BCF
TCON2, 0
Start TMR1
MOVF
BSF
MOVWF
TMR1
MOVF
NOP
07h
NOP
NOP
NOP
00h
Instruction
fetched
MOVLB 3
NOP
06h
TMR1, W
Read TMR1
TCON2, 0
Stop TMR1
TMR1, W
Write TMR1 Read TMR1
TMR1
PR1
04h
05h
03h
04h
05h
08h
TMR1ON
WR_TMR1
WR_TCON2
TMR1IF
RD_TMR1
TMR1
reads 03h
TMR1
reads 04h
1998 Microchip Technology Inc.
DS30289A-page 113
PIC17C7XX
NOTES:
DS30289A-page 114
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 14-1: USART MODULE GENERIC
NAMES
14.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULES
Generic name
USART1 name USART2 name
Registers
RCSTA
TXSTA
SPBRG
RCREG
TXREG
RCSTA1
TXSTA1
RCSTA2
TXSTA2
SPBRG2
RCREG2
TXREG2
Each USART module is a serial I/O module. There are
two USART modules that are available on the
PIC17C7XX. They are specified as USART1 and
USART2. The description of the operation of these
modules is generic in regard to the register names and
pin names used. Table 14-1 shows the generic names
that are used in the description of operation and the
actual names for both USART1 and USART2. Since
the control bits in each register have the same function,
their names are the same (there is no need to differen-
tiate).
SPBRG1
RCREG1
TXREG1
Interrupt Control Bits
RC1IE
RCIE
RCIF
TXIE
TXIF
RC2IE
RC2IF
TX2IE
TX2IF
RC1IF
TX1IE
TX1IF
The Transmit Status And Control Register (TXSTA) is
shown in Figure 14-1, while the Receive Status And
Control Register (RCSTA) is shown in Figure 14-2.
Pins
RX/DT
TX/CK
RA4/RX1/DT1
RA5/TX1/CK1
RG6/RX2/DT2
RG7/TX2/CK2
FIGURE 14-1: TXSTA1 REGISTER (ADDRESS: 15h, BANK 0)
TXSTA2 REGISTER (ADDRESS: 15h, BANK 4)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
CSRC TX9 TXEN SYNC
bit7
U - 0
—
U - 0
—
R - 1
TRMT
R/W - x
TX9D
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 7:
CSRC: Clock Source Select bit
Synchronous mode:
1 = Master Mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
Asynchronous mode:
Don’t care
bit 6:
bit 5:
TX9: 9-bit Transmit Select bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SREN/CREN overrides TXEN in SYNC mode
bit 4:
SYNC: USART Mode Select bit
(Synchronous/Asynchronous)
1 = Synchronous mode
0 = Asynchronous mode
bit 3-2: Unimplemented: Read as '0'
bit 1:
TRMT: Transmit Shift Register (TSR) Empty bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data (can be used to calculated the parity in software)
1998 Microchip Technology Inc.
DS30289A-page 115
PIC17C7XX
The USART can be configured as a full duplex asyn-
chronous system that can communicate with peripheral
devices such as CRT terminals and personal comput-
ers, or it can be configured as a half duplex synchro-
nous system that can communicate with peripheral
devices such as A/D or D/A integrated circuits, Serial
EEPROMs etc. The USART can be configured in the
following modes:
The SPEN (RCSTA<7>) bit has to be set in order to
configure the I/O pins as the Serial Communication
Interface (USART).
The USART module will control the direction of the
RX/DT and TX/CK pins, depending on the states of the
USART configuration bits in the RCSTA and TXSTA
registers. The bits that control I/O direction are:
• SPEN
• TXEN
• SREN
• CREN
• CSRC
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
FIGURE 14-2: RCSTA1 REGISTER (ADDRESS: 13h, BANK 0)
RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN RX9 SREN CREN
bit7
U - 0
—
R - 0
FERR
R - 0
OERR
R - x
RX9D
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 0
bit 7:
bit 6:
bit 5:
SPEN: Serial Port Enable bit
1 = Configures TX/CK and RX/DT pins as serial port pins
0 = Serial port disabled
RX9: 9-bit Receive Select bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
bit 4:
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable continuous reception
0 = Disables continuous reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
bit 3:
bit 2:
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
bit 1:
bit 0:
OERR: Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
RX9D: 9th bit of receive data (can be the software calculated parity bit)
DS30289A-page 116
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 14-3: USART TRANSMIT
Sync
Master/Slave
BRG
÷ 4
Sync/Async
CK/TX
Sync/Async
Sync/Async
TSR
÷ 16
Clock
• • •
Start 0 1
7 8 Stop
DT
Load
Bit Count
TXEN/
Write to TXREG
8
• • •
0 1
7
TXREG
Interrupt
TXSTA<0>
Data Bus
TXIE
FIGURE 14-4: USART RECEIVE
Interrupt
RCIE
OSC
÷ 4
BRG
Master/Slave
Sync
Sync/Async
Async/Sync
enable
Buffer
Logic
Bit Count
÷ 16
CK
RX
START
Detect
SPEN
SREN/
CREN/
Start_Bit
RSR
Majority
Detect
Buffer
Logic
Clock
Data
MSb
Stop 8 7
LSb
1 0
• • •
FIFO
Logic
RX9
Async/Sync
RCREG
Clk
FIFO
• • •
• • •
RX9D
RX9D
7
7
1 0
1 0
FERR
FERR
Data Bus
1998 Microchip Technology Inc.
DS30289A-page 117
PIC17C7XX
Writing a new value to the SPBRG, causes the BRG
timer to be reset (or cleared), this ensures that the BRG
does not wait for a timer overflow before outputting the
new baud rate.
14.1
USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. Table 14-2 shows
the formula for computation of the baud rate for differ-
ent USART modes.These only apply when the USART
is in synchronous master mode (internal clock) and
asynchronous mode.
14.1.1 EFFECTS OF RESET
After any device reset the SPBRG register is cleared.
The SPBRG register will need to be loaded with the
desired value after each reset.
Given the desired baud rate and Fosc, the nearest inte-
ger value between 0 and 255 can be calculated using
the formula below. The error in baud rate can then be
determined.
TABLE 14-2: BAUD RATE FORMULA
SYNC
Mode
Baud Rate
0
1
Asynchronous
Synchronous
FOSC/(64(X+1))
FOSC/(4(X+1))
X = value in SPBRG (0 to 255)
Example 14-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
SYNC = 0
EXAMPLE 14-1: CALCULATING BAUD
RATE ERROR
Desired Baud rate=Fosc / (64 (X + 1))
9600 =
16000000 /(64 (X + 1))
X
=
25.042 → 25
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
=
9615
Error
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
=
(9615 - 9600) / 9600
0.16%
TABLE 14-3: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
13h, Bank 0
RCSTA1
SPEN
CSRC
RX9
TX9
SREN
TXEN
CREN
SYNC
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x
0000 -00u
15h, Bank 0
17h, Bank 0
TXSTA1
0000 --1x
0000 0000
0000 --1u
0000 0000
SPBRG1
Baud rate generator register
13h, Bank 4
RCSTA2
SPEN
CSRC
RX9
TX9
SREN
TXEN
CREN
SYNC
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x
0000 -00u
15h, Bank 4
17h, Bank 4
TXSTA2
0000 --1x
0000 0000
0000 --1u
0000 0000
SPBRG2
Baud rate generator register
Legend:
x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used by the Baud Rate Generator.
DS30289A-page 118
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 14-4: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
0.3
1.2
NA
NA
—
—
—
—
NA
NA
—
—
—
—
—
—
—
80
64
20
12
0
NA
NA
—
—
—
—
NA
NA
—
—
—
—
2.4
NA
—
—
NA
—
NA
—
—
NA
—
—
9.6
NA
—
—
NA
—
NA
—
—
NA
—
—
19.2
76.8
96
NA
—
—
NA
—
19.53
76.92
96.15
294.1
500
+1.73
+0.16
+0.16
-1.96
0
255
64
51
16
9
19.23
76.92
95.24
307.69
500
+0.16
+0.16
-0.79
+2.56
0
207
51
41
12
7
77.10
95.93
294.64
485.29
8250
32.22
+0.39
-0.07
-1.79
-2.94
—
106
85
27
16
0
77.16
96.15
297.62
480.77
6250
24.41
+0.47
+0.16
-0.79
-3.85
—
300
500
HIGH
LOW
5000
19.53
—
0
4000
15.625
—
0
—
255
—
255
—
255
—
255
FOSC = 10 MHz
KBAUD
FOSC = 7.159 MHz
FOSC = 5.068 MHz
BAUD
RATE
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
NA
—
—
—
—
NA
NA
—
—
—
—
NA
NA
—
—
—
0
—
—
NA
2.4
NA
—
—
NA
—
—
NA
—
9.6
9.766
19.23
75.76
96.15
312.5
500
+1.73
+0.16
-1.36
+0.16
+4.17
0
255
129
32
25
7
9.622
19.24
77.82
94.20
298.3
NA
+0.23
+0.23
+1.32
-1.88
-0.57
—
185
92
22
18
5
9.6
131
65
15
12
3
19.2
76.8
96
19.2
79.2
97.48
316.8
NA
0
+3.13
+1.54
+5.60
—
300
500
HIGH
LOW
4
—
—
2500
9.766
—
0
1789.8
6.991
—
0
1267
4.950
—
0
—
255
—
255
—
255
FOSC = 1 MHz
FOSC = 32.768 kHz
FOSC = 3.579 MHz
BAUD
RATE
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
KBAUD
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
NA
—
—
—
—
—
92
46
11
8
NA
1.202
2.404
9.615
19.24
83.34
NA
—
+0.16
+0.16
+0.16
+0.16
+8.51
—
—
207
103
25
12
2
0.303
1.170
NA
+1.14
-2.48
—
26
6
NA
2.4
NA
—
—
—
—
—
—
—
—
0
9.6
9.622
19.04
74.57
99.43
298.3
NA
+0.23
-0.83
-2.90
_3.57
-0.57
—
NA
—
19.2
76.8
96
NA
—
NA
—
—
NA
—
300
500
HIGH
LOW
2
NA
—
—
NA
—
—
0
NA
—
—
NA
—
894.9
3.496
—
250
—
0
8.192
0.032
—
—
255
0.976
—
255
—
255
1998 Microchip Technology Inc.
DS30289A-page 119
PIC17C7XX
TABLE 14-5: BAUD RATES FOR ASYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
0.3
1.2
NA
—
—
—
—
214
53
26
6
NA
NA
—
—
—
—
162
40
19
4
NA
—
—
255
129
32
15
3
NA
1.202
2.404
9.615
19.23
83.33
NA
—
+0.16
+0.16
+0.16
+0.16
+8.51
—
—
207
103
25
12
2
NA
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
—
2.4
2.398
9.548
19.09
73.66
103.12
257.81
515.62
-0.07
-0.54
-0.54
-4.09
+7.42
-14.06
+3.13
—
2.396
9.53
19.53
78.13
97.65
390.63
NA
0.14
-0.76
+1.73
+1.73
+1.73
+30.21
—
9.6
19.2
76.8
96
4
3
2
—
300
500
1
0
0
NA
—
—
0
—
0
—
0
NA
—
—
HIGH 515.62
LOW 2.014
0
—
—
312.5
1.221
—
250
—
0
—
255
1.53
—
255
—
255
0.977
—
255
FOSC = 7.159 MHz
FOSC = 5.068 MHz
FOSC = 10 MHz
KBAUD
BAUD
RATE
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
+3.13
0.3
1.2
NA
—
+0.16
+0.16
+1.73
+1.73
+1.73
—
—
129
64
15
7
NA
1.203
2.380
9.322
18.64
NA
—
_0.23
-0.83
-2.90
-2.90
—
—
92
46
11
5
0.31
1.2
255
65
32
7
1.202
2.404
9.766
19.53
78.13
NA
0
0
2.4
2.4
9.6
9.9
-3.13
+3.13
+3.13
—
19.2
76.8
96
19.8
79.2
NA
3
1
—
—
—
—
0
0
—
—
—
0
NA
—
—
—
—
0
300
500
HIGH
LOW
NA
—
NA
—
NA
—
NA
—
NA
—
NA
—
156.3
0.610
—
111.9
0.437
—
79.2
0.309
—
—
255
—
255
—
255
FOSC = 1 MHz
FOSC = 32.768 kHz
FOSC = 3.579 MHz
BAUD
RATE
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
KBAUD
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
0.301
1.190
2.432
9.322
18.64
NA
+0.23
-0.83
+1.32
-2.90
-2.90
—
185
46
22
5
0.300
1.202
2.232
NA
+0.16
+0.16
-6.99
—
51
12
6
0.256
NA
-14.67
—
1
—
—
—
—
—
—
—
—
0
2.4
NA
—
9.6
—
—
—
—
—
—
0
NA
—
19.2
76.8
96
2
NA
—
NA
—
—
—
—
—
0
NA
—
NA
—
NA
—
NA
—
NA
—
300
500
HIGH
LOW
NA
—
NA
—
NA
—
NA
—
NA
—
NA
—
55.93
0.218
—
15.63
0.061
—
0.512
0.002
—
—
255
—
255
—
255
DS30289A-page 120
1998 Microchip Technology Inc.
PIC17C7XX
Transmission
is
enabled
by
setting
the
14.2
USART Asynchronous Mode
TXEN (TXSTA<5>) bit.The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 14-5). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 14-6). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the TX/CK
pin will revert to hi-impedance.
In this mode, the USART uses standard nonre-
turn-to-zero (NRZ) format (one start bit, eight or nine
data bits, and one stop bit).The most common data for-
mat is 8-bits. An on-chip dedicated 8-bit baud rate gen-
erator can be used to derive standard baud rate
frequencies from the oscillator. The USART’s transmit-
ter and receiver are functionally independent but use
the same data format and baud rate. The baud rate
generator produces a clock x64 of the bit shift rate. Par-
ity is not supported by the hardware, but can be imple-
mented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
value should be written to TX9D (TXSTA<0>). The
ninth bit value must be written before writing the 8-bit
data to the TXREG. This is because a data write to
TXREG can result in an immediate transfer of the data
to the TSR (if the TSR is empty).
The asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing components:
• Baud Rate Generator
• Sampling Circuit
Steps to follow when setting up an Asynchronous
Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver
1. Initialize the SPBRG register for the appropriate
baud rate.
14.2.1 USART ASYNCHRONOUS TRANSMITTER
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
The USART transmitter block diagram is shown in
Figure 14-3.The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG).TXREG is
loaded with data in software. The TSR is not loaded
until the stop bit has been transmitted from the previous
load. As soon as the stop bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), the
TXREG is empty and an interrupt bit, TXIF, is set. This
interrupt can be enabled/disabled by setting/clearing
the TXIE bit. TXIF will be set regardless of TXIE and
cannot be reset in software. It will reset only when new
data is loaded into TXREG. While TXIF indicates the
status of the TXREG, the TRMT (TXSTA<1>) bit shows
the status of the TSR. TRMT is a read only bit which is
set when the TSR is empty. No interrupt logic is tied to
this bit, so the user has to poll this bit in order to deter-
mine if the TSR is empty.
3. If interrupts are desired, then set the TXIE bit.
4. If 9-bit transmission is desired, then set the TX9
bit.
5. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
6. Load data to the TXREG register.
7. Enable the transmission by setting TXEN (starts
transmission).
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner than doing these two events in the opposite
order.
Note: To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
Note: The TSR is not mapped in data memory,
so it is not available to the user.
1998 Microchip Technology Inc.
DS30289A-page 121
PIC17C7XX
FIGURE 14-5: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
TX
Start Bit
Bit 0
Bit 1
Word 1
Bit 7/8
(TX/CK pin)
Stop Bit
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
FIGURE 14-6: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
TX
Start Bit
Start Bit
Word 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Stop Bit
(TX/CK pin)
Word 1
TXIF bit
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
Note: This timing diagram shows two consecutive transmissions.
TABLE 14-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
16h, Bank 1
17h, Bank 1
13h, Bank 0
16h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
16h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
TMR3IF TMR2IF TMR1IF CA2IF CA1IF
TMR3IE TMR2IE TMR1IE CA2IE CA1IE
TX1IF
TX1IE
OERR
RC1IF
RC1IE
RX9D
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
TXREG1
TXSTA1
SPBRG1
PIR2
RX9
SREN
CREN
—
FERR
Serial port transmit register (USART1)
CSRC TX9 TXEN SYNC
Baud rate generator register (USART1)
—
—
TRMT
TX9D
SSPIF
SSPIE
SPEN
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
—
—
CA4IF CA3IF
CA4IE CA3IE
TX2IF
TX2IE
OERR
RC2IF
RC2IE
RX9D
PIE2
RCSTA2
TXREG2
TXSTA2
SPBRG2
CREN
—
FERR
Serial port transmit register (USART2)
CSRC TX9 TXEN SYNC
Baud rate generator register (USART2)
—
—
TRMT
TX9D
x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for asynchronous
transmission.
DS30289A-page 122
1998 Microchip Technology Inc.
PIC17C7XX
14.2.2 USART ASYNCHRONOUS RECEIVER
Note: The FERR and the 9th receive bit are buff-
ered the same way as the receive data.
Reading the RCREG register will allow the
RX9D and FERR bits to be loaded with val-
ues for the next received Received data.
Therefore, it is essential for the user to
read the RCSTA register before reading
RCREG in order not to lose the old FERR
and RX9D information.
The receiver block diagram is shown in Figure 14-4.
The data comes in the RX/DT pin and drives the data
recovery block. The data recovery block is actually a
high speed shifter operating at 16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the stop bit, the received
data in the RSR is transferred to the RCREG (if it is
empty). If the transfer is complete, the interrupt bit,
RCIF, is set. The actual interrupt can be enabled/dis-
abled by setting/clearing the RCIE bit. RCIF is a read
only bit which is cleared by the hardware. It is cleared
when RCREG has been read and is empty. RCREG is
a double buffered register; (i.e. it is a two deep FIFO).
It is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte begin
shifting to the RSR. On detection of the stop bit of the
third byte, if the RCREG is still full, then the overrun
error bit, OERR (RCSTA<1>) will be set. The word in
the RSR will be lost. RCREG can be read twice to
retrieve the two bytes in the FIFO.The OERR bit has to
be cleared in software which is done by resetting the
receive logic (CREN is set). If the OERR bit is set,
transfers from the RSR to RCREG are inhibited, so it is
essential to clear the OERR bit if it is set. The framing
error bit FERR (RCSTA<2>) is set if a stop bit is not
detected.
14.2.3 SAMPLING
The data on the RX/DT pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX/DT pin.The sampling is done
on the seventh, eighth and ninth falling edges of a x16
clock (Figure 14-7).
The x16 clock is a free running clock, and the three
sample points occur at a frequency of every 16 falling
edges.
FIGURE 14-7: RX PIN SAMPLING SCHEME
Start bit
Bit0
RX
(RX/DT pin)
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
Samples
FIGURE 14-8: START BIT DETECT
Start bit
RX
(RX/DT pin)
x16 CLK
First rising edge of x16 clock after RX pin goes low
Q2, Q4 CLK
RX sampled low
1998 Microchip Technology Inc.
DS30289A-page 123
PIC17C7XX
Steps to follow when setting up an Asynchronous
Reception:
7. Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
1. Initialize the SPBRG register for the appropriate
baud rate.
8. Read RCREG for the 8-bit received data.
9. If an overrun error occurred, clear the error by
clearing the OERR bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. Enable the reception by setting the CREN bit.
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
6. The RCIF bit will be set when reception com-
pletes and an interrupt will be generated if the
RCIE bit was set.
FIGURE 14-9: ASYNCHRONOUS RECEPTION
Start
RX
Start
bit
Start
bit
bit
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
(RX/DT pin)
Rcv shift
reg
Rcv buffer reg
Word 3
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 14-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
16h, Bank 1
17h, Bank 1
13h, Bank 0
14h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
14h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
RX2
TX1IF
TX1IE
OERR
RX1
RC1IF
RC1IE
RX9D
RX0
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
RCREG1
TXSTA1
SPBRG1
PIR2
RX9
RX6
TX9
SREN
RX5
CREN
RX4
—
RX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud rate generator register
SSPIF
SSPIE
SPEN
RX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
RX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
RX2
TX2IF
TX2IE
OERR
RX1
RC2IF
RC2IE
RX9D
RX0
PIE2
RCSTA2
RCREG2
TXSTA2
SPBRG2
CREN
RX4
SYNC
RX6
RX3
—
CSRC
TX9
TXEN
—
TRMT
TX9D
Baud rate generator register
x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for asynchronous reception.
DS30289A-page 124
1998 Microchip Technology Inc.
PIC17C7XX
tion). The TX/CK pin will remain an output if the CSRC
bit is set (internal clock). The transmitter logic is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear the TXEN
bit. If the SREN bit is set (to interrupt an ongoing trans-
mission and receive a single word), then after the single
word is received, SREN will be cleared and the serial
port will revert back to transmitting, since the TXEN bit
is still set. The DT line will immediately switch from
hi-impedance receive mode to transmit and start driv-
ing. To avoid this, TXEN should be cleared.
14.3
USART Synchronous Master Mode
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e. transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchro-
nous mode is entered by setting the SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit
is set in order to configure the I/O pins to CK (clock) and
DT (data) lines respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting the
CSRC (TXSTA<7>) bit.
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
14.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 14-3.The heart of the transmitter is the transmit
(serial) shift register (TSR).The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), TXREG
is empty and the TXIF bit is set. This interrupt can be
enabled/disabled by setting/clearing the TXIE bit. TXIF
will be set regardless of the state of bitTXIE and cannot
be cleared in software. It will reset only when new data
is loaded into TXREG. While TXIF indicates the status
of TXREG, TRMT (TXSTA<1>) shows the status of the
TSR. TRMT is a read only bit which is set when the
TSR is empty. No interrupt logic is tied to this bit, so the
user has to poll this bit in order to determine if the TSR
is empty. The TSR is not mapped in data memory, so it
is not available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
2. Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
3. Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
4. If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
5. If 9-bit transmission is desired, then set the TX9
bit.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Transmission is enabled by setting the TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The first data
bit will be shifted out on the next available rising edge
of the clock on the TX/CK pin. Data out is stable around
the falling edge of the synchronous clock
(Figure 14-11). The transmission can also be started
by first loading TXREG and then setting TXEN. This is
advantageous when slow baud rates are selected,
since BRG is kept in RESET when the TXEN, CREN,
and SREN bits are clear. Setting the TXEN bit will start
the BRG, creating a shift clock immediately. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to the TSR, resulting in an empty TXREG.
Back-to-back transfers are possible.
7. Start transmission by loading data to the
TXREG register.
8. Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner than doing these two events in the reverse
order.
Note: To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. The RX/DT and TX/CK pins will revert to hi-imped-
ance. If either CREN or SREN are set during a
transmission, the transmission is aborted and the
RX/DT pin reverts to a hi-impedance state (for a recep-
1998 Microchip Technology Inc.
DS30289A-page 125
PIC17C7XX
TABLE 14-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
16h, Bank 1
17h, Bank 1
13h, Bank 0
16h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
16h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
TX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
TX2
TX1IF
TX1IE
OERR
TX1
RC1IF
RC1IE
RX9D
TX0
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
TXREG1
TXSTA1
SPBRG1
PIR2
RX9
TX6
TX9
SREN
TX5
CREN
TX4
—
TX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud rate generator register
SSPIF
SSPIE
SPEN
TX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
TX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
TX2
TX2IF
TX2IE
OERR
TX1
RC2IF
RC2IE
RX9D
TX0
PIE2
RCSTA2
TXREG2
TXSTA2
SPBRG2
CREN
TX4
TX6
TX3
—
CSRC
TX9
TXEN
SYNC
—
TRMT
TX9D
Baud rate generator register
x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
master transmission.
FIGURE 14-10: SYNCHRONOUS TRANSMISSION
Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit1
bit2
bit0
DT
(RX/DT pin)
bit0
bit7
Word 1
Word 2
CK
(TX/CK pin)
Write to
TXREG
Write word 2
Write word 1
TXIF
Interrupt flag
TRMT
'1'
TXEN
FIGURE 14-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
DT
bit0
bit2
bit1
bit6
bit7
(RX/DT pin)
CK
(TX/CK pin)
Write to
TXREG
TXIF bit
TRMT bit
DS30289A-page 126
1998 Microchip Technology Inc.
PIC17C7XX
14.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. See Section 14.1 for details.
Once synchronous mode is selected, reception is
enabled by setting either the SREN (RCSTA<5>) bit or
the CREN (RCSTA<4>) bit. Data is sampled on the
RX/DT pin on the falling edge of the clock. If SREN is
set, then only a single word is received. If CREN is set,
the reception is continuous until CREN is reset. If both
bits are set, then CREN takes precedence. After clock-
ing the last bit, the received data in the Receive Shift
Register (RSR) is transferred to RCREG (if it is empty).
If the transfer is complete, the interrupt bit RCIF is set.
The actual interrupt can be enabled/disabled by set-
ting/clearing the RCIE bit. RCIF is a read only bit which
is RESET by the hardware. In this case it is reset when
RCREG has been read and is empty. RCREG is a dou-
ble buffered register; i.e., it is a two deep FIFO. It is pos-
sible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting into the RSR. On the clocking of the last
bit of the third byte, if RCREG is still full, then the over-
run error bit OERR (RCSTA<1>) is set.The word in the
RSR will be lost. RCREG can be read twice to retrieve
the two bytes in the FIFO. The OERR bit has to be
cleared in software. This is done by clearing the CREN
bit. If OERR is set, transfers from RSR to RCREG are
inhibited, so it is essential to clear the OERR bit if it is
set.The 9th receive bit is buffered the same way as the
receive data. Reading the RCREG register will allow
the RX9D and FERR bits to be loaded with values for
the next received data; therefore, it is essential for the
user to read the RCSTA register before reading
RCREG in order not to lose the old FERR and RX9D
information.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
6. The RCIF bit will be set when reception is com-
plete and an interrupt will be generated if the
RCIE bit was set.
7. Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
8. Read the 8-bit received data by reading
RCREG.
9. If any error occurred, clear the error by clearing
CREN.
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic so that it will
be in the proper state when receive is
re-enabled.
FIGURE 14-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
DT
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
(RX/DT pin)
CK
(TX/CK pin)
Write to the
SREN bit
SREN bit
CREN bit
'0'
'0'
RCIF bit
Read
RCREG
Note: Timing diagram demonstrates SYNC master mode with SREN = 1.
1998 Microchip Technology Inc.
DS30289A-page 127
PIC17C7XX
TABLE 14-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
16h, Bank 1
17h, Bank 1
13h, Bank 0
14h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
14h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
RX2
TX1IF
TX1IE
OERR
RX1
RC1IF
RC1IE
RX9D
RX0
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
RCREG1
TXSTA1
SPBRG1
PIR2
RX9
RX6
TX9
SREN
RX5
CREN
RX4
—
RX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud rate generator register
SSPIF
SSPIE
SPEN
RX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
RX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
RX2
TX2IF
TX2IE
OERR
RX1
RC2IF
RC2IE
RX9D
RX0
PIE2
RCSTA2
RCREG2
TXSTA2
SPBRG2
CREN
RX4
SYNC
RX6
RX3
—
CSRC
TX9
TXEN
—
TRMT
TX9D
Baud rate generator register
x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
master reception.
DS30289A-page 128
1998 Microchip Technology Inc.
PIC17C7XX
14.4.2 USART SYNCHRONOUS SLAVE
14.4
USART Synchronous Slave Mode
RECEPTION
The synchronous slave mode differs from the master
mode in the fact that the shift clock is supplied exter-
nally at the TX/CK pin (instead of being supplied inter-
nally in the master mode). This allows the device to
transfer or receive data in the SLEEP mode. The slave
mode is entered by clearing the CSRC (TXSTA<7>) bit.
Operation of the synchronous master and slave modes
are identical except in the case of the SLEEP mode.
Also, SREN is a don't care in slave mode.
If receive is enabled (CREN) prior to the SLEEPinstruc-
tion, then a word may be received during SLEEP. On
completely receiving the word, the RSR will transfer the
data to RCREG (setting RCIF) and if the RCIE bit is set,
the interrupt generated will wake the chip from SLEEP.
If the global interrupt is enabled, the program will
branch to the interrupt vector (0020h).
14.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the sync master and slave modes are
identical except in the case of the SLEEP mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to TXREG and then the SLEEP
instruction executes, the following will occur. The first
word will immediately transfer to the TSR and will trans-
mit as the shift clock is supplied. The second word will
remain in TXREG. TXIF will not be set. When the first
word has been shifted out of TSR, TXREG will transfer
the second word to the TSR and the TXIF flag will now
be set. If TXIE is enabled, the interrupt will wake the
chip from SLEEP and if the global interrupt is enabled,
then the program will branch to interrupt vector
(0020h).
1. Enable the synchronous master serial port by
setting the SYNC and SPEN bits and clearing
the CSRC bit.
2. If interrupts are desired, then set the RCIE bit.
3. If 9-bit reception is desired, then set the RX9 bit.
4. To enable reception, set the CREN bit.
5. The RCIF bit will be set when reception is com-
plete and an interrupt will be generated if the
RCIE bit was set.
Steps to follow when setting up a Synchronous Slave
Transmission:
6. Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
1. Enable the synchronous slave serial port by set-
ting the SYNC and SPEN bits and clearing the
CSRC bit.
7. Read the 8-bit received data by reading
RCREG.
8. If any error occurred, clear the error by clearing
the CREN bit.
2. Clear the CREN bit.
3. If interrupts are desired, then set the TXIE bit.
4. If 9-bit transmission is desired, then set the TX9
bit.
Note: To abort reception, either clear the SPEN
bit or the CREN bit (when in continuous
receive mode). This will reset the receive
logic, so that it will be in the proper state
when receive is re-enabled.
5. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
6. Start transmission by loading data to TXREG.
7. Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner than doing these two events in the reverse
order.
Note: To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
1998 Microchip Technology Inc.
DS30289A-page 129
PIC17C7XX
TABLE 14-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
16h, Bank 1
17h, Bank 1
13h, Bank 0
15h, Bank 0
16h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
16h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
CSRC
TX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
—
TX1IF
TX1IE
OERR
TRMT
TX1
RC1IF
RC1IE
RX9D
TX9D
TX0
x000 0010
0000 0000
0000 -00x
0000 --1x
xxxx xxxx
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
0000 --1u
uuuu uuuu
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
TXSTA1
TXREG1
SPBRG1
PIR2
RX9
TX9
TX6
SREN
TXEN
TX5
CREN
SYNC
TX4
—
—
TX3
TX2
Baud rate generator register
SSPIF
SSPIE
SPEN
TX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
TX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
TX2
TX2IF
TX2IE
OERR
TX1
RC2IF
RC2IE
RX9D
TX0
PIE2
RCSTA2
TXREG2
TXSTA2
SPBRG2
CREN
TX4
TX6
TX3
—
CSRC
TX9
TXEN
SYNC
—
TRMT
TX9D
Baud rate generator register
x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
slave transmission.
TABLE 14-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
POR,
BOR
MCLR, WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank1
17h, Bank1
13h, Bank0
14h, Bank0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
14h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
RX2
TX1IF
TX1IE
OERR
RX1
RC1IF
RC1IE
RX9D
RX0
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
RCREG1
TXSTA1
SPBRG1
PIR2
RX9
RX6
TX9
SREN
RX5
CREN
RX4
—
RX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud rate generator register
SSPIF
SSPIE
SPEN
RX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
RX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
RX2
TX2IF
TX2IE
OERR
RX1
RC2IF
RC2IE
RX9D
RX0
PIE2
RCSTA2
RCREG2
TXSTA2
SPBRG2
CREN
RX4
SYNC
RX6
RX3
—
CSRC
TX9
TXEN
—
TRMT
TX9D
Baud rate generator register
x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
slave reception.
DS30289A-page 130
1998 Microchip Technology Inc.
PIC17C7XX
2
FIGURE 15-2: I C SLAVE MODE BLOCK
DIAGRAM
15.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Internal
data bus
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Read
Write
SSPBUF reg
SSPSR reg
SCL
SDA
shift
clock
• Serial Peripheral Interface (SPI)
2
• Inter-Integrated Circuit (I C)
MSb
LSb
Figure 15-1 shows a block diagram for the SPI mode,
while Figure 15-2, and Figure 15-3 shows the block
diagrams for the two different I C modes of operation.
Addr Match
or General
Call detected
Match detect
SSPADD reg
2
FIGURE 15-1: SPI MODE BLOCK
DIAGRAM
Internal
data bus
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit detect
Read
Write
2
FIGURE 15-3: I C MASTER MODE BLOCK
DIAGRAM
SSPBUF reg
SSPSR reg
Internal
data bus
Read
Write
shift
clock
SDI
bit0
SSPADD<6:0>
7
Baud Rate Generator
SDO
SSPBUF reg
SSPSR reg
SCL
Control
Enable
SS
shift
clock
SS
Edge
Select
SDA
MSb
LSb
2
Clock Select
Addr Match
or General
Call detected
Match detect
SSPADD reg
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 output
2
Edge
Select
Set/Clear S bit
and
Clear/Set P, bit
(SSPSTAT reg)
Start and Stop bit
detect / generate
TOSC
Prescaler
4, 16, 64
SCK
and Set SSPIF
Data to TX/RX in SSPSR
Data direction bit
1998 Microchip Technology Inc.
DS30289A-page 131
PIC17C7XX
FIGURE 15-4: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6)
R/W-0 R/W-0
SMP CKE
bit7
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
bit0
- n = Value at POR reset
bit 7:
SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
2
In I C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6:
CKE: SPI Clock Edge Select (Figure 15-9, Figure 15-11, and Figure 15-12)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
2
bit 5:
bit 4:
D/A: Data/Address bit (I C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
bit 2:
S: Start bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
2
R/W: Read/Write bit information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to
the next start bit, stop bit, or not ACK bit.
2
In I C slave mode:
1 = Read
0 = Write
2
In I C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
2
bit 1:
bit 0:
UA: Update Address (10-bit I C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
2
Transmit (I C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
DS30289A-page 132
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 15-5: SSPCON1: SYNC SERIAL PORT CONTROL REGISTER1 (ADDRESS 11h, BANK 6)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit, read
as ‘0’
- n = Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
Master Mode:
2
1 = A write to the SSPBUF register was attempted while the I C conditions were not valid for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data
in SSPSR is lost. Overflow can only occur in slave mode. In slave mode the user must read the SSPBUF, even if
only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new recep-
tion (and transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software).
0 = No overflow
2
In I C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit
mode. (Must be cleared in software).
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
2
In I C mode
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: In SPI mode, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
2
In I C slave mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
2
In I C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI master mode, clock = FOSC/4
0001= SPI master mode, clock = FOSC/16
0010= SPI master mode, clock = FOSC/64
0011= SPI master mode, clock = TMR2 output/2
0100= SPI slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
2
0110= I C slave mode, 7-bit address
2
0111= I C slave mode, 10-bit address
2
1000= I C master mode, clock = FOSC / (4 * (SSPADD+1) )
1xx1= Reserved
1x1x= Reserved
1998 Microchip Technology Inc.
DS30289A-page 133
PIC17C7XX
FIGURE 15-6: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit, Read
as ‘0’
- n = Value at POR reset
2
bit 7:
bit 6:
GCEN: General Call Enable bit (In I C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
2
ACKSTAT: Acknowledge Status bit (In I C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
2
bit 5:
bit 4:
ACKDT: Acknowledge Data bit (In I C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
2
ACKEN: Acknowledge Sequence Enable bit (In I C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically cleared by hard-
ware.
0 = Acknowledge sequence idle
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
2
bit 3:
RCEN: Receive Enable bit (In I C master mode only).
2
1 = Enables Receive mode for I C
0 = Receive idle
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
2
bit 2:
PEN: Stop Condition Enable bit (In I C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
2
bit 1: RSEN: Repeated Start Condition Enabled bit (In I C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled)
2
bit 0: SEN: Start Condition Enabled bit (In I C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
DS30289A-page 134
1998 Microchip Technology Inc.
PIC17C7XX
15.1
SPI Mode
FIGURE 15-7: MSSP BLOCK DIAGRAM
(SPI MODE)
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish com-
munication, typically three pins are used:
Internal
data bus
Read
Write
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
SSPBUF reg
SSPSR reg
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
shift
clock
SDI
bit0
15.1.1 OPERATION
SDO
When initializing the SPI, several options need to be
specified.This is done by programming the appropriate
control
bits
in
the
SSPCON1
register
Control
Enable
SS
(SSPCON1<5:0>) and SSPSTAT<7:6>. These control
bits allow the following to be specified:
SS
Edge
Select
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase
2
Clock Select
(middle or end of data output time)
• Clock edge
(output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 output
2
Edge
Select
TOSC
Prescaler
4, 16, 64
SCK
Figure 15-7 shows the block diagram of the MSSP
module when in SPI mode.
Data to TX/RX in SSPSR
Data direction bit
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and BUFfer register (SSPBUF). The
a
SSPSR shifts the data in and out of the device, MSb
first.The SSPBUF holds the data that was written to the
SSPSR, until the received data is ready. Once the
8-bits of data have been received, that byte is moved to
the SSPBUF register. Then the buffer full detect bit BF
(SSPSTAT<0>) and the interrupt flag bit SSPIF
(PIR2<7>) are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON1<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSP-
BUF register completed successfully.
1998 Microchip Technology Inc.
DS30289A-page 135
PIC17C7XX
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has com-
pleted.The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 15-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
15.1.2 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>) must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
registers, and then set bit SSPEN. This configures the
SDI, SDO, SCK, and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the DDR register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have DDRB<7> cleared
• SCK (Master mode) must have DDRB<6> cleared
• SCK (Slave mode) must have DDRB<6> set
• SS must have PORTA<2> set
EXAMPLE 15-1: LOADING THE SSPBUF
(SSPSR) REGISTER
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (DDR) register to the opposite value.
MOVLB 6
; Bank 6
LOOP BTFSS SSPSTAT, BF
; Has data been
;
;
;
received
(transmit
complete)?
15.1.3 TYPICAL CONNECTION
Figure 15-8 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
GOTO LOOP
MOVPF SSPBUF, RXDATA ; Save in user RAM
MOVFP TXDATA, SSPBUF ; New data to xmit
; No
The SSPSR is not directly readable or writable, and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP status register (SSPSTAT) indi-
cates the various status conditions.
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
FIGURE 15-8: SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
Shift Register
(SSPSR)
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
DS30289A-page 136
1998 Microchip Technology Inc.
PIC17C7XX
15.1.4 MASTER MODE
MSb is transmitted first. In master mode, the SPI clock
rate (bit rate) is user programmable to be one of the fol-
lowing:
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 15-8) is to broad-
cast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
This allows a maximum bit clock frequency (at 33 MHz)
of 8.25 MHz.
Figure 15-9 shows the waveforms for master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON1<4>). This then would give
waveforms for SPI communication as shown in
Figure 15-9, Figure 15-11, and Figure 15-12 where the
FIGURE 15-9: SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 clock
modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit6
bit6
bit2
bit2
bit5
bit5
bit4
bit4
bit1
bit1
bit0
bit0
SDO
(CKE = 0)
bit7
bit7
bit3
bit3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
1998 Microchip Technology Inc.
DS30289A-page 137
PIC17C7XX
15.1.5 SLAVE MODE
floating output. External pull-up/ pull-down resistors
may be desirable, depending on the application.
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR2<7>)
is set.
Note: When the SPI is in Slave Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
While in slave mode the external clock is supplied by
the external clock source on the SCK pin.This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
Note: If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level or clearing the SSPEN bit.
While in sleep mode, the slave can transmit/receive
data. When a byte is received the device will wake-up
from sleep.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
15.1.6 SLAVE SELECT SYNCHRONIZATION
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The RA2 Data Latch must be high. When the SS pin
is low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the
middle of
a transmitted byte, and becomes a
FIGURE 15-10: SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit7
bit7
bit0
bit0
SDO
bit7
SDI
(SMP = 0)
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
DS30289A-page 138
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 15-11: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit3
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 15-12: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
bit0
SDO
bit7
bit7
bit3
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
1998 Microchip Technology Inc.
DS30289A-page 139
PIC17C7XX
15.1.7 SLEEP OPERATION
15.1.8 EFFECTS OF A RESET
In master mode all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from sleep. After the device returns to
normal mode, the module will continue to trans-
mit/receive data.
A reset disables the MSSP module and terminates the
current transfer.
In slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in sleep mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP interrupt
flag bit will be set and if enabled will wake the device
from sleep.
TABLE 15-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR MCLR, WDT
07h,
INTSTA
PEIF T0CKIF
T0IF
INTF
PEIE T0CKIE
T0IE
INTE 0000 0000 0000 0000
Unbanked
10h, Bank 4 PIR2
11h, Bank 4 PIE2
14h, Bank 6 SSPBUF
SSPIF BCLIF
SSPIE BCLIE
ADIF
ADIE
—
—
CA4IF CA3IF
CA4IE CA3IE
TX2IF
TX2IE
RC2IF
RC2IE
000- 0010 000- 0010
000- 0000 000- 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
11h, Bank 6 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
13h, Bank 6 SSPSTAT SMP CKE D/A R/W UA BF
P
S
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
DS30289A-page 140
1998 Microchip Technology Inc.
PIC17C7XX
2
2
15.2
MSSP I C Operation
FIGURE 15-14: I C MASTER MODE BLOCK
DIAGRAM
2
The MSSP module in I C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit address-
Internal
data bus
Read
Write
SSPADD<6:0>
7
2
ing. Appendix E: gives an overview of the I C bus spec-
Baud Rate Generator
ification.
SSPBUF reg
SSPSR reg
Refer to Application Note AN578, "Use of the SSP
Module in the I C Multi-Master Environment."
SCL
2
shift
clock
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independant of device frequency.
SDA
MSb
LSb
Addr Match
Match detect
SSPADD reg
2
FIGURE 15-13: I C SLAVE MODE BLOCK
DIAGRAM
Internal
data bus
Set/Clear S bit
and
Read
Write
Start and Stop bit
detect / generate
Clear/Set P, bit
(SSPSTAT reg)
SSPBUF reg
SSPSR reg
SCL
SDA
and Set SSPIF
shift
clock
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins that are automatically
MSb
LSb
2
configured when the I C mode is enabled. The SSP
module functions are enabled by setting SSP Enable
bit SSPEN (SSPCON1<5>).
Addr Match
Match detect
SSPADD reg
2
The MSSP module has six registers for I C operation.
These are the:
• SSP Control Register1 (SSPCON1)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit detect
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
2
The SSPCON1 register allows control of the I C oper-
ation. Four mode selection bits (SSPCON1<3:0>) allow
2
one of the following I C modes to be selected:
2
• I C Slave mode (7-bit address)
2
• I C Slave mode (10-bit address)
2
• I C Master mode, clock = OSC/4 (SSPADD +1)
2
Before selecting any I C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
2
ate DDR bits. Selecting an I C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
2
as the clock and data lines in I C mode.
1998 Microchip Technology Inc.
DS30289A-page 141
PIC17C7XX
The SSPSTAT register gives the status of the data
15.2.1 SLAVE MODE
transfer. This information includes detection of
a
In slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data when required
(slave-transmitter).
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer.
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create
a doubled buffered
receiver.This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON1<6>) is set and the byte in the
SSPSR is lost.
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overflow bit SSPOV (SSPCON1<6>) was
set before the transfer was received.
The SSPADD register holds the slave address. In 10-bit
mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF, but bit SSPIF and SSPOV are
set. Table 15-2 shows what happens when a data
transfer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
2
of the I C specification as well as the requirement of the
MSSP module is shown in timing parameter #100 and
parameter #101 of the Electrical Specifications.
DS30289A-page 142
1998 Microchip Technology Inc.
PIC17C7XX
15.2.1.1 ADDRESSING
5. Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
a) The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
Note: Following the Repeated Start condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
b) The buffer full bit, BF is set on the falling edge of
the 8th SCL pulse.
c) An ACK pulse is generated.
15.2.1.2 SLAVE RECEPTION
d) SSP interrupt flag bit, SSPIF (PIR2<7>) is set
(interrupt is generated if enabled) - on the falling
edge of the 9th SCL pulse.
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7- 9 for slave-transmit-
ter:
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON1<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR2<7>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occured.The ACK is not sent and the SSP-
BUF is updated.
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
TABLE 15-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Generate ACK
Pulse
BF
SSPOV
SSPSR → SSPBUF
0
1
1
0
0
0
1
1
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
1998 Microchip Technology Inc.
DS30289A-page 143
PIC17C7XX
15.2.1.3
SLAVE TRANSMISSION
As a slave-transmitter, the ACK pulse from the mas-
ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the not ACK
is latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then the SCL pin
should be enabled by setting the CKP bit.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCLpin is held low.The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then SCL pin
should be enabled by setting bit CKP (SSPCON1<4>).
The master must monitor the SCL pin prior to asserting
another clock pulse. The slave devices may be holding
off the master by stretching the clock. The eight data
bits are shifted out on the falling edge of the SCL input.
This ensures that the SDA signal is valid during the
SCL high time (Figure 15-16).
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
and the SSPSTAT register is used to determine the sta-
tus of the byte tranfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
2
FIGURE 15-15: I C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W=0
ACK
Not
Receiving Address
A7 A6 A5 A4
Receiving Data
Receiving Data
ACK
ACK
SDA
A3 A2 A1
D5
D2
6
D0
8
D5
D2
D0
8
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
3
9
7
1
2
4
9
5
4
3
6
9
5
1
2
3
6
1
2
4
8
5
P
SCL
S
SSPIF
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON1<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
2
FIGURE 15-16: I C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
Transmitting Data Not ACK
D7 D6 D5 D4 D3 D2 D1 D0
R/W = 1
Receiving Address
ACK
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
SSPIF
BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON1<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
DS30289A-page 144
1998 Microchip Technology Inc.
PIC17C7XX
2
FIGURE 15-17: I C SLAVE-TRANSMITTER (10-BIT ADDRESS)
1998 Microchip Technology Inc.
DS30289A-page 145
PIC17C7XX
2
FIGURE 15-18: I C SLAVE-RECEIVER (10-BIT ADDRESS)
DS30289A-page 146
1998 Microchip Technology Inc.
PIC17C7XX
15.2.2 GENERAL CALL ADDRESS SUPPORT
If the general call address matches, the SSPSR is
transfered to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit)
the SSPIF flag is set.
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
acknowledge.
When the interrupt is serviced. The source for the
interrupt can be checked by reading the contents of
the SSPBUF to determine if the address was device
specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the
UA bit is set (SSPSTAT<1>). If the general call
address is sampled when GCEN is set while the slave
is configured in 10-bit address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
acknowledge (Figure 15-19).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a start-bit detect, 8-bits are shifted
into SSPSR and the address is compared against
SSPADD, and is also compared to the general call
address, fixed in hardware.
FIGURE 15-19: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving data
D5 D4 D3 D2 D1
ACK
9
R/W = 0
ACK
General Call Address
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
'0'
'1'
1998 Microchip Technology Inc.
DS30289A-page 147
PIC17C7XX
15.2.3 SLEEP OPERATION
15.2.4 EFFECTS OF A RESET
2
While in sleep mode, the I C module can receive
A reset diables the SSP module and terminates the
current transfer.
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep (if the SSP interrupt is enabled).
2
TABLE 15-3: REGISTERS ASSOCIATED WITH I C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR MCLR, WDT
07h, Unbanked INTSTA
PEIF
T0CKIF
BCLIF
T0IF
INTF
—
PEIE
T0CKIE
CA3IF
T0IE
INTE
0000 0000
000- 0000
0000 0000
000- 0000
10h, Bank 4
11h, Bank 4
PIR2
PIE2
SSPIF
ADIF
CA4IF
TX2IF
RC2IF
SSPIE
BCLIE
ADIE
—
CA4IE
CA3IE
TX2IE
RC2IE
000- 0000
0000 0000
000- 0000
0000 0000
Synchronous Serial Port (I2C mode) Address Register
Synchronous Serial Port Receive Buffer/Transmit Register
SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
GCEN ACKSTAT ACKDT ACKEN
SMP CKE D/A
10h. Bank 6
14h, Bank 6
SSPADD
SSPBUF
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
11h, Bank 6
12h, Bank 6
13h, Bank 6
Legend:
SSPCON1 WCOL
SSPCON2
SSPSTAT
RCEN
S
PEN
R/W
RSEN
UA
SEN
BF
P
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
DS30289A-page 148
1998 Microchip Technology Inc.
PIC17C7XX
15.2.5 MASTER MODE
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abled. Control of the I C bus may be taken when the P
bit is set, or the bus is idle with both the S and P bits
clear.
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
2
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
2
FIGURE 15-20: SSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
data bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
rate
generator
SDA
shift
clock
SDA in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit detect,
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
SCL in
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
1998 Microchip Technology Inc.
DS30289A-page 149
PIC17C7XX
2
15.2.6 MULTI-MASTER MODE
15.2.7.1 I C MASTER MODE OPERATION
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
Start condition. Since the Repeated Start condition is
2
2
when the MSSP module is disabled. Control of the I C
also the beginning of the next serial transfer, the I C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
bus will not be released.
In Master Transmitter mode serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device, (7 bits) and the Read/Write (R/W) bit.
In this case the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In multi-master operation, the SDA line must be moni-
tored, for abitration, to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
In Master receive mode the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case the R/W bit will be
logic '1'. Thus the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
2
15.2.7 I C MASTER MODE SUPPORT
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting
the SSPEN bit. Once master mode is enabled, the
user has six options.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
-
-
Assert a start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
2
100 kHz, 400 kHz, or 1 MHz I C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the
SSPBUF. Once the given operation is complete (i.e.
transmission of the last data bit is followed by ACK) the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
-
Write to the SSPBUF register initiating trans-
mission of data/address.
-
-
-
Generate a stop condition on SDA and SCL.
Configure the I C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
2
2
Note: The MSSP Module when configured in I C
Master Mode does not allow queueing of
events. For instance: The user is not
allowed to initiate a start condition, and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case the
SSPBUF will not be written to, and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
DS30289A-page 150
1998 Microchip Technology Inc.
PIC17C7XX
A typical transmit sequence would go as follows:
15.2.8 BAUD RATE GENERATOR
a) The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
2
In I C master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 15-21). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY), on the
Q2 and Q4 clock.
b) SSPIF is set. The module will wait the required
start time before any other operation takes
place.
c) The user loads the SSPBUF with address to
transmit.
d) Address is shifted out the SDA pin until all 8 bits
are transmitted.
In I2C master mode, the BRG is reloaded automati-
cally. If Clock Arbitration is taking place for instance,
the BRG will be reloaded when the SCL pin is sampled
high (Figure 15-22).
e) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
FIGURE 15-21: BAUD RATE GENERATOR
BLOCK DIAGRAM
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g) The user loads the SSPBUF with eight bits of
data.
SSPM3:SSPM0
SSPADD<6:0>
h) DATA is shifted out the SDA pin until all 8 bits
are transmitted.
SSPM3:SSPM0
SCL
Reload
Control
Reload
i) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
Fosc/4
BRG Down Counter
CLKOUT
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
k) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
l) Interrupt is generated once the STOP condition
is complete.
FIGURE 15-22: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements
(on Q2 and Q4 cycles)
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
reload
1998 Microchip Technology Inc.
DS30289A-page 151
PIC17C7XX
2
15.2.9 I C MASTER MODE START CONDITION
15.2.9.1 WCOL STATUS FLAG
TIMING
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
To initiate a START condition the user sets the start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is re-loaded with the contents of SSPADD<6:0>,
and starts its count. If SCL and SDA are both sampled
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
high when the baud rate generator times out (T
),
BRG
the SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (T
) the
BRG
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended
leaving the SDA line held low, and the START condition
is complete.
Note: If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag (BCLIF) is set,
the START condition is aborted, and the
2
I C module is reset into its IDLE state.
FIGURE 15-23: FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here.
SDA = 1,
At completion of start bit,
Hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
2nd Bit
1st Bit
TBRG
SDA
SCL
TBRG
S
DS30289A-page 152
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 15-24: START CONDITION FLOWCHART
SSPEN = 1,
SSPCON1<3:0> = 1000
Idle Mode
SEN (SSPCON2<0> = 1)
Bus collision detected,
Set BCLIF,
No
SDA = 1?
Release SCL,
Clear SEN
SCL = 1?
Yes
Load BRG with
SSPADD<6:0>
No
No
Yes
No
BRG
Rollover?
SCL= 0?
SDA = 0?
Yes
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>,
Set S bit.
BRG
rollover?
No
No
SCL = 0?
Yes
Yes
Reset BRG
Force SCL = 0,
Start Condition Done,
Clear SEN
and set SSPIF
1998 Microchip Technology Inc.
DS30289A-page 153
PIC17C7XX
2
15.2.10 I C MASTER MODE REPEATED START
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I C mod-
2
ule is in the idle state. When the RSEN bit is set, the
SCL pin is asserted low. When the SCL pin is sam-
pled low, the baud rate generator is loaded with the
contents of SSPADD<6:0>, and begins counting. The
SDA pin is released (brought high) for one baud rate
15.2.10.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
generator count (T
). When the baud rate generator
BRG
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high the baud rate generator is re-loaded with the con-
tents of SSPADD<6:0> and begins counting. SDA
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
and SCL must be sampled high for one T
.
This
action is then followed by assertion of the SDA pin
(SDA is low) for one T while SCL is high. Follow-
BRG
BRG
ing this, the RSEN bit in the SSPCON2 register will be
automatically cleared, and the baud rate generator is
not reloaded, leaving the SDA pin held low. As soon
as a start condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. The SSPIF
bit will not be set until the baud rate generator has
timed-out.
Note 1: If the RSEN is programmed while any
other event is in progress, it will not take
effect.
Note 2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 15-25: REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
occurs here.
At completion of start bit,
hardware clear RSEN bit
and set SSPIF
SCL = 1
SDA = 1,
SCL(no change)
TBRG
TBRG
TBRG
1st Bit
SDA
Write to SSPBUF occurs here.
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated Start
DS30289A-page 154
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 15-26: REPEATED START CONDITION FLOWCHART (PAGE 1)
Start
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
B
RSEN = 1
Force SCL = 0
No
SCL = 0?
Yes
Release SDA,
Load BRG with
SSPADD<6:0>
No
BRG
rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
Bus Collision,
Set BCLIF,
Release SDA,
Clear RSEN
No
SDA = 1?
Yes
Load BRG with
SSPADD<6:0>
C
A
1998 Microchip Technology Inc.
DS30289A-page 155
PIC17C7XX
FIGURE 15-27: REPEATED START CONDITION FLOWCHART (PAGE 2)
B
C
A
Yes
No
No
No
BRG
rollover?
SDA = 0?
SCL = 1?
Yes
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>
Set S
No
No
BRG
rollover?
SCL = '0'?
Yes
Yes
Force SCL = 0,
Reset BRG
Repeated Start
condition done,
Clear RSEN,
Set SSPIF.
DS30289A-page 156
1998 Microchip Technology Inc.
PIC17C7XX
2
15.2.11 I C MASTER MODE TRANSMISSION
15.2.11.1 BF STATUS FLAG
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit address is accomplished by simply writ-
ing a value to SSPBUF register. This action will set
the buffer full flag (BF) and allow the baud rate genera-
tor to begin counting and start the next transmission.
Each bit of address/data will be shifted out onto the
SDA pin after the falling edge of SCL is asserted (see
data hold time spec). SCL is held low for one baud
In transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
15.2.11.2 WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
rate generator roll over count (T
). Data should be
BRG
valid before SCL is released high (see Data setup time
spec). When the SCL pin is released high, it is held
WCOL must be cleared in software.
15.2.11.3 AKSTAT STATUS FLAG
that way for T
,
the data on the SDA pin must
BRG
remain stable for that duration and some hold time
after the next falling edge of SCL. After the eighth bit
is shifted out (the falling edge of the eighth clock), the
BF flag is cleared and the master releases SDA allow-
ing the slave device being addressed to respond with
an ACK bit during the ninth bit time, if an address
match occurs or if data was received properly. The
status of ACK is read into the ACKDT on the falling
edge of the ninth clock. If the master receives an
acknowledge, the acknowledge status bit (AKSTAT) is
cleared. If not, the bit is set. After the ninth clock the
SSPIF is set, and the master clock (baud rate genera-
tor) is suspended until the next data byte is loaded into
the SSPBUF leaving SCL low and SDA unchanged.
(Figure 15-29)
In transmit mode, the AKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0), and is set when the slave does not
acknowledge (ACK = 1). A slave sends an acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock the master will de-assert
the SDA pin allowing the slave to respond with an
acknowledge. On the falling edge of the ninth clock the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared, and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
1998 Microchip Technology Inc.
DS30289A-page 157
PIC17C7XX
FIGURE 15-28: MASTER TRANSMIT FLOWCHART
Idle Mode
Write SSPBUF
Num_Clocks = 0,
BF = 1
Force SCL = 0
Release SDA so
slave can drive ACK,
Force BF = 0
Yes
Num_Clocks
= 8?
No
Load BRG with
SSPADD<6:0>,
start BRG count
Load BRG with
SSPADD<6:0>,
start BRG count,
SDA = Current Data bit
No
BRG
rollover?
BRG
No
rollover?
Yes
Yes
Force SCL = 1,
Stop BRG
Stop BRG,
Force SCL = 1
(Clock Arbitration)
No
(Clock Arbitration)
SCL = 1?
Yes
No
SCL = 1?
Yes
Read SDA and place into
ACKSTAT bit (SSPCON2<6>)
Bus collision detected
No
SDA =
Data bit?
Set BCLIF, hold prescale off,
Clear XMIT enable
Load BRG with
SSPADD<6:0>,
count high time
Yes
Load BRG with
SSPADD<6:0>,
count SCL high time
No
Rollover?
Yes
No
No
No
SDA =
Data bit?
BRG
rollover?
Yes
SCL = 0?
Force SCL = 0,
Set SSPIF
Yes
Yes
Reset BRG
Num_Clocks
= Num_Clocks + 1
DS30289A-page 158
1998 Microchip Technology Inc.
PIC17C7XX
2
FIGURE 15-29: I C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
1998 Microchip Technology Inc.
DS30289A-page 159
PIC17C7XX
2
15.2.12 I C MASTER MODE RECEPTION
15.2.12.1 BF STATUS FLAG
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
In receive operation, BF is set when an address or
data byte is loaded into SSPBUF from SSPSR. It is
cleared when SSPBUF is read.
Note: The SSP Module must be in an IDLE
STATE before the RCEN bit is set, or the
RCEN bit will be disregarded.
15.2.12.2 SSPOV STATUS FLAG
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already
set from a previous reception.
The baud rate generator begins counting, and on
each rollover, the state of the SCL pin changes (high
to low/low to high), and data is shifted into the SSPSR.
After the falling edge of the eighth clock, the receive
enable flag is automatically cleared, the contents of
the SSPSR are loaded into the SSPBUF, the BF flag is
set, the SSPIF is set, and the baud rate generator is
suspended from counting, holding SCL low. The SSP
is now in IDLE state, awaiting the next command.
When the buffer is read by the CPU, the BF flag is
automatically cleared. The user can then send an
acknowledge bit at the end of reception, by setting the
15.2.12.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e. SSPSR is still shifting in a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>).
DS30289A-page 160
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 15-30: MASTER RECEIVER FLOWCHART
Idle mode
RCEN = 1
Num_Clocks = 0,
Release SDA
Force SCL=0,
Load BRG w/
SSPADD<6:0>,
start count
BRG
No
rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
Sample SDA,
Shift data into SSPSR
Load BRG with
SSPADD<6:0>,
start count.
No
No
BRG
SCL = 0?
Yes
rollover?
Yes
Num_Clocks
= Num_Clocks + 1
No
Num_Clocks
= 8?
Yes
Force SCL = 0,
Set SSPIF,
Set BF.
Move contents of SSPSR
into SSPBUF,
Clear RCEN.
1998 Microchip Technology Inc.
DS30289A-page 161
PIC17C7XX
2
FIGURE 15-31: I C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
DS30289A-page 162
1998 Microchip Technology Inc.
PIC17C7XX
15.2.13 ACKNOWLEDGE SEQUENCE TIMING
15.2.13.1 WCOL STATUS FLAG
An acknowledge sequence is enabled by setting the
If the user writes the SSPBUF when an acknowledege
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data
bit is presented on the SDA pin. If the user wishes to
generate an acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(T
), and the SCL pin is de-asserted (pulled high).
BRG
When the SCL pin is sampled high (clock arbitration),
the baud rate generator counts for T . The SCL pin
BRG
is then pulled low. Following this, the ACKEN bit is
automatically cleared, the baud rate generator is
turned off, and the SSP module then goes into IDLE
mode. (Figure 15-32)
FIGURE 15-32: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of acknowledge sequence
Note: TBRG= one baud rate generator period.
1998 Microchip Technology Inc.
DS30289A-page 163
PIC17C7XX
FIGURE 15-33: ACKNOWLEDGE FLOWCHART
Idle mode
Set ACKEN
Force SCL = 0
BRG
Yes
rollover?
No
No
SCL = 0?
Yes
Force SCL = 0,
Clear ACKEN
Set SSPIF
Yes
SCL = 0?
No
Reset BRG
Drive ACKDT bit
(SSPCON2<5>)
onto SDA pin,
Load BRG with
SSPADD<6:0>,
start count.
No
ACKDT = 1?
Yes
No
BRG
rollover?
Yes
SDA = 1?
No
Yes
Force SCL = 1
Bus collision detected,
Set BCLIF,
Release SCL,
Clear ACKEN
No
SCL = 1?
Yes
(Clock Arbitration)
Load BRG with
SSPADD <6:0>,
start count.
DS30289A-page 164
1998 Microchip Technology Inc.
PIC17C7XX
15.2.14 STOP CONDITION TIMING
15.2.14.1 WCOL STATUS FLAG
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/trans-
mit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator
times out, the SCL pin will be brought high, and one
If the user writes the SSPBUF when
a STOP
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
T
(baud rate generator rollover count) later, the
BRG
SDA pin will be de-asserted. When the SDA pin is
sampled high while SCL is high, the P bit (SSP-
STAT<4>) is set. A TBRG later the PEN bit is cleared
and the SSPIF bit is set. (Figure 15-34)
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e. bus is free).
FIGURE 15-34: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup stop condition.
Note: TBRG = one baud rate generator period.
1998 Microchip Technology Inc.
DS30289A-page 165
PIC17C7XX
FIGURE 15-35: STOP CONDITION FLOWCHART
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
PEN = 1
Start BRG
Force SDA = 0
SCL doesn’t change
No
BRG
rollover?
Yes
No
SDA = 0?
Release SDA,
Start BRG
Yes
Start BRG
No
BRG
rollover?
No
BRG
Yes
rollover?
Bus Collision detected,
Set BCLIF,
No
Yes
P bit Set?
Yes
Clear PEN
De-assert SCL,
SCL = 1
SDA going from
0 to 1 while SCL = 1
(Clock Arbitration)
Set SSPIF,
No
Stop Condition done
PEN cleared.
SCL = 1?
Yes
DS30289A-page 166
1998 Microchip Technology Inc.
PIC17C7XX
15.2.15 CLOCK ARBITRATION
15.2.16 SLEEP OPERATION
2
Clock arbitration occurs when the master during any
receive, transmit, or repeated start/stop condition
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud
rate generator (BRG) is suspended from counting until
the SCL pin is actually sampled high. When the SCL
pin is sampled high, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device.
(Figure 15-36)
While in sleep mode, the I C module can receive
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep ( if the SSP interrupt is enabled).
15.2.17 EFFECTS OF A RESET
A reset disables the SSP module and terminates the
current transfer.
FIGURE 15-36: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL
SDA
SCL line sampled once every machine cycle (T • 4).
Hold off BRG until SCL is sampled high.
osc
TBRG
TBRG
TBRG
1998 Microchip Technology Inc.
DS30289A-page 167
PIC17C7XX
15.2.18 MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I2C bus is free, the user can resume communica-
tion by asserting a START condition.
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
2
the I C port to its IDLE state. (Figure 15-37).
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user ser-
vices the bus collision interrupt service routine, and if
In multi-master mode, the interrupt generation on the
detection of start and stop conditions allows the deter-
2
mination of when the bus is free. Control of the I C
2
the I C bus is free, the user can resume communica-
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
tion by asserting a START condition.
FIGURE 15-37: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt.
BCLIF
DS30289A-page 168
1998 Microchip Technology Inc.
PIC17C7XX
15.2.18.1 BUS COLLISION DURING A START
CONDITION
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-40). If however a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
is sampled as '0', a bus collision does not occur. At
the end of the BRG count the SCL pin is asserted low.
During a START condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 15-38)
b) SCL is sampled low before SDA is asserted low.
(Figure 15-39)
During a START condition both the SDA and the SCL
pins are monitored.
Note: The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition, and if the
address is the same, arbitration must be
allowed to continue into the data portion,
REPEATED START, or STOP conditions.
If:
the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 15-38).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 15-38: BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1
SDA
SCL
Set SEN, enable start
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into idle state.
SEN
SDA sampled low before
START condition.
Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1
BCLIF
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
1998 Microchip Technology Inc.
DS30289A-page 169
PIC17C7XX
FIGURE 15-39: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
SEN
Set SEN, enable start
sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF.
SCL = 0 before BRG time out,
Bus collision occurs, Set BCLIF.
BCLIF
Interrupts cleared
in software.
S
'0'
'0'
'0'
'0'
SSPIF
FIGURE 15-40: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S
TBRG
Set SSPIF
Less than TBRG
SDA pulled low by other master.
Reset BRG and assert SDA
SDA
SCL
S
SCL pulled low after BRG
Timeout
SEN
Set SEN, enable start
sequence if SDA = 1, SCL = 1
'0'
BCLIF
S
SSPIF
Interrupts cleared
in software.
SDA = 0, SCL = 1
Set SSPIF
DS30289A-page 170
1998 Microchip Technology Inc.
PIC17C7XX
15.2.18.2 BUS COLLISION DURING A REPEATED
START CONDITION
’0’). If however SDA is sampled high then the BRG is
reloaded and begins counting. If SDA goes from high
to low before the BRG times out, no bus collision
occurs, because no two masters can assert SDA at
exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted,
then a bus collision occurs. In this case, another mas-
ter is attempting to transmit a data ’1’ during the
Repeated Start condition.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>,
and counts down to 0. The SCL pin is then
de-asserted, and when sampled high, the SDA pin is
sampled. If SDA is low, a bus collision has occurred
(i.e. another master is attempting to transmit a data
If at the end of the BRG time out both SCL and SDA
are still high, the SDA pin is driven low, the BRG is
reloaded, and begins counting. At the end of the
count, regardless of the status of the SCL pin, the SCL
pin is driven low and the Repeated Start condition is
complete. (Figure 15-41)
FIGURE 15-41: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
RSEN
BCLIF
Cleared in software
'0'
'0'
'0'
S
'0'
SSPIF
FIGURE 15-42: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
BCLIF
RSEN
Set BCLIF. Release SDA and SCL
Interrupt cleared
in software
'0'
'0'
'0'
'0'
S
SSPIF
1998 Microchip Technology Inc.
DS30289A-page 171
PIC17C7XX
15.2.18.3 BUS COLLISION DURING A STOP
CONDITION
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allow to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0'. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs.
This is another case of another master attempting to
drive a data '0'. (Figure 15-43)
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
FIGURE 15-43: BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
Set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
'0'
'0'
'0'
'0'
SSPIF
FIGURE 15-44: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high
Set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
'0'
'0'
'0'
'0'
SSPIF
DS30289A-page 172
1998 Microchip Technology Inc.
PIC17C7XX
2
The bus capacitance is the total capacitance of wire,
connections, and pins.This capacitance limits the max-
15.3
Connection Considerations for I C
Bus
imum value of R due to the specified rise time
p
2
For standard-mode I C bus devices, the values of
(Figure 15-45).
resistors R R in Figure 15-45 depends on the follow-
ing parameters
p
s
The SMP bit is the slew rate control enabled bit.This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I C mode (master or slave).
2
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
leakage current).
The supply voltage limits the minimum value of resistor
R
due to the specified minimum sink current of 3 mA
p
at VOL max = 0.4V for the specified output stages. For
example, with a supply voltage of VDD = 5V+10% and
VOL max = 0.4V at 3 mA, R
= (5.5-0.4)/0.003 =
p min
1.7 kΩ. VDD as
a
function of
R
is shown in
p
Figure 15-45. The desired noise margin of 0.1VDD for
the low level, limits the maximum value of R . Series
s
resistors are optional and used to improve ESD sus-
ceptibility.
2
FIGURE 15-45: SAMPLE DEVICE CONFIGURATION FOR I C BUS
VDD + 10%
DEVICE
R
R
p
p
R
R
s
s
SDA
SCL
C =10 - 400 pF
2
b
NOTE: I C devices with input levels related to VDD must have one common supply
line to which the pull up resistor is also connected.
1998 Microchip Technology Inc.
DS30289A-page 173
PIC17C7XX
15.4
Example Program
Example 15-2 shows MPLAB-C17 ’C’ code for using
2
the I C module in master mode to communicate with a
24LC01B serial EEPROM. This example uses the
PICmicro ’C’ libraries included with MPLAB-C17.
EXAMPLE 15-2: INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB-C17)
// Include necessary header files
#include <p17c756.h>
#include <delays.h>
#include <stdlib.h>
#include <i2c16.h>
// Processor header file
// Delay routines header file
// Standard Library header file
// I2C routines header file
#define CONTROL 0xa0
// Control byte definition for 24LC01B
// Function declarations
void main(void);
void WritePORTD(static unsigned char data);
void ByteWrite(static unsigned char address,static unsigned char data);
unsigned char ByteRead(static unsigned char address);
void ACKPoll(void);
// Main program
void main(void)
{
static unsigned char address;
static unsigned char datao;
static unsigned char datai;
// I2C address of 24LC01B
// Data written to 24LC01B
// Data read from 24LC01B
address = 0;
// Preset address to 0
OpenI2C(MASTER,SLEW_ON);
SSPADD = 39;
// Configure I2C Module Master mode, Slew rate control on
// Configure clock for 100KHz
while(address<128)
// Loop 128 times, 24LC01B is 128x8
{
datao = PORTB;
do
{
ByteWrite(address,datao);
// Write data to EEPROM
ACKPoll();
// Poll the 24LC01B for state
datai = ByteRead(address); // Read data from EEPROM into SSPBUF
} while(datai != datao);
// Loop as long as data not correctly
// written to 24LC01B
address++;
// Increment address
}
while(1)
{
// Done writing 128 bytes to 24LC01B, Loop forever
Nop();
}
}
DS30289A-page 174
1998 Microchip Technology Inc.
PIC17C7XX
EXAMPLE 15-2: INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB-C17) (Cont.’d)
// Writes the byte data to 24LC01B at the specified address
void ByteWrite(static unsigned char address, static unsigned char data)
{
StartI2C();
// Send start bit
IdleI2C();
WriteI2C(CONTROL);
IdleI2C();
if (!SSPCON2bits.ACKSTAT)
{
// Wait for idle condition
// Send control byte
// Wait for idle condition
// If 24LC01B ACKs
WriteI2C(address);
IdleI2C();
// Send control byte
// Wait for idle condition
if (!SSPCON2bits.ACKSTAT)
WriteI2C(data);
}
// If 24LC01B ACKs
// Send data
IdleI2C();
StopI2C();
IdleI2C();
return;
// Wait for idle condition
// Send stop bit
// Wait for idle condition
}
// Reads a byte of data from 24LC01B at the specified address
unsigned char ByteRead(static unsigned char address)
{
StartI2C();
// Send start bit
IdleI2C();
WriteI2C(CONTROL);
// Wait for idle condition
// Send control byte
IdleI2C();
if (!SSPCON2bits.ACKSTAT)
// Wait for idle condition
// If the 24LC01B ACKs
{
WriteI2C(address);
// Send address
IdleI2C();
if (!SSPCON2bits.ACKSTAT)
// Wait for idle condition
// If the 24LC01B ACKs
{
RestartI2C();
// Send restart
IdleI2C();
WriteI2C(CONTROL+1);
IdleI2C();
if (!SSPCON2bits.ACKSTAT)
// Wait for idle condition
// Send control byte with R/W set
// Wait for idle condition
// If the 24LC01B ACKs
{
getcI2C();
IdleI2C();
NotAckI2C();
IdleI2C();
StopI2C();
IdleI2C();
}
// Read a byte of data from 24LC01B
// Wait for idle condition
// Send a NACK to 24LC01B
// Wait for idle condition
// Send stop bit
// Wait for idle condition
}
}
return(SSPBUF);
}
1998 Microchip Technology Inc.
DS30289A-page 175
PIC17C7XX
EXAMPLE 15-2: INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB-C17) (Cont.’d)
void ACKPoll(void)
{
StartI2C();
// Send start bit
IdleI2C();
WriteI2C(CONTROL);
IdleI2C();
// Wait for idle condition
// Send control byte
// Wait for idle condition
// Poll the ACK bit coming from the 24LC01B
// Loop as long as the 24LC01B NACKs
while (SSPCON2bits.ACKSTAT)
{
RestartI2C();
IdleI2C();
WriteI2C(CONTROL);
IdleI2C();
// Send a restart bit
// Wait for idle condition
// Send control byte
// Wait for idle condition
}
IdleI2C();
StopI2C();
IdleI2C();
return;
// Wait for idle condition
// Send stop bit
// Wait for idle condition
}
DS30289A-page 176
1998 Microchip Technology Inc.
PIC17C7XX
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode.To oper-
ate in sleep, the A/D clock must be derived from the
A/D’s internal RC oscillator.
16.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has
twelve analog inputs for the PIC17C75X devices and
sixteen for the PIC17C76X devices.
The A/D module has four registers. These registers
are:
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the input
into the converter. The converter then generates a dig-
ital result of this analog level via successive approxima-
tion. This A/D conversion, of the analog input signal,
results in a corresponding 10-bit digital number.
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Figure 16-1, controls
the operation of the A/D module. The ADCON1 regis-
ter, shown in Figure 16-2, configures the functions of
the port pins. The port pins can be configured as ana-
log inputs (RG3 and RG2 can also be the voltage refer-
ences) or as digital I/O.
The analog reference voltages (positive and negative
supply) are software selectable to either the device’s
supply voltages (AVDD, AVss) or the voltage level on
the RG3/AN0/VREF+ and RG2/AN1/VREF- pins.
FIGURE 16-1: ADCON0 REGISTER (ADDRESS: 14h, BANK 5)
R/W-0 R/W-0 R/W-0
CHS3 CHS2 CHS1
bit7
R/W-0
CHS0
U-0
—
R/W-0
U-0
—
R/W-0
ADON
GO/DONE
R =Readable bit
W = Writable bit
U =Unimplemented bit,
read as ‘0’
bit0
- n = Value at POR reset
bit 7-4: CHS3:CHS0: Analog Channel Select bits
0000= channel 0, (AN0)
0001= channel 1, (AN1)
0010= channel 2, (AN2)
0011= channel 3, (AN3)
0100= channel 4, (AN4)
0101= channel 5, (AN5)
0110= channel 6, (AN6)
0111= channel 7, (AN7)
1000= channel 8, (AN8)
1001= channel 9, (AN9)
1010= channel 10, (AN10)
1011= channel 11, (AN11)
1100= channel 12, (AN12) (PIC17C76X only)
1101= channel 13, (AN13) (PIC17C76X only)
1110= channel 14, (AN14) (PIC17C76X only)
1111= channel 15, (AN15) (PIC17C76X only)
11xx= RESERVED, do not select (PIC17C75X only)
bit 3:
bit 2:
Unimplemented: Read as '0'
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared
by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
1998 Microchip Technology Inc.
DS30289A-page 177
PIC17C7XX
FIGURE 16-2: ADCON1 REGISTER (ADDRESS 15h, BANK 5)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PCFG3
PCFG2
PCFG1
PCFG0
R =Readable bit
W = Writable bit
U =Unimplemented
bit, read as ‘0’
bit0
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/8
01= FOSC/32
10= FOSC/64
11= FRC (clock derived from an internal RC oscillator)
bit 5:
bit 4:
ADFM: A/D Result format select
1 = Right justified. 6 Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ’0’.
Unimplemented: Read as '0'
bit 3-1: PCFG3:PCFG1: A/D Port Configuration Control bits
PCFG3:PCFG
AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
1
000
001
010
011
100
101
110
111
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
bit 0:
PCFG0: A/D Voltage Reference Select bit
1 = A/D reference is the VREF+ and VREF- pins
0 = A/D reference is AVDD and AVSS
Note:When this bit is set, ensure that the A/D voltage reference specifications are met.
DS30289A-page 178
1998 Microchip Technology Inc.
PIC17C7XX
The ADRESH:ADRESL registers contains the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared,
and A/D interrupt flag bit ADIF is set. The block dia-
grams of the A/D module are shown in Figure 16-3.
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Clear GLINTD bit
3. Wait the required acquisition time.
4. Start conversion:
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding DDR bits selected as inputs.
To determine sample time, see Section 16.1. After this
acquisition time has elapsed the A/D conversion can be
started. The following steps should be followed for
doing an A/D conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
1. Configure the A/D module:
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 16-3: A/D BLOCK DIAGRAM
CHS3:CHS0
1011
1011
1011
1011
(1)
AN15
(1)
AN14
(1)
AN13
(1)
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
VIN
0100
(Input voltage)
AN4
0011
AN3
A/D
Converter
0010
AN2
0001
AN1
PCFG0
0000
AN0
VREF-
(Reference
voltage)
AVSS
VREF+
AVDD
(1) These channels only available on PIC16C76X devices
1998 Microchip Technology Inc.
DS30289A-page 179
PIC17C7XX
Figure 16-4 shows the conversion sequence, and the
terms that are used. Acquisition time is the time that the
A/D module’s holding capacitor is connected to the
external voltage level.Then there is the conversion time
of 12 TAD, which is started when the GO bit is set. The
sum of these two times is the sampling time.There is a
minimum acquisition time to ensure that the holding
capacitor is charged to a level that will give the desired
accuracy for the A/D conversion.
FIGURE 16-4: A/D CONVERSION SEQUENCE
A/D Sample Time
Acquisition Time
A/D Conversion Time
A/D conversion complete, result is loaded in ADRES register.
Holding capacitor begins acquiring voltage level on selected
channel ADIF bit is set
When A/D conversion is started
(setting the GO bit)
When A/D holding capacitor starts to charge.
After A/D conversion, or when new A/D channel is selected
DS30289A-page 180
1998 Microchip Technology Inc.
PIC17C7XX
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D).The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
16.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-5.The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD),
Figure 16-5. The maximum recommended imped-
ance for analog sources is 10 kΩ. As the impedance
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed)
this acquisition must be done before the conversion
can be started.
Example 16-1 shows the calculation of the minimum
required acquisition time TACQ.
This calculation is based on the following application
system assumptions.
CHOLD
Rs
Conversion Error
VDD
=
=
≤
=
120 pF
10 kΩ
1/2 LSb
5V → Rss = 7 kΩ
(see
graph in Figure 16-5)
Temperature
VHOLD
=
=
50°C (system max.)
0V @ time = 0
EQUATION 16-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 16-2: A/D MINIMUM CHARGING TIME
(-Tc/CHOLD(RIC + RSS + RS))
VHOLD
or
Tc
=
=
(VREF - (VREF/2048)) • (1 - e
)
-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 16-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ =
Temperature coefficient is only required for temperatures > 25°C.
TAMP + TC + TCOFF
TACQ =
TC =
2 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0004885)
-120 pF (18 kΩ) ln(0.0004885)
-2.16 µs (-7.6241)
16.47 µs
TACQ =
2 µs + 16.47 µs + [(50°C - 25°C)(0.05 µs/°C)]
18.447 µs + 1.25 µs
19.72 µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
Note 2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
Note 3: The maximum recommended impedance for analog sources is 10 kΩ.This is required to meet the pin leak-
age specification.
Note 4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again. Dur-
ing this time the holding capacitor is not connected to the selected A/D input channel.
1998 Microchip Technology Inc.
DS30289A-page 181
PIC17C7XX
FIGURE 16-5: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CHOLD
= DAC capacitance
= 120 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I leakage = leakage current at the pin due to
various junctions
VDD 4V
3V
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
DS30289A-page 182
1998 Microchip Technology Inc.
PIC17C7XX
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
16.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
Table 16-1 and Table 16-2 show the resultant TAD
times derived from the device operating frequencies
and the A/D clock source selected. These times are for
standard voltage range devices.
• 8TOSC
• 32TOSC
• 64TOSC
• Internal RC oscillator
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Operation ADCS1:ADCS0
Device Frequency
33 MHz
20 MHz
5 MHz
1.6 µs
6.4 µs
1.25 MHz
333.33 kHz
(2)
(2)
8TOSC
32TOSC
64TOSC
RC
00
01
10
11
6.4 µs
24 µs
242 ns
970 ns
400 ns
(2)
(3)
(3)
1.6 µs
25.6 µs
96 µs
(3)
(3)
(3)
1.94 µs
3.2 µs
12.8 µs
51.2 µs
192 µs
(1, 4)
(1, 4)
(1, 4)
(1, 4)
(1)
2 - 6 µs
2 - 6 µs
2 - 6 µs
2 - 6 µs
2 - 6 µs
Legend: Shaded cells are are outside of recommended ranges.
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequencies is greater than 1 MHz, the RC A/D conversion clock source is only recom-
mended for sleep operation.
TABLE 16-2: TAD vs. DEVICE OPERATING FREQUENCIES (EXTENDEDVOLTAGE DEVICES (LC))
AD Clock Source (TAD)
Operation ADCS1:ADCS0
Device Frequency
8 MHz
4 MHz
2 MHz
4 µs
1 MHz
333.33 kHz
(2)
(2)
8TOSC
32TOSC
64TOSC
RC
00
01
10
11
8 µs
24 µs
1.0 µs
4.0 µs
2.0 µs
8 µs
(3)
(3)
16 µs
32 µs
64 µs
96 µs
(3)
(3)
(1)
(3)
8.0 µs
16 µs
32 µs
192 µs
(1, 4)
(1, 4)
(1, 4)
(1)
3 - 9 µs
3 - 9 µs
3 - 9 µs
3 - 9 µs
3 - 9 µs
Legend: Shaded cells are are outside of recommended ranges.
Note 1: The RC source has a typical TAD time of 6 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequencies is greater than 1 MHz, the RC A/D conversion clock source is only recom-
mended for sleep operation.
1998 Microchip Technology Inc.
DS30289A-page 183
PIC17C7XX
16.3
Configuring Analog Port Pins
16.4
A/D Conversions
The ADCON1, and DDR registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding DDR bits
set (input). If the DDR bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
Example 16-2 shows how to perform an A/D conver-
sion. The PORTF and lower four PORTG pins are con-
figured as analog inputs. The analog references
(VREF+ and VREF-) are the device AVDD and AVSS.The
A/D interrupt is enabled, and the A/D conversion clock
is FRC. The conversion is performed on the RG3/AN0
pin (channel 0).
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the DDR bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample.That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2TAD wait is required before the next
acquisition is started. After this 2TAD wait, acquisition
on the selected channel is automatically started.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN15:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specification.
In Figure 16-6, after the GO bit is set, the first time seg-
mant has a minimum of TCY and a maximum of TAD.
EXAMPLE 16-2: A/D CONVERSION
MOVLB
CLRF
MOVLW
MOVWF
MOVLB
BCF
BSF
BSF
BCF
5
; Bank 5
ADCON1, F
0x01
ADCON0
; Configure A/D inputs, All analog, TAD = Fosc/8, left just.
; A/D is on, Channel 0 is selected
;
; Bank 4
; Clear A/D interrupt flag bit
; Enable A/D interrupts
4
PIR2, ADIF
PIE2, ADIE
INTSTA, PEIE
CPUSTA, GLINTD
; Enable peripheral interrupts
; Enable all interrupts
;
;
;
;
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
MOVLB
5
; Bank 5
BSF
:
:
ADCON0, GO
; Start A/D Conversion
;
;
The ADIF bit will be set and the GO/DONE bit
is cleared upon completion of the A/D Conversion
FIGURE 16-6: A/D CONVERSION TAD CYCLES
Tcy to TAD TAD1
TAD2
b9
TAD3
b8
TAD4 TAD5
b7 b6
TAD6 TAD7 TAD8 TAD9 TAD10TAD11
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
DS30289A-page 184
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 16-7: FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
Yes
Yes
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
GO = 0,
ADIF = 1
SLEEP
Instruction?
A/D Clock
= RC?
No
No
Yes
Yes
Abort Conversion
GO = 0,
ADIF = 0
Wake-up
From Sleep?
Finish Conversion
GO = 0,
ADIF = 1
Device in
SLEEP?
Wait 2TAD
No
No
SLEEP
Power-down A/D
Finish Conversion
GO = 0,
ADIF = 1
Stay in Sleep
Power-down A/D
Wait 2TAD
Wait 2TAD
1998 Microchip Technology Inc.
DS30289A-page 185
PIC17C7XX
16.4.1 A/D RESULT REGISTERS
16.5
A/D Operation During Sleep
The A/D module can operate during SLEEP mode.This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion.This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 16-8 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general pur-
pose 8-bit registers.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
16.6
Effects of a Reset
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The value that is in the ADRESH:ADRESL registers is
not modified for
a
Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
FIGURE 16-8: A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
0 7 6 5
ADFM = 1
0
7
7
2 1 0 7
0
0000 00
0000 00
RESULT
ADRESL
10-bits
RESULT
ADRESH
10-bits
ADRESH
ADRESL
Left Justified
Right Justified
DS30289A-page 186
1998 Microchip Technology Inc.
PIC17C7XX
16.7
A/D Accuracy/Error
16.8
Connection Considerations
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high fre-
quencies, TAD should be derived from the device oscil-
lator.
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.3V, then the accuracy of the conver-
sion is out of specification.
An external RC filter is sometimes added for anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
The absolute accuracy specified for the A/D converter
includes the sum of all contributions for quantization
error, integral error, differential error, full scale error, off-
set error, and monotonicity. It is defined as the maxi-
mum deviation from an actual transition versus an ideal
transition for any code. The absolute error of the A/D
converter is specified at < ±1 LSb for VDD = VREF (over
the device’s specified operating range). However, the
accuracy of the A/D converter will degrade as VREF
diverges from VDD.
16.9
Transfer Function
The transfer function of the A/D converter is as follows:
the first transition occurs when the analog input voltage
(VAIN) equals Analog VREF / 1024 (Figure 16-9).
For a given range of analog inputs, the output digital
code will be the same.This is due to the quantization of
the analog input to a digital code. Quantization error is
typically ± 1/2 LSb and is inherent in the analog to dig-
ital conversion process.The only way to reduce quanti-
zation error is to increase the resolution of the A/D
converter or oversample.
FIGURE 16-9: A/D TRANSFER FUNCTION
3FFh
3FEh
Offset error measures the first actual transition of a
code versus the first ideal transition of a code. Offset
error shifts the entire transfer function. Offset error can
be calibrated out of a system or introduced into a sys-
tem through the interaction of the total leakage current
and source impedance at the analog input.
003h
002h
001h
000h
Gain error measures the maximum deviation of the last
actual transition and the last ideal transition adjusted
for offset error.This error appears as a change in slope
of the transfer function. The difference in gain error to
full scale error is that full scale does not take offset error
into account. Gain error can be calibrated out in soft-
ware.
Linearity error refers to the uniformity of the code
changes. Linearity errors cannot be calibrated out of
the system. Integral non-linearity error measures the
actual code transition versus the ideal code transition
adjusted by the gain error for each code.
Analog input voltage
16.10 References
A good reference for the undestanding A/D converter is
the "Analog-Digital Conversion Handbook" third edi-
tion, published by Prentice Hall (ISBN 0-13-03-2848-0).
Differential non-linearity measures the maximum
actual code width versus the ideal code width. This
measure is unadjusted.
The maximum pin leakage current is specified in the
Device Data Sheet electrical specification parameter
#D060.
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high fre-
quencies, TAD should be derived from the device oscil-
lator. TAD must not violate the minimum and should be
minimized to reduce inaccuracies due to noise and
sampling capacitor bleed off.
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
1998 Microchip Technology Inc.
DS30289A-page 187
PIC17C7XX
TABLE 16-3: REGISTERS/BITS ASSOCIATED WITH A/D
POR,
BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
06h, unbanked CPUSTA
07h, unbanked INTSTA
—
—
STAKAV GLINTD
TO
PD
POR
T0IE
BOR
INTE
--11 1100
0000 0000
--11 qq11
0000 0000
000- 0010
PEIF
T0CKIF
BCLIF
BCLIE
T0IF
ADIF
ADIE
INTF
—
PEIE
T0CKIE
CA3IF
CA3IE
10h, Bank 4
11h, Bank 4
10h, Bank 5
11h, Bank 5
PIR2
SSPIF
SSPIE
CA4IF
CA4IE
TX2IF
TX2IE
RC2IF 000- 0010
PIE2
—
RC2IE 000- 0000
000- 0000
1111 1111
1111 1111
DDRF
PORTF
Data Direction register for PORTF
0000 0000
0000 0000
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
1111 1111
1111 1111
uuuu 0000
12h, Bank 5
13h, Bank 5
DDRG
Data Direction register for PORTG
RG7/ RG6/ RG5/
RG3/
AN0/VREF
+
xxxx 0000
PORTG
RG4/
CAP3
RG2/
AN1/VREF
-
RG1/
AN2
RG0/
AN3
TX2/CK2 RX2/DT2 PWM3
ADCON0
ADCON1
CHS3
CHS2
CHS1
ADFM
CHS0
—
—
GO/DONE
PCFG2
—
ADON 0000 -0-0
0000 -0-0
000- 0000
uuuu uuuu
uuuu uuuu
14h, Bank 5
15h, Bank 5
16h, Bank 5
ADCS1
ADCS0
PCFG3
PCFG1 PCFG0 000- 0000
xxxx xxxx
ADRESL A/D Result Low Register
ADRESH A/D Result High Register
xxxx xxxx
17h, Bank 5
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30289A-page 188
1998 Microchip Technology Inc.
PIC17C7XX
The PIC17CXXX has a Watchdog Timer which can be
shutoff only through EPROM bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on POR and BOR. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in RESET until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 96 ms (nominal) on power-up only,
designed to keep the part in RESET while the power
supply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
17.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of
real-time applications. The PIC17CXXX family has a
host of such features intended to maximize system reli-
ability, minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These are:
• Oscillator selection (Section 4.0)
• Reset (Section 5.0)
The SLEEP mode is designed to offer a very low cur-
rent power-down mode. The user can wake from
SLEEP through external reset, Watchdog Timer Reset
or through an interrupt. Several oscillator options are
also made available to allow the part to fit the applica-
tion. The RC oscillator option saves system cost while
the LF crystal option saves power. Configuration bits
are used to select various options. This configuration
word has the format shown in Figure 17-1.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts (Section 6.0)
• Watchdog Timer (WDT)
• SLEEP mode
• Code protection
FIGURE 17-1: CONFIGURATION WORDS
U - x
bit15
U - x
bit15
bit 6H
R/P - 1 R/P - 1 U - x U - x
PM2 BODEN
bit 8 bit 7
U - x
—
U - x
—
U - x
—
U - x
—
High (H) Table Read Addr.
FE0Fh - FE08h
—
—
—
bit 0
U - x
R/P - 1 U - x R/P - 1 R/P - 1
R/P - 1
R/P - 1 R/P - 1 Low (L) Table Read Addr.
—
—
PM1
—
PM0 WDTPS1 WDTPS0 FOSC1 FOSC0 FE07h - FE00h
bit 0
bit 8 bit 7
BODEN: Brown-out Detect Enable
1 =
0 =
Brown-out Detect circuitry is enabled
Brown-out Detect circuitry is disabled
bits 7H:6L:4L PM2, PM1, PM0, Processor Mode Select bits
111 = Microprocessor Mode
110 = Microcontroller mode
101 = Extended microcontroller mode
000 = Code protected microcontroller mode
bits 2L:3L
bits 1L:0L
—
WDTPS1:WDTPS0, WDT Postscaler Select bits
11 = WDT enabled, postscaler = 1
10 = WDT enabled, postscaler = 256
01 = WDT enabled, postscaler = 64
00 = WDT disabled, 16-bit overflow timer
FOSC1:FOSC0, Oscillator Select bits
11 = EC oscillator
10 = XT oscillator
01 = RC oscillator
00 = LF oscillator
Reserved
1998 Microchip Technology Inc.
DS30289A-page 189
PIC17C7XX
17.1
Configuration Bits
17.2
Oscillator Configurations
The PIC17CXXX has eight configuration locations
(Table 17-1). These locations can be programmed
(read as '0') or left unprogrammed (read as '1') to select
various device configurations. Any write to a configura-
tion location, regardless of the data, will program that
configuration bit. A TABLWT instruction is required to
write to program memory locations. The configuration
bits can be read by using the TABLRD instructions.
Reading any configuration location between FE00h
and FE07h will read the low byte of the configuration
word (Figure 17-1) into the TABLATL register.The TAB-
LATH register will be FFh. Reading a configuration
location between FE08h and FE0Fh will read the high
byte of the configuration word into the TABLATL regis-
ter. The TABLATH register will be FFh.
17.2.1 OSCILLATOR TYPES
The PIC17CXXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
• LF
• XT
• EC
• RC
Low Power Crystal
Crystal/Resonator
External Clock Input
Resistor/Capacitor
For information on the different oscillator types and how
to use them, please refer to Section 4.0.
Addresses FE00h through FE0Fh are only in the pro-
gram memory space for microcontroller and code pro-
tected microcontroller modes. A device programmer
will be able to read the configuration word in any pro-
cessor mode. See programming specifications for more
detail.
TABLE 17-1: CONFIGURATION
LOCATIONS
Bit
Address
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
FE00h
FE01h
FE02h
FE03h
FE04h
FE06h
FE0Eh
FE0Fh
PM1
BODEN
PM2
Note: When programming the desired configura-
tion locations, they must be programmed in
ascending order. Starting with address
FE00h.
DS30289A-page 190
1998 Microchip Technology Inc.
PIC17C7XX
17.3.2 CLEARING THE WDT AND POSTSCALER
The WDT and postscaler are cleared when:
17.3
Watchdog Timer (WDT)
The Watchdog Timer’s function is to recover from
software malfunction. The WDT uses an internal free
running on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation, a WDT time-out generates a device RESET.
The WDT can be permanently disabled by
programming the configuration bits WDTPS1:WDTPS0
as '00' (Section 17.1).
• The device is in the reset state
• A SLEEPinstruction is executed
• A CLRWDTinstruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the reset state.
17.3.3 WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
Under normal operation, the WDT must be cleared on
a regular interval. This time must be less than the min-
imum WDT overflow time. Not clearing the WDT in this
time frame will cause the WDT to overflow and reset the
device.
The WDT and postscaler become the Power-up Timer
whenever the PWRT is invoked.
17.3.4 WDT AS NORMAL TIMER
17.3.1 WDT PERIOD
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 TOSC cycles. On overflow, the TO bit
is cleared (device is not reset). The CLRWDTinstruction
can be used to set the TO bit. This allows the WDT to
be a simple overflow timer. The simple timer does not
increment when in sleep.
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1).The time-out periods vary with temper-
DD
ature, V and process variations from part to part (see
DC specs). If longer time-out periods are desired, con-
figuration bits should be used to enable the WDT with
a greater prescale. Thus, typical time-out periods up to
3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and its postscale setting and prevent it from timing out
thus generating a device RESET condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
FIGURE 17-2: WATCHDOG TIMER BLOCK DIAGRAM
On-chip RC
Oscillator
WDT
Postscaler
(1)
WDTPS1:WDTPS0
4 - to - 1 MUX
WDT Overflow
WDT Enable
Note 1: This oscillator is separate from the external
RC oscillator on the OSC1 pin.
TABLE 17-2: REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
—
Config
See Figure 17-1 for location of WDTPSx bits in Configuration Word.
STKAV GLINTD TO PD
(Note 1)
(Note 1)
06h, Unbanked CPUSTA
—
—
POR
BOR
--11 11qq --11 qquu
Legend:
Note 1:
-= unimplemented read as '0', q- value depends on condition, shaded cells are not used by the WDT.
This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
1998 Microchip Technology Inc.
DS30289A-page 191
PIC17C7XX
Any reset event will cause a device reset. Any interrupt
event is considered a continuation of program execu-
tion.The TO and PD bits in the CPUSTA register can be
used to determine the cause of device reset. The PD
bit, which is set on power-up, is cleared when SLEEP
is invoked. The TO bit is cleared if WDT time-out
occurred (and caused wake-up).
17.4
Power-down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEPinstruction. This clears the Watchdog Timer and
postscaler (if enabled). The PD bit is cleared and the
TO bit is set (in the CPUSTA register). In SLEEP mode,
the oscillator driver is turned off.The I/O ports maintain
their status (driving high, low, or hi-impedance).
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GLINTD bit. If the GLINTD
bit is set (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the
GLINTD bit is clear (enabled), the device executes the
instruction after the SLEEP instruction and then
branches to the interrupt vector address. In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEPinstruction.
The MCLR/VPP pin must be at a logic high level
(VIHMC). A WDT time-out RESET does not drive the
MCLR/VPP pin low.
17.4.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
• Power-on Reset
• Brown-out Reset
• External reset input on MCLR/VPP pin
• WDT Reset (if WDT was enabled)
• Interrupt from RA0/INT pin, RB port change,
T0CKI interrupt, or some peripheral Interrupts
Note: If the global interrupt is disabled (GLINTD
is set), but any interrupt source has both its
interrupt enable bit and the corresponding
interrupt flag bit set, the device will imme-
diately wake-up from sleep. The TO bit is
set, and the PD bit is cleared.
The following peripheral interrupts can wake the device
from SLEEP:
• Capture interrupts
• USART synchronous slave transmit interrupts
• USART synchronous slave receive interrupts
• A/D conversion complete
The WDT is cleared when the device wakes from
SLEEP, regardless of the source of wake-up.
17.4.1.1 WAKE-UP DELAY
• SPI slave transmit / receive complete
2
• I C slave receive
When the oscillator type is configured in XT or LF
mode, the Oscillator Start-up Timer (OST) is activated
on wake-up. The OST will keep the device in reset for
1024TOSC. This needs to be taken into account when
considering the interrupt response time when coming
out of SLEEP.
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip Q clocks are present.
FIGURE 17-3: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Tost(2)
CLKOUT(4)
'0' or '1'
INT
(RA0/INT pin)
Interrupt Latency (2)
INTF flag
GLINTD bit
Processor
in SLEEP
INSTRUCTION FLOW
0004h
PC
PC+1
PC+2
0005h
PC
Instruction
Inst (PC+2)
Inst (PC+1)
Inst (PC) = SLEEP
Inst (PC-1)
Inst (PC+1)
SLEEP
fetched
Instruction
executed
Dummy Cycle
Note 1: XT or LF oscillator mode assumed.
2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.
3: When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30289A-page 192
1998 Microchip Technology Inc.
PIC17C7XX
17.4.2 MINIMIZING CURRENT CONSUMPTION
17.5
Code Protection
To minimize current consumption, all I/O pins should be
either at VDD, or VSS, with no external circuitry drawing
current from the I/O pin. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should be at VDD or VSS.The contributions
from on-chip pull-ups on PORTB should also be con-
sidered, and disabled when possible.
The code in the program memory can be protected by
selecting the microcontroller in code protected mode
(PM2:PM0 = '000').
In this mode, instructions that are in the on-chip pro-
gram memory space, can continue to read or write the
program memory. An instruction that is executed out-
side of the internal program memory range will be
inhibited from writing to or reading from program mem-
ory.
Note: Microchip does not recommend code pro-
tecting windowed devices.
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
1998 Microchip Technology Inc.
DS30289A-page 193
PIC17C7XX
For complete details of serial programming, please
refer to the PIC17C7XX Programming Specification.
(Contact your local Microchip Technology Sales Office
for availability.)
17.6
In-Circuit Serial Programming
The PIC17C7XX group of the high end family
(PIC17CXXX) has an added feature that allows serial
programming while in the end application circuit.This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
FIGURE 17-4: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC17C7XX
Devices may be serialized to make the product unique,
“special” variants of the product may be offered, and
code updates are possible. This allows for increased
design flexibility.
+5V
0V
VDD
VSS
VPP
MCLR/VPP
To place the device into the serial programming test
mode, two pins will need to be placed at VIHH. These
are the TEST pin and the MCLR/VPP pin. Also a
sequence of events must occur as follows:
TEST CNTL
Dev. CLK
TEST
RA1/T0CKI
Data I/O
RA4/RX1/DT1
RA5/TX1/CK1
1. The TEST pin is placed at VIHH.
Data CLK
2. The MCLR/VPP pin is placed at VIHH.
There is a setup time between step 1 and step 2 that
must be met.
After this sequence the Program Counter is pointing to
program memory address 0xFF60. This location is in
the Boot ROM. The code initializes the USART/SCI so
that it can receive commands. For this, the device must
be clocked.The device clock source in this mode is the
RA1/T0CKI pin. After delaying to allow the USART/SCI
to initialize, commands can be received. The flow is
shown in these 3 steps:
VDD
To Normal
Connections
1. The device clock source starts.
2. Wait 80 device clocks for Boot ROM code to con-
figure the USART/SCI.
3. Commands may now be sent.
TABLE 17-3: ICSP INTERFACE PINS
During Programming
Description
Name
Function
DT
Type
RA4/RX1/DT1
RA5/TX1/CK1
RA1/T0CKI
TEST
I/O
I
Serial Data
CK
Serial Clock
OSCI
TEST
MCLR/VPP
VDD
I
Device Clock Source
I
Test mode selection control input. Force to VIHH,
Master Clear reset and Device Programming Voltage
Positive supply for logic and I/O pins
MCLR/VPP
VDD
P
P
P
VSS
VSS
Ground reference for logic and I/O pins
DS30289A-page 194
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 18-1: OPCODE FIELD
18.0 INSTRUCTION SET SUMMARY
DESCRIPTIONS
The PIC17CXXX instruction set consists of 58 instruc-
tions. Each instruction is a 16-bit word divided into an
OPCODE and one or more operands. The opcode
specifies the instruction type, while the operand(s) fur-
ther specify the operation of the instruction. The
PIC17CXXX instruction set can be grouped into three
types:
Field
Description
f
p
i
Register file address (00h to FFh)
Peripheral register file address (00h to 1Fh)
Table pointer control i = '0' (do not change)
i = '1' (increment after instruction execution)
t
Table byte select t = '0' (perform operation on lower
byte)
t = '1' (perform operation on upper byte literal field,
constant data)
• byte-oriented
• bit-oriented
• literal and control operations
WREG Working register (accumulator)
These formats are shown in Figure 18-1.
b
k
x
Bit address within an 8-bit file register
Literal field, constant data or label
Table 18-1 shows the field descriptions for the
opcodes.These descriptions are useful for understand-
ing the opcodes in Table 18-2 and in each specific
instruction descriptions.
Don't care location (= '0' or '1')
The assembler will generate code with x = '0'. It is
the recommended form of use for compatibility with
all Microchip software tools.
byte-oriented instructions, 'f' represents a file regis-
ter designator and 'd' represents a destination designa-
tor. The file register designator specifies which file
register is to be used by the instruction.
d
Destination select
0 = store result in WREG
1 = store result in file register f
Default is d = '1'
The destination designator specifies where the result of
the operation is to be placed. If 'd' = '0', the result is
placed in the WREG register. If 'd' = '1', the result is
placed in the file register specified by the instruction.
u
s
Unused, encoded as '0'
Destination select
0 = store result in file register f and in the WREG
1 = store result in file register f
Default is s = '1'
bit-oriented instructions, 'b' represents a bit field des-
ignator which selects the number of the bit affected by
the operation, while 'f' represents the number of the file
in which the bit is located.
label Label name
C,DC, ALU status bits Carry, Digit Carry, Zero, Overflow
Z,OV
literal and control operations, 'k' represents an 8- or
13-bit constant or literal value.
GLINTD Global Interrupt Disable bit (CPUSTA<4>)
TBLPTR Table Pointer (16-bit)
The instruction set is highly orthogonal and is grouped
into:
TBLAT Table Latch (16-bit) consists of high byte (TBLATH)
and low byte (TBLATL)
TBLATL Table Latch low byte
TBLATH Table Latch high byte
TOS Top of Stack
• byte-oriented operations
• bit-oriented operations
• literal and control operations
PC
Program Counter
All instructions are executed within one single instruc-
tion cycle, unless:
BSR Bank Select Register
WDT Watchdog Timer Counter
• a conditional test is true
TO
PD
Time-out bit
• the program counter is changed as a result of an
instruction
Power-down bit
dest Destination either the WREG register or the speci-
• a table read or a table write instruction is executed
(in this case, the execution takes two instruction
cycles with the second cycle executed as a NOP)
fied register file location
[ ]
( )
→
Options
Contents
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 25 MHz, the normal
instruction execution time is 160 ns. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 320 ns.
Assigned to
Register bit field
In the set of
< >
User defined term (font is courier)
italics
1998 Microchip Technology Inc.
DS30289A-page 195
PIC17C7XX
Table 18-2 lists the instructions recognized by the
MPASM assembler.
18.1
Special Function Registers as
Source/Destination
Note 1: Any unused opcode is Reserved. Use of
any reserved opcode may cause unex-
pected operation.
The PIC17C7XX’s orthogonal instruction set allows
read and write of all file registers, including special
function registers. There are some special situations
the user should be aware of:
All instruction examples use the following format to rep-
resent a hexadecimal number:
18.1.1 ALUSTA AS DESTINATION
0xhh
If an instruction writes to ALUSTA, the Z, C, DC and OV
bits may be set or cleared as a result of the instruction
and overwrite the original data bits written. For exam-
where h signifies a hexadecimal digit.
To represent a binary number:
0000 0100b
ple, executing CLRF
ALUSTA will clear register
ALUSTA, and then set the Z bit leaving 0000 0100bin
the register.
where b signifies a binary string.
FIGURE 18-1: GENERAL FORMAT FOR
INSTRUCTIONS
18.1.2 PCL AS SOURCE OR DESTINATION
Byte-oriented file register operations
Read, write or read-modify-write on PCL may have the
following results:
15
9
8
7
0
OPCODE
d
f (FILE #)
Read PC:
PCH → PCLATH; PCL → dest
d = 0 for destination WREG
d = 1 for destination f
f = 8-bit file register address
Write PCL:
PCLATH → PCH;
8-bit destination value → PCL
Read-Modify-Write: PCL→ ALU operand
PCLATH → PCH;
Byte to Byte move operations
15 13 12
OPCODE p (FILE #)
8
7
0
0
8-bit result → PCL
f (FILE #)
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
p = peripheral register file address
f = 8-bit file register address
18.1.3 BIT MANIPULATION
Bit-oriented file register operations
15 11 10
All bit manipulation instructions are done by first read-
ing the entire register, operating on the selected bit and
writing the result back (read-modify-write (R-M-W)).
The user should keep this in mind when operating on
some special function registers, such as ports.
8
7
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit address
f = 8-bit file register address
Literal and control operations
15
Note: Status bits that are manipulated by the
device (including the Interrupt flag bits) are
set or cleared in the Q1 cycle. So there is
no issue on doing R-M-W instructions on
registers which contain these bits
8
7
0
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOoperations
15 13 12
OPCODE
k (literal)
k = 13-bit immediate value
DS30289A-page 196
1998 Microchip Technology Inc.
PIC17C7XX
The four Q cycles that make up an instruction cycle
(TCY) can be generalized as:
18.2
Q Cycle Activity
Each instruction cycle (TCY) is comprised of four Q
cycles (Q1-Q4). The Q cycle is the same as the device
oscillator cycle (TOSC). The Q cycles provide the tim-
ing/designation for the Decode, Read, Process Data,
Write etc., of each instruction cycle. The following dia-
gram shows the relationship of the Q cycles to the
instruction cycle.
Q1: Instruction Decode Cycle or forced No
operation
Q2: Instruction Read Cycle or No operation
Q3: Process the Data
Q4: Instruction Write Cycle or No operation
Each instruction will show the detailed Q cycle opera-
tion for the instruction.
FIGURE 18-2: Q CYCLE ACTIVITY
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Tosc
TCY1
TCY2
TCY3
1998 Microchip Technology Inc.
DS30289A-page 197
PIC17C7XX
TABLE 18-2: PIC17CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
f,d
f,d
f,d
f,s
f,d
f
ADD WREG to f
1
1
1
1
1
0000 111d ffff ffff
0001 000d ffff ffff
0000 101d ffff ffff
0010 100s ffff ffff
0001 001d ffff ffff
OV,C,DC,Z
ADD WREG and Carry bit to f
AND WREG with f
OV,C,DC,Z
Z
None
Z
Clear f, or Clear f and Clear WREG
Complement f
3
COMF
CPFSEQ
CPFSGT
CPFSLT
DAW
Compare f with WREG, skip if f = WREG
Compare f with WREG, skip if f > WREG
Compare f with WREG, skip if f < WREG
Decimal Adjust WREG Register
Decrement f
1 (2) 0011 0001 ffff ffff
1 (2) 0011 0010 ffff ffff
1 (2) 0011 0000 ffff ffff
None 6,8
f
None 2,6,8
None 2,6,8
f
f,s
f,d
f,d
f,d
f,d
f,d
f,d
f,d
f,p
p,f
f
1
1
0010 111s ffff ffff
0000 011d ffff ffff
C
3
DECF
OV,C,DC,Z
DECFSZ
DCFSNZ
INCF
Decrement f, skip if 0
Decrement f, skip if not 0
Increment f
1 (2) 0001 011d ffff ffff
1 (2) 0010 011d ffff ffff
None 6,8
None 6,8
1
0001 010d ffff ffff
OV,C,DC,Z
INCFSZ
INFSNZ
IORWF
MOVFP
MOVPF
MOVWF
MULWF
NEGW
NOP
Increment f, skip if 0
Increment f, skip if not 0
Inclusive OR WREG with f
Move f to p
1 (2) 0001 111d ffff ffff
1 (2) 0010 010d ffff ffff
None 6,8
None 6,8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000 100d ffff ffff
011p pppp ffff ffff
010p pppp ffff ffff
0000 0001 ffff ffff
0011 0100 ffff ffff
0010 110s ffff ffff
0000 0000 0000 0000
0001 101d ffff ffff
0010 001d ffff ffff
0001 100d ffff ffff
0010 000d ffff ffff
0010 101s ffff ffff
0000 010d ffff ffff
0000 001d ffff ffff
0001 110d ffff ffff
Z
None
Move p to f
Z
Move WREG to f
None
f
Multiply WREG with f
Negate WREG
None
f,s
—
f,d
f,d
f,d
f,d
f,s
f,d
f,d
f,d
OV,C,DC,Z 1,3
No Operation
None
C
RLCF
Rotate left f through Carry
Rotate left f (no carry)
Rotate right f through Carry
Rotate right f (no carry)
Set f
RLNCF
RRCF
None
C
RRNCF
SETF
None
None
OV,C,DC,Z
OV,C,DC,Z
None
3
1
1
SUBWF
SUBWFB
SWAPF
TABLRD
TABLWT
TLRD
Subtract WREG from f
Subtract WREG from f with Borrow
Swap f
t,i,f Table Read
t,i,f Table Write
2 (3) 1010 10ti ffff ffff
None
7
5
2
1
1
1010 11ti ffff ffff
1010 00tx ffff ffff
1010 01tx ffff ffff
None
t,f
t,f
Table Latch Read
Table Latch Write
None
TLWT
None
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
(WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkkis loaded into the LSB of
the PC (PCL)
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRDto PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an NOP is executed.
DS30289A-page 198
1998 Microchip Technology Inc.
PIC17C7XX
TABLE 18-2: PIC17CXXX INSTRUCTION SET (Cont.’d)
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
Affected
Notes
MSb
1 (2) 0011 0011 ffff ffff
LSb
TSTFSZ
XORWF
f
Test f, skip if 0
None 6,8
f,d
Exclusive OR WREG with f
1
0000 110d ffff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f,b
f,b
f,b
f,b
f,b
Bit Clear f
1
1
1000 1bbb ffff ffff
1000 0bbb ffff ffff
None
BSF
Bit Set f
None
BTFSC
BTFSS
BTG
Bit test, skip if clear
Bit test, skip if set
Bit Toggle f
1 (2) 1001 1bbb ffff ffff
1 (2) 1001 0bbb ffff ffff
None 6,8
None 6,8
None
1
0011 1bbb ffff ffff
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
k
ADD literal to WREG
1
1
2
1
2
1
2
1
1
1
1
2
2
2
1
1
1
1011 0001 kkkk kkkk
1011 0101 kkkk kkkk
111k kkkk kkkk kkkk
0000 0000 0000 0100
110k kkkk kkkk kkkk
1011 0011 kkkk kkkk
1011 0111 kkkk kkkk
1011 1000 uuuu kkkk
1011 101x kkkk uuuu
1011 0000 kkkk kkkk
1011 1100 kkkk kkkk
0000 0000 0000 0101
1011 0110 kkkk kkkk
0000 0000 0000 0010
0000 0000 0000 0011
1011 0010 kkkk kkkk
1011 0100 kkkk kkkk
OV,C,DC,Z
k
AND literal with WREG
Subroutine Call
Z
None
TO,PD
None
Z
k
7
7
CLRWDT
GOTO
—
k
Clear Watchdog Timer
Unconditional Branch
IORLW
LCALL
MOVLB
MOVLR
MOVLW
MULLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
Inclusive OR literal with WREG
Long Call
k
None 4,7
None
k
Move literal to low nibble in BSR
Move literal to high nibble in BSR
Move literal to WREG
k
None
k
None
k
Multiply literal with WREG
Return from interrupt (and enable interrupts)
Return literal to WREG
Return from subroutine
Enter SLEEP Mode
None
—
k
GLINTD
7
7
7
None
None
—
—
k
TO, PD
OV,C,DC,Z
Z
Subtract WREG from literal
Exclusive OR literal with WREG
k
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
(WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkkis loaded into the LSB of
the PC (PCL)
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRDto PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an NOP is executed.
1998 Microchip Technology Inc.
DS30289A-page 199
PIC17C7XX
ADDLW
ADD Literal to WREG
ADDWF
Syntax:
ADD WREG to f
[ label ] ADDWF f,d
0 ≤ f ≤ 255
Syntax:
[ label ] ADDLW
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
d
[0,1]
(WREG) + k → (WREG)
Operation:
(WREG) + (f) → (dest)
OV, C, DC, Z
Status Affected:
Encoding:
OV, C, DC, Z
1011
0001
kkkk
kkkk
0000
111d
ffff
ffff
The contents of WREG are added to
the 8-bit literal 'k' and the result is
placed in WREG.
Add WREG to register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Decode
Read
register 'f'
Process
Data
Write to
destination
ADDLW
0x15
Example:
ADDWF
REG, 0
Example:
Before Instruction
WREG = 0x10
Before Instruction
WREG
REG
=
=
0x17
0xC2
After Instruction
WREG = 0x25
After Instruction
WREG
REG
=
=
0xD9
0xC2
DS30289A-page 200
1998 Microchip Technology Inc.
PIC17C7XX
ADDWFC
Syntax:
ADD WREG and Carry bit to f
[ label ] ADDWFC f,d
0 ≤ f ≤ 255
ANDLW
And Literal with WREG
Syntax:
[ label ] ANDLW
k
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
d
[0,1]
(WREG) .AND. (k) → (WREG)
Operation:
(WREG) + (f) + C → (dest)
Z
Status Affected:
Encoding:
OV, C, DC, Z
1011
0101
kkkk
kkkk
0001
000d
ffff
ffff
The contents of WREG are AND’ed with
the 8-bit literal 'k'.The result is placed in
WREG.
Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result is
placed in data memory location 'f'.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
'k'
Process
Data
Write to
WREG
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
ANDLW
0x5F
Example:
Before Instruction
WREG
ADDWFC
REG
0
Example:
=
0xA3
0x03
Before Instruction
After Instruction
WREG
Carry bit
REG
WREG
=
=
=
1
=
0x02
0x4D
After Instruction
Carry bit
REG
WREG
=
=
=
0
0x02
0x50
1998 Microchip Technology Inc.
DS30289A-page 201
PIC17C7XX
ANDWF
Syntax:
AND WREG with f
BCF
Bit Clear f
[ label ] ANDWF f,d
Syntax:
Operands:
[ label ] BCF f,b
Operands:
0 ≤ f ≤ 255
0 ≤ f ≤ 255
0 ≤ b ≤ 7
d
[0,1]
Operation:
(WREG) .AND. (f) → (dest)
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Status Affected:
Encoding:
Z
None
0000
101d
ffff
ffff
1000
1bbb
ffff
ffff
The contents of WREG are AND’ed with
register 'f'. If 'd' is 0 the result is stored
in WREG. If 'd' is 1 the result is stored
back in register 'f'.
Bit 'b' in register 'f' is cleared.
Description:
1
1
Cycles:
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
BCF
FLAG_REG,
7
Example:
Before Instruction
FLAG_REG = 0xC7
ANDWF
REG, 1
Example:
After Instruction
FLAG_REG = 0x47
Before Instruction
WREG
=
0x17
0xC2
REG
=
After Instruction
WREG
REG
=
=
0x17
0x02
DS30289A-page 202
1998 Microchip Technology Inc.
PIC17C7XX
BSF
Bit Set f
BTFSC
Bit Test, skip if Clear
Syntax:
Operands:
[ label ] BSF f,b
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 255
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
1000
0bbb
ffff
ffff
1001
1bbb
ffff
ffff
Bit 'b' in register 'f' is set.
If bit 'b' in register ’f' is 0 then the next
instruction is skipped.
Description:
1
1
If bit 'b' is 0 then the next instruction
fetched during the current instruction exe-
cution is discarded, and a NOPis exe-
cuted instead, making this a two-cycle
instruction.
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
Words:
Cycles:
1
1(2)
BSF
FLAG_REG, 7
Example:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Before Instruction
FLAG_REG= 0x0A
Decode
Read
register 'f'
Process
Data
No
operation
After Instruction
FLAG_REG= 0x8A
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG,1
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
If FLAG<1>
PC
1998 Microchip Technology Inc.
DS30289A-page 203
PIC17C7XX
BTFSS
Bit Test, skip if Set
BTG
Bit Toggle f
Syntax:
[ label ] BTFSS f,b
Syntax:
Operands:
[ label ] BTG f,b
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
0 ≤ f ≤ 255
0 ≤ b < 7
Operation:
skip if (f<b>) = 1
None
Operation:
(f<b>) → (f<b>)
Status Affected:
Encoding:
Status Affected:
Encoding:
None
1001
0bbb
ffff
ffff
0011
1bbb
ffff
ffff
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
Bit 'b' in data memory location 'f' is
inverted.
Description:
Description:
If bit 'b' is 1, then the next instruction
fetched during the current instruction exe-
cution, is discarded and an NOPis exe-
cuted instead, making this a two-cycle
instruction.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
Process
Data
Write
register 'f'
register 'f'
1(2)
Q Cycle Activity:
Q1
BTG
PORTC,
4
Example:
Q2
Q3
Q4
Before Instruction:
PORTC
Decode
Read
register 'f'
Process
Data
No
operation
=
0111 0101[0x75]
0110 0101[0x65]
If skip:
Q1
After Instruction:
PORTC
=
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSS
:
:
FLAG,1
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
If FLAG<1>
PC
DS30289A-page 204
1998 Microchip Technology Inc.
PIC17C7XX
CALL
Subroutine Call
[ label ] CALL
0 ≤ k ≤ 8191
CLRF
Clear f
Syntax:
k
Syntax:
[label] CLRF f,s
Operands:
Operation:
Operands:
Operation:
0 ≤ f ≤ 255
PC+ 1→ TOS, k → PC<12:0>,
k<12:8> → PCLATH<4:0>;
PC<15:13> → PCLATH<7:5>
00h → f, s [0,1]
00h → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
100s
ffff
ffff
111k
kkkk
kkkk
kkkk
Clears the contents of the specified reg-
ister(s).
s = 0: Data memory location 'f' and
WREG are cleared.
s = 1: Data memory location 'f' is
cleared.
Description:
Subroutine call within 8K page. First,
return address (PC+1) is pushed onto
the stack. The 13-bit value is loaded
into PC bits<12:0>. Then the
upper-eight bits of the PC are copied
into PCLATH. CALLis a two-cycle
instruction.
Description:
Words:
Cycles:
1
1
See LCALLfor calls outside 8K memory
space.
Q Cycle Activity:
Q1
Words:
Cycles:
1
2
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
and if
specified
WREG
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
'k'<7:0>,
Push PC to
stack
Process
Data
Write to PC
CLRF
FLAG_REG, 1
Example:
Before Instruction
FLAG_REG
No
No
operation
No
operation
No
operation
=
=
0x5A
0x01
operation
WREG
After Instruction
FLAG_REG
WREG
HERE
CALL THERE
Example:
=
=
0x00
0x01
Before Instruction
PC Address(HERE)
=
After Instruction
PC
=
Address(THERE)
TOS =
Address (HERE + 1)
1998 Microchip Technology Inc.
DS30289A-page 205
PIC17C7XX
CLRWDT
Syntax:
Clear Watchdog Timer
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 255
[ label ] CLRWDT
None
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
00h → WDT
0 → WDT postscaler,
1 → TO
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
1 → PD
0001
001d
ffff
ffff
Status Affected:
Encoding:
TO, PD
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
Description:
0000
0000
0000
0100
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the postscaler
of the WDT. Status bits TO and PD are
set.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
COMF
REG1,0
Example:
Before Instruction
CLRWDT
Example:
REG1
=
0x13
Before Instruction
After Instruction
WDT counter
=
?
REG1
=
0x13
WREG
=
0xEC
After Instruction
WDT counter
WDT Postscaler
TO
=
=
=
=
0x00
0
1
1
PD
DS30289A-page 206
1998 Microchip Technology Inc.
PIC17C7XX
Compare f with WREG,
skip if f = WREG
Compare f with WREG,
skip if f > WREG
CPFSEQ
Syntax:
CPFSGT
Syntax:
[ label ] CPFSEQ
f
[ label ] CPFSGT
f
Operands:
Operation:
0 ≤ f ≤ 255
Operands:
Operation:
0 ≤ f ≤ 255
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
(f) − (WREG),
skip if (f) > (WREG)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
0010
ffff
ffff
0011
0001
ffff
ffff
Compares the contents of data memory
location 'f' to the contents of the WREG
by performing an unsigned subtraction.
Description:
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
Description:
If the contents of 'f' are greater than the
contents of WREG then the fetched
instruction is discarded and an NOP is
executed instead making this a
two-cycle instruction.
If 'f' = WREG then the fetched instruc-
tion is discarded and an NOP is exe-
cuted instead making this a two-cycle
instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1 (2)
1 (2)
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
No
operation
Decode
Read
register 'f'
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NEQUAL
EQUAL
CPFSEQ REG
:
:
Example:
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Example:
Before Instruction
PC Address
Before Instruction
=
=
=
HERE
PC
WREG
=
=
Address (HERE)
WREG
REG
?
?
?
After Instruction
After Instruction
If REG
>
=
≤
WREG;
Address (GREATER)
WREG;
If REG
=
=
≠
=
WREG;
Address (EQUAL)
WREG;
PC
If REG
PC
PC
If REG
PC
=
Address (NGREATER)
Address (NEQUAL)
1998 Microchip Technology Inc.
DS30289A-page 207
PIC17C7XX
Compare f with WREG,
DAW
Decimal Adjust WREG Register
[label] DAW f,s
CPFSLT
Syntax:
skip if f < WREG
[ label ] CPFSLT
0 ≤ f ≤ 255
Syntax:
Operands:
f
0 ≤ f ≤ 255
Operands:
Operation:
s
[0,1]
(f) – (WREG),
skip if (f) < (WREG)
(unsigned comparison)
If [WREG<3:0> >9] .OR. [DC = 1] then
WREG<3:0> + 6 → f<3:0>, s<3:0>;
else
Operation:
Status Affected:
Encoding:
None
WREG<3:0> → f<3:0>, s<3:0>;
0011
0000
ffff
ffff
If [WREG<7:4> >9] .OR. [C = 1] then
WREG<7:4> + 6 → f<7:4>, s<7:4>
else
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
Description:
WREG<7:4> → f<7:4>, s<7:4>
If the contents of 'f' are less than the
contents of WREG, then the fetched
instruction is discarded and an NOP is
executed instead making this a
two-cycle instruction.
Status Affected:
Encoding:
C
0010
111s
ffff
ffff
DAW adjusts the eight bit value in
WREG resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
Description:
Words:
Cycles:
1
1 (2)
s = 0: Result is placed in Data
memory location 'f' and
Q Cycle Activity:
Q1
Q2
Q3
Q4
WREG.
Decode
Read
register 'f'
Process
Data
No
operation
s = 1: Result is placed in Data
memory location 'f'.
If skip:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
Decode
Read
register 'f'
Process
Data
Write
register 'f'
and other
specified
register
Before Instruction
PC
W
=
=
Address (HERE)
?
DAW
REG1, 0
Example1:
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
WREG;
Address (LESS)
WREG;
Before Instruction
WREG
REG1
C
=
=
=
=
0xA5
??
0
Address (NLESS)
DC
0
After Instruction
WREG
REG1
C
=
=
=
=
0x05
0x05
1
DC
0
Example 2:
Before Instruction
WREG
REG1
C
=
=
=
=
0xCE
??
0
DC
0
After Instruction
WREG
REG1
C
=
=
=
=
0x24
0x24
1
DC
0
DS30289A-page 208
1998 Microchip Technology Inc.
PIC17C7XX
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 255
DECFSZ
Syntax:
Decrement f, skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 255
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) – 1 → (dest)
Operation:
(f) – 1 → (dest);
skip if result = 0
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
None
0000
011d
ffff
ffff
0001
011d
ffff
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Description:
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Words:
Cycles:
1
1
If the result is 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead mak-
ing it a two-cycle instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
Words:
Cycles:
1
destination
1(2)
DECF
CNT,
1
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
CNT
Z
=
=
0x01
0
Decode
Read
register 'f'
Process
Data
Write to
destination
After Instruction
If skip:
Q1
CNT
=
0x00
1
Q2
Q3
Q4
Z
=
No
No
No
No
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT, 1
HERE
Example:
NZERO
ZERO
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT - 1
0;
Address (HERE)
0;
Address (NZERO)
1998 Microchip Technology Inc.
DS30289A-page 209
PIC17C7XX
DCFSNZ
Syntax:
Decrement f, skip if not 0
GOTO
Unconditional Branch
[label] DCFSNZ f,d
Syntax:
[ label ] GOTO
0 ≤ k ≤ 8191
k
Operands:
0 ≤ f ≤ 255
Operands:
Operation:
d
[0,1]
k → PC<12:0>;
Operation:
(f) – 1 → (dest);
skip if not 0
k<12:8> → PCLATH<4:0>,
PC<15:13> → PCLATH<7:5>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
011d
ffff
ffff
110k
kkkk
kkkk
kkkk
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
GOTOallows an unconditional branch
anywhere within an 8K page boundary.
The thirteen bit immediate value is
loaded into PC bits <12:0>. Then the
upper eight bits of PC are loaded into
PCLATH. GOTOis always a two-cycle
instruction.
Description:
Description:
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead mak-
ing it a two-cycle instruction.
Words:
Cycles:
1
2
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'k'
Process
Data
Write to PC
Decode
Read
register 'f'
Process
Data
Write to
destination
No
No
No
No
operation
operation
operation
operation
If skip:
Q1
Q2
Q3
Q4
GOTO THERE
Example:
No
No
No
No
operation
operation
operation
operation
After Instruction
PC Address (THERE)
=
HERE
ZERO
NZERO
DCFSNZ TEMP, 1
:
:
Example:
Before Instruction
TEMP_VALUE
=
?
After Instruction
TEMP_VALUE
If TEMP_VALUE
PC
=
=
=
≠
=
TEMP_VALUE - 1,
0;
Address (ZERO)
0;
Address (NZERO)
If TEMP_VALUE
PC
DS30289A-page 210
1998 Microchip Technology Inc.
PIC17C7XX
INCF
Increment f
INCFSZ
Syntax:
Increment f, skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 255
Syntax:
Operands:
[ label ] INCF f,d
0 ≤ f ≤ 255
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) + 1 → (dest)
Operation:
(f) + 1 → (dest)
skip if result = 0
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
None
0001
010d
ffff
ffff
0001
111d
ffff
ffff
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Words:
Cycles:
1
1
If the result is 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making
it a two-cycle instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register 'f'
Process
Data
Write to
destination
1(2)
Q Cycle Activity:
Q1
INCF
CNT, 1
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register 'f'
Process
Data
Write to
destination
CNT
Z
C
=
=
=
0xFF
0
?
If skip:
Q1
Q2
Q3
Q4
After Instruction
No
operation
No
operation
No
operation
No
operation
CNT
Z
C
=
=
=
0x00
1
1
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
1998 Microchip Technology Inc.
DS30289A-page 211
PIC17C7XX
INFSNZ
Syntax:
Increment f, skip if not 0
IORLW
Inclusive OR Literal with WREG
[label] INFSNZ f,d
Syntax:
[ label ] IORLW k
Operands:
0 ≤ f ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
d
[0,1]
(WREG) .OR. (k) → (WREG)
Operation:
(f) + 1 → (dest),
skip if not 0
Z
1011
0011
kkkk
kkkk
Status Affected:
Encoding:
None
The contents of WREG are OR’ed with
the eight bit literal 'k'. The result is
placed in WREG.
0010
010d
ffff
ffff
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
Words:
Cycles:
1
1
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making
it a two-cycle instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1(2)
IORLW
0x35
Example:
Q Cycle Activity:
Q1
Before Instruction
WREG
=
0x9A
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
After Instruction
WREG
=
0xBF
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
HERE
ZERO
NZERO
INFSNZ REG, 1
Example:
Before Instruction
REG
=
REG
After Instruction
REG
If REG
PC
If REG
PC
=
=
=
=
=
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
DS30289A-page 212
1998 Microchip Technology Inc.
PIC17C7XX
IORWF
Inclusive OR WREG with f
[ label ] IORWF f,d
0 ≤ f ≤ 255
LCALL
Long Call
Syntax:
Syntax:
[ label ] LCALL
0 ≤ k ≤ 255
k
Operands:
Operands:
Operation:
d
[0,1]
PC + 1 → TOS;
Operation:
(WREG) .OR. (f) → (dest)
k → PCL, (PCLATH) → PCH
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
0000
100d
ffff
ffff
1011
0111
kkkk
kkkk
Inclusive OR WREG with register 'f'. If
'd' is 0 the result is placed in WREG. If
'd' is 1 the result is placed back in regis-
ter 'f'.
LCALLallows an unconditional subrou-
tine call to anywhere within the 64K pro-
gram memory space.
Description:
Description:
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit desti-
nation address is then loaded into the
program counter. The lower 8-bits of
the destination address is embedded in
the instruction. The upper 8-bits of PC
is loaded from PC high holding latch,
PCLATH.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Words:
Cycles:
1
2
IORWF RESULT, 0
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
RESULT
=
0x13
0x91
WREG
=
Decode
Read
literal 'k'
Process
Data
Write
register PCL
After Instruction
No
operation
No
operation
No
operation
No
operation
RESULT
=
0x13
0x93
WREG
=
MOVLW HIGH(SUBROUTINE)
MOVPF WREG, PCLATH
Example:
LCALL LOW(SUBROUTINE)
Before Instruction
SUBROUTINE
PC
=
=
16-bit Address
?
After Instruction
PC
=
Address (SUBROUTINE)
1998 Microchip Technology Inc.
DS30289A-page 213
PIC17C7XX
MOVFP
Syntax:
Move f to p
MOVLB
Move Literal to low nibble in BSR
[label] MOVFP f,p
Syntax:
[ label ] MOVLB
0 ≤ k ≤ 15
k
Operands:
0 ≤ f ≤ 255
0 ≤ p ≤ 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (BSR<3:0>)
None
Operation:
(f) → (p)
Status Affected:
Encoding:
None
1011
1000
uuuu
kkkk
011p
pppp
ffff
ffff
The four bit literal 'k' is loaded in the
Bank Select Register (BSR). Only the
low 4-bits of the Bank Select Register
are affected. The upper half of the BSR
is unchanged. The assembler will
encode the “u” fields as '0'.
Move data from data memory location 'f'
to data memory location 'p'. Location 'f'
can be anywhere in the 256 byte data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Description:
Either ’p' or 'f' can be WREG (a useful
special situation).
Words:
Cycles:
1
1
MOVFPis particularly useful for transfer-
ring a data memory location to a periph-
eral register (such as the transmit buffer
or an I/O port). Both 'f' and 'p' can be
indirectly addressed.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
Process
Data
Write literal
'k' to
literal 'k'
Words:
Cycles:
1
1
BSR<3:0>
MOVLB
5
Example:
Q Cycle Activity:
Q1
Before Instruction
BSR register
Q2
Q3
Q4
=
=
0x22
Decode
Read
register 'f'
Process
Data
Write
register 'p'
After Instruction
BSR register
0x25 (Bank 5)
MOVFP
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x33,
0x11
After Instruction
REG1
=
=
0x33,
0x33
REG2
DS30289A-page 214
1998 Microchip Technology Inc.
PIC17C7XX
Move Literal to high nibble in
BSR
MOVLW
Move Literal to WREG
MOVLR
Syntax:
[ label ] MOVLW
0 ≤ k ≤ 255
k → (WREG)
None
k
Syntax:
[ label ] MOVLR
0 ≤ k ≤ 15
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
k → (BSR<7:4>)
Status Affected: None
1011
0000
kkkk
kkkk
Encoding:
1011
101x
kkkk
uuuu
The eight bit literal 'k' is loaded into
WREG.
The 4-bit literal 'k' is loaded into the
most significant 4-bits of the Bank
Select Register (BSR). Only the high
4-bits of the Bank Select Register
are affected. The lower half of the
BSR is unchanged. The assembler
will encode the “u” fields as 0.
Description:
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1
MOVLW
0x5A
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
After Instruction
WREG
Decode
Read literal
'k'
Process
Data
Write
literal 'k' to
BSR<7:4>
=
0x5A
MOVLR
5
Example:
Before Instruction
BSR register
=
=
0x22
0x52
After Instruction
BSR register
1998 Microchip Technology Inc.
DS30289A-page 215
PIC17C7XX
MOVPF
Syntax:
Move p to f
MOVWF
Move WREG to f
[ label ] MOVWF
0 ≤ f ≤ 255
[label] MOVPF p,f
Syntax:
f
Operands:
0 ≤ f ≤ 255
0 ≤ p ≤ 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
(WREG) → (f)
None
Operation:
(p) → (f)
Status Affected:
Encoding:
Z
0000
0001
ffff
ffff
010p
pppp
ffff
ffff
Move data from WREG to register 'f'.
Location 'f' can be anywhere in the 256
byte data space.
Move data from data memory location
'p' to data memory location 'f'. Location
'f' can be anywhere in the 256 byte data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Description:
Words:
Cycles:
1
1
Either 'p' or 'f' can be WREG (a useful
special situation).
Q Cycle Activity:
Q1
Q2
Q3
Q4
MOVPFis particularly useful for transfer-
ring a peripheral register (e.g. the timer
or an I/O port) to a data memory loca-
tion. Both 'f' and 'p' can be indirectly
addressed.
Decode
Read
register 'f'
Process
Data
Write
register 'f'
MOVWF
REG
Example:
Words:
Cycles:
1
1
Before Instruction
WREG
=
0x4F
0xFF
REG
=
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
WREG
=
0x4F
0x4F
Decode
Read
register 'p'
Process
Data
Write
register 'f'
REG
=
MOVPF
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x11
0x33
After Instruction
REG1
=
=
0x11
0x11
REG2
DS30289A-page 216
1998 Microchip Technology Inc.
PIC17C7XX
MULLW
Multiply Literal with WREG
MULWF
Multiply WREG with f
Syntax:
[ label ] MULLW
k
Syntax:
[ label ] MULWF
f
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
Operation:
0 ≤ f ≤ 255
(k x WREG) → PRODH:PRODL
(WREG x f) → PRODH:PRODL
Status Affected: None
Status Affected: None
Encoding:
1011
1100
kkkk
kkkk
Encoding:
0011
0100
ffff
ffff
An unsigned multiplication is carried
out between the contents of WREG
and the 8-bit literal 'k'. The 16-bit
result is placed in PRODH:PRODL
register pair. PRODH contains the
high byte.
An unsigned multiplication is carried
out between the contents of WREG
and the register file location 'f'. The
16-bit result is stored in the
PRODH:PRODL register pair.
PRODH contains the high byte.
Description:
Description:
WREG is unchanged.
Both WREG and 'f' are unchanged.
None of the status flags are affected.
None of the status flags are affected.
Note that neither overflow nor carry
is possible in this operation. A zero
result is possible but not detected.
Note that neither overflow nor carry
is possible in this operation. A zero
result is possible but not detected.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write
Decode
Read
register 'f'
Process
Data
Write
registers
PRODH:
PRODL
registers
PRODH:
PRODL
MULLW
0xC4
MULWF
REG
Example:
Example:
Before Instruction
Before Instruction
WREG
PRODH
PRODL
=
=
=
0xE2
?
?
WREG
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
After Instruction
WREG
After Instruction
WREG
=
=
=
0xC4
0xAD
0x08
PRODH
PRODL
=
=
=
=
0xC4
0xB5
0x8A
0x94
REG
PRODH
PRODL
1998 Microchip Technology Inc.
DS30289A-page 217
PIC17C7XX
NEGW
Negate W
NOP
No Operation
[ label ] NOP
None
Syntax:
[label] NEGW f,s
Syntax:
Operands:
0 ≤ f ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
s
[0,1]
No operation
None
Operation:
WREG + 1 → (f);
WREG + 1 → s
0000
0000
0000
0000
Status Affected:
Encoding:
OV, C, DC, Z
No operation.
0010
110s
ffff
ffff
1
1
WREG is negated using two’s comple-
ment. If 's' is 0 the result is placed in
WREG and data memory location 'f'. If
's' is 1 the result is placed only in data
memory location 'f'.
Description:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
No
Q4
Decode
No
No
operation
Words:
Cycles:
1
1
operation
operation
Q Cycle Activity:
Q1
Example:
None.
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
and other
specified
register
NEGW
REG,0
Example:
Before Instruction
WREG
REG
=
=
0011 1010
1010 1011
[0x3A],
[0xAB]
After Instruction
WREG
REG
=
=
1100 0110
1100 0110
[0xC6]
[0xC6]
DS30289A-page 218
1998 Microchip Technology Inc.
PIC17C7XX
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RETLW
Return Literal to WREG
Syntax:
Syntax:
[ label ] RETLW k
Operands:
Operation:
Operands:
Operation:
0 ≤ k ≤ 255
TOS → (PC);
k → (WREG); TOS → (PC);
0 → GLINTD;
PCLATH is unchanged
PCLATH is unchanged.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
GLINTD
1011
0110
kkkk
kkkk
0000
0000
0000
0101
WREG is loaded with the eight bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Description:
Return from Interrupt. Stack is POP’ed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
Description:
Words:
Cycles:
1
2
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Process
Data
POP PC
from stack,
Write to
literal 'k'
Decode
No
operation
Clear
GLINTD
POP PC
from stack
WREG
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
RETFIE
Example:
CALL TABLE ; WREG contains table
Example:
After Interrupt
;
;
;
offset value
WREG now has
table value
PC
GLINTD
=
=
TOS
0
:
TABLE
ADDWF PC
; WREG = offset
; Begin table
;
RETLW k0
RETLW k1
:
:
RETLW kn
; End of table
Before Instruction
WREG
=
0x07
After Instruction
WREG
=
value of k7
1998 Microchip Technology Inc.
DS30289A-page 219
PIC17C7XX
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
[ label ] RLCF f,d
0 ≤ f ≤ 255
Syntax:
[ label ] RETURN
None
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
TOS → PC;
None
Operation:
f<n> → d<n+1>;
f<7> → C;
C → d<0>
0000
0000
0000
0010
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter.
Status Affected:
Encoding:
C
0001
101d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
C
Decode
No
operation
Process
Data
POP PC
from stack
Words:
Cycles:
1
1
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Read
register 'f'
Q3
Process
Data
Q4
RETURN
Example:
Decode
Write to
destination
After Interrupt
PC = TOS
RLCF
REG,0
Example:
Before Instruction
REG
=
1110 0110
C
=
0
After Instruction
REG
WREG
C
=
=
=
1110 0110
1100 1100
1
DS30289A-page 220
1998 Microchip Technology Inc.
PIC17C7XX
RLNCF
Rotate Left f (no carry)
[ label ] RLNCF f,d
0 ≤ f ≤ 255
RRCF
Rotate Right f through Carry
[ label ] RRCF f,d
0 ≤ f ≤ 255
Syntax:
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
f<n> → d<n+1>;
f<7> → d<0>
Operation:
f<n> → d<n-1>;
f<0> → C;
C → d<7>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
C
0010
001d
ffff
ffff
0001
100d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
stored back in register 'f'.
Description:
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Description:
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write to
destination
Q2
Read
register 'f'
Q3
Process
Data
Q4
Decode
Write to
destination
RLNCF
REG, 1
Example:
Before Instruction
RRCF REG1,0
Example:
C
=
0
REG
=
1110 1011
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
C
=
REG
=
1101 0111
After Instruction
REG1
WREG
C
=
=
=
1110 0110
0111 0011
0
1998 Microchip Technology Inc.
DS30289A-page 221
PIC17C7XX
RRNCF
Syntax:
Rotate Right f (no carry)
SETF
Set f
[ label ] RRNCF f,d
Syntax:
Operands:
[ label ] SETF f,s
Operands:
0 ≤ f ≤ 255
0 ≤ f ≤ 255
d
[0,1]
s
[0,1]
Operation:
f<n> → d<n-1>;
f<0> → d<7>
Operation:
FFh → f;
FFh → d
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
000d
ffff
ffff
0010
101s
ffff
ffff
The contents of register 'f' are rotated
one bit to the right. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed back in register 'f'.
If 's' is 0, both the data memory location
'f' and WREG are set to FFh. If 's' is 1
only the data memory location 'f' is set
to FFh.
Description:
Description:
Words:
Cycles:
1
1
register f
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write
register 'f'
and other
specified
register
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
RRNCF
REG, 1
Example 1:
SETF
REG, 0
Example1:
Before Instruction
Before Instruction
WREG
REG
=
=
?
REG
WREG
=
=
0xDA
0x05
1101 0111
After Instruction
After Instruction
WREG
REG
=
=
0
REG
WREG
=
=
0xFF
0xFF
1110 1011
Example2:
SETF
REG, 1
RRNCF
Before Instruction
REG, 0
Example 2:
Before Instruction
REG
WREG
=
=
0xDA
0x05
WREG
=
?
REG
=
1101 0111
After Instruction
After Instruction
REG
WREG
=
=
0xFF
0x05
WREG
REG
=
=
1110 1011
1101 0111
DS30289A-page 222
1998 Microchip Technology Inc.
PIC17C7XX
SLEEP
SUBLW
Subtract WREG from Literal
Enter SLEEP mode
Syntax:
[ label ] SUBLW k
Syntax:
[ label ] SLEEP
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
Operation:
k – (WREG) → (WREG)
00h → WDT;
0 → WDT postscaler;
1 → TO;
OV, C, DC, Z
1011
0010
kkkk
kkkk
0 → PD
WREG is subtracted from the eight bit
literal 'k'. The result is placed in
WREG.
Status Affected:
Encoding:
TO, PD
0000
0000
0000
0011
Words:
Cycles:
1
1
The power-down status bit (PD) is
cleared.The time-out status bit (TO) is
set. Watchdog Timer and its
Description:
Q Cycle Activity:
Q1
postscaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1
SUBLW 0x02
Example 1:
Q Cycle Activity:
Q1
Before Instruction
WREG
=
1
?
Q2
Q3
Q4
C
=
Decode
No
operation
Process
Data
Go to
sleep
After Instruction
WREG
C
Z
=
=
=
1
1
0
; result is positive
SLEEP
Example:
Before Instruction
Example 2:
TO
=
?
Before Instruction
PD
=
?
WREG
C
=
=
2
?
After Instruction
TO
PD
=
=
1 †
0
After Instruction
WREG
=
=
=
0
1
1
†
If WDT causes wake-up, this bit is cleared
C
Z
; result is zero
Example 3:
Before Instruction
WREG
C
=
=
3
?
After Instruction
WREG
C
Z
=
=
=
FF ; (2’s complement)
0
0
; result is negative
1998 Microchip Technology Inc.
DS30289A-page 223
PIC17C7XX
SUBWF
Syntax:
Subtract WREG from f
Subtract WREG from f with
Borrow
SUBWFB
[ label ] SUBWF f,d
Syntax:
[ label ] SUBWFB f,d
Operands:
0 ≤ f ≤ 255
d
[0,1]
Operands:
0 ≤ f ≤ 255
d
[0,1]
Operation:
(f) – (W) → (dest)
Operation:
(f) – (W) – C → (dest)
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
OV, C, DC, Z
0000
010d
ffff
ffff
0000
001d
ffff
ffff
Subtract WREG from register 'f' (2’s
complement method). If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s comple-
ment method). If 'd' is 0 the result is
stored in WREG. If 'd' is 1 the result is
stored back in register 'f'.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write to
Q2
Q3
Q4
destination
Decode
Read
register 'f'
Process
Data
Write to
destination
SUBWF
REG1, 1
Example 1:
Before Instruction
SUBWFB REG1, 1
Example 1:
REG1
WREG
C
=
=
=
3
2
?
Before Instruction
REG1
WREG
C
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
After Instruction
REG1
WREG
C
=
=
=
=
1
2
1
0
After Instruction
; result is positive
REG1
WREG
C
=
=
=
=
0x0C
0x0D
1
(0000 1011)
(0000 1101)
; result is positive
Z
Example 2:
Before Instruction
Z
0
Example2:
SUBWFB REG1,0
REG1
WREG
C
=
=
=
2
2
?
Before Instruction
REG1
WREG
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
After Instruction
REG1
WREG
C
=
=
=
=
0
2
1
1
After Instruction
; result is zero
REG1
WREG
C
=
=
=
=
0x1B
0x00
1
(0001 1011)
Z
; result is zero
Example 3:
Before Instruction
Z
1
Example3:
SUBWFB REG1,1
REG1
WREG
C
=
=
=
1
2
?
Before Instruction
REG1
WREG
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
After Instruction
REG1
WREG
C
=
=
=
=
FF
2
0
After Instruction
; result is negative
REG1
WREG
C
=
=
=
=
0xF5
0x0E
0
(1111 0100) [2’s comp]
(0000 1101)
; result is negative
Z
0
Z
0
DS30289A-page 224
1998 Microchip Technology Inc.
PIC17C7XX
SWAPF
Syntax:
Swap f
TABLRD
Syntax:
Table Read
[ label ] SWAPF f,d
[ label ] TABLRD t,i,f
Operands:
0 ≤ f ≤ 255
Operands:
0 ≤ f ≤ 255
d
[0,1]
i
t
[0,1]
[0,1]
Operation:
f<3:0> → dest<7:4>;
f<7:4> → dest<3:0>
Operation:
If t = 1,
TBLATH → f;
If t = 0,
TBLATL → f;
Status Affected:
Encoding:
None
0001
110d
ffff
ffff
Prog Mem (TBLPTR) → TBLAT;
If i = 1,
TBLPTR + 1 → TBLPTR
If i = 0,
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed in register 'f'.
Description:
TBLPTR is unchanged
Words:
Cycles:
1
1
Status Affected:
Encoding:
None
1010
10ti
ffff
ffff
Q Cycle Activity:
Q1
Q2
Q3
Q4
1. A byte of the table latch (TBLAT)
is moved to register file 'f'.
Description:
Decode
Read
Process
Data
Write to
destination
If t = 1: the high byte is moved;
If t = 0: the low byte is moved
register 'f'
2. Then the contents of the program
memory location pointed to by
SWAPF
REG,
0
Example:
the
16-bit
Table
Pointer
Before Instruction
(TBLPTR) is loaded into the
16-bit Table Latch (TBLAT).
REG
=
0x53
0x35
After Instruction
3. If i = 1: TBLPTR is incremented;
If i = 0: TBLPTR is not
incremented
REG
=
Words:
Cycles:
1
2 (3 cycle if f = PCL)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
Process
Data
Write
register 'f'
TBLATH or
TBLATL
No
No
No
No
operation
operation
(Table Pointer
on Address
bus)
operation
operation
(OE goes low)
1998 Microchip Technology Inc.
DS30289A-page 225
PIC17C7XX
TABLRD
Table Read
TABLWT
Syntax:
Table Write
TABLRD 1, 1, REG ;
Example1:
[ label ] TABLWT t,i,f
Before Instruction
Operands:
0 ≤ f ≤ 255
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
i
t
[0,1]
[0,1]
Operation:
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH;
TBLAT → Prog Mem (TBLPTR);
If i = 1,
MEMORY(TBLPTR)
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0xAA
0x12
0x34
0xA357
0x5678
TBLPTR + 1 → TBLPTR
If i = 0,
MEMORY(TBLPTR)
TBLPTR is unchanged
TABLRD 0, 0, REG ;
Example2:
Status Affected:
Encoding:
None
Before Instruction
1010
11ti
ffff
ffff
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
1. Load value in ’f’ into 16-bit table
latch (TBLAT)
Description:
If t = 1: load into high byte;
If t = 0: load into low byte
MEMORY(TBLPTR)
After Instruction (table write completion)
2. The contents of TBLAT is written
to the program memory location
pointed to by TBLPTR
REG
=
=
=
=
=
0x55
TBLATH
0x12
TBLATL
0x34
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle
If TBLPTR points to an internal
EPROM location, then the
instruction is terminated when
an interrupt is received.
TBLPTR
MEMORY(TBLPTR)
0xA356
0x1234
Note: The MCLR/VPP pin must be at the programming
voltage for successful programming of internal
memory.
If MCLR/VPP = VDD
the programming sequence of internal memory
will be interrupted. A short write will occur (2 TCY).
The internal memory location will not be affected.
3. The TBLPTR can be automati-
cally incremented
If i = 1; TBLPTR is not
incremented
If i = 0; TBLPTR is incremented
Words:
1
Cycles:
2 (many if write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register
TBLATH or
TBLATL
No
No
No
No
operation
operation
(Table Pointer
on Address
bus)
operation
operation
(Table Latch on
Address bus,
WR goes low)
DS30289A-page 226
1998 Microchip Technology Inc.
PIC17C7XX
TABLWT
Table Write
TLRD
Table Latch Read
TABLWT 1, 1, REG
Example1:
Syntax:
Operands:
[ label ] TLRD t,f
Before Instruction
0 ≤ f ≤ 255
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0xFFFF
t
[0,1]
If t = 0,
TBLATL → f;
If t = 1,
TBLATH → f
None
1010
Operation:
MEMORY(TBLPTR)
After Instruction (table write completion)
Status Affected:
Encoding:
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0x53
0x55
0xA357
0x5355
00tx
ffff
ffff
Read data from 16-bit table latch
(TBLAT) into file register 'f'. Table Latch
is unaffected.
Description:
MEMORY(TBLPTR - 1)
TABLWT 0, 0, REG
Example 2:
If t = 1; high byte is read
If t = 0; low byte is read
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0xFFFF
This instruction is used in conjunction
with TABLRDto transfer data from pro-
gram memory to data memory.
Words:
Cycles:
1
1
MEMORY(TBLPTR)
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x53
0xA356
0xAA53
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
Process
Data
Write
register 'f'
MEMORY(TBLPTR)
TBLATH or
TBLATL
Program
Memory
Data
15
15
0
0
Memory
TLRD
t, RAM
Example:
TBLPTR
Before Instruction
t
=
=
=
0
?
8
7
RAM
TBLAT
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
16 bits
8 bits
TBLAT
After Instruction
RAM
=
0xAF
TBLAT
=
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
Before Instruction
t
=
=
=
1
?
RAM
TBLAT
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
After Instruction
RAM
=
0x00
TBLAT
=
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
Program
Memory
Data
Memory
15
15
0
0
TBLPTR
8
7
16 bits
8 bits
TBLAT
1998 Microchip Technology Inc.
DS30289A-page 227
PIC17C7XX
TLWT
Table Latch Write
TSTFSZ
Test f, skip if 0
[ label ] TSTFSZ f
0 ≤ f ≤ 255
Syntax:
Operands:
[ label ] TLWT t,f
Syntax:
0 ≤ f ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
t
[0,1]
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH
None
1010
skip if f = 0
Operation:
None
0011
0011
ffff
ffff
If 'f' = 0, the next instruction, fetched
during the current instruction execution,
is discarded and an NOP is executed
making this a two-cycle instruction.
Status Affected:
Encoding:
01tx
ffff
ffff
Data from file register 'f' is written into
the 16-bit table latch (TBLAT).
Description:
Words:
Cycles:
1
1 (2)
If t = 1; high byte is written
If t = 0; low byte is written
Q Cycle Activity:
Q1
Q2
Q3
Q4
This instruction is used in conjunction
with TABLWTto transfer data from data
memory to program memory.
Decode
Read
Process
Data
No
operation
register 'f'
If skip:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register
TBLATH or
TBLATL
HERE
NZERO
ZERO
TSTFSZ CNT
:
:
Example:
Before Instruction
PC = Address (HERE)
TLWT
t, RAM
Example:
After Instruction
If CNT
PC
If CNT
PC
Before Instruction
=
=
≠
=
0x00,
Address (ZERO)
0x00,
t
=
=
=
0
RAM
TBLAT
0xB7
0x0000 (TBLATH = 0x00)
(TBLATL = 0x00)
Address (NZERO)
After Instruction
RAM
=
0xB7
TBLAT
=
0x00B7 (TBLATH = 0x00)
(TBLATL = 0xB7)
Before Instruction
t
=
=
=
1
RAM
TBLAT
0xB7
0x0000 (TBLATH = 0x00)
(TBLATL = 0x00)
After Instruction
RAM
=
0xB7
TBLAT
=
0xB700 (TBLATH = 0xB7)
(TBLATL = 0x00)
DS30289A-page 228
1998 Microchip Technology Inc.
PIC17C7XX
Exclusive OR Literal with
WREG
XORWF
Syntax:
Exclusive OR WREG with f
[ label ] XORWF f,d
0 ≤ f ≤ 255
XORLW
Syntax:
[ label ] XORLW k
Operands:
d
[0,1]
Operands:
Operation:
Status Affected:
Encoding:
0 ≤ k ≤ 255
Operation:
(WREG) .XOR. (f) → (dest)
(WREG) .XOR. k → (WREG)
Status Affected:
Encoding:
Z
Z
0000
110d
ffff
ffff
1011
0100
kkkk
kkkk
Exclusive OR the contents of WREG
with register 'f'. If 'd' is 0 the result is
stored in WREG. If 'd' is 1 the result is
stored back in the register 'f'.
Description:
The contents of WREG are XOR’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
Description:
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Decode
Read
register 'f'
Process
Data
Write to
destination
XORLW 0xAF
= 0xB5
Example:
XORWF
REG, 1
Example:
Before Instruction
Before Instruction
WREG
After Instruction
WREG
REG
WREG
=
=
0xAF
0xB5
=
0x1A
After Instruction
REG
WREG
=
=
0x1A
0xB5
1998 Microchip Technology Inc.
DS30289A-page 229
PIC17C7XX
NOTES:
DS30289A-page 230
1998 Microchip Technology Inc.
PIC17C7XX
19.3
ICEPIC: Low-cost PICmicro™
In-Circuit Emulator
19.0 DEVELOPMENT SUPPORT
19.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER /PICMASTER CE Real-Time
In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
19.4
PRO MATE II: Universal Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH −MP)
19.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
gram
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC14C000, PIC12CXXX,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
19.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use,
low-cost prototype programmer. It connects to the PC
via one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip micro-
controllers.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be sup-
ported with an adapter socket. PICSTART Plus is CE
compliant.
The PICMASTER Emulator System has been
designed as
a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1998 Microchip Technology Inc.
DS30289A-page 231
PIC17C7XX
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
19.6
PICDEM-1 Low-Cost PICmicro™
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on
a PRO MATE II or
19.9
MPLAB™ Integrated Development
Environment Software
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
19.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
19.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
19.10 Assembler (MPASM)
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
The MPASM Universal Macro Assembler is
a
PC-hosted symbolic assembler. It supports all micro-
controller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
DS30289A-page 232
1998 Microchip Technology Inc.
PIC17C7XX
MPASM has the following features to assist in develop-
ing software for specific use applications.
19.14 MP-DriveWay – Application Code
Generator
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
MP-DriveWay is an easy-to-use Windows-based Appli-
cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Micro-
chip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
19.15 SEEVAL Evaluation and
Programming System
19.11 Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The
input/output radix can be set by the user and the exe-
cution can be performed in; single step, execute until
break, or in a trace mode.
The Total Endurance
Disk is included to aid in
trade-off analysis and reliability calculations. The total
kit can significantly reduce time-to-market and result in
an optimized system.
19.16 KEELOQ Evaluation and
Programming Tools
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out-
side of the laboratory environment making it an excel-
lent multi-project software development tool.
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products.The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
19.12 C Compiler (MPLAB-C17)
The MPLAB-C Code Development System is
a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
19.13 Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for imple-
menting more complex systems.
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
1998 Microchip Technology Inc.
DS30289A-page 233
24CXX
PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
PIC17C7XX
25CXX
93CXX HCSXXX
EMULATOR PRODUCTS
PICMASTER
PICMASTER-CE
/
(PIC17C75X only)
In-Circuit Emulator
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
MPLAB™-ICE
ICEPIC Low-Cost
In-Circuit Emulator
SOFTWARE PRODUCTS
MPLAB
Integrated
Development
Environment
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
MPLAB C17
Compiler
fuzzyTECH -MP
Explorer/Edition
Fuzzy Logic Dev. Tool
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
MP-DriveWay
Applications
Code Generator
Total Endurance
Software Model
ü
PROGRAMMERS
PICSTART Plus
Low-Cost
Universal Dev. Kit
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
PRO MATE II
Universal Programmer
ü
ü
ü
ü
ü
KEELOQ Programmer
DEMO BOARDS
SEEVAL Designers Kit
PICDEM-1
ü
ü
ü
ü
PICDEM-2
ü
ü
PICDEM-3
ü
KEELOQ Evaluation Kit
ü
PIC17C7XX
20.0 PIC17C7 MXX ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias............................................................................................................. -55˚C to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on VDD with respect to VSS ............................................................................................................. 0V to +7.5V
Voltage on MCLR with respect to VSS (Note 2)..........................................................................................-0.3V to +14V
Voltage on RA2 and RA3 with respect to VSS............................................................................................-0.3V to +8.5V
Voltage on all other pins with respect to VSS .................................................................................... -0.3V to VDD + 0.3V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin(s) - total (@ 70˚C) ............................................................................................500 mA
Maximum current into VDD pin(s) - total (@ 70˚C) ...............................................................................................500 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA
Maximum output current sunk by any I/O pin (except RA2 and RA3).....................................................................35 mA
Maximum output current sunk by RA2 or RA3 pins ................................................................................................60 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA and PORTB (combined).................................................................................150 mA
Maximum current sourced by PORTA and PORTB (combined)............................................................................100 mA
Maximum current sunk by PORTC, PORTD and PORTE (combined)..................................................................150 mA
Maximum current sourced by PORTC, PORTD and PORTE (combined).............................................................100 mA
Maximum current sunk by PORTF and PORTG (combined) ................................................................................150 mA
Maximum current sourced by PORTF and PORTG (combined)...........................................................................100 mA
Maximum current sunk by PORTH and PORTJ (combined).................................................................................150 mA
Maximum current sourced by PORTH and PORTJ (combined)............................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at those or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 235
PIC17C7XX
TABLE 20-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
JW Devices
OSC
PIC17LC7XX-08
PIC17C7XX-16
PIC17C7XX-33
(Ceramic Windowed
Devices)
RC VDD: 3.0V to 5.5V
IDD †: 6 mA max.
VDD: 4.5V to 5.5V
IDD †: 6 mA max.
VDD: 4.5V to 5.5V
IDD †: 6 mA max.
VDD: 4.5V to 5.5V
IDD †: 6 mA max.
IPD †: 5 µA max. at 5.5V
Freq: 4 MHz max.
IPD †: 5 µA max. at 5.5V
Freq: 4 MHz max.
IPD †: 5 µA max. at 5.5V
Freq: 4 MHz max.
IPD †: 5 µA max. at 5.5V
Freq: 4 MHz max.
XT VDD: 3.0V to 5.5V
IDD †: 12 mA max.
VDD: 4.5V to 5.5V
IDD †: 38 mA max.
IPD †: 5 µA max. at 5.5V
Freq: 16 MHz max.
VDD: 4.5V to 5.5V
IDD †: 50 mA max.
IPD †: 5 µA max. at 5.5V
Freq: 33 MHz max.
VDD: 4.5V to 5.5V
IDD †: 50 mA max.
IPD †: 5 µA max. at 5.5V
Freq: 33 MHz max.
IPD †: 5 µA max. at 5.5V
Freq: 8 MHz max.
EC VDD: 3.0V to 5.5V
IDD †: 12 mA max.
VDD: 4.5V to 5.5V
IDD †: 38 mA max.
IPD †: 5 µA max. at 5.5V
Freq: 16 MHz max.
VDD: 4.5V to 5.5V
IDD †: 50 mA max.
IPD †: 5 µA max. at 5.5V
Freq: 33 MHz max.
VDD: 4.5V to 5.5V
IDD †: 50 mA max.
IPD †: 5 µA max. at 5.5V
Freq: 33 MHz max.
IPD †: 5 µA max. at 5.5V
Freq: 8 MHz max.
LF VDD: 3.0V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 3.0V to 5.5V
IDD †: 115 µA max. at 32 kHz IDD †: 85 µA typ. at 32 kHz
IDD †: 85 µA typ. at 32 kHz
IPD †: < 1 µA typ. at 5.5V
Freq: 2 MHz max.
IDD †: 115 µA max. at 32 kHz
IPD †: 5 µA max. at 5.5V
Freq: 2 MHz max.
IPD †: 5 µA max. at 5.5V
IPD †: < 1 µA typ. at 5.5V
Freq: 2 MHz max.
Freq: 2 MHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
†
The WDT, BOR,and A/D circuitry are disabled.
DS30289A-page 236
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
20.1
DC CHARACTERISTICS
PIC17C7XX-16 (Commercial, Industrial)
PIC17C7XX-33 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
DC CHARACTERISTICS
Param.
-40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
Unit
No.
Sym
Characteristic
Supply Voltage
Min
Typ†
Max
s
Conditions
VDD
4.5
–
5.5
5.5
V
PIC17C7XX - 33,
PIC17C7XX - 16
PIC17C7XX - 16
D001
VBOR *
1.5 *
–
–
–
V
V
V
(BOR enabled)(Note 5)
VDR
RAM Data Retention
Voltage (Note 1)
–
–
Device in SLEEP mode
D002
D003
VPOR
VDD start voltage to
ensure internal
VSS
See section on Power-on
Reset for details
Power-on Reset signal
SVDD
VBOR
VPORTP
IDD
VDD rise rate to ensure
proper operation
0.085 *
3.65
–
–
–
–
4.35
–
V/ms See section on Power-on
Reset for details
D004
D005
D006
Brown-out Reset
voltage trip point
V
Power-on Reset trip
point
2.2
V
VDD = VPORTP
Supply Current
(Note 2)
–
–
–
–
–
TBD
TBD
TBD
TBD
TBD
6 *
12
24 *
38 *
50
mA
mA
mA
mA
mA
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
FOSC = 16 MHz
FOSC = 25 MHz
FOSC = 33 MHz
D010
D011
D012
D013
D015
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be con-
sidered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as:
VDD /(2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
5: This is the voltage where the device enters the Brown-Out-Reset. When BOR is enabled, the device (-16)
will operate correctly to this trip point.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 237
PIC17C7XX
Standard Operating Conditions (unless otherwise stated)
Operating temperature
DC CHARACTERISTICS
-40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
Param.
Unit
No.
Sym
IPD
Characteristic
Min
Typ†
Max
s
Conditions
Power-down Current
(Note 3)
–
< 1
20
µA
VDD = 5.5V, WDT disabled
D021
Module Differential
Current
∆IBOR
BOR circuitry
–
150
300
µA
VDD = 4.5V, BODEN
enabled
D023
∆IWDT
∆IAD
Watchdog Timer
A/D converter
–
–
10
1
35
–
µA
µA
VDD = 5.5V
D024
D026
VDD = 5.5V, A/D not con-
verting
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be con-
sidered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as:
VDD /(2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
5: This is the voltage where the device enters the Brown-Out-Reset. When BOR is enabled, the device (-16)
will operate correctly to this trip point.
DS30289A-page 238
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
20.2
DC CHARACTERISTICS
PIC17LC7XX -08(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
DC CHARACTERISTICS
-40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
Param.
No.
Sym
VDD
Characteristic
Min
3.0
Typ†
Max
Units
Conditions
Supply Voltage
–
–
5.5
–
V
V
D001
D002
VDR
RAM Data Retention
Voltage (Note 1)
1.5 *
Device in SLEEP mode
VPOR
VDD start voltage to
ensure internal
Power-on Reset sig-
nal
–
VSS
–
V
See section on Power-on
Reset for details
D003
SVDD
VDD rise rate to
ensure proper
operation
0.010 *
–
–
V/ms
See section on Power-on
Reset for details
D004
VBOR
VPORTP
IDD
Brown-out Reset
voltage trip point
3.65
–
–
4.35
–
V
V
D005
D006
Power-on Reset trip
point
2.2
VDD = VPORTP
Supply Current
(Note 2)
–
–
–
3
6
85
6 *
12
150
mA
mA
µA
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
FOSC = 32 kHz,
D010
D011
D014
(EC osc configuration)
IPD
Power-down Current
(Note 3)
–
< 1
5
µA
VDD = 3.0V,
WDT disabled
D021
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD, MCLR = VDD;
WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes extended
microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
formula IR = VDD/2Rext (mA) with Rext in kOhm.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 239
PIC17C7XX
Standard Operating Conditions (unless otherwise stated)
Operating temperature
DC CHARACTERISTICS
-40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
Module Differential
Current
∆IBOR
BOR circuitry
–
150
300
µA
VDD = 4.5V, BODEN
enabled
D023
∆IWDT
∆IAD
Watchdog Timer
A/D converter
–
–
10
1
35
–
µA
µA
VDD = 5.5V
D024
D026
VDD = 5.5V, A/D not con-
verting
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD, MCLR = VDD;
WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes extended
microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30289A-page 240
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
20.3
DC CHARACTERISTICS
PIC17C7XX-16 (Commercial, Industrial)
PIC17C7XX-33( Commercial, Industrial)
PIC17LC7XX-08 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Param.
Operating voltage VDD range as described in Section 20.1
No.
Sym
Characteristic
Input Low Voltage
I/O ports
with TTL buffer (Note 6)
Min
Typ†
Max Units
Conditions
VIL
VSS
VSS
–
–
0.8
0.2VDD
V
V
4.5V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 4.5V
D030
D031
with Schmitt Trigger buffer
RA2, RA3
2
VSS
VSS
–
–
0.3VDD
0.2VDD
V
V
I C compliant
All others
D032
D033
MCLR, OSC1 (in EC and RC
mode)
OSC1 (in XT, and LF mode)
VSS
–
0.2VDD
V
Note1
–
0.5VDD
–
V
Input High Voltage
I/O ports
VIH
with TTL buffer (Note 6)
2.0
1 + 0.2VDD
–
–
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 4.5V
D040
D041
with Schmitt Trigger buffer
RA2, RA3
2
0.7VDD
0.8VDD
–
–
VDD
VDD
V
V
I C compliant
All others
D042
D043
D050
MCLR
OSC1 (XT, and LF mode)
0.8VDD
–
–
VDD
–
V
V
Note1
0.5VDD
VHYS Hysteresis of
Schmitt Trigger inputs
These parameters are characterized but not tested.
0.15VDD *
–
–
V
*
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated.These parameters are for design guidance only and
are not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17C7XX Programming
Specifications (Literature number DS TBD).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 241
PIC17C7XX
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in Section 20.1
Param.
No.
Sym
Characteristic
Input Leakage Current
(Notes 2, 3)
Min
Typ†
Max Units
Conditions
IIL
I/O ports (except RA2, RA3)
–
–
±1
µA Vss ≤ VPIN ≤ VDD,
I/O Pin (in digital mode) at
hi-impedance PORTB
weak pull-ups disabled
D060
D061
D062
D063
D063B
D064
MCLR, TEST
RA2, RA3
–
–
±2
±2
µA VPIN = Vss or VPIN = VDD
µA Vss ≤ VRA2, VRA3 ≤ 12V
OSC1 (EC, RC modes)
OSC1 (XT, LF modes)
–
–
–
–
±1
µA Vss ≤ VPIN ≤ VDD
µA RF ≥ 1 MΩ
VPIN
MCLR, TEST
–
–
25
µA VMCLR = VPP = 12V
(when not programming)
D070 IPURB PORTB weak pull-up current
60
200
400
µA VPIN = VSS, RBPU = 0
4.5V ≤ VDD ≤ 5.5V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated.These parameters are for design guidance only and
are not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17C7XX Programming
Specifications (Literature number DS TBD).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
DS30289A-page 242
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Param.
Operating voltage VDD range as described in Section 20.1
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Output Low Voltage
VOL
I/O ports
IOL = VDD/1.250 mA
4.5V ≤ VDD ≤ 5.5V
VDD = 3.0V
IOL = 6 mA, VDD = 4.5V
Note 6
IOL = 60.0 mA, VDD = 5.5V
IOL = 60.0 mA, VDD = 2.5V
IOL = 60.0 mA, VDD = 4.5V
IOL = 1 mA, VDD = 4.5V
IOL = VDD/5 mA
D080
–
–
–
–
–
–
0.1VDD
0.1VDD *
0.4
V
V
V
with TTL buffer
RA2 and RA3
D081
D082
–
–
–
–
–
–
–
–
–
–
3.0
0.4
0.6
0.4
0.1VDD *
V
V
V
V
V
OSC2/CLKOUT
(RC and EC osc modes)
D083
D084
(PIC17LC7XX only)
Output High Voltage (Note 3)
VOH
I/O ports (except RA2 and RA3)
IOH = -VDD/2.5 mA
4.5V ≤ VDD ≤ 5.5V
VDD = 3.0V
IOH = -6.0 mA, VDD = 4.5V
Note 6
D090
D091
0.9VDD
0.9VDD *
2.4
–
–
–
–
–
–
V
V
V
with TTL buffer
OSC2/CLKOUT
(RC and EC osc modes)
2.4
0.9VDD *
–
–
–
–
V
V
IOH = -5 mA, VDD = 4.5V
IOH = -VDD/5 mA
D093
D094
(PIC17LC7XX only)
RA2 and RA3 pins only
pulled-up to externally
applied voltage
VOD
Open Drain High Voltage
–
–
8.5
V
D150
Capacitive Loading Specs on
Output Pins
Cosc2 OSC2/CLKOUT pin
–
–
25 ‡
pF In EC or RC osc modes
when OSC2 pin is output-
ting CLKOUT. External
clock is used to drive
OSC1.
D100
CIO
All I/O pins and OSC2
(in RC mode)
System Interface Bus
(PORTC, PORTD and PORTE)
–
–
–
–
50 ‡
50 ‡
pF
D101
D102
CAD
pF In Microprocessor or
Extended Microcontroller
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated.These parameters are for design guidance only and
are not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17C7XX Programming
Specifications (Literature number DS TBD).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 243
PIC17C7XX
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +40˚C
Operating voltage VDD range as described in Section 20.1
DC CHARACTERISTICS
Param.
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Internal Program Memory
Programming Specs (Note 4)
D110
D111
VPP
Voltage on MCLR/VPP pin
12.75
4.75
–
5.0
13.25
5.25
V
V
Note 5
VDDP Supply voltage during
programming
D112
D113
IPP
IDDP
Current into MCLR/VPP pin
Supply current during
programming
–
–
25 ‡
–
50 ‡
30 ‡
mA
mA
D114
TPROG Programming pulse width
100
–
1000
ms Terminated via inter-
nal/external interrupt or a
reset
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
Note 1: When using the Table Write for internal programming, the device temperature must be less than 40˚C.
Note 2: For In-Circuit Serial Programming (ICSP ), refer to the device programming specification.
DS30289A-page 244
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
20.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
3. TCC:ST
4. Ts
(I C specifications only)
2
2. TppS
(I C specifications only)
T
F
Frequency
T
Time
Lowercase symbols (pp) and their meanings:
pp
ad
Address/Data
ALE
ost
pwrt
rb
Oscillator Start-Up Timer
Power-Up Timer
PORTB
al
cc
ck
dt
Capture1 and Capture2
CLKOUT or clock
Data in
rd
RD
rw
RD or WR
in
INT pin
t0
T0CKI
io
I/O port
t123
wdt
wr
TCLK12 and TCLK3
Watchdog Timer
WR
mc
oe
os
MCLR
OE
OSC1
Uppercase symbols and their meanings:
S
D
E
F
H
I
Driven
L
Low
Edge
P
R
V
Z
Period
Rise
Fall
High
Valid
Invalid (Hi-impedance)
Hi-impedance
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 245
PIC17C7XX
FIGURE 20-1: PARAMETER MEASUREMENT INFORMATION
All timings are measure between high and low measurement points as indicated in the figures below.
INPUT LEVEL CONDITIONS
PORTC, D, E, F, G, H and J pins
VIH = 2.4V
VIL = 0.4V
Data in valid
All other input pins
Data in invalid
VIH = 0.9VDD
VIL = 0.1VDD
Data in valid
Data in invalid
OUTPUT LEVEL CONDITIONS
0.25V
0.25V
VOH = 0.7VDD
VDD/2
VOL = 0.3VDD
0.25V
0.25V
Data out valid
Data out invalid
Output
driven
Output
hi-impedance
0.9 VDD
Fall Time
0.1 VDD
Rise Time
LOAD CONDITIONS
Load Condition 1
Pin
CL
VSS
50 pF ≤ CL
DS30289A-page 246
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
20.5
Timing Diagrams and Specifications
FIGURE 20-2: EXTERNAL CLOCK TIMING
Q4
Q3
3
Q4
3
Q1
Q1
Q2
OSC1
1
4
4
2
OSC2 †
† In EC and RC modes only.
TABLE 20-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
DC
DC
DC
—
—
—
8
16
33
MHz EC osc mode - 08 devices (8 MHz devices)
Fosc External CLKIN Fre-
MHz
MHz
- 16 devices (16 MHz devices)
- 33 devices (33 MHz devices)
quency
(Note 1)
Oscillator Frequency
(Note 1)
DC
2
2
2
DC
—
—
—
—
—
4
8
16
33
2
MHz RC osc mode
MHz XT osc mode - 08 devices (8 MHz devices)
MHz
MHz
- 16 devices (16 MHz devices)
- 33 devices (33 MHz devices)
MHz LF osc mode
Tosc External CLKIN Period
125
62.5
30.3
—
—
—
—
—
—
ns
ns
ns
EC osc mode - 08 devices (8 MHz devices)
- 16 devices (16 MHz devices)
1
(Note 1)
- 33 devices (33 MHz devices)
Oscillator Period
(Note 1)
250
125
62.5
30.3
500
—
—
—
—
—
—
ns
ns
ns
ns
ns
RC osc mode
1,000
1,000
1,000
—
XT osc mode - 08 devices (8 MHz devices)
- 16 devices (16 MHz devices)
- 33 devices (33 MHz devices)
LF osc mode
TCY
Instruction Cycle Time
(Note 1)
121.2 4/Fosc
DC
ns
ns
ns
2
3
TosL, Clock in (OSC1)
TosH high or low time
10 ‡
—
—
—
—
EC oscillator
EC oscillator
TosR, Clock in (OSC1)
TosF rise or fall time
5 ‡
4
†
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 247
PIC17C7XX
FIGURE 20-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
OSC2 †
13
12
18
16
14
19
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
† In EC and RC modes only.
TABLE 20-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
Typ
No.
Sym
Characteristic
Min
†
Max
Units Conditions
TosL2ckL OSC1↓ to CLKOUT↓
TosL2ckH OSC1↓ to CLKOUT↑
—
—
15 ‡
15 ‡
30 ‡
30 ‡
ns
ns
Note 1
Note 1
10
11
12
13
14
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
—
—
5 ‡
5 ‡
—
15 ‡
15 ‡
ns
ns
ns
Note 1
Note 1
Note 1
TckH2ioV CLKOUT ↑ to Port out valid
TioV2ckH Port in valid before CLKOUT↑
0.5TCY + 20
‡
0.25TCY + 25 ‡
—
—
—
—
—
—
ns
ns
ns
ns
Note 1
Note 1
15
16
17
18
TckH2ioI
TosL2ioV
TosL2ioI
Port in hold after CLKOUT↑
0 ‡
—
OSC1↓ (Q1 cycle) to Port out valid
100 ‡
—
OSC1↓ (Q2 cycle) to Port input
invalid
0 ‡
(I/O in hold time)
TioV2osL Port input valid to OSC1↓
30 ‡
—
—
ns
19
(I/O in setup time)
TioR
Port output rise time
Port output fall time
INT pin high or low time
—
—
10 ‡
10 ‡
—
35 ‡
35 ‡
—
ns
ns
ns
ns
20
21
22
23
TioF
TinHL
TrbHL
25 *
25 *
RB7:RB0 change INT high or low
time
—
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Measurements are taken in EC Mode where CLKOUT output is 4 x TOSC.
DS30289A-page 248
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET TIMING
VDD
MCLR
30
Internal
POR / BOR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
35
Address /
Data
TABLE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
30
31
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
VDD = 5V
TmcL
TWDT
MCLR Pulse Width (low)
100 *
5 *
—
—
ns
Watchdog Timer Time-out Period
(Postscale = 1)
12
25 *
ms
VDD = 5V
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period
Power-up Timer Period
—
1024TOSC§
—
200 *
—
ms
ms
ns
TOSC = OSC1 period
VDD = 5V
32
33
34
35
40 *
96
—
MCLR to I/O hi-impedance
100 ‡
Depends on pin load
PIC17C7XX
TmcL2adI MCLR to System
Interface bus
—
—
—
—
100 *
120 *
ns
ns
PIC17LC7XX
(AD15:AD0>) invalid
TBOR
Brown-out Reset Pulse Width (low)
100 *
—
—
ns
3.9V ≤ VDD ≤ 4.2V
36
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25∞C unless otherwise stated. These parameters are for design guidance only and are
not tested.
‡
§
These parameters are for design guidance only and are not tested, nor characterized.
This specification ensured by design.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 249
PIC17C7XX
FIGURE 20-5: TIMER0 EXTERNAL CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 20-5: TIMER0 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
Tt0H T0CKI High Pulse Width No Prescaler
0.5TCY + 20 §
—
—
ns
40
With Prescaler
Tt0L T0CKI Low Pulse Width No Prescaler
With Prescaler
10*
0.5TCY + 20 §
10*
—
—
—
—
—
—
—
—
ns
ns
ns
41
42
Tt0P T0CKI Period
Greater of:
20 ns or TCY + 40 §
N
ns N = prescale value
(1, 2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 20-6: TIMER1,TIMER2, AND TIMER3 EXTERNAL CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 20-6: TIMER1,TIMER2, AND TIMER3 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Typ
†
Sym
Characteristic
Min
Max
Units Conditions
Tt123H TCLK12 and TCLK3 high time
Tt123L TCLK12 and TCLK3 low time
0.5TCY + 20 §
0.5TCY + 20 §
—
—
—
—
ns
ns
45
46
47
Tt123P TCLK12 and TCLK3 input period
TCY + 40 §
N
—
—
ns N = prescale value
(1, 2, 4, 8)
TckE2tmrI Delay from selected External Clock Edge to
Timer increment
2TOSC §
—
6Tosc §
—
48
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25∞C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
DS30289A-page 250
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-7: CAPTURE TIMINGS
CAP pin
(Capture Mode)
50
51
52
TABLE 20-7: CAPTURE REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
TccL Capture pin input low time
10 *
10 *
—
—
—
—
ns
ns
50
51
52
TccH
TccP
Capture pin input high time
Capture pin input period
2TCY §
N
—
—
ns N = prescale value (4
or 16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25∞C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 20-8: PWM TIMINGS
PWM pin
(PWM Mode)
53
54
TABLE 20-8: PWM REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
TccR PWM pin output rise time
TccF PWM pin output fall time
—
—
10 * 35 *
10 * 35 *
ns
ns
53
54
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25∞C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 251
PIC17C7XX
FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
BIT6 - - - - - -1
MSb
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Refer to Figure 20-1 for load conditions.
TABLE 20-9: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY *
—
—
ns
70
TscH
SCK input high time
(slave mode)
Continuous 1.25TCY + 30 *
—
—
—
—
—
—
—
—
—
—
ns
71
71A
72
Single Byte
40
ns Note 1
TscL
SCK input low time
(slave mode)
Continuous 1.25TCY + 30 *
ns
Single Byte
40
ns Note 1
ns
72A
73
TdiV2scH, Setup time of SDI data input to SCK
TdiV2scL
100 *
edge
TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 *
edge of Byte2
—
—
—
—
ns Note 1
ns
73A
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100 *
TdoR
TdoF
TscR
TscF
SDO data output rise time
—
—
—
—
—
10 25 *
10 25 *
10 25 *
10 25 *
ns
ns
ns
ns
ns
75
76
78
79
80
SDO data output fall time
SCK output rise time (master mode)
SCK output fall time (master mode)
TscH2doV, SDO data output valid after SCK edge
TscL2doV
—
50 *
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30289A-page 252
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-10: SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Refer to Figure 20-1 for load conditions.
TABLE 20-10: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
TscH
SCK input high time
(slave mode)
Continuous 1.25TCY + 30 *
—
—
—
—
—
—
ns
71
Single Byte
40
ns Note 1
ns
71A
72
TscL
SCK input low time
(slave mode)
Continuous 1.25 TCY + 30
*
Single Byte
40
—
—
—
—
ns Note 1
ns
72A
73
TdiV2scH, Setup time of SDI data input to SCK
100 *
TdiV2scL
TB2B
edge
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 *
edge of Byte2
—
—
—
—
ns Note 1
ns
73A
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100 *
TdoR
TdoF
TscR
TscF
SDO data output rise time
—
—
—
—
—
10 25 *
10 25 *
10 25 *
10 25 *
ns
ns
ns
ns
ns
75
76
78
79
80
SDO data output fall time
SCK output rise time (master mode)
SCK output fall time (master mode)
TscH2doV, SDO data output valid after SCK edge
TscL2doV
—
50 *
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY *
—
—
ns
81
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 253
PIC17C7XX
FIGURE 20-11: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Refer to Figure 20-1 for load conditions.
TABLE 20-11: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY *
—
—
ns
70
TscH
SCK input high time
(slave mode)
Continuous 1.25TCY + 30 *
—
—
—
—
—
—
—
—
—
—
ns
71
71A
72
Single Byte
40
ns Note 1
TscL
SCK input low time
(slave mode)
Continuous 1.25TCY + 30 *
ns
Single Byte
40
ns Note 1
ns
72A
73
TdiV2scH, Setup time of SDI data input to SCK
TdiV2scL
100 *
edge
TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 *
edge of Byte2
—
—
—
—
ns Note 1
ns
73A
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100 *
TdoR
TdoF
SDO data output rise time
SDO data output fall time
—
—
10 25 *
10 25 *
ns
ns
ns
ns
ns
ns
75
76
77
78
79
80
TssH2doZ SS↑ to SDO output hi-impedance
10 *
—
—
50 *
TscR
TscF
SCK output rise time (master mode)
SCK output fall time (master mode)
10 25 *
10 25 *
—
TscH2doV, SDO data output valid after SCK edge
TscL2doV
—
—
50 *
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40 *
—
—
ns
83
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30289A-page 254
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-12: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Refer to Figure 20-1 for load conditions.
TABLE 20-12: SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 1)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY *
—
—
ns
70
TscH
TscL
TB2B
SCK input high time
(slave mode)
Continuous 1.25TCY + 30 *
—
—
—
—
—
—
—
—
—
—
ns
71
71A
72
Single Byte
Continuous 1.25TCY + 30 *
Single Byte 40
40
ns Note 1
ns
SCK input low time
(slave mode)
ns Note 1
ns Note 1
72A
73A
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 *
edge of Byte2
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100 *
—
—
ns
74
TdoR
TdoF
SDO data output rise time
SDO data output fall time
—
—
10 25 *
10 25 *
ns
ns
ns
ns
75
76
77
80
TssH2doZ SS↑ to SDO output hi-impedance
10 *
—
—
—
50 *
50 *
TscH2doV, SDO data output valid after SCK edge
TscL2doV
TssL2doV SDO data output valid after SS↓ edge
—
—
—
50 *
—
ns
ns
82
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40 *
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 255
PIC17C7XX
2
FIGURE 20-13: I C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 20-1 for load conditions.
2
TABLE 20-13: I C BUS START/STOP BITS REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ Max Units
Conditions
TSU:STA START condition 100 kHz mode
Setup time 400 kHz mode
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated
START condition
90
ns
ns
ns
ns
(1)
1 MHz mode
THD:STA START condition 100 kHz mode
After this period the first
clock pulse is generated
91
92
Hold time
400 kHz mode
(1)
1 MHz mode
100 kHz mode
400 kHz mode
TSU:STO STOP condition
Setup time
(1)
1 MHz mode
100 kHz mode
400 kHz mode
THD:STO STOP condition
Hold time
93
(1)
1 MHz mode
This specification ensured by design.
Note 1: Maximum pin capacitance = 10 pF for all I C pins.
§
2
DS30289A-page 256
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
2
FIGURE 20-14: I C BUS DATA TIMING
103
102
100
101
109
SCL
90
106
91
92
107
SDA
In
110
109
SDA
Out
Note: Refer to Figure 20-1 for load conditions.
2
TABLE 20-14: I C BUS DATA REQUIREMENTS
Param No.
Sym
Characteristic
Min
Max
Units
Conditions
THIGH
Clock high time
100 kHz mode 2(TOSC)(BRG + 1) §
—
—
—
—
—
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
ns
100
400 kHz mode 2(TOSC)(BRG + 1) §
(1)
1 MHz mode
2(TOSC)(BRG + 1) §
TLOW
TR
Clock low time
100 kHz mode 2(TOSC)(BRG + 1) §
101
102
103
90
400 kHz mode 2(TOSC)(BRG + 1) §
(1)
1 MHz mode
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1) §
—
SDA and SCL
rise time
—
1000 *
300 *
300 *
300 *
300 *
100 *
—
—
—
—
—
—
—
0.9 *
—
—
—
—
—
—
Cb is specified to be from
10 to 400 pF
20 + 0.1Cb *
(1)
1 MHz mode
100 kHz mode
400 kHz mode
—
TF
SDA and SCL
fall time
—
20 + 0.1Cb *
—
Cb is specified to be from
10 to 400 pF
(1)
1 MHz mode
ns
TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) §
setup time 400 kHz mode 2(TOSC)(BRG + 1) §
ms
ms
ms
ms
ms
ms
ns
ms
ns
ns
ns
ns
ms
ms
ms
ns
Only relevant for repeated
START condition
(1)
1 MHz mode
2(TOSC)(BRG + 1) §
THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) §
After this period the first
clock pulse is generated
91
hold time
400 kHz mode 2(TOSC)(BRG + 1) §
(1)
1 MHz mode
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1) §
THD:DAT Data input
hold time
0
0
106
107
92
(1)
1 MHz mode
100 kHz mode
400 kHz mode
TBD *
250 *
100 *
TBD *
TSU:DAT Data input
setup time
Note 2
(1)
1 MHz mode
TSU:STO STOP condition
setup time
100 kHz mode 2(TOSC)(BRG + 1) §
400 kHz mode 2(TOSC)(BRG + 1) §
(1)
1 MHz mode
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1) §
—
TAA
TBUF
Cb
Output valid
from clock
—
—
—
4.7 ‡
1.3 ‡
TBD *
—
3500 *
1000 *
—
—
—
109
ns
ns
ms
ms
ms
pF
(1)
1 MHz mode
100 kHz mode
400 kHz mode
Bus free time
Time the bus must be free
before a new transmission
can start
110
(1)
1 MHz mode
Bus capacitive loading
—
400 *
D102 ‡
*
Characterized but not tested.
§
‡
This specification ensured by design.
These parameters are for design guidance only and are not tested, nor characterized.
2
Note 1: Maximum pin capacitance = 10 pF for all I C pins.
2
2
2: A fast-mode (400 KHz) I C-bus device can be used in a standard-mode I C-bus system, but the parameter # 107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter # 102 + # 107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released.
3:
C is specified to be from 10-400pF. The minimum specifications are characterized with C =10pF. The rise time spec (t )
b
b
r
is characterized with R =R min. The minimum fall time specification (t ) is characterized with C =10pF, and R =R max.
p
p
f
b
p
p
These are only valid for fast mode operation (VDD=4.5-5.5V) and where the SPM bit (SSPSTAT<7>)=1.)
4: Max specifications for these parameters are valid for falling edge only. Specs are characterized with R =R min and
p
p
C =400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.
b
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 257
PIC17C7XX
FIGURE 20-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TX/CK
pin
121
121
RX/DT
pin
122
120
TABLE 20-15: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Typ
†
Sym
Characteristic
Min
Max Units
Conditions
TckH2dtV SYNC XMIT (MASTER &
SLAVE)
120
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
—
—
—
—
—
—
—
—
—
—
—
—
50
75 *
25
ns
ns
ns
ns
ns
ns
Clock high to data out valid
TckRF
TdtRF
Clock out rise time and fall
time (Master Mode)
121
122
40 *
25
Data out rise time and fall time PIC17CXXX
PIC17LCXXX
40 *
*
Characterized but not tested.
†
Data in “Typ” column is at 5V, 25∞C unless otherwise stated.These parameters are for design guidance only and are
not tested.
FIGURE 20-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TX/CK
125
pin
RX/DT
pin
126
TABLE 20-16: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Typ
†
Sym
Characteristic
Min
Max
Units
Conditions
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data setup before CK↓ (DT setup time)
125
126
15
15
—
—
—
—
ns
ns
TckL2dtl
Data hold after CK↓ (DT hold time)
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated.These parameters are for design guidance only and are not
tested.
DS30289A-page 258
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-17: USART ASYNCHRONOUS MODE START BIT DETECT
Start bit
RX
(RX/DT pin)
121A
x16 CLK
Q2, Q4 CLK
120A
123A
TABLE 20-17: USART ASYNCHRONOUS MODE START BIT DETECT REQUIREMENTS
Param
No.
Sym
Characteristic
Min
—
Typ†
—
Max
TCY §
Note 1
Units
ns
Conditions
TdtL2ckH
TdtRF
Time to ensure that the RX pin is sampled low
120A
121A
Data rise time and fall time
Receive
Transmit
—
—
ns
—
—
—
—
40 †
ns
ns
TckH2bckL Time from RX pin sampled low to first rising edge
of x16 clock
TCY §
123A
†
§
These parameters are for design guidance only and are not tested.
This specification ensured by design.
Note 1: Schmitt trigger will determine logic level.
FIGURE 20-18: USART ASYNCHRONOUS RECEIVE SAMPLING WAVEFORM
Start bit
Bit0
RX
(RX/DT pin)
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
126A
1
2
3
125A
Samples
TABLE 20-18: USART ASYNCHRONOUS RECEIVE SAMPLING REQUIREMENTS
Param
No.
Typ
†
Sym
Characteristic
Min
Max
Units
Conditions
TdtL2ckH
Setup time of RX pin to first data sam-
pled
TCY §
—
—
—
ns
125A
126A
TdtL2ckH
Hold time of RX pin from last data sam-
pled
TCY §
—
ns
§
This specification ensured by design.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 259
PIC17C7XX
TABLE 20-19: A/D CONVERTER CHARACTERISTICS
Param.
No.
Sym Characteristic
NR Resolution
Min
Typ†
Max
Units
Conditions
VREF+ = VDD = 5.12V,
A01
—
—
10
bit
VSS ≤ VAIN ≤ VREF+
—
—
—
—
10*
bit
(VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
EABS Absolute error
< ±1
LSb VREF+ = VDD = 5.12V,
A02
A03
A04
A05
A06
VSS ≤ VAIN ≤ VREF+
—
—
—
—
< ±1*
< ±1
LSb (VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
EIL
EDL
EFS
Integral linearity error
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
—
—
—
—
< ±1*
< ±1
LSb (VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
Differential linearity error
Full scale error
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
—
—
—
—
< ±1*
< ±1
LSb (VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
—
—
—
—
< ±1*
< ±1
LSb (VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
EOFF Offset error
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
LSb
—
—
—
< ±1*
—
(VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
—
Monotonicity
guaran-
teed
—
V
VSS ≤ VAIN ≤ VREF
A10
A20
A20A
A21
A22
A25
A30
A40
VREF Reference voltage
(VREF+ — VREF-)
0V
—
—
—
—
—
—
—
VREF delta when changing voltage lev-
els on VREF inputs.
3V *
—
V
Absolute minimum electrical spec.
To ensure 10-bit accuracy
VREF+ Reference voltage High
VREF- Reference voltage Low
AVSS
+ 3.0V
AVDD +
0.3V
V
AVSS
- 0.3V
AVDD -
3.0V
V
VAIN
ZAIN
IAD
Analog input voltage
AVSS
- 0.3V
VREF +
0.3V
V
Recommended impedance of
analog voltage source
—
10.0
kΩ
A/D conversion
current (VDD)
PIC17CXXX
—
—
10
180
90
—
—
µA
µA
µA
Average current consumption when
A/D is on. (Note 1)
PIC17LCXXX
IREF
VREF input current (Note 2)
—
1000
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
A50
—
—
10
µA
During A/D conversion cycle
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RG0 and RG1 pins or AVDD and AVSS pins, whichever is selected as reference input.
DS30289A-page 260
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-19: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 TCY
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 20-20: A/D CONVERSION REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
TOSC based, VREF ≥ 3.0V
TOSC based, VREF full range
A/D RC Mode
TAD
A/D clock period
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
1.6
3.0
—
—
—
µs
µs
130
—
2.0 *
3.0 *
11 §
4.0
6.0
—
6.0 *
9.0 *
12 §
µs
µs
A/D RC Mode
TCNV
TACQ
Conversion time
(not including acquisition time) (Note 1)
TAD
131
132
Acquisition time
(Note 2)
10 *
20
—
—
—
µs
µs
The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e. 5 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
TGO
Q4 to ADCLK start
—
Tosc/2 §
—
—
If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
SLEEPinstruction to be exe-
cuted.
134
*
These parameters are characterized but not tested.
†
§
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 261
PIC17C7XX
FIGURE 20-20: MEMORY INTERFACE WRITE TIMING
Q1
Q2
Q3
Q4
Q2
Q1
OSC1
ALE
OE
151
WR
150
addr out
154
data out
AD<15:0>
addr out
152
153
TABLE 20-21: MEMORY INTERFACE WRITE REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ†
Max Units Conditions
TadV2alL AD<15:0> (address) valid to
PIC17CXXX
0.25TCY - 10
—
—
ns
—
150
ALE↓ (address setup time) PIC17LCXXX 0.25TCY - 10*
—
—
—
TalL2adI
ALE↓ to address out invalid
PIC17CXXX
0
—
ns
—
151
152
(address hold time)
PIC17LCXXX
0*
TadV2wrL Data out valid to WR↓
(data setup time)
PIC17CXXX
0.25TCY - 40
—
—
—
ns
—
PIC17LCXXX 0.25TCY - 40*
TwrH2adI WR↑ to data out invalid
(data hold time)
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
—
—
—
—
0.25TCY§
0.25TCY§
0.25TCY§
0.25TCY§
—
ns
—
153
154
TwrL
WR pulse width
—
ns
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
DS30289A-page 262
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-21: MEMORY INTERFACE READ TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
OE
164
168
160
165
161
Data in
162
AD<15:0>
WR
Addr out
150
Addr out
151
163
167
'1'
'1'
TABLE 20-22: MEMORY INTERFACE READ REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
TadV2alL AD15:AD0 (address) valid to
PIC17CXXX 0.25TCY - 10
—
—
150
ns
ALE↓ (address setup time) PIC17LCXXX 0.25TCY - 10*
—
—
—
—
—
—
TalL2adI
ALE↓ to address out invalid
PIC17CXXX
5*
5*
151
160
ns
ns
ns
ns
(address hold time)
PIC17LCXXX
TadZ2oeL AD15:AD0 hi-impedance to
OE↓
PIC17CXXX
0*
0*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIC17LCXXX
ToeH2adD OE↑ to AD15:AD0 driven
PIC17CXXX 0.25TCY - 15
PIC17LCXXX 0.25TCY - 15*
161
162
163
TadV2oeH Data in valid before OE↑
(data setup time)
PIC17CXXX
PIC17LCXXX
PIC17CXXX
35
45*
0
ToeH2adI OE↑to data in invalid
(data hold time)
ns
ns
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
0*
—
—
—
—
—
TalH
ALE pulse width
0.25TCY §
0.25TCY §
164
165
ToeL
OE pulse width
PIC17CXXX 0.5TCY - 35 §
PIC17LCXXX 0.5TCY - 35 §
—
—
ns
ns
—
TCY §
TCY §
—
—
TalH2alH ALE↑ to ALE↑(cycle time)
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
—
—
—
—
—
—
166
167
Tacc
Toe
Address access time
0.75TCY - 30
ns
ns
—
0.75TCY -
45*
Output enable access time
(OE low to Data Valid)
PIC17CXXX
—
—
—
—
0.5TCY - 45
0.5TCY - 75*
168
PIC17LCXXX
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 263
PIC17C7XX
NOTES:
DS30289A-page 264
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
21.0 PIC17C7XX DC AND AC CHARACTERISTICS
The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some
graphs or tables the data presented is outside specified operating range (e.g. outside specified VDD range). This is for
information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3σ) and (mean - 3σ)
respectively where σ is standard deviation.
TABLE 21-1: PIN CAPACITANCE PER PACKAGE TYPE
Typical Capacitance (pF)
Pin Name
68-pin PLCC
64-pin TQFP
All pins, except MCLR, VDD, and VSS
MCLR pin
10
20
10
20
FIGURE 21-1: TYPICAL RC OSCILLATOR FREQUENCY vs.TEMPERATURE
FOSC
Frequency normalized to +25°C
FOSC (25°C)
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0
10
20
25
30
40
50
60
70
T(°C)
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 265
PIC17C7XX
FIGURE 21-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 10k
3.0
2.5
2.0
1.5
Cext = 22 pF, T = 25°C
1.0
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
FIGURE 21-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 3.3k
3.0
2.5
R = 5.1k
2.0
1.5
R = 10k
1.0
Cext = 100 pF, T = 25°C
0.5
0.0
R = 100k
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
DS30289A-page 266
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
R = 3.3k
R = 5.1k
R = 10k
0.4
0.2
Cext = 300 pF, T = 25°C
R = 160k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
TABLE 21-2: RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5V, 25°C
Cext
Rext
22 pF
10k
100k
3.3k
5.1k
10k
3.33 MHz
353 kHz
3.54 MHz
2.43 MHz
1.30 MHz
129 kHz
1.54 MHz
980 kHz
564 kHz
35 kHz
± 12%
± 13%
± 10%
± 14%
± 17%
± 10%
± 14%
± 12%
± 16%
± 18%
100 pF
300 pF
100k
3.3k
5.1k
10k
160k
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 267
PIC17C7XX
FIGURE 21-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD
500
450
400
350
Max @ -40°C
300
Typ @ 25°C
250
200
150
Min @ 85°C
100
50
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 21-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
20
18
Max @ -40°C
16
14
12
10
8
Typ @ 25°C
6
Min @ 85°C
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30289A-page 268
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-7: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C)
100000
10000
1000
7.0V
6.5V
6.0V
5.5V
5.0V
100
4.5V
4.0V
10
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
FIGURE 21-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125°C TO -40°C)
100000
10000
1000
100
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
4.0V
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 269
PIC17C7XX
FIGURE 21-9: TYPICAL IPD vs. VDD WATCHDOG DISABLED 25°C
12
10
8
6
4
2
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 21-10: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Temp. = 85°C
Temp. = 70°C
Temp. = 0°C
Temp. = -40°C
6.5 7.0
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30289A-page 270
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-11: TYPICAL IPD vs. VDD WATCHDOG ENABLED 25°C
30
25
20
15
10
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 21-12: MAXIMUM IPD vs. VDD WATCHDOG ENABLED
60
50
40
-40°C
0°C
70°C
85°C
30
20
10
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 271
PIC17C7XX
FIGURE 21-13: WDT TIMER TIME-OUT PERIOD vs. VDD
30
25
Max. 85°C
20
Max. 70°C
Min. 0°C
15
10
Typ. 25°C
Min. -40°C
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
FIGURE 21-14: IOH vs. VOH, VDD = 3V
0
-2
-4
-6
Min @ 85°C
-8
Typ @ 25°C
-10
-12
-14
Max @ -40°C
-16
-18
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOH (Volts)
DS30289A-page 272
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-15: IOH vs. VOH, VDD = 5V
0
-5
-10
-15
-20
Min @ 85°C
Max @ -40°C
-25
Typ @ 25°C
-30
-35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOH (Volts)
FIGURE 21-16: IOL vs. VOL, VDD = 3V
30
Max. -40°C
25
20
Typ. 25°C
15
10
Min. +85°C
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 273
PIC17C7XX
FIGURE 21-17: IOL vs. VOL, VDD = 5V
90
80
70
60
50
40
30
Max @ -40°C
Typ @ 25°C
Min @ +85°C
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
FIGURE 21-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD
2.0
1.8
Max (-40°C to +85°C)
1.6
Typ @ 25°C
1.4
1.2
1.0
Min (-40°C to +85°C)
0.8
0.6
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
5.5
6.0
DS30289A-page 274
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-19: VIH, VIL of I/O PINS (SCHMITT TRIGGER) VS. VDD
5.0
VIH, max (-40°C to +85°C)
4.5
VIH, typ (25°C)
4.0
VIH, min (-40°C to +85°C)
3.5
3.0
2.5
VIL, max (-40°C to +85°C)
VIL, typ (25°C)
VIL, min (-40°C to +85°C)
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 21-20: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT AND LF MODES) vs. VDD
3.4
3.2
Typ (25°C)
3.0
Max (-40°C to +85°C)
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
Min (-40°C to +85°C)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1998 Microchip Technology Inc.
Preliminary
DS30289A-page 275
PIC17C7XX
NOTES:
DS30289A-page 276
Preliminary
1998 Microchip Technology Inc.
PIC17C7XX
22.0 PACKAGING INFORMATION
Package Type: K04-085 64-Lead Plastic Thin Quad Flatpack (PT)
10x10x1 mm Body, 1.0/0.1 mm Lead Form
E1
E
# leads = n1
p
D
D1
2
1
B
n
X x 45°
α
L
A
R2
c
R1
φ
A1
A2
L1
β
Units
Dimension Limits
Pitch
INCHES
NOM
0.020
MILLIMETERS*
MIN
MAX
MIN
NOM
0.50
MAX
p
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
n
n1
A
A1
A2
R1
R2
L
64
16
64
16
0.039
0.015
0.002
0.003
0.003
0.005
0
0.043
0.025
0.004
0.003
0.006
0.012
3.5
0.047
1.00
1.10
0.64
0.10
0.08
0.14
0.30
3.5
1.20
0.035
0.006
0.010
0.008
0.015
7
0.38
0.05
0.08
0.08
0.13
0
0.89
0.15
0.25
0.20
0.38
7
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
0.003
0.004
0.007
0.463
0.463
0.390
0.390
0.025
5
0.008
0.006
0.009
0.472
0.472
0.394
0.394
0.035
10
0.013
0.008
0.011
0.482
0.482
0.398
0.398
0.045
15
0.08
0.09
0.17
11.75
11.75
9.90
9.90
0.64
5
0.20
0.15
0.22
12.00
12.00
10.00
10.00
0.89
10
0.33
0.20
0.27
12.25
12.25
10.10
10.10
1.14
15
†
D1
E1
‡
D
E
‡
X
α
β
5
12
15
5
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1998 Microchip Technology Inc.
DS30289A-page 277
PIC17C7XX
Package Type: K04-049 68-Lead Plastic Leaded Chip Carrier (L) – Square
E1
E
# leads = n1
D D1
n 12
α
CH1 x 45°
CH2 x 45°
A3
A1
R1
L
A
32°
c
R2
B1
B
A2
p
β
D2
E2
Units
INCHES*
NOM
68
MILLIMETERS
Dimension Limits
Number of Pins
Pitch
Overall Pack. Height
Shoulder Height
Standoff
MIN
MAX
MIN
NOM
68
MAX
n
e1
A
A1
A2
A3
CH1
CH2
E1
D1
E
D
E2
D2
n1
c
B1
B
0.050
0.175
0.103
0.025
0.026
0.045
0.005
0.990
0.990
0.954
0.954
0.920
0.920
17
0.010
0.029
0.018
0.058
0.005
0.025
5
1.27
0.165
0.185
4.19
2.41
0.43
0.53
0.89
0.00
25.02
25.02
24.13
24.13
23.11
23.11
4.45
2.60
0.62
0.66
1.14
0.13
25.15
25.15
24.23
24.23
23.37
23.37
17
4.70
2.79
0.81
0.79
1.40
0.095
0.017
0.021
0.035
0.000
0.985
0.985
0.950
0.950
0.910
0.910
0.110
0.032
0.031
0.055
0.010
0.995
0.995
0.958
0.958
0.930
0.930
Side 1 Chamfer Dim.
Corner Chamfer (1)
Corner Chamfer (other)
Overall Pack. Width
Overall Pack. Length
Molded Pack. Width
Molded Pack. Length
Footprint Width
Footprint Length
Pins along Width
Lead Thickness
Upper Lead Width
Lower Lead Width
Upper Lead Length
Shoulder Inside Radius
J-Bend Inside Radius
Mold Draft Angle Top
Mold Draft Angle Bottom
*
0.25
25.27
25.27
24.33
24.33
23.62
23.62
‡
‡
0.008
0.026
0.015
0.050
0.003
0.015
0
0.012
0.031
0.021
0.065
0.010
0.035
10
0.20
0.66
0.38
1.27
0.08
0.38
0
0.25
0.72
0.46
1.46
0.13
0.64
5
0.30
0.79
0.53
1.65
0.25
0.89
10
†
L
R1
R2
α
β
0
5
10
0
5
10
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”
DS30289A-page 278
1998 Microchip Technology Inc.
PIC17C7XX
Package Type: K04-093 84-Lead Plastic Leaded Chip Carrier (L) – Square
E1
E
# leads = n1
D1
D
α
n12
CH2 x 45°
CH1 x 45°
A3
R1
c
A
A1
45°
B1
B
L
R2
β
p
A2
D2
E2
Units
INCHES*
NOM
84
MILLIMETERS
Dimension Limits
Number of Pins
Pitch
Overall Pack. Height
Shoulder Height
Standoff
Side 1 Chamfer Dim.
Corner Chamfer (1)
Corner Chamfer(other)
Overall Pack. Width
Overall Pack. Length
Molded Pack. Width
Molded Pack. Length
Footprint Width
MIN
MAX
MIN
NOM
84
MAX
n
p
A
A1
A2
0.050
0.173
0.105
0.025
0.045
0.045
0.015
1.190
1.190
1.154
1.154
1.110
1.110
21
0.010
0.028
0.018
0.058
0.005
0.027
5
1.27
0.165
0.090
0.020
0.042
0.042
0.010
1.185
1.185
1.150
1.150
1.095
1.095
0.180
4.19
2.29
0.51
1.07
1.07
0.25
30.10
30.10
29.21
29.21
27.81
27.81
4.38
2.67
0.64
1.14
1.14
0.38
30.23
30.23
29.31
29.31
28.19
28.19
21
4.57
3.05
0.76
1.22
1.22
0.120
0.030
0.048
0.048
0.020
1.195
1.195
1.158
1.158
1.125
1.125
A3
CH1
CH2
E1
D1
E
0.51
30.35
30.35
29.41
29.41
28.58
28.58
‡
‡
D
E2
D2
n1
c
B1
B
Footprint Length
Pins along Width
Lead Thickness
0.008
0.023
0.013
0.050
0.003
0.022
0
0.012
0.033
0.023
0.065
0.010
0.032
10
0.20
0.58
0.33
1.27
0.08
0.56
0
0.25
0.71
0.46
1.46
0.13
0.69
5
0.30
0.84
0.58
1.65
0.25
0.81
10
†
Upper Lead Width
Lower Lead Width
Upper Lead Length
Shoulder Inside Radius
J-Bend Inside Radius
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L
R1
R2
α
β
0
5
10
10
0
5
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1998 Microchip Technology Inc.
DS30289A-page 279
PIC17C7XX
Package Type: K04-092 80-Lead Plastic Thin Quad Flatpack (PT)
12x12x1 mm Body, 1.0/0.1 mm Lead Form
E1
E
# lead s = n1
p
D
D1
2
1
B
n
X x 45°
L
α
A
R2
c
R1
φ
L1
A1
β
A2
Units
Dimension Limits
Pitch
INCHES
NOM
MILLIMETERS*
MIN
MAX
MIN
NOM
0.50
80
MAX
p
n
n1
A
A1
A2
R1
R2
L
0.020
80
20
0.043
0.025
0.004
0.003
0.006
0.012
3.5
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
20
0.039
0.047
1.00
0.38
1.10
0.64
0.10
0.08
0.14
0.30
3.5
1.20
0.015
0.002
0.003
0.003
0.005
0
0.035
0.006
0.010
0.008
0.015
7
0.89
0.15
0.25
0.20
0.38
7
0.05
0.08
0.08
0.13
0
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
0.003
0.004
0.007
0.542
0.542
0.462
0.462
0.025
5
0.008
0.006
0.009
0.551
0.551
0.472
0.472
0.035
10
0.013
0.008
0.011
0.561
0.561
0.482
0.482
0.045
15
0.08
0.09
0.17
13.77
13.77
11.73
11.73
0.64
5
0.20
0.15
0.22
14.00
14.00
12.00
12.00
0.89
10
0.33
0.20
0.27
14.25
14.25
12.24
12.24
1.14
15
†
D1
E1
‡
D
E
‡
X
α
β
5
12
15
5
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30289A-page 280
1998 Microchip Technology Inc.
PIC17C7XX
22.1
Package Marking Information
64-Lead TQFP
Example
MMMMMMMMMM
MMMMMMMMMM
MMMMMMMMMM
PIC17C752
-08I/PT
AABBCDE
9817CAE
68/84-Lead CERQUAD Windowed
Example
PIC17C756-04/CL
9850CAE
MMMMMMMMMMMMMMMMM
AABBCDE
68/84-Lead PLCC
Example
MMMMMMMMMMMMMMMMM
MMMMMMMMMMMMMMMMM
MMMMMMMMMMMMMMMMM
MMMMMMMMMMMMMMMMM
PIC17C756A
-08/L
AABBCDE
9848CAE
Example
80-Lead TQFP
MMMMMMMMMMMM
MMMMMMMMMMMM
PIC17C752
-08I/PT
AABBCDE
9817CAE
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1998 Microchip Technology Inc.
DS30289A-page 281
PIC17C7XX
NOTES:
DS30289A-page 282
1998 Microchip Technology Inc.
PIC17C7XX
APPENDIX A:MODIFICATIONS
APPENDIX B:COMPATIBILITY
The following is the list of modifications over the
PIC16CXX microcontroller family:
To convert code written for PIC16CXXX to
PIC17CXXX, the user should take the following steps:
1. Instruction word length is increased to 16-bit.
This allows larger page sizes both in program
memory (8 Kwords verses 2 Kwords) and regis-
ter file (256 bytes versus 128 bytes).
2. Four modes of operation: microcontroller, pro-
tected microcontroller, extended microcontroller,
and microprocessor.
1. Remove any TRIS and OPTION instructions,
and implement the equivalent code.
2. Separate the interrupt service routine into its
four vectors.
3. Replace:
MOVF
with:
REG1, W
3. 22 new instructions.
MOVFP
REG1, WREG
The MOVF, TRIS and OPTION instructions have
been removed.
4. Replace:
MOVF
REG1, W
REG2
4. Four new instructions (TLRD, TLWT, TABLRD,
TABLWT) for transferring data between data
memory and program memory. They can be
used to “self program” the EPROM program
memory.
MOVWF
with:
MOVPF
or
MOVFP
REG1, REG2 ; Addr(REG1)<20h
REG1, REG2 ; Addr(REG2)<20h
5. Single cycle data memory to data memory
transfers possible (MOVPF and MOVFP instruc-
tions).These instructions do not affect the Work-
ing register (WREG).
6. W register (WREG) is now directly addressable.
7. A PC high latch register (PCLATH) is extended
to 8-bits. The PCLATCH register is now both
readable and writable.
8. Data memory paging is redefined slightly.
9. DDR registers replaces function of TRIS regis-
ters.
10. Multiple Interrupt vectors added. This can
decrease the latency for servicing interrupts.
11. Stack size is increased to 16 deep.
12. BSR register for data memory paging.
13. Wake up from SLEEP operates slightly differ-
ently.
Note: If REG1 and REG2 are both at addresses
greater then 20h, two instructions are
required.
MOVFP
MOVPF
REG1, WREG ;
WREG, REG2 ;
5. Ensure that all bit names and register names are
updated to new data memory map locations.
6. Verify data memory banking.
7. Verify mode of operation for indirect addressing.
8. Verify peripheral routines for compatibility.
9. Weak pull-ups are enabled on reset.
Upgrading from PIC17C42 Devices
To convert code from the PIC17C42 to all the other
PIC17CXXX devices, the user should take the following
steps.
14. The Oscillator Start-Up Timer (OST) and
Power-Up Timer (PWRT) operate in parallel and
not in series.
15. PORTB interrupt on change feature works on all
eight port pins.
1. If the hardware multiply is to be used, ensure
that any variables at address 18h and 19h are
moved to another address.
2. Ensure that the upper nibble of the BSR was not
written with a non-zero value. This may cause
unexpected operation since the RAM bank is no
longer 0.
16. TMR0 is 16-bit plus 8-bit prescaler.
17. Second indirect addressing register added
(FSR1 and FSR2). Configuration bits can select
the FSR registers to auto-increment, auto-dec-
rement, remain unchanged after an indirect
address.
18. Hardware multiplier added (8 x 8 → 16-bit)
19. Peripheral modules operate slightly differently.
20. A/D has both a VREF+ and VREF-.
21. USARTs do not implement BRGH feature.
22. Oscillator modes slightly redefined.
23. Control/Status bits and registers have been
placed in different registers and the control bit
for globally enabling interrupts has inverse
polarity.
3. The disabling of global interrupts has been
enhanced so there is no additional testing of the
GLINTD bit after a BSF CPUSTA, GLINTD
instruction.
24. In-circuit serial programming is implemented dif-
ferently.
1998 Microchip Technology Inc.
DS30289A-page 283
PIC17C7XX
APPENDIX C:WHAT’S NEW
APPENDIX D:WHAT’S CHANGED
This is a new Data Sheet for the Following Devices:
This is a new Data Sheet. The following are changes
from the PIC17C75X data Sheet:
• PIC17C752
• PIC17C756A
• PIC17C762
• PIC17C766
Updated the Master SSP section.
Updated the 10-bit A/D section.
Minor corrections and updates throughout the data
sheet.
This Data Sheet is based of the PIC17C75X Data
Sheet (DS30246A)
PIC17C752 Data Memory upgraded to 678 bytes
Port initialization values clarified
Extended voltage specification for external memory
interface added
Some Electrical Specifications changed due to new
process technology
Clarified operation of Table Reads / Table Writes with
external memory (for microprocessor and extended
microcontroller modes).
Added waveforms / requirements for USART Asynchro-
nous mode in Electrical specifications.
Clarification to Master SSP Baud Rate Generator tim-
ing figure and associated text.
2
Added example code for I C operation using
MPLAB-C17 ’C’ code.
Updated Packaging Diagrams / Tables
DS30289A-page 284
1998 Microchip Technology Inc.
PIC17C7XX
2
External pull-up resistors are used to ensure a high
level when no device is pulling the line down.The num-
ber of devices that may be attached to the I C bus is
limited only by the maximum bus loading specification
of 400 pF.
APPENDIX E: I C OVERVIEW
This section provides an overview of the Inter-Inte-
grated Circuit (I C) bus, with Section 15.2 discussing
the operation of the SSP module in I C mode.
2
2
2
2
The I C bus is a two-wire serial interface developed by
E.1
Initiating and Terminating Data
Transfer
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to
100 Kbps.This device will communicate with fast mode
devices if attached to the same bus.
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission.The START condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure E-1 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data trans-
fer. Due to the definition of the START and STOP con-
ditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
2
The I C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hard-
ware, including general call support. Table E-1 defines
some of the I C bus terminology. For additional infor-
mation on the I C interface specification, refer to the
Philips document “The I C bus and how to use it.”
#939839340011, which can be obtained from the Phil-
ips Corporation.
2
2
2
FIGURE E-1: START AND STOP
CONDITIONS
2
In the I C interface protocol each device has an
address.When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer.That is they can be thought of as operating in either
of these two relations:
SDA
S
SCL
P
Change
of Data
Allowed
Change
of Data
Allowed
Start
Stop
Condition
Condition
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
2
TABLE E-1:
Term
I C BUS TERMINOLOGY
Description
Transmitter
Receiver
Master
The device that sends the data to the bus.
The device that receives the data from the bus.
The device which initiates the transfer, generates the clock and terminates the transfer.
The device addressed by a master.
Slave
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
1998 Microchip Technology Inc.
DS30289A-page 285
PIC17C7XX
2
E.2
ADDRESSING I C DEVICES
FIGURE E-4: SLAVE-RECEIVER
ACKNOWLEDGE
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure E-2). The
more complex is the 10-bit address with a R/W bit
(Figure E-3). For 10-bit address format, two bytes must
be transmitted with the first five bits specifying this to be
a 10-bit address.
Data
Output by
Transmitter
Data
Output by
Receiver
not acknowledge
acknowledge
SCL from
Master
9
8
2
1
FIGURE E-2: 7-BIT ADDRESS FORMAT
S
Clock Pulse for
Acknowledgment
MSb
LSb
Start
Condition
R/W ACK
S
slave address
Sent by
Slave
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
S
R/W
ACK
Start Condition
Read/Write pulse
Acknowledge
2
FIGURE E-3: I C10-BITADDRESSFORMAT
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line.This allows the slave to move the
received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech-
nique can also be implemented at the bit level,
Figure E-5. The slave will inherently stretch the clock,
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the CKP bit to enable clock
stretching when it is a receiver.
S
1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
sent by slave
= 0 for write
S
- Start Condition
R/W - Read/Write Pulse
ACK - Acknowledge
E.3
Transfer Acknowledge
All data must be transmitted per byte, with no limit to the
number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowl-
edge bit (ACK) (Figure E-4). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure E-1).
FIGURE E-5: DATA TRANSFER WAIT STATE
SDA
MSB
acknowledgment
signal from receiver
acknowledgment
signal from receiver
byte complete
interrupt with receiver
clock line held low while
interrupts are serviced
SCL
S
1
2
7
8
9
1
2
3 • 8
9
P
Start
Condition
Stop
Condition
Address
R/W ACK Wait
State
Data
ACK
DS30289A-page 286
1998 Microchip Technology Inc.
PIC17C7XX
Figure E-6 and Figure E-7 show Master-transmitter
and Master-receiver data transfer sequences.
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure E-8.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
FIGURE E-6: MASTER-TRANSMITTER SEQUENCE
For 7-bit address:
For 10-bit address:
S Slave AddressR/W A1Slave Address A2
S Slave AddressR/W A Data A Data A/A P
First 7 bits
Second byte
'0' (write)
data transferred
(n bytes - acknowledge)
(write)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
Data A
Data A/A P
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
S = Start Condition
A master transmitter addresses a slave receiver
with a 10-bit address.
From slave to master
P = Stop Condition
FIGURE E-7: MASTER-RECEIVER SEQUENCE
For 7-bit address:
For 10-bit address:
S Slave AddressR/W A1Slave Address A2
First 7 bits Second byte
(write)
S Slave AddressR/W A Data A Data
A P
'1' (read) data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
SrSlave AddressR/W A3 Data A Data A P
First 7 bits
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
(read)
S = Start Condition
A master transmitter addresses a slave receiver
with a 10-bit address.
From slave to master
P = Stop Condition
FIGURE E-8: COMBINED FORMAT
(read or write)
(n bytes + acknowledge)
S Slave AddressR/W A Data A/A Sr Slave Address R/W A Data A/A P
(write)
Direction of transfer
may change at this point
(read)
Sr = repeated
Start Condition
Transfer direction of data and acknowledgment bits depends on R/W bits.
Combined format:
SrSlave Address R/W A Slave Address A Data A
First 7 bits Second byte
Data A/A Sr Slave Address R/W A Data A
First 7 bits
Data A P
(read)
(write)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
S = Start Condition
From slave to master
P = Stop Condition
1998 Microchip Technology Inc.
DS30289A-page 287
PIC17C7XX
E.4
Multi-Master
E.5
Clock Synchronization
2
The I C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time, arbi-
tration and synchronization occur.
Clock synchronization occurs after the devices have
started arbitration. This is performed using
a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached.The low to high tran-
sition of this clock may not change the state of the SCL
line, if another device clock is still within its low period.
The SCL line is held low by the device with the longest
low period. Devices with shorter low periods enter a
high wait-state, until the SCL line comes high. When
the SCL line comes high, all devices start counting off
their high periods. The first device to complete its high
period will pull the SCL line low.The SCL line high time
is determined by the device with the shortest high
period, Figure E-10.
E.4.1
ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure E-9), and turns off its data output stage. A mas-
ter which lost arbitration can generate clock pulses until
the end of the data byte where it lost arbitration. When
the master devices are addressing the same device,
arbitration continues into the data.
FIGURE E-9: MULTI-MASTER
ARBITRATION
(TWO MASTERS)
FIGURE E-10: CLOCK SYNCHRONIZATION
transmitter 1 loses arbitration
DATA 1 SDA
start counting
HIGH period
wait
state
DATA 1
DATA 2
SDA
CLK
1
counter
reset
CLK
2
SCL
SCL
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode.This is because the winning mas-
ter-transmitter may be addressing it.
2
E.6
I C Timing Specifications
Table E-2 (Figure E-11) and Table E-3 (Figure E-12)
show the timing specifications as required by the Phil-
ips specification for I C. For additional information
Arbitration is not allowed between:
2
• A repeated START condition
please refer to Section 15.2 and Section 20.5.
• A STOP condition and a data bit
• A repeated START condition and a STOP condi-
tion
Care needs to be taken to ensure that these conditions
do not occur.
DS30289A-page 288
1998 Microchip Technology Inc.
PIC17C7XX
2
FIGURE E-11: I C BUS START/STOP BITS TIMING SPECIFICATION
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
2
TABLE E-2:
I C BUS START/STOP BITS TIMING SPECIFICATION
Microchip
Parameter
No.
Sym
Characteristic
Min
Typ Max Units
Conditions
90
91
92
93
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated
START condition
ns
ns
ns
ns
THD:STA START condition
Hold time
4000
600
After this period the first clock
pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000 ‡
600 ‡
1998 Microchip Technology Inc.
DS30289A-page 289
PIC17C7XX
2
FIGURE E-12: I C BUS DATA TIMING SPECIFICATION
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
2
TABLE E-3:
I C BUS DATA TIMING SPECIFICATION
Microchip
Parameter
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
101
102
THIGH
Clock high time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.0
0.6
—
—
µs
µs
µs
µs
ns
ns
TLOW
TR
Clock low time
4.7
—
1.3
—
SDA and SCL rise
time
—
1000
300
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
103
TF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
91
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
THD:STA START condition hold 100 kHz mode
—
After this period the first clock
pulse is generated
time
400 kHz mode
100 kHz mode
400 kHz mode
—
106
107
92
THD:DAT Data input hold time
—
0
0.9
—
TSU:DAT Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
Note 2
—
TSU:STO STOP condition setup 100 kHz mode
—
time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
109
110
TAA
Output valid from
clock
3500
1000
—
Note 1
—
TBUF
Bus free time
4.7
1.3
Time the bus must be free
before a new transmission can
start
—
D102
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement tsu;DAT ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I C bus specification) before the SCL line is
released.
DS30289A-page 290
1998 Microchip Technology Inc.
PIC17C7XX
APPENDIX F: STATUS AND CONTROL REGISTERS
FIGURE F-1: PIC17C7XX REGISTER FILE MAP
Addr Unbanked
INDF0
FSR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(4)
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
SSPADD
SSPCON1 PW3DCH
Bank 7
Bank 8
PORTA
DDRB
DDRC
TMR1
TMR2
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
PIR2
PIE2
—
DDRF
PW3DCL
DDRH
10h
11h
12h
13h
14h
15h
16h
17h
PORTC
DDRD
PORTD
DDRE
PORTE
PIR1
PORTF
DDRG
PORTH
DDRJ
PORTJ
—
PORTB
TMR3L
TMR3H
PR1
SSPCON2
CA3L
CA3H
CA4L
CA4H
TCON3
—
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
Unbanked
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
PORTG
ADCON0
ADCON1
ADRESL
ADRESH
SSPSTAT
SSPBUF
—
—
—
—
PR2
CA2H
—
PR3L/CA1L
PR3H/CA1H
TCON1
TCON2
—
PIE1
PRODL
PRODH
18h
19h
1Ah
General
Purpose
RAM
1Fh
20h
(2)
(2)
(2, 3)
(2, 3)
Bank 0
Bank 1
Bank 2
Bank 3
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked.The lower nibble of the BSR specifies the bank. All unbanked SFRs
ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh are
banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register
(BSR) bits.
3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented regis-
ter reads ‘0’s.
4: Bank 8 is only implemented on the PIC17C76X devices.
1998 Microchip Technology Inc.
DS30289A-page 291
PIC17C7XX
FIGURE F-2: ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)
R/W - 1 R/W - 1 R/W - 1 R/W - 1 R/W - x R/W - x R/W - x R/W - x
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
FS3
FS2
FS1
FS0
OV
Z
DC
C
bit7
bit0
bit 7-6: FS3:FS2: FSR1 Mode Select bits
00 = Post auto-decrement FSR1 value
01 = Post auto-increment FSR1 value
1x = FSR1 value does not change
bit 5-4: FS1:FS0: FSR0 Mode Select bits
00 = Post auto-decrement FSR0 value
01 = Post auto-increment FSR0 value
1x = FSR0 value does not change
bit 3:
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic, (in this arithmetic operation)
0 = No overflow occurred
bit 2:
bit 1:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The results of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWFand ADDLWinstructions.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow the polarity is reversed.
bit 0:
C: carry/borrow bit
For ADDWFand ADDLWinstructions. Note that a subtraction is executed by adding the two’s complement
of the second operand.
For rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the source
register.
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result
Note: For borrow the polarity is reversed.
DS30289A-page 292
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-3: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
U - 0
R = Readable bit
W = Writable bit
U = Unimplemented,
reads as ‘0’
INTEDG
T0SE
T0CS
T0PS3
T0PS2
T0PS1
T0PS0
—
bit7
bit0
-n = Value at POR reset
bit 7:
bit 6:
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
T0SE: Timer0 External Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0 (External Clock)
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit
When T0CS = 1 (Internal Clock)
Don’t care
bit 5:
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for Timer0.
1 = Internal instruction clock cycle (TCY)
0 = External clock input on the T0CKI pin
bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for Timer0.
T0PS3:T0PS0
Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
bit 0:
Unimplemented: Read as '0'
1998 Microchip Technology Inc.
DS30289A-page 293
PIC17C7XX
FIGURE F-4: CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U - 0
—
U - 0
—
R - 1
STKAV GLINTD
R/W - 1
R - 1
TO
R - 1
PD
R/W - 0 R/W - 1
POR BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5:
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh → 0h (stack overflow).
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred
(Once this bit has been cleared by a stack overflow, only a device reset will set this bit)
bit 4:
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
bit 3:
bit 2:
bit 1:
bit 0:
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDTinstruction
0 = A Watchdog Timer time-out occurred
PD: Power-down Status bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set by software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
When BODEN configuration bit is set (enabled):
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set by software)
When BODEN configuration bit is clear (disabled):
Don’t care
DS30289A-page 294
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-5: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R - 0
PEIF
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7
bit 7:
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits. The
interrupt logic forces program execution to address (20h) when a peripheral interrupt is pending.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
bit 6:
bit 5:
bit 4:
bit 3:
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin
PEIE: Peripheral Interrupt Enable bit
This bit acts as a global enable bit for the peripheral interrupts that have their corresponding enable bits
set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
bit 2:
bit 1:
bit 0:
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin
1998 Microchip Technology Inc.
DS30289A-page 295
PIC17C7XX
FIGURE F-6: PIE1 REGISTER (ADDRESS: 17h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE
R = Readable bit
W = Writable bit
-n = Value at POR reset
bit7
bit0
bit 7:
RBIE: PORTB Interrupt on Change Enable bit
1 = Enable PORTB interrupt on change
0 = Disable PORTB interrupt on change
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TMR3IE: TMR3 Interrupt Enable bit
1 = Enable TMR3 interrupt
0 = Disable TMR3 interrupt
TMR2IE: TMR2 Interrupt Enable bit
1 = Enable TMR2 interrupt
0 = Disable TMR2 interrupt
TMR1IE: TMR1 Interrupt Enable bit
1 = Enable TMR1 interrupt
0 = Disable TMR1 interrupt
CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture2 interrupt
0 = Disable Capture2 interrupt
CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture1 interrupt
0 = Disable Capture1 interrupt
TX1IE: USART1 Transmit Interrupt Enable bit
1 = Enable USART1 Transmit buffer empty interrupt
0 = Disable USART1 Transmit buffer empty interrupt
RC1IE: USART1 Receive Interrupt Enable bit
1 = Enable USART1 Receive buffer full interrupt
0 = Disable USART1 Receive buffer full interrupt
DS30289A-page 296
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-7: PIE2 REGISTER (ADDRESS: 11h, BANK 4)
R/W - 0 R/W - 0 R/W - 0
U - 0
—
R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA4IE CA3IE TX2IE RC2IE
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
SSPIE BCLIE
ADIE
bit7
bit 7:
bit 6:
bit 5:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enable SSP Interrupt
0 = Disable SSP Interrupt
BCLIE: Bus Collision Interrupt Enable bit
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
ADIE: A/D Module Interrupt Enable bit
1 = Enable A/D Module Interrupt
0 = Disable A/D Module Interrupt
bit 4:
bit 3:
Unimplemented: Read as ‘0’
CA4IE: Capture4 Interrupt Enable bit
1 = Enable Capture4 Interrupt
0 = Disable Capture4 Interrupt
bit 2:
bit 1:
bit 0:
CA3IE: Capture3 Interrupt Enable bit
1 = Enable Capture3 Interrupt
0 = Disable Capture3 Interrupt
TX2IE: USART2 Transmit Interrupt Enable bit
1 = Enable USART2 Transmit Buffer Empty Interrupt
0 = Disable USART2 Transmit Buffer Empty Interrupt
RC2IE: USART2 Receive Interrupt Enable bit
1 = Enable USART2 Receive Buffer Full Interrupt
0 = Disable USART2 Receive Buffer Full Interrupt
1998 Microchip Technology Inc.
DS30289A-page 297
PIC17C7XX
FIGURE F-8: PIR1 REGISTER (ADDRESS: 16h, BANK 1)
R/W - x R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R - 1 R - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
RBIF TMR3IF TMR2IF TMR1IF CA2IF
CA1IF TX1IF RC1IF
bit7
bit0
bit 7:
bit 6:
RBIF: PORTB Interrupt on Change Flag bit
1 = One of the PORTB inputs changed (software must end the mismatch condition)
0 = None of the PORTB inputs have changed
TMR3IF: TMR3 Interrupt Flag bit
If Capture1 is enabled (CA1/PR3 = 1)
1 = TMR3 overflowed
0 = TMR3 did not overflow
If Capture1 is disabled (CA1/PR3 = 0)
1 = TMR3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value
0 = TMR3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L) value
bit 5:
bit 4:
TMR2IF: TMR2 Interrupt Flag bit
1 = TMR2 value has rolled over to 0000h from equalling the period register (PR2) value
0 = TMR2 value has not rolled over to 0000h from equalling the period register (PR2) value
TMR1IF: TMR1 Interrupt Flag bit
If TMR1 is in 8-bit mode (T16 = 0)
1 = TMR1 value has rolled over to 0000h from equalling the period register (PR1) value
0 = TMR1 value has not rolled over to 0000h from equalling the period register (PR1) value
If Timer1 is in 16-bit mode (T16 = 1)
1 = TMR2:TMR1 value has rolled over to 0000h from equalling the period register (PR2:PR1) value
0 = TMR2:TMR1 value has not rolled over to 0000h from equalling the period register (PR2:PR1) value
bit 3:
bit 2:
bit 1:
bit 0:
CA2IF: Capture2 Interrupt Flag bit
1 = Capture event occurred on RB1/CAP2 pin
0 = Capture event did not occur on RB1/CAP2 pin
CA1IF: Capture1 Interrupt Flag bit
1 = Capture event occurred on RB0/CAP1 pin
0 = Capture event did not occur on RB0/CAP1 pin
TX1IF: USART1 Transmit Interrupt Flag bit (State controlled by hardware)
1 = USART1 Transmit buffer is empty
0 = USART1 Transmit buffer is full
RC1IF: USART1 Receive Interrupt Flag bit (State controlled by hardware)
1 = USART1 Receive buffer is full
0 = USART1 Receive buffer is empty
DS30289A-page 298
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-9: PIR2 REGISTER (ADDRESS: 10h, BANK 4)
R/W - 0 R/W - 0 R/W - 0
U - 0
—
R/W - 0 R/W - 0
CA4IF CA3IF
R - 1
TX2IF
R - 0
RC2IF
R = Readable bit
SSPIF BCLIF
ADIF
W = Writable bit
-n = Value at POR reset
bit7
bit0
bit 7:
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the
interrupt service routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I C Slave / Master
2
A transmission/reception has taken place.
I C Master
2
The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).
0 = An SSP interrupt condition has NOT occurred.
bit 6:
bit 5:
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I C master mode
0 = No bus collision has occurred
2
ADIF: A/D Module Interrupt Flag bit
1 = An A/D conversion is complete
0 = An A/D conversion is not complete
bit 4:
bit 3:
Unimplemented: Read as '0'
CA4IF: Capture4 Interrupt Flag bit
1 = Capture event occurred on RE3/CAP4 pin
0 = Capture event did not occur on RE3/CAP4 pin
bit 2:
bit 1:
bit 0:
CA3IF: Capture3 Interrupt Flag bit
1 = Capture event occurred on RG4/CAP3 pin
0 = Capture event did not occur on RG4/CAP3 pin
TX2IF:USART2 Transmit Interrupt Flag bit (State controlled by hardware)
1 = USART2 Transmit buffer is empty
0 = USART2 Transmit buffer is full
RC2IF: USART2 Receive Interrupt Flag bit (State controlled by hardware)
1 = USART2 Receive buffer is full
0 = USART2 Receive buffer is empty
1998 Microchip Technology Inc.
DS30289A-page 299
PIC17C7XX
FIGURE F-10: TXSTA1 REGISTER (ADDRESS: 15h, BANK 0)
TXSTA2 REGISTER (ADDRESS: 15h, BANK 4)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
CSRC TX9 TXEN SYNC
bit7
U - 0
—
U - 0
—
R - 1
TRMT
R/W - x
TX9D
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit0
bit 7:
CSRC: Clock Source Select bit
Synchronous mode:
1 = Master Mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
Asynchronous mode:
Don’t care
bit 6:
bit 5:
TX9: 9-bit Transmit Select bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SREN/CREN overrides TXEN in SYNC mode
bit 4:
SYNC: USART Mode Select bit
(Synchronous/Asynchronous)
1 = Synchronous mode
0 = Asynchronous mode
bit 3-2: Unimplemented: Read as '0'
bit 1:
TRMT: Transmit Shift Register (TSR) Empty bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data (can be used to calculated the parity in software)
DS30289A-page 300
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-11: RCSTA1 REGISTER (ADDRESS: 13h, BANK 0)
RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN RX9 SREN CREN
bit7
U - 0
—
R - 0
FERR
R - 0
OERR
R - x
RX9D
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 0
bit 7:
bit 6:
bit 5:
SPEN: Serial Port Enable bit
1 = Configures TX/CK and RX/DT pins as serial port pins
0 = Serial port disabled
RX9: 9-bit Receive Select bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
bit 4:
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable continuous reception
0 = Disables continuous reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
bit 3:
bit 2:
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
bit 1:
bit 0:
OERR: Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
RX9D: 9th bit of receive data (can be the software calculated parity bit)
1998 Microchip Technology Inc.
DS30289A-page 301
PIC17C7XX
FIGURE F-12: TCON1 REGISTER (ADDRESS: 16h, BANK 3)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
bit7
bit0
bit 7-6: CA2ED1:CA2ED0: Capture2 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 5-4: CA1ED1:CA1ED0: Capture1 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 3:
bit 2:
bit 1:
bit 0:
T16: Timer2:Timer1 Mode Select bit
1 = Timer2 and Timer1 form a 16-bit timer
0 = Timer2 and Timer1 are two 8-bit timers
TMR3CS: Timer3 Clock Source Select bit
1 = TMR3 increments off the falling edge of the RB5/TCLK3 pin
0 = TMR3 increments off the internal clock
TMR2CS: Timer2 Clock Source Select bit
1 = TMR2 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR2 increments off the internal clock
TMR1CS: Timer1 Clock Source Select bit
1 = TMR1 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR1 increments off the internal clock
DS30289A-page 302
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-13: TCON2 REGISTER (ADDRESS: 17h, BANK 3)
R - 0
R - 0
R/W - 0
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
bit7
bit0
bit 7:
CA2OVF: Capture2 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L)
before the next capture event occurred.The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture2 register
0 = No overflow occurred on Capture2 register
bit 6:
CA1OVF: Capture1 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(PR3H/CA1H:PR3L/CA1L) before the next capture event occurred. The capture register retains the old-
est unread capture value (last capture before overflow). Subsequent capture events will not update the
capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture1 register
0 = No overflow occurred on Capture1 register
bit 5:
bit 4:
bit 3:
PWM2ON: PWM2 On bit
1 = PWM2 is enabled
(The RB3/PWM2 pin ignores the state of the DDRB<3> bit)
0 = PWM2 is disabled
(The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction)
PWM1ON: PWM1 On bit
1 = PWM1 is enabled
(The RB2/PWM1 pin ignores the state of the DDRB<2> bit)
0 = PWM1 is disabled
(The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction)
CA1/PR3: CA1/PR3 Register Mode Select bit
1 = Enables Capture1
(PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without a period register)
0 = Enables the Period register
(PR3H/CA1H:PR3L/CA1L is the Period register for Timer3)
bit 2:
bit 1:
TMR3ON: Timer3 On bit
1 = Starts Timer3
0 = Stops Timer3
TMR2ON: Timer2 On bit
This bit controls the incrementing of the TMR2 register. When TMR2:TMR1 form the 16-bit timer (T16 is
set), TMR2ON must be set. This allows the MSB of the timer to increment.
1 = Starts Timer2 (Must be enabled if the T16 bit (TCON1<3>) is set)
0 = Stops Timer2
bit 0:
TMR1ON: Timer1 On bit
When T16 is set (in 16-bit Timer Mode)
1 = Starts 16-bit TMR2:TMR1
0 = Stops 16-bit TMR2:TMR1
When T16 is clear (in 8-bit Timer Mode)
1 = Starts 8-bit Timer1
0 = Stops 8-bit Timer1
1998 Microchip Technology Inc.
DS30289A-page 303
PIC17C7XX
FIGURE F-14: TCON3 REGISTER (ADDRESS: 16h, BANK 7)
U-0
-
R - 0
R - 0
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Reads as ‘0’
CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
bit7
bit0
-n = Value at POR reset
bit 7:
bit 6:
Unimplemented: Read as ‘0’
CA4OVF: Capture4 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture4 registers
0 = No overflow occurred on Capture4 registers
bit 5:
CA3OVF: Capture3 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA3H:CA3L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture3 registers
0 = No overflow occurred on Capture3 registers
bit 4-3: CA4ED1:CA4ED0: Capture4 Mode Select bits
00= Capture on every falling edge
01= Capture on every rising edge
10= Capture on every 4th rising edge
11= Capture on every 16th rising edge
bit 2-1: CA3ED1:CA3ED0: Capture3 Mode Select bits
00= Capture on every falling edge
01= Capture on every rising edge
10= Capture on every 4th rising edge
11= Capture on every 16th rising edge
bit 0:
PWM3ON: PWM3 On bit
1 = PWM3 is enabled
(The RG5/PWM3 pin ignores the state of the DDRG<5> bit)
0 = PWM3 is disabled
(The RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)
DS30289A-page 304
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-15: ADCON0 REGISTER (ADDRESS: 14h, BANK 5)
R/W-0 R/W-0 R/W-0
CHS3 CHS2 CHS1
bit7
R/W-0
CHS0
U-0
—
R/W-0
U-0
—
R/W-0
ADON
GO/DONE
R =Readable bit
W = Writable bit
U =Unimplemented bit,
read as ‘0’
bit0
- n = Value at POR reset
bit 7-4: CHS3:CHS0: Analog Channel Select bits
0000 = channel 0, (AN0)
0001 = channel 1, (AN1)
0010 = channel 2, (AN2)
0011 = channel 3, (AN3)
0100 = channel 4, (AN4)
0101 = channel 5, (AN5)
0110 = channel 6, (AN6)
0111 = channel 7, (AN7)
1000 = channel 8, (AN8)
1001 = channel 9, (AN9)
1010 = channel 10, (AN10)
1011 = channel 11, (AN11)
1100 = channel 12, (AN12) (PIC17C76X only)
1101 = channel 13, (AN13) (PIC17C76X only)
1110 = channel 14, (AN14) (PIC17C76X only)
1111 = channel 15, (AN15) (PIC17C76X only)
11xx = RESERVED, do not select
bit 3:
bit 2:
Unimplemented: Read as '0'
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared
by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
1998 Microchip Technology Inc.
DS30289A-page 305
PIC17C7XX
FIGURE F-16: ADCON1 REGISTER (ADDRESS 15h, BANK 5)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PCFG3
PCFG2
PCFG1
PCFG0
R =Readable bit
W = Writable bit
U =Unimplemented
bit, read as ‘0’
bit0
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/8
01 = FOSC/32
10 = FOSC/64
11 = FRC (clock derived from an internal RC oscillation)
bit 5:
bit 4:
ADFM: A/D Result format select
1 = Right justified. 6 Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ’0’.
Unimplemented: Read as '0'
bit 3-0: PCFG3:PCFG1: A/D Port Configuration Control bits
PCFG3:PCFG1 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
000
001
010
011
100
101
110
111
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
bit 0:
PCFG0: A/D Voltage Reference Select bit
1 = A/D reference is the VREF+ and VREF- pins
0 = A/D reference is AVDD and AVSS
Note:When this bit is set, ensure that the A/D voltage reference specifications are met.
DS30289A-page 306
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-17: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6)
R/W-0 R/W-0
SMP CKE
bit7
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
bit0
- n = Value at POR reset
bit 7:
SMP: SPI Data Input Sample Phase bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
2
In I C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6:
CKE: SPI Clock Edge Select (Figure 15-9, Figure 15-11, and Figure 15-12)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
2
bit 5:
bit 4:
D/A: Data/Address bit (I C slave mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
2
P: Stop bit (I C mode only)
This bit is cleared when the SSP module is disabled, SSPEN is cleared
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
2
bit 3:
bit 2:
S: Start bit (I C mode only)
This bit is cleared when the SSP module is disabled, SSPEN is cleared
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
2
R/W: Read/Write bit information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to
the next start bit, stop bit, or not ACK bit.
2
In I C slave mode:
1 = Read
0 = Write
2
In I C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the SSP is in IDLE mode.
2
bit 1:
bit 0:
UA: Update Address (10-bit I C slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
2
Transmit (I C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
1998 Microchip Technology Inc.
DS30289A-page 307
PIC17C7XX
FIGURE F-18: SSPCON1: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 11h, BANK 6)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit, read
as ‘0’
- n = Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
Master Mode:
2
1 = A write to the SSPBUF register was attempted while the I C conditions were not valid for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data
in SSPSR is lost. Overflow can only occur in slave mode. In slave mode the user must read the SSPBUF, even if
only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new recep-
tion (and transmission) is initiated by writing to the SSPBUF register (Must be cleared by software).
0 = No overflow
2
In I C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit
mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
2
In I C mode
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: In SPI mode, pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
2
In I C slave mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
2
In I C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI master mode, clock = FOSC/4
0001= SPI master mode, clock = FOSC/16
0010= SPI master mode, clock = FOSC/64
0011= SPI master mode, clock = TMR2 output/2
0100= SPI slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
2
0110= I C slave mode, 7-bit address
2
0111= I C slave mode, 10-bit address
2
1000= I C master mode, clock = FOSC / (4 * (SSPADD+1) )
1xx1= Reserved
1x1x= Reserved
DS30289A-page 308
1998 Microchip Technology Inc.
PIC17C7XX
FIGURE F-19: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit, Read
as ‘0’
- n = Value at POR reset
2
bit 7:
bit 6:
GCEN: General Call Enable bit (In I C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
2
ACKSTAT: Acknowledge Status bit (In I C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
2
bit 5:
bit 4:
ACKDT: Acknowledge Data bit (In I C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
2
ACKEN: Acknowledge Sequence Enable bit (In I C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically cleared by hard-
ware.
0 = Acknowledge sequence idle
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
2
bit 3:
RCEN: Receive Enable bit (In I C master mode only).
2
1 = Enables Receive mode for I C
0 = Receive idle
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
2
bit 2:
PEN: Stop Condition Enable bit (In I C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
2
bit 1: RSEN: Repeated Start Condition Enabled bit (In I C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled)
2
bit 0: SEN: Start Condition Enabled bit (In I C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
2
Note: If the I C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be
written (or writes to the SSPBUF are disabled).
1998 Microchip Technology Inc.
DS30289A-page 309
PIC17C7XX
NOTES:
DS30289A-page 310
1998 Microchip Technology Inc.
PIC17C7XX
Baud Rate Formula .......................................................... 118
Baud Rate Generator ....................................................... 151
Baud Rate Generator (BRG) ............................................ 118
Baud Rates
Asynchronous Mode................................................. 120
Synchronous Mode................................................... 119
BCF .................................................................................. 202
BCLIE ......................................................................... 34, 297
BCLIF ......................................................................... 36, 299
BF..................................................... 132, 142, 157, 160, 307
Bit Manipulation................................................................ 196
Block Diagrams
INDEX
A
A/D
Accuracy/Error .......................................................... 187
ADCON0 Register..................................................... 177
ADCON1 Register..................................................... 178
ADIF bit..................................................................... 179
Analog Input Model Block Diagram........................... 182
Analog-to-Digital Converter....................................... 177
Block Diagram........................................................... 179
Configuring Analog Port Pins.................................... 184
Configuring the Interrupt ........................................... 179
Configuring the Module............................................. 179
Connection Considerations....................................... 187
Conversion Clock...................................................... 183
Conversions.............................................................. 184
Converter Characteristics ......................................... 260
Delays....................................................................... 181
Effects of a Reset...................................................... 186
Equations.................................................................. 181
Flowchart of A/D Operation....................................... 185
GO/DONE bit ............................................................ 179
Internal Sampling Switch (Rss) Impedence.............. 181
Operation During Sleep ............................................ 186
Sampling Requirements............................................ 181
Sampling Time.......................................................... 181
Source Impedence.................................................... 181
Time Delays.............................................................. 181
Transfer Function...................................................... 187
A/D Interrupt................................................................ 36, 299
A/D Interrupt Flag bit, ADIF......................................... 36, 299
A/D Module Interrupt Enable, ADIE ............................ 34, 297
ACK........................................................................... 142, 286
Acknowledge Data bit, AKD.............................................. 134
Acknowledge Data bitr, AKD............................................. 309
Acknowledge Pulse........................................................... 142
Acknowledge Sequence Enable bit, AKE ................. 134, 309
Acknowledge Status bit, AKS ................................... 134, 309
ADCON0............................................................................. 47
ADCON1............................................................................. 47
ADDLW............................................................................. 200
ADDWF............................................................................. 200
ADDWFC .......................................................................... 201
ADIE............................................................................ 34, 297
ADIF............................................................................ 36, 299
ADRES Register ............................................................... 177
ADRESH............................................................................. 47
ADRESL.............................................................................. 47
AKD........................................................................... 134, 309
AKE........................................................................... 134, 309
AKS................................................................... 134, 157, 309
ALU....................................................................................... 9
ALUSTA...................................................................... 46, 196
ALUSTA Register................................................................ 49
ANDLW............................................................................. 201
ANDWF............................................................................. 202
Application Note AN552,'Implementing Wake-up
A/D............................................................................ 179
Analog Input Model................................................... 182
Baud Rate Generator ............................................... 151
BSR Operation ........................................................... 56
External Brown-out Protection Circuit (Case1)........... 29
External Power-on Reset Circuit ................................ 22
External Program Memory Connection ...................... 43
2
I C Master Mode ...................................................... 149
2
I C Module................................................................ 141
Indirect Addressing..................................................... 53
On-chip Reset Circuit ................................................. 21
PORTD....................................................................... 78
PORTE ........................................................... 80, 88, 89
Program Counter Operation ....................................... 55
PWM......................................................................... 105
RA0 and RA1.............................................................. 70
RA2............................................................................. 70
RA3............................................................................. 71
RA4 and RA5.............................................................. 71
RB3:RB2 Port Pins..................................................... 73
RB7:RB4 and RB1:RB0 Port Pins.............................. 72
RC7:RC0 Port Pins..................................................... 76
2
SSP (I C Mode)........................................................ 141
SSP (SPI Mode) ....................................................... 135
2
SSP Module (I C Master Mode)............................... 131
2
SSP Module (I C Slave Mode)................................. 131
SSP Module (SPI Mode) .......................................... 131
Timer3 with One Capture and One Period
Register .................................................................... 108
TMR1 and TMR2 in 16-bit Timer/Counter Mode ...... 103
TMR1 and TMR2 in Two 8-bit Timer/Counter
Mode......................................................................... 102
TMR3 with Two Capture Registers........................... 110
Using CALL, GOTO.................................................... 55
WDT ......................................................................... 191
BODEN............................................................................... 29
Borrow ...................................................................................9
BRG.......................................................................... 118, 151
Brown-out Protection.......................................................... 29
Brown-out Reset (BOR)...................................................... 29
BSF................................................................................... 203
BSR .............................................................................. 46, 56
BSR Operation ................................................................... 56
BTFSC.............................................................................. 203
BTFSS.............................................................................. 204
BTG .................................................................................. 204
Buffer Full bit, BF.............................................................. 142
Buffer Full Status bit, BF........................................... 132, 307
Bus Arbitration.................................................................. 168
Bus Collision
on Keystroke.' ..................................................................... 72
Application Note AN578, "Use of the SSP Module
in the I2C Multi-Master Environment." .............................. 141
Assembler
MPASM Assembler................................................... 232
Asynchronous Master Transmission................................. 122
Asynchronous Transmitter................................................ 121
B
Section...................................................................... 168
Bus Collision During a RESTART Condition .................... 171
Bus Collision During a Start Condition ............................. 169
Bus Collision During a Stop Condition.............................. 172
Bus Collision Interrupt Enable, BCLIE........................ 34, 297
Bus Collision Interrupt Flag bit, BCLIF ....................... 36, 299
Bank Select Register (BSR)................................................ 56
Banking......................................................................... 44, 56
1998 Microchip Technology Inc.
DS30289A-page 311
PIC17C7XX
CPFSEQ........................................................................... 207
CPFSGT ........................................................................... 207
CPFSLT............................................................................ 208
CPUSTA ............................................................... 46, 50, 192
Crystal Operation, Overtone Crystals................................. 16
Crystal or Ceramic Resonator Operation............................ 16
Crystal Oscillator................................................................. 15
D
C
C..............................................................................9, 49, 292
C Compiler ........................................................................233
CA1/PR3 ...........................................................................100
CA1ED0 ..............................................................................99
CA1ED1 ..............................................................................99
CA1IE..................................................................................33
CA1IF..........................................................................35, 298
CA1OVF............................................................................100
CA2ED0 ..............................................................................99
CA2ED1 ..............................................................................99
CA2H.............................................................................26, 47
CA2IE..........................................................................33, 109
CA2IF..................................................................35, 109, 298
CA2L .............................................................................26, 47
CA2OVF............................................................................100
CA3H...................................................................................48
CA3IE..........................................................................34, 297
CA3IF..........................................................................36, 299
CA3L ...................................................................................48
CA4H...................................................................................48
CA4IE..........................................................................34, 297
CA4IF..........................................................................36, 299
Calculating Baud Rate Error .............................................118
CALL ...........................................................................52, 205
Capacitor Selection
D/A............................................................................ 132, 307
Data Memory
GPR...................................................................... 41, 44
Indirect Addressing..................................................... 53
Organization ............................................................... 44
SFR ............................................................................ 41
Data Memory Banking ........................................................ 44
Data/Address bit, D/A ............................................... 132, 307
DAW ................................................................................. 208
DC........................................................................... 9, 49, 292
DDRB...................................................................... 25, 46, 72
DDRC ..................................................................... 26, 46, 76
DDRD ..................................................................... 26, 46, 78
DDRE...................................................................... 26, 46, 80
DDRF.................................................................................. 47
DDRG ................................................................................. 47
DECF................................................................................ 209
DECFSNZ......................................................................... 210
DECFSZ ........................................................................... 209
Delay From External Clock Edge........................................ 96
Development Support....................................................... 231
Development Tools........................................................... 231
Digit Borrow .......................................................................... 9
Digit Carry (DC) .................................................................... 9
Duty Cycle ........................................................................ 105
E
Ceramic Resonators ...................................................16
Crystal Oscillator.........................................................16
Capture .......................................................................99, 108
Capture Sequence to Read Example................................111
Capture1
Mode...........................................................................99
Overflow............................................100, 101, 303, 304
Capture1 Interrupt.......................................................35, 298
Capture2
Electrical Characteristics
Mode...........................................................................99
Overflow............................................100, 101, 303, 304
Capture2 Interrupt.......................................................35, 298
Capture3 Interrupt Enable, CA3IE ..............................34, 297
Capture3 Interrupt Flag bit, CA3IF..............................36, 299
Capture4 Interrupt Enable, CA4IE ..............................34, 297
Capture4 Interrupt Flag bit, CA4IF..............................36, 299
Carry (C) ...............................................................................9
Ceramic Resonators ...........................................................15
Circular Buffer .....................................................................52
CKE...........................................................................132, 307
CKP...........................................................................133, 308
Clearing the Prescaler.......................................................191
Clock Polarity Select bit, CKP...................................133, 308
Clock/Instruction Cycle (Figure)..........................................19
Clocking Scheme/Instruction Cycle.....................................19
CLRF.................................................................................205
CLRWDT...........................................................................206
Code Examples
Indirect Addressing .....................................................53
Loading the SSPBUF register...................................136
Saving Status and WREG in RAM..............................40
Table Read .................................................................62
Table Write..................................................................60
Code Protection ................................................................193
COMF................................................................................206
Configuration
PIC17C752/756
Absolute Maximum Ratings.............................. 235
Capture Timing................................................. 251
CLKOUT and I/O Timing .................................. 248
DC Characteristics............................................ 237
External Clock Timing....................................... 247
Memory Interface Read Timing ........................ 263
Memory Interface Write Timing ........................ 262
Parameter Measurement Information............... 246
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing................... 249
Timer0 Clock Timing......................................... 250
Timer1, Timer2 and Timer3 Clock Timing ........ 250
Timing Parameter Symbology .......................... 245
USART Module Synchronous Receive
Timing............................................................... 258
USART Module Synchronous Transmission
Timing............................................................... 258
EPROM Memory Access Time Order Suffix....................... 43
Extended Microcontroller.................................................... 41
Extended Microcontroller Mode.......................................... 43
External Memory Interface.................................................. 43
External Program Memory Waveforms............................... 43
F
Family of Devices
PIC17C75X................................................................... 6
FERR................................................................................ 123
Flowcharts
Bits............................................................................190
Locations...................................................................190
Oscillator.............................................................15, 190
Word .........................................................................189
Acknowledge ............................................................ 164
Master Receiver ....................................................... 161
Master Transmit........................................................ 158
DS30289A-page 312
1998 Microchip Technology Inc.
PIC17C7XX
Restart Condition ...................................................... 155
Start Condition .......................................................... 153
Stop Condition .......................................................... 166
FOSC0.............................................................................. 189
FOSC1.............................................................................. 189
FS0 ............................................................................. 49, 292
FS1 ............................................................................. 49, 292
FS2 ............................................................................. 49, 292
FS3 ............................................................................. 49, 292
FSR0............................................................................. 46, 53
FSR1............................................................................. 46, 53
Fuzzy Logic Dev. System (fuzzyTECH -MP) .................. 233
G
GCE .......................................................................... 134, 309
General Call Address Sequence....................................... 147
General Call Address Support .......................................... 147
General Call Enable bit, GCE ................................... 134, 309
General Format for Instructions ........................................ 196
General Purpose RAM........................................................ 41
General Purpose RAM Bank............................................... 56
General Purpose Register (GPR) ....................................... 44
GLINTD......................................................... 37, 50, 109, 192
Global Interrupt Disable bit, GLINTD .................................. 37
GOTO ............................................................................... 210
GPR (General Purpose Register) ....................................... 44
GPR Banks ......................................................................... 56
Graphs
Master-Transmitter Sequence.................................. 287
Multi-master.............................................................. 288
START...................................................................... 285
STOP................................................................ 285, 286
Transfer Acknowledge.............................................. 286
2
I C Master Mode Receiver Flowchart............................... 161
I C Master Mode Reception ............................................. 160
I C Master Mode Restart Condition.................................. 154
I C Mode Selection........................................................... 141
2
2
2
2
I C Module
Acknowledge Flowchart............................................ 164
Acknowledge Sequence timing ................................ 163
Addressing................................................................ 143
Baud Rate Generator ............................................... 151
Block Diagram .......................................................... 149
BRG Block Diagram ................................................. 151
BRG Reset due to SDA Collision ............................. 170
BRG Timing.............................................................. 151
Bus Arbitration.......................................................... 168
Bus Collision............................................................. 168
Acknowledge.................................................... 168
Restart Condition.............................................. 171
Restart Condition Timing (Case1).................... 171
Restart Condition Timing (Case2).................... 171
Start Condition.................................................. 169
Start Condition Timing.............................. 169, 170
Stop Condition.................................................. 172
Stop Condition Timing (Case1) ........................ 172
Stop Condition Timing (Case2) ........................ 172
Transmit Timing................................................ 168
Bus Collision timing .................................................. 168
Clock Arbitration ....................................................... 167
Clock Arbitration Timing (Master Transmit).............. 167
Conditions to not give ACK Pulse............................. 142
General Call Address Support.................................. 147
Master Mode............................................................. 149
Master Mode 7-bit Reception timing......................... 162
Master Mode Operation............................................ 150
Master Mode Start Condition.................................... 152
Master Mode Transmission ...................................... 157
Master Mode Transmit Sequence ............................ 150
Master Transmit Flowchart....................................... 158
Multi-Master Communication.................................... 168
Multi-master Mode.................................................... 150
Operation.................................................................. 141
Repeat Start Condition timing................................... 154
Restart Condition Flowchart ..................................... 155
Slave Mode............................................................... 142
Slave Reception ....................................................... 143
Slave Transmission .................................................. 144
SSPBUF ................................................................... 142
Start Condition Flowchart ......................................... 153
Stop Condition Flowchart ......................................... 166
Stop Condition Receive or Transmit timing .............. 165
Stop Condition timing ............................................... 165
Waveforms for 7-bit Reception................................. 144
Waveforms for 7-bit Transmission............................ 144
IOH vs. VOH, VDD = 3V .............................................. 272
IOH vs. VOH, VDD = 5V .............................................. 273
IOL vs. VOL, VDD = 3V ............................................... 273
IOL vs. VOL, VDD = 5V ............................................... 274
Maximum IDD vs. Frequency (External Clock
125°C to -40°C) ........................................................ 269
Maximum IPD vs. VDD Watchdog Disabled............... 270
Maximum IPD vs. VDD Watchdog Enabled................ 271
RC Oscillator Frequency vs. VDD (Cext = 100 pF) ... 266
RC Oscillator Frequency vs. VDD (Cext = 22 pF) ..... 266
RC Oscillator Frequency vs. VDD (Cext = 300 pF) ... 267
Transconductance of LF Oscillator vs.VDD ............... 268
Transconductance of XT Oscillator vs. VDD.............. 268
Typical IDD vs. Frequency (External Clock 25°C) ..... 269
Typical IPD vs. VDD Watchdog Disabled 25°C .......... 270
Typical IPD vs. VDD Watchdog Enabled 25°C........... 271
Typical RC Oscillator vs. Temperature ..................... 265
VIH, VIL of MCLR, T0CKI and OSC1 (In RC Mode)
vs. VDD...................................................................... 275
VTH (Input Threshold Voltage) of I/O Pins
vs. VDD...................................................................... 274
VTH (Input Threshold Voltage) of OSC1 Input
(In XT, HS, and LP Modes) vs. VDD......................... 275
WDT Timer Time-Out Period vs. VDD ....................... 272
H
Hardware Multiplier............................................................. 65
I
I/O Ports
Bi-directional ............................................................... 91
I/O Ports...................................................................... 69
Programming Considerations ..................................... 91
Read-Modify-Write Instructions................................... 91
Successive Operations ............................................... 92
2
I C Module Address Register, SSPADD .......................... 142
I C Slave Mode ................................................................ 142
2
INCF ................................................................................. 211
INCFSNZ.......................................................................... 212
INCFSZ............................................................................. 211
In-Circuit Serial Programming .......................................... 194
INDF0 ........................................................................... 46, 53
INDF1 ........................................................................... 46, 53
Indirect Addressing
2
I C..................................................................................... 141
2
Addressing I C Devices............................................ 286
Arbitration.................................................................. 288
Combined Format ..................................................... 287
2
I C Overview............................................................. 285
Initiating and Terminating Data Transfer................... 285
Master-Receiver Sequence ...................................... 287
Indirect Addressing..................................................... 53
Operation.................................................................... 53
1998 Microchip Technology Inc.
DS30289A-page 313
PIC17C7XX
Instruction Set Summary .................................................. 195
Instructions
TABLRD ..................................................................... 62
TLRD .......................................................................... 62
INT Pin................................................................................ 38
INTE.................................................................................... 32
Registers.....................................................................53
Initialization Conditions for Special Function Registers ......25
Initializing PORTB...............................................................73
Initializing PORTC...............................................................76
Initializing PORTD...............................................................78
Initializing PORTE...................................................80, 82, 84
INSTA..................................................................................46
Instruction Flow/Pipelining ..................................................19
Instruction Set ...................................................................198
ADDLW.....................................................................200
ADDWF.....................................................................200
ADDWFC ..................................................................201
ANDLW.....................................................................201
ANDWF.....................................................................202
BCF...........................................................................202
BSF...........................................................................203
BTFSC ......................................................................203
BTFSS ......................................................................204
BTG...........................................................................204
CALL.........................................................................205
CLRF.........................................................................205
CLRWDT...................................................................206
COMF .......................................................................206
CPFSEQ ...................................................................207
CPFSGT ...................................................................207
CPFSLT ....................................................................208
DAW..........................................................................208
DECF ........................................................................209
DECFSNZ.................................................................210
DECFSZ....................................................................209
GOTO .......................................................................210
INCF..........................................................................211
INCFSNZ ..................................................................212
INCFSZ.....................................................................211
IORLW ......................................................................212
IORWF......................................................................213
LCALL.......................................................................213
MOVFP .....................................................................214
MOVLB .....................................................................214
MOVLR .....................................................................215
MOVLW ....................................................................215
MOVPF .....................................................................216
MOVWF ....................................................................216
MULLW.....................................................................217
MULWF.....................................................................217
NEGW.......................................................................218
NOP ..........................................................................218
RETFIE .....................................................................219
RETLW .....................................................................219
RETURN...................................................................220
RLCF.........................................................................220
RLNCF......................................................................221
RRCF........................................................................221
RRNCF .....................................................................222
SETF.........................................................................222
SLEEP ......................................................................223
SUBLW .....................................................................223
SUBWF.....................................................................224
SUBWFB...................................................................224
SWAPF .....................................................................225
TABLRD............................................................225, 226
TABLWT ...........................................................226, 227
TLRD.........................................................................227
TLWT ........................................................................228
TSTFSZ ....................................................................228
XORLW.....................................................................229
XORWF.....................................................................229
INTEDG ........................................................................ 51, 95
2
Inter-Integrated Circuit (I
C) ............................................. 131
Internal Sampling Switch (Rss) Impedence...................... 181
Interrupt on Change Feature .............................................. 72
Interrupt Status Register (INTSTA)..................................... 32
Interrupts
A/D Interrupt ....................................................... 36, 299
Bus Collision Interrupt ........................................ 36, 299
Capture1 Interrupt .............................................. 35, 298
Capture2 Interrupt .............................................. 35, 298
Capture3 Interrupt .............................................. 36, 299
Capture4 Interrupt .............................................. 36, 299
Context Saving ........................................................... 37
Flag bits
TMR1IE .............................................................. 31
TMR1IF............................................................... 31
TMR2IE .............................................................. 31
TMR2IF............................................................... 31
TMR3IE .............................................................. 31
TMR3IF............................................................... 31
Global Interrupt Disable.............................................. 37
Interrupts .................................................................... 31
Logic........................................................................... 31
Operation.................................................................... 37
Peripheral Interrupt Enable......................................... 33
Peripheral Interrupt Request ...................................... 35
PIE2 Register ............................................................. 34
PIR1 Register ............................................................. 35
PIR2 Register ............................................................. 36
PORTB Interrupt on Change .............................. 35, 298
PWM......................................................................... 106
RA0/INT...................................................................... 37
Status Register........................................................... 32
Synchronous Serial Port Interrupt ...................... 36, 299
T0CKI Interrupt........................................................... 37
Timing......................................................................... 38
TMR1 Overflow Interrupt .................................... 35, 298
TMR2 Overflow Interrupt .................................... 35, 298
TMR3 Overflow Interrupt .................................... 35, 298
USART1 Receive Interrupt................................. 35, 298
USART1 Transmit Interrupt................................ 35, 298
USART2 Receive Interrupt................................. 36, 299
Vectors
Peripheral Interrupt............................................. 37
Program Memory Locations ............................... 41
RA0/INT Interrupt ............................................... 37
T0CKI Interrupt................................................... 37
Vectors/Priorities ........................................................ 37
Wake-up from SLEEP .............................................. 192
INTF.................................................................................... 32
INTSTA............................................................................... 46
INTSTA Register................................................................. 32
IORLW.............................................................................. 212
IORWF.............................................................................. 213
L
LCALL......................................................................... 52, 213
M
Maps
Register File Map ............................................... 45, 291
Memory
External Interface ....................................................... 43
DS30289A-page 314
1998 Microchip Technology Inc.
PIC17C7XX
External Memory Waveforms...................................... 43
Memory Map (Different Modes) .................................. 42
Mode Memory Access ................................................ 42
Organization................................................................ 41
Program Memory ........................................................ 41
Program Memory Map ................................................ 41
Microcontroller .................................................................... 41
Microprocessor ................................................................... 41
Minimizing Current Consumption...................................... 193
MOVFP ....................................................................... 44, 214
Moving Data Between Data and Program Memories.......... 44
MOVLB ....................................................................... 44, 214
MOVLR ............................................................................. 215
MOVLW ............................................................................ 215
MOVPF ....................................................................... 44, 216
MOVWF ............................................................................ 216
MPLAB-C.......................................................................... 233
MPSIM Software Simulator............................................... 233
MULLW............................................................................. 217
Multi-Master Communication ............................................ 168
Multi-Master Mode ............................................................ 150
Multiply Examples
16 x 16 Routine........................................................... 66
16 x 16 Signed Routine............................................... 67
8 x 8 Routine............................................................... 65
8 x 8 Signed Routine................................................... 65
MULWF............................................................................. 217
N
NEGW............................................................................... 218
NOP .................................................................................. 218
O
PICDEM-2 Low-Cost PIC16CXX Demo Board................. 232
PICDEM-3 Low-Cost PIC16C9XXX Demo Board ............ 232
PICMASTER In-Circuit Emulator...................................... 231
PICSTART Low-Cost Development System .................... 231
PIE.................................................................... 124, 128, 130
PIE1.............................................................................. 26, 46
PIE2........................................................................ 26, 34, 47
PIR.................................................................... 124, 128, 130
PIR1.............................................................................. 26, 46
PIR2.............................................................................. 26, 47
PM0 .......................................................................... 189, 193
PM1 .......................................................................... 189, 193
POP.............................................................................. 37, 52
POR.................................................................................... 22
PORTA ................................................................... 25, 46, 70
PORTB ................................................................... 25, 46, 72
PORTB Interrupt on Change ...................................... 35, 298
PORTC................................................................... 26, 46, 76
PORTD................................................................... 26, 46, 78
PORTE ................................................................... 26, 46, 80
PORTF ............................................................................... 47
PORTG............................................................................... 47
Power-down Mode............................................................ 192
Power-on Reset (POR)....................................................... 22
Power-up Timer (PWRT).................................................... 22
PR1............................................................................... 26, 47
PR2............................................................................... 26, 47
PR3/CA1H.......................................................................... 26
PR3/CA1L........................................................................... 26
PR3H/CA1H ....................................................................... 47
PR3L/CA1L......................................................................... 47
Prescaler Assignments....................................................... 97
PRO MATE Universal Programmer.................................. 231
PRODH......................................................................... 28, 48
PRODL ......................................................................... 28, 48
Program Counter (PC)........................................................ 55
Program Memory
Opcode Field Descriptions................................................ 195
Opcodes.............................................................................. 55
Oscillator
Configuration....................................................... 15, 190
Crystal......................................................................... 15
External Clock............................................................. 17
External Crystal Circuit ............................................... 17
External Parallel Resonant Crystal Circuit.................. 17
External Series Resonant Crystal Circuit.................... 17
RC............................................................................... 18
RC Frequencies........................................................ 267
Oscillator Start-up Time (Figure)......................................... 22
Oscillator Start-up Timer (OST) .......................................... 22
OST..................................................................................... 22
OV........................................................................... 9, 49, 292
Overflow (OV) ....................................................................... 9
P
P................................................................................ 132, 307
Packaging Information ...................................................... 277
PC (Program Counter)........................................................ 55
PCFG0 bit ................................................................. 178, 306
PCFG1 bit ................................................................. 178, 306
PCFG2 bit ................................................................. 178, 306
PCH .................................................................................... 55
PCL....................................................................... 46, 55, 196
PCLATH........................................................................ 46, 55
PD............................................................................... 50, 192
PEIE............................................................................ 32, 109
PEIF.................................................................................... 32
Peripheral Bank .................................................................. 56
Peripheral Banks................................................................. 56
Peripheral Interrupt Enable................................................. 33
Peripheral Interrupt Request (PIR1) ................................... 35
Peripheral Register Banks .................................................. 44
PICDEM-1 Low-Cost PIC16/17 Demo Board ................... 232
External Access Waveforms....................................... 43
External Connection Diagram..................................... 43
Map............................................................................. 41
Modes
Extended Microcontroller.................................... 41
Microcontroller.................................................... 41
Microprocessor................................................... 41
Protected Microcontroller ................................... 41
Operation.................................................................... 41
Organization ............................................................... 41
Protected Microcontroller.................................................... 41
PS0............................................................................... 51, 95
PS1............................................................................... 51, 95
PS2............................................................................... 51, 95
PS3............................................................................... 51, 95
PUSH............................................................................ 37, 52
PW1DCH...................................................................... 26, 47
PW1DCL....................................................................... 26, 47
PW2DCH...................................................................... 26, 47
PW2DCL....................................................................... 26, 47
PW3DCH...................................................................... 28, 48
PW3DCL....................................................................... 28, 48
PWM........................................................................... 99, 105
Duty Cycle ................................................................ 106
External Clock Source.............................................. 107
Frequency vs. Resolution......................................... 106
Interrupts .................................................................. 106
Max Resolution/Frequency for External Clock
Input.......................................................................... 107
Output....................................................................... 105
1998 Microchip Technology Inc.
DS30289A-page 315
PIC17C7XX
Periods......................................................................106
PWM1 .......................................................100, 101, 303, 304
PWM1ON..................................................................100, 105
PWM2 .......................................................100, 101, 303, 304
PWM2ON..................................................................100, 105
PWM3ON..................................................................101, 304
PWRT..................................................................................22
R
PORTB ....................................................................... 46
PORTC....................................................................... 46
PORTD....................................................................... 46
PORTE ....................................................................... 46
PORTF ....................................................................... 47
PORTG....................................................................... 47
PR1............................................................................. 47
PR2............................................................................. 47
PR3H/CA1H ............................................................... 47
PR3L/CA1L................................................................. 47
PRODH....................................................................... 48
PRODL ....................................................................... 48
PW1DCH.................................................................... 47
PW1DCL..................................................................... 47
PW2/DCL.................................................................... 47
PW2DCH.................................................................... 47
PW3DCH.................................................................... 48
PW3DCL..................................................................... 48
RCREG1..................................................................... 46
RCREG2..................................................................... 47
RCSTA1 ..................................................................... 46
RCSTA2 ..................................................................... 47
SPBRG1..................................................................... 46
SPBRG2..................................................................... 47
Special Function Table............................................... 46
SSPADD..................................................................... 48
SSPBUF ..................................................................... 48
SSPCON1 .................................................................. 48
SSPCON2 .................................................................. 48
SSPSTAT ........................................................... 48, 132
T0STA ............................................................ 46, 51, 95
TBLPTRH ................................................................... 46
TBLPTRL.................................................................... 46
TCON1 ................................................................. 47, 99
TCON2 ............................................................... 47, 100
TCON3 ............................................................... 48, 101
TMR0H ....................................................................... 46
TMR1.......................................................................... 47
TMR2.......................................................................... 47
TMR3H ....................................................................... 47
TMR3L........................................................................ 47
TXREG1 ..................................................................... 46
TXREG2 ..................................................................... 47
TXSTA1...................................................................... 46
TXSTA2...................................................................... 47
WREG .................................................................. 37, 46
R/W ...........................................................................132, 307
R/W bit ......................................................................143, 286
R/W bit ..............................................................................143
RA1/T0CKI pin ....................................................................95
RBIE....................................................................................33
RBIF....................................................................................35
RBPU ..................................................................................72
RC Oscillator.......................................................................18
RC Oscillator Frequencies ................................................267
RC1IE..................................................................................33
RC1IF..........................................................................35, 298
RC2IE..........................................................................34, 297
RC2IF..........................................................................36, 299
RCE,Receive Enable bit, RCE..................................134, 309
RCREG .....................................................123, 124, 128, 129
RCREG1 .......................................................................25, 46
RCREG2 .......................................................................25, 47
RCSTA..............................................................124, 128, 130
RCSTA1........................................................................25, 46
RCSTA2........................................................................25, 47
Read/Write bit, R/W ..................................................132, 307
Reading 16-bit Value...........................................................97
Receive Overflow Indicator bit, SSPOV....................133, 308
Receive Status and Control Register................................115
Register File Map........................................................45, 291
Registers
ADCON0.....................................................................47
ADCON1.....................................................................47
ADRESH.....................................................................47
ADRESL......................................................................47
ALUSTA..........................................................37, 46, 49
BRG ..........................................................................118
BSR.......................................................................37, 46
CA2H ..........................................................................47
CA2L...........................................................................47
CA3H ..........................................................................48
CA3L...........................................................................48
CA4H ..........................................................................48
CA4L...........................................................................48
CPUSTA ...............................................................46, 50
DDRB..........................................................................46
DDRC..........................................................................46
DDRD..........................................................................46
DDRE..........................................................................46
DDRF..........................................................................47
DDRG .........................................................................47
FSR0.....................................................................46, 53
FSR1.....................................................................46, 53
INDF0....................................................................46, 53
INDF1....................................................................46, 53
INSTA .........................................................................46
INTSTA .......................................................................32
PCL.............................................................................46
PCLATH......................................................................46
PIE1 ......................................................................33, 46
PIE2 ......................................................................34, 47
PIR1......................................................................35, 46
PIR2......................................................................36, 47
PORTA........................................................................46
Regsters
TMR0L........................................................................ 46
Reset
Section........................................................................ 21
Status Bits and Their Significance.............................. 23
Time-Out in Various Situations................................... 23
Time-Out Sequence ................................................... 23
Restart Condition Enabled bit, RSE.......................... 134, 309
RETFIE............................................................................. 219
RETLW ............................................................................. 219
RETURN........................................................................... 220
RLCF ................................................................................ 220
RLNCF.............................................................................. 221
RRCF................................................................................ 221
RRNCF ............................................................................. 222
RSE .......................................................................... 134, 309
RX Pin Sampling Scheme ................................................ 123
S
S ............................................................................... 132, 307
SAE........................................................................... 134, 309
Sampling........................................................................... 123
DS30289A-page 316
1998 Microchip Technology Inc.
PIC17C7XX
Saving STATUS and WREG in RAM.................................. 40
SCK................................................................................... 135
SCL................................................................................... 142
SDA................................................................................... 142
SDI.................................................................................... 135
SDO .................................................................................. 135
Serial Clock, SCK ............................................................. 135
Serial Clock, SCL.............................................................. 142
Serial Data Address, SDA................................................. 142
Serial Data In, SDI ............................................................ 135
Serial Data Out, SDO........................................................ 135
SETF................................................................................. 222
SFR................................................................................... 196
SFR (Special Function Registers)....................................... 41
SFR As Source/Destination .............................................. 196
Signed Math.......................................................................... 9
Slave Select Synchronization ........................................... 138
Slave Select, SS ............................................................... 135
SLEEP ...................................................................... 192, 223
SMP .......................................................................... 132, 307
Software Simulator (MPSIM) ............................................ 233
SPBRG ............................................................. 124, 128, 130
SPBRG1 ....................................................................... 25, 46
SPBRG2 ....................................................................... 25, 47
SPE........................................................................... 134, 309
Special Features of the CPU ............................................ 189
Special Function Registers ................................... 41, 46, 196
Summary..................................................................... 46
Special Function Registers, File Map ......................... 45, 291
SPI
SSPCON2 .................................................................. 48, 134
SSPEN ..................................................................... 133, 308
SSPIE......................................................................... 34, 297
SSPIF ................................................................. 36, 143, 299
SSPM3:SSPM0 ........................................................ 133, 308
SSPOV ..................................................... 133, 142, 160, 308
SSPSTAT ........................................................... 48, 132, 142
Stack
Operation.................................................................... 52
Pointer ........................................................................ 52
Stack........................................................................... 41
Start bit (S) ............................................................... 132, 307
Start Condition Enabled bit, SAE.............................. 134, 309
STKAV.......................................................................... 50, 52
Stop bit (P)................................................................ 132, 307
Stop Condition Enable bit......................................... 134, 309
SUBLW............................................................................. 223
SUBWF............................................................................. 224
SUBWFB .......................................................................... 224
SWAPF............................................................................. 225
Synchronous Master Mode............................................... 125
Synchronous Master Reception ....................................... 127
Synchronous Master Transmission .................................. 125
Synchronous Serial Port................................................... 131
Synchronous Serial Port Enable bit, SSPEN............ 133, 308
Synchronous Serial Port Interrupt .............................. 36, 299
Synchronous Serial Port Interrupt Enable, SSPIE...... 34, 297
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 ........................................................ 133, 308
Synchronous Slave Mode................................................. 129
T
Master Mode............................................................. 137
Serial Clock............................................................... 135
Serial Data In ............................................................ 135
Serial Data Out ......................................................... 135
Serial Peripheral Interface (SPI) ............................... 131
Slave Select.............................................................. 135
SPI clock................................................................... 137
SPI Mode .................................................................. 135
SPI Clock Edge Select, CKE .................................... 132, 307
SPI Data Input Sample Phase Select, SMP ............. 132, 307
SPI Master/Slave Connection........................................... 136
SPI Module
T0CKI ................................................................................. 37
T0CKI Pin ........................................................................... 38
T0CKIE............................................................................... 32
T0CKIF ............................................................................... 32
T0CS ............................................................................ 51, 95
T0IE.................................................................................... 32
T0IF .................................................................................... 32
T0SE............................................................................. 51, 95
T0STA .......................................................................... 46, 51
T16 ..................................................................................... 99
Table Latch......................................................................... 54
Table Pointer ...................................................................... 54
Table Read
Master/Slave Connection.......................................... 136
Slave Mode............................................................... 138
Slave Select Synchronization ................................... 138
Slave Synch Timnig .................................................. 138
SS ..................................................................................... 135
SSP................................................................................... 131
Block Diagram (SPI Mode) ....................................... 135
SPI Mode .................................................................. 135
SSPADD ........................................................... 142, 143
SSPBUF............................................................ 137, 142
SSPCON1................................................................. 133
SSPCON2................................................................. 134
SSPSR.............................................................. 137, 142
SSPSTAT.......................................................... 132, 142
Example...................................................................... 62
Table Reads Section .................................................. 62
TLRD .......................................................................... 62
Table Write
Code........................................................................... 60
Timing......................................................................... 60
To External Memory ................................................... 60
TABLRD ................................................................... 225, 226
TABLWT................................................................... 226, 227
TAD ................................................................................... 183
TBLATH.............................................................................. 54
TBLATL .............................................................................. 54
TBLPTRH ..................................................................... 46, 54
TBLPTRL...................................................................... 46, 54
TCLK12 ...................................................................... 99, 302
TCLK3 ........................................................................ 99, 302
TCON1 ......................................................................... 26, 47
TCON2 ............................................................................... 47
TCON2,TCON3 .................................................................. 26
TCON3 ....................................................................... 48, 101
Time-Out Sequence ........................................................... 23
Timer Resources ................................................................ 93
2
SSP I C
2
SSP I C Operation.................................................... 141
SSP Module
SPI Master Mode ...................................................... 137
SPI Master./Slave Connection.................................. 136
SPI Slave Mode ........................................................ 138
SSPCON1 Register .................................................. 141
SSP Overflow Detect bit, SSPOV..................................... 142
SSPADD ............................................................................. 48
SSPBUF...................................................................... 48, 142
SSPCON1........................................................... 48, 133, 141
1998 Microchip Technology Inc.
DS30289A-page 317
PIC17C7XX
Timer0.................................................................................95
Timer1
TMR0.................................................................... 96, 97
TMR0 Read/Write in Timer Mode............................... 98
TMR1, TMR2, and TMR3 in Timer Mode ................. 113
Wake-Up from SLEEP.............................................. 192
TLRD ................................................................................ 227
TLWT................................................................................ 228
TMR0
16-bit Mode...............................................................103
Clock Source Select....................................................99
On bit ................................................100, 101, 303, 304
Section................................................................99, 102
Timer2
16-bit Mode...............................................................103
Clock Source Select....................................................99
On bit ................................................100, 101, 303, 304
Section................................................................99, 102
Timer3
Clock Source Select....................................................99
On bit ................................................100, 101, 303, 304
Section................................................................99, 108
Timers
16-bit Read................................................................. 97
16-bit Write ................................................................. 97
Module........................................................................ 96
Operation.................................................................... 96
Overview..................................................................... 93
Prescaler Assignments............................................... 97
Read/Write Considerations......................................... 97
Read/Write in Timer Mode.......................................... 98
Timing................................................................... 96, 97
TMR0 Status/Control Register (T0STA) ............................. 51
TMR0H ............................................................................... 46
TMR0L................................................................................ 46
TMR1............................................................................ 26, 47
8-bit Mode................................................................. 102
External Clock Input ................................................. 102
Overview..................................................................... 93
Timer Mode .............................................................. 113
Two 8-bit Timer/Counter Mode................................. 102
Using with PWM ....................................................... 105
TMR1 Overflow Interrupt ............................................ 35, 298
TMR1CS............................................................................. 99
TMR1IE............................................................................... 33
TMR1IF....................................................................... 35, 298
TMR1ON........................................................................... 100
TMR2............................................................................ 26, 47
8-bit Mode................................................................. 102
External Clock Input ................................................. 102
In Timer Mode .......................................................... 113
Two 8-bit Timer/Counter Mode................................. 102
Using with PWM ....................................................... 105
TMR2 Overflow Interrupt ............................................ 35, 298
TMR2CS............................................................................. 99
TMR2IE............................................................................... 33
TMR2IF....................................................................... 35, 298
TMR2ON........................................................................... 100
TMR3
TCON3......................................................................101
Timing Diagrams
A/D Conversion.........................................................261
Acknowledge Sequence Timing................................163
Asynchronous Master Transmission.........................122
Asynchronous Reception..........................................124
Back to Back Asynchronous Master Transmission...122
Baud Rate Generator with Clock Arbitration.............151
BRG Reset Due to SDA Collision .............................170
Bus Collision
Start Condition Timing ......................................169
Bus Collision During a Restart Condition
(Case 1) ....................................................................171
Bus Collision During a Restart Condition
(Case2) .....................................................................171
Bus Collision During a Start Condition
(SCL = 0)...................................................................170
Bus Collision During a Stop Condition......................172
Bus Collision for Transmit and Acknowledge............168
External Parallel Resonant Crystal Oscillator
Circuit..........................................................................17
External Program Memory Access .............................43
2
I C Bus Data.............................................................257
2
I C Bus Start/Stop bits..............................................256
2
I C Master Mode First Start bit timing.......................152
2
I C Master Mode Reception timing...........................162
2
I C Master Mode Transmission timing......................159
Interrupt (INT, TMR0 Pins)..........................................38
Master Mode Transmit Clock Arbitration...................167
Oscillator Start-up Time ..............................................22
PIC17C752/756 Capture Timing...............................251
PIC17C752/756 CLKOUT and I/O............................248
PIC17C752/756 External Clock ................................247
PIC17C752/756 Memory Interface Read..................263
PIC17C752/756 Memory Interface Write..................262
PIC17C752/756 PWM Timing...................................251
PIC17C752/756 Reset, Watchdog Timer,
Oscillator Start-up Timer and Power-up Timer .........249
PIC17C752/756 Timer0 Clock ..................................250
PIC17C752/756 Timer1, Timer2 and Timer3
Clock.........................................................................250
PIC17C752/756 USART Module Synchronous
Example, Reading From........................................... 112
Example, Writing To ................................................. 112
External Clock Input ................................................. 112
In Timer Mode .......................................................... 113
One Capture and One Period Register Mode .......... 108
Overview..................................................................... 93
Reading/Writing........................................................ 112
TMR3 Interrupt Flag bit, TMR3IF................................ 35, 298
TMR3CS..................................................................... 99, 108
TMR3H ......................................................................... 26, 47
TMR3IE............................................................................... 33
TMR3IF....................................................................... 35, 108
TMR3L.......................................................................... 26, 47
TMR3ON................................................................... 100, 108
TO....................................................................... 50, 191, 192
Transmit Status and Control Register............................... 115
TSTFSZ ............................................................................ 228
Turning on 16-bit Timer .................................................... 103
TX1IE.................................................................................. 33
TX1IF.......................................................................... 35, 298
TX2IE.......................................................................... 34, 297
TX2IF.......................................................................... 36, 299
TXREG ..................................................... 121, 125, 129, 130
TXREG1 ....................................................................... 25, 46
Receive.....................................................................258
PIC17C752/756 USART Module Synchronous
Transmission.............................................................258
Repeat Start Condition..............................................154
Slave Synchronization ..............................................138
Stop Condition Receive or Transmit .........................165
Synchronous Reception............................................127
Synchronous Transmission.......................................126
Table Write..................................................................60
DS30289A-page 318
1998 Microchip Technology Inc.
PIC17C7XX
TXREG2........................................................................ 25, 47
TXSTA .............................................................. 124, 128, 130
TXSTA1 ........................................................................ 25, 46
TXSTA2 ........................................................................ 25, 47
U
UA............................................................................. 132, 307
Update Address, UA ................................................. 132, 307
Upward Compatibility............................................................ 5
USART
Asynchronous Master Transmission......................... 122
Asynchronous Mode ................................................. 121
Asynchronous Receive ............................................. 123
Asynchronous Transmitter........................................ 121
Baud Rate Generator................................................ 118
Synchronous Master Mode....................................... 125
Synchronous Master Reception................................ 127
Synchronous Master Transmission........................... 125
Synchronous Slave Mode......................................... 129
Synchronous Slave Transmit.................................... 129
USART1 Receive Interrupt ......................................... 35, 298
USART1 Transmit Interrupt ........................................ 35, 298
USART2 Receive Interrupt Enable, RC2IE................. 34, 297
USART2 Receive Interrupt Flag bit, RC2IF ................ 36, 299
USART2 Receive Interrupt Flag bit, TX2IF................. 36, 299
USART2 Transmit Interrupt Enable, TX2IE ................ 34, 297
V
VDD ........................................................................... 237, 239
W
Wake-up from SLEEP....................................................... 192
Wake-up from SLEEP Through Interrupt.......................... 192
Watchdog Timer................................................................ 191
Waveform for General Call Address Sequence................ 147
Waveforms
External Program Memory Access ............................. 43
WCOL ............................... 133, 152, 157, 160, 163, 165, 308
WCOL Status Flag............................................................ 152
WDT.................................................................................. 191
Clearing the WDT ..................................................... 191
Normal Timer ............................................................ 191
Period........................................................................ 191
Programming Considerations ................................... 191
WDTPS0........................................................................... 189
WDTPS1........................................................................... 189
WREG................................................................................. 46
Write Collision Detect bit, WCOL.............................. 133, 308
X
XORLW............................................................................. 229
XORWF............................................................................. 229
Z
Z.............................................................................. 9, 49, 292
Zero (Z)................................................................................. 9
1998 Microchip Technology Inc.
DS30289A-page 319
PIC17C7XX
NOTES:
DS30289A-page 320
1998 Microchip Technology Inc.
PIC17C7XX
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
980106
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
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available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. PICmicro, FlexROM, MPLAB and fuzzy-
LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
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All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
1998 Microchip Technology Inc.
DS30289A-page 321
PIC17C7XX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Literature Number:
DS30289A
Device:
PIC17C7XX
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
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DS30289A-page 322
1998 Microchip Technology Inc.
PIC17C7XX
PIC17C7XX Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Examples
PART NO. – XX X /XX XXX
Pattern:
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices
a)
b)
c)
PIC17C756 – 16L
Commercial Temp.,
PLCC package,
16 MHz,
Package:
CL
PT
L
= Windowed LCC
= TQFP
= PLCC
normal VDD limits
PIC17LC756–08/PT
Commercial Temp.,
TQFP package,
8MHz,
Temperature
Range:
Frequency
Range:
–
I
= 0˚C to +70˚C
= –40˚C to +85˚C
08
16
33
= 8 MHz
= 16 MHz
= 33 MHz
extended VDD limits
PIC17C756–33I/PT
Industrial Temp.,
TQFP package,
33 MHz,
Device:
PIC17C756
PIC17C756T
PIC17LC756
: Standard VDD range
: (Tape and Reel)
: Extended VDD range
normal VDD limits
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. The Microchip Website at www.microchip.com
2. Your local Microchip sales office (see following page)
3. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1998 Microchip Technology Inc.
DS30289A-page 323
PIC17C7XX
NOTES:
DS30289A-page 324
1998 Microchip Technology Inc.
PIC17C7XX
NOTES:
1998 Microchip Technology Inc.
DS30289A-page 325
PIC17C7XX
NOTES:
DS30289A-page 326
1998 Microchip Technology Inc.
PIC17C7XX
NOTES:
1998 Microchip Technology Inc.
DS30289A-page 327
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
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Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
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