PIC17C756A-33E/L [MICROCHIP]
8-BIT, OTPROM, 33 MHz, RISC MICROCONTROLLER, PQCC68, PLASTIC, MO-047, LCC-68;
| 型号： | PIC17C756A-33E/L |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, OTPROM, 33 MHz, RISC MICROCONTROLLER, PQCC68, PLASTIC, MO-047, LCC-68 可编程只读存储器 时钟 外围集成电路 |
| 文件： | 总306页 (文件大小：4388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC17C7XX
High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D
Microcontroller Core Features:
Pin Diagrams
• Only 58 single word instructions to learn
84 PLCC
• All single cycle instructions (121 ns), except for
program branches and table reads/writes which
are two-cycle
1110 9
8 7 6 5 4 3 2 1 84838281807978777675
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RH2
RH3
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
RJ5
• Operating speed:
RJ4
RA0/INT
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
- DC - 33 MHz clock input
- DC - 121 ns instruction cycle
• 8 x 8 Single-Cycle Hardware Multiplier
• Interrupt capability
MCLR/VPP
TEST
NC
VSS
VDD
NC
PIC17C76X
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
• 16 level deep hardware stack
• Direct, indirect, and relative addressing modes
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
• Internal/external program memory execution,
capable of addressing 64 K x 16 program memory
space
RJ3
RJ2
333435363738394041424344454647484950515253
Memory
Device
Program (x16)
Data (x8)
PIC17C752
PIC17C756A
PIC17C762
PIC17C766
8 K
16 K
8 K
678
902
678
902
Special Microcontroller Features:
16 K
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
Peripheral Features:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Up to 66 I/O pins with individual direction control
• 10-bit, multi-channel Analog-to-Digital converter
• High current sink/source for direct LED drive
• Four capture input pins
• Brown-out Reset
• Code protection
• Power saving SLEEP mode
• Selectable oscillator options
- Captures are 16-bit, max resolution 121 ns
• Three PWM outputs (resolution is 1 to 10-bits)
CMOS Technology:
• TMR0: 16-bit timer/counter with
8-bit programmable prescaler
• Low power, high speed CMOS EPROM
technology
• TMR1: 8-bit timer/counter
• TMR2: 8-bit timer/counter
• TMR3: 16-bit timer/counter
• Fully static design
• Wide operating voltage range (3.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low power consumption
• Two Universal Synchronous Asynchronous
Receiver Transmitters (USART/SCI) with
independent baud rate generators
- < 5 mA @ 5V, 4 MHz
• Synchronous Serial Port (SSP) with SPI™ and
I2C™ modes (including I2C Master mode)
- 100 µA typical @ 4.5V, 32 kHz
- < 1 µA typical standby current @ 5V
1998-2013 Microchip Technology Inc.
DS30289C-page 1
PIC17C7XX
Pin Diagrams cont.’d
68-Pin PLCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
RA0/INT
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIC17C75X
NC
VSS
VDD
NC
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
64-Pin TQFP
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RA0/INT
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
2
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
3
4
5
6
7
PIC17C75X
8
9
VSS
OSC2/CLKOUT
OSC1/CLKIN
VDD
10
11
12
13
14
15
16
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
DS30289C-page 2
1998-2013 Microchip Technology Inc.
PIC17C7XX
Pin Diagrams cont.’d
84-pin PLCC
11 10 9 8
7 6 5 4 3 2 1 84838281807978777675
RH2
RH3
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RJ5
RJ4
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
PIC17C76X
NC
VSS
VDD
NC
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
55
54
RJ3
RJ2
333435363738394041424344
47 50 5253
4546 4849 51
80-Pin TQFP
807978777675 7473 72717069 68676665 64636261
1
2
60
RJ5
RJ4
RA0/INT
RH2
RH3
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
VSS
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RJ3
PIC17C76X
VSS
VDD
RF7/AN11
RF6/AN10
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
RH4/AN12
RH5/AN13
RJ2
212223242526272829303132
3334353637383940
1998-2013 Microchip Technology Inc.
DS30289C-page 3
PIC17C7XX
Table of Contents
1.0
Overview........................................................................................................................................................7
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
Device Varieties.............................................................................................................................................9
Architectural Overview.................................................................................................................................11
On-chip Oscillator Circuit .............................................................................................................................17
Reset............................................................................................................................................................23
Interrupts......................................................................................................................................................33
Memory Organization...................................................................................................................................43
Table Reads and Table Writes ....................................................................................................................59
Hardware Multiplier......................................................................................................................................67
I/O Ports.......................................................................................................................................................71
Overview of Timer Resources......................................................................................................................95
Timer0..........................................................................................................................................................97
Timer1, Timer2, Timer3, PWMs and Captures ..........................................................................................101
Universal Synchronous Asynchronous Receiver Transmitter (USART) Modules......................................117
Master Synchronous Serial Port (MSSP) Module......................................................................................133
Analog-to-Digital Converter (A/D) Module .................................................................................................179
Special Features of the CPU .....................................................................................................................191
Instruction Set Summary............................................................................................................................197
Development Support ................................................................................................................................233
PIC17C7XX Electrical Characteristics .......................................................................................................239
PIC17C7XX DC and AC Characteristics....................................................................................................267
Packaging Information ...............................................................................................................................281
Appendix A: Modifications .......................................................................................................................................287
Appendix B: Compatibility........................................................................................................................................287
Appendix C: What’s New .........................................................................................................................................288
Appendix D: What’s Changed..................................................................................................................................288
Index .......................................................................................................................................................................... 289
On-Line Support..........................................................................................................................................................299
Reader Response .......................................................................................................................................................300
Product Identification System......................................................................................................................................301
DS30289C-page 4
1998-2013 Microchip Technology Inc.
PIC17C7XX
TO OUR VALUED CUSTOMERS
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-
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1998-2013 Microchip Technology Inc.
DS30289C-page 5
PIC17C7XX
NOTES:
DS30289C-page 6
1998-2013 Microchip Technology Inc.
PIC17C7XX
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software mal-
function.
1.0
OVERVIEW
This data sheet covers the PIC17C7XX group of the
PIC17CXXX family of microcontrollers. The following
devices are discussed in this data sheet:
There are four configuration options for the device
operational mode:
• PIC17C752
• PIC17C756A
• PIC17C762
• PIC17C766
• Microprocessor
• Microcontroller
• Extended microcontroller
• Protected microcontroller
The PIC17C7XX devices are 68/84-pin, EPROM
based members of the versatile PIC17CXXX family of
low cost, high performance, CMOS, fully static, 8-bit
microcontrollers.
The microprocessor and extended microcontroller
modes allow up to 64K-words of external program
memory.
The device also has Brown-out Reset circuitry. This
allows a device RESET to occur if the device VDD falls
below the Brown-out voltage trip point (BVDD). The chip
will remain in Brown-out Reset until VDD rises above
BVDD.
All PIC® microcontrollers employ an advanced RISC
architecture. The PIC17CXXX has enhanced core fea-
tures, 16-level deep stack, and multiple internal and
external interrupt sources. The separate instruction
and data buses of the Harvard architecture allow a 16-
bit wide instruction word with a separate 8-bit wide data
path. The two stage instruction pipeline allows all
instructions to execute in a single cycle, except for pro-
gram branches (which require two cycles). A total of 58
instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance. For mathematical intensive applications,
all devices have a single cycle 8 x 8 Hardware
Multiplier.
A UV erasable, CERQUAD packaged version (compat-
ible with PLCC), is ideal for code development, while
the cost-effective One-Time-Programmable (OTP) ver-
sion is suitable for production in any volume.
The PIC17C7XX fits perfectly in applications that
require extremely fast execution of complex software
programs. These include applications ranging from
precise motor control and industrial process control to
automotive, instrumentation, and telecom applications.
The EPROM technology makes customization of appli-
cation programs (with unique security codes, combina-
tions, model numbers, parameter storage, etc.) fast
and convenient. Small footprint package options
(including die sales) make the PIC17C7XX ideal for
applications with space limitations that require high
performance.
PIC17CXXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
PIC17C7XX devices have up to 902 bytes of RAM and
66 I/O pins. In addition, the PIC17C7XX adds several
peripheral features, useful in many high performance
applications, including:
High speed execution, powerful peripheral features,
flexible I/O, and low power consumption all at low cost
make the PIC17C7XX ideal for a wide range of embed-
ded control applications.
• Four timer/counters
• Four capture inputs
• Three PWM outputs
• Two independent Universal Synchronous Asyn-
chronous Receiver Transmitters (USARTs)
1.1
Family and Upward Compatibility
The PIC17CXXX family of microcontrollers have archi-
tectural enhancements over the PIC16C5X and
PIC16CXX families. These enhancements allow the
device to be more efficient in software and hardware
requirements. Refer to Appendix A for a detailed list of
enhancements and modifications. Code written for
PIC16C5X or PIC16CXX can be easily ported to
PIC17CXXX devices (Appendix B).
• An A/D converter (multi-channel, 10-bit resolution)
• A Synchronous Serial Port
(SPI and I2C w/ Master mode)
These special features reduce external components,
thus reducing cost, enhancing system reliability and
reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low cost solution, the LF oscil-
lator is for low frequency crystals and minimizes power
consumption, XT is a standard crystal and the EC is for
external clock input.
1.2
Development Support
The PIC17CXXX family is supported by a full featured
macro assembler, a software simulator, an in-circuit
emulator, a universal programmer, a “C” compiler and
fuzzy logic support tools. For additional information,
see Section 19.0.
The SLEEP (power-down) mode offers additional
power saving. Wake-up from SLEEP can occur through
several external and internal interrupts and device
RESETS.
1998-2013 Microchip Technology Inc.
DS30289C-page 7
PIC17C7XX
TABLE 1-1:
PIC17CXXX FAMILY OF DEVICES
Features
PIC17C42A
PIC17C43
PIC17C44
PIC17C752 PIC17C756A PIC17C762 PIC17C766
Maximum Frequency
of Operation
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
Operating Voltage Range
2.5 - 6.0V
2 K
2.5 - 6.0V
4 K
2.5 - 6.0V
8 K
3.0 - 5.5V
8 K
3.0 - 5.5V
16 K
—
3.0 - 5.5V
8 K
3.0 - 5.5V
16 K
—
Program
(EPROM)
(ROM)
Memory ( x16)
—
—
—
—
—
Data Memory (bytes)
232
454
454
678
902
678
902
Hardware Multiplier (8 x 8)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Timer0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(16-bit + 8-bit postscaler)
Timer1 (8-bit)
Yes
Yes
Yes
2
Yes
Yes
Yes
2
Yes
Yes
Yes
2
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Timer2 (8-bit)
Timer3 (16-bit)
Capture inputs (16-bit)
PWM outputs (up to 10-bit)
USART/SCI
2
2
2
3
3
3
3
1
1
1
2
2
2
2
A/D channels (10-bit)
—
—
—
—
—
—
12
Yes
12
Yes
16
Yes
16
Yes
2
SSP (SPI/I C w/Master
mode)
Power-on Reset
Watchdog Timer
External Interrupts
Interrupt Sources
Code Protect
Yes
Yes
Yes
11
Yes
Yes
Yes
11
Yes
Yes
Yes
11
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
—
Yes
—
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
In-Circuit Serial
Programming
—
—
—
I/O Pins
33
33
33
50
50
66
66
I/O High
Current Capability
Source
Sink
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
(1)
(1)
(1)
(1)
(1)
(1)
(1)
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
Package Types
40-pin DIP
40-pin DIP
40-pin DIP 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP
44-pin PLCC 44-pin PLCC 44-pin PLCC 68-pin PLCC 68-pin PLCC 84-pin PLCC 84-pin PLCC
44-pin MQFP
44-pin TQFP
44-pin
MQFP
44-pin
MQFP
44-pin TQFP 44-pin TQFP
Note 1: Pins RA2 and RA3 can sink up to 60 mA.
DS30289C-page 8
1998-2013 Microchip Technology Inc.
PIC17C7XX
2.3
Quick-Turnaround-Production
(QTP) Devices
2.0
DEVICE VARIETIES
Each device has a variety of frequency ranges and
packaging options. Depending on application and pro-
duction requirements, the proper device option can be
selected using the information in the PIC17C7XX Prod-
uct Selection System section at the end of this data
sheet. When placing orders, please use the
“PIC17C7XX Product Identification System” at the
back of this data sheet to specify the correct part num-
ber. When discussing the functionality of the device,
memory technology and voltage range does not matter.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
There are two memory type options. These are speci-
fied in the middle characters of the part number.
2.4
Serialized Quick-Turnaround
1. C, as in PIC17C756A. These devices have
sm
Production (SQTP )Devices
EPROM type memory.
Microchip offers a unique programming service, where
a few user defined locations in each device are pro-
grammed with different serial numbers. The serial num-
bers may be random, pseudo-random or sequential.
2. CR, as in PIC17CR756A. These devices have
ROM type memory.
All these devices operate over the standard voltage
range. Devices are also offered which operate over an
extended voltage range (and reduced frequency
range). Table 2-1 shows all possible memory types and
voltage range designators for a particular device.
These designators are in bold typeface.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
2.5
Read Only Memory (ROM) Devices
TABLE 2-1:
Memory Type
DEVICE MEMORY VARIETIES
Voltage Range
Microchip offers masked ROM versions of several of
the highest volume parts, thus giving customers a low
cost option for high volume, mature products.
Standard
Extended
ROM devices do not allow serialization information in
the program memory space.
EPROM
ROM
PIC17CXXX
PIC17LCXXX
For information on submitting ROM code, please con-
tact your regional sales office.
PIC17CRXXX
PIC17LCRXXX
Note: Not all memory technologies are available
for a particular device.
Note: Presently, NO ROM versions of the
PIC17C7XX devices are available.
2.1
UV Erasable Devices
The UV erasable version, offered in CERQUAD pack-
age, is optimal for prototype development and pilot
programs.
The UV erasable version can be erased and repro-
grammed to any of the configuration modes. Third
party programmers also are available; refer to the Third
Party Guide for a list of sources.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages, permit
the user to program them once. In addition to the program
memory, the configuration bits must be programmed.
1998-2013 Microchip Technology Inc.
DS30289C-page 9
PIC17C7XX
NOTES:
DS30289C-page 10
1998-2013 Microchip Technology Inc.
PIC17C7XX
The WREG register is an 8-bit working register used for
ALU operations.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC17CXXX can be attrib-
uted to a number of architectural features, commonly
found in RISC microprocessors. To begin with, the
PIC17CXXX uses a modified Harvard architecture.
This architecture has the program and data accessed
from separate memories. So, the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions to
be sized differently than the 8-bit wide data word.
PIC17CXXX opcodes are 16-bits wide, enabling single
word instructions. The full 16-bit wide program memory
bus fetches a 16-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions. Consequently, all instructions execute in a single
cycle (121 ns @ 33 MHz), except for program branches
and two special instructions that transfer data between
program and data memory.
All PIC17CXXX devices have an 8 x 8 hardware multi-
plier. This multiplier generates a 16-bit result in a single
cycle.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), Zero
(Z) and Overflow (OV) bits in the ALUSTA register. The
C and DC bits operate as a borrow and digit borrow out
bit, respectively, in subtraction. See the SUBLW and
SUBWFinstructions for examples.
Signed arithmetic is comprised of a magnitude and a
sign bit. The overflow bit indicates if the magnitude
overflows and causes the sign bit to change state. That
is, if the result of 8-bit signed operations is greater than
127 (7Fh), or less than -128 (80h).
Signed math can have greater than 7-bit values (mag-
nitude), if more than one byte is used. The overflow bit
only operates on bit6 (MSb of magnitude) and bit7 (sign
bit) of each byte value in the ALU. That is, the overflow
bit is not useful if trying to implement signed math
where the magnitude, for example, is 11-bits.
The PIC17CXXX can address up to 64K x 16 of pro-
gram memory space.
The PIC17C752 and PIC17C762 integrate 8K x 16 of
EPROM program memory on-chip.
The PIC17C756A and PIC17C766 integrate 16K x 16
EPROM program memory on-chip.
If the signed math values are greater than 7-bits (such
as 15-, 24-, or 31-bit), the algorithm must ensure that
the low order bytes of the signed value ignore the over-
flow status bit.
A simplified block diagram is shown in Figure 3-1. The
descriptions of the device pins are listed in Table 3-1.
Program execution can be internal only (Microcontrol-
ler or Protected Microcontroller mode), external only
(Microprocessor mode), or both (Extended Microcon-
troller mode). Extended Microcontroller mode does not
allow code protection.
Example 3-1 shows two cases of doing signed arithme-
tic. The Carry (C) bit and the Overflow (OV) bit are the
most important status bits for signed math operations.
EXAMPLE 3-1:
8-BIT MATH ADDITION
The PIC17CXXX can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the Program Counter (PC) and Working
Register (WREG), are mapped in data memory. The
PIC17CXXX has an orthogonal (symmetrical) instruction
set that makes it possible to carry out any operation on
any register using any addressing mode. This symmetri-
cal nature and lack of ‘special optimal situations’ make
programming with the PIC17CXXX simple, yet efficient.
In addition, the learning curve is reduced significantly.
Hex Value
Signed Values
Unsigned Values
FFh
-1
1
255
1
+
=
01h
00h
+
=
+
0 (FEh)
= 256 00h
C bit = 1
C bit = 1
C bit = 1
OV bit = 0
OV bit = 0
OV bit = 0
DC bit = 1
Z bit = 1
DC bit = 1
Z bit = 1
DC bit = 1
Z bit = 1
One of the PIC17CXXX family architectural enhance-
ments from the PIC16CXX family, allows two file regis-
ters to be used in some two operand instructions. This
allows data to be moved directly between two registers
without going through the WREG register, thus increas-
ing performance and decreasing program memory
usage.
Hex Value
Signed Values
Unsigned Values
7Fh
127
127
+
=
01h
80h
+
=
1
+
1
128 00h
= 128
The PIC17CXXX devices contain an 8-bit ALU and
working register. The ALU is a general purpose arith-
metic unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
C bit = 0
OV bit = 1
C bit = 0
OV bit = 1
C bit = 0
OV bit = 1
DC bit = 1
Z bit = 0
DC bit = 1
Z bit = 0
DC bit = 1
Z bit = 0
1998-2013 Microchip Technology Inc.
DS30289C-page 11
PIC17C7XX
FIGURE 3-1:
PIC17C752/756A BLOCK DIAGRAM
PORTA
Clock
Generator
OSC1,
OSC2
Q1, Q2,
Q3, Q4
RA0/INT
RA1/T0CKI
IR<16>
Power-on
Reset
BITOP
WREG<8>
RA2/SS/SCL
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
Brown-out
Reset
VDD, VSS
Chip_reset
& Other
Control
Watchdog
Timer
MCLR, VPP
Test
PORTB
8 x 8 mult
ALU
Signals
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
Test Mode
Select
PRODH PRODL
Shifter
IR Latch <16>
8
8
RB7/SDO
8
BSR <7:4>
IR <7:0>
PORTC
16
F1
F9
Decode
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
12
Read/Write
Decode
for
Instruction
Decode
RAM
Address
Buffer
Data RAM
17C756A
902 x 8
Registers
ROM Latch <16>
Mapped
in Data
Space
8
Control Outputs
17C752
678 x 8
PORTD
RD0/AD8
RD1/AD9
AD<15:0>
PORTC,
PORTD
Data Latch
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
Literal
BSR
Table
Latch <16>
Data Latch
Program
Memory
(EPROM)
17C756A
16K x 16
PORTE
17C752
8K x 16
RE0/ALE
RE1/OE
RE2/WR
ALE,
WR,
OE,
Address
Latch
Table Pointer<16>
Stack
PCLATH<8>
RE3/CAP4
PORTE
16
16
PORTF
PCH
PCL
16
16 x 16
16
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
Data Bus<8>
10-bit
A/D
Timer0
Timer2
Timer3
PWM1
PWM2
PWM3
Capture2
SSP
USART1
USART2
PORTG
RG0/AN3
RG1/AN2
RG2/AN1/VREF-
RG3/AN0/VREF+
RG4/CAP3
Interrupt
Module
Timer1
Capture1 Capture3 Capture4
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
DS30289C-page 12
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 3-2:
PIC17C762/766 BLOCK DIAGRAM
PORTA
Clock
Generator
RA0/INT
RA1/T0CKI
RA2/SS/SCL
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
Q1, Q2,
Q3, Q4
OSC1,
OSC2
Power-on
Reset
IR<16>
BITOP
WREG<8>
VDD, VSS
Watchdog
Timer
Chip_reset
& Other
Control
Test Mode
Select
PORTB
MCLR, VPP
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
Signals
Brown-out
Reset
8 x 8 mult
ALU
Test
AVDD, AVSS
PRODH PRODL
Shifter
IR Latch <16>
RB7/SDO
PORTC
8
8
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
BSR <7:4>
IR <7:0>
8
16
FSR0
FSR1
Decode
12
Read/Write
Decode
for
Instruction
Decode
RAM
Address
Buffer
Registers
ROM Latch <16>
PORTD
Mapped
in Data
Space
8
RD0/AD8
RD1/AD9
Data RAM
Control Outputs
17C766
902 x 8
and
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
17C762
678 x 8
Data Latch
AD<15:0>
PORTC,
PORTD
PORTE
PORTF
Literal
BSR
Table
Latch <16>
Data Latch
RE0/ALE
RE1/OE
RE2/WR
Program
Memory
(EPROM)
17C766
16K x 16,
and
17C762
8K x 16
RE3/CAP4
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
ALE,
WR,
OE,
Address
Latch
Table Pointer<16>
Stack
PCLATH<8>
PORTE
16
PORTG
RG0/AN3
RG1/AN2
RG2/AN1/VREF-
RG3/AN0/VREF+
RG4/CAP3
RG5/PWM3
RG6/RX2/DT2
RG7/TX2/CK2
16
PCH
PCL
16
16 x 16
16
Data Bus<8>
PORTJ
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
PORTH
Timer0
Timer2
Timer3
PWM1
PWM2
PWM3
USART1
USART2
RH0
RH1
RH2
RH3
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
Timer1
Capture1
10-bit
A/D
Interrupt
Module
SSP
Capture2 Capture3 Capture4
1998-2013 Microchip Technology Inc.
DS30289C-page 13
PIC17C7XX
TABLE 3-1:
PINOUT DESCRIPTIONS
PIC17C75X
PIC17C76X
Name
Description
DIP
No.
PLCC TQFP PLCC
QFP I/O/P Buffer
No.
No.
No.
No.
Type
Type
OSC1/CLKIN
47
50
39
62
49
I
ST
Oscillator input in Crystal/Resonator or RC Oscillator
mode. External clock input in External Clock mode.
OSC2/CLKOUT
48
51
40
63
50
O
—
Oscillator output. Connects to crystal or resonator in
Crystal Oscillator mode. In RC Oscillator or External
Clock modes, OSC2 pin outputs CLKOUT which has
one fourth the frequency (FOSC/4) of OSC1 and
denotes the instruction cycle rate.
MCLR/VPP
15
16
7
20
9
I/P
ST
Master clear (RESET) input or Programming Voltage
(VPP) input. This is the active low RESET input to the
device.
PORTA pins have individual differentiations that are
listed in the following descriptions:
RA0/INT
56
41
60
44
48
33
72
56
58
43
I
I
ST
ST
RA0 can also be selected as an external inter-
rupt input. Interrupt can be configured to be on
positive or negative edge. Input only pin.
RA1/T0CKI
RA1 can also be selected as an external inter-
rupt input and the interrupt can be configured to
be on positive or negative edge. RA1 can also
be selected to be the clock input to the Timer0
timer/counter. Input only pin.
(2)
RA2/SS/SCL
RA3/SDI/SDA
RA4/RX1/DT1
42
43
40
45
46
43
34
35
32
57
58
51
44
45
38
I/O
ST
ST
ST
RA2 can also be used as the slave select input
for the SPI or the clock input for the I C bus.
High voltage, high current, open drain port pin.
2
(2)
I/O
RA3 can also be used as the data input for the
2
SPI or the data for the I C bus.
High voltage, high current, open drain port pin.
(1)
I/O
RA4 can also be selected as the USART1 (SCI)
Asynchronous Receive or USART1 (SCI)
Synchronous Data.
Output available from USART only.
(1)
RA5/TX1/CK1
39
42
31
50
37
I/O
ST
RA5 can also be selected as the USART1 (SCI)
Asynchronous Transmit or USART1 (SCI)
Synchronous Clock.
Output available from USART only.
PORTB is a bi-directional I/O Port with software
configurable weak pull-ups.
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
55
54
50
53
52
59
58
54
57
56
47
46
42
45
44
71
70
66
69
68
57
56
52
55
54
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RB0 can also be the Capture1 input pin.
RB1 can also be the Capture2 input pin.
RB2 can also be the PWM1 output pin.
RB3 can also be the PWM2 output pin.
RB4 can also be the external clock input to
Timer1 and Timer2.
RB5/TCLK3
RB6/SCK
RB7/SDO
51
44
45
55
47
48
43
36
37
67
59
60
53
46
47
I/O
I/O
I/O
ST
ST
ST
RB5 can also be the external clock input to
Timer3.
RB6 can also be used as the master/slave clock
for the SPI.
RB7 can also be used as the data output for the
SPI.
Legend: I = Input only; O = Output only;
P = Power; — = Not Used;
I/O = Input/Output;
TTL = TTL input;
ST = Schmitt Trigger input
Note 1: The output is only available by the peripheral operation.
2: Open drain input/output pin. Pin forced to input upon any device RESET.
DS30289C-page 14
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 3-1:
PINOUT DESCRIPTIONS (CONTINUED)
PIC17C75X
PIC17C76X
Name
Description
DIP
No.
PLCC TQFP PLCC
QFP I/O/P Buffer
No.
No.
No.
No.
Type
Type
PORTC is a bi-directional I/O Port.
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
2
3
58
55
54
53
52
51
50
49
3
72
69
68
67
66
65
64
63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
This is also the least significant byte (LSB) of
the 16-bit wide system bus in Microprocessor
mode or Extended Microcontroller mode. In
multiplexed system bus configuration, these
pins are address output as well as data input or
output.
63
62
61
60
58
58
57
67
66
65
64
63
62
61
83
82
81
80
79
78
77
PORTD is a bi-directional I/O Port.
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
10
9
11
10
9
2
15
14
9
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
This is also the most significant byte (MSB) of
the 16-bit system bus in Microprocessor mode
or Extended Microcontroller mode. In multi-
plexed system bus configuration, these pins are
address output as well as data input or output.
1
3
8
64
63
62
61
60
59
78
77
76
75
74
73
7
8
8
6
7
7
5
6
6
4
5
5
3
4
4
PORTE is a bi-directional I/O Port.
RE0/ALE
11
12
3
16
5
I/O
TTL
In Microprocessor mode or Extended Microcon-
troller mode, RE0 is the Address Latch Enable
(ALE) output. Address should be latched on the
falling edge of ALE output.
RE1/OE
12
13
14
13
14
15
4
5
6
17
18
19
6
7
8
I/O
I/O
I/O
TTL
TTL
ST
In Microprocessor or Extended Microcontroller
mode, RE1 is the Output Enable (OE) control
output (active low).
RE2/WR
RE3/CAP4
In Microprocessor or Extended Microcontroller
mode, RE2 is the Write Enable (WR) control
output (active low).
RE3 can also be the Capture4 input pin.
PORTF is a bi-directional I/O Port.
RF0 can also be analog input 4.
RF1 can also be analog input 5.
RF2 can also be analog input 6.
RF3 can also be analog input 7.
RF4 can also be analog input 8.
RF5 can also be analog input 9.
RF6 can also be analog input 10.
RF7 can also be analog input 11.
RF0/AN4
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
26
25
24
23
22
21
20
19
28
27
26
25
24
23
22
21
18
17
16
15
14
13
12
11
36
35
30
29
28
27
26
25
24
23
18
17
16
15
14
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Legend: I = Input only; O = Output only;
P = Power; — = Not Used;
I/O = Input/Output;
TTL = TTL input;
ST = Schmitt Trigger input
Note 1: The output is only available by the peripheral operation.
2: Open drain input/output pin. Pin forced to input upon any device RESET.
1998-2013 Microchip Technology Inc.
DS30289C-page 15
PIC17C7XX
TABLE 3-1:
PINOUT DESCRIPTIONS (CONTINUED)
PIC17C75X
PIC17C76X
Name
Description
DIP
No.
PLCC TQFP PLCC
QFP I/O/P Buffer
No.
No.
No.
No.
Type
Type
PORTG is a bi-directional I/O Port.
RG0 can also be analog input 3.
RG1 can also be analog input 2.
RG0/AN3
32
31
30
34
33
32
24
23
22
42
41
40
30
29
28
I/O
I/O
I/O
ST
ST
ST
RG1/AN2
RG2/AN1/VREF-
RG2 can also be analog input 1, or
the ground reference voltage.
RG3/AN0/VREF+
29
31
21
39
27
I/O
ST
RG3 can also be analog input 0, or
the positive reference voltage.
RG4/CAP3
35
36
38
38
39
41
27
28
30
46
47
49
33
34
36
I/O
I/O
I/O
ST
ST
ST
RG4 can also be the Capture3 input pin.
RG5 can also be the PWM3 output pin.
RG5/PWM3
RG6/RX2/DT2
RG6 can also be selected as the USART2 (SCI)
Asynchronous Receive or USART2 (SCI)
Synchronous Data.
RG7/TX2/CK2
37
40
29
48
35
I/O
ST
RG7 can also be selected as the USART2 (SCI)
Asynchronous Transmit or USART2 (SCI)
Synchronous Clock.
PORTH is a bi-directional I/O Port. PORTH is only
available on the PIC17C76X devices.
RH0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
11
12
13
31
32
33
34
79
80
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
RH1
RH2
RH3
2
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
19
20
21
22
RH4 can also be analog input 12.
RH5 can also be analog input 13.
RH6 can also be analog input 14.
RH7 can also be analog input 15.
PORTJ is a bi-directional I/O Port. PORTJ is only
available on the PIC17C76X devices.
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
TEST
—
—
—
—
—
—
—
—
16
—
—
—
—
—
—
—
—
17
—
—
—
—
—
—
—
—
8
52
53
54
55
73
74
75
76
21
39
40
41
42
59
60
61
62
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Test mode selection control input. Always tie to VSS
for normal operation.
VSS
17, 33, 19, 36, 9, 25, 23, 44, 11, 31,
49, 64 53, 68 41, 56 65, 84 51, 70
P
P
P
P
Ground reference for logic and I/O pins.
VDD
AVSS
AVDD
NC
1, 18, 2, 20, 10, 26, 24, 45, 12, 32,
34, 46 37, 49, 38, 57 61, 2 48, 71
Positive supply for logic and I/O pins.
28
27
—
30
20
19
—
38
26
25
—
Ground reference for A/D converter.
This pin MUST be at the same potential as VSS.
29
37
Positive supply for A/D converter.
This pin MUST be at the same potential as VDD.
1, 18,
1, 22,
No Connect. Leave these pins unconnected.
35, 52
43, 64
Legend: I = Input only; O = Output only;
P = Power; — = Not Used;
I/O = Input/Output;
TTL = TTL input;
ST = Schmitt Trigger input
Note 1: The output is only available by the peripheral operation.
2: Open drain input/output pin. Pin forced to input upon any device RESET.
DS30289C-page 16
1998-2013 Microchip Technology Inc.
PIC17C7XX
4.1.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
4.0
ON-CHIP OSCILLATOR
CIRCUIT
In XT or LF modes, a crystal or ceramic resonator is con-
nected to the OSC1/CLKIN and OSC2/CLKOUT pins to
establish oscillation (Figure 4-2). The PIC17CXXX oscil-
lator design requires the use of a parallel cut crystal. Use
of a series cut crystal may give a frequency out of the
crystal manufacturers specifications.
The internal oscillator circuit is used to generate the
device clock. Four device clock periods generate an
internal instruction clock (TCY).
There are four modes that the oscillator can operate in.
They are selected by the device configuration bits dur-
ing device programming. These modes are:
For frequencies above 24 MHz, it is common for the
crystal to be an overtone mode crystal. Use of overtone
mode crystals require a tank circuit to attenuate the
gain at the fundamental frequency. Figure 4-3 shows
an example circuit.
• LF
• XT
Low Frequency (FOSC 2 MHz)
Standard Crystal/Resonator Frequency
(2 MHz FOSC 33 MHz)
• EC
• RC
External Clock Input
(Default oscillator configuration)
4.1.3
OSCILLATOR/RESONATOR
START-UP
External Resistor/Capacitor
(FOSC 4 MHz)
As the device voltage increases from Vss, the oscillator
will start its oscillations. The time required for the oscil-
lator to start oscillating depends on many factors.
These include:
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 96 ms (nomi-
nal) on POR and BOR. The PWRT is designed to keep
the part in RESET while the power supply stabilizes.
With these two timers on-chip, most applications need
no external RESET circuitry.
• Crystal/resonator frequency
• Capacitor values used (C1 and C2)
• Device VDD rise time
• System temperature
• Series resistor value (and type) if used
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake from SLEEP
through external RESET, Watchdog Timer Reset, or
through an interrupt.
• Oscillator mode selection of device (which selects
the gain of the internal oscillator inverter)
Figure 4-1 shows an example of a typical oscillator/
resonator start-up. The peak-to-peak voltage of the
oscillator waveform can be quite low (less than 50% of
device VDD) when the waveform is centered at VDD/2
(refer to parameter #D033 and parameter #D043 in the
electrical specification section).
Several oscillator options are made available to allow
the part to better fit the application. The RC oscillator
option saves system cost while the LF crystal option
saves power. Configuration bits are used to select var-
ious options.
4.1
Oscillator Configurations
FIGURE 4-1:
OSCILLATOR/
RESONATOR START-UP
CHARACTERISTICS
4.1.1
OSCILLATOR TYPES
The PIC17CXXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
• LF
• XT
• EC
• RC
Low Power Crystal
Crystal/Resonator
External Clock Input
Resistor/Capacitor
The main difference between the LF and XT modes is
the gain of the internal inverter of the oscillator circuit,
which allows the different frequency ranges.
For more details on the device configuration bits, see
Section 17.0.
Crystal Start-up Time
Time
1998-2013 Microchip Technology Inc.
DS30289C-page 17
PIC17C7XX
FIGURE 4-2:
CRYSTAL OR CERAMIC
RESONATOROPERATION
(XT OR LF OSC
FIGURE 4-3:
CRYSTAL OPERATION,
OVERTONE CRYSTALS
(XT OSC
CONFIGURATION)
CONFIGURATION)
C1
C2
OSC1
OSC1
C1
C2
SLEEP
XTAL
SLEEP
RF
OSC2
(Note 1)
OSC2
To internal
logic
C3
L1
PIC17CXXX
PIC17CXXX
0.1 F
See Table 4-1 and Table 4-2 for recommended values of C1
and C2.
To filter the fundamental frequency:
1
(2f)2
=
L1*C2
Note 1: A series resistor (Rs) may be required for AT strip
cut crystals.
Where f = tank circuit resonant frequency. This should be
midway between the fundamental and the 3rd overtone
frequencies of the crystal.
C3 blocks DC current to ground.
TABLE 4-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
TABLE 4-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Oscillator
Type
Resonator
Frequency
Capacitor Range
(1)
C1 = C2
Osc
Type
(2)
(2)
Freq
C1
C2
LF
455 kHz
2.0 MHz
15 - 68 pF
10 - 33 pF
LF
32 kHz
1 MHz
2 MHz
100-150 pF
10-68 pF
10-68 pF
100-150 pF
10-68 pF
10-68 pF
XT
4.0 MHz
8.0 MHz
16.0 MHz
22 - 68 pF
33 - 100 pF
33 - 100 pF
XT
2 MHz
4 MHz
8 MHz
16 MHz
24 MHz
32 MHz
47-100 pF
15-68 pF
15-47 pF
15-47 pF
15-47 pF
10-47 pF
47-100 pF
15-68 pF
15-47 pF
15-47 pF
15-47 pF
10-47 pF
Higher capacitance increases the stability of the oscillator,
but also increases the start-up time. These values are for
design guidance only. Since each resonator has its own
characteristics, the user should consult the resonator manu-
facturer for appropriate values of external components.
Note 1: These values include all board capacitances on
this pin. Actual capacitor value depends on
(1)
(1)
Higher capacitance increases the stability of the oscillator,
but also increases the start-up time and the oscillator cur-
rent. These values are for design guidance only. RS may be
required in XT mode to avoid overdriving the crystals with
low drive level specification. Since each crystal has its own
characteristics, the user should consult the crystal manufac-
turer for appropriate values for external components.
Note 1: Overtone crystals are used at 24 MHz and
higher. The circuit in Figure 4-3 should be used
to select the desired harmonic frequency.
board capacitance.
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
0.3%
0.5%
0.5%
0.5%
0.5%
2: These values include all board capacitances on
this pin. Actual capacitor value depends on
Resonators used did not have built-in capacitors.
board capacitance.
Crystals Used:
32.768 kHz
1.0 MHz
2.0 MHz
4.0 MHz
8.0 MHz
Epson C-001R32.768K-A
ECS-10-13-1
20 PPM
50 PPM
50 PPM
50 PPM
50 PPM
ECS-20-20-1
ECS-40-20-1
ECS ECS-80-S-4
ECS-80-18-1
16.0 MHz
25 MHz
32 MHz
ECS-160-20-1
CTS CTS25M
CRYSTEK HF-2
50 PPM
50 PPM
50 PPM
DS30289C-page 18
1998-2013 Microchip Technology Inc.
PIC17C7XX
4.1.4
EXTERNAL CLOCK OSCILLATOR
FIGURE 4-5:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
In the EC oscillator mode, the OSC1 input can be
driven by CMOS drivers. In this mode, the OSC1/
CLKIN pin is hi-impedance and the OSC2/CLKOUT pin
is the CLKOUT output (4 TOSC).
+5V
To Other
Devices
10 k
4.7 k
74AS04
PIC17CXXX
FIGURE 4-4:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
OSC1
74AS04
10 k
Clock from
ext. system
OSC1
XTAL
PIC17CXXX
OSC2
CLKOUT
(FOSC/4)
10k
20 pF
20 pF
4.1.5
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Figure 4-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental fre-
quency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator cir-
cuit. The 330 resistors provide the negative feedback
to bias the inverters in their linear region.
Either a prepackaged oscillator can be used, or a sim-
ple oscillator circuit with TTL gates can be built. Pre-
packaged oscillators provide a wide operating range
and better stability. A well designed crystal oscillator
will provide good performance with TTL gates. Two
types of crystal oscillator circuits can be used: one with
series resonance, or one with parallel resonance.
FIGURE 4-6:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Figure 4-5 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fun-
damental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 k resistor provides the
negative feedback for stability. The 10 k potentiome-
ter biases the 74AS04 in the linear region. This could
be used for external oscillator designs.
To Other
Devices
330
330
74AS04
74AS04
74AS04
PIC17CXXX
OSC1
0.1 F
XTAL
1998-2013 Microchip Technology Inc.
DS30289C-page 19
PIC17C7XX
4.1.6
RC OSCILLATOR
FIGURE 4-7:
RC OSCILLATOR MODE
VDD
For timing insensitive applications, the RC device
option offers additional cost savings. RC oscillator fre-
quency is a function of the supply voltage, the resistor
(REXT) and capacitor (CEXT) values, and the operating
temperature. In addition to this, oscillator frequency will
vary from unit to unit due to normal process parameter
variation. Furthermore, the difference in lead frame
capacitance between package types will also affect
oscillation frequency, especially for low CEXT values.
The user also needs to take into account variation due
to tolerance of external R and C components used.
Figure 4-7 shows how the R/C combination is con-
nected to the PIC17CXXX. For REXT values below
2.2 k, the oscillator operation may become unstable,
or stop completely. For very high REXT values (e.g.
1 M), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
REXT between 3 k and 100 k.
PIC17CXXX
REXT
Internal
Clock
OSC1
CEXT
VSS
OSC2/CLKOUT
FOSC/4
4.1.6.1
RC Start-up
As the device voltage increases, the RC will immedi-
ately start its oscillations once the pin voltage levels
meet the input threshold specifications (parameter
#D032 and parameter #D042 in the electrical specifica-
tion section). The time required for the RC to start oscil-
lating depends on many factors. These include:
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, oscillation frequency can
vary dramatically due to changes in external capaci-
tances, such as PCB trace capacitance or package
lead frame capacitance.
• Resistor value used
• Capacitor value used
• Device VDD rise time
• System temperature
See Section 21.0 for RC frequency variation from part
to part due to normal process variation. The variation is
larger for larger R (since leakage current variation will
affect RC frequency more for large R) and for smaller
C (since variation of input capacitance will affect RC
frequency more).
See Section 21.0 for variation of oscillator frequency
due to VDD for given REXT/CEXT values, as well as fre-
quency variation due to operating temperature for
given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin and can be used for test pur-
poses or to synchronize other logic (see Figure 4-8 for
waveform).
DS30289C-page 20
1998-2013 Microchip Technology Inc.
PIC17C7XX
4.2
Clocking Scheme/Instruction
Cycle
4.3
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 4-1).
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1 and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-8.
A fetch cycle begins with the program counter incre-
menting in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the Q2,
Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination write).
FIGURE 4-8:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 4-1:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetched instruc-
tion is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1998-2013 Microchip Technology Inc.
DS30289C-page 21
PIC17C7XX
NOTES:
DS30289C-page 22
1998-2013 Microchip Technology Inc.
PIC17C7XX
When the device enters the “RESET state”, the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impedance inputs. The RESET state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
5.0
RESET
The PIC17CXXX differentiates between various kinds
of RESET:
• Power-on Reset (POR)
• Brown-out Reset
• MCLR Reset
Note: While the device is in a RESET state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
• WDT Reset
Some registers are not affected in any RESET condi-
tion, their status is unknown on POR and unchanged in
any other RESET. Most other registers are forced to a
“RESET state”. The TO and PD bits are set or cleared
differently in different RESET situations, as indicated in
Table 5-3. These bits, in conjunction with the POR and
BOR bits, are used in software to determine the nature
of the RESET. See Table 5-4 for a full description of the
RESET states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
BOR
Module
Brown-out
Reset
WDT
Module
WDT
Time_Out
Reset
VDD Rise
Detect
S
Power_On_Reset
VDD
OST/PWRT
Chip_Reset
R
Q
OST
10-bit Ripple Counter
OSC1
PWRT
On-chip
RC OSC†
10-bit Ripple Counter
(Enable the PWRT timer
only during POR or BOR)
(If PWRT is invoked, or a Wake-up from
SLEEP and OSC type is XT or LF)
† This RC oscillator is shared with the WDT when not in a power-up sequence.
1998-2013 Microchip Technology Inc.
DS30289C-page 23
PIC17C7XX
5.1.2
POWER-UP TIMER (PWRT)
5.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from the rising
edge of the internal POR signal if VDD and MCLR are
tied, or after the first rising edge of MCLR (detected
high). The Power-up Timer operates on an internal RC
oscillator. The chip is kept in RESET as long as the
PWRT is active. In most cases, the PWRT delay allows
VDD to rise to an acceptable level.
5.1.1
POWER-ON RESET (POR)
The Power-on Reset circuit holds the device in RESET
until VDD is above the trip point (in the range of 1.4V -
2.3V). The devices produce an internal RESET for both
rising and falling VDD. To take advantage of the POR,
just tie the MCLR/VPP pin directly (or through a resistor)
to VDD. This will eliminate external RC components
usually needed to create Power-on Reset. A minimum
rise time for VDD is required. See Electrical Specifica-
tions for details.
The power-up time delay will vary from chip to chip and
with VDD and temperature. See DC parameters for
details.
5.1.3
OSCILLATOR START-UP TIMER
(OST)
Figure 5-2 and Figure 5-3 show two possible POR
circuits.
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024TOSC) delay whenever the PWRT
is invoked, or a wake-up from SLEEP event occurs in XT
or LF mode. The PWRT and OST operate in parallel.
FIGURE 5-2:
USING ON-CHIP POR
The OST counts the oscillator pulses on the OSC1/
CLKIN pin. The counter only starts incrementing after
the amplitude of the signal reaches the oscillator input
thresholds. This delay allows the crystal oscillator or
resonator to stabilize before the device exits RESET.
The length of the time-out is a function of the crystal/
resonator frequency.
VDD
VDD
MCLR
PIC17CXXX
Figure 5-4 shows the operation of the OST circuit. In
this figure, the oscillator is of such a low frequency that
although enabled simultaneously, the OST does not
time-out until after the Power-up Timer time-out.
FIGURE 5-3:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
FIGURE 5-4:
OSCILLATOR START-UP
TI M E ( L O W F R E Q U E N C Y )
POR or BOR Trip Point
VDD
D
VDD
VDD
R
R1
MCLR
OSC2
MCLR
PIC17CXXX
C
TOSC1
TOST
OST TIME_OUT
Note 1: An external Power-on Reset circuit is
required only if VDD power-up time is too
slow. The diode D helps discharge the capac-
itor quickly when VDD powers down.
PWRT TIME_OUT
2: R < 40 k is recommended to ensure that the
voltage drop across R does not exceed 0.2V
(max. leakage current spec. on the MCLR/
VPP pin is 5 A). A larger voltage drop will
degrade VIH level on the MCLR/VPP pin.
3: R1 = 100 to 1 k will limit any current flow-
ing into MCLR from external capacitor C in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
TPWRT
INTERNAL RESET
This figure shows in greater detail the timings involved
with the oscillator start-up timer. In this example, the low
frequency crystal start-up time is larger than power-up
time (TPWRT).
TOSC1 = time for the crystal oscillator to react to an oscil-
lation level detectable by the Oscillator Start-up Timer
(OST).
TOST = 1024TOSC.
DS30289C-page 24
1998-2013 Microchip Technology Inc.
PIC17C7XX
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/VPP pin must be
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
5.1.4
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: First,
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST and
PWRT timers start. In general, the PWRT time-out is
longer, except with low frequency crystals/resonators.
The total time-out also varies based on oscillator config-
uration. Table 5-1 shows the times that are associated
with the oscillator configuration. Figure 5-5 and Figure 5-
6 display these time-out sequences.
The time-out sequence begins from the first rising edge
of MCLR.
Table 5-3 shows the RESET conditions for some spe-
cial registers, while Table 5-4 shows the initialization
conditions for all the registers.
TABLE 5-1:
TIME-OUT IN VARIOUS SITUATIONS
POR, BOR
Oscillator
Configuration
Wake-up from
MCLR Reset
SLEEP
XT, LF
Greater of: 96 ms or 1024TOSC
Greater of: 96 ms or 1024TOSC
1024TOSC
—
—
—
EC, RC
TABLE 5-2:
STATUS BITS AND THEIR SIGNIFICANCE
(1)
POR
BOR
TO
PD
Event
Power-on Reset
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
1
1
1
0
1
1
1
1
MCLR Reset during normal operation
Brown-out Reset
0
0
0
x
Illegal, TO is set on POR
0
x
0
x
x
1
0
1
Illegal, PD is set on POR
CLRWDTinstruction executed
Note 1: When BODEN is enabled, else the BOR status bit is unknown.
TABLE 5-3:
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
Event
PCH:PCL
0000h
CPUSTA(4)
OST Active
Yes
Power-on Reset
Brown-out Reset
--11 1100
--11 1110
--11 1111
0000h
Yes
MCLR Reset during normal operation
0000h
No
MCLR Reset during SLEEP
0000h
0000h
--11 1011
--11 0111
Yes(2)
No
WDT Reset during normal operation
WDT Reset during SLEEP(3)
0000h
--11 0011
--11 1011
Yes(2)
Yes(2)
Yes(2)
Interrupt Wake-up from SLEEP GLINTD is set
PC + 1
PC + 1(1)
GLINTD is clear
--10 1011
Legend: u= unchanged, x= unknown, -= unimplemented, read as '0'
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active (on wake-up) when the oscillator is configured for XT or LF modes.
3: The Program Counter = 0; that is, the device branches to the RESET vector and places SFRs in WDT
Reset states. This is different from the mid-range devices.
4: When BODEN is enabled, else the BOR status bit is unknown.
1998-2013 Microchip Technology Inc.
DS30289C-page 25
PIC17C7XX
In Figure 5-5, Figure 5-6 and Figure 5-7, the TPWRT
timer time-out is greater then the TOST timer time-out,
as would be the case in higher frequency crystals. For
lower frequency crystals (i.e., 32 kHz), TOST may be
greater.
FIGURE 5-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 5-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
FIGURE 5-7:
SLOW RISE TIME (MCLR TIED TO VDD)
Minimum VDD Operating Voltage
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30289C-page 26
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through Interrupt
Address
Unbanked
INDF0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
N/A
N/A
N/A
FSR0
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
PC + 1(2)
PCL
PCLATH
ALUSTA
T0STA
CPUSTA(3)
INTSTA
INDF1
0000 0000
1111 xxxx
0000 000-
--11 11qq
0000 0000
N/A
uuuu uuuu
1111 uuuu
0000 000-
--11 qquu
0000 0000
N/A
uuuu uuuu
1111 uuuu
0000 000-
--uu qquu
uuuu uuuu(1)
N/A
FSR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
PORTA(4,6)
DDRB
PORTB(4)
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
10h
11h
12h
13h
14h
15h
16h
17h
0-xx 11xx
1111 1111
xxxx xxxx
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
0000 0000
0-uu 11uu
1111 1111
uuuu uuuu
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
0000 0000
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu --uu
uuuu uuuu
uuuu uuuu
Legend: u= unchanged, x= unknown, -= unimplemented, read as '0', q= value depends on condition
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for RESET value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device RESET, these pins are configured as inputs.
1998-2013 Microchip Technology Inc.
DS30289C-page 27
PIC17C7XX
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED)
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through Interrupt
Address
Bank 1
DDRC(5)
PORTC(4,5)
DDRD(5)
PORTD(4,5)
DDRE(5)
10h
11h
12h
13h
14h
15h
16h
17h
1111 1111
xxxx xxxx
1111 1111
xxxx xxxx
---- 1111
---- xxxx
x000 0010
0000 0000
1111 1111
uuuu uuuu
1111 1111
uuuu uuuu
---- 1111
---- uuuu
u000 0010
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
---- uuuu
PORTE(4,5)
PIR1
uuuu uuuu(1)
uuuu uuuu
PIE1
Bank 2
TMR1
10h
11h
12h
13h
14h
15h
16h
17h
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR2
TMR3L
TMR3H
PR1
PR2
PR3/CA1L
PR3/CA1H
Bank 3
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
10h
11h
12h
13h
14h
15h
16h
17h
xx-- ----
xx0- ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
uu-- ----
uu0- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uu-- ----
uuu- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
CA2H
TCON1
TCON2
Legend: u= unchanged, x= unknown, -= unimplemented, read as '0', q= value depends on condition
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for RESET value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device RESET, these pins are configured as inputs.
DS30289C-page 28
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED)
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through Interrupt
Address
Bank 4
uuu- uuuu(1)
uuu- uuuu
---- ----
uuuu -uuu
uuuu uuuu
uuuu --uu
uuuu uuuu
uuuu uuuu
PIR2
10h
000- 0010
000- 0010
PIE2
11h
12h
13h
14h
15h
16h
17h
000- 0000
---- ----
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
0000 0000
000- 0000
---- ----
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
0000 0000
Unimplemented
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
Bank 5
DDRF
10h
11h
1111 1111
0000 0000
1111 1111
0000 0000
uuuu uuuu
uuuu uuuu
PORTF(4)
DDRG
12h
13h
1111 1111
xxxx 0000
1111 1111
uuuu 0000
uuuu uuuu
uuuu uuuu
PORTG(4)
ADCON0
ADCON1
ADRESL
ADRESH
14h
15h
16h
17h
0000 -0-0
000- 0000
xxxx xxxx
xxxx xxxx
0000 -0-0
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Bank 6
SSPADD
10h
11h
12h
13h
14h
15h
16h
17h
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
---- ----
---- ----
---- ----
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
---- ----
---- ----
---- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ----
---- ----
---- ----
SSPCON1
SSPCON2
SSPSTAT
SSPBUF
Unimplemented
Unimplemented
Unimplemented
Legend: u= unchanged, x= unknown, -= unimplemented, read as '0', q= value depends on condition
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for RESET value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device RESET, these pins are configured as inputs.
1998-2013 Microchip Technology Inc.
DS30289C-page 29
PIC17C7XX
TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED)
Power-on Reset
Brown-out Reset
MCLR Reset
WDT Reset
Wake-up from SLEEP
through Interrupt
Address
Bank 7
PW3DCL
PW3DCH
CA3L
10h
11h
12h
13h
14h
15h
16h
17h
xx0- ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-000 0000
---- ----
uu0- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-000 0000
---- ----
uuu- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- ----
CA3H
CA4L
CA4H
TCON3
Unimplemented
Bank 8
DDRH
10h
11h
1111 1111
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
PORTH(4)
DDRJ
12h
13h
1111 1111
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
PORTJ(4)
Unbanked
PRODL
18h
19h
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PRODH
Legend: u= unchanged, x= unknown, -= unimplemented, read as '0', q= value depends on condition
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for RESET value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device RESET, these pins are configured as inputs.
DS30289C-page 30
1998-2013 Microchip Technology Inc.
PIC17C7XX
that may be implemented. Each needs to be evaluated
to determine if they match the requirements of the
application.
5.1.5
BROWN-OUT RESET (BOR)
PIC17C7XX devices have on-chip Brown-out Reset
circuitry. This circuitry places the device into a RESET
when the device voltage falls below a trip point (BVDD).
This ensures that the device does not continue pro-
gram execution outside the valid operation range of the
device. Brown-out Resets are typically used in AC line
applications, or large battery applications, where large
loads may be switched in (such as automotive).
FIGURE 5-8:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
33k
VDD
Note: Before using the on-chip Brown-out for a
voltage supervisory function, please
review the electrical specifications to
ensure that they meet your requirements.
10k
40 k
MCLR
PIC17CXXX
The BODEN configuration bit can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below BVDD (typically 4.0 V,
paramter #D005 in electrical specification section), for
greater than parameter #35, the Brown-out situation
will reset the chip. A RESET is not guaranteed to occur
if VDD falls below BVDD for less than paramter #35. The
chip will remain in Brown-out Reset until VDD rises
above BVDD. The Power-up Timer and Oscillator Start-
up Timer will then be invoked. This will keep the chip in
RESET the greater of 96 ms and 1024 TOSC. If VDD
drops below BVDD while the Power-up Timer/Oscillator
Start-up Timer is running, the chip will go back into a
Brown-out Reset. The Power-up Timer/Oscillator Start-
up Timer will be initialized. Once VDD rises above
BVDD, the Power-up Timer/Oscillator Start-up Timer
will start their time delays. Figure 5-10 shows typical
Brown-out situations.
This circuit will activate RESET when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
FIGURE 5-9:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
R1
VDD
Q1
MCLR
R2
40 k
PIC17CXXX
This brown-out circuit is less expensive, albeit less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
In some applications, the Brown-out Reset trip point of
the device may not be at the desired level. Figure 5-8
and Figure 5-9 are two examples of external circuitry
R1
= 0.7V
VDD •
R1 + R2
FIGURE 5-10:
BROWN-OUT SITUATIONS
VDD
BVDD Max.
BVDD Min.
Internal
RESET
Greater of 96 ms
and 1024 TOSC
VDD
BVDD Max.
BVDD Min.
Internal
RESET
< 96 ms
Greater of 96 ms
and 1024 TOSC
VDD
BVDD Max.
BVDD Min.
Internal
RESET
Greater of 96 ms
and 1024 TOSC
1998-2013 Microchip Technology Inc.
DS30289C-page 31
PIC17C7XX
NOTES:
DS30289C-page 32
1998-2013 Microchip Technology Inc.
PIC17C7XX
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupts, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. There are four
interrupt vectors. Each vector address is for a specific
interrupt source (except the peripheral interrupts, which
all vector to the same address). These sources are:
6.0
INTERRUPTS
PIC17C7XX devices have 18 sources of interrupt:
• External interrupt from the RA0/INT pin
• Change on RB7:RB0 pins
• TMR0 Overflow
• TMR1 Overflow
• TMR2 Overflow
• TMR3 Overflow
• External interrupt from the RA0/INT pin
• TMR0 Overflow
• USART1 Transmit buffer empty
• USART1 Receive buffer full
• USART2 Transmit buffer empty
• USART2 Receive buffer full
• SSP Interrupt
• T0CKI edge occurred
• Any peripheral interrupt
When program execution vectors to one of these inter-
rupt vector addresses (except for the peripheral inter-
rupts), the interrupt flag bit is automatically cleared.
Vectoring to the peripheral interrupt vector address
does not automatically clear the source of the interrupt.
In the peripheral Interrupt Service Routine, the
source(s) of the interrupt can be determined by testing
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
• SSP I2C bus collision interrupt
• A/D conversion complete
• Capture1
• Capture2
• Capture3
• Capture4
• T0CKI edge occurred
There are six registers used in the control and status of
interrupts. These are:
When an interrupt condition is met, that individual inter-
rupt flag bit will be set, regardless of the status of its
corresponding mask bit or the GLINTD bit.
• CPUSTA
• INTSTA
• PIE1
• PIR1
• PIE2
For external interrupt events, there will be an interrupt
latency. For two-cycle instructions, the latency could be
one instruction cycle longer.
The “return from interrupt” instruction, RETFIE, can be
used to mark the end of the Interrupt Service Routine.
When this instruction is executed, the stack is “POPed”
and the GLINTD bit is cleared (to re-enable interrupts).
• PIR2
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Section 6.4.
FIGURE 6-1:
INTERRUPT LOGIC
RBIF
RBIE
TMR3IF
TMR3IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
INTSTA
Wake-up (If in SLEEP mode)
or terminate long write
CA2IF
CA2IE
T0IF
T0IE
CA1IF
CA1IE
INTF
INTE
Interrupt to CPU
TX1IF
TX1IE
T0CKIF
RC1IF
RC1IE
T0CKIE
PEIF
SSPIF
SSPIE
PEIE
BCLIF
BCLIE
GLINTD (CPUSTA<4>)
ADIF
ADIE
CA4IF
CA4IE
CA3IF
CA3IE
TX2IF
TX2IE
RC2IF
RC2IE
1998-2013 Microchip Technology Inc.
DS30289C-page 33
PIC17C7XX
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is cleared,
the device will vector to the RESET address (0x00).
6.1
Interrupt Status Register (INTSTA)
The Interrupt Status/Control register (INTSTA) contains
the flag and enable bits for non-peripheral interrupts.
The PEIF bit is a read only, bit wise OR of all the periph-
eral flag bits in the PIR registers (Figure 6-4 and
Figure 6-5).
Prior to disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
Note: All interrupt flag bits get set by their speci-
fied condition, even if the corresponding
interrupt enable bit is clear (interrupt dis-
abled), or the GLINTD bit is set (all inter-
rupts disabled).
REGISTER 6-1: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R-0
PEIF
R/W-0
T0CKIF
R/W-0
T0IF
R/W-0
INTF
R/W-0
PEIE
R/W-0
T0CKIE
R/W-0
T0IE
R/W-0
INTE
bit 7
bit 0
bit 7
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
The interrupt logic forces program execution to address (20h) when a peripheral interrupt is
pending.
1= A peripheral interrupt is pending
0= No peripheral interrupt is pending
bit 6
bit 5
bit 4
bit 3
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).
1= The software specified edge occurred on the RA1/T0CKI pin
0= The software specified edge did not occur on the RA1/T0CKI pin
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).
1 = TMR0 overflowed
0= TMR0 did not overflow
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (08h).
1= The software specified edge occurred on the RA0/INT pin
0= The software specified edge did not occur on the RA0/INT pin
PEIE: Peripheral Interrupt Enable bit
This bit acts as a global enable bit for the peripheral interrupts that have their corresponding
enable bits set.
1= Enable peripheral interrupts
0= Disable peripheral interrupts
bit 2
bit 1
bit 0
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1= Enable software specified edge interrupt on the RA1/T0CKI pin
0= Disable interrupt on the RA1/T0CKI pin
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enable TMR0 overflow interrupt
0= Disable TMR0 overflow interrupt
INTE: External Interrupt on RA0/INT Pin Enable bit
1= Enable software specified edge interrupt on the RA0/INT pin
0= Disable software specified edge interrupt on the RA0/INT pin
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
DS30289C-page 34
1998-2013 Microchip Technology Inc.
PIC17C7XX
6.2
Peripheral Interrupt Enable
Register1 (PIE1) and Register2
(PIE2)
These registers contains the individual enable bits for
the peripheral interrupts.
REGISTER 6-2: PIE1 REGISTER (ADDRESS: 17h, BANK 1)
R/W-0
RBIE
R/W-0
R/W-0
R/W-0
R/W-0
CA2IE
R/W-0
CA1IE
R/W-0
TX1IE
R/W-0
RC1IE
bit 0
TMR3IE
TMR2IE
TMR1IE
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBIE: PORTB Interrupt-on-Change Enable bit
1= Enable PORTB interrupt-on-change
0= Disable PORTB interrupt-on-change
TMR3IE: TMR3 Interrupt Enable bit
1= Enable TMR3 interrupt
0= Disable TMR3 interrupt
TMR2IE: TMR2 Interrupt Enable bit
1= Enable TMR2 interrupt
0= Disable TMR2 interrupt
TMR1IE: TMR1 Interrupt Enable bit
1= Enable TMR1 interrupt
0= Disable TMR1 interrupt
CA2IE: Capture2 Interrupt Enable bit
1= Enable Capture2 interrupt
0= Disable Capture2 interrupt
CA1IE: Capture1 Interrupt Enable bit
1= Enable Capture1 interrupt
0= Disable Capture1 interrupt
TX1IE: USART1 Transmit Interrupt Enable bit
1= Enable USART1 Transmit buffer empty interrupt
0= Disable USART1 Transmit buffer empty interrupt
RC1IE: USART1 Receive Interrupt Enable bit
1= Enable USART1 Receive buffer full interrupt
0= Disable USART1 Receive buffer full interrupt
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
1998-2013 Microchip Technology Inc.
DS30289C-page 35
PIC17C7XX
REGISTER 6-3: PIE2 REGISTER (ADDRESS: 11h, BANK 4)
R/W-0
SSPIE
R/W-0
BCLIE
R/W-0
ADIE
U-0
—
R/W-0
CA4IE
R/W-0
CA3IE
R/W-0
TX2IE
R/W-0
RC2IE
bit 7
bit 0
bit 7
bit 6
bit 5
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enable SSP interrupt
0= Disable SSP interrupt
BCLIE: Bus Collision Interrupt Enable bit
1= Enable bus collision interrupt
0= Disable bus collision interrupt
ADIE: A/D Module Interrupt Enable bit
1= Enable A/D module interrupt
0= Disable A/D module interrupt
bit 4
bit 3
Unimplemented: Read as ‘0’
CA4IE: Capture4 Interrupt Enable bit
1= Enable Capture4 interrupt
0= Disable Capture4 interrupt
bit 2
bit 1
bit 0
CA3IE: Capture3 Interrupt Enable bit
1= Enable Capture3 interrupt
0= Disable Capture3 interrupt
TX2IE: USART2 Transmit Interrupt Enable bit
1= Enable USART2 Transmit buffer empty interrupt
0= Disable USART2 Transmit buffer empty interrupt
RC2IE: USART2 Receive Interrupt Enable bit
1= Enable USART2 Receive buffer full interrupt
0= Disable USART2 Receive buffer full interrupt
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
DS30289C-page 36
1998-2013 Microchip Technology Inc.
PIC17C7XX
6.3
Peripheral Interrupt Request
Register1 (PIR1) and Register2
(PIR2)
Note:
These bits will be set by the specified condi-
tion, even if the corresponding interrupt
enable bit is cleared (interrupt disabled), or
the GLINTD bit is set (all interrupts disabled).
Before enabling an interrupt, the user may
wish to clear the interrupt flag to ensure that
the program does not immediately branch to
the peripheral Interrupt Service Routine.
These registers contains the individual flag bits for the
peripheral interrupts.
REGISTER 6-4: PIR1 REGISTER (ADDRESS: 16h, BANK 1)
R/W-x
RBIF
R/W-0
TMR3IF
R/W-0
TMR2IF
R/W-0
TMR1IF
R/W-0
CA2IF
R/W-0
CA1IF
R-1
TX1IF
R-0
RC1IF
bit 7
bit 0
bit 7
bit 6
RBIF: PORTB Interrupt-on-Change Flag bit
1= One of the PORTB inputs changed (software must end the mismatch condition)
0= None of the PORTB inputs have changed
TMR3IF: TMR3 Interrupt Flag bit
If Capture1 is enabled (CA1/PR3 = 1):
1= TMR3 overflowed
0= TMR3 did not overflow
If Capture1 is disabled (CA1/PR3 = 0):
1= TMR3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value
0= TMR3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L)
value
bit 5
bit 4
TMR2IF: TMR2 Interrupt Flag bit
1= TMR2 value has rolled over to 0000h from equalling the period register (PR2) value
0= TMR2 value has not rolled over to 0000h from equalling the period register (PR2) value
TMR1IF: TMR1 Interrupt Flag bit
If TMR1 is in 8-bit mode (T16 = 0):
1= TMR1 value has rolled over to 0000h from equalling the period register (PR1) value
0= TMR1 value has not rolled over to 0000h from equalling the period register (PR1) value
If Timer1 is in 16-bit mode (T16 = 1):
1= TMR2:TMR1 value has rolled over to 0000h from equalling the period register (PR2:PR1)
value
0= TMR2:TMR1 value has not rolled over to 0000h from equalling the period register (PR2:PR1)
value
bit 3
bit 2
bit 1
bit 0
CA2IF: Capture2 Interrupt Flag bit
1= Capture event occurred on RB1/CAP2 pin
0= Capture event did not occur on RB1/CAP2 pin
CA1IF: Capture1 Interrupt Flag bit
1= Capture event occurred on RB0/CAP1 pin
0= Capture event did not occur on RB0/CAP1 pin
TX1IF: USART1 Transmit Interrupt Flag bit (state controlled by hardware)
1= USART1 Transmit buffer is empty
0= USART1 Transmit buffer is full
RC1IF: USART1 Receive Interrupt Flag bit (state controlled by hardware)
1= USART1 Receive buffer is full
0= USART1 Receive buffer is empty
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
1998-2013 Microchip Technology Inc.
DS30289C-page 37
PIC17C7XX
REGISTER 6-5: PIR2 REGISTER (ADDRESS: 10h, BANK 4)
R/W-0
SSPIF
R/W-0
BCLIF
R/W-0
ADIF
U-0
—
R/W-0
CA4IF
R/W-0
CA3IF
R-1
TX2IF
R-0
RC2IF
bit 7
bit 0
bit 7
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1= The SSP interrupt condition has occurred and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI:
A transmission/reception has taken place.
I2C Slave/Master:
A transmission/reception has taken place.
I2C Master:
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was idle (Multi-master system).
A STOP condition occurred while the SSP module was idle (Multi-master system).
0= An SSP interrupt condition has NOT occurred
bit 6
bit 5
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision has occurred in the SSP, when configured for I2C Master mode
0= No bus collision has occurred
ADIF: A/D Module Interrupt Flag bit
1= An A/D conversion is complete
0= An A/D conversion is not complete
bit 4
bit 3
Unimplemented: Read as '0'
CA4IF: Capture4 Interrupt Flag bit
1= Capture event occurred on RE3/CAP4 pin
0= Capture event did not occur on RE3/CAP4 pin
bit 2
bit 1
bit 0
CA3IF: Capture3 Interrupt Flag bit
1= Capture event occurred on RG4/CAP3 pin
0= Capture event did not occur on RG4/CAP3 pin
TX2IF:USART2 Transmit Interrupt Flag bit (state controlled by hardware)
1= USART2 Transmit buffer is empty
0= USART2 Transmit buffer is full
RC2IF: USART2 Receive Interrupt Flag bit (state controlled by hardware)
1= USART2 Receive buffer is full
0= USART2 Receive buffer is empty
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
DS30289C-page 38
1998-2013 Microchip Technology Inc.
PIC17C7XX
6.4
Interrupt Operation
6.5
RA0/INT Interrupt
Global Interrupt Disable bit, GLINTD (CPUSTA<4>),
enables all unmasked interrupts (if clear), or disables
all interrupts (if set). Individual interrupts can be dis-
abled through their corresponding enable bits in the
INTSTA register. Peripheral interrupts need either the
global peripheral enable PEIE bit disabled, or the spe-
cific peripheral enable bit disabled. Disabling the
peripherals via the global peripheral enable bit, dis-
ables all peripheral interrupts. GLINTD is set on
RESET (interrupts disabled).
The external interrupt on the RA0/INT pin is edge trig-
gered. Either the rising edge if the INTEDG bit
(T0STA<7>) is set, or the falling edge if the INTEDG bit
is clear. When a valid edge appears on the RA0/INT
pin, the INTF bit (INTSTA<4>) is set. This interrupt can
be disabled by clearing the INTE control bit
(INTSTA<0>). The INT interrupt can wake the proces-
sor from SLEEP. See Section 17.4 for details on
SLEEP operation.
6.6
T0CKI Interrupt
The RETFIE instruction clears the GLINTD bit while
forcing the Program Counter (PC) to the value loaded
at the Top-of-Stack.
The external interrupt on the RA1/T0CKI pin is edge
triggered. Either the rising edge if the T0SE bit
(T0STA<6>) is set, or the falling edge if the T0SE bit is
clear. When a valid edge appears on the RA1/T0CKI
pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt
can be disabled by clearing the T0CKIE control bit
(INTSTA<2>). The T0CKI interrupt can wake up the
processor from SLEEP. See Section 17.4 for details on
SLEEP operation.
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector. There are four interrupt
vectors which help reduce interrupt latency.
The peripheral interrupt vector has multiple interrupt
sources. Once in the peripheral Interrupt Service Rou-
tine, the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The peripheral interrupt
flag bit(s) must be cleared in software before re-
enabling interrupts to avoid continuous interrupts.
6.7
Peripheral Interrupt
The peripheral interrupt flag indicates that at least one
of the peripheral interrupts occurred (PEIF is set). The
PEIF bit is a read only bit and is a bit wise OR of all the
flag bits in the PIR registers AND’d with the correspond-
ing enable bits in the PIE registers. Some of the periph-
eral interrupts can wake the processor from SLEEP.
See Section 17.4 for details on SLEEP operation.
The PIC17C7XX devices have four interrupt vectors.
These vectors and their hardware priority are shown in
Table 6-1. If two enabled interrupts occur “at the same
time”, the interrupt of the highest priority will be ser-
viced first. This means that the vector address of that
interrupt will be loaded into the program counter (PC).
6.8
Context Saving During Interrupts
TABLE 6-1:
INTERRUPT VECTORS/
PRIORITIES
During an interrupt, only the returned PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt; e.g. WREG, ALUSTA and the
BSR registers. This requires implementation in software.
Address
Vector
Priority
0008h
0010h
0018h
0020h
External Interrupt on RA0/
INT pin (INTF)
1 (Highest)
Example 6-2 shows the saving and restoring of infor-
mation for an Interrupt Service Routine. This is for a
simple interrupt scheme, where only one interrupt may
occur at a time (no interrupt nesting). The SFRs are
stored in the non-banked GPR area.
TMR0 Overflow Interrupt
(T0IF)
2
3
External Interrupt on T0CKI
(T0CKIF)
Example 6-2 shows the saving and restoring of infor-
mation for a more complex Interrupt Service Routine.
This is useful where nesting of interrupts is required. A
maximum of 6 levels can be done by this example. The
BSR is stored in the non-banked GPR area, while the
other registers would be stored in a particular bank.
Therefore, 6 saves may be done with this routine (since
there are 6 non-banked GPR registers). These routines
require a dedicated indirect addressing register, FSR0,
to be selected for this.
Peripherals (PEIF)
4 (Lowest)
Note 1: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GLINTD bit.
2: Before disabling any of the INTSTA enable
bits, the GLINTD bit should be set
(disabled).
The PUSH and POP code segments could either be in
each Interrupt Service Routine, or could be subroutines
that were called. Depending on the application, other
registers may also need to be saved.
1998-2013 Microchip Technology Inc.
DS30289C-page 39
PIC17C7XX
FIGURE 6-2:
INT PIN/T0CKI PIN INTERRUPT TIMING
DS30289C-page 40
1998-2013 Microchip Technology Inc.
PIC17C7XX
EXAMPLE 6-1:
SAVING STATUS AND WREG IN RAM (SIMPLE)
; The addresses that are used to store the CPUSTA and WREG values must be in the data memory
; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP
; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.
;
UNBANK1
UNBANK2
UNBANK3
UNBANK4
UNBANK5
EQU
EQU
EQU
EQU
EQU
0x01A
0x01B
0x01C
0x01D
0x01E
; Address for 1st location to save
; Address for 2nd location to save
; Address for 3rd location to save
; Address for 4th location to save
; Address for 5th location to save
;
(Label Not used in program)
; Address for 6th location to save
(Label Not used in program)
UNBANK6
;
EQU
0x01F
;
:
; At Interrupt Vector Address
; Push ALUSTA value
; Push BSR value
; Push WREG value
; Push PCLATH value
PUSH
MOVFP
MOVFP
MOVFP
MOVFP
;
ALUSTA, UNBANK1
BSR, UNBANK2
WREG, UNBANK3
PCLATH, UNBANK4
:
; Interrupt Service Routine (ISR) code
;
POP
;
MOVFP
MOVFP
MOVFP
MOVFP
UNBANK4, PCLATH
UNBANK3, WREG
UNBANK2, BSR
; Restore PCLATH value
; Restore WREG value
; Restore BSR value
; Restore ALUSTA value
UNBANK1, ALUSTA
RETFIE
; Return from interrupt (enable interrupts)
1998-2013 Microchip Technology Inc.
DS30289C-page 41
PIC17C7XX
EXAMPLE 6-2:
SAVING STATUS AND WREG IN RAM (NESTED)
; The addresses that are used to store the CPUSTA and WREG values must be in the data memory
; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP
; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.
; This routine uses the FRS0, so it controls the FS1 and FS0 bits in the ALUSTA register.
;
Nobank_FSR
Bank_FSR
ALU_Temp
WREG_TEMP
BSR_S1
BSR_S2
BSR_S3
BSR_S4
BSR_S5
BSR_S6
;
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0x40
0x41
0x42
0x43
0x01A
0x01B
0x01C
0x01D
0x01E
0x01F
; 1st location to save BSR
; 2nd location to save BSR (Label Not used in program)
; 3rd location to save BSR (Label Not used in program)
; 4th location to save BSR (Label Not used in program)
; 5th location to save BSR (Label Not used in program)
; 6th location to save BSR (Label Not used in program)
INITIALIZATION
CALL
;
CLEAR_RAM
; Must Clear all Data RAM
;
INIT_POINTERS
CLRF
; Must Initialize the pointers for POP and PUSH
; Set All banks to 0
BSR, F
CLRF
BSF
CLRF
MOVLW
MOVWF
MOVWF
MOVLW
MOVWF
:
ALUSTA, F
ALUSTA, FS1
WREG, F
BSR_S1
FSR0
Nobank_FSR
0x20
; FSR0 post increment
; Clear WREG
; Load FSR0 with 1st address to save BSR
Bank_FSR
:
; Your code
:
:
; At Interrupt Vector Address
PUSH
BSF
ALUSTA, FS0
; FSR0 has auto-increment, does not affect status bits
BCF
ALUSTA, FS1
; does not affect status bits
MOVFP
CLRF
MOVPF
MOVPF
MOVPF
MOVFP
MOVFP
MOVFP
MOVFP
MOVPF
MOVFP
;
BSR, INDF0
BSR, F
; No Status bits are affected
; Peripheral and Data RAM Bank 0 No Status bits are affected
;
; Save the FSR for BSR values
;
; Restore FSR value for other values
; Push ALUSTA value
; Push WREG value
ALUSTA, ALU_Temp
FSR0, Nobank_FSR
WREG, WREG_TEMP
Bank_FSR, FSR0
ALU_Temp, INDF0
WREG_TEMP, INDF0
PCLATH, INDF0
FSR0, Bank_FSR
Nobank_FSR, FSR0
; Push PCLATH value
; Restore FSR value for other values
;
:
; Interrupt Service Routine (ISR) code
;
POP
CLRF
MOVFP
DECF
MOVFP
MOVFP
BSF
MOVPF
MOVPF
DECF
MOVFP
MOVFP
MOVFP
ALUSTA, F
Bank_FSR, FSR0
FSR0, F
INDF0, PCLATH
INDF0, WREG
ALUSTA, FS1
INDF0, ALU_Temp
FSR0, Bank_FSR
Nobank_FSR, F
Nobank_FSR, FSR0
ALU_Temp, ALUSTA
INDF0, BSR
; FSR0 has auto-decrement, does not affect status bits
; Restore FSR value for other values
;
; Pop PCLATH value
; Pop WREG value
; FSR0 does not change
; Pop ALUSTA value
; Restore FSR value for other values
;
; Save the FSR for BSR values
;
; No Status bits are affected
;
RETFIE
; Return from interrupt (enable interrupts)
DS30289C-page 42
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 7-1:
PROGRAM MEMORY MAP
AND STACK
7.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC17C7XX; pro-
gram memory and data memory. Each block has its
own bus, so that access to each block can occur during
the same oscillator cycle.
PC<15:0>
16
CALL, RETURN
RETFIE, RETLW
Stack Level 1
The data memory can further be broken down into
General Purpose RAM and the Special Function Reg-
isters (SFRs). The operation of the SFRs that control
the “core” are described here. The SFRs used to con-
trol the peripheral modules are described in the section
discussing each individual peripheral module.
Stack Level 16
0000h
RESET Vector
INT Pin Interrupt Vector
Timer0 Interrupt Vector
T0CKI Pin Interrupt Vector
Peripheral Interrupt Vector
0008h
0010h
0018h
7.1
Program Memory Organization
PIC17C7XX devices have a 16-bit program counter
capable of addressing a 64K x 16 program memory
space. The RESET vector is at 0000h and the interrupt
vectors are at 0008h, 0010h, 0018h, and 0020h
(Figure 7-1).
0020h
0021h
7.1.1
PROGRAM MEMORY OPERATION
The PIC17C7XX can operate in one of four possible
program memory configurations. The configuration is
selected by configuration bits. The possible modes are:
1FFFh
(PIC17C752
PIC17C762)
• Microprocessor
• Microcontroller
• Extended Microcontroller
• Protected Microcontroller
3FFFh
(PIC17C756A
PIC17C766)
The Microcontroller and Protected Microcontroller
modes only allow internal execution. Any access
beyond the program memory reads unknown data. The
Protected Microcontroller mode also enables the code
protection feature.
FDFFh
FE00h
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
Reserved
PM1
Reserved
FE01h
FE02h
FE03h
FE04h
FE05h
FE06h
FE07h
FE08h
FE0Dh
FE0Eh
FE0Fh
FE10h
FF5Fh
FF60h
The Extended Microcontroller mode accesses both
the internal program memory, as well as external pro-
gram memory. Execution automatically switches
between internal and external memory. The 16-bits of
address allow a program memory range of 64K-words.
Reserved
BODEN
PM2
The Microprocessor mode only accesses the external
program memory. The on-chip program memory is
ignored. The 16-bits of address allow a program mem-
ory range of 64K-words. Microprocessor mode is the
default mode of an unprogrammed device.
Test EPROM
Boot ROM
FFFFh
The different modes allow different access to the con-
figuration bits, test memory and boot ROM. Table 7-1
lists which modes can access which areas in memory.
Test Memory and Boot Memory are not required for
normal operation of the device. Care should be taken
to ensure that no unintended branches occur to these
areas.
Note 1: User memory space may be internal, external,
or both. The memory configuration depends
on the processor mode.
1998-2013 Microchip Technology Inc.
DS30289C-page 43
PIC17C7XX
The PIC17C7XX can operate in modes where the pro-
gram memory is off-chip. They are the Microprocessor
and Extended Microcontroller modes. The Micropro-
cessor mode is the default for an unprogrammed
device.
TABLE 7-1:
MODE MEMORY ACCESS
Internal
Program
Memory
Configuration Bits,
Test Memory,
Boot ROM
Operating
Mode
Microprocessor
Microcontroller
No Access
Access
No Access
Access
Regardless of the processor mode, data memory is
always on-chip.
Extended
Microcontroller
Access
Access
No Access
Access
Protected
Microcontroller
FIGURE 7-2:
MEMORY MAP IN DIFFERENT MODES
Extended
Microcontroller
Mode
Microcontroller
Modes
Microprocessor
Mode
0000h
0000h
0000h
On-chip
Program
Memory
On-chip
Program
Memory
01FFFh
2000h
01FFFh
2000h
External
Program
Memory
External
Program
Memory
PIC17C752/762
Config. Bits
Test Memory
Boot ROM
FE00h
FFFFh
FFFFh
FFFFh
OFF-CHIP
ON-CHIP
00h
OFF-CHIP
ON-CHIP
00h
OFF-CHIP
ON-CHIP
00h
120h
120h
120h
FFh 1FFh
ON-CHIP
FFh 1FFh
ON-CHIP
FFh 1FFh
ON-CHIP
0000h
3FFFh
0000h
0000h
On-chip
Program
Memory
On-chip
Program
Memory
3FFFh
4000h
External
Program
Memory
4000h
External
Program
Memory
PIC17C756A/766
Config. Bits
Test Memory
Boot ROM
FE00h
FFFFh
FFFFh
FFFFh
OFF-CHIP
00h
ON-CHIP
OFF-CHIP
00h
ON-CHIP
OFF-CHIP
ON-CHIP
00h
120h
220h 320h
120h
120h
320h
320h
220h
220h
2FFh
FFh 1FFh
FFh 1FFh
3FFh
FFh 1FFh
2FFh
2FFh 3FFh
3FFh
ON-CHIP
ON-CHIP
ON-CHIP
DS30289C-page 44
1998-2013 Microchip Technology Inc.
PIC17C7XX
In Extended Microcontroller mode, when the device is
executing out of internal memory, the control signals
will continue to be active. That is, they indicate the
action that is occurring in the internal memory. The
external memory access is ignored.
7.1.2
EXTERNAL MEMORY INTERFACE
When either Microprocessor or Extended Microcontrol-
ler mode is selected, PORTC, PORTD and PORTE are
configured as the system bus. PORTC and PORTD are
the multiplexed address/data bus and PORTE<2:0> is
for the control signals. External components are
needed to demultiplex the address and data. This can
be done as shown in Figure 7-4. The waveforms of
address and data are shown in Figure 7-3. For com-
plete timings, please refer to the electrical specification
section.
The following selection is for use with Microchip
EPROMs. For interfacing to other manufacturers mem-
ory, please refer to the electrical specifications of the
desired PIC17C7XX device, as well as the desired
memory device to ensure compatibility.
TABLE 7-2:
EPROM MEMORY ACCESS
TIME ORDERING SUFFIX
FIGURE 7-3:
EXTERNAL PROGRAM
MEMORY ACCESS
WAVEFORMS
PIC17C7XX Instruction
Oscillator CycleTime
Q1 Q2
Q4 Q1 Q2
Q4 Q1
Q3
Q3
Frequency
(TCY)
EPROM Suffix
AD
<15:0>
8 MHz
500 ns
250 ns
200 ns
160 ns
-25
-15
-10
-70
Address out Data in
Data out
Address out
16 MHz
20 MHz
25 MHz
ALE
OE
'1'
WR
Read Cycle
Write Cycle
Note: The access times for this requires the use
of fast SRAMs.
The system bus requires that there is no bus conflict
(minimal leakage), so the output value (address) will be
capacitively held at the desired value.
The electrical specifications now include timing specifi-
cations for the memory interface with PIC17LCXXX
devices. These specifications reflect the capability of
the device by characterization. Please validate your
design with these timings.
As the speed of the processor increases, external
EPROM memory with faster access time must be used.
Table 7-2 lists external memory speed requirements for
a given PIC17C7XX device frequency.
FIGURE 7-4:
TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM
AD15-AD0
(3)
(3)
Memory
(LSB)
Memory
(MSB)
A15-A0
(3)
AD7-AD0
373
Ax-A0
D7-D0
Ax-A0
PIC17CXXX
D7-D0
CE
CE
(2)
(2)
OE WR
OE WR
AD15-AD8
ALE
(3)
373
(1)
138
(1)
I/O
OE
WR
Note 1: Use of I/O pins is only required for paged memory.
2: This signal is unused for ROM and EPROM devices.
3: 16-bit wide devices are now common and could be used instead of 8-bit wide devices.
1998-2013 Microchip Technology Inc.
DS30289C-page 45
PIC17C7XX
7.2.1
GENERAL PURPOSE REGISTER
(GPR)
7.2
Data Memory Organization
Data memory is partitioned into two areas. The first is
the General Purpose Registers (GPR) area, and the
second is the Special Function Registers (SFR) area.
The SFRs control and provide status of device opera-
tion.
All devices have some amount of GPR area. The GPRs
are 8-bits wide. When the GPR area is greater than
232, it must be banked to allow access to the additional
memory space.
Portions of data memory are banked, this occurs in
both areas. The GPR area is banked to allow greater
than 232 bytes of general purpose RAM.
All the PIC17C7XX devices have banked memory in
the GPR area. To facilitate switching between these
banks, the MOVLR bankinstruction has been added to
the instruction set. GPRs are not initialized by a Power-
on Reset and are unchanged on all other RESETS.
Banking requires the use of control bits for bank selec-
tion. These control bits are located in the Bank Select
Register (BSR). If an access is made to the unbanked
region, the BSR bits are ignored. Figure 7-5 shows the
data memory map organization.
7.2.2
SPECIAL FUNCTION REGISTERS
(SFR)
The SFRs are used by the CPU and peripheral func-
tions to control the operation of the device (Figure 7-5).
These registers are static RAM.
Instructions MOVPF and MOVFP provide the means to
move values from the peripheral area (“P”) to any loca-
tion in the register file (“F”), and vice-versa. The defini-
tion of the “P” range is from 0h to 1Fh, while the “F”
range is 0h to FFh. The “P” range has six more loca-
tions than peripheral registers, which can be used as
General Purpose Registers. This can be useful in some
applications where variables need to be copied to other
locations in the general purpose RAM (such as saving
status information during an interrupt).
The SFRs can be classified into two sets, those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described here, while those related to a
peripheral feature are described in the section for each
peripheral feature.
The peripheral registers are in the banked portion of
memory, while the core registers are in the unbanked
region. To facilitate switching between the peripheral
banks, the MOVLB bankinstruction has been provided.
The entire data memory can be accessed either
directly, or indirectly (through file select registers FSR0
and FSR1) (see Section 7.4). Indirect addressing uses
the appropriate control bits of the BSR for access into
the banked areas of data memory. The BSR is
explained in greater detail in Section 7.8.
DS30289C-page 46
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 7-5:
PIC17C7XX REGISTER FILE MAP
Addr Unbanked
INDF0
FSR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1,4)
Bank 0
PORTA
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
SSPADD
SSPCON1 PW3DCH
Bank 7
Bank 8
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
PIR1
TMR1
TMR2
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
PIR2
PIE2
—
DDRF
PORTF
PW3DCL
DDRH
PORTH
DDRJ
PORTJ
—
10h
11h
12h
13h
14h
15h
16h
17h
DDRB
PORTB
TMR3L
TMR3H
PR1
DDRG
SSPCON2
CA3L
CA3H
CA4L
CA4H
TCON3
—
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
Unbanked
PRODL
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
PORTG
ADCON0
ADCON1
ADRESL
ADRESH
SSPSTAT
SSPBUF
—
—
—
—
PR2
CA2H
—
PR3L/CA1L
PR3H/CA1H
TCON1
TCON2
—
PIE1
18h
19h
1Ah
PRODH
General
Purpose
RAM
1Fh
20h
(2)
(2)
(2)
(2,3)
Bank 0
Bank 1
Bank 2
Bank 3
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All unbanked
SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh are
banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register
(BSR) bits.
3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented reg-
ister reads ‘0’s.
4: Bank 8 is only implemented on the PIC17C76X devices.
1998-2013 Microchip Technology Inc.
DS30289C-page 47
PIC17C7XX
TABLE 7-3:
SPECIAL FUNCTION REGISTERS
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unbanked
00h
01h
02h
INDF0
FSR0
Uses contents of FSR0 to address Data Memory (not a physical register)
Indirect Data Memory Address Pointer 0
---- ---- ---- ----
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
PCL
Low order 8-bits of PC
(1)
03h
04h
05h
PCLATH
ALUSTA
T0STA
Holding Register for upper 8-bits of PC
0000 0000 uuuu uuuu
1111 xxxx 1111 uuuu
0000 000- 0000 000-
FS3
FS2
FS1
FS0
OV
Z
DC
C
INTEDG
T0SE
T0CS
T0PS3
T0PS2
T0PS1
T0PS0
—
(2)
06h
07h
08h
09h
CPUSTA
INTSTA
INDF1
—
—
STKAV
T0IF
GLINTD
INTF
TO
PD
POR
T0IE
BOR
INTE
--11 11qq --11 qquu
0000 0000 0000 0000
---- ---- ---- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
PEIF
T0CKIF
PEIE
T0CKIE
Uses contents of FSR1 to address Data Memory (not a physical register)
Indirect Data Memory Address Pointer 1
Working Register
FSR1
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
TMR0 Register; Low Byte
TMR0 Register; High Byte
Low Byte of Program Memory Table Pointer
High Byte of Program Memory Table Pointer
Bank Select Register
Bank 0
RA5/TX1/ RA4/RX1/ RA3/SDI/ RA2/SS/
(4,6)
10h
PORTA
RBPU
—
RA1/T0CKI RA0/INT 0-xx 11xx 0-uu 11uu
CK1
Data Direction Register for PORTB
DT1
SDA
SCL
11h
12h
DDRB
1111 1111 1111 1111
RB7/
SDO
RB6/
SCK
RB5/
RB4/
RB3/
RB2/
RB1/
CAP2
RB0/
CAP1
(4)
PORTB
xxxx xxxx uuuu uuuu
TCLK3
TCLK12
PWM2
PWM1
13h
14h
15h
16h
17h
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
SPEN
RX9
SREN
CREN
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x 0000 -00u
xxxx xxxx uuuu uuuu
0000 --1x 0000 --1u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
Serial Port Receive Register
CSRC TX9 TXEN
SYNC
Serial Port Transmit Register (for USART1)
Baud Rate Generator Register (for USART1)
Bank 1
(5)
10h
11h
12h
DDRC
Data Direction Register for PORTC
1111 1111 1111 1111
(4,5)
PORTC
RC7/AD7 RC6/AD6 RC5/AD5 RC4/AD4 RC3/AD3 RC2/AD2 RC1/AD1 RC0/AD0 xxxx xxxx uuuu uuuu
(5)
DDRD
Data Direction Register for PORTD
1111 1111 1111 1111
RD1/AD9 RD0/AD8 xxxx xxxx uuuu uuuu
---- 1111 ---- 1111
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
(4,5)
13h
14h
15h
PORTD
(5)
DDRE
Data Direction Register for PORTE
RE3/
CAP4
(4,5)
PORTE
—
—
—
—
RE2/WR
RE1/OE
RE0/ALE
---- xxxx ---- uuuu
16h
17h
PIR1
PIE1
RBIF
RBIE
TMR3IF
TMR3IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CA2IF
CA2IE
CA1IF
CA1IE
TX1IF
TX1IE
RC1IF
RC1IE
x000 0010 u000 0010
0000 0000 0000 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0', q= value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6: On any device RESET, these pins are configured as inputs.
DS30289C-page 48
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 7-3:
SPECIAL FUNCTION REGISTERS (CONTINUED)
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
10h
11h
12h
13h
14h
15h
16h
17h
TMR1
TMR2
Timer1’s Register
Timer2’s Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR3L
TMR3H
PR1
Timer3’s Register; Low Byte
Timer3’s Register; High Byte
Timer1’s Period Register
Timer2’s Period Register
PR2
PR3L/CA1L
PR3H/CA1H
Timer3’s Period Register - Low Byte/Capture1 Register; Low Byte
Timer3’s Period Register - High Byte/Capture1 Register; High Byte
Bank 3
10h
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
DC1
DC1
DC9
DC9
DC0
DC0
DC8
DC8
—
TM2PW2
DC7
—
—
—
—
—
—
—
—
—
—
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
11h
12h
DC6
DC6
DC5
DC5
DC4
DC4
DC3
DC3
DC2
DC2
13h
DC7
14h
Capture2 Low Byte
Capture2 High Byte
15h
CA2H
16h
TCON1
CA2ED1 CA2ED0 CA1ED1
CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Bank 4
10h
PIR2
SSPIF
SSPIE
—
BCLIF
BCLIE
—
ADIF
ADIE
—
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
—
TX2IF
TX2IE
—
RC2IF
RC2IE
—
000- 0010 000- 0010
000- 0000 000- 0000
---- ---- ---- ----
0000 -00x 0000 -00u
xxxx xxxx uuuu uuuu
0000 --1x 0000 --1u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
11h
PIE2
12h
Unimplemented
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
—
13h
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
14h
Serial Port Receive Register for USART2
CSRC TX9 TXEN SYNC
15h
—
—
TRMT
TX9D
16h
Serial Port Transmit Register for USART2
Baud Rate Generator for USART2
17h
Bank 5:
10h
DDRF
Data Direction Register for PORTF
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
xxxx 0000 uuuu 0000
0000 -0-0 0000 -0-0
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
(4)
11h
12h
13h
PORTF
DDRG
Data Direction Register for PORTG
RG7/
RG6/
RG5/
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
(4)
PORTG
TX2/CK2 RX2/DT2
PWM3
14h
15h
16h
17h
ADCON0
ADCON1
ADRESL
ADRESH
CHS3
CHS2
CHS1
ADFM
CHS0
—
—
GO/DONE
PCFG2
—
ADON
ADCS1
ADCS0
PCFG3
PCFG1
PCFG0 000- 0000 000- 0000
xxxx xxxx uuuu uuuu
A/D Result Register Low Byte
A/D Result Register High Byte
xxxx xxxx uuuu uuuu
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0', q= value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6: On any device RESET, these pins are configured as inputs.
1998-2013 Microchip Technology Inc.
DS30289C-page 49
PIC17C7XX
TABLE 7-3:
SPECIAL FUNCTION REGISTERS (CONTINUED)
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 6
2
2
10h
11h
SSPADD
SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode 0000 0000 0000 0000
SSPCON1
WCOL
GCEN
SMP
SSPOV
AKSTAT
CKE
SSPEN
AKDT
D/A
CKP
AKEN
P
SSPM3
RCEN
S
SSPM2
PEN
SSPM1
RSEN
UA
SSPM0 0000 0000 0000 0000
12h
SSPCON2
SEN
BF
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
---- ---- ---- ----
---- ---- ---- ----
---- ---- ---- ----
13h
SSPSTAT
R/W
14h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
15h
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16h
17h
Bank 7
10h
PW3DCL
PW3DCH
CA3L
DC1
DC9
DC0
DC8
TM2PW3
DC7
—
—
—
—
—
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
11h
DC6
DC5
DC4
DC3
DC2
12h
Capture3 Low Byte
Capture3 High Byte
Capture4 Low Byte
Capture4 High Byte
13h
CA3H
14h
CA4L
15h
CA4H
16h
TCON3
Unimplemented
—
—
CA4OVF CA3OVF
CA4ED1 CA4ED0 CA3ED1
CA3ED0 PWM3ON -000 0000 -000 0000
17h
—
—
—
—
—
—
—
---- ---- ---- ----
(3)
Bank 8
(3)
10h
DDRH
Data Direction Register for PORTH
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
RH7/
AN15
RH6/
AN14
RH5/
AN13
RH4/
AN12
(3)
(4)
11h
PORTH
RH3
RH2
RH1
RH0
(3)
12h
DDRJ
Data Direction Register for PORTJ
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- ---- ---- ----
---- ---- ---- ----
---- ---- ---- ----
---- ---- ---- ----
(3)
(4)
13h
PORTJ
RJ7
—
RJ6
—
RJ5
—
RJ4
—
RJ3
—
RJ2
—
RJ1
—
RJ0
—
(3)
14h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
(3)
15h
—
—
—
—
—
—
—
—
(3)
16h
—
—
—
—
—
—
—
—
(3)
17h
—
—
—
—
—
—
—
—
Unbanked
18h
19h
PRODL
PRODH
Low Byte of 16-bit Product (8 x 8 Hardware Multiply)
High Byte of 16-bit Product (8 x 8 Hardware Multiply)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0', q= value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6: On any device RESET, these pins are configured as inputs.
DS30289C-page 50
1998-2013 Microchip Technology Inc.
PIC17C7XX
It is recommended, therefore, that only BCF, BSF, SWAPF
and MOVWFinstructions be used to alter the ALUSTA
register, because these instructions do not affect any
status bits. To see how other instructions affect the sta-
tus bits, see the “Instruction Set Summary.”
7.2.2.1
ALU Status Register (ALUSTA)
The ALUSTA register contains the status bits of the
Arithmetic and Logic Unit and the mode control bits for
the indirect addressing register.
As with all the other registers, the ALUSTA register can
be the destination for any instruction. If the ALUSTA
register is the destination for an instruction that affects
the Z, DC, C, or OV bits, then the write to these three
bits is disabled. These bits are set or cleared according
to the device logic. Therefore, the result of an instruc-
tion with the ALUSTA register as destination may be
different than intended.
Note 1: The C and DC bits operate as a borrow and
digit borrow bit, respectively, in subtraction.
See the SUBLWand SUBWFinstructions for
examples.
2: The overflow bit will be set if the 2’s comple-
ment result exceeds +127, or is less than -128.
The Arithmetic and Logic Unit (ALU) is capable of car-
rying out arithmetic or logical operations on two oper-
For example, the CLRF ALUSTA, Finstruction will clear
the upper four bits and set the Z bit. This leaves the
ALUSTA register as 0000u1uu(where u= unchanged).
ands, or
a single operand. All single operand
instructions operate either on the WREG register, or
the given file register. For two operand instructions, one
of the operands is the WREG register and the other is
either a file register, or an 8-bit immediate constant.
REGISTER 7-1: ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)
R/W-1
FS3
R/W-1
FS2
R/W-1
FS1
R/W-1
FS0
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7-6
bit 5-4
bit 3
FS3:FS2: FSR1 Mode Select bits
00= Post auto-decrement FSR1 value
01= Post auto-increment FSR1 value
1x= FSR1 value does not change
FS1:FS0: FSR0 Mode Select bits
00= Post auto-decrement FSR0 value
01= Post auto-increment FSR0 value
1x= FSR0 value does not change
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWFand ADDLWinstructions.
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
Note: For borrow, the polarity is reversed.
C: Carry/borrow bit
bit 0
For ADDWFand ADDLWinstructions. Note that a subtraction is executed by adding the two’s
complement of the second operand.
For rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the
source register.
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result
Note: For borrow, the polarity is reversed.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
1998-2013 Microchip Technology Inc.
DS30289C-page 51
PIC17C7XX
logic. Therefore, the result of an instruction with the
CPUSTA register as destination may be different than
intended.
7.2.2.2
CPU Status Register (CPUSTA)
The CPUSTA register contains the status and control
bits for the CPU. This register has a bit that is used to
globally enable/disable interrupts. If only a specific
interrupt is desired to be enabled/disabled, please refer
to the Interrupt Status (INTSTA) register and the
Peripheral Interrupt Enable (PIE) registers. The
CPUSTA register also indicates if the stack is available
and contains the Power-down (PD) and Time-out (TO)
bits. The TO, PD, and STKAV bits are not writable.
These bits are set and cleared according to device
The POR bit allows the differentiation between a
Power-on Reset, external MCLR Reset, or a WDT
Reset. The BOR bit indicates if a Brown-out Reset
occurred.
Note 1: The BOR status bit is a don’t care and is
not necessarily predictable if the Brown-out
circuit is disabled (when the BODEN bit in
the Configuration word is programmed).
REGISTER 7-2: CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U-0
—
U-0
—
R-1
STKAV
R/W-1
GLINTD
R-1
TO
R-1
PD
R/W-0
POR
R/W-1
BOR
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as '0'
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh 0h
(stack overflow).
1= Stack is available
0= Stack is full, or a stack overflow may have occurred (once this bit has been cleared by a
stack overflow, only a device RESET will set this bit)
bit 4
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits
set can cause an interrupt.
1= Disable all interrupts
0= Enables all unmasked interrupts
bit 3
bit 2
bit 1
bit 0
TO: WDT Time-out Status bit
1= After power-up, by a CLRWDTinstruction, or by a SLEEPinstruction
0= A Watchdog Timer time-out occurred
PD: Power-down Status bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set by software)
BOR: Brown-out Reset Status bit
When BODEN Configuration bit is set (enabled):
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set by software)
When BODEN Configuration bit is clear (disabled):
Don’t care
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
DS30289C-page 52
1998-2013 Microchip Technology Inc.
PIC17C7XX
7.2.2.3
TMR0 Status/Control Register
(T0STA)
This register contains various control bits. Bit7
(INTEDG) is used to control the edge upon which a sig-
nal on the RA0/INT pin will set the RA0/INT interrupt
flag. The other bits configure Timer0, it’s prescaler and
clock source.
REGISTER 7-3: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W-0
INTEDG
R/W-0
T0SE
R/W-0
T0CS
R/W-0
T0PS3
R/W-0
T0PS2
R/W-0
T0PS1
R/W-0
T0PS0
U-0
—
bit 7
bit 0
bit 7
bit 6
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
T0SE: Timer0 External Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0 (External Clock):
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or sets a T0CKIF bit
When T0CS = 1 (Internal Clock):
Don’t care
bit 5
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for Timer0.
1 = Internal instruction clock cycle (TCY)
0 = External clock input on the T0CKI pin
bit 4-1
T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for Timer0.
T0PS3:T0PS0
Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
bit 0
Unimplemented: Read as '0'
Legend:
R = Readable bit
- n = Value at POR Reset
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
1998-2013 Microchip Technology Inc.
DS30289C-page 53
PIC17C7XX
7.3
Stack Operation
7.4
Indirect Addressing
PIC17C7XX devices have a 16 x 16-bit hardware stack
(Figure 7-1). The stack is not part of either the program
or data memory space, and the stack pointer is neither
readable nor writable. The PC (Program Counter) is
“PUSH’d” onto the stack when a CALL or LCALL
instruction is executed, or an interrupt is acknowl-
edged. The stack is “POP’d” in the event of a RETURN,
RETLW, or a RETFIEinstruction execution. PCLATH is
not affected by a “PUSH” or a “POP” operation.
Indirect addressing is a mode of addressing data mem-
ory where the data memory address in the instruction
is not fixed. That is, the register that is to be read or
written can be modified by the program. This can be
useful for data tables in the data memory. Figure 7-6
shows the operation of indirect addressing. This
depicts the moving of the value to the data memory
address specified by the value of the FSR register.
Example 7-1 shows the use of indirect addressing to
clear RAM in a minimum number of instructions. A sim-
ilar concept could be used to move a defined number
of bytes (block) of data to the USART transmit register
(TXREG). The starting address of the block of data to
be transmitted could easily be modified by the program.
The stack operates as a circular buffer, with the stack
pointer initialized to '0' after all RESETS. There is a
stack available bit (STKAV) to allow software to ensure
that the stack will not overflow. The STKAV bit is set
after a device RESET. When the stack pointer equals
Fh, STKAV is cleared. When the stack pointer rolls over
from Fh to 0h, the STKAV bit will be held clear until a
device RESET.
FIGURE 7-6:
INDIRECTADDRESSING
RAM
Note 1: There is not a status bit for stack under-
flow. The STKAV bit can be used to detect
the underflow which results in the stack
pointer being at the Top-of-Stack.
Instruction
Executed
Opcode
Address
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW and RETFIE instruc-
tions, or the vectoring to an interrupt
vector.
8
File = INDFx
8
8
Instruction
Fetched
3: After a RESET, if a “POP” operation
occurs before a “PUSH” operation, the
STKAV bit will be cleared. This will
appear as if the stack is full (underflow
has occurred). If a “PUSH” operation
occurs next (before another “POP”), the
STKAV bit will be locked clear. Only a
device RESET will cause this bit to set.
FSR
Opcode
File
7.4.1
INDIRECT ADDRESSING
REGISTERS
The PIC17C7XX has four registers for indirect address-
ing. These registers are:
After the device is “PUSH’d” sixteen times (without a
“POP”), the seventeenth push overwrites the value
from the first push. The eighteenth push overwrites the
second push (and so on).
• INDF0 and FSR0
• INDF1 and FSR1
Registers INDF0 and INDF1 are not physically imple-
mented. Reading or writing to these registers activates
indirect addressing, with the value in the corresponding
FSR register being the address of the data. The FSR is
an 8-bit register and allows addressing anywhere in the
256-byte data memory address range. For banked
memory, the bank of memory accessed is specified by
the value in the BSR.
If file INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if INDF0
(or INDF1) is written to indirectly, the operation will be
equivalent to a NOP, and the status bits are not affected.
DS30289C-page 54
1998-2013 Microchip Technology Inc.
PIC17C7XX
7.4.2
INDIRECT ADDRESSING
OPERATION
7.5
Table Pointer (TBLPTRL and
TBLPTRH)
The indirect addressing capability has been enhanced
over that of the PIC16CXX family. There are two control
bits associated with each FSR register. These two bits
configure the FSR register to:
File registers TBLPTRL and TBLPTRH form a 16-bit
pointer to address the 64K program memory space.
The table pointer is used by instructions TABLWTand
TABLRD.
• Auto-decrement the value (address) in the FSR
after an indirect access
The TABLRDand the TABLWTinstructions allow trans-
fer of data between program and data space. The table
pointer serves as the 16-bit address of the data word
within the program memory. For a more complete
description of these registers and the operation of
Table Reads and Table Writes, see Section 8.0.
• Auto-increment the value (address) in the FSR
after an indirect access
• No change to the value (address) in the FSR after
an indirect access
These control bits are located in the ALUSTA register.
The FSR1 register is controlled by the FS3:FS2 bits
and FSR0 is controlled by the FS1:FS0 bits.
7.6
Table Latch (TBLATH, TBLATL)
The table latch (TBLAT) is a 16-bit register, with
TBLATH and TBLATL referring to the high and low
bytes of the register. It is not mapped into data or pro-
gram memory. The table latch is used as a temporary
holding latch during data transfer between program
and data memory (see TABLRD, TABLWT, TLRD and
TLWT instruction descriptions). For a more complete
description of these registers and the operation of
Table Reads and Table Writes, see Section 8.0.
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the
ALUSTA register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
If the FSR register contains a value of 0h, an indirect
read will read 0h (Zero bit is set) while an indirect write
will be equivalent to a NOP(status bits are not affected).
Indirect addressing allows single cycle data transfers
within the entire data space. This is possible with the
use of the MOVPFand MOVFPinstructions, where either
'p' or 'f' is specified as INDF0(or INDF1).
If the source or destination of the indirect address is in
banked memory, the location accessed will be deter-
mined by the value in the BSR.
A simple program to clear RAM from 20h - FFh is
shown in Example 7-1.
EXAMPLE 7-1:
INDIRECT ADDRESSING
MOVLW 0x20
MOVWF FSR0
;
; FSR0 = 20h
BCF
BSF
BCF
ALUSTA, FS1 ; Increment FSR
ALUSTA, FS0 ; after access
ALUSTA, C
; C = 0
MOVLW END_RAM + 1
LP CLRF INDF0, F
CPFSEQ FSR0
;
; Addr(FSR) = 0
; FSR0 = END_RAM+1?
; NO, clear next
; YES, All RAM is
; cleared
GOTO
LP
:
:
1998-2013 Microchip Technology Inc.
DS30289C-page 55
PIC17C7XX
Using Figure 7-7, the operations of the PC and
PCLATH for different instructions are as follows:
7.7
Program Counter Module
The Program Counter (PC) is a 16-bit register. PCL, the
low byte of the PC, is mapped in the data memory. PCL
is readable and writable just as is any other register.
PCH is the high byte of the PC and is not directly
addressable. Since PCH is not mapped in data or pro-
gram memory, an 8-bit register PCLATH (PC high
latch) is used as a holding latch for the high byte of the
PC. PCLATH is mapped into data memory. The user
can read or write PCH through PCLATH.
a) LCALLinstructions:
An 8-bit destination address is provided in the
instruction (opcode). PCLATH is unchanged.
PCLATH PCH
Opcode<7:0> PCL
b) Read instructions on PCL:
Any instruction that reads PCL.
PCL data bus ALU or destination
PCH PCLATH
The 16-bit wide PC is incremented after each instruc-
tion fetch during Q1 unless:
c) Write instructions on PCL:
Any instruction that writes to PCL.
8-bit data data bus PCL
PCLATH PCH
• Modified by a GOTO, CALL, LCALL, RETURN,
RETLW, or RETFIEinstruction
• Modified by an interrupt response
• Due to destination write to PCL by an instruction
d) Read-Modify-Write instructions on PCL:
“Skips” are equivalent to a forced NOP cycle at the
skipped address.
Any instruction that does a read-write-modify
operation on PCL, such as ADDWF PCL.
Figure 7-7 and Figure 7-8 show the operation of the
program counter for various situations.
Read:
Write:
PCL data bus ALU
8-bit result data bus PCL
PCLATH PCH
FIGURE 7-7:
PROGRAM COUNTER
OPERATION
e) RETURNinstruction:
Stack<MRU> PC<15:0>
Internal Data Bus <8>
Using Figure 7-8, the operation of the PC and PCLATH
for GOTOand CALLinstructions is as follows:
8
CALL, GOTOinstructions:
A 13-bit destination address is provided in the
instruction (opcode).
PCLATH
8
Opcode<12:0> PC<12:0>
PC<15:13> PCLATH<7:5>
Opcode<12:8> PCLATH<4:0>
8
PCH
PCL
FIGURE 7-8:
PROGRAM COUNTER
USING THE CALLAND
GOTOINSTRUCTIONS
The read-modify-write only affects the PCL with the
result. PCH is loaded with the value in the PCLATH. For
example, ADDWF PCL will result in a jump within the
current page. If PC = 03F0h, WREG = 30h and
PCLATH = 03h before instruction, PC = 0320h after the
instruction. To accomplish a true 16-bit computed jump,
the user needs to compute the 16-bit destination
address, write the high byte to PCLATH and then write
the low value to PCL.
15
13 12
8 7
0
From Instruction
5
PC<15:13>
3
The following PC related operations do not change
PCLATH:
8
4
5
7
0
PCLATH
a) LCALL, RETLW, and RETFIEinstructions.
b) Interrupt vector is forced onto the PC.
8
c) Read-modify-write instructions on PCL
15
0
8 7
(e.g. BSF PCL).
PCL
PCH
DS30289C-page 56
1998-2013 Microchip Technology Inc.
PIC17C7XX
bank in order to address all peripherals related to a sin-
gle task. To assist this, a MOVLB bankinstruction has
been included in the instruction set.
7.8
Bank Select Register (BSR)
The BSR is used to switch between banks in the data
memory area (Figure 7-9). In the PIC17C7XX devices,
the entire byte is implemented. The lower nibble is
used to select the peripheral register bank. The upper
nibble is used to select the general purpose memory
bank.
The need for a large general purpose memory space
dictated a general purpose RAM banking scheme. The
upper nibble of the BSR selects the currently active
general purpose RAM bank. To assist this, a MOVLR
bank instruction has been provided in the instruction
set.
All the Special Function Registers (SFRs) are mapped
into the data memory space. In order to accommodate
the large number of registers, a banking scheme has
been used. A segment of the SFRs, from address 10h
to address 17h, is banked. The lower nibble of the bank
select register (BSR) selects the currently active
“peripheral bank.” Effort has been made to group the
peripheral registers of related functionality in one bank.
However, it will still be necessary to switch from bank to
If the currently selected bank is not implemented (such
as Bank 13), any read will read all '0's. Any write is
completed to the bit bucket and the ALU status bits will
be set/cleared as appropriate.
Note: Registers in Bank 15 in the Special Func-
tion Register area, are reserved for
Microchip use. Reading of registers in this
bank may cause random values to be read.
FIGURE 7-9:
BSR OPERATION
BSR
7
4 3
0
(2)
(1)
Address
Range
4
5
6
7
0
1
2
3
8
15
(Peripheral)
Banks
SFR
10h
17h
Bank 4 Bank 5 Bank 6 Bank 7
Bank 0 Bank 1 Bank 2 Bank 3
Bank 8 Bank 15
0
1
2
15
3
4
(RAM)
GPR
20h
FFh
Banks
Bank 0 Bank 1 Bank 2
Bank 3
Bank 15
Bank 4
Note 1: For the SFRs only Banks 0 through 8 are implemented. Selection of an unimplemented bank is not recommended.
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
2: For the GPRs, Bank 3 is unimplemented on the PIC17C752 and the PIC17C762. Selection of an unimplemented bank
is not recommended.
3: SFR Bank 8 is only implemented on the PIC17C76X.
1998-2013 Microchip Technology Inc.
DS30289C-page 57
PIC17C7XX
NOTES:
DS30289C-page 58
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 8-2:
TABLWTINSTRUCTION
OPERATION
8.0
TABLE READS AND TABLE
WRITES
The PIC17C7XX has four instructions that allow the
processor to move data from the data memory space to
the program memory space, and vice versa. Since the
program memory space is 16-bits wide and the data
memory space is 8-bits wide, two operations are
required to move 16-bit values to/from the data
memory.
TABLE POINTER
TBLPTRH
TBLPTRL
TABLATL
TABLE LATCH (16-bit)
TABLATH
The TLWT t,fand TABLWT t,i,finstructions are
used to write data from the data memory space to the
program memory space. The TLRD t,fand TABLRD
t,i,finstructions are used to write data from the pro-
gram memory space to the data memory space.
3
3
TABLWT 1,i,f
TABLWT 0,i,f
Data
Memory
Program Memory
The program memory can be internal or external. For
the program memory access to be external, the device
needs to be operating in Microprocessor or Extended
Microcontroller mode.
f
1
Figure 8-1 through Figure 8-4 show the operation of
these four instructions. The steps show the sequence
of operation.
Prog-Mem
(TBLPTR)
2
FIGURE 8-1:
TLWTINSTRUCTION
OPERATION
TABLE POINTER
TBLPTRH
TBLPTRL
TABLATL
TABLE LATCH (16-bit)
TABLATH
Step 1: 8-bit value from register 'f', loaded into the high or low
byte in TABLAT (16-bit).
2: 16-bit TABLAT value written to address Program Memory
(TBLPTR).
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
TLWT 1,f
TLWT 0,f
Program Memory
Data
Memory
f
1
Step 1: 8-bit value from register 'f', loaded into the high or low
byte in TABLAT (16-bit).
1998-2013 Microchip Technology Inc.
DS30289C-page 59
PIC17C7XX
FIGURE 8-3:
TLRDINSTRUCTION
OPERATION
FIGURE 8-4:
TABLRDINSTRUCTION
OPERATION
TABLE POINTER
TABLE POINTER
TBLPTRH
TBLPTRH
TBLPTRL
TABLATL
TBLPTRL
TABLE LATCH (16-bit)
TABLATH
TABLE LATCH (16-bit)
TABLATH
TABLATL
TLRD 1,f
TLRD 0,f
3
3
TABLRD 1,i,f
TABLRD 0,i,f
Data
Memory
Program Memory
Data
Memory
Program Memory
f
1
f
1
Prog-Mem
(TBLPTR)
2
Step 1: 8-bit value from TABLAT (16-bit) high or low byte,
loaded into register 'f'.
Step 1: 8-bit value from TABLAT (16-bit) high or low byte,
loaded into register 'f'.
2: 16-bit value at Program Memory (TBLPTR), loaded into
TABLAT register.
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
DS30289C-page 60
1998-2013 Microchip Technology Inc.
PIC17C7XX
8.1.1
TERMINATING LONG WRITES
8.1
Table Writes to Internal Memory
An interrupt source or RESET are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the interrupt
enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execu-
tion is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specifi-
cation #D114). Having only one interrupt enabled to ter-
minate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write, the interrupt flag of the
highest priority enabled interrupt, will terminate the long
write and automatically be cleared.
The sequence of events for programming an internal
program memory location should be:
Note 1: If an interrupt is pending, the TABLWTis
aborted (a NOPis executed). The highest
priority pending interrupt, from the
T0CKI, RA0/INT, or TMR0 sources that
is enabled, has its flag cleared.
1. Disable all interrupt sources, except the source
to terminate EPROM program write.
2. Raise MCLR/VPP pin to the programming
voltage.
2: If the interrupt is not being used for the
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it termi-
nate the long write prematurely.
3. Clear the WDT.
4. Do the table write. The interrupt will terminate
the long write.
5. Verify the memory location (table read).
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
Note 1: Programming requirements must be
met. See timing specification in electrical
specifications for the desired device.
Violating these specifications (including
temperature) may result in EPROM
locations that are not fully programmed
and may lose their state over time.
The GLINTD bit determines whether the program will
branch to the interrupt vector when the long write is ter-
minated. If GLINTD is clear, the program will vector, if
GLINTD is set, the program will not vector to the
interrupt address.
2: If the VPP requirement is not met, the
table write is a 2-cycle write and the pro-
gram memory is unchanged.
TABLE 8-1:
INTERRUPT - TABLE WRITE INTERACTION
Interrupt
Source
Enable
Bit
Flag
Bit
GLINTD
Action
RA0/INT,
TMR0,
T0CKI
0
1
1
Terminate long table write (to internal program memory),
branch to interrupt vector (branch clears flag bit).
None.
0
1
1
1
0
1
0
x
1
None.
Terminate long table write, do not branch to interrupt
vector (flag is automatically cleared).
Peripheral
0
0
1
1
1
1
0
1
1
0
x
1
Terminate long table write, branch to interrupt vector.
None.
None.
Terminate long table write, do not branch to interrupt
vector (flag remains set).
1998-2013 Microchip Technology Inc.
DS30289C-page 61
PIC17C7XX
EXAMPLE 8-1:
TABLE WRITE
8.2
Table Writes to External Memory
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
CLRWDT
; Clear WDT
HIGH (TBL_ADDR) ; Load the Table
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
;
;
;
address
HIGH (DATA)
1, WREG
LOW (DATA)
; Load HI byte
in TABLATH
; Load LO byte
8.2.1
TABLE WRITE CODE
;
MOVLW
TABLWT 0,0,WREG
The “i” operand of the TABLWTinstruction can specify
that the value in the 16-bit TBLPTR register is automat-
ically incremented (for the next write). In Example 8-1,
the TBLPTR register is not automatically incremented.
;
;
;
;
in TABLATL
and write to
program memory
(Ext. SRAM)
FIGURE 8-5:
TABLWTWRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
PC+1
TBL
Data out
PC+2
Instruction
Fetched
TABLWT
INST (PC+1)
INST (PC+2)
INST (PC+1)
Instruction
Executed
INST (PC-1)
TABLWT cycle1
TABLWT cycle2
Data write cycle
ALE
OE
'1'
WR
Note: If external write and GLINTD = '1' and Enable bit = '1', then when '1' Flag bit, do table write.
The highest pending interrupt is cleared.
DS30289C-page 62
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 8-6:
CONSECUTIVE TABLWTWRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TBL1
Data out 1
Data out 2
PC
PC+2
PC+3
AD15:AD0
PC+1
TBL2
Instruction
Fetched
TABLWT1
TABLWT2
INST (PC+2)
INST (PC+3)
INST (PC+2)
Instruction
Executed
TABLWT1 cycle1
TABLWT2 cycle2
Data write cycle
INST (PC-1)
TABLWT1 cycle2 TABLWT2 cycle1
Data write cycle
ALE
OE
WR
1998-2013 Microchip Technology Inc.
DS30289C-page 63
PIC17C7XX
EXAMPLE 8-2:
TABLE READ
8.3
Table Reads
The table read allows the program memory to be read.
This allows constants to be stored in the program mem-
ory space and retrieved into data memory when
needed. Example 8-2 reads the 16-bit value at program
memory address TBLPTR. After the dummy byte has
been read from the TABLATH, the TABLATH is loaded
with the 16-bit data from program memory address
TBLPTR and then increments the TBLPTR value. The
first read loads the data into the latch and can be con-
sidered a dummy read (unknown data loaded into 'f').
INDF0 should be configured for either auto-increment
or auto-decrement.
MOVLW
MOVWF
MOVLW
MOVWF
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
;
;
;
address
TABLRD 0, 1, DUMMY ; Dummy read,
;
;
Updates TABLATH
Increments TBLPTR
TLRD
1, INDF0
; Read HI byte
of TABLATH
TABLRD 0, 1, INDF0 ; Read LO byte
;
;
;
;
of TABLATL and
Update TABLATH
Increment TBLPTR
FIGURE 8-7:
TABLRDTIMING
Q4
Q4
Q4
Q1 Q2
Q3
Q4
Q1 Q2
Q1 Q2
Q1 Q2
Q3
Q3
Q3
AD15:AD0
PC
PC+1
TBL
Data in
PC+2
Instruction
Fetched
INST (PC+2)
INST (PC+1)
TABLRD
INST (PC+1)
Instruction
Executed
INST (PC-1)
TABLRD cycle2
Data read cycle
TABLRD cycle1
ALE
OE
'1'
WR
FIGURE 8-8:
TABLRDTIMING (CONSECUTIVE TABLRDINSTRUCTIONS)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Data in 1
PC
TBL1
PC+2
TBL2 Data in 2
AD15:AD0
PC+1
PC+3
Instruction
Fetched
TABLRD1
INST (PC+2)
INST (PC+3)
INST (PC+2)
TABLRD2
Instruction
Executed
INST (PC-1) TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1
Data read cycle
TABLRD2 cycle2
Data read cycle
ALE
OE
'1'
WR
DS30289C-page 64
1998-2013 Microchip Technology Inc.
PIC17C7XX
8.4
Operation with External Memory
Interface
When the table reads/writes are accessing external
memory (via the external system interface bus), the
table latch for the table reads is different from the table
latch for the table writes (see Figure 8-9).
This means that you cannot do a TABLRDinstruction,
and use the values that were loaded into the table
latches for a TABLWT instruction. Any table write
sequence should use both the TLWT and then the
TABLWTinstructions.
FIGURE 8-9:
ACCESSINGEXTERNALMEMORYWITHTABLRDANDTABLWTINSTRUCTIONS
TABLPTR
Program Memory
(In External Memory Space)
TABLATH (for Table Reads)
TABLRD
TABLATH (for Table Writes)
TABLWT
1998-2013 Microchip Technology Inc.
DS30289C-page 65
PIC17C7XX
NOTES:
DS30289C-page 66
1998-2013 Microchip Technology Inc.
PIC17C7XX
Example 9-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
9.0
HARDWARE MULTIPLIER
All PIC17C7XX devices have an 8 x 8 hardware multi-
plier included in the ALU of the device. By making the
multiply a hardware operation, it completes in a single
instruction cycle. This is an unsigned multiply that gives
a 16-bit result. The result is stored into the 16-bit
Product register (PRODH:PRODL). The multiplier does
not affect any flags in the ALUSTA register.
EXAMPLE 9-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MOVFP
MULWF
ARG1, WREG
ARG2
;
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
; ARG1 * ARG2 ->
;
PRODH:PRODL
• Higher computational throughput
• Reduces code size requirements for multiply algo-
rithms
EXAMPLE 9-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
MOVFP
MULWF
ARG1, WREG
ARG2
; ARG1 * ARG2 ->
PRODH:PRODL
Table 9-1 shows a performance comparison between
PIC17CXXX devices using the single cycle hardware
multiply and performing the same function without the
hardware multiply.
;
BTFSC
SUBWF
ARG2, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
Example 9-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
MOVFP
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
TABLE 9-1:
PERFORMANCE COMPARISON
Multiply Method
Program
Memory
(Words)
Time
@ 33 MHz @ 16 MHz @ 8 MHz
Cycles
(Max)
Routine
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
13
1
69
1
8.364 s
0.121 s
—
17.25 s
0.25 s
—
34.50 s
0.50 s
—
Without hardware multiply
Hardware multiply
—
6
—
6
0.727 s
29.333 s
2.91 s
30.788 s
4.36 s
1.50 s
60.50 s
6.0 s
63.50 s
9.0 s
3.0 s
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
121.0 s
12.0 s
127.0 s
18.0 s
Without hardware multiply
Hardware multiply
1998-2013 Microchip Technology Inc.
DS30289C-page 67
PIC17C7XX
Example 9-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 9-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers,
RES3:RES0.
EXAMPLE 9-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFP
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
PRODH:PRODL
EQUATION 9-1:
16 x 16 UNSIGNED
MULTIPLICATION
MOVPF
MOVPF
PRODH, RES1 ;
PRODL, RES0 ;
ALGORITHM
ARG1H:ARG1L ARG2H:ARG2L
(ARG1H ARG2H 216)
(ARG1H ARG2L 28)
(ARG1L ARG2H 28)
(ARG1L ARG2L)
;
;
MOVFP
MULWF
ARG1H, WREG
ARG2H
RES3:RES0
=
=
; ARG1H * ARG2H ->
PRODH:PRODL
+
+
+
;
MOVPF
MOVPF
PRODH, RES3 ;
PRODL, RES2 ;
MOVFP
MULWF
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
;
MOVFP
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
DS30289C-page 68
1998-2013 Microchip Technology Inc.
PIC17C7XX
Example 9-4 shows the sequence to do a 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 9-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVFP
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
PRODH:PRODL
MOVPF
MOVPF
PRODH, RES1 ;
PRODL, RES0 ;
EQUATION 9-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
MOVFP
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
PRODH:PRODL
;
RES3:RES0
MOVPF
MOVPF
PRODH, RES3 ;
PRODL, RES2 ;
= ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216)
(ARG1H ARG2L 28)
+
+
+
+
+
MOVFP
MULWF
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
;
PRODH:PRODL
(ARG1L ARG2H 28)
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
PRODH, WREG ;
RES2, F
WREG, F
RES3, F
(ARG1L ARG2L)
; Add cross
products
(-1 ARG2H<7> ARG1H:ARG1L 216)
(-1 ARG1H<7> ARG2H:ARG2L 216)
;
;
;
ADDWFC
;
MOVFP
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
ADDWFC
;
;
BTFSS
GOTO
MOVFP
SUBWF
MOVFP
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG ;
RES2
ARG1H, WREG ;
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
SIGN_ARG1
BTFSS
GOTO
ARG1H, 7
CONT_CODE
; ARG1H:ARG1L neg?
; no, done
MOVFP
SUBWF
MOVFP
SUBWFB
;
ARG2L, WREG ;
RES2
ARG2H, WREG ;
RES3
;
CONT_CODE
:
1998-2013 Microchip Technology Inc.
DS30289C-page 69
PIC17C7XX
NOTES:
DS30289C-page 70
1998-2013 Microchip Technology Inc.
PIC17C7XX
When some of these peripheral modules are turned on,
the port pin will automatically configure to the alternate
function. The modules that do this are:
10.0 I/O PORTS
PIC17C75X devices have seven I/O ports, PORTA
through PORTG. PIC17C76X devices have nine I/O
ports, PORTA through PORTJ. PORTB through
PORTJ have a corresponding Data Direction Register
(DDR), which is used to configure the port pins as
inputs or outputs. Some of these ports pins are multi-
plexed with alternate functions.
• PWM Module
• SSP Module
• USART/SCI Module
When a pin is automatically configured as an output by
a peripheral module, the pins data direction (DDR) bit
is unknown. After disabling the peripheral module, the
user should re-initialize the DDR bit to the desired con-
figuration.
PORTC, PORTD, and PORTE are multiplexed with the
system bus. These pins are configured as the system
bus when the device’s configuration bits are selected to
Microprocessor or Extended Microcontroller modes. In
the two other microcontroller modes, these pins are
general purpose I/O.
The other peripheral modules (which require an input)
must have their data direction bits configured appropri-
ately.
PORTA, PORTB, PORTE<3>, PORTF, PORTG and
the upper four bits of PORTH are multiplexed with the
peripheral features of the device. These peripheral fea-
tures are:
Note: A pin that is a peripheral input, can be con-
figured as an output (DDRx<y> is cleared).
The peripheral events will be determined
by the action output on the port pin.
• Timer Modules
• Capture Modules
• PWM Modules
• USART/SCI Modules
• SSP Module
When the device enters the “RESET state”, the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impedance inputs. The RESET state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
• A/D Module
• External Interrupt pin
1998-2013 Microchip Technology Inc.
DS30289C-page 71
PIC17C7XX
Example 10-1 shows an instruction sequence to initial-
ize PORTA. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.1 PORTA Register
PORTA is a 6-bit wide latch. PORTA does not have a
corresponding Data Direction Register (DDR). Upon a
device RESET, the PORTA pins are forced to be hi-
impedance inputs. For the RA4 and RA5 pins, the
peripheral module controls the output. When a device
RESET occurs, the peripheral module is disabled, so
these pins are forced to be hi-impedance inputs.
EXAMPLE 10-1:
INITIALIZING PORTA
MOVLB
MOVLW 0xF3
0
; Select Bank 0
;
Reading PORTA reads the status of the pins.
MOVWF PORTA ; Initialize PORTA
RA<3:2> are output low
The RA0 pin is multiplexed with the external interrupt,
INT. The RA1 pin is multiplexed with TMR0 clock input,
RA2 and RA3 are multiplexed with the SSP functions,
and RA4 and RA5 are multiplexed with the USART1
functions. The control of RA2, RA3, RA4 and RA5 as
outputs, is automatically configured by their multi-
plexed peripheral module when the module is enabled.
;
;
;
;
RA<5:4> and RA<1:0>
are inputs
(outputs floating)
FIGURE 10-1:
RA0 AND RA1 BLOCK
DIAGRAM
10.1.1
USING RA2, RA3 AS OUTPUTS
The RA2 and RA3 pins are open drain outputs. To use
the RA2 and/or the RA3 pin(s) as output(s), simply
write to the PORTA register the desired value. A '0' will
cause the pin to drive low, while a '1' will cause the pin
to float (hi-impedance). An external pull-up resistor
should be used to pull the pin high. Writes to the RA2
and RA3 pins will not affect the other PORTA pins.
Data Bus
Note: When using the RA2 or RA3 pin(s) as out-
put(s), read-modify-write instructions (such
as BCF, BSF, BTG) on PORTA are not
recommended.
RD_PORTA
(Q2)
Note: Input pins have protection diodes to VDD and VSS.
Such operations read the port pins, do the
desired operation, and then write this value
to the data latch. This may inadvertently
cause the RA2 or RA3 pins to switch from
input to output (or vice-versa).
FIGURE 10-2:
RA2 BLOCK DIAGRAM
Peripheral Data In
D
Q
Data Bus
To avoid this possibility, use a shadow reg-
ister for PORTA. Do the bit operations on
this shadow register and then move it to
PORTA.
EN
RD_PORTA
(Q2)
Q
D
WR_PORTA
(Q4)
Q
1
0
CK
SCL Out
2
I C Mode Enable
Note: I/O pin has protection diodes to VSS.
DS30289C-page 72
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 10-3:
RA3 BLOCK DIAGRAM
FIGURE 10-4:
RA4 AND RA5 BLOCK
DIAGRAM
Peripheral Data In
Serial Port Input Signal
D
Q
Data Bus
EN
Data Bus
RD_PORTA
(Q2)
RD_PORTA
(Q2)
Q
D
Serial Port Output Signals
WR_PORTA
(Q4)
OE = SPEN,SYNC,TXEN, CREN, SREN for RA4
OE = SPEN (SYNC+SYNC, CSRC) for RA5
Q
CK
SDA Out
'1'
Note: I/O pins have protection diodes to VDD and VSS.
SSP Mode
Note: I/O pin has protection diodes to VSS.
TABLE 10-1: PORTA FUNCTIONS
Name
RA0/INT
Bit0 Buffer Type
Function
bit0
bit1
ST
ST
Input or external interrupt input.
RA1/T0CKI
Input or clock input to the TMR0 timer/counter and/or an external interrupt
input.
RA2/SS/SCL
RA3/SDI/SDA
RA4/RX1/DT1
RA5/TX1/CK1
bit2
bit3
bit4
bit5
ST
ST
ST
ST
Input/output or slave select input for the SPI, or clock input for the I2C bus.
Output is open drain type.
Input/output or data input for the SPI, or data for the I2C bus.
Output is open drain type.
Input or USART1 Asynchronous Receive input, or
USART1 Synchronous Data input/output.
Input or USART1 Asynchronous Transmit output, or
USART1 Synchronous Clock input/output.
RBPU
bit7
—
Control bit for PORTB weak pull-ups.
Legend: ST = Schmitt Trigger input
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH PORTA
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
RA5/
RA4/
RA3/
RA2/
10h, Bank 0
PORTA(1)
RBPU
—
RA1/T0CKI RA0/INT
0-xx 11xx 0-uu 11uu
TX1/CK1 RX1/DT1 SDI/SDA SS/SCL
05h, Unbanked T0STA
INTEDG T0SE
T0CS
SREN
TXEN
T0PS3
CREN
SYNC
T0PS2
—
T0PS1
FERR
—
T0PS0
OERR
TRMT
—
0000 000- 0000 000-
0000 -00x 0000 -00u
0000 --1x 0000 --1u
13h, Bank 0
15h, Bank 0
RCSTA1
TXSTA1
SPEN
CSRC
RX9
TX9
RX9D
TX9D
—
Legend: x= unknown, u= unchanged, -= unimplemented, reads as '0'. Shaded cells are not used by PORTA.
Note 1: On any device RESET, these pins are configured as inputs.
1998-2013 Microchip Technology Inc.
DS30289C-page 73
PIC17C7XX
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt by:
10.2 PORTB and DDRB Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is DDRB. A '1' in DDRB
configures the corresponding port pin as an input. A '0'
in the DDRB register configures the corresponding port
pin as an output. Reading PORTB reads the status of
the pins, whereas writing to PORTB will write to the port
latch.
a) Read-Write PORTB (such as: MOVPF PORTB,
PORTB). This will end the mismatch condition.
b) Then, clear the RBIF bit.
A mismatch condition will continue to set the RBIF bit.
Reading, then writing PORTB, will end the mismatch
condition and allow the RBIF bit to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (PORTA<7>) bit. The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are enabled on
any RESET.
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on this port, allows easy
interface to a keypad and makes it possible for wake-
up on key depression. For an example, refer to Appli-
cation Note AN552, “Implementing Wake-up on
Keystroke.”
PORTB also has an interrupt-on-change feature. Only
pins configured as inputs can cause this interrupt to
occur (i.e., any RB7:RB0 pin configured as an output is
excluded from the interrupt-on-change comparison).
The input pins (of RB7:RB0) are compared with the
value in the PORTB data latch. The “mismatch” outputs
of RB7:RB0 are OR’d together to set the PORTB Inter-
rupt Flag bit, RBIF (PIR1<7>).
The interrupt-on-change feature is recommended for
wake-up on operations, where PORTB is only used for
the interrupt-on-change feature and key depression
operations.
Note: On a device RESET, the RBIF bit is inde-
terminate, since the value in the latch may
be different than the pin.
FIGURE 10-5:
BLOCK DIAGRAM OF RB5:RB4 AND RB1:RB0 PORT PINS
Peripheral Data In
RBPU
(PORTA<7>)
Weak
Pull-up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
WR_PORTB (Q4)
CK
D
Port
Q
Data
CK
Note: I/O pins have protection diodes to VDD and VSS.
DS30289C-page 74
1998-2013 Microchip Technology Inc.
PIC17C7XX
Example 10-2 shows an instruction sequence to initial-
ize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
EXAMPLE 10-2:
INITIALIZING PORTB
MOVLB
CLRF
0
; Select Bank 0
PORTB, F ; Init PORTB by clearing
output data latches
; Value used to initialize
data direction
; Set RB<3:0> as inputs
;
MOVLW 0xCF
MOVWF DDRB
;
;
;
RB<5:4> as outputs
RB<7:6> as inputs
FIGURE 10-6:
BLOCK DIAGRAM OF RB3:RB2 PORT PINS
Peripheral Data In
RBPU (PORTA<7>)
Weak
Pull-up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
R
D
Port
Q
Data
WR_PORTB (Q4)
CK
Peripheral_output
Peripheral_enable
Note: I/O pins have protection diodes to VDD and VSS.
1998-2013 Microchip Technology Inc.
DS30289C-page 75
PIC17C7XX
FIGURE 10-7:
BLOCK DIAGRAM OF RB6 PORT PIN
Peripheral Data In
(PORTA<7>)
RBPU
Weak
Pull-up
Match Signal
from other
port pins
RBIF
D
Q
Data Bus
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
Port
P
N
Data
0
1
Q
D
WR_PORTB (Q4)
CK
Q
SPI Output
SPI Output Enable
Note: I/O pin has protection diodes to Vdd and Vss.
FIGURE 10-8:
BLOCK DIAGRAM OF RB7 PORT PIN
Peripheral Data In
(PORTA<7>)
RBPU
Weak
Pull-up
Match Signal
from other
port pins
RBIF
D
Q
Data Bus
EN
RD_DDRB (Q2)
RD_PORTB (Q2)
D
Q
OE
WR_DDRB (Q4)
CK
Port
P
N
0
1
Data
SS Output Disable
WR_PORTB (Q4)
Q
D
CK
Q
SPI Output
SPI Output Enable
Note: I/O pin has protection diodes to VDD and VSS.
DS30289C-page 76
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 10-3: PORTB FUNCTIONS
Name
Bit
Buffer Type
Function
RB0/CAP1
bit0
ST
Input/output or the Capture1 input pin. Software programmable weak
pull-up and interrupt-on-change features.
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6/SCK
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
Input/output or the Capture2 input pin. Software programmable weak
pull-up and interrupt-on-change features.
Input/output or the PWM1 output pin. Software programmable weak pull-up
and interrupt-on-change features.
Input/output or the PWM2 output pin. Software programmable weak pull-up
and interrupt-on-change features.
Input/output or the external clock input to Timer1 and Timer2. Software
programmable weak pull-up and interrupt-on-change features.
Input/output or the external clock input to Timer3. Software programmable
weak pull-up and interrupt-on-change features.
Input/output or the Master/Slave clock for the SPI. Software programmable
weak pull-up and interrupt-on-change features.
RB7/SDO
Input/output or data output for the SPI. Software programmable weak
pull-up and interrupt-on-change features.
Legend: ST = Schmitt Trigger input
TABLE 10-4: REGISTERS/BITS ASSOCIATED WITH PORTB
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
12h, Bank 0
PORTB
RB7/
SDO
RB6/
SCK
RB5/
TCLK3
RB4/
TCLK12
RB3/
PWM2
RB2/
PWM1
RB1/
CAP2
RB0/
CAP1
xxxx xxxx uuuu uuuu
11h, Bank 0
10h, Bank 0
DDRB
Data Direction Register for PORTB
1111 1111 1111 1111
0-xx 11xx 0-uu 11uu
PORTA
—
RA5/
RA4/
RA3/
RA2/
RA1/T0CKI RA0/INT
RBPU
TX1/CK1 RX1/DT1 SDI/SDA SS/SCL
06h, Unbanked CPUSTA
07h, Unbanked INTSTA
—
—
STKAV
GLINTD
TO
PD
POR
T0IE
BOR
INTE
--11 11qq --11 qquu
0000 0000 0000 0000
x000 0010 u000 0010
0000 0000 0000 0000
PEIF
RBIF
RBIE
T0CKIF
TMR3IF
TMR3IE
T0IF
INTF
PEIE
CA2IF
CA2IE
T16
T0CKIE
CA1IF
CA1IE
16h, Bank 1
17h, Bank 1
16h, Bank 3
17h, Bank 3
PIR1
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CA1ED0
TX1IF
TX1IE
RC1IF
RC1IE
PIE1
TCON1
TCON2
CA2ED1 CA2ED0 CA1ED1
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
0000 0000 0000 0000
Legend:
x= unknown, u= unchanged, - = unimplemented, read as '0', q = value depends on condition. Shaded cells are not used by PORTB.
1998-2013 Microchip Technology Inc.
DS30289C-page 77
PIC17C7XX
Example 10-3 shows an instruction sequence to initial-
ize PORTC. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.3 PORTC and DDRC Registers
PORTC is an 8-bit bi-directional port. The correspond-
ing data direction register is DDRC. A '1' in DDRC con-
figures the corresponding port pin as an input. A '0' in
the DDRC register configures the corresponding port
pin as an output. Reading PORTC reads the status of
the pins, whereas writing to PORTC will write to the port
latch. PORTC is multiplexed with the system bus.
When operating as the system bus, PORTC is the low
order byte of the address/data bus (AD7:AD0). The tim-
ing for the system bus is shown in the Electrical Speci-
fications section.
EXAMPLE 10-3:
INITIALIZING PORTC
MOVLB
CLRF
1
; Select Bank 1
PORTC, F ; Initialize PORTC data
; latches before setting
; the data direction reg
MOVLW
MOVWF
0xCF
DDRC
; Value used to initialize
; data direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
Note: This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a
general purpose I/O.
FIGURE 10-9:
BLOCK DIAGRAM OF RC7:RC0 PORT PINS
To D_Bus IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTC
WR_PORTC
Port
D
D
0
1
Q
Data
CK
RD_DDRC
WR_DDRC
Q
R
CK
S
EX_EN
DATA/ADDR_OUT
System Bus
Control
DRV_SYS
Note: I/O pins have protection diodes to VDD and VSS.
DS30289C-page 78
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 10-5: PORTC FUNCTIONS
Name
RC0/AD0
Bit
Buffer Type
Function
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
Legend: TTL = TTL input
TABLE 10-6: REGISTERS/BITS ASSOCIATED WITH PORTC
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
11h, Bank 1 PORTC RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
10h, Bank 1 DDRC Data Direction Register for PORTC
Legend: x= unknown, u= unchanged
1998-2013 Microchip Technology Inc.
DS30289C-page 79
PIC17C7XX
Example 10-4 shows an instruction sequence to initial-
ize PORTD. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.4 PORTD and DDRD Registers
PORTD is an 8-bit bi-directional port. The correspond-
ing data direction register is DDRD. A '1' in DDRD con-
figures the corresponding port pin as an input. A '0' in
the DDRD register configures the corresponding port
pin as an output. Reading PORTD reads the status of
the pins, whereas writing to PORTD will write to the port
latch. PORTD is multiplexed with the system bus.
When operating as the system bus, PORTD is the high
order byte of the address/data bus (AD15:AD8). The
timing for the system bus is shown in the Electrical
Specifications section.
EXAMPLE 10-4:
INITIALIZING PORTD
MOVLB
CLRF
1
; Select Bank 1
PORTD, F ; Initialize PORTD data
; latches before setting
; the data direction reg
MOVLW
MOVWF
0xCF
DDRD
; Value used to initialize
; data direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Note: This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a gen-
eral purpose I/O.
FIGURE 10-10:
BLOCK DIAGRAM OF RD7:RD0 PORT PINS (IN I/O PORT MODE)
To D_Bus IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTD
Port
D
D
0
1
Q
Data
WR_PORTD
CK
RD_DDRD
WR_DDRD
Q
R
CK
S
EX_EN
DATA/ADDR_OUT
DRV_SYS
System Bus
Control
Note: I/O pins have protection diodes to VDD and VSS.
DS30289C-page 80
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 10-7: PORTD FUNCTIONS
Name
Bit
Buffer Type
Function
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Input/output or system bus address/data pin.
Legend: TTL = TTL input
TABLE 10-8: REGISTERS/BITS ASSOCIATED WITH PORTD
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
13h, Bank 1 PORTD
12h, Bank 1 DDRD
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
Data Direction Register for PORTD
Legend: x= unknown, u= unchanged
1998-2013 Microchip Technology Inc.
DS30289C-page 81
PIC17C7XX
Example 10-5 shows an instruction sequence to initial-
ize PORTE. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.5 PORTE and DDRE Register
PORTE is a 4-bit bi-directional port. The corresponding
data direction register is DDRE. A '1' in DDRE config-
ures the corresponding port pin as an input. A '0' in the
DDRE register configures the corresponding port pin
as an output. Reading PORTE reads the status of the
pins, whereas writing to PORTE will write to the port
latch. PORTE is multiplexed with the system bus.
When operating as the system bus, PORTE contains
the control signals for the address/data bus
(AD15:AD0). These control signals are Address Latch
Enable (ALE), Output Enable (OE) and Write (WR).
The control signals OE and WR are active low signals.
The timing for the system bus is shown in the Electrical
Specifications section.
EXAMPLE 10-5:
INITIALIZING PORTE
MOVLB
CLRF
1
; Select Bank 1
PORTE, F ; Initialize PORTE data
; latches before setting
; the data direction
; register
MOVLW
MOVWF
0x03
; Value used to initialize
; data direction
; Set RE<1:0> as inputs
; RE<3:2> as outputs
; RE<7:4> are always
; read as '0'
DDRE
Note: Three pins of this port are configured as
the system bus when the device’s configu-
ration bits are selected to Microprocessor
or Extended Microcontroller modes. The
other pin is a general purpose I/O or
Capture4 pin. In the two other micro-
controller modes, RE2:RE0 are general
purpose I/O pins.
FIGURE 10-11:
BLOCK DIAGRAM OF RE2:RE0 (IN I/O PORT MODE)
Data Bus
TTL
Input
Buffer
RD_PORTE
WR_PORTE
Port
D
D
0
1
Q
Data
CK
RD_DDRE
WR_DDRE
Q
R
CK
S
EX_EN
CNTL
System Bus
Control
DRV_SYS
Note: I/O pins have protection diodes to VDD and VSS.
DS30289C-page 82
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 10-12:
BLOCK DIAGRAM OF RE3/CAP4 PORT PIN
Peripheral In
Data Bus
D
Q
EN
VDD
P
RD_PORTE
WR_PORTE
Q
D
D
Port
Data
CK
Q
N
RD_DDRE
WR_DDRE
Q
CK
S
Q
Note: I/O pin has protection diodes to VDD and VSS.
TABLE 10-9: PORTE FUNCTIONS
Name
RE0/ALE
Bit
Buffer Type
Function
bit0
bit1
TTL
TTL
Input/output or system bus Address Latch Enable (ALE) control pin.
Input/output or system bus Output Enable (OE) control pin.
RE1/OE
RE2/WR
bit2
bit3
TTL
ST
Input/output or system bus Write (WR) control pin.
Input/output or Capture4 input pin.
RE3/CAP4
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-10: REGISTERS/BITS ASSOCIATED WITH PORTE
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
15h, Bank 1 PORTE
—
—
—
—
RE3/CAP4 RE2/WR RE1/OE RE0/ALE
---- xxxx
---- 1111
---- uuuu
---- 1111
14h, Bank 1 DDRE
14h, Bank 7 CA4L
Data Direction Register for PORTE
Capture4 Low Byte
xxxx xxxx
xxxx xxxx
-000 0000
uuuu uuuu
uuuu uuuu
-000 0000
15h, Bank 7 CA4H
16h, Bank 7 TCON3
Capture4 High Byte
—
CA4OVF CA3OVF CA4ED1 CA4ED0
CA3ED1 CA3ED0 PWM3ON
Legend:
x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.
1998-2013 Microchip Technology Inc.
DS30289C-page 83
PIC17C7XX
Example 10-6 shows an instruction sequence to initial-
ize PORTF. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.6 PORTF and DDRF Registers
PORTF is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRF. A '1' in DDRF
configures the corresponding port pin as an input. A '0'
in the DDRF register configures the corresponding port
pin as an output. Reading PORTF reads the status of
the pins, whereas writing to PORTF will write to the
respective port latch.
EXAMPLE 10-6:
INITIALIZING PORTF
MOVLB
MOVWF 0x0E
MOVWF ADCON1
5
; Select Bank 5
; Configure PORTF as
; Digital
All eight bits of PORTF are multiplexed with 8 channels
of the 10-bit A/D converter.
CLRF
PORTF, F ; Initialize PORTF data
;
;
;
latches before
the data direction
register
Upon RESET, the entire Port is automatically config-
ured as analog inputs and must be configured in soft-
ware to be a digital I/O.
MOVLW
MOVWF
0x03
DDRF
; Value used to init
data direction
; Set RF<1:0> as inputs
;
;
RF<7:2> as outputs
FIGURE 10-13:
BLOCK DIAGRAM OF RF7:RF0
Data Bus
D
Q
Q
VDD
P
WR PORTF
CK
Data Latch
I/O pin
D
Q
Q
N
WR DDRF
CK
VSS
DDRF Latch
ST
Input
Buffer
RD DDRF
Q
D
EN
RD PORTF
VAIN
PCFG3:PCFG0
CHS3:CHS0
To other pads
To other pads
Note: I/O pins have protection diodes to VDD and VSS.
DS30289C-page 84
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 10-11: PORTF FUNCTIONS
Name
RF0/AN4
Bit
Buffer Type
Function
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output or analog input 4.
Input/output or analog input 5.
Input/output or analog input 6.
Input/output or analog input 7.
Input/output or analog input 8.
Input/output or analog input 9.
RF1/AN5
RF2/AN6
RF3/AN7
RF4/AN8
RF5/AN9
RF6/AN10
RF7/AN11
Input/output or analog input 10.
Input/output or analog input 11.
Legend: ST = Schmitt Trigger input
TABLE 10-12: REGISTERS/BITS ASSOCIATED WITH PORTF
Value on
MCLR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
WDT
10h, Bank 5 DDRF
11h, Bank 5 PORTF
Data Direction Register for PORTF
1111 1111 1111 1111
0000 0000 0000 0000
RF7/
RF6/
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
AN11
AN10
15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM
—
PCFG3 PCFG2 PCFG1 PCFG0
000- 0000 000- 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTF.
1998-2013 Microchip Technology Inc.
DS30289C-page 85
PIC17C7XX
Example 10-7 shows the instruction sequence to initial-
ize PORTG. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLBinstruction to load the
BSR register for bank selection.
10.7 PORTG and DDRG Registers
PORTG is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is DDRG. A '1' in
DDRG configures the corresponding port pin as an
input. A '0' in the DDRG register configures the corre-
sponding port pin as an output. Reading PORTG reads
the status of the pins, whereas writing to PORTG will
write to the port latch.
EXAMPLE 10-7:
INITIALIZING PORTG
MOVLB
5
; Select Bank 5
MOVLW 0x0E
MOVPF WREG, ADCON1 ; digital
; Configure PORTG as
The lower four bits of PORTG are multiplexed with four
channels of the 10-bit A/D converter.
CLRF
PORTG, F
; Initialize PORTG data
;
;
;
latches before
the data direction
register
The remaining bits of PORTG are multiplexed with
peripheral output and inputs. RG4 is multiplexed with
the CAP3 input, RG5 is multiplexed with the PWM3
output, RG6 and RG7 are multiplexed with the
USART2 functions.
MOVLW
MOVWF
0x03
DDRG
; Value used to init
data direction
; Set RG<1:0> as inputs
;
Upon RESET, RG3:RG0 is automatically configured as
analog inputs and must be configured in software to be
a digital I/O.
;
RG<7:2> as outputs
FIGURE 10-14:
BLOCK DIAGRAM OF RG3:RG0
Data Bus
D
Q
Q
VDD
WR PORTG
CK
P
Data Latch
I/O pin
D
Q
Q
N
WR DDRG
CK
VSS
DDRG Latch
ST
Input
Buffer
RD DDRG
Q
D
EN
RD PORTG
VAIN
PCFG3:PCFG0
To other pads
To other pads
CHS3:CHS0
Note: I/O pins have protection diodes to VDD and VSS.
DS30289C-page 86
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 10-15:
RG4 BLOCK DIAGRAM
Peripheral Data In
Data Bus
Q
D
EN
RD_PORTG
WR_PORTG
D
D
VDD
P
CK
Q
RD_DDRG
WR_DDRG
Q
Q
N
CK
Note: I/O pins have protection diodes to VDD and VSS.
FIGURE 10-16:
RG7:RG5 BLOCK DIAGRAM
Peripheral Data In
Data Bus
D
Q
EN
RD_PORTG
WR_PORTG
D
D
Q
Port
Data
VDD
P
CK
1
0
Q
RD_DDRG
WR_DDRG
Q
Q
N
CK
R
OUTPUT
OUTPUT ENABLE
Note: I/O pins have protection diodes to VDD and VSS.
1998-2013 Microchip Technology Inc.
DS30289C-page 87
PIC17C7XX
TABLE 10-13: PORTG FUNCTIONS
Name
RG0/AN3
Bit
Buffer Type
Function
bit0
bit1
bit2
bit3
bit4
bit5
bit6
ST
ST
ST
ST
ST
ST
ST
Input/output or analog input 3.
Input/output or analog input 2.
RG1/AN2
RG2/AN1/VREF-
RG3/AN0/VREF+
RG4/CAP3
Input/output or analog input 1 or the ground reference voltage.
Input/output or analog input 0 or the positive reference voltage.
Input/output or the Capture3 input pin.
RG5/PWM3
Input/output or the PWM3 output pin.
RG6/RX2/DT2
Input/output or the USART2 (SCI) Asynchronous Receive or USART2
(SCI) Synchronous Data.
RG7/TX2/CK2
bit7
ST
Input/output or the USART2 (SCI) Asynchronous Transmit or USART2
(SCI) Synchronous Clock.
Legend: ST = Schmitt Trigger input
TABLE 10-14: REGISTERS/BITS ASSOCIATED WITH PORTG
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
12h, Bank 5
13h, Bank 5
DDRG
Data Direction Register for PORTG
1111 1111
xxxx 0000
1111 1111
uuuu 0000
PORTG
RG7/
RG6/
RG5/
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
TX2/CK2 RX2/DT2
PWM3
15h, Bank 5
Legend:
ADCON1
ADCS1 ADCS0
ADFM
—
PCFG3
PCFG2
PCFG1 PCFG0
000- 0000
000- 0000
x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTG.
DS30289C-page 88
1998-2013 Microchip Technology Inc.
PIC17C7XX
EXAMPLE 10-8:
INITIALIZING PORTH
10.8 PORTH and DDRH Registers
(PIC17C76X only)
MOVLB
8
; Select Bank 8
; Configure PORTH as
; digital
MOVLW 0x0E
MOVPF ADCON1
PORTH is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is DDRH. A '1' in
DDRH configures the corresponding port pin as an
input. A '0' in the DDRH register configures the corre-
sponding port pin as an output. Reading PORTH reads
the status of the pins, whereas writing to PORTH will
write to the respective port latch.
CLRF
PORTH, F ; Initialize PORTH data
;
;
;
latches before
the data direction
register
MOVLW
MOVWF
0x03
DDRH
; Value used to init
data direction
; Set RH<1:0> as inputs
;
The upper four bits of PORTH are multiplexed with
4 channels of the 10-bit A/D converter.
;
RH<7:2> as outputs
The remaining bits of PORTH are general purpose I/O.
Upon RESET, RH7:RH4 are automatically configured
as analog inputs and must be configured in software to
be a digital I/O.
FIGURE 10-17:
BLOCK DIAGRAM OF RH7:RH4
Data Bus
D
Q
Q
VDD
WR PORTH
WR DDRH
CK
P
Data Latch
I/O pin
D
Q
Q
N
CK
VSS
DDRH Latch
ST
Input
Buffer
RD DDRH
Q
D
EN
RD PORT
PCFG3:PCFG0
To other pads
VAIN
CHS3:CHS0
To other pads
Note: I/O pins have protection diodes to VDD and VSS.
1998-2013 Microchip Technology Inc.
DS30289C-page 89
PIC17C7XX
FIGURE 10-18:
RH3:RH0 BLOCK DIAGRAM
Data Bus
Q
D
EN
RD_PORTH
WR_PORTH
D
D
VDD
P
CK
CK
Q
RD_DDRH
WR_DDRH
Q
Q
N
Note: I/O pins have protection diodes to VDD and VSS.
TABLE 10-15: PORTH FUNCTIONS
Name
Bit
Buffer Type
Function
RH0
RH1
RH2
RH3
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output.
Input/output.
Input/output.
Input/output.
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
Input/output or analog input 12.
Input/output or analog input 13.
Input/output or analog input 14.
Input/output or analog input 15.
Legend: ST = Schmitt Trigger input
TABLE 10-16: REGISTERS/BITS ASSOCIATED WITH PORTH
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
10h, Bank 8
11h, Bank 8
DDRH
Data Direction Register for PORTH
1111 1111 1111 1111
0000 xxxx 0000 uuuu
000- 0000 000- 0000
RH7/
AN15
RH6/
AN14
RH5/
AN13
RH4/
AN12
PORTH
RH3
RH2
RH1
RH0
15h, Bank 5
Legend:
ADCON1
ADCS1
ADCS0
ADFM
—
PCFG3
PCFG2
PCFG1
PCFG0
x= unknown, u= unchanged
DS30289C-page 90
1998-2013 Microchip Technology Inc.
PIC17C7XX
EXAMPLE 10-9:
INITIALIZING PORTJ
10.9 PORTJ and DDRJ Registers
(PIC17C76X only)
MOVLB
CLRF
8
; Select Bank 8
PORTJ, F ; Initialize PORTJ data
; latches before setting
; the data direction
; register
PORTJ is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is DDRJ. A '1' in DDRJ
configures the corresponding port pin as an input. A '0'
in the DDRJ register configures the corresponding port
pin as an output. Reading PORTJ reads the status of
the pins, whereas writing to PORTJ will write to the
respective port latch.
MOVLW
MOVWF
0xCF
; Value used to initialize
; data direction
; Set RJ<3:0> as inputs
; RJ<5:4> as outputs
; RJ<7:6> as inputs
DDRJ
PORTJ is a general purpose I/O port.
FIGURE 10-19:
PORTJ BLOCK DIAGRAM
Data Bus
Q
D
EN
RD_PORTJ
WR_PORTJ
D
D
VDD
P
CK
CK
Q
RD_DDRJ
WR_DDRJ
Q
Q
N
Note: I/O pins have protection diodes to VDD and VSS.
1998-2013 Microchip Technology Inc.
DS30289C-page 91
PIC17C7XX
TABLE 10-17: PORTJ FUNCTIONS
Name
Bit
Buffer Type
Function
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Legend: ST = Schmitt Trigger input
TABLE 10-18: REGISTERS/BITS ASSOCIATED WITH PORTJ
Value on,
POR,
BOR
MCLR,
WDT
Address
Name Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
12h, Bank 8 DDRJ Data Direction Register for PORTJ
13h, Bank 8 PORTJ RJ7 RJ6 RJ5 RJ4 RJ3
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
RJ2
RJ1
RJ0
Legend: x= unknown, u= unchanged
DS30289C-page 92
1998-2013 Microchip Technology Inc.
PIC17C7XX
EXAMPLE 10-10: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
10.10 I/O Programming Considerations
10.10.1 BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read, followed by a write operation. For example, the
BCF and BSF instructions read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB, will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g. bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the content
of the data latch may now be unknown.
; Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
; PORTB<7:6> have pull-ups and are
; not connected to other circuitry
;
;
;
;
PORT latch PORT pins
---------- ---------
BCF
BCF
PORTB, 7
PORTB, 6
; 01pp pppp
; 10pp pppp
11pp pppp
11pp pppp
BCF
BCF
DDRB, 7
DDRB, 6
; 10pp pppp
; 10pp pppp
11pp pppp
10pp pppp
;
; Note that the user may have expected the
; pin values to be 00pp pppp. The 2nd BCF
; caused RB7 to be latched as the pin value
; (High).
Reading a port reads the values of the port pins. Writing
to the port register writes the value to the port latch.
When using read-modify-write instructions (BCF, BSF,
BTG, etc.) on a port, the value of the port pins is read,
the desired operation is performed with this value and
the value is then written to the port latch.
Note: A pin actively outputting a Low or High
should not be driven from external devices,
in order to change the level on this pin (i.e.,
“wired-or”, “wired-and”). The resulting high
output currents may damage the device.
Example 10-10 shows the possible effect of two
sequential read-modify-write instructions on an I/O port.
1998-2013 Microchip Technology Inc.
DS30289C-page 93
PIC17C7XX
Figure 10-21 shows the I/O model which causes this
situation. As the effective capacitance (C) becomes
larger, the rise/fall time of the I/O pin increases. As the
device frequency increases, or the effective capaci-
tance increases, the possibility of this subsequent
PORTx read-modify-write instruction issue increases.
This effective capacitance includes the effects of the
board traces.
10.10.2 SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 10-20). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load depen-
dent) before executing the instruction that reads the
values on that I/O port. Otherwise, the previous state of
that pin may be read into the CPU, rather than the
“new” state. When in doubt, it is better to separate
these instructions with a NOP, or another instruction
not accessing this I/O port.
The best way to address this is to add a series resistor
at the I/O pin. This resistor allows the I/O pin to get to
the desired level before the next instruction.
The use of NOP instructions between the subsequent
PORTx read-modify-write instructions, is a lower cost
solution, but has the issue that the number of NOP
instructions is dependent on the effective capacitance
C and the frequency of the device.
FIGURE 10-20:
SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q4
Q3
Q1 Q2
Q3
Q3
Q3
Q1 Q2
Q1 Q2
Q1 Q2
Note:
PC + 3
PC
PC + 1
PC + 2
This example shows a write to PORTB,
followed by a read from PORTB.
Instruction
Fetched
MOVWF PORTB
write to
PORTB
MOVF PORTB,W
NOP
NOP
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Instruction
Executed
MOVWF PORTB
write to
PORTB
MOVF PORTB,W
NOP
FIGURE 10-21:
PIC17CXXX
I/O CONNECTION ISSUES
BSF PORTx, PINy
Q2 Q3 Q4
BSF PORTx, PINz
Q1
Q2
Q3
Q4
Q1
I/O
VIL
(1)
C
PORTx, PINy
Read PORTx, PINy as low
Note 1: This is not a capacitor to ground, but the effective
BSF PORTx, PINz clears the value
to be driven on the PORTx, PINy pin.
capacitive loading on the trace.
DS30289C-page 94
1998-2013 Microchip Technology Inc.
PIC17C7XX
11.3 Timer2 Overview
11.0 OVERVIEW OF TIMER
RESOURCES
The Timer2 module is an 8-bit timer/counter with an 8-
bit period register (PR2). When the TMR2 value rolls
over from the period match value to 0h, the TMR2IF
flag is set and an interrupt will be generated, if enabled.
In Counter mode, the clock comes from the RB4/
TCLK12 pin, which can also provide the clock for the
Timer1 module.
The PIC17C7XX has four timer modules. Each module
can generate an interrupt to indicate that an event has
occurred. These timers are called:
• Timer0 - 16-bit timer with programmable 8-bit
prescaler
• Timer1 - 8-bit timer
• Timer2 - 8-bit timer
• Timer3 - 16-bit timer
TMR2 can be concatenated with TMR1 to form a 16-bit
timer. The TMR2 register is the MSB and TMR1 is the
LSB. When in the 16-bit timer mode, there is a corre-
sponding 16-bit period register (PR2:PR1). When the
TMR2:TMR1 value rolls over from the period match
value to 0h, the TMR1IF flag is set and an interrupt will
be generated, if enabled.
For enhanced time base functionality, four input Cap-
tures and three Pulse Width Modulation (PWM) outputs
are possible. The PWMs use the Timer1 and Timer2
resources and the input Captures use the Timer3
resource.
11.4 Timer3 Overview
11.1 Timer0 Overview
The Timer3 module is a 16-bit timer/counter with a 16-
bit period register. When the TMR3H:TMR3L value
rolls over to 0h, the TMR3IF bit is set and an interrupt
will be generated, if enabled. In Counter mode, the
clock comes from the RB5/TCLK3 pin.
The Timer0 module is a simple 16-bit overflow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock.
When Timer0 uses an external clock source, it has the
flexibility to allow user selection of the incrementing
edge, rising or falling.
When operating in the four Capture modes, the period
registers become the second (of four) 16-bit capture
registers.
The Timer0 module also has a programmable pres-
caler. The T0PS3:T0PS0 bits (T0STA<4:1>) determine
the prescale value. TMR0 can increment at the follow-
ing rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128,
1:256.
11.5 Role of the Timer/Counters
The timer modules are general purpose, but have ded-
icated resources associated with them. TImer1 and
Timer2 are the time bases for the three Pulse Width
Modulation (PWM) outputs, while Timer3 is the time
base for the four input captures.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher than the device’s fre-
quency. The maximum external frequency on the
T0CKI pin is 50 MHz, given the high and low time
requirements of the clock.
11.2 Timer1 Overview
The Timer1 module is an 8-bit timer/counter with an 8-
bit period register (PR1). When the TMR1 value rolls
over from the period match value to 0h, the TMR1IF
flag is set and an interrupt will be generated if enabled.
In Counter mode, the clock comes from the RB4/
TCLK12 pin, which can also be selected to be the clock
for the Timer2 module.
TMR1 can be concatenated with TMR2 to form a 16-bit
timer. The TMR1 register is the LSB and TMR2 is the
MSB. When in the 16-bit timer mode, there is a corre-
sponding 16-bit period register (PR2:PR1). When the
TMR2:TMR1 value rolls over from the period match
value to 0h, the TMR1IF flag is set and an interrupt will
be generated, if enabled.
1998-2013 Microchip Technology Inc.
DS30289C-page 95
PIC17C7XX
NOTES:
DS30289C-page 96
1998-2013 Microchip Technology Inc.
PIC17C7XX
12.0 TIMER0
The Timer0 module consists of a 16-bit timer/counter,
TMR0. The high byte is register TMR0H and the low
byte is register TMR0L. A software programmable 8-bit
prescaler makes Timer0 an effective 24-bit overflow
timer. The clock source is software programmable as
either the internal instruction clock, or an external clock
on the RA1/T0CKI pin. The control bits for this module
are in register T0STA (Figure 12-1).
REGISTER 12-1: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W-0
INTEDG
R/W-0
T0SE
R/W-0
T0CS
R/W-0
T0PS3
R/W-0
T0PS2
R/W-0
T0PS1
R/W-0
T0PS0
U-0
—
bit 7
bit 0
bit 7
bit 6
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1= Rising edge of RA0/INT pin generates interrupt
0= Falling edge of RA0/INT pin generates interrupt
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0 (External Clock):
1= Rising edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit
0= Falling edge of RA1/T0CKI pin increments TMR0 and/or sets the T0CKIF bit
When T0CS = 1 (Internal Clock):
Don’t care
bit 5
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for TMR0.
1= Internal instruction clock cycle (TCY)
0= External clock input on the T0CKI pin
bit 4-1
T0PS3:T0PS0: Timer0 Prescale Selection bits
These bits select the prescale value for TMR0.
T0PS3:T0PS0 Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
bit 0
Unimplemented: Read as '0'
Legend:
R = Readable bit
- n = Value at POR Reset
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
1998-2013 Microchip Technology Inc.
DS30289C-page 97
PIC17C7XX
12.1 Timer0 Operation
12.2 Using Timer0 with External Clock
When the T0CS (T0STA<5>) bit is set, TMR0 incre-
ments on the internal clock. When T0CS is clear, TMR0
increments on the external clock (RA1/T0CKI pin). The
external clock edge can be selected in software. When
the T0SE (T0STA<6>) bit is set, the timer will increment
on the rising edge of the RA1/T0CKI pin. When T0SE
is clear, the timer will increment on the falling edge of
the RA1/T0CKI pin. The prescaler can be programmed
to introduce a prescale of 1:1 to 1:256. The timer incre-
ments from 0000h to FFFFh and rolls over to 0000h.
On overflow, the TMR0 Interrupt Flag bit (T0IF) is set.
The TMR0 interrupt can be masked by clearing the cor-
responding TMR0 Interrupt Enable bit (T0IE). The
TMR0 Interrupt Flag bit (T0IF) is automatically cleared
when vectoring to the TMR0 interrupt vector.
When an external clock input is used for Timer0, it is
synchronized with the internal phase clocks. Figure 12-
2 shows the synchronization of the external clock. This
synchronization is done after the prescaler. The output
of the prescaler (PSOUT) is sampled twice in every
instruction cycle to detect a rising or a falling edge. The
timing requirements for the external clock are detailed
in the electrical specification section.
12.2.1
DELAY FROM EXTERNAL CLOCK
EDGE
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time TMR0 is actually
incremented. Figure 12-2 shows that this delay is
between 3TOSC and 7TOSC. Thus, for example, mea-
suring the interval between two edges (e.g. period) will
be accurate within 4TOSC (121 ns @ 33 MHz).
FIGURE 12-1:
TIMER0 MODULE BLOCK DIAGRAM
Interrupt-on-Overflow
sets T0IF
(INTSTA<5>)
Prescaler
(8 Stage
Async Ripple
Counter)
0
1
Synchronization
TMR0H<8> TMR0L<8>
RA1/T0CKI
FOSC/4
PSOUT
T0SE
(T0STA<6>)
4
Q2
Q4
T0PS3:T0PS0
(T0STA<4:1>)
T0CS
(T0STA<5>)
FIGURE 12-2:
TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler
Output
(Note 3)
(Note 2)
(PSOUT)
Sampled
Prescaler
Output
(Note 1)
Increment
TMR0
T0
T0 + 1
T0 + 2
TMR0
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
2: = PSOUT is sampled here.
3: The PSOUT high time is too short and is missed by the sampling circuit.
DS30289C-page 98
1998-2013 Microchip Technology Inc.
PIC17C7XX
12.3.2
WRITING A 16-BIT VALUE TO TMR0
12.3 Read/Write Consideration for
TMR0
Since writing to either TMR0L or TMR0H will effectively
inhibit increment of that half of the TMR0 in the next
cycle (following write), but not inhibit increment of the
other half, the user must write to TMR0L first and
TMR0H second, in two consecutive instructions, as
shown in Example 12-2. The interrupt must be dis-
abled. Any write to either TMR0L or TMR0H clears the
prescaler.
Although TMR0 is a 16-bit timer/counter, only 8-bits at
a time can be read or written during a single instruction
cycle. Care must be taken during any read or write.
12.3.1
READING 16-BIT VALUE
The problem in reading the entire 16-bit value is that
after reading the low (or high) byte, its value may
change from FFh to 00h.
EXAMPLE 12-2:
16-BIT WRITE
Example 12-1 shows a 16-bit read. To ensure a proper
read, interrupts must be disabled during this routine.
BSF
CPUSTA, GLINTD ; Disable interrupts
MOVFP
MOVFP
BCF
RAM_L, TMR0L
RAM_H, TMR0H
;
;
EXAMPLE 12-1:
16-BIT READ
CPUSTA, GLINTD ; Done, enable
interrupts
;
MOVPF
MOVPF
MOVFP
CPFSLT TMR0L
RETURN
MOVPF
MOVPF
RETURN
TMR0L, TMPLO
TMR0H, TMPHI
TMPLO, WREG
;read low tmr0
;read high tmr0
;tmplo wreg
;tmr0l < wreg?
;no then return
;read low tmr0
;read high tmr0
;return
12.4 Prescaler Assignments
Timer0 has an 8-bit prescaler. The prescaler selection
is fully under software control; i.e., it can be changed
“on the fly” during program execution. Clearing the
prescaler is recommended before changing its setting.
The value of the prescaler is “unknown” and assigning
a value that is less than the present value, makes it dif-
ficult to take this unknown time into account.
TMR0L, TMPLO
TMR0H, TMPHI
FIGURE 12-3:
TMR0 TIMING: WRITE HIGH OR LOW BYTE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
PC+1
PC+2
PC+3
PC+4
PC
T0
T0+1
New T0 (NT0)
New T0+1
TMR0L
Fetch
MOVFP W,TMR0L MOVFP TMR0L,W MOVFP TMR0L,W MOVFP TMR0L,W
Instruction
Executed
Write to TMR0L
Read TMR0L
(Value = NT0)
Read TMR0L
(Value = NT0)
Read TMR0L
(Value = NT0 +1)
TMR0H
1998-2013 Microchip Technology Inc.
DS30289C-page 99
PIC17C7XX
FIGURE 12-4:
TMR0 READ/WRITE IN TIMER MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
WR_TRM0L
WR_TMR0H
RD_TMR0L
12
AB
12
13
56
TMR0H
57
58
TMR0L
FE
FF
MOVFP
MOVFP
MOVPF
MOVPF
TMR0L,W
MOVPF
MOVPF
DATAL,TMR0L DATAH,TMR0H
TMR0L,W
TMR0L,W
TMR0L,W
Instruction
Fetched
Write TMR0L Write TMR0H Read TMR0L Read TMR0L Read TMR0L Read TMR0L
Previously
Fetched
Instruction
MOVFP
MOVFP
MOVPF
MOVPF
MOVPF
Instruction
Executed
DATAL,TMR0L DATAH,TMR0H
TMR0L,W
TMR0L,W
TMR0L,W
Write TMR0L Write TMR0H Read TMR0L Read TMR0L Read TMR0L
Note: In this example, old TMR0 value is 12FEh, new value of AB56h is written.
TABLE 12-1: REGISTERS/BITS ASSOCIATED WITH TIMER0
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
05h, Unbanked
06h, Unbanked
07h, Unbanked
0Bh, Unbanked
0Ch, Unbanked
T0STA
INTEDG
—
T0SE
—
T0CS
STKAV
T0IF
T0PS3
GLINTD
INTF
T0PS2
TO
T0PS1
PD
T0PS0
POR
—
0000 000-
--11 11qq
0000 0000
xxxx xxxx
xxxx xxxx
0000 000-
--11 qquu
0000 0000
uuuu uuuu
uuuu uuuu
CPUSTA
INTSTA
TMR0L
TMR0H
BOR
INTE
PEIF
T0CKIF
PEIE
T0CKIE
T0IE
TMR0 Register; Low Byte
TMR0 Register; High Byte
Legend:
x= unknown, u= unchanged, -= unimplemented, read as a '0', q= value depends on condition. Shaded cells are not used by Timer0.
DS30289C-page 100
1998-2013 Microchip Technology Inc.
PIC17C7XX
Six other registers comprise the Capture2, Capture3,
and Capture4 registers (CA2H:CA2L, CA3H:CA3L,
and CA4H:CA4L).
13.0 TIMER1, TIMER2, TIMER3,
PWMS AND CAPTURES
The PIC17C7XX has a wealth of timers and time based
functions to ease the implementation of control applica-
tions. These time base functions include three PWM
outputs and four Capture inputs.
Figure 13-1, Figure 13-2 and Figure 13-3 are the con-
trol registers for the operation of Timer1, Timer2 and
Timer3, as well as PWM1, PWM2, PWM3, Capture1,
Capture2, Capture3 and Capture4.
Timer1 and Timer2 are two 8-bit incrementing timers,
each with an 8-bit period register (PR1 and PR2, respec-
tively) and separate overflow interrupt flags. Timer1 and
Timer2 can operate either as timers (increment on inter-
nal FOSC/4 clock), or as counters (increment on falling
edge of external clock on pin RB4/TCLK12). They are
also software configurable to operate as a single 16-bit
timer/counter. These timers are also used as the time
base for the PWM (Pulse Width Modulation) modules.
Table 13-1 shows the Timer resource requirements for
these time base functions. Each timer is an open
resource so that multiple functions may operate with it.
TABLE 13-1: TIME-BASE FUNCTION/
RESOURCEREQUIREMENTS
Time Base Function
Timer Resource
Timer1
PWM1
Timer3 is a 16-bit timer/counter which uses the TMR3H
and TMR3L registers. Timer3 also has two additional
registers (PR3H/CA1H:PR3L/CA1L) that are config-
urable as a 16-bit period register or a 16-bit capture
register. TMR3 can be software configured to incre-
ment from the internal system clock (FOSC/4), or from
an external signal on the RB5/TCLK3 pin. Timer3 is the
time base for all of the 16-bit captures.
PWM2
Timer1 or Timer2
Timer1 or Timer2
Timer3
PWM3
Capture1
Capture2
Capture3
Capture4
Timer3
Timer3
Timer3
REGISTER 13-1: TCON1 REGISTER (ADDRESS: 16h, BANK 3)
R/W-0
CA2ED1 CA2ED0
R/W-0
R/W-0
CA1ED1
R/W-0
CA1ED0
R/W-0
T16
R/W-0
R/W-0
R/W-0
TMR3CS TMR2CS TMR1CS
bit 7
bit 0
bit 7-6
bit 5-4
CA2ED1:CA2ED0: Capture2 Mode Select bits
00= Capture on every falling edge
01= Capture on every rising edge
10= Capture on every 4th rising edge
11= Capture on every 16th rising edge
CA1ED1:CA1ED0: Capture1 Mode Select bits
00= Capture on every falling edge
01= Capture on every rising edge
10= Capture on every 4th rising edge
11= Capture on every 16th rising edge
bit 3
bit 2
bit 1
bit 0
T16: Timer2:Timer1 Mode Select bit
1= Timer2 and Timer1 form a 16-bit timer
0= Timer2 and Timer1 are two 8-bit timers
TMR3CS: Timer3 Clock Source Select bit
1= TMR3 increments off the falling edge of the RB5/TCLK3 pin
0= TMR3 increments off the internal clock
TMR2CS: Timer2 Clock Source Select bit
1= TMR2 increments off the falling edge of the RB4/TCLK12 pin
0= TMR2 increments off the internal clock
TMR1CS: Timer1 Clock Source Select bit
1= TMR1 increments off the falling edge of the RB4/TCLK12 pin
0= TMR1 increments off the internal clock
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
1998-2013 Microchip Technology Inc.
DS30289C-page 101
PIC17C7XX
REGISTER 13-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3)
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
bit 7
bit 0
bit 7
CA2OVF: Capture2 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(CA2H:CA2L) before the next capture event occurred. The capture register retains the oldest
unread capture value (last capture before overflow). Subsequent capture events will not update
the capture register with the TMR3 value until the capture register has been read (both bytes).
1= Overflow occurred on Capture2 register
0= No overflow occurred on Capture2 register
bit 6
CA1OVF: Capture1 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (PR3H/
CA1H:PR3L/CA1L), before the next capture event occurred. The capture register retains the old-
est unread capture value (last capture before overflow). Subsequent capture events will not
update the capture register with the TMR3 value until the capture register has been read (both
bytes).
1= Overflow occurred on Capture1 register
0= No overflow occurred on Capture1 register
bit 5
bit 4
bit 3
PWM2ON: PWM2 On bit
1=PWM2 is enabled
(The RB3/PWM2 pin ignores the state of the DDRB<3> bit.)
0=PWM2 is disabled
(The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction.)
PWM1ON: PWM1 On bit
1=PWM1 is enabled
(The RB2/PWM1 pin ignores the state of the DDRB<2> bit.)
0=PWM1 is disabled
(The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction.)
CA1/PR3: CA1/PR3 Register Mode Select bit
1=Enables Capture1
(PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without a period register.)
0=Enables the Period register
(PR3H/CA1H:PR3L/CA1L is the Period register for Timer3.)
bit 2
bit 1
TMR3ON: Timer3 On bit
1= Starts Timer3
0= Stops Timer3
TMR2ON: Timer2 On bit
This bit controls the incrementing of the TMR2 register. When TMR2:TMR1 form the 16-bit timer
(T16 is set), TMR2ON must be set. This allows the MSB of the timer to increment.
1= Starts Timer2 (must be enabled if the T16 bit (TCON1<3>) is set)
0= Stops Timer2
bit 0
TMR1ON: Timer1 On bit
When T16 is set (in 16-bit Timer mode):
1= Starts 16-bit TMR2:TMR1
0= Stops 16-bit TMR2:TMR1
When T16 is clear (in 8-bit Timer mode:
1= Starts 8-bit Timer1
0= Stops 8-bit Timer1
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
DS30289C-page 102
1998-2013 Microchip Technology Inc.
PIC17C7XX
REGISTER 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7)
U-0
—
R-0
R-0
R/W-0
CA4ED1 CA4ED0
R/W-0
R/W-0
CA3ED1
R/W-0
CA3ED0 PWM3ON
R/W-0
CA4OVF CA3OVF
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
CA4OVF: Capture4 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(CA4H:CA4L) before the next capture event occurred. The capture register retains the oldest
unread capture value (last capture before overflow). Subsequent capture events will not update
the capture register with the TMR3 value until the capture register has been read (both bytes).
1= Overflow occurred on Capture4 registers
0= No overflow occurred on Capture4 registers
bit 5
CA3OVF: Capture3 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(CA3H:CA3L) before the next capture event occurred. The capture register retains the oldest
unread capture value (last capture before overflow). Subsequent capture events will not update
the capture register with the TMR3 value until the capture register has been read (both bytes).
1= Overflow occurred on Capture3 registers
0= No overflow occurred on Capture3 registers
bit 4-3
bit 2-1
bit 0
CA4ED1:CA4ED0: Capture4 Mode Select bits
00= Capture on every falling edge
01= Capture on every rising edge
10= Capture on every 4th rising edge
11= Capture on every 16th rising edge
CA3ED1:CA3ED0: Capture3 Mode Select bits
00= Capture on every falling edge
01= Capture on every rising edge
10= Capture on every 4th rising edge
11= Capture on every 16th rising edge
PWM3ON: PWM3 On bit
1= PWM3 is enabled (the RG5/PWM3 pin ignores the state of the DDRG<5> bit)
0= PWM3 is disabled (the RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
1998-2013 Microchip Technology Inc.
DS30289C-page 103
PIC17C7XX
Each timer also has a corresponding interrupt enable
bit (TMRxIE). The timer interrupt can be enabled/
disabled by setting/clearing this bit. For peripheral
interrupts to be enabled, the Peripheral Interrupt
Enable bit must be set (PEIE = '1') and global interrupt
must be enabled (GLINTD = '0').
13.1 Timer1 and Timer2
13.1.1
TIMER1, TIMER2 IN 8-BIT MODE
Both Timer1 and Timer2 will operate in 8-bit mode
when the T16 bit is clear. These two timers can be inde-
pendently configured to increment from the internal
instruction cycle clock (TCY), or from an external clock
source on the RB4/TCLK12 pin. The timer clock source
is configured by the TMRxCS bit (x = 1 for Timer1,
or = 2 for Timer2). When TMRxCS is clear, the clock
source is internal and increments once every instruc-
tion cycle (FOSC/4). When TMRxCS is set, the clock
source is the RB4/TCLK12 pin and the counters will
increment on every falling edge of the RB4/TCLK12
pin.
The timers can be turned on and off under software
control. When the timer on control bit (TMRxON) is set,
the timer increments from the clock source. When
TMRxON is cleared, the timer is turned off and cannot
cause the timer interrupt flag to be set.
13.1.1.1
External Clock Input for Timer1 and
Timer2
When TMRxCS is set, the clock source is the RB4/
TCLK12 pin, and the counter will increment on every
falling edge on the RB4/TCLK12 pin. The TCLK12
input is synchronized with internal phase clocks. This
causes a delay from the time a falling edge appears on
TCLK12 to the time TMR1 or TMR2 is actually incre-
mented. For the external clock input timing require-
ments, see the Electrical Specification section.
The timer increments from 00h until it equals the Period
register (PRx). It then resets to 00h at the next incre-
ment cycle. The timer interrupt flag is set when the
timer is reset. TMR1 and TMR2 have individual inter-
rupt flag bits. The TMR1 interrupt flag bit is latched into
TMR1IF and the TMR2 interrupt flag bit is latched into
TMR2IF.
FIGURE 13-1:
TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE
0
1
FOSC/4
RESET
TMR1
Set TMR1IF
(PIR1<4>)
TMR1ON
(TCON2<0>)
Comparatorx8
Equal
TMR1CS
(TCON1<0>)
PR1
RB4/TCLK12
1
0
RESET
Equal
TMR2
Comparatorx8
PR2
FOSC/4
Set TMR2IF
(PIR1<5>)
TMR2ON
(TCON2<1>)
TMR2CS
(TCON1<1>)
DS30289C-page 104
1998-2013 Microchip Technology Inc.
PIC17C7XX
13.1.2
TIMER1 AND TIMER2 IN 16-BIT
MODE
13.1.2.1
External Clock Input for
TMR2:TMR1
When TMR1CS is set, the 16-bit TMR2:TMR1 incre-
ments on the falling edge of clock input TCLK12. The
input on the RB4/TCLK12 pin is sampled and synchro-
nized by the internal phase clocks twice every instruc-
tion cycle. This causes a delay from the time a falling
edge appears on RB4/TCLK12 to the time
TMR2:TMR1 is actually incremented. For the external
clock input timing requirements, see the Electrical
Specification section.
To select 16-bit mode, set the T16 bit. In this mode,
TMR2 and TMR1 are concatenated to form a 16-bit
timer (TMR2:TMR1). The 16-bit timer increments until
it matches the 16-bit period register (PR2:PR1). On the
following timer clock, the timer value is reset to 0h, and
the TMR1IF bit is set.
When selecting the clock source for the 16-bit timer, the
TMR1CS bit controls the entire 16-bit timer and
TMR2CS is a “don’t care”, however, ensure that
TMR2ON is set (allows TMR2 to increment). When
TMR1CS is clear, the timer increments once every
instruction cycle (FOSC/4). When TMR1CS is set, the
timer increments on every falling edge of the RB4/
TCLK12 pin. For the 16-bit timer to increment, both
TMR1ON and TMR2ON bits must be set (Table 13-2).
TABLE 13-2: TURNING ON 16-BIT TIMER
T16 TMR2ON TMR1ON
Result
16-bit timer
1
1
1
(TMR2:TMR1) ON
Only TMR1 increments
16-bit timer OFF
1
1
0
0
x
1
1
0
1
Timers in 8-bit mode
FIGURE 13-2:
TMR2 AND TMR1 IN 16-BIT TIMER/COUNTER MODE
1
RB4/TCLK12
0
FOSC/4
TMR1ON
(TCON2<0>)
MSB
LSB
TMR1 x 8
TMR1CS
RESET
Equal
(TCON1<0>)
TMR2 x 8
Comparator x16
Set Interrupt TMR1IF
(PIR1<4>)
PR2 x 8
PR1 x 8
1998-2013 Microchip Technology Inc.
DS30289C-page 105
PIC17C7XX
TABLE 13-3: SUMMARY OF TIMER1, TIMER2 AND TIMER3 REGISTERS
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
16h, Bank 3
TCON1
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
0000 0000 0000 0000
0000 0000 0000 0000
17h, Bank 3
16h, Bank 7
TCON2
TCON3
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
—
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
x000 0010 u000 0010
0000 0000 0000 0000
0000 0000 0000 0000
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
TMR1
TMR2
PIR1
Timer1’s Register
Timer2’s Register
RBIF
RBIE
PEIF
—
TMR3IF
TMR2IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
TO
CA1IF
CA1IE
T0CKIE
PD
TX1IF
TX1IE
T0IE
RC1IF
RC1IE
INTE
PIE1
TMR3IE TMR2IE
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIF
—
T0IF
STKAV
GLINTD
POR
BOR
--11 11qq --11 qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
10h, Bank 7
12h, Bank 3
13h, Bank 3
11h, Bank 7
Legend:
PR1
Timer1 Period Register
Timer2 Period Register
PR2
PW1DCL
PW2DCL
PW3DCL
PW1DCH
PW2DCH
PW3DCH
DC1
DC1
DC1
DC9
DC9
DC9
DC0
DC0
DC0
DC8
DC8
DC8
—
TM2PW2
TM2PW3
DC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC6
DC6
DC6
DC5
DC5
DC5
DC4
DC4
DC4
DC3
DC3
DC3
DC2
DC2
DC2
DC7
DC7
x= unknown, u= unchanged, -= unimplemented, read as a '0', q = value depends on condition.
Shaded cells are not used by Timer1 or Timer2.
DS30289C-page 106
1998-2013 Microchip Technology Inc.
PIC17C7XX
The user needs to set the PWM1ON bit (TCON2<4>)
to enable the PWM1 output. When the PWM1ON bit is
set, the RB2/PWM1 pin is configured as PWM1 output
and forced as an output, irrespective of the data direc-
tion bit (DDRB<2>). When the PWM1ON bit is clear,
the pin behaves as a port pin and its direction is con-
trolled by its data direction bit (DDRB<2>). Similarly,
the PWM2ON (TCON2<5>) bit controls the configura-
tion of the RB3/PWM2 pin and the PWM3ON
(TCON3<0>) bit controls the configuration of the RG5/
PWM3 pin.
13.1.3
USING PULSE WIDTH
MODULATION (PWM) OUTPUTS
WITH TIMER1 AND TIMER2
Three high speed pulse width modulation (PWM) out-
puts are provided. The PWM1 output uses Timer1 as
its time base, while PWM2 and PWM3 may indepen-
dently be software configured to use either Timer1 or
Timer2 as the time base. The PWM outputs are on the
RB2/PWM1, RB3/PWM2 and RG5/PWM3 pins.
Each PWM output has a maximum resolution of 10-
bits. At 10-bit resolution, the PWM output frequency is
32.2 kHz (@ 32 MHz clock) and at 8-bit resolution the
PWM output frequency is 128.9 kHz. The duty cycle of
the output can vary from 0% to 100%.
FIGURE 13-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
PWxDCL<7:6>
Write
Duty Cycle Registers
Figure 13-3 shows a simplified block diagram of a
PWM module.
PWxDCH
The duty cycle registers are double buffered for glitch
free operation. Figure 13-4 shows how a glitch could
occur if the duty cycle registers were not double
buffered.
Read
(Slave)
PWMx
Comparator
R
S
Q
TMRx
(Note 1)
PWMxON
Comparator
Clear Timer,
PWMx pin and
Latch D.C.
PRy
Note 1: 8-bit timer is concatenated with 2-bit internal
Q clock or 2 bits of the prescaler to create
10-bit time base.
FIGURE 13-4:
PWM OUTPUT (NOT BUFFERED)
0
10
20
30
40
0
10
20
30
40
0
PWM
Output
Timer
Interrupt
Write New
Timer Interrupt
PWM Duty Cycle Value New PWM Duty Cycle Value
Transferred to Slave
Note: The dotted line shows PWM output if duty cycle registers were not double buffered.
If the new duty cycle is written after the timer has passed that value, then the PWM does
not reset at all during the current cycle, causing a “glitch”.
In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.
1998-2013 Microchip Technology Inc.
DS30289C-page 107
PIC17C7XX
If DCx
= 0, then the duty cycle is zero. If
13.1.3.1
PWM Periods
PRx = PWxDCH, then the PWM output will be low for
one to four Q-clocks (depending on the state of the
PWxDCL<7:6> bits). For a duty cycle to be 100%, the
PWxDCH value must be greater then the PRx value.
The period of the PWM1 output is determined by
Timer1 and its period register (PR1). The period of the
PWM2 and PWM3 outputs can be individually software
configured to use either Timer1 or Timer2 as the time-
base. For PWM2, when TM2PW2 bit (PW2DCL<5>) is
clear, the time base is determined by TMR1 and PR1
and when TM2PW2 is set, the time base is determined
by Timer2 and PR2. For PWM3, when TM2PW3 bit
(PW3DCL<5>) is clear, the time base is determined by
TMR1 and PR1, and when TM2PW3 is set, the time
base is determined by Timer2 and PR2.
The duty cycle registers for both PWM outputs are dou-
ble buffered. When the user writes to these registers,
they are stored in master latches. When TMR1 (or
TMR2) overflows and a new PWM period begins, the
master latch values are transferred to the slave latches
and the PWMx pin is forced high.
Note: For PW1DCH, PW1DCL, PW2DCH,
PW2DCL, PW3DCH and PW3DCL regis-
ters, a write operation writes to the "master
latches", while a read operation reads the
"slave latches". As a result, the user may
not read back what was just written to the
duty cycle registers (until transferred to
slave latch).
Running two different PWM outputs on two different
timers allows different PWM periods. Running all
PWMs from Timer1 allows the best use of resources by
freeing Timer2 to operate as an 8-bit timer. Timer1 and
Timer2 cannot be used as a 16-bit timer if any PWM is
being used.
The PWM periods can be calculated as follows:
The user should also avoid any "read-modify-write"
operations on the duty cycle registers, such as:
ADDWF PW1DCH. This may cause duty cycle outputs
that are unpredictable.
period of PWM1 = [(PR1) + 1] x 4TOSC
period of PWM2 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
period of PWM3 = [(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
TABLE 13-4: PWM FREQUENCY vs.
RESOLUTION AT 33 MHz
The duty cycle of PWMx is determined by the 10-bit
value DCx<9:0>. The upper 8-bits are from register
PWxDCH and the lower 2-bits are from PWxDCL<7:6>
(PWxDCH:PWxDCL<7:6>). Table 13-4 shows the
maximum PWM frequency (FPWM), given the value in
the period register.
Frequency (kHz)
PWM
Frequency
32.2 64.5 90.66 128.9 515.6
PRx Value
0xFF 0x7F 0x5A
10-bit 9-bit 8.5-bit
0x3F
8-bit
0x0F
6-bit
High
Resolution
The number of bits of resolution that the PWM can
achieve depends on the operation frequency of the
device as well as the PWM frequency (FPWM).
Standard
Resolution
8-bit 7-bit 6.5-bit
6-bit
4-bit
Maximum PWM resolution (bits) for a given PWM
frequency:
13.1.3.2 PWM INTERRUPTS
The PWM modules make use of the TMR1 and/or
TMR2 interrupts. A timer interrupt is generated when
TMR1 or TMR2 equals its period register and on the
following increment is cleared to zero. This interrupt
also marks the beginning of a PWM cycle. The user
can write new duty cycle values before the timer
rollover. The TMR1 interrupt is latched into the TMR1IF
bit and the TMR2 interrupt is latched into the TMR2IF
bit. These flags must be cleared in software.
FOSC
log ( FPWM )
=
bits
log (2)
where: FPWM = 1 / period of PWM
The PWMx duty cycle is as follows:
PWMx Duty Cycle = (DCx) x TOSC
where DCx represents the 10-bit value from
PWxDCH:PWxDCL.
DS30289C-page 108
1998-2013 Microchip Technology Inc.
PIC17C7XX
13.1.3.3
External Clock Source
13.1.3.4
Maximum Resolution/Frequency for
External Clock Input
The PWMs will operate, regardless of the clock source
of the timer. The use of an external clock has ramifica-
tions that must be understood. Because the external
TCLK12 input is synchronized internally (sampled once
per instruction cycle), the time TCLK12 changes to the
time the timer increments, will vary by as much as 1TCY
(one instruction cycle). This will cause jitter in the duty
cycle as well as the period of the PWM output.
The use of an external clock for the PWM time base
(Timer1 or Timer2) limits the PWM output to a maxi-
mum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when inter-
nal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, is shown in Table 13-4 (Standard
Resolution mode).
This jitter will be 1TCY, unless the external clock is syn-
chronized with the processor clock. Use of one of the
PWM outputs as the clock source to the TCLK12 input,
will supply a synchronized clock.
In general, when using an external clock source for
PWM, its frequency should be much less than the
device frequency (FOSC).
TABLE 13-5: REGISTERS/BITS ASSOCIATED WITH PWM
Value on
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 3
17h, Bank 3
TCON1
TCON2
CA2ED1 CA2ED0
CA1ED1
CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
0000 0000 0000 0000
16h, Bank 7
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
TCON3
TMR1
TMR2
PIR1
—
CA4OVF
CA3OVF
CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
x000 0010 u000 0010
0000 0000 0000 0000
0000 0000 0000 0000
Timer1’s Register
Timer2’s Register
RBIF
RBIE
PEIF
TMR3IF
TMR2IF
TMR2IE
T0IF
TMR1IF
TMR1IE
INTF
CA2IF
CA2IE
PEIE
CA1IF
CA1IE
TX1IF
TX1IE
T0IE
RC1IF
RC1IE
INTE
PIE1
TMR3IE
T0CKIF
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIE
—
—
STKAV
GLINTD
TO
PD
POR
BOR
--11 11qq --11 qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
10h, Bank 7
12h, Bank 3
13h, Bank 3
11h, Bank 7
Legend:
PR1
Timer1 Period Register
Timer2 Period Register
PR2
PW1DCL
PW2DCL
PW3DCL
PW1DCH
PW2DCH
PW3DCH
DC1
DC1
DC1
DC9
DC9
DC9
DC0
DC0
DC0
DC8
DC8
DC8
—
TM2PW2
TM2PW3
DC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC6
DC6
DC6
DC5
DC5
DC5
DC4
DC4
DC4
DC3
DC3
DC3
DC2
DC2
DC2
DC7
DC7
x= unknown, u= unchanged, -= unimplemented, read as '0', q= value depends on conditions.
Shaded cells are not used by PWM Module.
1998-2013 Microchip Technology Inc.
DS30289C-page 109
PIC17C7XX
(RB0/CAP1, RB1/CAP2, RG4/CAP3, and RE3/CAP4),
one for each capture register pair. The capture pins are
multiplexed with the I/O pins. An event can be:
13.2 Timer3
Timer3 is a 16-bit timer consisting of the TMR3H and
TMR3L registers. TMR3H is the high byte of the timer
and TMR3L is the low byte. This timer has an associ-
ated 16-bit period register (PR3H/CA1H:PR3L/CA1L).
This period register can be software configured to be a
another 16-bit capture register.
• A rising edge
• A falling edge
• Every 4th rising edge
• Every 16th rising edge
When the TMR3CS bit (TCON1<2>) is clear, the timer
increments every instruction cycle (FOSC/4). When
TMR3CS is set, the counter increments on every falling
edge of the RB5/TCLK3 pin. In either mode, the
TMR3ON bit must be set for the timer/counter to incre-
ment. When TMR3ON is clear, the timer will not incre-
ment or set flag bit TMR3IF.
Each 16-bit capture register has an interrupt flag asso-
ciated with it. The flag is set when a capture is made.
The capture modules are truly part of the Timer3 block.
Figure 13-5 and Figure 13-6 show the block diagrams
for the two modes of operation.
13.2.1
THREE CAPTURE AND ONE
PERIOD REGISTER MODE
Timer3 has two modes of operation, depending on the
CA1/PR3 bit (TCON2<3>). These modes are:
In this mode, registers PR3H/CA1H and PR3L/CA1L
constitute a 16-bit period register. A block diagram is
shown in Figure 13-5. The timer increments until it
equals the period register and then resets to 0000h on
the next timer clock. TMR3 Interrupt Flag bit (TMR3IF)
is set at this point. This interrupt can be disabled by
clearing the TMR3 Interrupt Enable bit (TMR3IE).
TMR3IF must be cleared in software.
• Three capture and one period register mode
• Four capture register mode
The PIC17C7XX has up to four 16-bit capture registers
that capture the 16-bit value of TMR3 when events are
detected on capture pins. There are four capture pins
FIGURE 13-5:
TIMER3 WITH THREE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
TMR3CS
(TCON1<2>)
PR3H/CA1H
PR3L/CA1L
TMR3L
Set TMR3IF
(PIR1<6>)
Comparatorx16
Equal
Reset
0
FOSC/4
TMR3H
1
TMR3ON
(TCON2<2>)
RB5/TCLK3
RB1/CAP2
Capture2
Edge select,
Enable
CA2H
Prescaler select
CA2L
2
Set CA2IF
(PIR1<3>)
CA2ED1: CA2ED0
(TCON1<7:6>)
Capture3
Enable
Edge select,
Prescaler select
RG4/CAP3
CA3H
CA3L
2
Set CA3IF
(PIR2<2>)
CA3ED1: CA3ED0
(TCON3<2:1>)
Capture4
Enable
Edge select,
Prescaler select
RE3/CAP4
CA4H
CA4L
2
Set CA4IF
(PIR2<3>)
CA4ED1: CA4ED0
(TCON3<4:3>)
DS30289C-page 110
1998-2013 Microchip Technology Inc.
PIC17C7XX
This mode (3 Capture, 1 Period) is selected if control bit
CA1/PR3 is clear. In this mode, the Capture1 register,
consisting of high byte (PR3H/CA1H) and low byte
(PR3L/CA1L), is configured as the period control regis-
ter for TMR3. Capture1 is disabled in this mode and the
corresponding interrupt bit, CA1IF, is never set. TMR3
increments until it equals the value in the period regis-
ter and then resets to 0000h on the next timer clock.
The input on the capture pin CAPx is synchronized
internally to internal phase clocks. This imposes certain
restrictions on the input waveform (see the Electrical
Specification section for timing).
The capture overflow status flag bit is double buffered.
The master bit is set if one captured word is already
residing in the Capture register (CAxH:CAxL) and
another “event” has occurred on the CAPx pin. The
new event will not transfer the TMR3 value to the cap-
ture register, protecting the previous unread capture
value. When the user reads both the high and the low
bytes (in any order) of the Capture register, the master
overflow bit is transferred to the slave overflow bit
(CAxOVF) and then the master bit is reset. The user
can then read TCONx to determine the value of CAx-
OVF.
All other Captures are active in this mode.
13.2.1.1
Capture Operation
The CAxED1 and CAxED0 bits determine the event on
which capture will occur. The possible events are:
• Capture on every falling edge
• Capture on every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
The recommended sequence to read capture registers
and capture overflow flag bits is shown in Example 13-1.
When a capture takes place, an interrupt flag is latched
into the CAxIF bit. This interrupt can be enabled by set-
ting the corresponding mask bit CAxIE. The Peripheral
Interrupt Enable bit (PEIE) must be set and the Global
Interrupt Disable bit (GLINTD) must be cleared for the
interrupt to be acknowledged. The CAxIF interrupt flag
bit is cleared in software.
When the capture prescale select is changed, the pres-
caler is not reset and an event may be generated.
Therefore, the first capture after such a change will be
ambiguous. However, it sets the time-base for the next
capture. The prescaler is reset upon chip RESET.
The capture pin, CAPx, is a multiplexed pin. When
used as a port pin, the capture is not disabled. How-
ever, the user can simply disable the Capture interrupt
by clearing CAxIE. If the CAPx pin is used as an output
pin, the user can activate a capture by writing to the
port pin. This may be useful during development phase
to emulate a capture interrupt.
1998-2013 Microchip Technology Inc.
DS30289C-page 111
PIC17C7XX
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set upon detection of the capture event. The
corresponding interrupt mask bit is CA1IE. The
Capture1 Overflow Status bit is CA1OVF.
13.2.2
FOUR CAPTURE MODE
This mode is selected by setting bit CA1/PR3. A block
diagram is shown in Figure 13-6. In this mode, TMR3
runs without a period register and increments from
0000h to FFFFh and rolls over to 0000h. The TMR3
interrupt Flag (TMR3IF) is set on this rollover. The
TMR3IF bit must be cleared in software.
All the captures operate in the same manner. Refer to
Section 13.2.1 for the operation of capture.
FIGURE 13-6:
TIMER3 WITH FOUR CAPTURES BLOCK DIAGRAM
Set TMR3IF
(PIR1<6>)
FOSC/4
0
1
TMR3H
TMR3L
TMR3ON
RB5/TCLK3
RB0/CAP1
TMR3CS
(TCON2<2>)
(TCON1<2>)
Capture1 Enable
Edge Select,
Prescaler Select
2
Set CA1IF
(PIR1<2>)
PR3H/CA1H
PR3L/CA1L
CA1ED1, CA1ED0
(TCON1<5:4>)
Capture2 Enable
Edge Select,
Prescaler Select
Set CA2IF
(PIR1<3>)
RB1/CAP2
RG4/CAP3
2
CA2H
CA2L
CA3L
CA2ED1, CA2ED0
(TCON1<7:6>)
Capture3 Enable
Set CA3IF
(PIR2<2>)
Edge Select,
Prescaler Select
2
CA3H
CA3ED1: CA3ED0
(TCON3<2:1>)
Capture4 Enable
Set CA4IF
(PIR2<3>)
Edge Select,
Prescaler Select
RE3/CAP4
2
CA4H
CA4L
CA4ED1: CA4ED0
(TCON3<4:3>)
DS30289C-page 112
1998-2013 Microchip Technology Inc.
PIC17C7XX
order) of the Capture register, the master overflow bit is
transferred to the slave overflow bit (CAxOVF) and
then the master bit is reset. The user can then read
TCONx to determine the value of CAxOVF.
13.2.3
READING THE CAPTURE
REGISTERS
The Capture overflow status flag bits are double buff-
ered. The master bit is set if one captured word is
already residing in the Capture register and another
“event” has occurred on the CAPx pin. The new event
will not transfer the TMR3 value to the capture register,
protecting the previous unread capture value. When
the user reads both the high and the low bytes (in any
An example of an instruction sequence to read capture
registers and capture overflow flag bits is shown in
Example 13-1. Depending on the capture source, dif-
ferent registers will need to be read.
EXAMPLE 13-1:
SEQUENCE TO READ CAPTURE REGISTERS
MOVLB 3
; Select Bank 3
MOVPF CA2L, LO_BYTE
MOVPF CA2H, HI_BYTE
MOVPF TCON2, STAT_VAL
; Read Capture2 low byte, store in LO_BYTE
; Read Capture2 high byte, store in HI_BYTE
; Read TCON2 into file STAT_VAL
TABLE 13-6: REGISTERS ASSOCIATED WITH CAPTURE
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
16h, Bank 3
17h, Bank 3
TCON1
CA2ED1 CA2ED0 CA1ED1
CA1ED0
T16
TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7
12h, Bank 2
13h, Bank 2
16h, Bank 1
17h, Bank 1
10h, Bank 4
11h, Bank 4
TCON3
TMR3L
TMR3H
PIR1
—
CA4OVF CA3OVF
CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
x000 0010 u000 0010
0000 0000 0000 0000
000- 0010 000- 0010
000- 0000 000- 0000
0000 0000 0000 0000
Holding Register for the Low Byte of the 16-bit TMR3 Register
Holding Register for the High Byte of the 16-bit TMR3 Register
RBIF
RBIE
TMR3IF
TMR3IE
BCLIF
TMR2IF
TMR2IE
ADIF
TMR1IF
TMR1IE
—
CA2IF
CA2IE
CA4IF
CA4IE
PEIE
CA1IF
CA1IE
CA3IF
CA3IE
T0CKIE
TX1IF
TX1IE
TX2IF
TX2IE
T0IE
RC1IF
RC1IE
RC2IF
RC2IE
INTE
PIE1
PIR2
SSPIF
SSPIE
PEIF
PIE2
BCLIE
ADIE
—
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
T0CKIF
T0IF
INTF
—
—
STKAV
GLINTD
TO
PD
POR
BOR
--11 11qq --11 qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h, Bank 2
17h, Bank 2
14h, Bank 3
15h, Bank 3
12h, Bank 7
13h, Bank 7
14h, Bank 7
15h, Bank 7
Legend:
PR3L/CA1L Timer3 Period Register, Low Byte/Capture1 Register, Low Byte
PR3H/CA1H Timer3 Period Register, High Byte/Capture1 Register, High Byte
CA2L
CA2H
CA3L
CA3H
CA4L
CA4H
Capture2 Low Byte
Capture2 High Byte
Capture3 Low Byte
Capture3 High Byte
Capture4 Low Byte
Capture4 High Byte
x= unknown, u= unchanged, -= unimplemented, read as '0', q= value depends on condition.
Shaded cells are not used by Capture.
1998-2013 Microchip Technology Inc.
DS30289C-page 113
PIC17C7XX
13.2.4
EXTERNAL CLOCK INPUT FOR
TIMER3
13.2.5
READING/WRITING TIMER3
Since Timer3 is a 16-bit timer and only 8-bits at a time
can be read or written, care should be taken when
reading or writing while the timer is running. The best
method is to stop the timer, perform any read or write
operation and then restart Timer3 (using the TMR3ON
bit). However, if it is necessary to keep Timer3 free-
running, care must be taken. For writing to the 16-bit
TMR3, Example 13-2 may be used. For reading the 16-
bit TMR3, Example 13-3 may be used. Interrupts must
be disabled during this routine.
When TMR3CS is set, the 16-bit TMR3 increments on
the falling edge of clock input TCLK3. The input on the
RB5/TCLK3 pin is sampled and synchronized by the
internal phase clocks, twice every instruction cycle.
This causes a delay from the time a falling edge
appears on TCLK3 to the time TMR3 is actually incre-
mented. For the external clock input timing require-
ments, see the Electrical Specification section.
Figure 13-7 shows the timing diagram when operating
from an external clock.
EXAMPLE 13-2:
WRITING TO TMR3
BSF
CPUSTA, GLINTD
; Disable interrupts
MOVFP
MOVFP
BCF
RAM_L, TMR3L
RAM_H, TMR3H
CPUSTA, GLINTD
;
;
; Done, enable interrupts
EXAMPLE 13-3:
READING FROM TMR3
MOVPF
MOVPF
MOVFP
CPFSLT TMR3L
RETURN
MOVPF
MOVPF
RETURN
TMR3L, TMPLO
TMR3H, TMPHI
TMPLO, WREG
; read low TMR3
; read high TMR3
; tmplo wreg
; TMR3L < wreg?
; no then return
; read low TMR3
; read high TMR3
; return
TMR3L, TMPLO
TMR3H, TMPHI
FIGURE 13-7:
TIMER1, TIMER2 AND TIMER3 OPERATION (IN COUNTER MODE)
Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4
TCLK12
or TCLK3
34h
35h
A8h
A9h
00h
TMR1, TMR2, or TMR3
PR1, PR2, or PR3H:PR3L
WR_TMR
'A9h'
'A9h'
RD_TMR
TMRxIF
MOVWF
TMRx
MOVFP
TMRx,W
MOVFP
TMRx,W
Instruction
Executed
Write to TMRx
Read TMRx
Read TMRx
Note 1: TCLK12 is sampled in Q2 and Q4.
2: indicates a sampling point.
3: The latency from TCLK12 to timer increment is between 2Tosc and 6Tosc.
DS30289C-page 114
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 13-8:
TIMER1, TIMER2 AND TIMER3 OPERATION (IN TIMER MODE)
Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
AD15:AD0
ALE
BCF
TCON2, 0
Start TMR1
MOVF
BSF
MOVWF
TMR1
MOVF
NOP
07h
NOP
NOP
NOP
00h
Instruction
Fetched
MOVLB 3
NOP
06h
TMR1, W
Read TMR1
TCON2, 0
Stop TMR1
TMR1, W
Write TMR1 Read TMR1
TMR1
PR1
04h
05h
03h
04h
05h
08h
TMR1ON
WR_TMR1
WR_TCON2
TMR1IF
RD_TMR1
TMR1
TMR1
Reads 03h Reads 04h
1998-2013 Microchip Technology Inc.
DS30289C-page 115
PIC17C7XX
NOTES:
DS30289C-page 116
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 14-1: USART MODULE GENERIC
NAMES
14.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULES
Generic Name USART1 Name USART2 Name
Registers
RCSTA
TXSTA
SPBRG
RCREG
TXREG
RCSTA1
TXSTA1
SPBRG1
RCREG1
TXREG1
RCSTA2
TXSTA2
SPBRG2
RCREG2
TXREG2
Each USART module is a serial I/O module. There are
two USART modules that are available on the
PIC17C7XX. They are specified as USART1 and
USART2. The description of the operation of these mod-
ules is generic in regard to the register names and pin
names used. Table 14-1 shows the generic names that
are used in the description of operation and the actual
names for both USART1 and USART2. Since the control
bits in each register have the same function, their names
are the same (there is no need to differentiate).
Interrupt Control Bits
RC1IE
RCIE
RCIF
TXIE
TXIF
RC2IE
RC2IF
TX2IE
TX2IF
RC1IF
TX1IE
TX1IF
The Transmit Status and Control Register (TXSTA) is
shown in Figure 14-1, while the Receive Status and
Control Register (RCSTA) is shown in Figure 14-2.
Pins
RA4/RX1/DT1
RA5/TX1/CK1
RX/DT
TX/CK
RG6/RX2/DT2
RG7/TX2/CK2
REGISTER 14-1: TXSTA1 REGISTER (ADDRESS: 15h, BANK 0)
TXSTA2 REGISTER (ADDRESS: 15h, BANK 4)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
U-0
—
R-1
TRMT
R/W-x
TX9D
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
Asynchronous mode:
Don’t care
bit 6
bit 5
TX9: 9-bit Transmit Select bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
SREN/CREN overrides TXEN in SYNC mode
bit 4
SYNC: USART Mode Select bit
(Synchronous/Asynchronous)
1= Synchronous mode
0= Asynchronous mode
bit 3-2
bit 1
Unimplemented: Read as '0'
TRMT: Transmit Shift Register (TSR) Empty bit
1= TSR empty
0= TSR full
bit 0
TX9D: 9th bit of Transmit Data (can be used to calculate the parity in software)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
1998-2013 Microchip Technology Inc.
DS30289C-page 117
PIC17C7XX
The USART can be configured as a full duplex asyn-
chronous system that can communicate with peripheral
devices such as CRT terminals and personal comput-
ers, or it can be configured as a half duplex synchro-
nous system that can communicate with peripheral
devices such as A/D or D/A integrated circuits, Serial
EEPROMs etc. The USART can be configured in the
following modes:
The SPEN (RCSTA<7>) bit has to be set in order to
configure the I/O pins as the Serial Communication
Interface (USART).
The USART module will control the direction of the RX/
DT and TX/CK pins, depending on the states of the
USART configuration bits in the RCSTA and TXSTA
registers. The bits that control I/O direction are:
• SPEN
• TXEN
• SREN
• CREN
• CSRC
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
REGISTER 14-2: RCSTA1 REGISTER (ADDRESS: 13h, BANK 0)
RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
—
R-0
FERR
R-0
OERR
R-x
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Configures TX/CK and RX/DT pins as serial port pins
0= Serial port disabled
RX9: 9-bit Receive Select bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically
cleared.
Synchronous mode:
1= Enable reception
0= Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
bit 4
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1= Enable continuous reception
0 = Disables continuous reception
Synchronous mode:
1= Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
bit 3
bit 2
Unimplemented: Read as '0'
FERR: Framing Error bit
1= Framing error (updated by reading RCREG)
0= No framing error
bit 1
bit 0
bit OERR: Overrun Error bit
1= Overrun (cleared by clearing CREN)
0= No overrun error
RX9D: 9th bit of Receive Data (can be the software calculated parity bit)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset ’1’ = Bit is set
DS30289C-page 118
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 14-1:
USART TRANSMIT
Sync
Master/Slave
BRG
4
Sync/Async
Sync/Async
TSR
Sync/Async
CK/TX
DT
16
Clock
Start 0 1
7 8 Stop
Load
TXEN/
Write to TXREG
8
Bit Count
0 1
7
TXREG
Interrupt
TXSTA<0>
Data Bus
TXIE
FIGURE 14-2:
USART RECEIVE
Interrupt
RCIE
OSC
4
BRG
Master/Slave
Sync
Sync/Async
Async/Sync
Enable
Bit Count
Buffer
Logic
CK
RX
16
START
Detect
SPEN
SREN/
CREN/
Start_Bit
RSR
Majority
Detect
Buffer
Logic
Clock
MSb
LSb
1 0
Data
Stop 8 7
FIFO
Logic
RX9
Async/Sync
RCREG
Clk
FIFO
RX9D
RX9D
7
7
1 0
1 0
FERR
FERR
Data Bus
1998-2013 Microchip Technology Inc.
DS30289C-page 119
PIC17C7XX
EXAMPLE 14-1:
CALCULATING BAUD
RATE ERROR
14.1 USART Baud Rate Generator
(BRG)
Desired Baud Rate = FOSC / (64 (X + 1))
9600 = 16000000 /(64 (X + 1))
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. Table 14-2 shows
the formula for computation of the baud rate for differ-
ent USART modes. These only apply when the USART
is in Synchronous Master mode (internal clock) and
Asynchronous mode.
X
= 25.042 25
Calculated Baud Rate = 16000000 / (64 (25 + 1))
= 9615
Error = (Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
= (9615 - 9600) / 9600
= 0.16%
Given the desired baud rate and Fosc, the nearest inte-
ger value between 0 and 255 can be calculated using
the formula below. The error in baud rate can then be
determined.
Writing a new value to the SPBRG, causes the BRG
timer to be reset (or cleared). This ensures that the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
TABLE 14-2: BAUD RATE FORMULA
SYNC
Mode
Baud Rate
Effects of Reset
0
1
Asynchronous
Synchronous
FOSC/(64(X+1))
FOSC/(4(X+1))
After any device RESET, the SPBRG register is
cleared. The SPBRG register will need to be loaded
with the desired value after each RESET.
X = value in SPBRG (0 to 255)
Example 14-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
SYNC = 0
TABLE 14-3: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
13h, Bank 0
15h, Bank 0
17h, Bank 0
13h, Bank 4
15h, Bank 4
17h, Bank 4
RCSTA1
TXSTA1
SPBRG1
RCSTA2
TXSTA2
SPBRG2
SPEN
CSRC
RX9
TX9
SREN
TXEN
CREN
SYNC
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x
0000 -00u
0000 --1x
0000 0000
0000 --1u
0000 0000
Baud Rate Generator Register
SPEN
CSRC
RX9
TX9
SREN
TXEN
CREN
SYNC
—
—
FERR
—
OERR
TRMT
RX9D
TX9D
0000 -00x
0000 -00u
0000 --1x
0000 0000
0000 --1u
0000 0000
Baud Rate Generator Register
Legend:
x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Baud Rate Generator.
DS30289C-page 120
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 14-4: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
BAUD
RATE
(K)
SPBRG
VALUE
SPBRG
VALUE
SPBRG
VALUE
SPBRG
VALUE
KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL)
0.3
1.2
NA
NA
—
—
—
—
NA
NA
—
—
—
—
—
—
—
80
64
20
12
0
NA
NA
—
—
—
—
—
—
255
64
51
16
9
NA
NA
—
—
—
—
2.4
NA
—
—
NA
—
NA
—
NA
—
—
9.6
NA
—
—
NA
—
NA
—
NA
—
—
19.2
76.8
96
NA
—
—
NA
—
19.53
76.92
96.15
294.1
500
+1.73
+0.16
+0.16
-1.96
0
19.23
76.92
95.24
307.69
500
+0.16
+0.16
-0.79
+2.56
0
207
51
41
12
7
77.10
95.93
294.64
485.29
8250
32.22
+0.39
-0.07
-1.79
-2.94
—
106
85
27
16
0
77.16
96.15
297.62
480.77
6250
24.41
+0.47
+0.16
-0.79
-3.85
—
300
500
HIGH
LOW
5000
19.53
—
0
4000
15.625
—
0
—
255
—
255
—
255
—
255
FOSC = 10 MHz
FOSC = 7.159 MHz
FOSC = 5.068 MHz
BAUD
RATE
(K)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
KBAUD
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
NA
—
—
—
—
NA
NA
—
—
—
—
NA
NA
—
—
—
0
—
—
NA
2.4
NA
—
—
NA
—
—
NA
—
9.6
9.766
19.23
75.76
96.15
312.5
500
+1.73
+0.16
-1.36
+0.16
+4.17
0
255
129
32
25
7
9.622
19.24
77.82
94.20
298.3
NA
+0.23
+0.23
+1.32
-1.88
-0.57
—
185
92
22
18
5
9.6
131
65
15
12
3
19.2
76.8
96
19.2
79.2
97.48
316.8
NA
0
+3.13
+1.54
+5.60
—
300
500
HIGH
LOW
4
—
—
2500
9.766
—
0
1789.8
6.991
—
0
1267
4.950
—
0
—
255
—
255
—
255
FOSC = 1 MHz
FOSC = 32.768 kHz
FOSC = 3.579 MHz
BAUD
RATE
(K)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
KBAUD
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
NA
—
—
—
—
—
92
46
11
8
NA
1.202
2.404
9.615
19.24
83.34
NA
—
+0.16
+0.16
+0.16
+0.16
+8.51
—
—
207
103
25
12
2
0.303
1.170
NA
+1.14
-2.48
—
26
6
NA
2.4
NA
—
—
—
—
—
—
—
—
0
9.6
9.622
19.04
74.57
99.43
298.3
NA
+0.23
-0.83
-2.90
_3.57
-0.57
—
NA
—
19.2
76.8
96
NA
—
NA
—
—
NA
—
300
500
HIGH
LOW
2
NA
—
—
NA
—
—
0
NA
—
—
NA
—
894.9
3.496
—
250
—
0
8.192
0.032
—
—
255
0.976
—
255
—
255
1998-2013 Microchip Technology Inc.
DS30289C-page 121
PIC17C7XX
TABLE 14-5: BAUD RATES FOR ASYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
BAUD
RATE
(K)
SPBRG
VALUE
SPBRG
VALUE
SPBRG
VALUE
SPBRG
VALUE
KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL)
0.3
1.2
NA
—
—
—
—
214
53
26
6
NA
NA
—
—
—
—
162
40
19
4
NA
—
—
255
129
32
15
3
NA
1.202
2.404
9.615
19.23
83.33
NA
—
+0.16
+0.16
+0.16
+0.16
+8.51
—
—
207
103
25
12
2
NA
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
—
2.4
2.398
9.548
19.09
73.66
103.12
257.81
515.62
-0.07
-0.54
-0.54
-4.09
+7.42
-14.06
+3.13
—
2.396
9.53
19.53
78.13
97.65
390.63
NA
0.14
-0.76
+1.73
+1.73
+1.73
+30.21
—
9.6
19.2
76.8
96
4
3
2
—
300
500
1
0
0
NA
—
—
0
—
0
—
0
NA
—
—
HIGH 515.62
LOW 2.014
0
—
—
312.5
1.221
—
250
—
0
—
255
1.53
—
255
—
255
0.977
—
255
FOSC = 7.159 MHz
FOSC = 5.068 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
KBAUD
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
+3.13
0.3
1.2
NA
—
+0.16
+0.16
+1.73
+1.73
+1.73
—
—
129
64
15
7
NA
1.203
2.380
9.322
18.64
NA
—
_0.23
-0.83
-2.90
-2.90
—
—
92
46
11
5
0.31
1.2
255
65
32
7
1.202
2.404
9.766
19.53
78.13
NA
0
0
2.4
2.4
9.6
9.9
-3.13
+3.13
+3.13
—
19.2
76.8
96
19.8
79.2
NA
3
1
—
—
—
—
0
0
—
—
—
0
NA
—
—
—
—
0
300
500
HIGH
LOW
NA
—
NA
—
NA
—
NA
—
NA
—
NA
—
156.3
0.610
—
111.9
0.437
—
79.2
0.309
—
—
255
—
255
—
255
FOSC = 1 MHz
FOSC = 32.768 kHz
FOSC = 3.579 MHz
BAUD
RATE
(K)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
KBAUD
%ERROR
KBAUD
%ERROR
KBAUD
%ERROR
0.3
1.2
0.301
1.190
2.432
9.322
18.64
NA
+0.23
-0.83
+1.32
-2.90
-2.90
—
185
46
22
5
0.300
1.202
2.232
NA
+0.16
+0.16
-6.99
—
51
12
6
0.256
NA
-14.67
—
1
—
—
—
—
—
—
—
—
0
2.4
NA
—
9.6
—
—
—
—
—
—
0
NA
—
19.2
76.8
96
2
NA
—
NA
—
—
—
—
—
0
NA
—
NA
—
NA
—
NA
—
NA
—
300
500
HIGH
LOW
NA
—
NA
—
NA
—
NA
—
NA
—
NA
—
55.93
0.218
—
15.63
0.061
—
0.512
0.002
—
—
255
—
255
—
255
DS30289C-page 122
1998-2013 Microchip Technology Inc.
PIC17C7XX
TRMT is a read only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user has
to poll this bit in order to determine if the TSR is empty.
14.2 USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip dedicated 8-bit baud rate genera-
tor can be used to derive standard baud rate frequen-
cies from the oscillator. The USART’s transmitter and
receiver are functionally independent but use the same
data format and baud rate. The baud rate generator
produces a clock x64 of the bit shift rate. Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
Note: The TSR is not mapped in data memory,
so it is not available to the user.
Transmission
is
enabled
by
setting
the
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 14-3). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally,
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR, resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 14-4). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the TX/CK
pin will revert to hi-impedance.
The Asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing components:
• Baud Rate Generator
• Sampling Circuit
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
value should be written to TX9D (TXSTA<0>). The
ninth bit value must be written before writing the 8-bit
data to the TXREG. This is because a data write to
TXREG can result in an immediate transfer of the data
to the TSR (if the TSR is empty).
• Asynchronous Transmitter
• Asynchronous Receiver
14.2.1
USART ASYNCHRONOUS
TRANSMITTER
Steps to follow when setting up an Asynchronous
Transmission:
The USART transmitter block diagram is shown in
Figure 14-1. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG). TXREG is
loaded with data in software. The TSR is not loaded until
the STOP bit has been transmitted from the previous
load. As soon as the STOP bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), the TXREG
is empty and an interrupt bit, TXIF, is set. This interrupt
can be enabled/disabled by setting/clearing the TXIE bit.
TXIF will be set, regardless of TXIE and cannot be reset
in software. It will reset only when new data is loaded into
TXREG. While TXIF indicates the status of the TXREG,
the TRMT (TXSTA<1>) bit shows the status of the TSR.
1. Initialize the SPBRG register for the appropriate
baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the TXIE bit.
4. If 9-bit transmission is desired, then set the TX9
bit.
5. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
6. Load data to the TXREG register.
7. Enable the transmission by setting TXEN (starts
transmission).
FIGURE 14-3:
ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
(TX/CK pin)
STOP Bit
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
1998-2013 Microchip Technology Inc.
DS30289C-page 123
PIC17C7XX
FIGURE 14-4:
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
TX
START Bit
START Bit
Word 2
Bit 0
Bit 1
Bit 7/8
Bit 0
STOP Bit
(TX/CK pin)
Word 1
TXIF bit
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
Note: This timing diagram shows two consecutive transmissions.
TABLE 14-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
BOR
16h, Bank 1
17h, Bank 1
13h, Bank 0
16h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
16h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
TMR3IF TMR2IF TMR1IF CA2IF CA1IF
TMR3IE TMR2IE TMR1IE CA2IE CA1IE
TX1IF
TX1IE
OERR
RC1IF
RC1IE
RX9D
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
TXREG1
TXSTA1
SPBRG1
PIR2
RX9
SREN
CREN
—
FERR
Serial Port Transmit Register (USART1)
CSRC TX9 TXEN SYNC
Baud Rate Generator Register (USART1)
—
—
TRMT
TX9D
SSPIF
SSPIE
SPEN
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
—
—
CA4IF CA3IF
CA4IE CA3IE
TX2IF
TX2IE
OERR
RC2IF
RC2IE
RX9D
PIE2
RCSTA2
TXREG2
TXSTA2
SPBRG2
CREN
—
FERR
Serial Port Transmit Register (USART2)
CSRC TX9 TXEN SYNC
Baud Rate Generator Register (USART2)
—
—
TRMT
TX9D
x= unknown, u= unchanged, -= unimplemented, read as a '0'. Shaded cells are not used for asynchronous transmission.
DS30289C-page 124
1998-2013 Microchip Technology Inc.
PIC17C7XX
ting the receive logic (CREN is set). If the OERR bit is
set, transfers from the RSR to RCREG are inhibited, so
it is essential to clear the OERR bit if it is set. The fram-
ing error bit FERR (RCSTA<2>) is set if a STOP bit is
not detected.
14.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 14-2.
The data comes in the RX/DT pin and drives the data
recovery block. The data recovery block is actually a
high speed shifter operating at 16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC.
Note: The FERR and the 9th receive bit are buff-
ered the same way as the receive data.
Reading the RCREG register will allow the
RX9D and FERR bits to be loaded with val-
ues for the next received data. Therefore,
it is essential for the user to read the
RCSTA register before reading RCREG, in
order not to lose the old FERR and RX9D
information.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG (if it is
empty). If the transfer is complete, the interrupt bit,
RCIF, is set. The actual interrupt can be enabled/
disabled by setting/clearing the RCIE bit. RCIF is a
read only bit which is cleared by the hardware. It is
cleared when RCREG has been read and is empty.
RCREG is a double buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte begin shifting to the RSR. On detection of the
STOP bit of the third byte, if the RCREG is still full, then
the overrun error bit, OERR (RCSTA<1>) will be set.
The word in the RSR will be lost. RCREG can be read
twice to retrieve the two bytes in the FIFO. The OERR
bit has to be cleared in software which is done by reset-
14.2.3
SAMPLING
The data on the RX/DT pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX/DT pin. The sampling is done
on the seventh, eighth and ninth falling edges of a x16
clock (Figure 14-5).
The x16 clock is a free running clock and the three
sample points occur at a frequency of every 16 falling
edges.
FIGURE 14-5:
RX PIN SAMPLING SCHEME
START bit
Bit0
RX
(RX/DT pin)
Baud CLK for all but START bit
Baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
Samples
FIGURE 14-6:
START BIT DETECT
START bit
RX
(RX/DT pin)
x16 CLK
First rising edge of x16 clock after RX pin goes low
Q2, Q4 CLK
RX sampled low
1998-2013 Microchip Technology Inc.
DS30289C-page 125
PIC17C7XX
Steps to follow when setting up an Asynchronous
Reception:
7. Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
1. Initialize the SPBRG register for the appropriate
baud rate.
8. Read RCREG for the 8-bit received data.
9. If an overrun error occurred, clear the error by
clearing the OERR bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. Enable the reception by setting the CREN bit.
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
6. The RCIF bit will be set when reception com-
pletes and an interrupt will be generated if the
RCIE bit was set.
FIGURE 14-7:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX
(RX/DT pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 3
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 14-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
16h, Bank 1
17h, Bank 1
13h, Bank 0
14h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
14h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
RX2
TX1IF
TX1IE
OERR
RX1
RC1IF
RC1IE
RX9D
RX0
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
RCREG1
TXSTA1
SPBRG1
PIR2
RX9
RX6
TX9
SREN
RX5
CREN
RX4
—
RX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud Rate Generator Register
SSPIF
SSPIE
SPEN
RX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
RX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
RX2
TX2IF
TX2IE
OERR
RX1
RC2IF
RC2IE
RX9D
RX0
PIE2
RCSTA2
RCREG2
TXSTA2
SPBRG2
CREN
RX4
SYNC
RX6
RX3
—
CSRC
TX9
TXEN
—
TRMT
TX9D
Baud Rate Generator Register
x= unknown, u= unchanged, -= unimplemented, read as a '0'. Shaded cells are not used for asynchronous reception.
DS30289C-page 126
1998-2013 Microchip Technology Inc.
PIC17C7XX
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. The RX/DT and TX/CK pins will revert to hi-imped-
ance. If either CREN or SREN are set during a
transmission, the transmission is aborted and the RX/
DT pin reverts to a hi-impedance state (for a reception).
The TX/CK pin will remain an output if the CSRC bit is
set (internal clock). The transmitter logic is not reset,
although it is disconnected from the pins. In order to
reset the transmitter, the user has to clear the TXEN bit.
If the SREN bit is set (to interrupt an ongoing transmis-
sion and receive a single word), then after the single
word is received, SREN will be cleared and the serial
port will revert back to transmitting, since the TXEN bit
is still set. The DT line will immediately switch from hi-
impedance Receive mode to transmit and start driving.
To avoid this, TXEN should be cleared.
14.3 USART Synchronous Master
Mode
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e., transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchro-
nous mode is entered by setting the SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit
is set in order to configure the I/O pins to CK (clock) and
DT (data) lines, respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting the
CSRC (TXSTA<7>) bit.
14.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
The USART transmitter block diagram is shown in
Figure 14-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), TXREG
is empty and the TXIF bit is set. This interrupt can be
enabled/disabled by setting/clearing the TXIE bit. TXIF
will be set regardless of the state of bit TXIE and cannot
be cleared in software. It will reset only when new data
is loaded into TXREG. While TXIF indicates the status
of TXREG, TRMT (TXSTA<1>) shows the status of the
TSR. TRMT is a read only bit which is set when the
TSR is empty. No interrupt logic is tied to this bit, so the
user has to poll this bit in order to determine if the TSR
is empty. The TSR is not mapped in data memory, so it
is not available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
2. Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
3. Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
4. If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
Transmission is enabled by setting the TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The first data
bit will be shifted out on the next available rising edge
of the clock on the TX/CK pin. Data out is stable around
the falling edge of the synchronous clock (Figure 14-9).
The transmission can also be started by first loading
TXREG and then setting TXEN. This is advantageous
when slow baud rates are selected, since BRG is kept
in RESET when the TXEN, CREN, and SREN bits are
clear. Setting the TXEN bit will start the BRG, creating
a shift clock immediately. Normally when transmission
is first started, the TSR is empty, so a transfer to
TXREG will result in an immediate transfer to the TSR,
resulting in an empty TXREG. Back-to-back transfers
are possible.
5. If 9-bit transmission is desired, then set the TX9 bit.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
7. Start transmission by loading data to the TXREG
register.
8. Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN), allows transmission to start
sooner than doing these two events in the reverse order.
Note: To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is re-
enabled.
1998-2013 Microchip Technology Inc.
DS30289C-page 127
PIC17C7XX
TABLE 14-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
16h, Bank 1
17h, Bank 1
13h, Bank 0
16h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
16h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
TX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
TX2
TX1IF
TX1IE
OERR
TX1
RC1IF
RC1IE
RX9D
TX0
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
TXREG1
TXSTA1
SPBRG1
PIR2
RX9
TX6
TX9
SREN
TX5
CREN
TX4
—
TX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud Rate Generator Register
SSPIF
SSPIE
SPEN
TX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
TX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
TX2
TX2IF
TX2IE
OERR
TX1
RC2IF
RC2IE
RX9D
TX0
PIE2
RCSTA2
TXREG2
TXSTA2
SPBRG2
CREN
TX4
TX6
TX3
—
CSRC
TX9
TXEN
SYNC
—
TRMT
TX9D
Baud Rate Generator Register
x= unknown, u= unchanged, -= unimplemented, read as a '0'. Shaded cells are not used for synchronous master transmission.
FIGURE 14-8:
SYNCHRONOUS TRANSMISSION
Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit0
bit1
bit2
bit7
bit0
DT
(RX/DT pin)
Word 1
Word 2
CK
(TX/CK pin)
Write to
TXREG
Write Word 2
Write Word 1
TXIF
Interrupt Flag
TRMT
'1'
TXEN
FIGURE 14-9:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
DT
bit0
bit2
bit1
bit6
bit7
(RX/DT pin)
CK
(TX/CK pin)
Write to
TXREG
TXIF bit
TRMT bit
DS30289C-page 128
1998-2013 Microchip Technology Inc.
PIC17C7XX
Steps to follow when setting up a Synchronous Master
Reception:
14.3.2
USART SYNCHRONOUS MASTER
RECEPTION
1. Initialize the SPBRG register for the appropriate
baud rate. See Section 14.1 for details.
Once Synchronous mode is selected, reception is
enabled by setting either the SREN (RCSTA<5>) bit or
the CREN (RCSTA<4>) bit. Data is sampled on the RX/
DT pin on the falling edge of the clock. If SREN is set,
then only a single word is received. If CREN is set, the
reception is continuous until CREN is reset. If both bits
are set, then CREN takes precedence. After clocking
the last bit, the received data in the Receive Shift
Register (RSR) is transferred to RCREG (if it is empty).
If the transfer is complete, the interrupt bit RCIF is set.
The actual interrupt can be enabled/disabled by set-
ting/clearing the RCIE bit. RCIF is a read only bit which
is reset by the hardware. In this case, it is reset when
RCREG has been read and is empty. RCREG is a dou-
ble buffered register; i.e., it is a two deep FIFO. It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin
shifting into the RSR. On the clocking of the last bit of
the third byte, if RCREG is still full, then the overrun
error bit OERR (RCSTA<1>) is set. The word in the
RSR will be lost. RCREG can be read twice to retrieve
the two bytes in the FIFO. The OERR bit has to be
cleared in software. This is done by clearing the CREN
bit. If OERR is set, transfers from RSR to RCREG are
inhibited, so it is essential to clear the OERR bit if it is
set. The 9th receive bit is buffered the same way as the
receive data. Reading the RCREG register will allow
the RX9D and FERR bits to be loaded with values for
the next received data; therefore, it is essential for the
user to read the RCSTA register before reading
RCREG in order not to lose the old FERR and RX9D
information.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
6. The RCIF bit will be set when reception is com-
plete and an interrupt will be generated if the
RCIE bit was set.
7. Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
8. Read the 8-bit received data by reading
RCREG.
9. If any error occurred, clear the error by clearing
CREN.
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic so that it will
be in the proper state when receive is re-
enabled.
FIGURE 14-10:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3 Q4Q1Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1 Q2Q3 Q4Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4
DT
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
(RX/DT pin)
CK
(TX/CK pin)
Write to the
SREN bit
SREN bit
CREN bit
'0'
'0'
RCIF bit
Read
RCREG
Note: Timing diagram demonstrates SYNC Master mode with SREN = 1.
1998-2013 Microchip Technology Inc.
DS30289C-page 129
PIC17C7XX
TABLE 14-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
16h, Bank 1
17h, Bank 1
13h, Bank 0
14h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
14h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
RX2
TX1IF
TX1IE
OERR
RX1
RC1IF
RC1IE
RX9D
RX0
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
RCREG1
TXSTA1
SPBRG1
PIR2
RX9
RX6
TX9
SREN
RX5
CREN
RX4
—
RX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud Rate Generator Register
SSPIF
SSPIE
SPEN
RX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
RX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
RX2
TX2IF
TX2IE
OERR
RX1
RC2IF
RC2IE
RX9D
RX0
PIE2
RCSTA2
RCREG2
TXSTA2
SPBRG2
CREN
RX4
SYNC
RX6
RX3
—
CSRC
TX9
TXEN
—
TRMT
TX9D
Baud Rate Generator Register
x= unknown, u= unchanged, -= unimplemented, read as a '0'. Shaded cells are not used for synchronous master reception.
DS30289C-page 130
1998-2013 Microchip Technology Inc.
PIC17C7XX
14.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
14.4 USART Synchronous Slave Mode
The Synchronous Slave mode differs from the Master
mode, in the fact that the shift clock is supplied exter-
nally at the TX/CK pin (instead of being supplied inter-
nally in the Master mode). This allows the device to
transfer or receive data in the SLEEP mode. The Slave
mode is entered by clearing the CSRC (TXSTA<7>) bit.
Operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode. Also, SREN is a “don't care” in Slave mode.
If receive is enabled (CREN) prior to the SLEEPinstruc-
tion, then a word may be received during SLEEP. On
completely receiving the word, the RSR will transfer the
data to RCREG (setting RCIF) and if the RCIE bit is set,
the interrupt generated will wake the chip from SLEEP.
If the global interrupt is enabled, the program will
branch to the interrupt vector (0020h).
14.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the SYNC Master and Slave modes
are identical except in the case of the SLEEP mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to TXREG and then the SLEEP
instruction executes, the following will occur. The first
word will immediately transfer to the TSR and will trans-
mit as the shift clock is supplied. The second word will
remain in TXREG. TXIF will not be set. When the first
word has been shifted out of TSR, TXREG will transfer
the second word to the TSR and the TXIF flag will now
be set. If TXIE is enabled, the interrupt will wake the
chip from SLEEP and if the global interrupt is enabled,
then the program will branch to the interrupt vector
(0020h).
1. Enable the synchronous master serial port by
setting the SYNC and SPEN bits and clearing
the CSRC bit.
2. If interrupts are desired, then set the RCIE bit.
3. If 9-bit reception is desired, then set the RX9 bit.
4. To enable reception, set the CREN bit.
5. The RCIF bit will be set when reception is com-
plete and an interrupt will be generated if the
RCIE bit was set.
Steps to follow when setting up a Synchronous Slave
Transmission:
6. Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
1. Enable the synchronous slave serial port by set-
ting the SYNC and SPEN bits and clearing the
CSRC bit.
7. Read the 8-bit received data by reading
RCREG.
8. If any error occurred, clear the error by clearing
the CREN bit.
2. Clear the CREN bit.
3. If interrupts are desired, then set the TXIE bit.
4. If 9-bit transmission is desired, then set the TX9
bit.
Note: To abort reception, either clear the SPEN
bit, or the CREN bit (when in Continuous
Receive mode). This will reset the receive
logic, so that it will be in the proper state
when receive is re-enabled.
5. If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
6. Start transmission by loading data to TXREG.
7. Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN), allows transmission to
start sooner than doing these two events in the reverse
order.
Note: To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is re-
enabled.
1998-2013 Microchip Technology Inc.
DS30289C-page 131
PIC17C7XX
TABLE 14-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
MCLR, WDT
16h, Bank 1
17h, Bank 1
13h, Bank 0
15h, Bank 0
16h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
16h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
CSRC
TX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
—
TX1IF
TX1IE
OERR
TRMT
TX1
RC1IF
RC1IE
RX9D
TX9D
TX0
x000 0010
0000 0000
0000 -00x
0000 --1x
xxxx xxxx
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
0000 --1u
uuuu uuuu
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
TXSTA1
TXREG1
SPBRG1
PIR2
RX9
TX9
TX6
SREN
TXEN
TX5
CREN
SYNC
TX4
—
—
TX3
TX2
Baud Rate Generator Register
SSPIF
SSPIE
SPEN
TX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
TX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
TX2
TX2IF
TX2IE
OERR
TX1
RC2IF
RC2IE
RX9D
TX0
PIE2
RCSTA2
TXREG2
TXSTA2
SPBRG2
CREN
TX4
TX6
TX3
—
CSRC
TX9
TXEN
SYNC
—
TRMT
TX9D
Baud Rate Generator Register
x= unknown, u= unchanged, -= unimplemented, read as a '0'. Shaded cells are not used for synchronous slave transmission.
TABLE 14-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
POR,
BOR
MCLR, WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank1
17h, Bank1
13h, Bank0
14h, Bank0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
14h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
PIR1
RBIF
RBIE
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
RX2
TX1IF
TX1IE
OERR
RX1
RC1IF
RC1IE
RX9D
RX0
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
PIE1
RCSTA1
RCREG1
TXSTA1
SPBRG1
PIR2
RX9
RX6
TX9
SREN
RX5
CREN
RX4
—
RX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud Rate Generator Register
SSPIF
SSPIE
SPEN
RX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
RX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
RX2
TX2IF
TX2IE
OERR
RX1
RC2IF
RC2IE
RX9D
RX0
PIE2
RCSTA2
RCREG2
TXSTA2
SPBRG2
CREN
RX4
SYNC
RX6
RX3
—
CSRC
TX9
TXEN
—
TRMT
TX9D
Baud Rate Generator Register
x= unknown, u= unchanged, -= unimplemented, read as a '0'. Shaded cells are not used for synchronous slave reception.
DS30289C-page 132
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 15-2:
I2C SLAVE MODE BLOCK
DIAGRAM
15.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Internal
Data Bus
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Read
Write
SSPBUF reg
SCL
SDA
Shift
Clock
• Serial Peripheral Interface (SPI)
• Inter-Integrated CircuitTM (I2C)
SSPSR reg
MSb
LSb
Figure 15-1 shows a block diagram for the SPI mode,
while Figure 15-2 and Figure 15-3 show the block
diagrams for the two different I2C modes of operation.
Addr Match
or General
Match Detect
Call Detected
FIGURE 15-1:
SPI MODE BLOCK
DIAGRAM
SSPADD reg
Set, Reset
S, P bits
(SSPSTAT reg)
START and
STOP bit Detect
Internal
Data Bus
Read
Write
SSPBUF reg
SSPSR reg
FIGURE 15-3:
I2C MASTER MODE
BLOCK DIAGRAM
Internal
Data Bus
Shift
Clock
SDI
bit0
Read
Write
SSPADD<6:0>
7
SDO
Baud Rate Generator
Control
Enable
SS
SSPBUF reg
SSPSR reg
SCL
SS
Shift
Clock
Edge
Select
2
SDA
MSb
LSb
Clock Select
SSPM3:SSPM0
Addr Match
or General
Call Detected
Match detect
SSPADD reg
SMP:CKE
2
4
TMR2 Output
2
Edge
Select
Tosc
Prescaler
4, 16, 64
SCK
Set/Clear S bit
and
Clear/Set P, bit
(SSPSTAT reg)
and Set SSPIF
START and STOP bit
Detect/Generate
Data to TX/RX in SSPSR
Data Direction bit
1998-2013 Microchip Technology Inc.
DS30289C-page 133
PIC17C7XX
REGISTER 15-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2C Master or Slave mode:
1= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for High Speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select (Figure 15-6, Figure 15-8 and Figure 15-9)
CKP = 0:
1= Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1:
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a STOP bit has been detected last (this bit is '0' on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a START bit has been detected last (this bit is '0' on RESET)
0 = START bit was not detected last
R/W: Read/Write bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or not ACK bit.
In I2C Slave mode:
1= Read
0= Write
In I2C Master mode:
1= Transmit is in progress
0= Transmit is not in progress
Or’ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1
bit 0
UA: Update Address (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset ’1’ = Bit is set
DS30289C-page 134
1998-2013 Microchip Technology Inc.
PIC17C7XX
REGISTER 15-2: SSPCON1:SYNCSERIALPORTCONTROLREGISTER1(ADDRESS11h,BANK6)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPM0
bit 0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
bit 7
bit 7
WCOL: Write Collision Detect bit
Master mode:
2
1= A write to the SSPBUF register was attempted while the I C conditions were not valid for a
transmission to be started
0= No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared
in software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave
mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting
overflow. In Master mode, the overflow bit is not set, since each new reception (and
transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software.)
0 = No overflow
2
In I C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
“don’t care” in Transmit mode. (Must be cleared in software.)
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1= Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
2
In I C mode:
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
In SPI mode, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
2
In I C Slave mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
2
In I C Master mode:
Unused in this mode
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
2
2
2
0110= I C Slave mode, 7-bit address
0111= I C Slave mode, 10-bit address
1000= I C Master mode, clock = FOSC / (4 * (SSPADD+1) )
1xx1= Reserved
1x1x= Reserved
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset
1998-2013 Microchip Technology Inc.
DS30289C-page 135
PIC17C7XX
REGISTER 15-3: SSPCON2:SYNCSERIALPORTCONTROLREGISTER2(ADDRESS12h,BANK6)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
GCEN: General Call Enable bit (in I2C Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (in I2C Master mode only)
In Master Transmit mode:
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (in I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit AKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 3
bit 2
RCEN: Receive Enable bit (in I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
PEN: STOP Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0= STOP condition idle
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 1
bit 0
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition idle
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
SEN: START Condition Enabled bit (In I2C Master mode only)
1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0= START condition idle.
Note: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset ’1’ = Bit is set
DS30289C-page 136
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 15-4:
MSSP BLOCK DIAGRAM
(SPI MODE)
15.1 SPI Mode
The SPI mode allows 8-bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
Internal
Data Bus
Read
Write
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
SSPBUF reg
Additionally, a fourth pin may be used when in a Slave
mode of operation:
SSPSR reg
Shift
SDI
bit0
• Slave Select (SS)
Clock
15.1.1
OPERATION
SDO
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
Control
Enable
SS
control
bits
in
the
SSPCON1
register
(SSPCON1<5:0>) and SSPSTAT<7:6>. These control
bits allow the following to be specified:
SS
Edge
Select
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
2
Clock Select
• Data Input Sample Phase
(middle or end of data output time)
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
2
• Clock Edge
(output data on rising/falling edge of SCK)
Edge
Select
Tosc
• Clock Rate (Master mode only)
Prescaler
4, 16, 64
SCK
• Slave Select mode (Slave mode only)
Figure 15-4 shows the block diagram of the MSSP
module when in SPI mode.
Data to TX/RX in SSPSR
Data Direction bit
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit BF
(SSPSTAT<0>) and the interrupt flag bit SSPIF
(PIR2<7>) are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON1<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPBUF register completed successfully.
1998-2013 Microchip Technology Inc.
DS30289C-page 137
PIC17C7XX
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 15-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
15.1.2
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
registers and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the DDR register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have DDRB<7> cleared
• SCK (Master mode) must have DDRB<6> cleared
• SCK (Slave mode) must have DDRB<6> set
• SS must have PORTA<2> set
EXAMPLE 15-1:
LOADING THE SSPBUF
(SSPSR) REGISTER
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (DDR) register to the opposite value.
MOVLB 6
; Bank 6
LOOP BTFSS SSPSTAT, BF
; Has data been
;
;
;
received
(transmit
complete)?
15.1.3
TYPICAL CONNECTION
Figure 15-5 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
GOTO LOOP
; No
MOVPF SSPBUF, RXDATA ; Save in user RAM
MOVFP TXDATA, SSPBUF ; New data to xmit
The SSPSR is not directly readable, or writable and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
• Master sends data—Slave sends dummy data
• Master sends data—Slave sends data
• Master sends dummy data—Slave sends data
FIGURE 15-5:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
Shift Register
(SSPSR)
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
DS30289C-page 138
1998-2013 Microchip Technology Inc.
PIC17C7XX
Figure 15-6, Figure 15-8 and Figure 15-9, where the
MSb is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
15.1.4
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 15-5) is to broad-
cast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
This allows a maximum bit clock frequency (at 33 MHz)
of 8.25 MHz.
Figure 15-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON1<4>). This then, would give
waveforms for SPI communication as shown in
FIGURE 15-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 clock
modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit6
bit6
bit2
bit2
bit5
bit5
bit4
bit4
bit1
bit1
bit0
bit0
SDO
(CKE = 0)
bit7
bit7
bit3
bit3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
1998-2013 Microchip Technology Inc.
DS30289C-page 139
PIC17C7XX
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
15.1.5
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR2<7>)
is set.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with
CKE = '1', then the SS pin control must be
enabled.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level, or clearing the SSPEN bit.
15.1.6
SLAVE SELECT
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The RA2 Data Latch must be high. When the SS pin
is low, transmission and reception are enabled and
FIGURE 15-7:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit7
bit7
bit0
bit0
SDO
bit7
SDI
(SMP = 0)
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
DS30289C-page 140
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 15-8:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit3
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
FIGURE 15-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
bit0
SDO
bit7
bit7
bit3
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
1998-2013 Microchip Technology Inc.
DS30289C-page 141
PIC17C7XX
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP inter-
rupt flag bit will be set and if enabled, will wake the
device from SLEEP.
15.1.7
SLEEP OPERATION
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
15.1.8
EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
TABLE 15-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR MCLR, WDT
07h, Unbanked INTSTA
PEIF T0CKIF
SSPIF BCLIF
SSPIE BCLIE
T0IF
ADIF
ADIE
INTF
—
PEIE T0CKIE
CA4IF CA3IF
CA4IE CA3IE
T0IE
TX2IF
TX2IE
INTE
RC2IF
RC2IE
0000 0000 0000 0000
000- 0010 000- 0010
000- 0000 000- 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
10h, Bank 4
11h, Bank 4
14h, Bank 6
11h, Bank 6
13h, Bank 6
PIR2
PIE2
—
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
SSPSTAT SMP CKE D/A R/W UA BF
P
S
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
DS30289C-page 142
1998-2013 Microchip Technology Inc.
PIC17C7XX
2
FIGURE 15-11:
I2C MASTER MODE
BLOCK DIAGRAM
15.2 MSSP I C Operation
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Internal
Data Bus
Read
SSPADD<6:0>
7
Write
Baud Rate Generator
Refer to Application Note AN578, “Use of the SSP
SSPBUF reg
SSPSR reg
Module in the I 2C Multi-Master Environment.”
SCL
A “glitch” filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
Shift
Clock
SDA
MSb
LSb
I2C SLAVE MODE BLOCK
DIAGRAM
Addr Match
Match Detect
FIGURE 15-10:
Internal
Data Bus
SSPADD reg
Read
Write
Set/Clear S bit
and
Clear/Set P, bit
(SSPSTAT reg)
START and STOP bit
Detect/Generate
SSPBUF reg
SCL
SDA
and Set SSPIF
Shift
Two pins are used for data transfer. These are the SCL
pin, which is the clock and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
ured when the I2C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON1<5>).
Clock
SSPSR reg
MSb
LSb
Addr Match
Match Detect
The MSSP module has six registers for I2C operation.
These are the:
SSPADD reg
• SSP Control Register1 (SSPCON1)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
Set, Reset
S, P bits
(SSPSTAT reg)
START and
STOP bit Detect
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
The SSPCON1 register allows control of the I2C oper-
ation. Four mode selection bits (SSPCON1<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I2C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate DDR bits. Selecting an I2C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I2C mode.
1998-2013 Microchip Technology Inc.
DS30289C-page 143
PIC17C7XX
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a START
or STOP bit, specifies if the received byte was data or
address if the next byte is the completion of 10-bit
address and if this will be a read or write data transfer.
15.2.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data when required (slave-
transmitter).
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON1<6>) is set and the byte in the
SSPSR is lost.
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overflow bit SSPOV (SSPCON1<6>) was
set before the transfer was received.
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF, but bit SSPIF and SSPOV are
set. Table 15-2 shows what happens when a data
transfer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification, as well as the requirement of
the MSSP module, are shown in timing parameter #100
and parameter #101 of the Electrical Specifications.
DS30289C-page 144
1998-2013 Microchip Technology Inc.
PIC17C7XX
5. Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
15.2.1.1
Addressing
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
a) The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
Note: Following the Repeated Start condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
b) The buffer full bit, BF, is set on the falling edge
of the 8th SCL pulse.
c) An ACK pulse is generated.
15.2.1.2
Slave Reception
d) SSP interrupt flag bit, SSPIF (PIR2<7>), is set
(interrupt is generated if enabled) - on the falling
edge of the 9th SCL pulse.
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘1111 0
A9 A8 0’, where A9 and A8 are the two MSbs of the
address. The sequence of events for a 10-bit address is
as follows, with steps 7- 9 for slave-transmitter:
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set,
or bit SSPOV (SSPCON1<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR2<7>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
1. Receive first (high) byte of Address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSP-
BUF is updated.
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF and UA are set).
TABLE 15-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Generate ACK
Transfer is Received
SSPSR SSPBUF
Pulse
BF
SSPOV
0
1
1
0
0
0
1
1
Yes
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
1998-2013 Microchip Technology Inc.
DS30289C-page 145
PIC17C7XX
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
15.2.1.3
Slave Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then
SCL pin should be enabled by setting bit CKP
(SSPCON1<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA sig-
nal is valid during the SCL high time (Figure 15-13).
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the not ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then, the SCL pin
should be enabled by setting the CKP bit.
FIGURE 15-12:
I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W = 0
ACK
Not
ACK
Receiving Address
A7 A6 A5 A4
Receiving Data
Receiving Data
ACK
SDA
A3 A2 A1
D7 D6 D5 D4 D3 D2
D0
8
D7 D6
D5
D4 D3
D2
D0
8
D1
7
D1
7
3
9
7
1
2
4
9
5
4
3
6
9
5
6
1
2
3
6
1
2
4
8
5
P
SCL
S
SSPIF
Bus Master
Terminates
Transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON1<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
FIGURE 15-13:
I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
Transmitting Data Not ACK
D7 D6 D5 D4 D3 D2 D1 D0
R/W = 1
Receiving Address
A7 A6 A5 A4 A3 A2 A1
ACK
SDA
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP (SSPCON1<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
DS30289C-page 146
1998-2013 Microchip Technology Inc.
PIC17C7XX
2
FIGURE 15-14:
I C SLAVE-TRANSMITTER (10-BIT ADDRESS)
1998-2013 Microchip Technology Inc.
DS30289C-page 147
PIC17C7XX
2
FIGURE 15-15:
I C SLAVE-RECEIVER (10-BIT ADDRESS)
DS30289C-page 148
1998-2013 Microchip Technology Inc.
PIC17C7XX
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF flag is set.
15.2.2
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF to determine if the address was device spe-
cific, or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set, while the slave is config-
ured in 10-bit address mode, then the second half of
the address is not necessary, the UA bit will not be set
and the slave will begin receiving data after the
acknowledge (Figure 15-16).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a START bit detect, 8-bits are shifted
into SSPSR and the address is compared against
SSPADD and is also compared to the general call
address, fixed in hardware.
FIGURE 15-16:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set Interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
ACK
General Call Address
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in Software
SSPBUF is Read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
'0'
'1'
1998-2013 Microchip Technology Inc.
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PIC17C7XX
15.2.3
SLEEP OPERATION
15.2.4
EFFECTS OF A RESET
While in SLEEP mode, the I2C module can receive
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
A RESET disables the SSP module and terminates the
current transfer.
TABLE 15-3: REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
MCLR, WDT
07h, Unbanked INTSTA
PEIF
SSPIF
SSPIE
T0CKIF
BCLIF
BCLIE
T0IF
ADIF
ADIE
INTF
—
PEIE
CA4IF
CA4IE
T0CKIE
CA3IF
CA3IE
T0IE
TX2IF
TX2IE
INTE
RC2IF
RC2IE
0000 0000
000- 0000
0000 0000
000- 0000
10h, Bank 4
11h, Bank 4
10h. Bank 6
14h, Bank 6
PIR2
PIE2
—
000- 0000
0000 0000
000- 0000
0000 0000
SSPADD
SSPBUF
Synchronous Serial Port (I2C mode) Address Register
Synchronous Serial Port Receive Buffer/Transmit Register
SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
GCEN ACKSTAT ACKDT ACKEN
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
11h, Bank 6
12h, Bank 6
SSPCON1 WCOL
SSPCON2
RCEN
S
PEN
R/W
RSEN
UA
SEN
BF
13h, Bank 6
Legend:
SSPSTAT
SMP
CKE
D/A
P
x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the SSP in I2C mode.
DS30289C-page 150
1998-2013 Microchip Technology Inc.
PIC17C7XX
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
15.2.5
MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I2C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
2
FIGURE 15-17:
SSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
SCL
START bit Detect,
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
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15.2.6
MULTI-MASTER MODE
15.2.7.1
I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer
is ended with a STOP condition or with a Repeated
Start condition. Since the Repeated Start condition is
also the beginning of the next serial transfer, the I2C
bus will not be released.
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET, or
when the MSSP module is disabled. Control of the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the STOP condition occurs.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In Multi-Master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address, followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
• Data Transfer
• A START Condition
• A Repeated Start Condition
• An Acknowledge Condition
15.2.7
I2C MASTER MODE SUPPORT
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz, or 1 MHz I2C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the SSP-
BUF. Once the given operation is complete (i.e., trans-
mission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
• Assert a START condition on SDA and SCL.
• Assert a Repeated Start condition on SDA and
SCL.
• Write to the SSPBUF register initiating
transmission of data/address.
• Generate a STOP condition on SDA and SCL.
• Configure the I2C port to receive data.
• Generate an Acknowledge condition at the end of
a received byte of data.
Note: The MSSP Module, when configured in I2C
Master mode, does not allow queueing of
events. For instance: The user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
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A typical transmit sequence would go as follows:
15.2.8
BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 15-18). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
remented twice per instruction cycle (TCY), on the Q2
and Q4 clock.
a) The user generates a START Condition by set-
ting the START enable bit (SEN) in SSPCON2.
b) SSPIF is set. The module will wait the required
START time before any other operation takes
place.
c) The user loads the SSPBUF with address to
transmit.
In I2C Master mode, the BRG is reloaded automatically.
If Clock Arbitration is taking place, for instance, the
BRG will be reloaded when the SCL pin is sampled
high (Figure 15-19).
d) Address is shifted out the SDA pin until all 8 bits
are transmitted.
e) The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
FIGURE 15-18:
BAUD RATE GENERATOR
BLOCK DIAGRAM
g) The user loads the SSPBUF with eight bits of data.
h) DATA is shifted out the SDA pin until all 8 bits are
transmitted.
SSPM3:SSPM0
SSPADD<6:0>
i) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
Reload
Reload
SSPM3:SSPM0
SCL
Control
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
FOSC/4
BRG Down Counter
CLKOUT
k) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
l) Interrupt is generated once the STOP condition
is complete.
FIGURE 15-19:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high.
SCL de-asserted but slave holds
SCL low (clock arbitration).
SCL
BRG decrements
(on Q2 and Q4 cycles).
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count.
BRG
Reload
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15.2.9
I2C MASTER MODE START
CONDITION TIMING
15.2.9.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended,
leaving the SDA line held low and the START condition
is complete.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
Note: If at the beginning of START condition, the
SDA and SCL pins are already sampled
low, or if during the START condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs.
The Bus Collision Interrupt Flag (BCLIF) is
set, the START condition is aborted and
the I2C module is reset into its IDLE state.
FIGURE 15-20:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here.
SDA = 1,
At completion of START bit,
Hardware clears SEN bit
and sets SSPIF bit.
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here.
2nd Bit
1st Bit
SDA
TBRG
SCL
TBRG
S
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PIC17C7XX
FIGURE 15-21:
START CONDITION FLOW CHART
SSPEN = 1,
SSPCON1<3:0> = 1000
Idle Mode
SEN (SSPCON2<0> = 1)
Bus Collision Detected,
No
Set BCLIF,
Release SCL,
Clear SEN
SDA = 1?
SCL = 1?
Yes
Load BRG with
SSPADD<6:0>
No
No
Yes
No
BRG
Rollover?
SCL= 0?
SDA = 0?
Yes
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>,
Set S bit.
BRG
Rollover?
No
No
SCL = 0?
Yes
Yes
Reset BRG
Force SCL = 0,
START Condition Done,
Clear SEN
and set SSPIF
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15.2.10 I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in 7-
bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C mod-
ule is in the idle state. When the RSEN bit is set, the
SCL pin is asserted low. When the SCL pin is sampled
low, the baud rate generator is loaded with the contents
of SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (TBRG). When the baud rate generator times out,
if SDA is sampled high, the SCL pin will be de-asserted
(brought high). When SCL is sampled high the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG. This action is then
followed by assertion of the SDA pin (SDA is low) for
one TBRG while SCL is high. Following this, the RSEN
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator is not reloaded,
leaving the SDA pin held low. As soon as a START con-
dition is detected on the SDA and SCL pins, the S bit
(SSPSTAT<3>) will be set. The SSPIF bit will not be set
until the baud rate generator has timed out.
15.2.10.1 WCOL status flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If the RSEN is programmed while any
other event is in progress, it will not take
effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data “1”.
FIGURE 15-22:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SDA = 1,
SCL = 1
At completion of START bit,
hardware clear RSEN bit
and set SSPIF
SCL (no change)
TBRG
TBRG
TBRG
1st Bit
SDA
Write to SSPBUF occurs here
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated Start
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FIGURE 15-23:
REPEATED START CONDITION FLOW CHART (PAGE 1)
Start
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
B
RSEN = 1
Force SCL = 0
No
SCL = 0?
Yes
Release SDA,
Load BRG with
SSPADD<6:0>
No
BRG
Rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
Bus Collision,
Set BCLIF,
Release SDA,
Clear RSEN
No
SDA = 1?
Yes
Load BRG with
SSPADD<6:0>
C
A
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FIGURE 15-24:
REPEATED START CONDITION FLOW CHART (PAGE 2)
B
C
A
Yes
No
No
No
BRG
Rollover?
SDA = 0?
SCL = 1?
Yes
Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>
Set S
No
No
BRG
Rollover?
SCL = '0'?
Yes
Yes
Force SCL = 0,
Repeated Start
condition done,
Clear RSEN,
Reset BRG
Set SSPIF.
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15.2.11 I2C MASTER MODE
TRANSMISSION
15.2.11.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit address, is accomplished by simply writ-
ing a value to SSPBUF register. This action will set the
buffer full flag (BF) and allow the baud rate generator to
begin counting and start the next transmission. Each bit
of address/data will be shifted out onto the SDA pin
after the falling edge of SCL is asserted (see data hold
time spec). SCL is held low for one baud rate generator
roll over count (TBRG). Data should be valid before SCL
is released high (see Data setup time spec). When the
SCL pin is released high, it is held that way for TBRG,
the data on the SDA pin must remain stable for that
duration and some hold time after the next falling edge
of SCL. After the eighth bit is shifted out (the falling
edge of the eighth clock), the BF flag is cleared and the
master releases SDA, allowing the slave device being
addressed to respond with an ACK bit during the ninth
bit time, if an address match occurs or if data was
received properly. The status of ACK is read into the
ACKDT on the falling edge of the ninth clock. If the
master receives an acknowledge, the acknowledge
status bit (AKSTAT) is cleared. If not, the bit is set. After
the ninth clock, the SSPIF is set and the master clock
(baud rate generator) is suspended until the next data
byte is loaded into the SSPBUF, leaving SCL low and
SDA unchanged (Figure 15-26).
15.2.11.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
15.2.11.3 AKSTAT Status Flag
In Transmit mode, the AKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge (ACK
= 0) and is set when the slave does not acknowledge
(ACK = 1). A slave sends an acknowledge when it has
recognized its address (including a general call), or
when the slave has properly received its data.
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin, allowing the slave to respond with an
acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
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FIGURE 15-25:
MASTER TRANSMIT FLOW CHART
Idle Mode
Write SSPBUF
Num_Clocks = 0,
BF = 1
Force SCL = 0
Release SDA so
Slave can drive ACK,
Force BF = 0
Yes
Num_Clocks
= 8?
No
Load BRG with
SSPADD<6:0>,
start BRG count
Load BRG with
SSPADD<6:0>,
Start BRG Count,
SDA = Current Data bit
No
BRG
Rollover?
BRG
No
Rollover?
Yes
Yes
Force SCL = 1,
Stop BRG
Stop BRG,
Force SCL = 1
(Clock Arbitration)
No
(Clock Arbitration)
SCL = 1?
Yes
No
SCL = 1?
Yes
Read SDA and place into
ACKSTAT bit (SSPCON2<6>)
Bus Collision Detected
No
SDA =
Data bit?
Set BCLIF, Hold Prescale Off,
Clear XMIT Enable
Load BRG with
SSPADD<6:0>,
Count High Time
Yes
Load BRG with
SSPADD<6:0>,
Count SCL High Time
No
Rollover?
Yes
No
No
No
SDA =
Data bit?
BRG
Rollover?
Yes
SCL = 0?
Force SCL = 0,
Set SSPIF
Yes
Yes
Reset BRG
Num_Clocks
= Num_Clocks + 1
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2
FIGURE 15-26:
I C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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15.2.12 I2C MASTER MODE RECEPTION
15.2.12.1 BF Status Flag
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
Note: The SSP Module must be in an IDLE
STATE before the RCEN bit is set, or the
RCEN bit will be disregarded.
15.2.12.2 SSPOV Status Flag
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already set
from a previous reception.
The baud rate generator begins counting and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally cleared. The user can then send an acknowledge
bit at the end of reception, by setting the acknowledge
sequence enable bit, ACKEN (SSPCON2<4>).
15.2.12.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
DS30289C-page 162
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FIGURE 15-27:
MASTER RECEIVER FLOW CHART
Idle Mode
RCEN = 1
Num_Clocks = 0,
Release SDA
Force SCL=0,
Load BRG w/
SSPADD<6:0>,
Start Count
BRG
No
Rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
Sample SDA,
Shift Data into SSPSR
Load BRG with
SSPADD<6:0>,
Start Count.
No
No
BRG
SCL = 0?
Yes
Rollover?
Yes
Num_Clocks
= Num_Clocks + 1
No
Num_Clocks
= 8?
Yes
Force SCL = 0,
Set SSPIF,
Set BF.
Move Contents of SSPSR
into SSPBUF,
Clear RCEN.
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2
FIGURE 15-28:
I C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
DS30289C-page 164
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15.2.13 ACKNOWLEDGE SEQUENCE
TIMING
15.2.13.1 WCOL Status Flag
If the user writes the SSPBUF when an acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
An acknowledge sequence is enabled by setting the
acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data bit
is presented on the SDA pin. If the user wishes to gen-
erate an acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(TBRG), and the SCL pin is de-asserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the baud rate generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is
automatically cleared, the baud rate generator is turned
off and the SSP module then goes into IDLE mode
(Figure 15-29).
FIGURE 15-29:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge Sequence Starts Here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN Automatically Cleared
TBRG
TBRG
SDA
SCL
D0
8
ACK
9
SSPIF
Cleared in
Software
Set SSPIF at the End
of Receive
Cleared in
Software
Set SSPIF at the End
of Acknowledge Sequence
Note: TBRG = one baud rate generator period.
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DS30289C-page 165
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FIGURE 15-30:
ACKNOWLEDGE FLOW CHART
Idle Mode
Set ACKEN
Force SCL = 0
BRG
Yes
Rollover?
No
No
SCL = 0?
Yes
Yes
Force SCL = 0,
Clear ACKEN
Set SSPIF
SCL = 0?
No
Reset BRG
Drive ACKDT bit
(SSPCON2<5>)
onto SDA pin,
Load BRG with
SSPADD<6:0>,
Start Count.
No
ACKDT = 1?
Yes
No
BRG
Rollover?
Yes
SDA = 1?
No
Yes
Force SCL = 1
Bus Collision Detected,
Set BCLIF,
Release SCL,
Clear ACKEN
No
SCL = 1?
Yes
(Clock Arbitration)
Load BRG with
SSPADD <6:0>,
Start Count.
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15.2.14 STOP CONDITION TIMING
15.2.14.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/
transmit the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to ‘0’. When the baud rate generator times
out, the SCL pin will be brought high and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 15-31).
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
FIGURE 15-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set.
Falling Edge of
9th Clock
TBRG
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
SCL brought high after TBRG.
SDA asserted low before rising edge of clock
to setup STOP condition.
Note: TBRG = one baud rate generator period.
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FIGURE 15-32:
STOP CONDITION FLOW CHART
Idle Mode,
SSPEN = 1,
SSPCON1<3:0> = 1000
PEN = 1
Start BRG
Force SDA = 0
SCL Doesn’t Change
No
BRG
Rollover?
Yes
No
SDA = 0?
Release SDA,
Start BRG
Yes
Start BRG
No
BRG
Rollover?
No
BRG
Yes
Rollover?
Bus Collision Detected,
Set BCLIF,
No
Yes
P bit Set?
Yes
Clear PEN
De-assert SCL,
SCL = 1
SDA going from
0 to 1 while SCL = 1
(Clock Arbitration)
Set SSPIF,
No
STOP Condition done,
PEN cleared
SCL = 1?
Yes
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15.2.15 CLOCK ARBITRATION
15.2.16 SLEEP OPERATION
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated Start/Stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count, in the event that the clock is
held low by an external device (Figure 15-33).
While in SLEEP mode, the I2C module can receive
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
15.2.17 EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
FIGURE 15-33:
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG Overflow,
Release SCL,
If SCL = 1 Load BRG with
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SSPADD<6:0>, and Start Count
to measure high time interval.
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (TOSC 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
TBRG
TBRG
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If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine,
and if the I2C bus is free, the user can resume commu-
nication by asserting a START condition.
15.2.18 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
the I2C port to its IDLE state (Figure 15-34).
The master will continue to monitor the SDA and SCL
pins and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted and
the SSPBUF can be written to. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume communica-
tion by asserting a START condition.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the
I2C bus can be taken when the P bit is set in the SSP-
STAT register, or the bus is idle and the S and P bits
are cleared.
FIGURE 15-34:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source.
Data changes
while SCL = 0.
Bus collision has occurred.
SDA released
by master.
SDA
SCL
Set bus collision
interrupt.
BCLIF
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If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-37). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0 and during this time, if the SCL pin is
sampled as '0', a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
15.2.18.1 Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 15-35).
b) SCL is sampled low before SDA is asserted low
(Figure 15-36).
During a START condition, both the SDA and the SCL
pins are monitored.
Note: The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition and if the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start, or Stop conditions.
If:
the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 15-35).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 15-35:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable START
condition if SDA = 1, SCL=1.
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
1998-2013 Microchip Technology Inc.
DS30289C-page 171
PIC17C7XX
FIGURE 15-36:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1.
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF.
SCL = 0 before BRG time-out,
Bus collision occurs, Set BCLIF.
BCLIF
Interrupts cleared
in software.
S
'0'
'0'
'0'
'0'
SSPIF
FIGURE 15-37:
BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
Time-out.
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1.
'0'
BCLIF
S
SSPIF
Interrupts cleared
in software.
SDA = 0, SCL = 1
Set SSPIF.
DS30289C-page 172
1998-2013 Microchip Technology Inc.
PIC17C7XX
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
15.2.18.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, then
a bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
Start condition.
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low, the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is com-
plete (Figure 15-38).
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to ‘0’. The SCL pin is then de-
asserted and when sampled high, the SDA pin is sam-
pled. If SDA is low, a bus collision has occurred (i.e.,
another master is attempting to transmit a data ’0’). If,
however, SDA is sampled high, then the BRG is
FIGURE 15-38:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software.
'0'
'0'
'0'
S
'0'
SSPIF
FIGURE 15-39:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software.
'0'
'0'
'0'
'0'
S
SSPIF
1998-2013 Microchip Technology Inc.
DS30289C-page 173
PIC17C7XX
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0'. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs. This
is another case of another master attempting to drive a
data '0' (Figure 15-40).
15.2.18.3 Bus Collision During a STOP
Condition
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
FIGURE 15-40:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
Set BCLIF.
TBRG
TBRG
TBRG
SDA
SDA asserted low.
SCL
PEN
BCLIF
P
'0'
'0'
'0'
'0'
SSPIF
FIGURE 15-41:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high.
Set BCLIF.
Assert SDA.
SCL
PEN
BCLIF
P
'0'
'0'
SSPIF
DS30289C-page 174
1998-2013 Microchip Technology Inc.
PIC17C7XX
example, with a supply voltage of VDD = 5V +10% and
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 k VDD as a function of Rp is shown in Figure 15-
42. The desired noise margin of 0.1 VDD for the low
level, limits the maximum value of Rs. Series resistors
are optional and used to improve ESD susceptibility.
15.3 Connection Considerations for
2
I C Bus
For standard mode I2C bus devices, the values of
resistors Rp Rs in Figure 15-42 depends on the follow-
ing parameters:
• Supply voltage
The bus capacitance is the total capacitance of wire,
connections and pins. This capacitance limits the max-
imum value of Rp due to the specified rise time
(Figure 15-42).
• Bus capacitance
• Number of connected devices (input current +
leakage current)
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register and controls the slew rate of
the I/O pins when in I2C mode (master or slave).
The supply voltage limits the minimum value of resistor
Rp due to the specified minimum sink current of 3 mA
at VOL max = 0.4V for the specified output stages. For
FIGURE 15-42:
SAMPLE DEVICE CONFIGURATION FOR I2C BUS
VDD + 10%
DEVICE
R
R
p
p
R
R
s
s
SDA
SCL
C = 10 - 400 pF
b
2
Note: I C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is
also connected.
1998-2013 Microchip Technology Inc.
DS30289C-page 175
PIC17C7XX
15.4 Example Program
Example 15-2 shows MPLAB® C17 ’C’ code for using
the I2C module in Master mode to communicate with a
24LC01B serial EEPROM. This example uses the PIC®
MCU ‘C’ libraries included with MPLAB C17.
EXAMPLE 15-2:
INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB C17)
// Include necessary header files
#include <p17c756.h>
#include <delays.h>
#include <stdlib.h>
#include <i2c16.h>
// Processor header file
// Delay routines header file
// Standard Library header file
// I2C routines header file
#define CONTROL 0xa0
// Control byte definition for 24LC01B
// Function declarations
void main(void);
void WritePORTD(static unsigned char data);
void ByteWrite(static unsigned char address,static unsigned char data);
unsigned char ByteRead(static unsigned char address);
void ACKPoll(void);
// Main program
void main(void)
{
static unsigned char address;
static unsigned char datao;
static unsigned char datai;
// I2C address of 24LC01B
// Data written to 24LC01B
// Data read from 24LC01B
address = 0;
// Preset address to 0
OpenI2C(MASTER,SLEW_ON);
SSPADD = 39;
// Configure I2C Module Master mode, Slew rate control on
// Configure clock for 100KHz
while(address<128)
// Loop 128 times, 24LC01B is 128x8
{
datao = PORTB;
do
{
ByteWrite(address,datao);
// Write data to EEPROM
ACKPoll();
// Poll the 24LC01B for state
datai = ByteRead(address); // Read data from EEPROM into SSPBUF
} while(datai != datao);
// Loop as long as data not correctly
// written to 24LC01B
address++;
// Increment address
}
while(1)
{
// Done writing 128 bytes to 24LC01B, Loop forever
Nop();
}
}
DS30289C-page 176
1998-2013 Microchip Technology Inc.
PIC17C7XX
EXAMPLE 15-2:
INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB C17)
// Writes the byte data to 24LC01B at the specified address
void ByteWrite(static unsigned char address, static unsigned char data)
{
StartI2C();
// Send start bit
IdleI2C();
WriteI2C(CONTROL);
IdleI2C();
if (!SSPCON2bits.ACKSTAT)
{
// Wait for idle condition
// Send control byte
// Wait for idle condition
// If 24LC01B ACKs
WriteI2C(address);
IdleI2C();
// Send control byte
// Wait for idle condition
if (!SSPCON2bits.ACKSTAT)
WriteI2C(data);
}
// If 24LC01B ACKs
// Send data
IdleI2C();
StopI2C();
IdleI2C();
return;
// Wait for idle condition
// Send stop bit
// Wait for idle condition
}
// Reads a byte of data from 24LC01B at the specified address
unsigned char ByteRead(static unsigned char address)
{
StartI2C();
// Send start bit
IdleI2C();
WriteI2C(CONTROL);
// Wait for idle condition
// Send control byte
IdleI2C();
if (!SSPCON2bits.ACKSTAT)
// Wait for idle condition
// If the 24LC01B ACKs
{
WriteI2C(address);
// Send address
IdleI2C();
if (!SSPCON2bits.ACKSTAT)
// Wait for idle condition
// If the 24LC01B ACKs
{
RestartI2C();
// Send restart
IdleI2C();
WriteI2C(CONTROL+1);
IdleI2C();
if (!SSPCON2bits.ACKSTAT)
// Wait for idle condition
// Send control byte with R/W set
// Wait for idle condition
// If the 24LC01B ACKs
{
getcI2C();
IdleI2C();
NotAckI2C();
IdleI2C();
StopI2C();
IdleI2C();
}
// Read a byte of data from 24LC01B
// Wait for idle condition
// Send a NACK to 24LC01B
// Wait for idle condition
// Send stop bit
// Wait for idle condition
}
}
return(SSPBUF);
}
1998-2013 Microchip Technology Inc.
DS30289C-page 177
PIC17C7XX
EXAMPLE 15-2:
INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB C17)
void ACKPoll(void)
{
StartI2C();
IdleI2C();
WriteI2C(CONTROL);
IdleI2C();
// Send start bit
// Wait for idle condition
// Send control byte
// Wait for idle condition
// Poll the ACK bit coming from the 24LC01B
// Loop as long as the 24LC01B NACKs
while (SSPCON2bits.ACKSTAT)
{
RestartI2C();
IdleI2C();
WriteI2C(CONTROL);
IdleI2C();
// Send a restart bit
// Wait for idle condition
// Send control byte
// Wait for idle condition
}
IdleI2C();
StopI2C();
IdleI2C();
return;
// Wait for idle condition
// Send stop bit
// Wait for idle condition
}
DS30289C-page 178
1998-2013 Microchip Technology Inc.
PIC17C7XX
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D clock must be derived from the
A/D’s internal RC oscillator.
16.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has
twelve analog inputs for the PIC17C75X devices and
sixteen for the PIC17C76X devices.
The A/D module has four registers. These registers
are:
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the input
into the converter. The converter then generates a dig-
ital result of this analog level via successive approxima-
tion. This A/D conversion of the analog input signal,
results in a corresponding 10-bit digital number.
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Register 16-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 16-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RG3 and RG2 can also be the volt-
age references), or as digital I/O.
The analog reference voltages (positive and negative
supply) are software selectable to either the device’s
supply voltages (AVDD, AVss), or the voltage level on
the RG3/AN0/VREF+ and RG2/AN1/VREF- pins.
REGISTER 16-1: ADCON0 REGISTER (ADDRESS: 14h, BANK 5)
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
U-0
—
R/W-0
U-0
—
R/W-0
ADON
bit 0
GO/DONE
bit 7
bit 7-4
CHS3:CHS0: Analog Channel Select bits
0000= channel 0, (AN0)
0001= channel 1, (AN1)
0010= channel 2, (AN2)
0011= channel 3, (AN3)
0100= channel 4, (AN4)
0101= channel 5, (AN5)
0110= channel 6, (AN6)
0111= channel 7, (AN7)
1000= channel 8, (AN8)
1001= channel 9, (AN9)
1010= channel 10, (AN10)
1011= channel 11, (AN11)
1100= channel 12, (AN12) (PIC17C76X only)
1101= channel 13, (AN13) (PIC17C76X only)
1110= channel 14, (AN14) (PIC17C76X only)
1111= channel 15, (AN15) (PIC17C76X only)
11xx= RESERVED, do not select (PIC17C75X only)
bit 3
bit 2
Unimplemented: Read as '0'
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion, which is automatically
cleared by hardware when the A/D conversion is complete)
0= A/D conversion not in progress
bit 1
bit 0
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR Reset ’1’ = Bit is set
1998-2013 Microchip Technology Inc.
DS30289C-page 179
PIC17C7XX
REGISTER 16-2: ADCON1 REGISTER (ADDRESS 15h, BANK 5)
R/W-0
ADCS1
bit 7
R/W-0
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
ADCS0
PCFG3
PCFG2
PCFG1 PCFG0
bit 0
bit 7-6
bit 5
ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/8
01= FOSC/32
10= FOSC/64
11= FRC (clock derived from an internal RC oscillator)
ADFM: A/D Result Format Select
1= Right justified. 6 Most Significant bits of ADRESH are read as ’0’.
0= Left justified. 6 Least Significant bits of ADRESL are read as ’0’.
bit 4
Unimplemented: Read as '0'
bit 3-1
bit 0
PCFG3:PCFG1: A/D Port Configuration Control bits
PCFG0: A/D Voltage Reference Select bit
1= A/D reference is the VREF+ and VREF- pins
0= A/D reference is AVDD and AVSS
Note: When this bit is set, ensure that the A/D voltage reference specifications are met.
PCFG3:PCFG0
AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
D
000x
001x
010x
011x
100x
101x
110x
111x
A = Analog input
D = Digital I/O
Legend:
R = Readable bit
- n = Value at POR Reset ’1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS30289C-page 180
1998-2013 Microchip Technology Inc.
PIC17C7XX
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and A/D interrupt flag bit, ADIF is set. The block
diagrams of the A/D module are shown in Figure 16-1.
2. Configure A/D interrupt (if desired):
a) Clear ADIF bit
b) Set ADIE bit
c) Clear GLINTD bit
3. Wait the required acquisition time.
4. Start conversion:
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding DDR bits selected as inputs.
To determine sample time, see Section 16.1. After this
acquisition time has elapsed, the A/D conversion can
be started. The following steps should be followed for
doing an A/D conversion:
a) Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
a) Polling for the GO/DONE bit to be cleared
OR
b) Waiting for the A/D interrupt
6. Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF, if required.
1. Configure the A/D module:
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
a) Configure analog pins/voltage reference/
and digital I/O (ADCON1)
b) Select A/D input channel (ADCON0)
c) Select A/D conversion clock (ADCON0)
d) Turn on A/D module (ADCON0)
FIGURE 16-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1011
1011
1011
1011
(1)
AN15
(1)
AN14
(1)
AN13
(1)
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
VIN
0100
(Input Voltage)
AN4
0011
AN3
A/D
Converter
0010
AN2
0001
AN1/VREF-
PCFG0
0000
AN0/VREF+
VREF-
(Reference
Voltage)
AVSS
VREF+
AVDD
Note 1: These channels are only available on PIC16C76X devices.
1998-2013 Microchip Technology Inc.
DS30289C-page 181
PIC17C7XX
Figure 16-2 shows the conversion sequence and the
terms that are used. Acquisition time is the time that the
A/D module’s holding capacitor is connected to the
external voltage level. Then, there is the conversion
time of 12 TAD, which is started when the GO bit is set.
The sum of these two times is the sampling time. There
is a minimum acquisition time to ensure that the holding
capacitor is charged to a level that will give the desired
accuracy for the A/D conversion.
FIGURE 16-2:
A/D CONVERSION SEQUENCE
A/D Sample Time
Acquisition Time
A/D Conversion Time
A/D conversion complete, result is loaded in ADRES register.
Holding capacitor begins acquiring voltage level on selected
channel, ADIF bit is set.
When A/D conversion is started
(setting the GO bit).
When A/D holding capacitor starts to charge.
After A/D conversion, or when new A/D channel is selected.
DS30289C-page 182
1998-2013 Microchip Technology Inc.
PIC17C7XX
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
16.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-3. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 16-3. The maximum recommended
impedance for analog sources is 10 k. As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed) this acquisition must be done before the
conversion can be started.
Example 16-1 shows the calculation of the minimum
required acquisition time (TACQ). This is based on the
following application system assumptions.
CHOLD
Rs
Conversion Error
VDD
=
=
=
120 pF
10 k
1/2 LSb
5V Rss = 7 k
(see graph in Figure 16-3)
50C (system max.)
0V @ time = 0
Temperature
VHOLD
=
=
EQUATION 16-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 16-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS))
-(120 pF)(1 k + RSS + RS) ln(1/2047)
)
EXAMPLE 16-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ =
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25C.
TACQ =
TC =
2 s + Tc + [(Temp - 25C)(0.05 s/C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 10 k) ln(0.0004885)
-120 pF (18 k) ln(0.0004885)
-2.16 s (-7.6241)
16.47 s
TACQ =
2 s + 16.47 s + [(50×C - 25C)(0.05 sC)]
18.447 s + 1.25 s
19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
1998-2013 Microchip Technology Inc.
DS30289C-page 183
PIC17C7XX
FIGURE 16-3:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
VT = 0.6V
ANx
SS
RIC 1k
RSS
RS
CHOLD
= DAC capacitance
= 120 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
I leakage = leakage current at the pin due to
various junctions
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
( k )
DS30289C-page 184
1998-2013 Microchip Technology Inc.
PIC17C7XX
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
16.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
Table 16-1 and Table 16-2 show the resultant TAD times
derived from the device operating frequencies and the
A/D clock source selected. These times are for stan-
dard voltage range devices.
• 8TOSC
• 32TOSC
• 64TOSC
• Internal RC oscillator
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Max FOSC
(MHz)
Operation
ADCS1:ADCS0
5
8TOSC
32TOSC
64TOSC
RC
00
01
10
11
20
33
—
Note: When the device frequency is greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
TABLE 16-2: TAD vs. DEVICE OPERATING FREQUENCIES (EXTENDED VOLTAGE DEVICES (LC))
AD Clock Source (TAD)
Max FOSC
(MHz)
Operation
ADCS1:ADCS0
2.67
8TOSC
32TOSC
64TOSC
RC
00
01
10
11
10.67
21.33
—
Note: When the device frequency is greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
1998-2013 Microchip Technology Inc.
DS30289C-page 185
PIC17C7XX
16.3 Configuring Analog Port Pins
16.4 A/D Conversions
The ADCON1, and DDR registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding DDR bits
set (input). If the DDR bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
Example 16-2 shows how to perform an A/D conver-
sion. The PORTF and lower four PORTG pins are con-
figured as analog inputs. The analog references
(VREF+ and VREF-) are the device AVDD and AVSS. The
A/D interrupt is enabled, and the A/D conversion clock
is FRC. The conversion is performed on the RG3/AN0
pin (channel 0).
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the DDR bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed A/
D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2TAD wait is required before the next
acquisition is started. After this 2TAD wait, acquisition
on the selected channel is automatically started.
2: Analog levels on any pin that is defined as
a digital input (including the AN15:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specification.
In Figure 16-4, after the GO bit is set, the first time seg-
ment has a minimum of TCY and a maximum of TAD.
EXAMPLE 16-2:
A/D CONVERSION
MOVLB
CLRF
MOVLW
MOVWF
MOVLB
BCF
BSF
BSF
BCF
5
; Bank 5
ADCON1, F
0x01
ADCON0
; Configure A/D inputs, All analog, TAD = Fosc/8, left just.
; A/D is on, Channel 0 is selected
;
; Bank 4
; Clear A/D interrupt flag bit
; Enable A/D interrupts
4
PIR2, ADIF
PIE2, ADIE
INTSTA, PEIE
CPUSTA, GLINTD
; Enable peripheral interrupts
; Enable all interrupts
;
;
;
;
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
MOVLB
5
; Bank 5
BSF
:
:
ADCON0, GO
; Start A/D Conversion
;
;
The ADIF bit will be set and the GO/DONE bit
is cleared upon completion of the A/D Conversion
FIGURE 16-4:
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1
TAD2
b9
TAD3
b8
TAD4 TAD5
b7 b6
TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b5
b4
b3
b2
b1
b0
Conversion starts.
Holding capacitor is disconnected from analog input (typically 100 ns).
Set GO bit
Next Q4: ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
DS30289C-page 186
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 16-5:
FLOW CHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
Yes
Yes
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
SLEEP
Instruction?
A/D Clock
= RC?
GO = 0,
ADIF = 1
No
No
Yes
From SLEEP?
Yes
Abort Conversion
GO = 0,
Wake-up
Finish Conversion
Device in
SLEEP?
Wait 2TAD
GO = 0,
ADIF = 1
ADIF = 0
No
No
SLEEP
Power-down A/D
Finish Conversion
Stay in SLEEP
Power-down A/D
Wait 2TAD
GO = 0,
ADIF = 1
Wait 2TAD
1998-2013 Microchip Technology Inc.
DS30289C-page 187
PIC17C7XX
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
16.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 16-6 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s’. When an A/
D result will not overwrite these locations (A/D disable),
these registers may be used as two general purpose 8-
bit registers.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEPinstruction immediately follows the
instruction that sets the GO/DONE bit.
16.5 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the A/
D interrupt is enabled, the device will wake-up from
16.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted.
The value that is in the ADRESH:ADRESL registers is
not modified for
a
Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
FIGURE 16-6:
A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
0 7 6 5
ADFM = 1
0
7
7
2 1 0 7
0
0000 00
0000 00
RESULT
ADRESL
10-bits
RESULT
ADRESH
10-bits
ADRESH
ADRESL
Left Justified
Right Justified
DS30289C-page 188
1998-2013 Microchip Technology Inc.
PIC17C7XX
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
16.7 A/D Accuracy/Error
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high fre-
quencies, TAD should be derived from the device oscil-
lator.
16.8 Connection Considerations
The absolute accuracy specified for the A/D converter
includes the sum of all contributions for quantization
error, integral error, differential error, full scale error, off-
set error, and monotonicity. It is defined as the maxi-
mum deviation from an actual transition versus an ideal
transition for any code. The absolute error of the A/D
converter is specified at < ±1 LSb for VDD = VREF (over
the device’s specified operating range). However, the
accuracy of the A/D converter will degrade as VREF
diverges from VDD.
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.3V, then the accuracy of the conver-
sion is out of specification.
An external RC filter is sometimes added for anti-
aliasing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 k recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
For a given range of analog inputs, the output digital
code will be the same. This is due to the quantization of
the analog input to a digital code. Quantization error is
typically ± 1/2 LSb and is inherent in the analog to dig-
ital conversion process. The only way to reduce quan-
tization error is to increase the resolution of the A/D
converter or oversample.
16.9 Transfer Function
The transfer function of the A/D converter is as follows:
the first transition occurs when the analog input voltage
(VAIN) equals Analog VREF / 1024 (Figure 16-7).
Offset error measures the first actual transition of a
code versus the first ideal transition of a code. Offset
error shifts the entire transfer function. Offset error can
be calibrated out of a system or introduced into a sys-
tem through the interaction of the total leakage current
and source impedance at the analog input.
FIGURE 16-7:
A/D TRANSFER
FUNCTION
3FFh
3FEh
Gain error measures the maximum deviation of the last
actual transition and the last ideal transition adjusted
for offset error. This error appears as a change in slope
of the transfer function. The difference in gain error to
full scale error is that full scale does not take offset error
into account. Gain error can be calibrated out in soft-
ware.
003h
002h
001h
000h
Linearity error refers to the uniformity of the code
changes. Linearity errors cannot be calibrated out of
the system. Integral non-linearity error measures the
actual code transition versus the ideal code transition,
adjusted by the gain error for each code.
Differential non-linearity measures the maximum actual
code width versus the ideal code width. This measure
is unadjusted.
Analog Input Voltage
The maximum pin leakage current is specified in the
Device Data Sheet electrical specification (Table 20-2,
parameter #D060).
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high fre-
quencies, TAD should be derived from the device oscil-
lator. TAD must not violate the minimum and should be
minimized to reduce inaccuracies due to noise and
sampling capacitor bleed off.
1998-2013 Microchip Technology Inc.
DS30289C-page 189
PIC17C7XX
16.10 References
A good reference for understanding A/D converter is the
"Analog-Digital Conversion Handbook" third edition,
published by Prentice Hall (ISBN 0-13-03-2848-0).
TABLE 16-3: REGISTERS/BITS ASSOCIATED WITH A/D
POR,
BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
06h, unbanked CPUSTA
07h, unbanked INTSTA
—
—
STAKAV GLINTD
TO
PD
POR
T0IE
BOR
INTE
--11 1100
0000 0000
000- 0010
--11 qq11
0000 0000
000- 0010
PEIF
T0CKIF
BCLIF
BCLIE
T0IF
ADIF
ADIE
INTF
—
PEIE
T0CKIE
CA3IF
CA3IE
10h, Bank 4
PIR2
SSPIF
SSPIE
CA4IF
CA4IE
TX2IF
TX2IE
RC2IF
RC2IE
11h, Bank 4
10h, Bank 5
PIE2
—
000- 0000
1111 1111
000- 0000
1111 1111
DDRF
Data Direction Register for PORTF
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
11h, Bank 5
12h, Bank 5
13h, Bank 5
PORTF
DDRG
0000 0000
1111 1111
xxxx 0000
0000 0000
1111 1111
uuuu 0000
Data Direction register for PORTG
RG7/ RG6/ RG5/
TX2/CK2 RX2/DT2 PWM3
RG4/
CAP3
RG3/
RG2/
RG1/
AN2
RG0/
AN3
PORTG
AN0/VREF+ AN1/VREF-
14h, Bank 5
15h, Bank 5
16h, Bank 5
17h, Bank 5
Legend:
ADCON0
ADCON1
ADRESL
CHS3
CHS2
CHS1
ADFM
CHS0
—
—
GO/DONE
PCFG2
—
ADON 0000 -0-0
0000 -0-0
000- 0000
uuuu uuuu
uuuu uuuu
ADCS1
ADCS0
PCFG3
PCFG1 PCFG0 000- 0000
xxxx xxxx
A/D Result Low Register
ADRESH A/D Result High Register
xxxx xxxx
x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note:
Other (non power-up) RESETS include: external RESET through MCLR and Watchdog Timer Reset.
DS30289C-page 190
1998-2013 Microchip Technology Inc.
PIC17C7XX
The PIC17CXXX has a Watchdog Timer which can be
shut-off only through EPROM bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on POR and BOR. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in RESET until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 96 ms (nominal) on power-up only,
designed to keep the part in RESET while the power
supply stabilizes. With these two timers on-chip, most
applications need no external RESET circuitry.
17.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC17CXXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
• Oscillator Selection (Section 4.0)
• RESET (Section 5.0)
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts (Section 6.0)
• Watchdog Timer (WDT)
• SLEEP mode
The SLEEP mode is designed to offer a very low cur-
rent power-down mode. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LF crystal option saves power. Configu-
ration bits are used to select various options. This con-
figuration word has the format shown in Figure 17-1.
• Code protection
REGISTER 17-1: CONFIGURATION WORDS
High (H) Table Read Addr.
FE0Fh - FE08h
U-x
—
R/P-1 R/P-1
PM2 BODEN
U-x
—
U-x
—
U-x
—
U-x
—
U-x
—
U-x
—
bit 15 bit 8 bit 7
bit 0
Low (L) Table Read Addr.
FE07h - FE00h
U-x
—
U-x
R/P-1
PM1
U-x R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
—
—
PM0 WDTPS1 WDTPS0 FOSC1 FOSC0
bit 0
bit 15 bit 8 bit 7
bits 7H, 6L, 4L
PM2, PM1, PM0: Processor Mode Select bits
111= Microprocessor mode
110= Microcontroller mode
101= Extended Microcontroller mode
000= Code Protected Microcontroller mode
bit 6H
BODEN: Brown-out Detect Enable
1= Brown-out Detect circuitry is enabled
0= Brown-out Detect circuitry is disabled
bits 3L:2L
WDTPS1:WDTPS0: WDT Postscaler Select bits
11= WDT enabled, postscaler = 1
10= WDT enabled, postscaler = 256
01= WDT enabled, postscaler = 64
00= WDT disabled, 16-bit overflow timer
bits 1L:0L
FOSC1:FOSC0: Oscillator Select bits
11= EC oscillator
10= XT oscillator
01= RC oscillator
00= LF oscillator
Shaded bits (—)
Reserved
1998-2013 Microchip Technology Inc.
DS30289C-page 191
PIC17C7XX
17.1 Configuration Bits
17.2 Oscillator Configurations
17.2.1 OSCILLATOR TYPES
The PIC17CXXX has eight configuration locations
(Table 17-1). These locations can be programmed
(read as '0'), or left unprogrammed (read as '1') to
select various device configurations. Any write to a
configuration location, regardless of the data, will pro-
gram that configuration bit. A TABLWTinstruction and
raising the MCLR/VPP pin to the programming voltage
are both required to write to program memory loca-
tions. The configuration bits can be read by using the
TABLRD instructions. Reading any configuration loca-
tion between FE00h and FE07h will read the low byte
of the configuration word (Figure 17-1) into the TAB-
LATL register. The TABLATH register will be FFh.
Reading a configuration location between FE08h and
FE0Fh will read the high byte of the configuration word
into the TABLATL register. The TABLATH register will
be FFh.
The PIC17CXXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
• LF
• XT
• EC
• RC
Low Power Crystal
Crystal/Resonator
External Clock Input
Resistor/Capacitor
For information on the different oscillator types and
how to use them, please refer to Section 4.0.
Addresses FE00h through FE0Fh are only in the pro-
gram memory space for Microcontroller and Code Pro-
tected Microcontroller modes. A device programmer
will be able to read the configuration word in any pro-
cessor mode. See programming specifications for
more detail.
TABLE 17-1: CONFIGURATION
LOCATIONS
Bit
Address
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
FE00h
FE01h
FE02h
FE03h
FE04h
FE06h
FE0Eh
FE0Fh
PM1
BODEN
PM2
Note: When programming the desired configura-
tion locations, they must be programmed
in ascending order, starting with address
FE00h.
DS30289C-page 192
1998-2013 Microchip Technology Inc.
PIC17C7XX
17.3.2
CLEARING THE WDT AND
POSTSCALER
17.3 Watchdog Timer (WDT)
The Watchdog Timer’s function is to recover from soft-
ware malfunction, or to reset the device while in SLEEP
mode. The WDT uses an internal free running on-chip
RC oscillator for its clock source. This does not require
any external components. This RC oscillator is sepa-
rate from the RC oscillator of the OSC1/CLKIN pin.
That means that the WDT will run even if the clock on
the OSC1/CLKIN and OSC2/CLKOUT pins has been
stopped, for example, by execution of a SLEEPinstruc-
tion. During normal operation, a WDT time-out gener-
ates a device RESET. The WDT can be permanently
disabled by programming the configuration bits
WDTPS1:WDTPS0 as '00' (Section 17.1).
The WDT and postscaler are cleared when:
• The device is in the RESET state
• A SLEEPinstruction is executed
• A CLRWDTinstruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the RESET state.
17.3.3
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., Max.
WDT postscaler), it may take several seconds before a
WDT time-out occurs.
Under normal operation, the WDT must be cleared on
a regular interval. This time must be less than the min-
imum WDT overflow time. Not clearing the WDT in this
time frame will cause the WDT to overflow and reset
the device.
The WDT and postscaler become the Power-up Timer
whenever the PWRT is invoked.
17.3.1
WDT PERIOD
17.3.4
WDT AS NORMAL TIMER
The WDT has a nominal time-out period of 12 ms (with
postscaler = 1). The time-out periods vary with temper-
ature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, con-
figuration bits should be used to enable the WDT with
a greater prescale. Thus, typical time-out periods up to
3.0 seconds can be realized.
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 TOSC cycles. On overflow, the TO bit
is cleared (device is not RESET). The CLRWDTinstruc-
tion can be used to set the TO bit. This allows the WDT
to be a simple overflow timer. The simple timer does
not increment when in SLEEP.
The CLRWDT and SLEEP instructions clear the WDT
and its postscale setting and prevent it from timing out,
thus generating a device RESET condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
FIGURE 17-1:
WATCHDOG TIMER BLOCK DIAGRAM
On-chip RC
Oscillator(1)
WDT
Postscaler
WDTPS1:WDTPS0
4 - to - 1 MUX
WDT Overflow
WDT Enable
Note 1: This oscillator is separate from the external
RC oscillator on the OSC1 pin.
TABLE 17-2: REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLR, WDT
POR, BOR
—
Config
See Figure 17-1 for location of WDTPSx bits in Configuration Word.
STKAV GLINTD TO PD
(Note 1)
(Note 1)
06h, Unbanked CPUSTA
Legend:
—
—
POR
BOR
--11 11qq --11 qquu
-= unimplemented, read as '0', q= value depends on condition. Shaded cells are not used by the WDT.
Note 1: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
1998-2013 Microchip Technology Inc.
DS30289C-page 193
PIC17C7XX
Any RESET event will cause a device RESET. Any
interrupt event is considered a continuation of program
execution. The TO and PD bits in the CPUSTA register
can be used to determine the cause of a device
RESET. The PD bit, which is set on power-up, is
cleared when SLEEP is invoked. The TO bit is cleared
if WDT time-out occurred (and caused a RESET).
17.4 Power-down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEPinstruction. This clears the Watchdog Timer and
postscaler (if enabled). The PD bit is cleared and the
TO bit is set (in the CPUSTA register). In SLEEP mode,
the oscillator driver is turned off. The I/O ports maintain
their status (driving high,low, or hi-impedance input).
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GLINTD bit. If the GLINTD
bit is set (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the
GLINTD bit is clear (enabled), the device executes the
instruction after the SLEEP instruction and then
branches to the interrupt vector address. In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOPafter the
SLEEPinstruction.
The MCLR/VPP pin must be at a logic high level
(VIHMC). A WDT time-out RESET does not drive the
MCLR/VPP pin low.
17.4.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
• Power-on Reset
• Brown-out Reset
• External RESET input on MCLR/VPP pin
• WDT Reset (if WDT was enabled)
• Interrupt from RA0/INT pin, RB port change,
T0CKI interrupt, or some peripheral interrupts
Note: If the global interrupt is disabled (GLINTD
is set), but any interrupt source has both its
interrupt enable bit and the corresponding
interrupt flag bit set, the device will imme-
diately wake-up from SLEEP. The TO bit is
set and the PD bit is cleared.
The following peripheral interrupts can wake the device
from SLEEP:
• Capture interrupts
• USART synchronous slave transmit interrupts
• USART synchronous slave receive interrupts
• A/D conversion complete
The WDT is cleared when the device wakes from
SLEEP, regardless of the source of wake-up.
17.4.1.1
Wake-up Delay
• SPI slave transmit/receive complete
• I2C slave receive
When the oscillator type is configured in XT or LF
mode, the Oscillator Start-up Timer (OST) is activated
on wake-up. The OST will keep the device in RESET
for 1024TOSC. This needs to be taken into account
when considering the interrupt response time when
coming out of SLEEP.
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip Q clocks are present.
FIGURE 17-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
(4)
CLKOUT
'0' or '1'
INT
(RA0/INT pin)
(2)
Interrupt Latency
INTF Flag
GLINTD bit
Processor
in SLEEP
INSTRUCTION FLOW
0004h
PC
PC+1
PC+2
0005h
PC
Instruction
Inst (PC+2)
Inst (PC+1)
Inst (PC) = SLEEP
Inst (PC-1)
Inst (PC+1)
SLEEP
Fetched
Instruction
Executed
Dummy Cycle
Note 1: XT or LF oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.
3: When GLINTD = 0, processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30289C-page 194
1998-2013 Microchip Technology Inc.
PIC17C7XX
17.4.2
MINIMIZING CURRENT
CONSUMPTION
17.5 Code Protection
The code in the program memory can be protected by
selecting the microcontroller in Code Protected mode
(PM2:PM0 = '000').
To minimize current consumption, all I/O pins should be
either at VDD, or VSS, with no external circuitry drawing
current from the I/O pin. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should be at VDD or VSS. The contributions
from on-chip pull-ups on PORTB should also be con-
sidered and disabled, when possible.
In this mode, instructions that are in the on-chip pro-
gram memory space, can continue to read or write the
program memory. An instruction that is executed out-
side of the internal program memory range will be
inhibited from writing to, or reading from, program
memory.
Note: Microchip does not recommend code pro-
tecting windowed devices.
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
1998-2013 Microchip Technology Inc.
DS30289C-page 195
PIC17C7XX
For complete details of serial programming, please
refer to the PIC17C7XX Programming Specification.
(Contact your local Microchip Technology Sales Office
for availability.)
17.6 In-Circuit Serial Programming
The PIC17C7XX group of the high-end family
(PIC17CXXX) has an added feature that allows serial
programming while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom firm-
ware to be programmed.
FIGURE 17-3:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC17C7XX
Devices may be serialized to make the product unique;
“special” variants of the product may be offered and
code updates are possible. This allows for increased
design flexibility.
+5V
0V
VDD
VSS
VPP
MCLR/VPP
To place the device into the Serial Programming Test
mode, two pins will need to be placed at VIHH. These
are the TEST pin and the MCLR/VPP pin. Also, a
sequence of events must occur as follows:
TEST CNTL
Dev. CLK
TEST
RA1/T0CKI
Data I/O
RA4/RX1/DT1
RA5/TX1/CK1
1. The TEST pin is placed at VIHH.
Data CLK
2. The MCLR/VPP pin is placed at VIHH.
There is a setup time between step 1 and step 2 that
must be met.
After this sequence, the Program Counter is pointing to
program memory address 0xFF60. This location is in
the Boot ROM. The code initializes the USART/SCI so
that it can receive commands. For this, the device must
be clocked. The device clock source in this mode is the
RA1/T0CKI pin. After delaying to allow the USART/SCI
to initialize, commands can be received. The flow is
shown in these 3 steps:
VDD
To Normal
Connections
1. The device clock source starts.
2. Wait 80 device clocks for Boot ROM code to
configure the USART/SCI.
3. Commands may now be sent.
TABLE 17-3: ICSP INTERFACE PINS
During Programming
Description
Name
Function
Type
RA4/RX1/DT1
RA5/TX1/CK1
RA1/T0CKI
TEST
DT
CK
I/O
I
Serial Data
Serial Clock
OSCI
TEST
MCLR/VPP
VDD
I
Device Clock Source
I
Test mode selection control input, force to VIHH
Master Clear Reset and Device Programming Voltage
Positive supply for logic and I/O pins
MCLR/VPP
VDD
P
P
P
VSS
VSS
Ground reference for logic and I/O pins
DS30289C-page 196
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 18-1: OPCODE FIELD
18.0 INSTRUCTION SET SUMMARY
DESCRIPTIONS
The PIC17CXXX instruction set consists of 58 instruc-
tions. Each instruction is a 16-bit word divided into an
OPCODE and one or more operands. The opcode
specifies the instruction type, while the operand(s) fur-
ther specify the operation of the instruction. The
PIC17CXXX instruction set can be grouped into three
types:
Field
Description
f
p
i
Register file address (00h to FFh)
Peripheral register file address (00h to 1Fh)
Table pointer control i = '0' (do not change)
i = '1' (increment after instruction execution)
t
Table byte select t = '0' (perform operation on lower
byte)
t = '1' (perform operation on upper byte literal field,
constant data)
• byte-oriented
• bit-oriented
• literal and control operations
WREG Working register (accumulator)
These formats are shown in Figure 18-1.
b
k
x
Bit address within an 8-bit file register
Literal field, constant data or label
Table 18-1 shows the field descriptions for the
opcodes. These descriptions are useful for understand-
ing the opcodes in Table 18-2 and in each specific
instruction descriptions.
Don't care location (= '0' or '1')
The assembler will generate code with x = '0'. It is
the recommended form of use for compatibility with
all Microchip software tools.
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
d
Destination select
0 = store result in WREG
1 = store result in file register f
Default is d = '1'
The destination designator specifies where the result of
the operation is to be placed. If 'd' = '0', the result is
placed in the WREG register. If 'd' = '1', the result is
placed in the file register specified by the instruction.
u
s
Unused, encoded as '0'
Destination select
0 = store result in file register f and in the WREG
1 = store result in file register f
Default is s = '1'
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
label Label name
C,DC, ALU status bits Carry, Digit Carry, Zero, Overflow
Z,OV
For literal and control operations, 'k' represents an 8-
or 13-bit constant or literal value.
GLINTD Global Interrupt Disable bit (CPUSTA<4>)
TBLPTR Table Pointer (16-bit)
The instruction set is highly orthogonal and is grouped
into:
TBLAT Table Latch (16-bit) consists of high byte (TBLATH)
and low byte (TBLATL)
• byte-oriented operations
• bit-oriented operations
TBLATL Table Latch low byte
TBLATH Table Latch high byte
TOS Top-of-Stack
• literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless:
PC
Program Counter
BSR Bank Select Register
• a conditional test is true
WDT Watchdog Timer Counter
• the program counter is changed as a result of an
instruction
TO
PD
Time-out bit
Power-down bit
• a table read or a table write instruction is executed
(in this case, the execution takes two instruction
cycles with the second cycle executed as a NOP)
dest Destination either the WREG register or the speci-
fied register file location
[ ]
( )
Options
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 25 MHz, the normal
instruction execution time is 160 ns. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 320 ns.
Contents
Assigned to
Register bit field
In the set of
< >
User defined term (font is courier)
italics
1998-2013 Microchip Technology Inc.
DS30289C-page 197
PIC17C7XX
Table 18-2 lists the instructions recognized by the
MPASM assembler.
18.1 Special Function Registers as
Source/Destination
Note 1: Any unused opcode is Reserved. Use of
any reserved opcode may cause unex-
pected operation.
The PIC17C7XX’s orthogonal instruction set allows
read and write of all file registers, including special
function registers. There are some special situations
the user should be aware of:
All instruction examples use the following format to rep-
resent a hexadecimal number:
18.1.1
ALUSTA AS DESTINATION
0xhh
If an instruction writes to ALUSTA, the Z, C, DC and OV
bits may be set or cleared as a result of the instruction
and overwrite the original data bits written. For exam-
where h signifies a hexadecimal digit.
To represent a binary number:
0000 0100b
ple, executing CLRF
ALUSTA will clear register
ALUSTA and then set the Z bit leaving 0000 0100bin
the register.
where b signifies a binary string.
FIGURE 18-1:
GENERAL FORMAT FOR
INSTRUCTIONS
18.1.2
PCL AS SOURCE OR DESTINATION
Read, write or read-modify-write on PCL may have the
following results:
Byte-oriented file register operations
15
9
8
7
0
Read PC:
PCH PCLATH; PCL dest
OPCODE
d
f (FILE #)
Write PCL:
PCLATH PCH;
8-bit destination value PCL
d = 0 for destination WREG
d = 1 for destination f
f = 8-bit file register address
Read-Modify-Write: PCL ALU operand
PCLATH PCH;
Byte to Byte move operations
15 13 12
OPCODE p (FILE #)
8-bit result PCL
8
7
0
0
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
f (FILE #)
p = peripheral register file address
f = 8-bit file register address
18.1.3
BIT MANIPULATION
Bit-oriented file register operations
15 11 10
All bit manipulation instructions are done by first read-
ing the entire register, operating on the selected bit and
writing the result back (read-modify-write (R-M-W)).
The user should keep this in mind when operating on
some special function registers, such as ports.
8
7
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit address
f = 8-bit file register address
Note: Status bits that are manipulated by the
device (including the interrupt flag bits) are
set or cleared in the Q1 cycle. So, there is
no issue on doing R-M-W instructions on
registers which contain these bits
Literal and control operations
15
8
7
0
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOoperations
15 13 12
OPCODE
k = 13-bit immediate value
k (literal)
DS30289C-page 198
1998-2013 Microchip Technology Inc.
PIC17C7XX
The four Q cycles that make up an instruction cycle
(TCY) can be generalized as:
18.2 Q Cycle Activity
Each instruction cycle (TCY) is comprised of four Q
cycles (Q1-Q4). The Q cycle is the same as the device
oscillator cycle (TOSC). The Q cycles provide the timing/
designation for the Decode, Read, Process Data,
Write, etc., of each instruction cycle. The following dia-
gram shows the relationship of the Q cycles to the
instruction cycle.
Q1: Instruction Decode Cycle or forced No
operation
Q2: Instruction Read Cycle or No operation
Q3: Process the Data
Q4: Instruction Write Cycle or No operation
Each instruction will show the detailed Q cycle opera-
tion for the instruction.
FIGURE 18-2:
Q CYCLE ACTIVITY
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOSC
TCY1
TCY2
TCY3
1998-2013 Microchip Technology Inc.
DS30289C-page 199
PIC17C7XX
TABLE 18-2: PIC17CXXX INSTRUCTION SET
16-bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f,d
ADD WREG to f
1
1
1
1
1
0000 111d ffff ffff OV,C,DC,Z
0001 000d ffff ffff OV,C,DC,Z
ADDWFC f,d
ADD WREG and Carry bit to f
AND WREG with f
ANDWF
CLRF
f,d
f,s
f,d
f
0000 101d ffff ffff
0010 100s ffff ffff
0001 001d ffff ffff
Z
Clear f, or Clear f and Clear WREG
Complement f
None
Z
3
COMF
CPFSEQ
CPFSGT
CPFSLT
DAW
Compare f with WREG, skip if f = WREG
Compare f with WREG, skip if f > WREG
Compare f with WREG, skip if f < WREG
Decimal Adjust WREG Register
Decrement f
1 (2) 0011 0001 ffff ffff
1 (2) 0011 0010 ffff ffff
1 (2) 0011 0000 ffff ffff
None
None
None
C
6,8
2,6,8
2,6,8
3
f
f
f,s
f,d
1
1
0010 111s ffff ffff
DECF
0000 011d ffff ffff OV,C,DC,Z
DECFSZ f,d
DCFSNZ f,d
Decrement f, skip if 0
Decrement f, skip if not 0
Increment f
1 (2) 0001 011d ffff ffff
1 (2) 0010 011d ffff ffff
None
None
6,8
6,8
INCF
f,d
f,d
f,d
f,d
f,p
p,f
f
1
0001 010d ffff ffff OV,C,DC,Z
INCFSZ
INFSNZ
IORWF
MOVFP
MOVPF
MOVWF
MULWF
NEGW
NOP
Increment f, skip if 0
Increment f, skip if not 0
Inclusive OR WREG with f
Move f to p
1 (2) 0001 111d ffff ffff
1 (2) 0010 010d ffff ffff
None
None
Z
6,8
6,8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000 100d ffff ffff
011p pppp ffff ffff
010p pppp ffff ffff
0000 0001 ffff ffff
0011 0100 ffff ffff
None
Z
Move p to f
Move WREG to f
None
None
f
Multiply WREG with f
Negate WREG
f,s
—
f,d
f,d
f,d
f,d
f,s
f,d
0010 110s ffff ffff OV,C,DC,Z
1,3
No Operation
0000 0000 0000 0000
0001 101d ffff ffff
0010 001d ffff ffff
0001 100d ffff ffff
0010 000d ffff ffff
0010 101s ffff ffff
None
C
RLCF
Rotate left f through Carry
Rotate left f (no carry)
Rotate right f through Carry
Rotate right f (no carry)
Set f
RLNCF
RRCF
None
C
RRNCF
SETF
None
None
3
1
1
SUBWF
Subtract WREG from f
Subtract WREG from f with Borrow
Swap f
0000 010d ffff ffff OV,C,DC,Z
0000 001d ffff ffff OV,C,DC,Z
SUBWFB f,d
SWAPF f,d
0001 110d ffff ffff
2 (3) 1010 10ti ffff ffff
None
None
None
None
TABLRD t,i,f
TABLWT t,i,f
Table Read
7
5
Table Write
2
1
1
1010 11ti ffff ffff
1010 00tx ffff ffff
1010 01tx ffff ffff
TLRD
TLWT
t,f
t,f
Table Latch Read
Table Latch Write
None
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
(WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into the LSB of the
PC (PCL).
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte), in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead a NOPis executed.
DS30289C-page 200
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 18-2: PIC17CXXX INSTRUCTION SET (CONTINUED)
16-bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
TSTFSZ
XORWF
f
Test f, skip if 0
1 (2) 0011 0011 ffff ffff
None
Z
6,8
f,d
Exclusive OR WREG with f
1
0000 110d ffff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f,b
f,b
f,b
f,b
f,b
Bit Clear f
1
1
1000 1bbb ffff ffff
1000 0bbb ffff ffff
None
None
None
None
None
BSF
Bit Set f
BTFSC
BTFSS
BTG
Bit test, skip if clear
Bit test, skip if set
Bit Toggle f
1 (2) 1001 1bbb ffff ffff
1 (2) 1001 0bbb ffff ffff
6,8
6,8
1
0011 1bbb ffff ffff
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
k
k
k
ADD literal to WREG
AND literal with WREG
Subroutine Call
1
1
2
1011 0001 kkkk kkkk OV,C,DC,Z
1011 0101 kkkk kkkk
111k kkkk kkkk kkkk
Z
None
7
CLRWDT
GOTO
—
k
Clear Watchdog Timer
1
2
1
2
1
1
1
1
2
2
2
0000 0000 0000 0100
110k kkkk kkkk kkkk
1011 0011 kkkk kkkk
1011 0111 kkkk kkkk
1011 1000 uuuu kkkk
1011 101x kkkk uuuu
1011 0000 kkkk kkkk
1011 1100 kkkk kkkk
0000 0000 0000 0101
1011 0110 kkkk kkkk
0000 0000 0000 0010
TO, PD
None
Z
Unconditional Branch
7
IORLW
k
Inclusive OR literal with WREG
Long Call
LCALL
k
None
None
None
None
None
GLINTD
None
None
4,7
MOVLB
MOVLR
MOVLW
MULLW
RETFIE
RETLW
RETURN
k
Move literal to low nibble in BSR
Move literal to high nibble in BSR
Move literal to WREG
k
k
k
Multiply literal with WREG
Return from interrupt (and enable interrupts)
Return literal to WREG
—
k
7
7
7
—
Return from subroutine
SLEEP
SUBLW
XORLW
—
k
Enter SLEEP mode
1
1
1
0000 0000 0000 0011
TO, PD
Subtract WREG from literal
Exclusive OR literal with WREG
1011 0010 kkkk kkkk OV,C,DC,Z
1011 0100 kkkk kkkk
k
Z
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
(WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into the LSB of the
PC (PCL).
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte), in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead a NOPis executed.
1998-2013 Microchip Technology Inc.
DS30289C-page 201
PIC17C7XX
ADDLW
ADD Literal to WREG
ADDWF
Syntax:
ADD WREG to f
Syntax:
[ label ] ADDLW
0 k 255
k
[ label ] ADDWF f,d
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 f 255
d [0,1]
(WREG) + k (WREG)
Operation:
(WREG) + (f) (dest)
OV, C, DC, Z
Status Affected:
Encoding:
OV, C, DC, Z
1011
0001
kkkk
kkkk
0000
111d
ffff
ffff
The contents of WREG are added to
the 8-bit literal 'k' and the result is
placed in WREG.
Add WREG to register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Words:
1
1
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Decode
Read
register 'f'
Process
Data
Write to
destination
ADDLW
0x15
Example:
ADDWF
REG, 0
Example:
Before Instruction
WREG = 0x10
Before Instruction
WREG
REG
=
=
0x17
0xC2
After Instruction
WREG = 0x25
After Instruction
WREG
REG
=
=
0xD9
0xC2
DS30289C-page 202
1998-2013 Microchip Technology Inc.
PIC17C7XX
ADDWFC
Syntax:
ADD WREG and Carry bit to f
ANDLW
And Literal with WREG
[ label ] ADDWFC f,d
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
0 f 255
d [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
(WREG) .AND. (k) (WREG)
Operation:
(WREG) + (f) + C (dest)
Z
Status Affected:
Encoding:
OV, C, DC, Z
1011
0101
kkkk
kkkk
0001
000d
ffff
ffff
The contents of WREG are AND’ed with
the 8-bit literal 'k'. The result is placed in
WREG.
Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result is
placed in data memory location 'f'.
Description:
Words:
1
1
Cycles:
Words:
1
1
Q Cycle Activity:
Q1
Cycles:
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
'k'
Process
Data
Write to
WREG
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
ANDLW
0x5F
Example:
Before Instruction
ADDWFC
REG
0
Example:
WREG
=
0xA3
0x03
Before Instruction
After Instruction
Carry bit =
1
WREG
=
REG
WREG
=
=
0x02
0x4D
After Instruction
Carry bit =
0
REG
WREG
=
=
0x02
0x50
1998-2013 Microchip Technology Inc.
DS30289C-page 203
PIC17C7XX
ANDWF
Syntax:
AND WREG with f
BCF
Bit Clear f
[ label ] ANDWF f,d
Syntax:
Operands:
[ label ] BCF f,b
Operands:
0 f 255
d [0,1]
0 f 255
0 b 7
Operation:
(WREG) .AND. (f) (dest)
Operation:
Status Affected:
Encoding:
0 (f<b>)
Status Affected:
Encoding:
Z
None
0000
101d
ffff
ffff
1000
1bbb
ffff
ffff
The contents of WREG are AND’ed with
register 'f'. If 'd' is 0 the result is stored
in WREG. If 'd' is 1 the result is stored
back in register 'f'.
Bit 'b' in register 'f' is cleared.
Description:
Description:
Words:
1
1
Cycles:
Words:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Cycles:
Decode
Read
register 'f'
Process
Data
Write
register 'f'
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
BCF
FLAG_REG,
7
Example:
Before Instruction
FLAG_REG = 0xC7
ANDWF
REG, 1
Example:
After Instruction
Before Instruction
FLAG_REG = 0x47
WREG
=
0x17
0xC2
REG
=
After Instruction
WREG
REG
=
=
0x17
0x02
DS30289C-page 204
1998-2013 Microchip Technology Inc.
PIC17C7XX
BSF
Bit Set f
BTFSC
Bit Test, skip if Clear
Syntax:
Operands:
[ label ] BSF f,b
Syntax:
[ label ] BTFSC f,b
0 f 255
0 b 7
Operands:
0 f 255
0 b 7
Operation:
Status Affected:
Encoding:
1 (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
1000
0bbb
ffff
ffff
1001
1bbb
ffff
ffff
Bit 'b' in register 'f' is set.
If bit 'b' in register ’f' is 0, then the next
instruction is skipped.
Description:
Words:
Description:
1
1
If bit 'b' is 0, then the next instruction
fetched during the current instruction exe-
cution is discarded and a NOPis executed
instead, making this a two-cycle
instruction.
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
BSF
FLAG_REG, 7
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register 'f'
Process
Data
No
operation
FLAG_REG
=
=
0x0A
After Instruction
FLAG_REG
If skip:
Q1
0x8A
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG,1
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
If FLAG<1>
PC
1998-2013 Microchip Technology Inc.
DS30289C-page 205
PIC17C7XX
BTFSS
Bit Test, skip if Set
BTG
Bit Toggle f
Syntax:
[ label ] BTFSS f,b
Syntax:
Operands:
[ label ] BTG f,b
Operands:
0 f 127
0 b < 7
0 f 255
0 b < 7
Operation:
skip if (f<b>) = 1
None
Operation:
(f<b>) (f<b>)
Status Affected:
Encoding:
Status Affected:
Encoding:
None
1001
0bbb
ffff
ffff
0011
1bbb
ffff
ffff
If bit 'b' in register 'f' is 1, then the next
instruction is skipped.
Bit 'b' in data memory location 'f' is
inverted.
Description:
Description:
If bit 'b' is 1, then the next instruction
fetched during the current instruction exe-
cution is discarded and a NOPis executed
instead, making this a two-cycle
instruction.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
1
Decode
Read
Process
Data
Write
register 'f'
register 'f'
Cycles:
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
BTG
PORTC,
4
Example:
Decode
Read
register 'f'
Process
Data
No
operation
Before Instruction:
PORTC
=
0111 0101[0x75]
If skip:
Q1
After Instruction:
PORTC
=
0110 0101[0x65]
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSS
:
:
FLAG,1
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
If FLAG<1>
PC
DS30289C-page 206
1998-2013 Microchip Technology Inc.
PIC17C7XX
CALL
Subroutine Call
[ label ] CALL k
0 k 8191
CLRF
Clear f
Syntax:
Syntax:
[label] CLRF f,s
0 f 255
Operands:
Operation:
Operands:
Operation:
PC+ 1 TOS, k PC<12:0>,
k<12:8> PCLATH<4:0>;
PC<15:13> PCLATH<7:5>
00h f, s [0,1]
00h dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
100s
ffff
ffff
111k
kkkk
kkkk
kkkk
Clears the contents of the specified
register(s).
s = 0: Data memory location 'f' and
WREG are cleared.
s = 1: Data memory location 'f' is
cleared.
Description:
Subroutine call within 8K page. First,
return address (PC+1) is pushed onto
the stack. The 13-bit value is loaded
into PC bits<12:0>. Then the upper-
eight bits of the PC are copied into
PCLATH. CALLis a two-cycle
instruction.
Description:
Words:
1
1
Cycles:
See LCALLfor calls outside 8K memory
space.
Q Cycle Activity:
Q1
Words:
1
2
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
and if
specified
WREG
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
'k'<7:0>,
Push PC to
stack
Process
Data
Write to PC
CLRF
FLAG_REG, 1
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction
FLAG_REG
=
=
0x5A
0x01
WREG
After Instruction
FLAG_REG
WREG
HERE
CALL THERE
Example:
=
=
0x00
0x01
Before Instruction
PC
=
Address(HERE)
After Instruction
PC
=
Address(THERE)
TOS =
Address (HERE + 1)
1998-2013 Microchip Technology Inc.
DS30289C-page 207
PIC17C7XX
CLRWDT
Syntax:
Clear Watchdog Timer
COMF
Complement f
[ label ] CLRWDT
Syntax:
Operands:
[ label ] COMF f,d
Operands:
Operation:
None
0 f 255
d [0,1]
00h WDT
0 WDT postscaler,
1 TO
Operation:
(f) (dest)
Status Affected:
Encoding:
Z
1 PD
0001
001d
ffff
ffff
Status Affected:
Encoding:
TO, PD
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
Description:
0000
0000
0000
0100
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the postscaler
of the WDT. Status bits TO and PD are
set.
Description:
Words:
1
1
Cycles:
Words:
1
1
Q Cycle Activity:
Q1
Cycles:
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write to
Q2
Q3
Q4
destination
Decode
No
operation
Process
Data
No
operation
COMF
REG1,0
Example:
Before Instruction
CLRWDT
Example:
REG1
=
0x13
Before Instruction
After Instruction
WDT counter
=
?
REG1
=
0x13
WREG
=
0xEC
After Instruction
WDT counter
WDT Postscaler
TO
=
=
=
=
0x00
0
1
1
PD
DS30289C-page 208
1998-2013 Microchip Technology Inc.
PIC17C7XX
Compare f with WREG,
skip if f = WREG
Compare f with WREG,
skip if f > WREG
CPFSEQ
Syntax:
CPFSGT
Syntax:
[ label ] CPFSEQ
0 f 255
f
[ label ] CPFSGT
0 f 255
f
Operands:
Operation:
Operands:
Operation:
(f) – (WREG),
(f) WREG),
skip if (f) = (WREG)
skip if (f) > (WREG)
(unsigned comparison)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
0001
ffff
ffff
0011
0010
ffff
ffff
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
Compares the contents of data memory
location 'f' to the contents of the WREG
by performing an unsigned subtraction.
Description:
Description:
If 'f' = WREG, then the fetched instruc-
tion is discarded and a NOPis executed
instead, making this a two-cycle
instruction.
If the contents of 'f' are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
Words:
1
Words:
1
Cycles:
1 (2)
Cycles:
1 (2)
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
No
operation
Decode
Read
Process
Data
No
operation
register 'f'
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG
Example:
NEQUAL
EQUAL
:
:
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Example:
Before Instruction
Before Instruction
PC Address
WREG
REG
=
=
=
HERE
?
?
PC
WREG
=
=
Address (HERE)
?
After Instruction
After Instruction
If REG
=
=
=
WREG;
Address (EQUAL)
WREG;
If REG
>
=
£
WREG;
Address (GREATER)
WREG;
PC
If REG
PC
PC
If REG
PC
Address (NEQUAL)
=
Address (NGREATER)
1998-2013 Microchip Technology Inc.
DS30289C-page 209
PIC17C7XX
Compare f with WREG,
CPFSLT
Syntax:
skip if f < WREG
[ label ] CPFSLT
0 f 255
DAW
Decimal Adjust WREG Register
f
Syntax:
Operands:
[label] DAW f,s
Operands:
Operation:
0 f 255
s [0,1]
(f) –WREG),
If [ [WREG<7:4> > 9].OR.[C = 1] ].AND.
[WREG<3:0> > 9]
then
skip if (f) < (WREG)
(unsigned comparison)
Operation:
Status Affected:
Encoding:
None
WREG<7:4> + 7 f<7:4>, s<7:4>;
0011
0000
ffff
ffff
If [WREG<7:4> > 9].OR.[C = 1]
then
WREG<7:4> + 6 f<7:4>, s<7:4>;
else
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
Description:
If the contents of 'f' are less than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
WREG<7:4> f<7:4>, s<7:4>;
If [WREG<3:0> > 9].OR.[DC = 1]
then
WREG<3:0> + 6 f<3:0>, s<3:0>;
else
WREG<3:0> f<3:0>, s<3:0>
Words:
1
Cycles:
1 (2)
Status Affected:
Encoding:
C
Q Cycle Activity:
Q1
0010
111s
ffff
ffff
Q2
Q3
Q4
DAW adjusts the eight-bit value in
WREG, resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
Description:
Decode
Read
register 'f'
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
s = 0: Result is placed in Data
memory location 'f' and
No
No
No
No
operation
operation
operation
operation
WREG.
s = 1: Result is placed in Data
memory location 'f'.
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
Words:
1
1
Cycles:
Before Instruction
Q Cycle Activity:
Q1
PC
W
=
=
Address (HERE)
?
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
After Instruction
register 'f'
and other
specified
register
If REG
<
WREG;
PC
If REG
PC
=
=
Address (LESS)
WREG;
Address (NLESS)
DAW
REG1, 0
Example:
Before Instruction
WREG
REG1
C
=
=
=
=
0xA5
??
0
DC
0
After Instruction
WREG
REG1
C
=
=
=
=
0x05
0x05
1
DC
0
DS30289C-page 210
1998-2013 Microchip Technology Inc.
PIC17C7XX
DECF
Decrement f
DECFSZ
Syntax:
Decrement f, skip if 0
Syntax:
Operands:
[ label ] DECF f,d
[ label ] DECFSZ f,d
0 f 255
d [0,1]
Operands:
0 f 255
d [0,1]
Operation:
(f) – 1 (dest)
Operation:
(f) – 1 (dest);
skip if result = 0
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
None
0000
011d
ffff
ffff
0001
011d
ffff
ffff
Decrement register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'.
Description:
The contents of register 'f' are decre-
mented. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is placed
back in register 'f'.
Description:
Words:
1
1
Cycles:
If the result is 0, the next instruction,
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
Words:
1
destination
Cycles:
1(2)
Q Cycle Activity:
Q1
DECF
CNT,
1
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register 'f'
Process
Data
Write to
destination
CNT
Z
=
=
0x01
0
If skip:
Q1
After Instruction
CNT
=
0x00
1
Q2
Q3
Q4
Z
=
No
No
No
No
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT, 1
HERE
Example:
NZERO
ZERO
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
=
CNT - 1
0;
Address (HERE)
0;
Address (NZERO)
1998-2013 Microchip Technology Inc.
DS30289C-page 211
PIC17C7XX
DCFSNZ
Syntax:
Decrement f, skip if not 0
GOTO
Unconditional Branch
[ label ] GOTO k
0 k 8191
[label] DCFSNZ f,d
Syntax:
Operands:
0 f 255
d [0,1]
Operands:
Operation:
k PC<12:0>;
Operation:
(f) – 1 (dest);
skip if not 0
k<12:8> PCLATH<4:0>,
PC:13> PCLATH<7:5>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
011d
ffff
ffff
110k
kkkk
kkkk
kkkk
The contents of register 'f' are decre-
mented. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is placed
back in register 'f'.
GOTOallows an unconditional branch
anywhere within an 8K page boundary.
The thirteen-bit immediate value is
loaded into PC bits <12:0>. Then the
upper eight bits of PC are loaded into
PCLATH. GOTOis always a two-cycle
instruction.
Description:
Description:
If the result is not 0, the next instruc-
tion, which is already fetched is dis-
carded and a NOPis executed instead,
making it a two-cycle instruction.
Words:
1
2
Words:
1
Cycles:
Cycles:
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'k'
Process
Data
Write to PC
Decode
Read
register 'f'
Process
Data
Write to
destination
No
No
No
No
operation
operation
operation
operation
If skip:
Q1
Q2
Q3
Q4
GOTO THERE
Example:
No
No
No
No
operation
operation
operation
operation
After Instruction
PC
=
Address (THERE)
HERE
ZERO
NZERO
DCFSNZ TEMP, 1
:
:
Example:
Before Instruction
TEMP_VALUE
=
?
After Instruction
TEMP_VALUE
If TEMP_VALUE
PC
=
=
=
=
TEMP_VALUE - 1,
0;
Address (ZERO)
0;
Address (NZERO)
If TEMP_VALUE
PC
DS30289C-page 212
1998-2013 Microchip Technology Inc.
PIC17C7XX
INCF
Increment f
INCFSZ
Syntax:
Increment f, skip if 0
Syntax:
Operands:
[ label ] INCF f,d
[ label ] INCFSZ f,d
0 f 255
d [0,1]
Operands:
0 f 255
d [0,1]
Operation:
(f) + 1 (dest)
Operation:
(f) + 1 (dest)
skip if result = 0
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
None
0001
010d
ffff
ffff
0001
111d
ffff
ffff
The contents of register 'f' are incre-
mented. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is placed
back in register 'f'.
Description:
The contents of register 'f' are incre-
mented. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is placed
back in register 'f'.
Description:
Words:
1
1
If the result is 0, the next instruction,
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
1
Decode
Read
register 'f'
Process
Data
Write to
destination
Cycles:
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
INCF
CNT, 1
Example:
Decode
Read
register 'f'
Process
Data
Write to
destination
Before Instruction
CNT
=
0xFF
Z
C
=
=
0
?
If skip:
Q1
Q2
Q3
Q4
After Instruction
No
operation
No
No
No
CNT
Z
C
=
=
=
0x00
1
1
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
=
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
1998-2013 Microchip Technology Inc.
DS30289C-page 213
PIC17C7XX
INFSNZ
Syntax:
Increment f, skip if not 0
IORLW
Inclusive OR Literal with WREG
[ label ] IORLW k
0 k 255
[label] INFSNZ f,d
Syntax:
Operands:
0 f 255
d [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
(WREG) .OR. (k) (WREG)
Z
Operation:
(f) + 1 (dest),
skip if not 0
1011
0011
kkkk
kkkk
Status Affected:
Encoding:
None
The contents of WREG are OR’ed with
the eight-bit literal 'k'. The result is
placed in WREG.
0010
010d
ffff
ffff
The contents of register 'f' are incre-
mented. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is placed
back in register 'f'.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
If the result is not 0, the next instruction,
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
1
Cycles:
1(2)
IORLW
0x35
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WREG
=
0x9A
Decode
Read
register 'f'
Process
Data
Write to
destination
After Instruction
WREG
=
0xBF
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
HERE
ZERO
NZERO
INFSNZ REG, 1
Example:
Before Instruction
REG
=
REG
After Instruction
REG
If REG
PC
If REG
PC
=
=
=
=
=
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
DS30289C-page 214
1998-2013 Microchip Technology Inc.
PIC17C7XX
IORWF
Inclusive OR WREG with f
LCALL
Long Call
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] LCALL
0 k 255
k
Operands:
0 f 255
d [0,1]
Operands:
Operation:
PC + 1 TOS;
Operation:
(WREG) .OR. (f) (dest)
k PCL, (PCLATH) PCH
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
0000
100d
ffff
ffff
1011
0111
kkkk
kkkk
Inclusive OR WREG with register 'f'. If
'd' is 0, the result is placed in WREG. If
'd' is 1, the result is placed back in
register 'f'.
LCALLallows an unconditional subrou-
tine call to anywhere within the 64K
program memory space.
Description:
Description:
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit desti-
nation address is then loaded into the
program counter. The lower 8-bits of
the destination address are embedded
in the instruction. The upper 8-bits of
PC are loaded from PC high holding
latch, PCLATH.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Words:
1
2
Cycles:
IORWF RESULT, 0
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
RESULT =
WREG
0x13
0x91
Decode
Read
literal 'k'
Process
Data
Write
register PCL
=
After Instruction
RESULT =
No
operation
No
operation
No
operation
No
operation
0x13
0x93
WREG
=
MOVLW HIGH(SUBROUTINE)
MOVPF WREG, PCLATH
Example:
LCALL LOW(SUBROUTINE)
Before Instruction
SUBROUTINE =
16-bit Address
?
PC
=
After Instruction
PC
=
Address (SUBROUTINE)
1998-2013 Microchip Technology Inc.
DS30289C-page 215
PIC17C7XX
MOVFP
Syntax:
Move f to p
MOVLB
Move Literal to low nibble in BSR
[ label ] MOVLB k
0 k 15
[label] MOVFP f,p
Syntax:
Operands:
0 f 255
0 p 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
k (BSR<3:0>)
None
Operation:
(f) (p)
Status Affected:
Encoding:
None
1011
1000
uuuu
kkkk
011p
pppp
ffff
ffff
The four-bit literal 'k' is loaded in the
Bank Select Register (BSR). Only the
low 4-bits of the Bank Select Register
are affected. The upper half of the BSR
is unchanged. The assembler will
encode the “u” fields as '0'.
Move data from data memory location 'f'
to data memory location 'p'. Location 'f'
can be anywhere in the 256 byte data
space (00h to FFh), while 'p' can be 00h
to 1Fh.
Description:
Either ’p' or 'f' can be WREG (a useful,
special situation).
Words:
1
1
Cycles:
MOVFPis particularly useful for transfer-
ring a data memory location to a periph-
eral register (such as the transmit buffer
or an I/O port). Both 'f' and 'p' can be
indirectly addressed.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write literal
'k' to
Words:
1
1
BSR<3:0>
Cycles:
Q Cycle Activity:
Q1
MOVLB
5
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register 'f'
Process
Data
Write
register 'p'
BSR register
=
=
0x22
After Instruction
BSR register
0x25 (Bank 5)
MOVFP
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x33,
0x11
After Instruction
REG1
=
=
0x33,
0x33
REG2
DS30289C-page 216
1998-2013 Microchip Technology Inc.
PIC17C7XX
Move Literal to high nibble in
BSR
MOVLR
MOVLW
Move Literal to WREG
[ label ] MOVLW k
0 k 255
Syntax:
[ label ] MOVLR k
0 k 15
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
k (BSR<7:4>)
None
k (WREG)
None
1011
101x
kkkk
uuuu
1011
0000
kkkk
kkkk
The 4-bit literal 'k' is loaded into the
most significant 4-bits of the Bank
Select Register (BSR). Only the high
4-bits of the Bank Select Register
are affected. The lower half of the
BSR is unchanged. The assembler
will encode the “u” fields as 0.
The eight-bit literal 'k' is loaded into
WREG.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
1
1
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
MOVLW
0x5A
Example:
Decode
Read literal
'k'
Process
Data
Write
literal 'k' to
BSR<7:4>
After Instruction
WREG
=
0x5A
MOVLR
5
Example:
Before Instruction
BSR register
=
=
0x22
0x52
After Instruction
BSR register
1998-2013 Microchip Technology Inc.
DS30289C-page 217
PIC17C7XX
MOVPF
Syntax:
Move p to f
MOVWF
Move WREG to f
[ label ] MOVWF
0 f 255
[label] MOVPF p,f
Syntax:
f
Operands:
0 f 255
0 p 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
(WREG) (f)
None
Operation:
(p) (f)
Status Affected:
Encoding:
Z
0000
0001
ffff
ffff
010p
pppp
ffff
ffff
Move data from WREG to register 'f'.
Location 'f' can be anywhere in the 256
byte data space.
Move data from data memory location
'p' to data memory location 'f'. Location
'f' can be anywhere in the 256 byte data
space (00h to FFh), while 'p' can be 00h
to 1Fh.
Description:
Words:
1
1
Cycles:
Either 'p' or 'f' can be WREG (a useful,
special situation).
Q Cycle Activity:
Q1
Q2
Q3
Q4
MOVPFis particularly useful for transfer-
ring a peripheral register (e.g. the timer
or an I/O port) to a data memory loca-
tion. Both 'f' and 'p' can be indirectly
addressed.
Decode
Read
register 'f'
Process
Data
Write
register 'f'
MOVWF
REG
Example:
Words:
1
1
Before Instruction
Cycles:
WREG
REG
=
=
0x4F
0xFF
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
WREG
REG
=
=
0x4F
0x4F
Decode
Read
register 'p'
Process
Data
Write
register 'f'
MOVPF
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x11
0x33
After Instruction
REG1
=
=
0x11
0x11
REG2
DS30289C-page 218
1998-2013 Microchip Technology Inc.
PIC17C7XX
MULLW
Multiply Literal with WREG
MULWF
Multiply WREG with f
Syntax:
[ label ] MULLW
0 k 255
k
Syntax:
[ label ] MULWF
0 f 255
f
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
(k x WREG) PRODH:PRODL
(WREG x f) PRODH:PRODL
None
None
1011
1100
kkkk
kkkk
0011
0100
ffff
ffff
An unsigned multiplication is carried
out between the contents of WREG
and the 8-bit literal 'k'. The 16-bit
result is placed in PRODH:PRODL
register pair. PRODH contains the
high byte.
An unsigned multiplication is carried
out between the contents of WREG
and the register file location 'f'. The
16-bit result is stored in the
PRODH:PRODL register pair.
PRODH contains the high byte.
WREG is unchanged.
Both WREG and 'f' are unchanged.
None of the status flags are affected.
None of the status flags are affected.
Note that neither overflow, nor carry
is possible in this operation. A zero
result is possible, but not detected.
Note that neither overflow, nor carry
is possible in this operation. A zero
result is possible, but not detected.
Words:
1
1
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write
Decode
Read
register 'f'
Process
Data
Write
registers
PRODH:
PRODL
registers
PRODH:
PRODL
MULLW
0xC4
MULWF
REG
Example:
Example:
Before Instruction
Before Instruction
WREG
PRODH
PRODL
=
=
=
0xE2
?
?
WREG
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
After Instruction
WREG
After Instruction
WREG
=
=
=
0xC4
0xAD
0x08
PRODH
PRODL
=
=
=
=
0xC4
0xB5
0x8A
0x94
REG
PRODH
PRODL
1998-2013 Microchip Technology Inc.
DS30289C-page 219
PIC17C7XX
NEGW
Negate W
NOP
No Operation
[ label ] NOP
None
Syntax:
[label] NEGW f,s
Syntax:
Operands:
0 f 255
s [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
No operation
None
Operation:
WREG + 1 (f);
WREG + 1 s
0000
0000
0000
0000
Status Affected:
Encoding:
OV, C, DC, Z
No operation.
0010
110s
ffff
ffff
1
1
WREG is negated using two’s comple-
ment. If 's' is 0, the result is placed in
WREG and data memory location 'f'. If
's' is 1, the result is placed only in data
memory location 'f'.
Description:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
No
Q4
Decode
No
No
operation
Words:
1
1
operation
operation
Cycles:
Q Cycle Activity:
Q1
Example:
None.
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
and other
specified
register
NEGW
REG,0
Example:
Before Instruction
WREG
REG
=
=
0011 1010[0x3A],
1010 1011[0xAB]
After Instruction
WREG
REG
=
=
1100 0110[0xC6]
1100 0110[0xC6]
DS30289C-page 220
1998-2013 Microchip Technology Inc.
PIC17C7XX
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RETLW
Return Literal to WREG
[ label ] RETLW k
0 k 255
Syntax:
Syntax:
Operands:
Operation:
Operands:
Operation:
TOS (PC);
k (WREG); TOS (PC);
0 GLINTD;
PCLATH is unchanged
PCLATH is unchanged.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
GLINTD
1011
0110
kkkk
kkkk
0000
0000
0000
0101
WREG is loaded with the eight-bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Description:
Return from Interrupt. Stack is POP’ed
and Top-of-Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
Description:
Words:
1
2
Words:
1
2
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Process
Data
POP PC
from stack,
Write to
literal 'k'
Decode
No
operation
Clear
GLINTD
POP PC
from stack
WREG
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
RETFIE
Example:
CALL TABLE ; WREG contains table
Example:
After Interrupt
;
;
;
offset value
WREG now has
table value
PC
GLINTD
=
=
TOS
0
:
TABLE
ADDWF PC
; WREG = offset
; Begin table
;
RETLW k0
RETLW k1
:
:
RETLW kn
; End of table
Before Instruction
WREG
=
0x07
After Instruction
WREG
=
value of k7
1998-2013 Microchip Technology Inc.
DS30289C-page 221
PIC17C7XX
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ] RETURN
None
Syntax:
Operands:
[ label ] RLCF f,d
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 f 255
d [0,1]
TOS PC;
None
Operation:
f<n> d<n+1>;
f<7> C;
C d<0>
0000
0000
0000
0010
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter.
Status Affected:
Encoding:
C
0001
101d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is stored
back in register 'f'.
Description:
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
C
Decode
No
operation
Process
Data
POP PC
from stack
Words:
1
1
No
operation
No
operation
No
operation
No
operation
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
RETURN
Example:
After Interrupt
PC = TOS
RLCF
REG,0
Example:
Before Instruction
REG
=
1110 0110
C
=
0
After Instruction
REG
WREG
C
=
=
=
1110 0110
1100 1100
1
DS30289C-page 222
1998-2013 Microchip Technology Inc.
PIC17C7XX
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f,d
Syntax:
Operands:
[ label ] RRCF f,d
Operands:
0 f 255
d [0,1]
0 f 255
d [0,1]
Operation:
f<n> d<n+1>;
f<7> d<0>
Operation:
f<n> d<n-1>;
f<0> C;
C d<7>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
C
0010
001d
ffff
ffff
0001
100d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result is
stored back in register 'f'.
Description:
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is placed
back in register 'f'.
Description:
register f
Words:
1
1
register f
C
Cycles:
Words:
1
1
Q Cycle Activity:
Q1
Cycles:
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
RLNCF
REG, 1
Example:
Before Instruction
RRCF REG1,0
Example:
C
=
0
REG
=
1110 1011
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
C
=
REG
=
1101 0111
After Instruction
REG1
WREG
C
=
=
=
1110 0110
0111 0011
0
1998-2013 Microchip Technology Inc.
DS30289C-page 223
PIC17C7XX
RRNCF
Syntax:
Rotate Right f (no carry)
SETF
Set f
[ label ] RRNCF f,d
Syntax:
Operands:
[ label ] SETF f,s
Operands:
0 f 255
d [0,1]
0 f 255
s [0,1]
Operation:
f<n> d<n-1>;
f<0> d<7>
Operation:
FFh f;
FFh d
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
000d
ffff
ffff
0010
101s
ffff
ffff
The contents of register 'f' are rotated
one bit to the right. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result is
placed back in register 'f'.
If 's' is 0, both the data memory location
'f' and WREG are set to FFh. If 's' is 1,
only the data memory location 'f' is set
to FFh.
Description:
Description:
Words:
1
1
register f
Cycles:
Words:
1
1
Q Cycle Activity:
Q1
Cycles:
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write
Q2
Q3
Q4
register 'f'
and other
specified
register
Decode
Read
register 'f'
Process
Data
Write to
destination
RRNCF
REG, 1
Example 1:
SETF
REG, 0
Example1:
Before Instruction
Before Instruction
WREG
REG
=
=
?
REG
WREG
=
=
0xDA
0x05
1101 0111
After Instruction
After Instruction
WREG
REG
=
=
0
REG
WREG
=
=
0xFF
0xFF
1110 1011
Example2:
SETF
REG, 1
RRNCF
REG, 0
Example 2:
Before Instruction
Before Instruction
REG
WREG
=
=
0xDA
0x05
WREG
REG
=
=
?
1101 0111
After Instruction
After Instruction
REG
WREG
=
=
0xFF
0x05
WREG
REG
=
=
1110 1011
1101 0111
DS30289C-page 224
1998-2013 Microchip Technology Inc.
PIC17C7XX
SLEEP
Enter SLEEP mode
[ label ] SLEEP
None
SUBLW
Subtract WREG from Literal
Syntax:
Syntax:
[ label ] SUBLW k
Operands:
Operation:
Operands:
0 k 255
00h WDT;
0 WDT postscaler;
1 TO;
Operation:
k – (WREG) WREG)
OV, C, DC, Z
Status Affected:
Encoding:
1011
0010
kkkk
kkkk
0 PD
WREG is subtracted from the eight-bit
literal 'k'. The result is placed in
WREG.
Description:
Status Affected:
Encoding:
TO, PD
0000
0000
0000
0011
The power-down status bit (PD) is
cleared. The time-out status bit (TO) is
set. Watchdog Timer and its post-
scaler are cleared.
Description:
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
The processor is put into SLEEP
mode with the oscillator stopped.
Q2
Q3
Q4
Decode
Read
Process
Data
Write to
WREG
Words:
1
1
literal 'k'
Cycles:
SUBLW 0x02
Example 1:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WREG
C
=
=
1
?
Decode
No
Process
Data
Go to
sleep
operation
After Instruction
WREG
C
Z
=
=
=
1
1
0
; result is positive
SLEEP
Example:
Before Instruction
Example 2:
TO
=
?
Before Instruction
PD
=
?
WREG
C
=
=
2
?
After Instruction
TO
=
1 †
After Instruction
PD
=
0
WREG
C
Z
=
=
=
0
1
1
† If WDT causes wake-up, this bit is cleared
; result is zero
Example 3:
Before Instruction
WREG
C
=
=
3
?
After Instruction
WREG
C
Z
=
=
=
FF ; (2’s complement)
0
0
; result is negative
1998-2013 Microchip Technology Inc.
DS30289C-page 225
PIC17C7XX
Subtract WREG from f with
Borrow
SUBWFB
SUBWF
Subtract WREG from f
Syntax:
[ label ] SUBWF f,d
Syntax:
[ label ] SUBWFB f,d
Operands:
0 f 255
d [0,1]
Operands:
0 f 255
d [0,1]
Operation:
(f) – (W) dest)
Operation:
(f) – (W) – C dest)
Status Affected:
Encoding:
OV, C, DC, Z
Status Affected:
Encoding:
OV, C, DC, Z
0000
010d
ffff
ffff
0000
001d
ffff
ffff
Subtract WREG from register 'f' (2’s
complement method). If 'd' is 0, the
result is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'.
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s comple-
ment method). If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result is
stored back in register 'f'.
Description:
Description:
Words:
1
1
Words:
1
1
Cycles:
Cycles:
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Decode
Read
register 'f'
Process
Data
Write to
destination
SUBWF
REG1, 1
Example 1:
SUBWFB REG1, 1
Example 1:
Before Instruction
Before Instruction
REG1
WREG
C
=
=
=
3
2
?
REG1
WREG
C
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
After Instruction
After Instruction
REG1
WREG
C
=
=
=
=
1
2
1
0
REG1
WREG
C
=
=
=
=
0x0C
0x0D
1
(0000 1011)
(0000 1101)
; result is positive
; result is positive
Z
Z
0
Example 2:
Before Instruction
Example2:
SUBWFB REG1,0
Before Instruction
REG1
WREG
C
=
=
=
2
2
?
REG1
WREG
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
After Instruction
After Instruction
REG1
WREG
C
=
=
=
=
0
2
1
1
REG1
WREG
C
=
=
=
=
0x1B
0x00
1
(0001 1011)
; result is zero
; result is zero
Z
Z
1
Example 3:
Before Instruction
Example3:
SUBWFB REG1,1
Before Instruction
REG1
WREG
C
=
=
=
1
2
?
REG1
WREG
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
After Instruction
After Instruction
REG1
WREG
C
=
=
=
=
FF
2
0
REG1
WREG
C
=
=
=
=
0xF5
0x0E
0
(1111 0100) [2’s comp]
(0000 1101)
; result is negative
; result is negative
Z
0
Z
0
DS30289C-page 226
1998-2013 Microchip Technology Inc.
PIC17C7XX
SWAPF
Syntax:
Swap f
TABLRD
Syntax:
Table Read
[ label ] SWAPF f,d
[ label ] TABLRD t,i,f
Operands:
0 f 255
d [0,1]
Operands:
0 f 255
i [0,1]
t [0,1]
Operation:
f<3:0> dest<7:4>;
f<7:4> dest<3:0>
Operation:
If t = 1,
TBLATH f;
If t = 0,
TBLATL f;
Status Affected:
Encoding:
None
0001
110d
ffff
ffff
Prog Mem (TBLPTR) TBLAT;
If i = 1,
TBLPTR + 1 TBLPTR
If i = 0,
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result is
placed in register 'f'.
Description:
TBLPTR is unchanged
Words:
1
1
Status Affected:
Encoding:
None
Cycles:
Q Cycle Activity:
Q1
1010
10ti
ffff
ffff
Q2
Q3
Q4
1. A byte of the table latch (TBLAT)
is moved to register file 'f'.
Description:
Decode
Read
Process
Data
Write to
destination
If t = 1: the high byte is moved;
If t = 0: the low byte is moved.
register 'f'
2. Then, the contents of the pro-
gram memory location pointed to
by the 16-bit Table Pointer
(TBLPTR) are loaded into the
16-bit Table Latch (TBLAT).
SWAPF
REG,
0
Example:
Before Instruction
REG
=
0x53
0x35
3. If i = 1: TBLPTR is incremented;
If i = 0: TBLPTR is not
incremented.
After Instruction
REG
=
Words:
1
Cycles:
2 (3-cycle if f = PCL)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
Process
Data
Write
register 'f'
TBLATH or
TBLATL
No
No
No
No
operation
operation
(Table Pointer
on Address
bus)
operation
operation
(OE goes low)
1998-2013 Microchip Technology Inc.
DS30289C-page 227
PIC17C7XX
TABLRD
Table Read
TABLWT
Syntax:
Table Write
TABLRD 1, 1, REG ;
Example1:
[ label ] TABLWT t,i,f
Before Instruction
Operands:
0 f 255
i [0,1]
t [0,1]
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
Operation:
If t = 0,
f TBLATL;
MEMORY(TBLPTR)
If t = 1,
f TBLATH;
TBLAT Prog Mem (TBLPTR);
If i = 1,
TBLPTR + 1 TBLPTR
If i = 0,
After Instruction (table write completion)
REG
=
=
=
=
=
0xAA
TBLATH
0x12
TBLATL
0x34
TBLPTR
MEMORY(TBLPTR)
0xA357
0x5678
TBLPTR is unchanged
TABLRD 0, 0, REG ;
Example2:
Status Affected:
Encoding:
None
Before Instruction
1010
11ti
ffff
ffff
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
1. Load value in ’f’ into 16-bit table
latch (TBLAT)
Description:
If t = 1: load into high byte;
If t = 0: load into low byte
MEMORY(TBLPTR)
After Instruction (table write completion)
2. The contents of TBLAT are writ-
ten to the program memory
location pointed to by TBLPTR.
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle.
If TBLPTR points to an internal
EPROM location, then the
instruction is terminated when
an interrupt is received.
REG
=
=
=
=
=
0x55
TBLATH
0x12
TBLATL
0x34
TBLPTR
MEMORY(TBLPTR)
0xA356
0x1234
Note:
The MCLR/VPP pin must be at the programming
voltage for successful programming of internal
memory.
If MCLR/VPP = VDD
the programming sequence of internal memory
will be interrupted. A short write will occur (2
TCY). The internal memory location will not be
affected.
3. The TBLPTR can be automati-
cally incremented
If i = 1; TBLPTR is not
incremented
If i = 0; TBLPTR is incremented
Words:
Cycles:
1
2 (many if write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register
TBLATH or
TBLATL
No
No
No
No
operation
operation
(Table Pointer
on Address
bus)
operation
operation
(Table Latch on
Address bus,
WR goes low)
DS30289C-page 228
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLWT
Table Write
TLRD
Table Latch Read
TABLWT 1, 1, REG
Example1:
Syntax:
Operands:
[ label ] TLRD t,f
Before Instruction
0 f 255
t [0,1]
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0xFFFF
Operation:
If t = 0,
TBLATL f;
If t = 1,
MEMORY(TBLPTR)
TBLATH f
After Instruction (table write completion)
Status Affected:
Encoding:
None
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0x53
0x55
0xA357
0x5355
1010
00tx
ffff
ffff
Read data from 16-bit table latch
(TBLAT) into file register 'f'. Table Latch
is unaffected.
Description:
MEMORY(TBLPTR - 1)
TABLWT 0, 0, REG
Example 2:
If t = 1; high byte is read
If t = 0; low byte is read
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0xFFFF
This instruction is used in conjunction
with TABLRDto transfer data from pro-
gram memory to data memory.
Words:
1
1
MEMORY(TBLPTR)
Cycles:
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
=
=
=
=
=
0x53
0xAA
0x53
0xA356
0xAA53
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
Process
Data
Write
register 'f'
MEMORY(TBLPTR)
TBLATH or
TBLATL
Program
Memory
Data
Memory
15
15
0
0
TLRD
t, RAM
Example:
TBLPTR
Before Instruction
8
7
t
=
=
=
0
?
RAM
TBLAT
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
16 bits
8 bits
TBLAT
After Instruction
RAM
=
0xAF
TBLAT
=
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
Before Instruction
t
=
=
=
1
?
RAM
TBLAT
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
After Instruction
RAM
=
0x00
TBLAT
=
0x00AF (TBLATH = 0x00)
(TBLATL = 0xAF)
Program
Memory
Data
Memory
15
0
TBLPTR
15
8
7
0
16 bits
8 bits
TBLAT
1998-2013 Microchip Technology Inc.
DS30289C-page 229
PIC17C7XX
TLWT
Table Latch Write
TSTFSZ
Test f, skip if 0
[ label ] TSTFSZ f
0 f 255
Syntax:
Operands:
[ label ] TLWT t,f
Syntax:
0 f 255
t [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
skip if f = 0
Operation:
If t = 0,
f TBLATL;
If t = 1,
None
0011
0011
ffff
ffff
f TBLATH
If 'f' = 0, the next instruction, fetched
during the current instruction execution,
is discarded and a NOPis executed,
making this a two-cycle instruction.
Status Affected:
Encoding:
None
1010
01tx
ffff
ffff
Data from file register 'f' is written into
the 16-bit table latch (TBLAT).
Description:
Words:
1
Cycles:
1 (2)
If t = 1; high byte is written
If t = 0; low byte is written
Q Cycle Activity:
Q1
Q2
Q3
Q4
This instruction is used in conjunction
with TABLWTto transfer data from data
memory to program memory.
Decode
Read
Process
Data
No
operation
register 'f'
Words:
1
1
If skip:
Q1
Cycles:
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register
HERE
NZERO
ZERO
TSTFSZ CNT
:
:
Example:
TBLATH or
TBLATL
Before Instruction
TLWT
t, RAM
PC = Address (HERE)
Example:
After Instruction
Before Instruction
If CNT
PC
If CNT
PC
=
=
¼
=
0x00,
Address (ZERO)
0x00,
t
=
=
=
0
RAM
TBLAT
0xB7
0x0000 (TBLATH = 0x00)
(TBLATL = 0x00)
Address (NZERO)
After Instruction
RAM
=
0xB7
TBLAT
=
0x00B7 (TBLATH = 0x00)
(TBLATL = 0xB7)
Before Instruction
t
=
=
=
1
RAM
TBLAT
0xB7
0x0000 (TBLATH = 0x00)
(TBLATL = 0x00)
After Instruction
RAM
=
0xB7
TBLAT
=
0xB700 (TBLATH = 0xB7)
(TBLATL = 0x00)
DS30289C-page 230
1998-2013 Microchip Technology Inc.
PIC17C7XX
Exclusive OR Literal with
WREG
XORLW
XORWF
Syntax:
Exclusive OR WREG with f
Syntax:
[ label ] XORLW k
[ label ] XORWF f,d
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 k 255
Operands:
0 f 255
d [0,1]
(WREG) .XOR. k WREG)
Operation:
(WREG) .XOR. (f) dest)
Z
Status Affected:
Encoding:
Z
1011
0100
kkkk
kkkk
0000
110d
ffff
ffff
The contents of WREG are XOR’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
Exclusive OR the contents of WREG
with register 'f'. If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result is
stored back in the register 'f'.
Description:
Words:
1
1
Cycles:
Words:
1
1
Q Cycle Activity:
Q1
Cycles:
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
XORLW 0xAF
= 0xB5
Example:
Before Instruction
WREG
XORWF
REG, 1
Example:
After Instruction
Before Instruction
WREG
=
0x1A
REG
=
0xAF
0xB5
1010 1111
1011 0101
WREG
=
After Instruction
REG
WREG
=
=
0x1A
0xB5
0001 1010
1998-2013 Microchip Technology Inc.
DS30289C-page 231
PIC17C7XX
NOTES:
DS30289C-page 232
1998-2013 Microchip Technology Inc.
PIC17C7XX
The MPLAB IDE allows you to:
19.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
19.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PIC MCU’s.
- MPLAB ICD for PIC16F87X
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
19.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
19.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
1998-2013 Microchip Technology Inc.
DS30289C-page 233
PIC17C7XX
19.4 MPLINK Object Linker/
MPLIB Object Librarian
19.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC micro-
controllers (MCUs). Software control of the MPLAB ICE
in-circuit emulator is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
building, downloading and source debugging from a
single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PIC microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
19.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
19.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PIC series microcontrollers on an instruction level. On
any given instruction, the data areas can be examined
or modified and stimuli can be applied from a file, or
user-defined key press, to any of the pins. The execu-
tion can be performed in single step, execute until
break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS30289C-page 234
1998-2013 Microchip Technology Inc.
PIC17C7XX
19.8 MPLAB ICD In-Circuit Debugger
19.11 PICDEM 1 Low Cost PIC MCU
Demonstration Board
Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC16F87X and can be used to
develop for this and other PIC microcontrollers from the
PIC16CXXX family. The MPLAB ICD utilizes the in-cir-
cuit debugging capability built into the PIC16F87X. This
feature, along with Microchip's In-Circuit Serial
ProgrammingTM protocol, offers cost-effective in-circuit
FLASH debugging from the graphical user interface of
the MPLAB Integrated Development Environment. This
enables a designer to develop and debug source code
by watching variables, single-stepping and setting
break points. Running at full speed enables testing
hardware in real-time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
19.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program PIC
MCU devices. It can also set code protection in this
mode.
19.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
19.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PIC devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
1998-2013 Microchip Technology Inc.
DS30289C-page 235
PIC17C7XX
19.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
19.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
19.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS30289C-page 236
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 19-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m r e g g u b D e s r e m m a o g P r r
s t K l a i E d v n a s d r a B o o m D e
1998-2013 Microchip Technology Inc.
DS30289C-page 237
PIC17C7XX
NOTES:
DS30289C-page 238
1998-2013 Microchip Technology Inc.
PIC17C7XX
20.0 PIC17C7XX ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ........................................................................................................... 0 V to +7.5 V
Voltage on MCLR with respect to VSS (Note 2) ....................................................................................... -0.3 V to +14 V
Voltage on RA2 and RA3 with respect to VSS.......................................................................................... -0.3 V to +8.5 V
Voltage on all other pins with respect to VSS ...................................................................................-0.3 V to VDD + 0.3 V
Total power dissipation (Note 1) ..............................................................................................................................1.0 W
Maximum current out of VSS pin(s) - total (@ 70°C)............................................................................................500 mA
Maximum current into VDD pin(s) - total (@ 70°C)...............................................................................................500 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA
Maximum output current sunk by any I/O pin (except RA2 and RA3).....................................................................35 mA
Maximum output current sunk by RA2 or RA3 pins ................................................................................................60 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA and PORTB (combined).................................................................................150 mA
Maximum current sourced by PORTA and PORTB (combined) ...........................................................................100 mA
Maximum current sunk by PORTC, PORTD and PORTE (combined)..................................................................150 mA
Maximum current sourced by PORTC, PORTD and PORTE (combined) ............................................................100 mA
Maximum current sunk by PORTF and PORTG (combined)................................................................................150 mA
Maximum current sourced by PORTF and PORTG (combined)...........................................................................100 mA
Maximum current sunk by PORTH and PORTJ (combined).................................................................................150 mA
Maximum current sourced by PORTH and PORTJ (combined) ...........................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than
pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at those or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
1998-2013 Microchip Technology Inc.
DS30289C-page 239
PIC17C7XX
FIGURE 20-1:
PIC17C7XX-33 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
PIC17C7XX-33
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
33 MHz
Frequency
FIGURE 20-2:
PIC17C7XX-16 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
PIC17C7XX-16
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
16 MHz
Frequency
DS30289C-page 240
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-3:
PIC17LC7XX-08 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC17LC7XX-08
3.5 V
3.0 V
2.5 V
2.0 V
8 MHz
Frequency
FIGURE 20-4:
PIC17C7XX/CL VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
PIC17C7XX/CL
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
8 MHz
33 MHz
Frequency
1998-2013 Microchip Technology Inc.
DS30289C-page 241
PIC17C7XX
20.1 DC Characteristics
Standard Operating Conditions (unless otherwise stated)
Operating temperature
PIC17LC7XX-08
(Commercial, Industrial)
-40°C TA +85°C for industrial and
0°C TA +70°C for commercial
Standard Operating Conditions (unless otherwise stated)
Operating temperature
PIC17C7XX-16
(Commercial, Industrial, Extended)
PIC17C7XX-33
-40°C TA +125°C for extended
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
(Commercial, Industrial, Extended)
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
D001
VDD
Supply Voltage
3.0
—
5.5
V
PIC17LC7XX
D001
D002
D003
PIC17C7XX-33
PIC17C7XX-16
4.5
VBOR
—
—
5.5
5.5
V
V
(BOR enabled) (Note 5)
VDR
RAM Data Retention
Voltage (Note 1)
1.5
—
—
—
V
Device in SLEEP mode
VPOR
VDD Start Voltage to
ensure internal
Vss
—
V
See section on Power-on
Reset for details
Power-on Reset signal
D004
SVDD
VDD Rise Rate to ensure proper operation
PIC17LCXX
0.010
0.085
3.65
—
—
—
—
V/ms See section on Power-on
Reset for details
D004
D005
D006
PIC17CXX
—
V/ms See section on Power-on
Reset for details
VBOR
Brown-out Reset
voltage trip point
—
4.35
—
V
VPORTP
Power-on Reset trip
2.2
V
VDD = VPORTP
point
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be
considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as:
VDD/(2 R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CLVDD) f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
Extended Microcontroller mode).
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2REXT (mA) with REXT in kOhm.
5: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device (-16)
will operate correctly to this trip point.
DS30289C-page 242
1998-2013 Microchip Technology Inc.
PIC17C7XX
Standard Operating Conditions (unless otherwise stated)
Operating temperature
PIC17LC7XX-08
(Commercial, Industrial)
-40°C TA +85°C for industrial and
0°C TA +70°C for commercial
Standard Operating Conditions (unless otherwise stated)
Operating temperature
PIC17C7XX-16
(Commercial, Industrial, Extended)
PIC17C7XX-33
-40°C TA +125°C for extended
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
(Commercial, Industrial, Extended)
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
D010
IDD
Supply Current (Note 2)
PIC17LC7XX
—
—
—
3
3
5
6
6
mA
mA
mA
FOSC = 4 MHz (Note 4)
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
D010
D011
PIC17C7XX
PIC17LC7XX
10
D011
D012
PIC17C7XX
—
—
5
9
10
18
mA
mA
FOSC = 8 MHz
FOSC = 16 MHz
D014
PIC17LC7XX
—
85
150
A
FOSC = 32 kHz,
(EC osc configuration)
D015
D021
PIC17C7XX
—
15
30
mA
FOSC = 33 MHz
IPD
Power-down Current (Note 3)
PIC17LC7XX
PIC17C7XX
—
—
<1
<1
5
A
A
VDD = 3.0V, WDT disabled
VDD = 5.5V, WDT disabled
D021
20
(commercial,
industrial)
D021A
(extended)
—
–
2
20
A
VDD = 5.5V, WDT disabled
Module Differential Current
D023
IBOR
BOR circuitry
75
150
A
VDD = 4.5V, BODEN
enabled
D024
D026
IWDT
IAD
Watchdog Timer
A/D converter
–
–
10
1
35
–
A
A
VDD = 5.5V
VDD = 5.5V, A/D not
converting
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be
considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as:
VDD/(2 R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CLVDD) f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
Extended Microcontroller mode).
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2REXT (mA) with REXT in kOhm.
5: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device (-16)
will operate correctly to this trip point.
1998-2013 Microchip Technology Inc.
DS30289C-page 243
PIC17C7XX
20.2 DC Characteristics: PIC17C7XX-16 (Commercial, Industrial, Extended)
PIC17C7XX-33 (Commercial, Industrial, Extended)
PIC17LC7XX-08 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
Operating voltage VDD range as described in Section 20.1
TA +125°C for extended
DC CHARACTERISTICS
Param.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
Input Low Voltage
I/O ports
VIL
D030
D031
with TTL buffer (Note 6)
Vss
Vss
–
–
0.8
0.2VDD
V
V
4.5V VDD 5.5V
3.0V VDD 4.5V
with Schmitt Trigger buffer
RA2, RA3
All others
Vss
Vss
–
–
0.3VDD
0.2VDD
V
V
I2C compliant
D032
D033
MCLR, OSC1 (in EC and RC
mode)
Vss
–
0.2VDD
V
(Note 1)
OSC1 (in XT, and LF mode)
Input High Voltage
I/O ports
–
0.5VDD
–
V
VIH
D040
D041
with TTL buffer (Note 6)
2.0
1+ 0.2VDD
–
–
VDD
VDD
V
V
4.5V VDD 5.5V
3.0V VDD 4.5V
with Schmitt Trigger buffer
RA2, RA3
All others
0.7VDD
0.8VDD
–
–
VDD
VDD
V
V
I2C compliant
D042
D043
D050
MCLR
0.8VDD
–
–
0.5VDD
–
VDD
–
V
V
V
(Note 1)
OSC1 (XT, and LF mode)
VHYS
Hysteresis of
0.15VDD
–
Schmitt Trigger Inputs
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. Higher leakage
current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17C7XX Programming
Specifications (Literature number DS TBD).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
DS30289C-page 244
1998-2013 Microchip Technology Inc.
PIC17C7XX
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
Operating voltage VDD range as described in Section 20.1
TA +125°C for extended
DC CHARACTERISTICS
Param.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
Input Leakage Current
(Notes 2, 3)
D060
IIL
I/O ports (except RA2, RA3)
–
–
1
A
Vss VPIN VDD,
I/O Pin (in digital mode) at
hi-impedance PORTB
weak pull-ups disabled
D061
D062
D063
D063B
D064
MCLR, TEST
–
–
2
2
1
VPIN
25
A
A
A
A
A
VPIN =Vss orVPIN =VDD
Vss VRA2, VRA3 12V
Vss VPIN VDD
RF 1 M
VMCLR = VPP = 12V
RA2, RA3
OSC1 (EC, RC modes)
OSC1 (XT, LF modes)
MCLR, TEST
–
–
–
–
–
–
(when not programming)
D070
D080
IPURB PORTB Weak Pull-up Current
85
130
260
A
VPIN = VSS, RBPU = 0
4.5V VDD 5.5V
Output Low Voltage
VOL
I/O ports
IOL = VDD/1.250 mA
4.5V VDD 5.5V
VDD 3.0V
IOL = 6 mA, VDD = 4.5V
(Note 6)
–
–
–
–
–
–
0.1VDD
0.1VDD
0.4
V
V
V
D081
D082
with TTL buffer
RA2 and RA3
–
–
–
–
3.0
0.6
V
V
IOL = 60.0 mA, VDD = 5.5V
IOL = 60.0 mA, VDD = 4.5V
D083
D084
OSC2/CLKOUT
(RC and EC osc modes)
–
–
–
–
0.4
0.1VDD
V
V
IOL = 1 mA, VDD = 4.5V
IOL = VDD/5 mA
(PIC17LC7XX only)
Output High Voltage (Note 3)
D090
D091
VOH
I/O ports (except RA2 and
RA3)
IOH = -VDD/2.5 mA
4.5V VDD 5.5V
VDD 3.0V
0.9VDD
0.9VDD
2.4
–
–
–
–
–
–
V
V
V
IOH = -6.0 mA, VDD = 4.5V
with TTL buffer
(Note 6)
D093
D094
OSC2/CLKOUT
(RC and EC osc modes)
2.4
0.9VDD
–
–
–
–
V
V
IOH = -5 mA, VDD = 4.5V
IOH = -VDD/5 mA
(PIC17LC7XX only)
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. Higher leakage
current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17C7XX Programming
Specifications (Literature number DS TBD).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
1998-2013 Microchip Technology Inc.
DS30289C-page 245
PIC17C7XX
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
Operating voltage VDD range as described in Section 20.1
TA +125°C for extended
DC CHARACTERISTICS
Param.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
D150
VOD
Open Drain High Voltage
–
–
8.5
V
RA2 and RA3 pins only
pulled up to externally
applied voltage
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2/CLKOUT pin
–
–
25
pF
In EC or RC osc modes,
when OSC2 pin is outputting
CLKOUT. External clock is
used to drive OSC1.
D101
CIO
All I/O pins and OSC2
(in RC mode)
–
–
50
pF
CAD
System Interface Bus
(PORTC, PORTD and PORTE)
–
–
50
pF
In Microprocessor or
Extended Microcontroller
mode
D102
Internal Program Memory
Programming Specs (Note 4)
D110
D111
VPP
VDDP
Voltage on MCLR/VPP pin
Supply voltage during
programming
12.75
4.75
–
5.0
13.25
5.25
V
V
(Note 5)
D112
D113
IPP
IDDP
Current into MCLR/VPP pin
Supply current during
programming
–
–
25
–
50
30
mA
mA
D114
TPROG Programming pulse width
100
–
1000
ms Terminated via internal/
external interrupt or a
RESET
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXXX devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. Higher leakage
current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17C7XX Programming
Specifications (Literature number DS TBD).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
Note 1: When using the Table Write for internal programming, the device temperature must be less than 40°C.
2: For In-Circuit Serial Programming (ICSP), refer to the device programming specification.
DS30289C-page 246
1998-2013 Microchip Technology Inc.
PIC17C7XX
20.3 Timing Parameter Symbology
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
ad
T
Time
Address/Data
ALE
ost
pwrt
rb
Oscillator Start-Up Timer
Power-Up Timer
PORTB
al
cc
ck
dt
Capture1 and Capture2
CLKOUT or clock
Data in
rd
RD
rw
RD or WR
in
INT pin
t0
T0CKI
io
I/O port
t123
wdt
wr
TCLK12 and TCLK3
Watchdog Timer
WR
mc
oe
os
MCLR
OE
OSC1
Uppercase symbols and their meanings:
S
D
E
F
H
I
Driven
L
Low
Edge
P
R
V
Z
Period
Rise
Fall
High
Valid
Invalid (Hi-impedance)
Hi-impedance
1998-2013 Microchip Technology Inc.
DS30289C-page 247
PIC17C7XX
FIGURE 20-5:
PARAMETER MEASUREMENT INFORMATION
All timings are measured between high and low
measurement points as indicated below.
INPUT LEVEL CONDITIONS
PORTC, D, E, F, G, H and J pins
VIH = 2.4V
VIL = 0.4V
Data in valid
Data in valid
All other input pins
Data in invalid
VIH = 0.9VDD
VIL = 0.1VDD
Data in invalid
OUTPUT LEVEL CONDITIONS
0.25V
0.25V
VOH = 0.7VDD
VDD/2
VOL = 0.3VDD
0.25V
0.25V
Data out valid
Output
driven
Output
hi-impedance
Data out invalid
0.9 VDD
Fall Time
0.1 VDD
Rise Time
LOAD CONDITIONS
Load Condition 1
Pin
C
L
VSS
50 pF C
L
DS30289C-page 248
1998-2013 Microchip Technology Inc.
PIC17C7XX
20.4 Timing Diagrams and Specifications
FIGURE 20-6:
EXTERNAL CLOCK TIMING
Q4
Q3
3
Q4
3
Q1
Q1
Q2
OSC1
1
4
4
2
OSC2 †
† In EC and RC modes only.
TABLE 20-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
FOSC External CLKIN
DC
DC
DC
—
—
—
8
16
33
MHz EC osc mode - 08 devices (8 MHz devices)
Frequency (Note 1)
MHz
MHz
- 16 devices (16 MHz devices)
- 33 devices (33 MHz devices)
Oscillator Frequency
(Note 1)
DC
2
2
2
DC
—
—
—
—
—
4
8
16
33
2
MHz RC osc mode
MHz XT osc mode - 08 devices (8 MHz devices)
MHz
MHz
- 16 devices (16 MHz devices)
- 33 devices (33 MHz devices)
MHz LF osc mode
1
TOSC
External CLKIN Period
(Note 1)
125
62.5
30.3
—
—
—
—
—
—
ns
ns
ns
EC osc mode - 08 devices (8 MHz devices)
- 16 devices (16 MHz devices)
- 33 devices (33 MHz devices)
Oscillator Period
(Note 1)
250
125
62.5
30.3
500
—
—
—
—
—
—
ns
ns
ns
ns
ns
RC osc mode
1,000
1,000
1,000
—
XT osc mode - 08 devices (8 MHz devices)
- 16 devices (16 MHz devices)
- 33 devices (33 MHz devices)
LF osc mode
2
3
TCY
Instruction Cycle Time
(Note 1)
121.2 4/FOSC
DC
—
5
ns
ns
ns
TosL, Clock in (OSC1)
TosH High or Low Time
10
—
—
—
EC oscillator
EC oscillator
4
TosR, Clock in (OSC1)
TosF Rise or Fall Time
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
1998-2013 Microchip Technology Inc.
DS30289C-page 249
PIC17C7XX
FIGURE 20-7:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
OSC2 †
13
12
18
16
14
19
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
† In EC and RC modes only.
TABLE 20-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
OSC1 to CLKOUT
Min
Typ†
Max
Units Conditions
10
11
12
13
14
15
16
17
18
TosL2ckL
TosL2ckH
TckR
—
—
—
—
—
15
15
5
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
OSC1 to CLKOUT
30
CLKOUT rise time
15
TckF
CLKOUT fall time
5
15
TckH2ioV
TioV2ckH
TckH2ioI
TosL2ioV
TosL2ioI
CLKOUT to Port out valid
Port in valid before CLKOUT
Port in hold after CLKOUT
OSC1 (Q1 cycle) to Port out valid
—
—
—
—
—
0.5TCY + 20
0.25TCY + 25
—
—
0
—
0
100
—
OSC1 (Q2 cycle) to Port input
invalid
(I/O in hold time)
19
TioV2osL
Port input valid to OSC1
30
—
—
ns
(I/O in setup time)
20
21
22
23
TioR
Port output rise time
Port output fall time
INT pin high or low time
—
—
25
25
10
10
—
—
35
35
—
—
ns
ns
ns
ns
TioF
TinHL
TrbHL
RB7:RB0 change INT high or low
time
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Measurements are taken in EC mode, where CLKOUT output is 4 x TOSC.
DS30289C-page 250
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP
TIMER, AND BROWN-OUT RESET TIMING
VDD
MCLR
30
Internal
POR/BOR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
35
Address/
Data
TABLE 20-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
31
TmcL
TWDT
MCLR Pulse Width (low)
100
5
—
—
ns
VDD = 5V
Watchdog Timer Time-out Period
(Postscale = 1)
12
25
ms
VDD = 5V
32
33
TOST
Oscillation Start-up Timer Period
Power-up Timer Period
—
1024TOSC
96
—
ms
ms
TOSC = OSC1 period
VDD = 5V
TPWRT
40
200
34
35
TIOZ
MCLR to I/O hi-impedance
100
—
—
ns
Depends on pin load
TmcL2adI MCLR to System
Interface bus
PIC17C7XX
—
—
—
—
100
120
ns
ns
PIC17LC7XX
(AD15:AD0>) invalid
36
TBOR
Brown-out Reset Pulse Width (low)
100
—
—
ns
VDD within VBOR limits
(parameter D005)
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
.
1998-2013 Microchip Technology Inc.
DS30289C-page 251
PIC17C7XX
FIGURE 20-9:
TIMER0 EXTERNAL CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 20-4: TIMER0 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
40
Tt0H T0CKI High Pulse Width No Prescaler
With Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
10
0.5TCY + 20
10
41
42
Tt0L T0CKI Low Pulse Width No Prescaler
With Prescaler
Tt0P T0CKI Period
Greater of:
20 ns or TCY + 40
N
N = prescale
value (1, 2, 4, ...,
256)
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
FIGURE 20-10:
TIMER1, TIMER2 AND TIMER3 EXTERNAL CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 20-5: TIMER1, TIMER2 AND TIMER3 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
45
46
47
Tt123H
Tt123L
Tt123P
TCLK12 and TCLK3 high time
TCLK12 and TCLK3 low time
TCLK12 and TCLK3 input period
0.5TCY + 20
0.5TCY + 20
—
—
—
—
—
—
ns
ns
ns
TCY + 40
N
N = prescale
value (1, 2, 4, 8)
48
TckE2tmrI Delay from selected External Clock Edge to
Timer increment
2TOSC
—
6Tosc
—
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
DS30289C-page 252
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-11:
CAPTURE TIMINGS
CAP pin
(Capture mode)
50
51
52
TABLE 20-6: CAPTURE REQUIREMENTS
Param
No.
Typ
†
Unit
s
Sym
Characteristic
Min
Max
Conditions
50
51
52
TccL Capture pin input low time
TccH Capture pin input high time
TccP Capture pin input period
10
10
—
—
—
—
—
—
ns
ns
ns
2TCY
N
N = prescale value
(4 or 16)
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
FIGURE 20-12:
PWM TIMINGS
PWM pin
(PWM mode)
53
54
TABLE 20-7: PWM REQUIREMENTS
Param
No.
Typ
†
Sym
Characteristic
Min
Max Units
Conditions
53
54
TccR PWM pin output rise time
TccF PWM pin output fall time
—
—
10
10
35
35
ns
ns
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
1998-2013 Microchip Technology Inc.
DS30289C-page 253
PIC17C7XX
FIGURE 20-13:
SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note:
Refer to Figure 20-5 for load conditions.
TABLE 20-8: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
70
TssL2scH,
TssL2scL
SS to SCK or SCK input
Tcy
—
—
ns
71
71A
72
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
40
1.25TCY + 30
40
(Note 1)
(Note 1)
TscL
SCK input low time
(Slave mode)
72A
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40
100
—
—
—
—
ns
ns
(Note 1)
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
75
76
78
79
80
TdoR
TdoF
TscR
TscF
SDO data output rise time
—
—
—
—
—
10
10
10
10
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDO data output fall time
SCK output rise time (Master mode)
SCK output fall time (Master mode)
SDO data output valid after SCK edge
TscH2doV,
TscL2doV
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30289C-page 254
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-14:
SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note:
Refer to Figure 20-5 for load conditions.
TABLE 20-9: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
TscH
Characteristic
SCK input high time
Min
Typ† Max Units
Conditions
71
71A
72
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
(Slave mode)
40
1.25 TCY + 30
40
(Note 1)
(Note 1)
TscL
SCK input low time
(Slave mode)
72A
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40
100
—
—
—
—
ns
ns
(Note 1)
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
75
76
78
79
80
TdoR
TdoF
TscR
TscF
SDO data output rise time
—
—
—
—
—
10
10
10
10
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDO data output fall time
SCK output rise time (Master mode)
SCK output fall time (Master mode)
SDO data output valid after SCK edge
TscH2doV,
TscL2doV
81
†
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
Tcy
—
—
ns
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
1998-2013 Microchip Technology Inc.
DS30289C-page 255
PIC17C7XX
FIGURE 20-15:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note:
Refer to Figure 20-5 for load conditions.
TABLE 20-10: SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
70
TssL2scH,
TssL2scL
SS to SCK or SCK input
Tcy
—
—
ns
71
71A
72
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
40
1.25TCY + 30
40
(Note 1)
(Note 1)
TscL
SCK input low time
(Slave mode)
72A
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40
100
—
—
—
—
ns
ns
(Note 1)
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
75
76
TdoR
TdoF
SDO data output rise time
SDO data output fall time
—
—
10
10
25
25
ns
ns
77
78
79
80
TssH2doZ
TscR
SS to SDO output hi-impedance
SCK output rise time (Master mode)
SCK output fall time (Master mode)
SDO data output valid after SCK edge
10
—
—
—
—
10
10
—
50
25
25
50
ns
ns
ns
ns
TscF
TscH2doV,
TscL2doV
83
†
TscH2ssH,
TscL2ssH
SS after SCK edge
1.5TCY + 40
—
—
ns
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30289C-page 256
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-16:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note:
Refer to Figure 20-5 for load conditions.
TABLE 20-11: SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
70
TssL2scH,
TssL2scL
SS to SCK or SCK input
Tcy
—
—
ns
71
71A
72
TscH
TscL
TB2B
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
40
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
(Note 1)
SCK input low time
(Slave mode)
1.25TCY + 30
40
72A
73A
(Note 1)
(Note 1)
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75
76
TdoR
TdoF
SDO data output rise time
SDO data output fall time
—
—
10
10
25
25
ns
ns
77
80
TssH2doZ
SS to SDO output hi-impedance
10
—
—
—
50
50
ns
ns
TscH2doV,
TscL2doV
SDO data output valid after SCK edge
82
83
TssL2doV
SDO data output valid after SS edge
SS after SCK edge
—
—
—
50
—
ns
ns
TscH2ssH,
TscL2ssH
1.5TCY + 40
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
1998-2013 Microchip Technology Inc.
DS30289C-page 257
PIC17C7XX
FIGURE 20-17:
I2C BUS START/STOP BITS TIMING
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 20-5 for load conditions.
TABLE 20-12: I2C BUS START/STOP BITS REQUIREMENTS
Param.
No.
Ty
p
Sym
Characteristic
Min
Max Units
Conditions
90
Tsu:sta
START condition
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Only relevant for
Repeated Start condition
Setup time
(1)
1 MHz mode
91
92
93
Thd:sta
Tsu:sto
Thd:sto
START condition
Hold time
100 kHz mode
400 kHz mode
After this period, the first
clock pulse is generated
(1)
1 MHz mode
STOP condition
Setup time
100 kHz mode
400 kHz mode
(1)
1 MHz mode
STOP condition
Hold time
100 kHz mode
400 kHz mode
(1)
1 MHz mode
2
Note 1: Maximum pin capacitance = 10 pF for all I C pins.
DS30289C-page 258
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-18:
I2C BUS DATA TIMING
103
102
100
101
109
SCL
90
106
91
92
107
SDA
In
110
109
SDA
Out
Note:
Refer to Figure 20-5 for load conditions.
TABLE 20-13: I2C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
Thigh
Clock high time
2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
400 kHz mode
2(TOSC)(BRG + 1)
(1)
1 MHz mode
2(TOSC)(BRG + 1)
—
101
102
103
90
Tlow
Tr
Clock low time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
2(TOSC)(BRG + 1)
—
(1)
1 MHz mode
2(TOSC)(BRG + 1)
—
SDA and SCL rise time 100 kHz mode
400 kHz mode
—
1000
300
300
300
300
10
Cb is specified to be from
10 to 400 pF
20 + 0.1Cb
ns
(1)
1 MHz mode
—
ns
Tf
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
ns
Cb is specified to be from
10 to 400 pF
20 + 0.1Cb
ns
(1)
1 MHz mode
—
ns
Tsu:sta START condition setup 100 kHz mode
2(TOSC)(BRG + 1)
—
ms
ms
ms
ms
ms
ms
ns
Only relevant for Repeated
Start condition
time
400 kHz mode
2(TOSC)(BRG + 1)
—
(1)
1 MHz mode
2(TOSC)(BRG + 1)
—
91
Thd:sta START condition hold
time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
After this period, the first
clock pulse is generated
2(TOSC)(BRG + 1)
—
(1)
1 MHz mode
2(TOSC)(BRG + 1)
—
106
107
92
Thd:dat Data input hold time
Tsu:dat Data input setup time
100 kHz mode
400 kHz mode
0
—
0
0.9
—
ms
ns
(1)
1 MHz mode
0
100 kHz mode
250
—
ns
(Note 2)
400 kHz mode
100
—
ns
(1)
1 MHz mode
100
—
ns
Tsu:sto STOP condition
setup time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
2(TOSC)(BRG + 1)
—
(1)
1 MHz mode
2(TOSC)(BRG + 1)
—
109
Taa
Output valid from clock 100 kHz mode
400 kHz mode
—
—
—
3500
1000
400
ns
(1)
1 MHz mode
ns
2
Note 1: Maximum pin capacitance = 10 pF for all I C pins.
2
2
2: A fast mode (400 KHz) I C bus device can be used in a standard mode I C bus system, but the parameter # 107 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter #102 + #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line is released.
3: C is specified to be from 10-400pF. The minimum specifications are characterized with C =10pF. The rise time spec (t )
b
b
r
is characterized with R =R min. The minimum fall time specification (t ) is characterized with C =10pF,and R =R max.
p
p
f
b
p
p
These are only valid for fast mode operation (VDD=4.5-5.5V) and where the SPM bit (SSPSTAT<7>) =1.)
4: Max specifications for these parameters are valid for falling edge only. Specs are characterized with R =R min and
p
p
C =400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.
b
1998-2013 Microchip Technology Inc.
DS30289C-page 259
PIC17C7XX
Param
Sym
No.
Characteristic
100 kHz mode
Min
Max
Units
Conditions
110
Tbuf
Bus free time
4.7
1.3
0.5
—
—
—
ms
ms
ms
pF
Time the bus must be free
before a new transmission
can start
400 kHz mode
(1)
1 MHz mode
—
D102
Cb
Bus capacitive loading
400
2
Note 1: Maximum pin capacitance = 10 pF for all I C pins.
2
2
2: A fast mode (400 KHz) I C bus device can be used in a standard mode I C bus system, but the parameter # 107 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter #102 + #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line is released.
3: C is specified to be from 10-400pF. The minimum specifications are characterized with C =10pF. The rise time spec (t )
b
b
r
is characterized with R =R min. The minimum fall time specification (t ) is characterized with C =10pF,and R =R max.
p
p
f
b
p
p
These are only valid for fast mode operation (VDD=4.5-5.5V) and where the SPM bit (SSPSTAT<7>) =1.)
4: Max specifications for these parameters are valid for falling edge only. Specs are characterized with R =R min and
p
p
C =400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.
b
FIGURE 20-19:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TX/CK
pin
121
121
RX/DT
pin
122
120
TABLE 20-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
—
—
—
—
—
—
—
—
—
—
—
—
50
75
25
40
25
40
ns
ns
ns
ns
ns
ns
121
122
†
TckRF
TdtRF
Clock out rise time and fall time
(Master mode)
Data out rise time and fall time
Data in “Typ” column is at 5V, 25C unless otherwise stated.
DS30289C-page 260
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-20:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TX/CK
pin
125
RX/DT
pin
126
TABLE 20-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Unit
s
Sym
Characteristic
Min
Typ†
Max
Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data setup before CK (DT setup time)
15
15
—
—
—
—
ns
ns
126
TckL2dtl
Data hold after CK (DT hold time)
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
1998-2013 Microchip Technology Inc.
DS30289C-page 261
PIC17C7XX
FIGURE 20-21:
USART ASYNCHRONOUS MODE START BIT DETECT
START bit
RX
(RX/DT pin)
121A
x16 CLK
Q2, Q4 CLK
120A
123A
TABLE 20-16: USART ASYNCHRONOUS MODE START BIT DETECT REQUIREMENTS
Param
No.
Unit
s
Sym
Characteristic
Min
Typ
Max
Conditions
120A
121A
TdtL2ckH
TdtRF
Time to ensure that the RX pin is sampled low
—
—
—
—
—
—
—
—
TCY
(Note 1)
40
ns
ns
ns
ns
Data rise time and fall time
Receive
Transmit
123A
TckH2bckL Time from RX pin sampled low to first rising edge
of x16 clock
TCY
Note 1: Schmitt trigger will determine logic level.
FIGURE 20-22:
USART ASYNCHRONOUS RECEIVE SAMPLING WAVEFORM
START bit
Bit0
RX
(RX/DT pin)
Baud CLK for all but START bit
Baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
126A
1
2
3
125A
Samples
TABLE 20-17: USART ASYNCHRONOUS RECEIVE SAMPLING REQUIREMENTS
Param
No.
Unit
s
Sym
Characteristic
Min
Typ
Max
Conditions
125A
126A
TdtL2ckH
TdtL2ckH
Setup time of RX pin to first data sampled
TCY
TCY
—
—
—
—
ns
ns
Hold time of RX pin from last data sam-
pled
DS30289C-page 262
1998-2013 Microchip Technology Inc.
PIC17C7XX
TABLE 20-18: A/D CONVERTER CHARACTERISTICS
Param.
No.
Sym
Characteristic
Resolution
Min
Typ†
Max
Units
Conditions
A01
NR
—
—
10
bit
VREF+ = VDD = 5.12V,
VSS VAIN VREF+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
bit
(VREF+ — VREF-) 3.0V,
VREF- VAIN VREF+
A02
A03
A04
A05
A06
EABS Absolute error
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
LSb VREF+ = VDD = 5.12V,
VSS VAIN VREF+
LSb (VREF+ — VREF-) 3.0V,
VREF- VAIN VREF+
EIL
EDL
EFS
Integral linearity error
LSb VREF+ = VDD = 5.12V,
VSS VAIN VREF+
LSb (VREF+ — VREF-) 3.0V,
VREF- VAIN VREF+
Differential linearity error
Full scale error
LSb VREF+ = VDD = 5.12V,
VSS VAIN VREF+
LSb (VREF+ — VREF-) 3.0V,
VREF- VAIN VREF+
LSb VREF+ = VDD = 5.12V,
VSS VAIN VREF+
LSb (VREF+ — VREF-) 3.0V,
VREF- VAIN VREF+
EOFF Offset error
LSb VREF+ = VDD = 5.12V,
VSS VAIN VREF+
LSb (VREF+ — VREF-) 3.0V,
VREF- VAIN VREF+
(3)
A10
A20
—
Monotonicity
—
guaranteed
—
—
—
—
V
VSS VAIN VREF
VREF Reference voltage
(VREF+ — VREF-)
0V
VREF delta when changing voltage
levels on VREF inputs
A20A
A21
A22
A25
A30
A40
3V
—
—
—
—
—
—
V
V
Absolute minimum electrical spec.
to ensure 10-bit accuracy
VREF+ Reference voltage high
VREF- Reference voltage low
AVSS
+ 3.0V
AVDD +
0.3V
Avss -
0.3V
AVDD -
3.0V
V
VAIN
ZAIN
IAD
Analog input voltage
AVSS -
0.3V
Vref +
0.3V
V
Recommended impedance of
analog voltage source
—
10.0
k
A/D conversion PIC17CXXX
—
—
10
180
90
—
—
A
A
A
Average current consumption when
A/D is on (Note 1)
current (VDD)
PIC17LCXXX
A50
IREF
VREF input current (Note 2)
—
1000
During VAIN acquisition.
Based on differential of VHOLD to
VAIN
—
—
10
A
During A/D conversion cycle
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RG0 and RG1 pins or AVDD and AVSS pins, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage and has no missing codes.
1998-2013 Microchip Technology Inc.
DS30289C-page 263
PIC17C7XX
FIGURE 20-23:
A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 20-19: A/D CONVERSION REQUIREMENTS
Param.
No.
Sym
Characteristic
PIC17CXXX
Min
Typ†
Max
Units
Conditions
130
TAD
A/D clock period
1.6
3.0
2.0
3.0
11
—
—
—
—
s
s
TOSC based, VREF 3.0V
TOSC based, VREF full range
A/D RC mode
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
4.0
6.0
—
6.0
9.0
12
s
s
A/D RC mode
131
132
TCNV
TACQ
Conversion time
(not including acquisition time) (Note 1)
Tad
Acquisition time
(Note 2)
20
—
—
—
s
s
10
The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
134
TGO
Q4 to ADCLK start
—
Tosc/2
—
—
If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
SLEEPinstruction to be
executed.
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 16.1 for minimum conditions when input voltage has changed more than 1 LSb.
DS30289C-page 264
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 20-24:
MEMORY INTERFACE WRITE TIMING
Q1
Q2
Q3
Q4
Q2
QQ11
OSC1
ALE
OE
151
WR
150
addr out
154
data out
AD<15:0>
addr out
152
153
TABLE 20-20: MEMORY INTERFACE WRITE REQUIREMENTS
Param.
No.
Unit
s
Sym
Characteristic
Min
Typ†
Max
Conditions
150
TadV2alL AD<15:0> (address) valid
to
PIC17CXXX
0.25TCY - 10
—
—
—
—
ns
ALE (address setup
PIC17LCXXX
0.25TCY - 10
time)
151
152
153
154
TalL2adI
ALE to address out invalid PIC17CXXX
0
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
(address hold time)
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
0
TadV2wrL Data out valid to WR
(data setup time)
0.25TCY - 40
—
0.25TCY - 40
—
TwrH2adI WR to data out invalid
(data hold time)
—
—
—
—
0.25TCY
0.25TCY
0.25TCY
0.25TCY
TwrL
WR pulse width
†
Data in “Typ” column is at 5V, 25C unless otherwise stated.
1998-2013 Microchip Technology Inc.
DS30289C-page 265
PIC17C7XX
FIGURE 20-25:
MEMORY INTERFACE READ TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
OE
164
168
160
165
161
Data in
162
AD<15:0>
Addr out
150
Addr out
151
163
167
'1'
'1'
WR
TABLE 20-21: MEMORY INTERFACE READ REQUIREMENTS
Param.
No.
Unit
s
Sym
Characteristic
Min
Typ†
Max
Conditions
150
TadV2alL
AD15:AD0 (address) valid to PIC17CXXX
0.25TCY - 10
—
—
—
—
—
—
—
—
—
—
—
—
ns
ALE (address setup time) PIC17LCXXX 0.25TCY - 10
151
160
TalL2adI
ALE to address out invalid PIC17CXXX
5
5
0
0
ns
ns
(address hold time)
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
TadZ2oeL AD15:AD0 hi-impedance to
OE
161
162
163
ToeH2ad
D
OE to AD15:AD0 driven
PIC17CXXX
0.25TCY - 15
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
PIC17LCXXX 0.25TCY - 15
TadV2oeH Data in valid before OE
(data setup time)
PIC17CXXX
PIC17LCXXX
PIC17CXXX
35
45
0
ToeH2adI OEto data in invalid
(data hold time)
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
0
—
0.25TCY
0.25TCY
—
—
—
—
—
—
—
—
164
165
166
167
168
†
TalH
ALE pulse width
—
ns
ns
ns
ns
ns
—
ToeL
TalH2alH
Tacc
0.5TCY - 35
OE pulse width
0.5TCY - 35
—
ALE to ALE(cycle time)
Address access time
—
—
—
—
—
—
TCY
TCY
—
0.75TCY - 30
0.75TCY - 45
0.5TCY - 45
0.5TCY - 75
—
Toe
Output enable access time
(OE low to data valid)
—
—
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
DS30289C-page 266
1998-2013 Microchip Technology Inc.
PIC17C7XX
21.0 PIC17C7XX DC AND AC CHARACTERISTICS
The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some
graphs or tables the data presented is outside specified operating range (e.g., outside specified VDD range). This is for
information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time.
• Typ or Typical represents the mean of the distribution at 25C.
• Max or Maximum represents (mean + 3) over the temperature range of -40C to 85C.
• Min or Minimum represents (mean - 3) over the temperature range of -40C to 85C.
Note: Standard deviation is denoted by sigma ().
TABLE 21-1: PIN CAPACITANCE PER PACKAGE TYPE
Typical Capacitance (pF)
Pin Name
68-pin PLCC
64-pin TQFP
All pins, except MCLR, VDD, and VSS
MCLR pin
10
20
10
20
FIGURE 21-1:
TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
Fosc
Frequency normalized to +25C
Fosc (25C)
1.10
REXT 10 k
CEXT = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0
10
20
25
30
40
50
60
70
T(C)
1998-2013 Microchip Technology Inc.
DS30289C-page 267
PIC17C7XX
FIGURE 21-2:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
3.0
R = 10k
2.5
2.0
1.5
1.0
0.5
CEXT = 22 pF, T = +25C
R = 100k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
FIGURE 21-3:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
3.0
R = 3.3k
R = 5.1k
2.5
2.0
1.5
1.0
R = 10k
CEXT = 100 pF, T = +25C
0.5
0.0
R = 100k
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
DS30289C-page 268
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-4:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
R = 3.3k
R = 5.1k
R = 10k
0.4
0.2
CEXT = 300 pF, T = +25C
R = 160k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
TABLE 21-2: RC OSCILLATOR FREQUENCIES
Average
FOSC @ 5V, +25C
CEXT
REXT
22 pF
10k
100k
3.3k
5.1k
10k
3.33 MHz
353 kHz
3.54 MHz
2.43 MHz
1.30 MHz
129 kHz
1.54 MHz
980 kHz
564 kHz
35 kHz
12%
13%
10%
14%
17%
10%
14%
12%
16%
18%
100 pF
300 pF
100k
3.3k
5.1k
10k
160k
1998-2013 Microchip Technology Inc.
DS30289C-page 269
PIC17C7XX
FIGURE 21-5:
TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD
500
450
400
350
300
250
200
150
Max @ -40C
Typ @ +25C
Min @ +85C
100
50
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 21-6:
TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
20
18
16
14
12
10
8
Max @ -40C
Typ @ +25C
6
Min @ +85C
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30289C-page 270
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-7:
TYPICAL IDD vs. FOSC OVER VDD (LF MODE)
1.2
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
1.0
0.8
0.6
0.4
0.2
0.0
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FOSC (MHz)
FIGURE 21-8:
MAXIMUM IDD vs. FOSC OVER VDD (LF MODE)
1.2
5.5V
5.0V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
1.0
0.8
0.6
0.4
0.2
0.0
4.5V
4.0V
3.5V
3.0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FOSC (MHz)
1998-2013 Microchip Technology Inc.
DS30289C-page 271
PIC17C7XX
FIGURE 21-9:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
16
14
12
10
8
5.5V
5.0V
Typical:statistical mean @ 25°C
Maximum: mean+3s(-40°Cto125°C)
Minimum: mean –3s (-40°C to 125°C)
4.5V
6
4
4.0V
3.5V
2
3.0V
0
0
5
10
15
20
25
30
35
F
(MHz)
OSC
FIGURE 21-10:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
18
16
14
12
10
8
5.5V
Typical: statistical mean @ 25°C
Maximum:mean+3s(-40°Cto125°C)
Minimum:
mean–3s (-40°C to 125°C)
5.0V
4.5V
6
4
4.0V
3.5V
2
3.0V
0
0
5
10
15
20
25
30
35
FOSC (MHz)
DS30289C-page 272
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-11:
TYPICAL AND MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS
DISABLED, -40C to +125C)
6.0
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
5.0
4.0
3.0
2.0
1.0
0.0
Max
Typ
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 21-12:
TYPICAL AND MAXIMUM IPD vs. VDD (SLEEP MODE, BOR ENABLED, -40C to
+125C)
2.0
1.8
1.6
1.4
1.2
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Max Reset
1.0
0.8
0.6
0.4
0.2
0.0
Typ Reset (25C)
Indeterminate State
Device in Reset
Device in Sleep
Typ Sleep (25C)
Max Sleep
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
1998-2013 Microchip Technology Inc.
DS30289C-page 273
PIC17C7XX
FIGURE 21-13:
TYPICAL AND MAXIMUM IPD vs. VDD (SLEEP MODE, WDT ENABLED, -40C to
+125C)
18
16
14
12
10
8
Max
Typ
6
4
2
0
3.0
3.5
4.0
4.5
5.0
5.5
V
(V)
DD
FIGURE 21-14:
TYPICAL AND MAXIMUM IRBPU vs. VDD (MEASURED PER INPUT PIN,
-40C TO +125C)
300
Typical:statisticalmean@25°C
250
200
150
100
50
Maximum: mean + 3s (-40°C to 125°C)
Minimum:
mean –3s (-40°C to 125°C)
Maximum
Typical (25C)
0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
DS30289C-page 274
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-15:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C)
40
35
30
25
20
15
10
5
Typical: statistical mean @ 25°C
Maximum:mean+3s (-40°C to 125°C)
Minimum: mean –3s (-40°C to 125°C)
Max (125C)
Typ (25C)
Min (-40C)
0
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 21-16:
TYPICAL WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO +125C)
30
25
20
15
10
5
125C
85C
25C
-40C
0
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
1998-2013 Microchip Technology Inc.
DS30289C-page 275
PIC17C7XX
FIGURE 21-17:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
Max
Typ (25C)
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
1.0
0.5
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 21-18:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C)
1 .6
Typical: statistical mean @ 25°C
1 .4
1 .2
1 .0
0 .8
0 .6
0 .4
0 .2
0 .0
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
M a x (1 2 5 C )
T yp (2 5 C )
Min (-40 C )
0
5
1 0
1 5
2 0
2 5
O L
I
(m A)
DS30289C-page 276
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-19:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C)
3.0
2.5
2.0
1.5
1.0
0.5
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Min
Max
Typ (25C)
0.0
0
5
10
15
20
25
IOH (-m A)
FIGURE 21-20:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C)
2.0
1.8
Typical: statisticalmean@25°C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean –3s (-40°C to 125°C)
Max (125C)
Typ (25C)
Min (-40C)
0
5
10
15
20
25
IOL (m A)
1998-2013 Microchip Technology Inc.
DS30289C-page 277
PIC17C7XX
FIGURE 21-21:
TYPICAL, MAXIMUM AND MINIMUM VIN vs. VDD (TTL INPUT, -40C to 125C)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Max
Typ (25C)
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
0.0
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 21-22:
MAXIMUM AND MINIMUM VIN vs. VDD (ST Input, -40 C to +125C)
3.5
Max Ris ing
Min Ris ing
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max Falling
Min Falling
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30289C-page 278
1998-2013 Microchip Technology Inc.
PIC17C7XX
FIGURE 21-23:
MAXIMUM AND MINIMUM VIN vs. VDD (I2C Input, -40C to +125C)
4.0
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max Ris ing
Min Ris ing
Max Falling
Min Falling
3.0
3.5
4.0
4.5
5.0
5.5
V
(V)
DD
1998-2013 Microchip Technology Inc.
DS30289C-page 279
PIC17C7XX
NOTES:
DS30289C-page 280
1998-2013 Microchip Technology Inc.
PIC17C7XX
22.0 PACKAGING INFORMATION
22.1 Package Marking Information
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC17C752
-08I/PT
0017CAE
68-Lead PLCC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC17C756A-08/L
0048CAE
80-Lead TQFP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC17C762
-08I/PT
0017CAE
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
1998-2013 Microchip Technology Inc.
DS30289C-page 281
PIC17C7XX
Package Marking Information (Cont.)
84-Lead PLCC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC17C766-08/L
0048CAE
DS30289C-page 282
1998-2013 Microchip Technology Inc.
PIC17C7XX
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45
A
c
L
A2
A1
(F)
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
NOM
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
64
.020
16
64
0.50
16
Pins per Side
Overall Height
n1
A
A2
A1
L
.039
.043
.039
.006
.024
.039
3.5
.472
.472
.394
.394
.007
.009
.035
10
.047
1.00
1.10
1.00
0.15
0.60
1.00
3.5
12.00
12.00
10.00
10.00
0.18
0.22
0.89
10
1.20
Molded Package Thickness
Standoff
.037
.002
.018
.041
.010
.030
0.95
0.05
0.45
1.05
0.25
0.75
§
Foot Length
(F)
Footprint (Reference)
Foot Angle
Overall Width
0
.463
.463
.390
.390
.005
.007
.025
5
7
.482
.482
.398
.398
.009
.011
.045
15
0
11.75
11.75
9.90
9.90
0.13
0.17
0.64
5
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
E
D
E1
D1
c
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
B
CH
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
1998-2013 Microchip Technology Inc.
DS30289C-page 283
PIC17C7XX
68-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
D1 D
n 1 2
CH2 x 45
CH1 x 45
A3
A2
A
32
c
B1
B
A1
p
D2
E2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
68
MAX
n
p
Number of Pins
Pitch
68
.050
17
1.27
17
Pins per Side
Overall Height
n1
A
.165
.173
.153
.028
.029
.045
.005
.990
.990
.954
.954
.920
.920
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
25.02
25.02
24.13
24.13
22.61
22.61
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
25.15
25.15
24.23
24.23
23.37
23.37
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.145
.020
.024
.040
.000
.985
.985
.950
.950
.890
.890
.008
.026
.013
0
.160
.035
.034
.050
.010
.995
.995
.958
.958
.930
.930
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
25.27
25.27
24.33
24.33
23.62
23.62
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-049
DS30289C-page 284
1998-2013 Microchip Technology Inc.
PIC17C7XX
80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
p
D1
D
2
1
B
c
n
CH x 45
A
A2
L
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
80
MAX
n
p
Number of Pins
Pitch
80
.020
20
.043
.039
.004
.024
.039
3.5
0.50
20
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
Foot Length
Footprint (Reference)
Foot Angle
0
.541
.541
.463
.463
.004
.007
.025
5
7
.561
.561
.482
.482
.008
.011
.045
15
0
13.75
13.75
11.75
11.75
0.09
0.17
0.64
5
7
14.25
14.25
12.25
12.25
0.20
0.27
1.14
15
Overall Width
E
D
E1
D1
c
.551
.551
.472
.472
.006
.009
.035
10
14.00
14.00
12.00
12.00
0.15
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
B
CH
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-092
1998-2013 Microchip Technology Inc.
DS30289C-page 285
PIC17C7XX
84-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
D1 D
n 1 2
CH2 x 45
CH1 x 45
A3
A2
A
32
c
B1
B
A1
p
D2
E2
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
68
MAX
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
68
.050
17
1.27
17
n1
A
.165
.173
.153
.028
.029
.045
.005
.990
.990
.954
.954
.920
.920
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
25.02
25.02
24.13
24.13
22.61
22.61
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
25.15
25.15
24.23
24.23
23.37
23.37
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.145
.020
.024
.040
.000
.985
.985
.950
.950
.890
.890
.008
.026
.013
0
.160
.035
.034
.050
.010
.995
.995
.958
.958
.930
.930
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
25.27
25.27
24.33
24.33
23.62
23.62
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-093
DS30289C-page 286
1998-2013 Microchip Technology Inc.
PIC17C7XX
APPENDIX A: MODIFICATIONS
APPENDIX B: COMPATIBILITY
The following is the list of modifications over the
PIC16CXX microcontroller family:
To convert code written for PIC16CXXX to
PIC17CXXX, the user should take the following steps:
1. Instruction word length is increased to 16-bit.
This allows larger page sizes, both in program
memory (8 Kwords verses 2 Kwords) and regis-
ter file (256 bytes versus 128 bytes).
1. Remove any TRIS and OPTION instructions,
and implement the equivalent code.
2. Separate the Interrupt Service Routine into its
four vectors.
2. Four modes of operation: Microcontroller,
Protected Microcontroller, Extended Micro-
controller, and Microprocessor.
3. Replace:
MOVF
with:
REG1, W
3. 22 new instructions.
MOVFP
REG1, WREG
The MOVF, TRIS and OPTION instructions are
no longer supported.
4. Replace:
MOVF
REG1, W
REG2
4. Four new instructions (TLRD, TLWT, TABLRD,
TABLWT) for transferring data between data
memory and program memory. They can be used
to “self program” the EPROM program memory.
MOVWF
with:
MOVPF
or
REG1, REG2 ; Addr(REG1)<20h
REG1, REG2 ; Addr(REG2)<20h
MOVFP
5. Single cycle data memory to data memory trans-
fers possible (MOVPF and MOVFP instructions).
These instructions do not affect the Working
register (WREG).
Note: If REG1 and REG2 are both at addresses
greater then 20h, two instructions are
required.
6. W register (WREG) is now directly addressable.
MOVFP
MOVPF
REG1, WREG ;
WREG, REG2 ;
7. A PC high latch register (PCLATH) is extended
to 8-bits. The PCLATCH register is now both
readable and writable.
5. Ensure that all bit names and register names are
updated to new data memory map locations.
8. Data memory paging is redefined slightly.
6. Verify data memory banking.
9. DDR registers replace function of TRIS regis-
ters.
7. Verify mode of operation for indirect addressing.
8. Verify peripheral routines for compatibility.
9. Weak pull-ups are enabled on RESET.
10. Multiple Interrupt vectors added. This can
decrease the latency for servicing interrupts.
10. WDT time-outs always reset the device (in run
or SLEEP mode).
11. Stack size is increased to 16 deep.
12. BSR register for data memory paging.
13. Wake-up from SLEEP operates slightly differently.
B.1
Upgrading from PIC17C42 Devices
14. The Oscillator Start-Up Timer (OST) and Power-
Up Timer (PWRT) operate in parallel and not in
series.
To convert code from the PIC17C42 to all the other
PIC17CXXX devices, the user should take the follow-
ing steps.
15. PORTB interrupt-on-change feature works on
all eight port pins.
1. If the hardware multiply is to be used, ensure
that any variables at address 18h and 19h are
moved to another address.
16. TMR0 is 16-bit, plus 8-bit prescaler.
17. Second indirect addressing register added
(FSR1 and FSR2). Control bits can select the
FSR registers to auto-increment, auto-decre-
ment, remain unchanged after an indirect
address.
2. Ensure that the upper nibble of the BSR was not
written with a non-zero value. This may cause
unexpected operation since the RAM bank is no
longer 0.
3. The disabling of global interrupts has been
enhanced, so there is no additional testing of the
GLINTD bit after a BSF CPUSTA, GLINTD
instruction.
18. Hardware multiplier added (8 x 8 16-bit).
19. Peripheral modules operate slightly differently.
20. A/D has both VREF+ and VREF- inputs.
21. USARTs do not implement BRGH feature.
22. Oscillator modes slightly redefined.
23. Control/Status bits and registers have been
placed in different registers and the control bit
for globally enabling interrupts has inverse
polarity.
24. In-circuit serial programming is implemented
differently.
1998-2013 Microchip Technology Inc.
DS30289C-page 287
PIC17C7XX
APPENDIX C: WHAT’S NEW
APPENDIX D: WHAT’S CHANGED
This is a new Data Sheet for the Following Devices:
Clarified the TAD vs. device maximum operating fre-
quency tables in Section 16.2.
• PIC17C752
• PIC17C756A
• PIC17C762
• PIC17C766
Added device characteristic graphs and charts in
Section 21.
Removed the “Preliminary” status from the entire
document.
This Data Sheet is based on the PIC17C75X Data
Sheet (DS30246A).
Revision C (January 2013)
Added a note to each package outline drawing.
DS30289C-page 288
1998-2013 Microchip Technology Inc.
PIC17C7XX
INDEX
A
A/D
B
Bank Select Register (BSR) ............................................... 57
Banking......................................................................... 46, 57
Baud Rate Formula........................................................... 120
Baud Rate Generator ....................................................... 153
Baud Rate Generator (BRG) ............................................ 120
Baud Rates
Asynchronous Mode................................................. 122
Synchronous Mode................................................... 121
BCF .................................................................................. 204
BCLIE ................................................................................. 36
BCLIF ................................................................................. 38
BF ............................................................. 134, 144, 159, 162
Bit Manipulation ................................................................ 198
Block Diagrams
Accuracy/Error .......................................................... 189
ADCON0 Register..................................................... 179
ADCON1 Register..................................................... 180
ADIF bit..................................................................... 181
Analog Input Model Block Diagram........................... 184
Analog-to-Digital Converter....................................... 179
Block Diagram........................................................... 181
Configuring Analog Port Pins.................................... 186
Configuring the Interrupt ........................................... 181
Configuring the Module............................................. 181
Connection Considerations....................................... 189
Conversion Clock...................................................... 185
Conversions.............................................................. 186
Converter Characteristics ......................................... 263
Delays....................................................................... 183
Effects of a RESET................................................... 188
Equations.................................................................. 183
Flow Chart of A/D Operation..................................... 187
GO/DONE bit ............................................................ 181
Internal Sampling Switch (Rss) Impedence.............. 183
Operation During SLEEP.......................................... 188
Sampling Requirements............................................ 183
Sampling Time.......................................................... 183
Source Impedence.................................................... 183
Time Delays.............................................................. 183
Transfer Function...................................................... 189
A/D Interrupt........................................................................ 38
A/D Interrupt Flag bit, ADIF................................................. 38
A/D Module Interrupt Enable, ADIE .................................... 36
ACK................................................................................... 144
Acknowledge Data bit, AKD.............................................. 136
Acknowledge Pulse........................................................... 144
Acknowledge Sequence Enable bit, AKE ......................... 136
Acknowledge Status bit, AKS ........................................... 136
ADCON0 ............................................................................. 49
ADCON1 ............................................................................. 49
ADDLW ............................................................................. 202
ADDWF............................................................................. 202
ADDWFC .......................................................................... 203
ADIE.................................................................................... 36
ADIF.................................................................................... 38
ADRES Register ............................................................... 179
ADRESH ............................................................................. 49
ADRESL.............................................................................. 49
AKD................................................................................... 136
AKE................................................................................... 136
AKS........................................................................... 136, 159
ALU ..................................................................................... 11
ALUSTA............................................................................ 198
ALUSTA Register................................................................ 51
ANDLW ............................................................................. 203
ANDWF............................................................................. 204
Application Note AN552, 'Implementing Wake-up
A/D............................................................................ 181
Analog Input Model................................................... 184
Baud Rate Generator ............................................... 153
BSR Operation ........................................................... 57
External Brown-out Protection Circuit (Case1)........... 31
External Power-on Reset Circuit ................................ 24
External Program Memory Connection ...................... 45
2
I C Master Mode ...................................................... 151
2
I C Module................................................................ 143
Indirect Addressing..................................................... 54
On-chip Reset Circuit ................................................. 23
PORTD....................................................................... 80
PORTE ........................................................... 82, 90, 91
Program Counter Operation ....................................... 56
PWM......................................................................... 107
RA0 and RA1.............................................................. 72
RA2............................................................................. 72
RA3............................................................................. 73
RA4 and RA5.............................................................. 73
RB3:RB2 Port Pins..................................................... 75
RB7:RB4 and RB1:RB0 Port Pins.............................. 74
RC7:RC0 Port Pins..................................................... 78
2
SSP (I C Mode)........................................................ 143
SSP (SPI Mode) ....................................................... 137
2
SSP Module (I C Master Mode)............................... 133
2
SSP Module (I C Slave Mode)................................. 133
SSP Module (SPI Mode) .......................................... 133
Timer3 with One Capture and One Period Register. 110
TMR1 and TMR2 in 16-bit Timer/Counter Mode ...... 105
TMR1 and TMR2 in Two 8-bit Timer/Counter Mode 104
TMR3 with Two Capture Registers........................... 112
Using CALL, GOTO.................................................... 56
WDT ......................................................................... 193
BODEN............................................................................... 31
Borrow ................................................................................ 11
BRG.......................................................................... 120, 153
Brown-out Protection .......................................................... 31
Brown-out Reset (BOR)...................................................... 31
BSF................................................................................... 205
BSR .................................................................................... 57
BSR Operation ................................................................... 57
BTFSC.............................................................................. 205
BTFSS .............................................................................. 206
BTG .................................................................................. 206
Buffer Full bit, BF.............................................................. 144
Buffer Full Status bit, BF................................................... 134
Bus Arbitration .................................................................. 170
Bus Collision
on Keystroke.' ..................................................................... 74
Application Note AN578, "Use of the SSP Module
in the I C Multi-Master Environment."............................... 143
2
Assembler
MPASM Assembler................................................... 233
Asynchronous Master Transmission................................. 123
Asynchronous Transmitter ................................................ 123
Section...................................................................... 170
1998-2013 Microchip Technology Inc.
DS30289C-page 289
PIC17C7XX
Bus Collision During a RESTART Condition.....................173
Bus Collision During a START Condition..........................171
Bus Collision During a STOP Condition............................174
Bus Collision Interrupt Enable, BCLIE ................................36
Bus Collision Interrupt Flag bit, BCLIF................................38
C
Configuration
Bits............................................................................ 192
Locations .................................................................. 192
Oscillator............................................................. 17, 192
Word ......................................................................... 191
CPFSEQ........................................................................... 209
CPFSGT ........................................................................... 209
CPFSLT............................................................................ 210
CPUSTA ..................................................................... 52, 194
Crystal Operation, Overtone Crystals................................. 18
Crystal or Ceramic Resonator Operation............................ 18
Crystal Oscillator................................................................. 17
D
C.................................................................................... 11, 51
CA1/PR3 ...........................................................................102
CA1ED0 ............................................................................101
CA1ED1 ............................................................................101
CA1IE..................................................................................35
CA1IF..................................................................................37
CA1OVF............................................................................102
CA2ED0 ............................................................................101
CA2ED1 ............................................................................101
CA2H............................................................................. 28, 49
CA2IE.......................................................................... 35, 111
CA2IF.......................................................................... 37, 111
CA2L ............................................................................. 28, 49
CA2OVF............................................................................102
CA3H...................................................................................50
CA3IE..................................................................................36
CA3IF..................................................................................38
CA3L ...................................................................................50
CA4H...................................................................................50
CA4IE..................................................................................36
CA4IF..................................................................................38
Calculating Baud Rate Error .............................................120
CALL ........................................................................... 54, 207
Capacitor Selection
D/A.................................................................................... 134
Data Memory
GPR...................................................................... 43, 46
Indirect Addressing..................................................... 54
Organization ............................................................... 46
SFR ............................................................................ 43
Data Memory Banking ........................................................ 46
Data/Address bit, D/A ....................................................... 134
DAW ................................................................................. 210
DC................................................................................. 11, 51
DDRB...................................................................... 27, 48, 74
DDRC ..................................................................... 28, 48, 78
DDRD ..................................................................... 28, 48, 80
DDRE...................................................................... 28, 48, 82
DDRF.................................................................................. 49
DDRG ................................................................................. 49
DECF................................................................................ 211
DECFSNZ......................................................................... 212
DECFSZ ........................................................................... 211
Delay From External Clock Edge........................................ 98
Digit Borrow ........................................................................ 11
Digit Carry (DC) .................................................................. 11
Duty Cycle ........................................................................ 107
E
Ceramic Resonators ...................................................18
Crystal Oscillator.........................................................18
Capture ..................................................................... 101, 110
Capture Sequence to Read Example................................113
Capture1
Mode .........................................................................101
Overflow............................................................102, 103
Capture1 Interrupt...............................................................37
Capture2
Electrical Characteristics
PIC17C752/756
Mode .........................................................................101
Overflow............................................................102, 103
Capture2 Interrupt...............................................................37
Capture3 Interrupt Enable, CA3IE ......................................36
Capture3 Interrupt Flag bit, CA3IF......................................38
Capture4 Interrupt Enable, CA4IE ......................................36
Capture4 Interrupt Flag bit, CA4IF......................................38
Carry (C) .............................................................................11
Ceramic Resonators ...........................................................17
Circular Buffer .....................................................................54
CKE...................................................................................134
CKP...................................................................................135
Clearing the Prescaler.......................................................193
Clock Polarity Select bit, CKP...........................................135
Clock/Instruction Cycle (Figure)..........................................21
Clocking Scheme/Instruction Cycle.....................................21
CLRF.................................................................................207
CLRWDT...........................................................................208
Code Examples
Absolute Maximum Ratings.............................. 239
Capture Timing................................................. 253
CLKOUT and I/O Timing .................................. 250
DC Characteristics............................................ 242
External Clock Timing....................................... 249
Memory Interface Read Timing ........................ 266
Memory Interface Write Timing ........................ 265
Parameter Measurement Information............... 248
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing................... 251
Timer0 Clock Timing......................................... 252
Timer1, Timer2 and Timer3 Clock Timing ........ 252
Timing Parameter Symbology .......................... 247
USART Module Synchronous Receive Timing. 261
USART Module Synchronous Transmission
Timing............................................................... 260
EPROM Memory Access Time Order Suffix....................... 45
Errata.................................................................................... 5
Extended Microcontroller.................................................... 43
Extended Microcontroller Mode.......................................... 45
External Memory Interface.................................................. 45
External Program Memory Waveforms............................... 45
Indirect Addressing .....................................................55
Loading the SSPBUF register...................................138
Saving Status and WREG in RAM..............................42
Table Read .................................................................64
Table Write..................................................................62
Code Protection ................................................................195
COMF................................................................................208
DS30289C-page 290
1998-2013 Microchip Technology Inc.
PIC17C7XX
Bus Collision............................................................. 170
Acknowledge .................................................... 170
RESTART Condition......................................... 173
RESTART Condition Timing (Case1)............... 173
RESTART Condition Timing (Case2)............... 173
START Condition.............................................. 171
START Condition Timing.......................... 171, 172
STOP Condition................................................ 174
STOP Condition Timing (Case1)...................... 174
STOP Condition Timing (Case2)...................... 174
Transmit Timing................................................ 170
Bus Collision Timing................................................. 170
Clock Arbitration ....................................................... 169
Clock Arbitration Timing (Master Transmit).............. 169
Conditions to not give ACK Pulse............................. 144
General Call Address Support.................................. 149
Master Mode............................................................. 151
Master Mode 7-bit Reception timing......................... 164
Master Mode Operation............................................ 152
Master Mode Start Condition.................................... 154
Master Mode Transmission ...................................... 159
Master Mode Transmit Sequence ............................ 152
Master Transmit Flowchart....................................... 160
Multi-Master Communication.................................... 170
Multi-master Mode.................................................... 152
Operation.................................................................. 143
Repeat Start Condition timing................................... 156
RESTART Condition Flowchart................................ 157
Slave Mode............................................................... 144
Slave Reception ....................................................... 145
Slave Transmission .................................................. 146
SSPBUF ................................................................... 144
Start Condition Flowchart ......................................... 155
Stop Condition Flowchart ......................................... 168
Stop Condition Receive or Transmit timing .............. 167
Stop Condition timing ............................................... 167
Waveforms for 7-bit Reception................................. 146
Waveforms for 7-bit Transmission............................ 146
F
Family of Devices
PIC17C75X................................................................... 8
FERR ................................................................................ 125
Flowcharts
Acknowledge............................................................. 166
Master Receiver........................................................ 163
Master Transmit........................................................ 160
RESTART Condition................................................. 157
Start Condition .......................................................... 155
STOP Condition........................................................ 168
FOSC0 .............................................................................. 191
FOSC1 .............................................................................. 191
FS0 ..................................................................................... 51
FS1 ..................................................................................... 51
FS2 ..................................................................................... 51
FS3 ..................................................................................... 51
FSR0................................................................................... 54
FSR1................................................................................... 54
G
GCE .................................................................................. 136
General Call Address Sequence....................................... 149
General Call Address Support .......................................... 149
General Call Enable bit, GCE ........................................... 136
General Format for Instructions ........................................ 198
General Purpose RAM........................................................ 43
General Purpose RAM Bank............................................... 57
General Purpose Register (GPR) ....................................... 46
GLINTD......................................................... 39, 52, 111, 194
Global Interrupt Disable bit, GLINTD .................................. 39
GOTO ............................................................................... 212
GPR (General Purpose Register) ....................................... 46
GPR Banks ......................................................................... 57
Graphs
RC Oscillator Frequency vs. VDD (CEXT = 100 pF)... 268
RC Oscillator Frequency vs. VDD (CEXT = 22 pF)..... 268
RC Oscillator Frequency vs. VDD (CEXT = 300 pF)... 269
Transconductance of LF Oscillator vs.VDD ............... 270
Transconductance of XT Oscillator vs. VDD.............. 270
Typical RC Oscillator vs. Temperature ..................... 267
H
Hardware Multiplier ............................................................. 67
I
I/O Ports
2
I C Module Address Register, SSPADD .......................... 144
I C Slave Mode ................................................................ 144
2
INCF ................................................................................. 213
INCFSNZ .......................................................................... 214
INCFSZ............................................................................. 213
In-Circuit Serial Programming........................................... 196
INDF0 ................................................................................. 54
INDF1 ................................................................................. 54
Indirect Addressing
Indirect Addressing..................................................... 54
Operation.................................................................... 55
Registers .................................................................... 54
Initializing PORTB............................................................... 75
Initializing PORTC .............................................................. 78
Initializing PORTD .............................................................. 80
Initializing PORTE................................................... 82, 84, 86
INSTA................................................................................. 48
Instruction Flow/Pipelining.................................................. 21
Instruction Set
Bi-directional ............................................................... 93
I/O Ports...................................................................... 71
Programming Considerations ..................................... 93
Read-Modify-Write Instructions................................... 93
Successive Operations ............................................... 94
2
I C..................................................................................... 143
I2C Input ........................................................................... 279
2
I C Master Mode Receiver Flow Chart ............................. 163
2
I C Master Mode Reception.............................................. 162
2
I C Master Mode RESTART Condition............................. 156
2
I C Mode Selection ........................................................... 143
2
I C Module
Acknowledge Flow Chart .......................................... 166
Acknowledge Sequence Timing................................ 165
Addressing................................................................ 145
Baud Rate Generator................................................ 153
Block Diagram........................................................... 151
BRG Block Diagram.................................................. 153
BRG Reset due to SDA Collision.............................. 172
BRG Timing .............................................................. 153
Bus Arbitration .......................................................... 170
ADDLW..................................................................... 202
ADDWF .................................................................... 202
ADDWFC.................................................................. 203
ANDLW..................................................................... 203
ANDWF .................................................................... 204
BCF .......................................................................... 204
BSF........................................................................... 205
BTFSC...................................................................... 205
BTFSS...................................................................... 206
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BTG...........................................................................206
CALL .........................................................................207
CLRF.........................................................................207
CLRWDT...................................................................208
COMF .......................................................................208
CPFSEQ ...................................................................209
CPFSGT ...................................................................209
CPFSLT ....................................................................210
DAW..........................................................................210
DECF ........................................................................211
DECFSNZ.................................................................212
DECFSZ....................................................................211
GOTO .......................................................................212
INCF..........................................................................213
INCFSNZ ..................................................................214
INCFSZ.....................................................................213
IORLW ......................................................................214
IORWF ......................................................................215
LCALL .......................................................................215
MOVFP .....................................................................216
MOVLB .....................................................................216
MOVLR .....................................................................217
MOVLW ....................................................................217
MOVPF .....................................................................218
MOVWF ....................................................................218
MULLW .....................................................................219
MULWF.....................................................................219
NEGW.......................................................................220
NOP ..........................................................................220
RETFIE .....................................................................221
RETLW .....................................................................221
RETURN ...................................................................222
RLCF.........................................................................222
RLNCF ......................................................................223
RRCF ........................................................................223
RRNCF .....................................................................224
SETF.........................................................................224
SLEEP ......................................................................225
SUBLW .....................................................................225
SUBWF.....................................................................226
SUBWFB...................................................................226
SWAPF .....................................................................227
TABLRD............................................................227, 228
TABLWT ........................................................... 228, 229
TLRD.........................................................................229
TLWT ........................................................................230
TSTFSZ ....................................................................230
XORLW.....................................................................231
XORWF.....................................................................231
Instruction Set Summary...................................................197
Instructions
Capture4 Interrupt ...................................................... 38
Context Saving ........................................................... 39
Flag bits
TMR1IE .............................................................. 33
TMR1IF............................................................... 33
TMR2IE .............................................................. 33
TMR2IF............................................................... 33
TMR3IE .............................................................. 33
TMR3IF............................................................... 33
Global Interrupt Disable.............................................. 39
Interrupts .................................................................... 33
Logic........................................................................... 33
Operation.................................................................... 39
Peripheral Interrupt Enable......................................... 35
Peripheral Interrupt Request....................................... 37
PIE2 Register ............................................................. 36
PIR1 Register ............................................................. 37
PIR2 Register ............................................................. 38
PORTB Interrupt on Change ...................................... 37
PWM......................................................................... 108
RA0/INT...................................................................... 39
Status Register ........................................................... 34
Synchronous Serial Port Interrupt............................... 38
T0CKI Interrupt ........................................................... 39
Timing......................................................................... 40
TMR1 Overflow Interrupt ............................................ 37
TMR2 Overflow Interrupt ............................................ 37
TMR3 Overflow Interrupt ............................................ 37
USART1 Receive Interrupt ......................................... 37
USART1 Transmit Interrupt ........................................ 37
USART2 Receive Interrupt ......................................... 38
Vectors
Peripheral Interrupt............................................. 39
Program Memory Locations ............................... 43
RA0/INT Interrupt ............................................... 39
T0CKI Interrupt................................................... 39
Vectors/Priorities......................................................... 39
Wake-up from SLEEP............................................... 194
INTF.................................................................................... 34
INTSTA Register................................................................. 34
IORLW.............................................................................. 214
IORWF.............................................................................. 215
IRBPU VS. VDD ................................................................... 274
K
KeeLoq Evaluation and Programming Tools .................... 236
L
LCALL......................................................................... 54, 215
M
Maps
Register File Map........................................................ 47
Memory
TABLRD......................................................................64
TLRD...........................................................................64
INT Pin ................................................................................40
INTE....................................................................................34
INTEDG......................................................................... 53, 97
External Interface ....................................................... 45
External Memory Waveforms ..................................... 45
Memory Map (Different Modes).................................. 44
Mode Memory Access................................................ 44
Organization ............................................................... 43
Program Memory........................................................ 43
Program Memory Map................................................ 43
Microcontroller .................................................................... 43
Microprocessor ................................................................... 43
Minimizing Current Consumption...................................... 195
MOVFP....................................................................... 46, 216
Moving Data Between Data and Program Memories ......... 46
MOVLB ....................................................................... 46, 216
MOVLR............................................................................. 217
MOVLW ............................................................................ 217
2
Inter-Integrated Circuit (I C)..............................................133
Internal Sampling Switch (Rss) Impedence ......................183
Interrupt on Change Feature...............................................74
Interrupt Status Register (INTSTA).....................................34
Interrupts
A/D Interrupt................................................................38
Bus Collision Interrupt.................................................38
Capture1 Interrupt.......................................................37
Capture2 Interrupt.......................................................37
Capture3 Interrupt.......................................................38
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PIC17C7XX
MOVPF ....................................................................... 46, 218
MOVWF ............................................................................ 218
MPLAB Integrated Development Environment Software .. 233
MULLW ............................................................................. 219
Multi-Master Communication ............................................ 170
Multi-Master Mode ............................................................ 152
Multiply Examples
16 x 16 Routine........................................................... 68
16 x 16 Signed Routine............................................... 69
8 x 8 Routine............................................................... 67
8 x 8 Signed Routine................................................... 67
MULWF............................................................................. 219
N
NEGW............................................................................... 220
NOP .................................................................................. 220
O
Opcode Field Descriptions................................................ 197
Opcodes.............................................................................. 56
Oscillator
Configuration....................................................... 17, 192
Crystal......................................................................... 17
External Clock............................................................. 19
External Crystal Circuit ............................................... 19
External Parallel Resonant Crystal Circuit.................. 19
External Series Resonant Crystal Circuit.................... 19
RC............................................................................... 20
RC Frequencies........................................................ 269
Oscillator Start-up Time (Figure)......................................... 24
Oscillator Start-up Timer (OST) .......................................... 24
OST..................................................................................... 24
OV................................................................................. 11, 51
Overflow (OV) ..................................................................... 11
P
P........................................................................................ 134
Packaging Information ...................................................... 281
PC (Program Counter)........................................................ 56
PCFG0 bit ......................................................................... 180
PCFG1 bit ......................................................................... 180
PCFG2 bit ......................................................................... 180
PCH .................................................................................... 56
PCL ............................................................................. 56, 198
PCLATH.............................................................................. 56
PD ............................................................................... 52, 194
PEIE............................................................................ 34, 111
PEIF.................................................................................... 34
Peripheral Bank .................................................................. 57
Peripheral Banks................................................................. 57
Peripheral Interrupt Enable ................................................. 35
Peripheral Interrupt Request (PIR1) ................................... 37
Peripheral Register Banks .................................................. 46
PICDEM-1 Low-Cost PICmicro Demo Board.................... 235
PICDEM-2 Low-Cost PIC16CXX Demo Board ................. 235
PICDEM-3 Low-Cost PIC16CXXX Demo Board............... 236
PICSTART“ Plus Entry Level Development System......... 235
PIE .................................................................... 126, 130, 132
PIE1 .............................................................................. 28, 48
PIE2 ........................................................................ 28, 36, 49
PIR.................................................................... 126, 130, 132
PIR1.............................................................................. 28, 48
PIR2.............................................................................. 28, 49
PM0........................................................................... 191, 195
PM1........................................................................... 191, 195
POP .............................................................................. 39, 54
POR .................................................................................... 24
PORTA.................................................................... 27, 48, 72
PORTB ................................................................... 27, 48, 74
PORTB Interrupt on Change .............................................. 37
PORTC ................................................................... 28, 48, 78
PORTD ................................................................... 28, 48, 80
PORTE ................................................................... 28, 48, 82
PORTF ............................................................................... 49
PORTG............................................................................... 49
Power-down Mode............................................................ 194
Power-on Reset (POR)....................................................... 24
Power-up Timer (PWRT).................................................... 24
PR1............................................................................... 28, 49
PR2............................................................................... 28, 49
PR3/CA1H .......................................................................... 28
PR3/CA1L........................................................................... 28
PR3H/CA1H........................................................................ 49
PR3L/CA1L......................................................................... 49
Prescaler Assignments....................................................... 99
PRO MATE“ II Universal Programmer.............................. 235
PRODH......................................................................... 30, 50
PRODL ......................................................................... 30, 50
Program Counter (PC)........................................................ 56
Program Memory
External Access Waveforms....................................... 45
External Connection Diagram..................................... 45
Map............................................................................. 43
Modes
Extended Microcontroller.................................... 43
Microcontroller.................................................... 43
Microprocessor................................................... 43
Protected Microcontroller.................................... 43
Operation.................................................................... 43
Organization ............................................................... 43
Protected Microcontroller.................................................... 43
PS0............................................................................... 53, 97
PS1............................................................................... 53, 97
PS2............................................................................... 53, 97
PS3............................................................................... 53, 97
PUSH............................................................................ 39, 54
PW1DCH ...................................................................... 28, 49
PW1DCL....................................................................... 28, 49
PW2DCH ...................................................................... 28, 49
PW2DCL....................................................................... 28, 49
PW3DCH ...................................................................... 30, 50
PW3DCL....................................................................... 30, 50
PWM......................................................................... 101, 107
Duty Cycle ................................................................ 108
External Clock Source.............................................. 109
Frequency vs. Resolution......................................... 108
Interrupts .................................................................. 108
Max Resolution/Frequency for External Clock Input 109
Output....................................................................... 107
Periods ..................................................................... 108
PWM1....................................................................... 102, 103
PWM1ON.................................................................. 102, 107
PWM2....................................................................... 102, 103
PWM2ON.................................................................. 102, 107
PWM3ON.......................................................................... 103
PWRT ................................................................................. 24
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PIC17C7XX
PR1............................................................................. 49
PR2............................................................................. 49
PR3H/CA1H................................................................ 49
PR3L/CA1L................................................................. 49
PRODH....................................................................... 50
PRODL ....................................................................... 50
PW1DCH .................................................................... 49
PW1DCL..................................................................... 49
PW2/DCL.................................................................... 49
PW2DCH .................................................................... 49
PW3DCH .................................................................... 50
PW3DCL..................................................................... 50
RCREG1..................................................................... 48
RCREG2..................................................................... 49
RCSTA1 ..................................................................... 48
RCSTA2 ..................................................................... 49
SPBRG1 ..................................................................... 48
SPBRG2 ..................................................................... 49
SSPADD..................................................................... 50
SSPBUF ..................................................................... 50
SSPCON1 .................................................................. 50
SSPCON2 .................................................................. 50
SSPSTAT ........................................................... 50, 134
T0STA ............................................................ 48, 53, 97
TBLPTRH ................................................................... 48
TBLPTRL.................................................................... 48
TCON1 ............................................................... 49, 101
TCON2 ............................................................... 49, 102
TCON3 ............................................................... 50, 103
TMR0H ....................................................................... 48
TMR1.......................................................................... 49
TMR2.......................................................................... 49
TMR3H ....................................................................... 49
TMR3L........................................................................ 49
TXREG1 ..................................................................... 48
TXREG2 ..................................................................... 49
TXSTA1 ...................................................................... 48
TXSTA2 ...................................................................... 49
WREG .................................................................. 39, 48
R
R/W ...................................................................................134
R/W bit ..............................................................................145
R/W bit ..............................................................................145
RA1/T0CKI pin ....................................................................97
RBIE....................................................................................35
RBIF....................................................................................37
RBPU ..................................................................................74
RC Oscillator.......................................................................20
RC Oscillator Frequencies ................................................269
RC1IE..................................................................................35
RC1IF..................................................................................37
RC2IE..................................................................................36
RC2IF..................................................................................38
RCE, Receive Enable bit, RCE.........................................136
RCREG .....................................................125, 126, 130, 131
RCREG1 ....................................................................... 27, 48
RCREG2 ....................................................................... 27, 49
RCSTA..............................................................126, 130, 132
RCSTA1........................................................................ 27, 48
RCSTA2........................................................................ 27, 49
Read/Write bit, R/W ..........................................................134
Reading 16-bit Value...........................................................99
Receive Overflow Indicator bit, SSPOV............................135
Receive Status and Control Register................................117
Register File Map................................................................47
Registers
ADCON0 .....................................................................49
ADCON1 .....................................................................49
ADRESH .....................................................................49
ADRESL......................................................................49
ALUSTA..........................................................39, 48, 51
BRG ..........................................................................120
BSR....................................................................... 39, 48
CA2H ..........................................................................49
CA2L ...........................................................................49
CA3H ..........................................................................50
CA3L ...........................................................................50
CA4H ..........................................................................50
CA4L ...........................................................................50
CPUSTA ............................................................... 48, 52
DDRB..........................................................................48
DDRC..........................................................................48
DDRD..........................................................................48
DDRE..........................................................................48
DDRF ..........................................................................49
DDRG .........................................................................49
FSR0..................................................................... 48, 54
FSR1..................................................................... 48, 54
INDF0....................................................................48, 54
INDF1....................................................................48, 54
INSTA .........................................................................48
INTSTA .......................................................................34
PCL .............................................................................48
PCLATH......................................................................48
PIE1 ...................................................................... 35, 48
PIE2 ...................................................................... 36, 49
PIR1...................................................................... 37, 48
PIR2...................................................................... 38, 49
PORTA........................................................................48
PORTB........................................................................48
PORTC .......................................................................48
PORTD .......................................................................48
PORTE........................................................................48
PORTF........................................................................49
PORTG .......................................................................49
Regsters
TMR0L........................................................................ 48
Reset
Section........................................................................ 23
Status Bits and Their Significance.............................. 25
Time-Out in Various Situations................................... 25
Time-Out Sequence.................................................... 25
Restart Condition Enabled bit, RSE.................................. 136
RETFIE............................................................................. 221
RETLW ............................................................................. 221
RETURN........................................................................... 222
RLCF ................................................................................ 222
RLNCF.............................................................................. 223
RRCF................................................................................ 223
RRNCF ............................................................................. 224
RSE .................................................................................. 136
RX Pin Sampling Scheme ................................................ 125
S
S ....................................................................................... 134
SAE................................................................................... 136
Sampling........................................................................... 125
Saving STATUS and WREG in RAM.................................. 42
SCK .................................................................................. 137
SCL................................................................................... 144
SDA .................................................................................. 144
SDI.................................................................................... 137
SDO.................................................................................. 137
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PIC17C7XX
SEEVAL Evaluation and Programming System................ 236
Serial Clock, SCK ............................................................. 137
Serial Clock, SCL.............................................................. 144
Serial Data Address, SDA................................................. 144
Serial Data In, SDI ............................................................ 137
Serial Data Out, SDO........................................................ 137
SETF................................................................................. 224
SFR................................................................................... 198
SFR (Special Function Registers)....................................... 43
SFR As Source/Destination .............................................. 198
Signed Math........................................................................ 11
Slave Select Synchronization ........................................... 140
Slave Select, SS ............................................................... 137
SLEEP ...................................................................... 194, 225
SLEEP Mode, All Peripherals Disabled ............................ 273
SLEEP Mode, BOR Enabled ............................................ 273
SMP .................................................................................. 134
Software Simulator (MPLAB SIM)..................................... 234
SPBRG ............................................................. 126, 130, 132
SPBRG1 ....................................................................... 27, 48
SPBRG2 ....................................................................... 27, 49
SPE................................................................................... 136
Special Features of the CPU ............................................ 191
Special Function Registers ......................................... 43, 198
Summary..................................................................... 48
Special Function Registers, File Map ................................. 47
SPI
SSPIE................................................................................. 36
SSPIF ......................................................................... 38, 145
SSPM3:SSPM0 ................................................................ 135
SSPOV ............................................................. 135, 144, 162
SSPSTAT ........................................................... 50, 134, 144
ST Input ............................................................................ 278
Stack
Operation.................................................................... 54
Pointer ........................................................................ 54
Stack........................................................................... 43
START bit (S) ................................................................... 134
START Condition Enabled bit, SAE.................................. 136
STKAV.......................................................................... 52, 54
STOP bit (P) ..................................................................... 134
STOP Condition Enable bit............................................... 136
SUBLW............................................................................. 225
SUBWF............................................................................. 226
SUBWFB .......................................................................... 226
SWAPF............................................................................. 227
Synchronous Master Mode............................................... 127
Synchronous Master Reception........................................ 129
Synchronous Master Transmission .................................. 127
Synchronous Serial Port................................................... 133
Synchronous Serial Port Enable bit, SSPEN.................... 135
Synchronous Serial Port Interrupt....................................... 38
Synchronous Serial Port Interrupt Enable, SSPIE.............. 36
Synchronous Serial Port Mode Select bits,
Master Mode............................................................. 139
Serial Clock............................................................... 137
Serial Data In ............................................................ 137
Serial Data Out ......................................................... 137
Serial Peripheral Interface (SPI) ............................... 133
Slave Select.............................................................. 137
SPI clock................................................................... 139
SPI Mode .................................................................. 137
SPI Clock Edge Select, CKE ............................................ 134
SPI Data Input Sample Phase Select, SMP ..................... 134
SPI Master/Slave Connection ........................................... 138
SPI Module
SSPM3:SSPM0 ................................................................ 135
Synchronous Slave Mode................................................. 131
T
T0CKI ................................................................................. 39
T0CKI Pin ........................................................................... 40
T0CKIE............................................................................... 34
T0CKIF ............................................................................... 34
T0CS ............................................................................ 53, 97
T0IE .................................................................................... 34
T0IF .................................................................................... 34
T0SE............................................................................. 53, 97
T0STA ................................................................................ 53
T16 ................................................................................... 101
Table Latch......................................................................... 55
Table Pointer ...................................................................... 55
Table Read
Master/Slave Connection.......................................... 138
Slave Mode............................................................... 140
Slave Select Synchronization ................................... 140
Slave Synch Timing .................................................. 140
SS ..................................................................................... 137
SSP................................................................................... 133
Block Diagram (SPI Mode) ....................................... 137
SPI Mode .................................................................. 137
SSPADD ........................................................... 144, 145
SSPBUF............................................................ 139, 144
SSPCON1................................................................. 135
SSPCON2................................................................. 136
SSPSR.............................................................. 139, 144
SSPSTAT.......................................................... 134, 144
Example...................................................................... 64
Table Reads Section .................................................. 64
TLRD .......................................................................... 64
Table Write
Code........................................................................... 62
Timing......................................................................... 62
To External Memory ................................................... 62
TABLRD ................................................................... 227, 228
TABLWT ................................................................... 228, 229
TAD ................................................................................... 185
TBLATH.............................................................................. 55
TBLATL .............................................................................. 55
TBLPTRH ........................................................................... 55
TBLPTRL............................................................................ 55
TCLK12 ............................................................................ 101
TCLK3 .............................................................................. 101
TCON1 ......................................................................... 28, 49
TCON2 ............................................................................... 49
TCON2,TCON3 .................................................................. 28
TCON3 ....................................................................... 50, 103
Time-Out Sequence............................................................ 25
Timer Resources ................................................................ 95
2
SSP I C
2
SSP I C Operation.................................................... 143
SSP Module
SPI Master Mode ...................................................... 139
SPI Master/Slave Connection................................... 138
SPI Slave Mode ........................................................ 140
SSPCON1 Register .................................................. 143
SSP Overflow Detect bit, SSPOV..................................... 144
SSPADD ............................................................................. 50
SSPBUF...................................................................... 50, 144
SSPCON1........................................................... 50, 135, 143
SSPCON2................................................................... 50, 136
SSPEN.............................................................................. 135
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PIC17C7XX
Timer0.................................................................................97
Timer1
TMR0.................................................................... 98, 99
TMR0 Read/Write in Timer Mode............................. 100
TMR1, TMR2, and TMR3 in Timer Mode ................. 115
Wake-Up from SLEEP.............................................. 194
TLRD ................................................................................ 229
TLWT................................................................................ 230
TMR0
16-bit Mode...............................................................105
Clock Source Select..................................................101
On bit ................................................................102, 103
Section ..............................................................101, 104
Timer2
16-bit Mode...............................................................105
Clock Source Select..................................................101
On bit ................................................................102, 103
Section ..............................................................101, 104
Timer3
Clock Source Select..................................................101
On bit ................................................................102, 103
Section ..............................................................101, 110
Timers
16-bit Read ................................................................. 99
16-bit Write ................................................................. 99
Module........................................................................ 98
Operation.................................................................... 98
Overview..................................................................... 95
Prescaler Assignments............................................... 99
Read/Write Considerations......................................... 99
Read/Write in Timer Mode........................................ 100
Timing................................................................... 98, 99
TMR0 Status/Control Register (T0STA) ............................. 53
TMR1............................................................................ 28, 49
8-bit Mode................................................................. 104
External Clock Input.................................................. 104
Overview..................................................................... 95
Timer Mode............................................................... 115
Two 8-bit Timer/Counter Mode................................. 104
Using with PWM ....................................................... 107
TMR1 Overflow Interrupt .................................................... 37
TMR1CS........................................................................... 101
TMR1IE............................................................................... 35
TMR1IF............................................................................... 37
TMR1ON........................................................................... 102
TMR2............................................................................ 28, 49
8-bit Mode................................................................. 104
External Clock Input.................................................. 104
In Timer Mode........................................................... 115
Two 8-bit Timer/Counter Mode................................. 104
Using with PWM ....................................................... 107
TMR2 Overflow Interrupt .................................................... 37
TMR2CS........................................................................... 101
TMR2IE............................................................................... 35
TMR2IF............................................................................... 37
TMR2ON........................................................................... 102
TMR3
Example, Reading From........................................... 114
Example, Writing To ................................................. 114
External Clock Input.................................................. 114
In Timer Mode........................................................... 115
One Capture and One Period Register Mode........... 110
Overview..................................................................... 95
Reading/Writing ........................................................ 114
TMR3 Interrupt Flag bit, TMR3IF........................................ 37
TMR3CS................................................................... 101, 110
TMR3H ......................................................................... 28, 49
TMR3IE............................................................................... 35
TMR3IF....................................................................... 37, 110
TMR3L.......................................................................... 28, 49
TMR3ON................................................................... 102, 110
TO....................................................................... 52, 193, 194
Transmit Status and Control Register............................... 117
TSTFSZ ............................................................................ 230
TTL INPUT........................................................................ 278
Turning on 16-bit Timer .................................................... 105
TX1IE.................................................................................. 35
TX1IF.................................................................................. 37
TX2IE.................................................................................. 36
TX2IF.................................................................................. 38
TXREG ..................................................... 123, 127, 131, 132
TXREG1 ....................................................................... 27, 48
TCON3......................................................................103
Timing Diagrams
A/D Conversion.........................................................264
Acknowledge Sequence Timing................................165
Asynchronous Master Transmission.........................123
Asynchronous Reception ..........................................126
Back to Back Asynchronous Master Transmission...124
Baud Rate Generator with Clock Arbitration .............153
BRG Reset Due to SDA Collision .............................172
Bus Collision
START Condition Timing ..................................171
Bus Collision During a RESTART Condition
(Case 1) ....................................................................173
Bus Collision During a RESTART Condition
(Case 2) ....................................................................173
Bus Collision During a START Condition
(SCL = 0)...................................................................172
Bus Collision During a
STOP Condition ........................................................174
Bus Collision for Transmit and Acknowledge............170
External Parallel Resonant Crystal Oscillator Circuit ..19
External Program Memory Access .............................45
2
I C Bus Data.............................................................259
2
I C Bus START/STOP bits .......................................258
2
I C Master Mode First START bit Timing .................154
2
I C Master Mode Reception Timing..........................164
2
I C Master Mode Transmission Timing.....................161
Interrupt (INT, TMR0 Pins)..........................................40
Master Mode Transmit Clock Arbitration...................169
Oscillator Start-up Time ..............................................24
PIC17C752/756 Capture Timing...............................253
PIC17C752/756 CLKOUT and I/O ............................250
PIC17C752/756 External Clock ................................249
PIC17C752/756 Memory Interface Read..................266
PIC17C752/756 Memory Interface Write ..................265
PIC17C752/756 PWM Timing...................................253
PIC17C752/756 Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer .........................251
PIC17C752/756 Timer0 Clock ..................................252
PIC17C752/756 Timer1, Timer2 and Timer3 Clock..252
PIC17C752/756 USART Module Synchronous
Receive .....................................................................261
PIC17C752/756 USART Module
Synchronous Transmission.......................................260
Repeat START Condition .........................................156
Slave Synchronization ..............................................140
STOP Condition Receive or Transmit.......................167
Synchronous Reception............................................129
Synchronous Transmission.......................................128
Table Write..................................................................62
DS30289C-page 296
1998-2013 Microchip Technology Inc.
PIC17C7XX
TXREG2........................................................................ 27, 49
TXSTA .............................................................. 126, 130, 132
TXSTA Register
TXEN Bit ......................................... 34, 51, 97, 101, 117
TXSTA1 ........................................................................ 27, 48
TXSTA2 ........................................................................ 27, 49
U
UA..................................................................................... 134
Update Address, UA ......................................................... 134
Upward Compatibility............................................................ 7
USART
Asynchronous Master Transmission......................... 123
Asynchronous Mode ................................................. 123
Asynchronous Receive ............................................. 125
Asynchronous Transmitter........................................ 123
Baud Rate Generator................................................ 120
Synchronous Master Mode....................................... 127
Synchronous Master Reception................................ 129
Synchronous Master Transmission........................... 127
Synchronous Slave Mode......................................... 131
Synchronous Slave Transmit.................................... 131
Transmit Enable (TXEN Bit)............ 34, 51, 97, 101, 117
USART1 Receive Interrupt ................................................. 37
USART1 Transmit Interrupt ................................................ 37
USART2 Receive Interrupt Enable, RC2IE......................... 36
USART2 Receive Interrupt Flag bit, RC2IF ........................ 38
USART2 Receive Interrupt Flag bit, TX2IF......................... 38
USART2 Transmit Interrupt Enable, TX2IE ........................ 36
V
W
Wake-up from SLEEP....................................................... 194
Wake-up from SLEEP Through Interrupt.......................... 194
Watchdog Timer ............................................................... 193
Waveform for General Call Address Sequence................ 149
Waveforms
External Program Memory Access............................. 45
WCOL....................................... 135, 154, 159, 162, 165, 167
WCOL Status Flag............................................................ 154
WDT ................................................................................. 193
Clearing the WDT..................................................... 193
Normal Timer............................................................ 193
Period ....................................................................... 193
Programming Considerations................................... 193
WDT PERIOD................................................................... 275
WDTPS0........................................................................... 191
WDTPS1........................................................................... 191
Write Collision Detect bit, WCOL...................................... 135
WWW, On-Line Support ....................................................... 5
X
XORLW ............................................................................ 231
XORWF ............................................................................ 231
Z
Z ................................................................................... 11, 51
Zero (Z)............................................................................... 11
VDD.................................................................................... 242
VOH VS. IOH ....................................................................... 276
VOL VS. IOL ........................................................................ 276
1998-2013 Microchip Technology Inc.
DS30289C-page 297
PIC17C7XX
NOTES:
DS30289C-page 298
1998-2013 Microchip Technology Inc.
PIC17C7XX
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
1998-2013 Microchip Technology Inc.
DS30289C-page299
PIC17C7XX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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RE:
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Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS30289C
Device:
PIC17C7XX
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30289C-page300
1998-2013 Microchip Technology Inc.
PIC17C7XX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
b)
c)
PIC17C756 – 16L Commercial Temp.,
PLCC package, 16 MHz,
normal VDD limits
PIC17LC756–08/PT Commercial Temp.,
TQFP package, 8MHz,
extended VDD limits
Device
PIC17C756: Standard VDD range
PIC17C756T: (Tape and Reel)
PIC17LC756: Extended VDD range
PIC17C756–33I/PT Industrial Temp.,
TQFP package, 33 MHz,
normal VDD limits
Temperature Range
Package
-
I
=
=
0C to +70C
-40C to +85C
CL
PT
L
=
=
=
Windowed LCC
TQFP
PLCC
Pattern
QTP, SQTP, ROM Code (factory specified) or
Special Requirements . Blamk for OTP and
Windowed devices.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1998-2013 Microchip Technology Inc.
DS30289C-page301
PIC17C7XX
NOTES:
DS30289C-page302
1998-2013 Microchip Technology Inc.
PIC17C7XX
NOTES:
1998-2013 Microchip Technology Inc.
DS30289C-page303
PIC17C7XX
DS30289C-page 304
1998-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1998-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769317
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
1998-2013 Microchip Technology Inc.
DS30289C-page 305
Worldwide Sales and Service
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11/29/12
DS30289C-page 306
1998-2013 Microchip Technology Inc.
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