PIC17LC756AT-16/PTL16 [MICROCHIP]
8-BIT, OTPROM, 16 MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, TQFP-64;
| 型号： | PIC17LC756AT-16/PTL16 |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, OTPROM, 16 MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, TQFP-64 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总44页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC17LC75X-16/PTL16
High-Performance 8-Bit CMOS EPROM Microcontrollers with 10-bit A/D
PIC17LC752/756A is tested for high frequency,
low voltage operation - 16 MHz @ 3V
Pin Diagrams
64-Pin TQFP
Microcontroller Core Features:
• Only 58 single word instructions to learn
• All single cycle instructions (250 ns) except for
program branches and table reads/writes which
are two-cycle
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RD1/AD9
RD0/AD8
RE0/ALE
RE1/OE
RE2/WR
RE3/CAP4
MCLR/VPP
TEST
VSS
VDD
RF7/AN11
RF6/AN10
1
2
3
4
5
RA0/INT
RB0/CAP1
RB1/CAP2
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB2/PWM1
• Operating speed:
6
- DC - 16 MHz clock input
7
8
9
10
11
12
13
14
15
16
PIC17LC75X-16/PTL16
VSS
- DC - 250 ns instruction cycle
• 8 x 8 Single-Cycle Hardware Multiplier
• Interrupt capability
OSC2/CLKOUT
OSC1/CLKIN
VDD
RB7/SDO
RB6/SCK
RA3/SDI/SDA
RA2/SS/SCL
RA1/T0CKI
RF5/AN9
RF4/AN8
RF3/AN7
RF2/AN6
• 16 level deep hardware stack
• Direct, indirect, and relative addressing modes
• Internal/external program memory execution,
Capable of addressing 64K x 16 program memory
space
Memory
Device
Program (x16)
Data (x8)
Special Microcontroller Features:
PIC17LC752
8K
678
902
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
PIC17LC756A
16K
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Peripheral Features:
• Up to 50 I/O pins with individual direction control
• 10-bit, multi-channel analog-to-digital converter
• High current sink/source for direct LED drive
• Four capture input pins
• Brown-out Reset
• Code-protection
• Power saving SLEEP mode
• Selectable oscillator options
- Captures are 16-bit, max resolution 250 ns
• Three PWM outputs (resolution is 1- to 10-bits)
CMOS Technology:
• TMR0: 16-bit timer/counter with
8-bit programmable prescaler
• Low-power, high-speed CMOS EPROM
technology
• TMR1: 8-bit timer/counter
• TMR2: 8-bit timer/counter
• TMR3: 16-bit timer/counter
• Fully static design
• Wide operating voltage range (3.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption
• Two Universal Synchronous Asynchronous
Receiver Transmitters (USART/SCI) with Inde-
pendent baud rate generators
- < 5 mA @ 5V, 4 MHz
- 100 µA typical @ 4.5V, 32 kHz
- < 1 µA typical standby current @ 5V
• Master Synchronous Serial Port (MSSP) with
SPI™ and I2C™ modes (including I2C master
mode)
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 1
PIC17LC75X-16/PTL16
Table of Contents
1.0 Overview ...............................................................................................................................................................3
2.0 Development Support ...........................................................................................................................................5
3.0 Electrical Characteristics.......................................................................................................................................9
4.0 DC and AC Characteristics .................................................................................................................................35
5.0 Packaging Information ........................................................................................................................................47
Index ............................................................................................................................................................................39
On-Line Support............................................................................................................................................................41
Reader Response .........................................................................................................................................................42
Product Identification System........................................................................................................................................43
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-
sion of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
•
•
Fill out and mail in the reader response form in the back of this data sheet.
E-mail us at webmaster@microchip.com.
We appreciate your assistance in making this a better document.
DS30176A-page 2
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
1.0
OVERVIEW
This data sheet covers the PIC17LC752-16/PTL16
and PIC17LC756A-16/PTL16 devices. The functional
characteristics of these devices are identical to the
PIC17LC752A/756A devices. For electrical specifica-
tions, see the electrical specifications contained within
this document. For all other information about these
devices, see the PIC17C7XX data sheet (DS30289).
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 3
Features
PIC17C752
PIC17LC752-16/PTL16 PIC17C756A PIC17LC756A-16/PTL16
PIC17C762
PIC17C766
Maximum Frequency
of Operation
33 MHz
16 MHz
33 MHz
16 MHz
33 MHz
33 MHz
Operating Voltage Range
3.0 - 5.5V
8K
3.0 - 5.5V
8K
3.0 - 5.5V
16K
3.0 - 5.5V
16K
3.0 - 5.5V
8K
3.0 - 5.5V
16K
Program
(EPROM)
(ROM)
Memory ( x16)
—
—
—
—
—
—
Data Memory (bytes)
678
678
902
902
678
902
Hardware Multiplier (8 x 8)
Yes
Yes
Yes
Yes
Yes
Yes
Timer0
Yes
Yes
Yes
Yes
Yes
Yes
(16-bit + 8-bit postscaler)
Timer1 (8-bit)
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Yes
Yes
Yes
4
Timer2 (8-bit)
Timer3 (16-bit)
Capture inputs (16-bit)
PWM outputs (up to 10-bit)
USART/SCI
3
3
3
3
3
3
2
2
2
2
2
2
A/D channels (10-bit)
SSP (SPI/I2C w/Master
mode)
12
Yes
12
Yes
12
Yes
12
Yes
16
Yes
16
Yes
Power-on Reset
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Yes
Yes
Yes
18
Watchdog Timer
External Interrupts
Interrupt Sources
Code Protect
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
In-circuit Serial Programming
I/O Pins
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
50
50
50
50
66
66
I/O High Current Source
25 mA
25 mA
25 mA
25 mA
25 mA
25 mA
Capability
25 mA(1)
25 mA(1)
25 mA(1)
25 mA(1)
25 mA(1)
25 mA(1)
Sink
Package Types
68-pin LCC
64-pin TQFP
68-pin LCC
64-pin TQFP
80-pin QFP
80-pin QFP
68-pin TQFP
68-pin TQFP
84-pin PLCC
84-pin PLCC
Note 1: Pins RA2 and RA3 can sink up to 60 mA.
PIC17LC75X-16/PTL16
MPLAB allows you to:
2.0
DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB™ IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
2.2
MPASM Assembler
Emulator
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- PICDEM-17
2.1
MPLAB Integrated Development
Environment Software
MPASM features include:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows -based applica-
tion which contains:
• MPASM and MPLINK are integrated into MPLAB
projects.
• MPASM allows user defined macros to be created
for streamlined assembly.
• Multiple functionality
- editor
• MPASM allows conditional assembly for multi pur-
pose source files.
- simulator
• MPASM directives allow complete control over the
assembly process.
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
2.3
MPLAB-C17 and MPLAB-C18
C Compilers
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
• On-line help
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 5
PIC17LC75X-16/PTL16
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
2.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
2.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
2.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
2.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
PIC16C7X, and PIC16CXXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of interchange-
able personality modules or daughter boards. The
emulator is capable of emulating without target applica-
tion circuitry being present.
2.9
PRO MATE II Universal Programmer
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allow it to verify programmed memory at
VDD min. and VDD max. for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
2.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS30176A-page 6
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
2.10
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
2.11
PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 7
PIC17LC75X-16/PTL16
TABLE 2-1:
DEVELOPMENT TOOLS FROM MICROCHIP
5 1 2 0 P M C
X X R X F C M
X X
H C S X
X X C 9 3
C 5 X 2 X /
C 4 X 2 X /
X X C 8 2 C 1 P I
X X 7 C 7 C 1 P I
X 4 C 7 C 1 P I
X X 9 C 6 C 1 P I
X 8 X 1 6 C I F P
X 8 C 6 C 1 P I
X X 7 C 6 C 1 P I
X 7 C 6 C 1 P I
X 6 2 6 1 F C I P
X X C 6 X C 1 P I
X 6 C 6 C 1 P I
X 5 C 6 C 1 P I
0 0 4 0 1 C I P
X X C 2 X C 1 P I
s l o o e T a r f t o w S s o r a t u l E m e r g g b e u D s m e a r m o g P r r
t i s K v a E l d a n d s a r o B o m e D
DS30176A-page 8
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
3.0
PIC17LC75X-16/PTL16 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................. 0V to +7.5V
Voltage on MCLR with respect to VSS (Note 2).......................................................................................... -0.3V to +14V
Voltage on RA2 and RA3 with respect to VSS............................................................................................ -0.3V to +8.5V
Voltage on all other pins with respect to VSS .....................................................................................-0.3V to VDD + 0.3V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin(s) - total (@ 70°C)............................................................................................500 mA
Maximum current into VDD pin(s) - total (@ 70°C)...............................................................................................500 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin (except RA2 and RA3).....................................................................35 mA
Maximum output current sunk by RA2 or RA3 pins ................................................................................................60 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA and PORTB (combined).................................................................................150 mA
Maximum current sourced by PORTA and PORTB (combined)............................................................................100 mA
Maximum current sunk by PORTC, PORTD and PORTE (combined)..................................................................150 mA
Maximum current sourced by PORTC, PORTD and PORTE (combined).............................................................100 mA
Maximum current sunk by PORTF and PORTG (combined) ................................................................................150 mA
Maximum current sourced by PORTF and PORTG (combined)...........................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin, rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at those or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
CAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
PIC17LC75X-16/PTL16 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 9
PIC17LC75X-16/PTL16
FIGURE 3-1: PIC17LC75X-16/PTL16 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
16 MHz
Frequency (MHz)
DS30176A-page 10
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
3.1
DC CHARACTERISTICS: PIC17LC75X-16/PTL16 (Commercial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Param.
No.
Sym
Characteristic
Min
3.0
Typ†
Max
5.5
–
Units
Conditions
VDD
Supply Voltage
–
–
V
V
D001
VDR
RAM Data Retention
Voltage (Note 1)
1.5 *
Device in SLEEP mode
D002
VPOR
VDD start voltage to
ensure internal
Power-on Reset signal
–
VSS
–
–
V
See section on Power-on
Reset for details
D003
D004
SVDD
VBOR
VDD rise rate to
ensure proper
operation
0.010 *
–
V/ms
See section on Power-on
Reset for details
Brown-out Reset
voltage trip point
3.65
–
–
4.35
–
V
V
D005
D006
VPORTP
IDD
Power-on Reset trip point
2.2
VDD = VPORTP
Supply Current
(Note 2)
–
–
–
3
3
85
6 *
6
150
mA
mA
µA
FOSC = 4 MHz (Note 4)
FOSC = 16 MHz, VDD = 3V
FOSC = 32 kHz,
D010
D011
D014
(EC osc configuration)
IPD
Power-down Current
(Note 3)
–
< 1
5
µA
VDD = 3.0V,
WDT disabled
D021
Module Differential
Current
∆IBOR
∆IWDT
∆IAD
BOR circuitry
Watchdog Timer
A/D converter
–
–
–
150
10
1
300
35
–
µA
µA
µA
VDD = 4.5V, BODEN enabled
VDD = 5.5V
D023
D024
D026
VDD = 5.5V, A/D not convert-
ing
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current
consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD, MCLR = VDD;
WDT disabled.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes extended
microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by
the formula IR = VDD/2Rext (mA) with Rext in kOhm.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 11
PIC17LC75X-16/PTL16
3.2
DC CHARACTERISTICS: PIC17LC75X-16/PTL16 (Commercial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in Section 3.1 of the
PIC17C7XX Data Sheet, (DS30289)
DC CHARACTERISTICS
Param.
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Input Low Voltage
I/O ports
with TTL buffer (Note 6)
VIL
VSS
VSS
–
–
0.8
0.2VDD
V
V
4.5V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 4.5V
D030
D031
with Schmitt Trigger buffer
RA2, RA3
2
VSS
VSS
–
–
0.3VDD
0.2VDD
V
V
I C compliant
All others
D032
D033
MCLR, OSC1 (in EC and RC mode)
OSC1 (in XT, and LF mode)
VSS
–
0.2VDD
V
V
Note1
–
0.5VDD
–
Input High Voltage
I/O ports
VIH
with TTL buffer (Note 6)
2.0
1 + 0.2VDD
–
–
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 4.5V
D040
D041
with Schmitt Trigger buffer
RA2, RA3
2
0.7VDD
0.8VDD
–
–
VDD
VDD
V
V
I C compliant
All others
D042
D043
D050
MCLR
0.8VDD
–
VDD
V
V
Note1
OSC1 (XT, and LF mode)
–
0.5VDD
–
VHYS
IIL
Hysteresis of
0.15VDD *
–
–
–
–
V
Schmitt Trigger inputs
Input Leakage Current
(Notes 2, 3)
I/O ports (except RA2, RA3)
–
±1
µA VSS ≤ VPIN ≤ VDD,
I/O Pin (in digital mode) at
hi-impedance PORTB weak
pull-ups disabled
D060
D061
D062
D063
D063B
D064
MCLR, TEST
RA2, RA3
–
±2
±2
µA VPIN = Vss or VPIN = VDD
µA VSS ≤ VRA2, VRA3 ≤ 12V
OSC1 (EC, RC modes)
OSC1 (XT, LF modes)
–
–
–
–
±1
µA VSS ≤ VPIN ≤ VDD
µA RF ≥ 1 MΩ
VPIN
MCLR, TEST
–
–
25
µA VMCLR = VPP = 12V
(when not programming)
D070
IPURB
PORTB weak pull-up current
60
200
400
µA VPIN = VSS, RBPU = 0
4.5V ≤ VDD ≤ 5.5V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC17C7XX
devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the table write
instructions. The complete programming specifications can be found in: PIC17C7XX Programming Specification (Literature
number DS30274).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
DS30176A-page 12
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in Section 3.1 of the
PIC17C7XX Data Sheet, (DS30289)
DC CHARACTERISTICS
Param.
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Output Low Voltage
I/O ports
VOL
IOL = VDD/1.250 mA
4.5V ≤ VDD ≤ 5.5V
VDD = 3.0V
IOL = 6 mA, VDD = 4.5V
Note 6
D080
–
–
–
–
–
–
0.1VDD
0.1VDD *
0.4
V
V
V
with TTL buffer
D081
RA2 and RA3
–
–
–
–
–
–
–
–
–
–
3.0
0.4
0.6
V
V
V
V
V
IOL = 60.0 mA, VDD = 5.5V
IOL = 60.0 mA, VDD = 2.5V
IOL = 60.0 mA, VDD = 4.5V
IOL = 1 mA, VDD = 4.5V
IOL = VDD/5 mA
D082
OSC2/CLKOUT
(RC and EC osc modes)
0.4
0.1VDD *
D083
D084
(PIC17LC75X-16/PTL16 only)
Output High Voltage (Note 3)
VOH
I/O ports (except RA2 and RA3)
IOH = -VDD/2.5 mA
4.5V ≤ VDD ≤ 5.5V
VDD = 3.0V
IOH = -6.0 mA, VDD = 4.5V
Note 6
D090
D091
0.9VDD
0.9VDD *
2.4
–
–
–
–
–
–
V
V
V
with TTL buffer
OSC2/CLKOUT
(RC and EC osc modes)
2.4
0.9VDD *
–
–
–
–
V
V
IOH = -5 mA, VDD = 4.5V
IOH = -VDD/5 mA
D093
D094
(PIC17LC75X-16/PTL16 only)
RA2 and RA3 pins only
pulled-up to externally applied
voltage
VOD
Open Drain High Voltage
–
–
8.5
V
D150
D100
Capacitive Loading Specs on Out-
put Pins
COSC2 OSC2/CLKOUT pin
–
–
25 ‡
pF In EC or RC osc modes when
OSC2 pin is outputting CLK-
OUT. External clock is used to
drive OSC1.
CIO
All I/O pins and OSC2
(in RC mode)
–
–
–
–
50 ‡
50 ‡
pF
D101
D102
CAD
System Interface Bus
(PORTC, PORTD and PORTE)
pF In microprocessor or extended
microcontroller mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC17C7XX
devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the table write
instructions. The complete programming specifications can be found in: PIC17C7XX Programming Specification (Literature
number DS30274).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 13
PIC17LC75X-16/PTL16
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +40°C
Operating voltage VDD range as described in Section 3.1 of the
PIC17C7XX Data Sheet, (DS30289)
DC CHARACTERISTICS
Param.
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
Internal Program Memory Pro-
gramming Specs (Note 4)
D110
D111
VPP
VDDP
Voltage on MCLR/VPP pin
Supply voltage during
programming
12.75
4.75
–
5.0
13.25
5.25
V
V
Note 5
D112
D113
IPP
IDDP
Current into MCLR/VPP pin
Supply current during
programming
–
–
25 ‡
–
50 ‡
30 ‡
mA
mA
D114
TPROG Programming pulse width
100
–
1000
µs Terminated via internal/external
interrupt or a reset
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC17C7XX
devices be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: These specifications are for the programming of the on-chip program memory EPROM through the use of the table write
instructions. The complete programming specifications can be found in: PIC17C7XX Programming Specification
(Literature number DS30274).
5: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
6: For TTL buffers, the better of the two specifications may be used.
Note: Internal Program Memory Programming Specs:
When using the Table Write for internal programming, the device temperature must be less than 40°C.
For In-Circuit Serial Programming (ICSP ), refer to the device programming specification.
DS30176A-page 14
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
3.3
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
2. TppS
T
F
Frequency
T
Time
Lowercase symbols (pp) and their meanings:
pp
ad
Address/Data
ALE
ost
pwrt
rb
Oscillator Start-Up Timer
Power-Up Timer
PORTB
al
cc
ck
dt
Capture1 and Capture2
CLKOUT or clock
Data in
rd
RD
rw
RD or WR
in
INT pin
t0
T0CKI
io
I/O port
t123
wdt
wr
TCLK12 and TCLK3
Watchdog Timer
WR
mc
oe
os
MCLR
OE
OSC1
Uppercase symbols and their meanings:
S
D
E
F
H
I
Driven
L
Low
Edge
P
R
V
Z
Period
Rise
Fall
High
Valid
Invalid (Hi-impedance)
Hi-impedance
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 15
PIC17LC75X-16/PTL16
FIGURE 3-2: PARAMETER MEASUREMENT INFORMATION
All timings are measured between high and low measurement points as indicated in the figures below.
Input Level Conditions
PORTC, D, E, F and G pins
VIH = 2.4V
VIL = 0.4V
Data in valid
All other input pins
Data in invalid
VIH = 0.9 VDD
VIL = 0.1 VDD
Data in valid
Data in invalid
Output Level Conditions
0.25V
0.25V
VOH = 0.7 VDD
VDD/2
VOL = 0.3 VDD
0.25V
0.25V
Data out valid
Data out invalid
Output
driven
Output
hi-impedance
0.9 VDD
Fall Time
0.1 VDD
Rise Time
Load Conditions
Load Condition 1
Pin
CL
VSS
50 pF ≤ CL
DS30176A-page 16
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
3.4
Timing Diagrams and Specifications
FIGURE 3-3: EXTERNAL CLOCK TIMING
Q4
Q3
3
Q4
3
Q1
Q1
Q2
OSC1
1
4
4
2
OSC2 †
† In EC and RC modes only.
TABLE 3-1:
Param
EXTERNAL CLOCK TIMING REQUIREMENTS
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
DC
—
16
MHz EC osc mode
FOSC External CLKIN Frequency
(Note 1)
Oscillator Frequency
(Note 1)
DC
2
DC
—
—
—
4
16
2
MHz RC osc mode
MHz XT osc mode
MHz LF osc mode
TOSC
External CLKIN Period
(Note 1)
62.5
—
—
ns
EC osc mode
1
Oscillator Period
(Note 1)
250
62.5
500
—
—
—
—
1,000
—
ns
ns
ns
RC osc mode
XT osc mode
LF osc mode
TCY
Instruction Cycle Time
(Note 1)
121.2 4/FOSC
DC
ns
ns
ns
2
3
4
TosL, Clock in (OSC1)
TosH high or low time
10 ‡
—
—
—
—
EC oscillator
EC oscillator
TosR, Clock in (OSC1)
TosF rise or fall time
5 ‡
†
‡
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 17
PIC17LC75X-16/PTL16
FIGURE 3-4: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
OSC2 †
13
12
18
16
14
19
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
† In EC and RC modes only.
TABLE 3-2:
CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10
11
12
13
14
15
16
17
18
TosL2ckL
OSC1↓ to CLKOUT↓
—
—
15 ‡
15 ‡
30 ‡
30 ‡
ns
ns
Note 1
Note 1
TosL2ckH OSC1↓ to CLKOUT↑
TckR
CLKOUT rise time
—
—
—
5 ‡
5 ‡
—
15 ‡
15 ‡
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
TckF
CLKOUT fall time
TckH2ioV
TioV2ckH
TckH2ioI
TosL2ioV
TosL2ioI
CLKOUT ↑ to Port out valid
Port in valid before CLKOUT↑
Port in hold after CLKOUT↑
OSC1↓ (Q1 cycle) to Port out valid
0.5TCY + 20 ‡
0.25TCY + 25 ‡
—
—
—
0 ‡
—
—
—
100 ‡
—
OSC1↓ (Q2 cycle) to Port input
invalid
0 ‡
—
(I/O in hold time)
TioV2osL
Port input valid to OSC1↓
(I/O in setup time)
30 ‡
—
—
ns
19
TioR
Port output rise time
Port output fall time
INT pin high or low time
—
—
10 ‡
10 ‡
—
35 ‡
35 ‡
—
ns
ns
ns
ns
20
21
22
23
TioF
TinHL
TrbHL
25 *
25 *
RB7:RB0 change INT high or low
time
—
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Measurements are taken in EC Mode where CLKOUT output is 4 x TOSC.
DS30176A-page 18
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
FIGURE 3-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET TIMING
VDD
MCLR
30
Internal
POR / BOR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
35
Address /
Data
TABLE 3-3:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
VDD = 5V
30
TmcL
MCLR Pulse Width (low)
100 *
—
—
ns
TWDT
Watchdog Timer Time-out Period
(Postscale = 1)
5 *
12
25 *
ms
VDD = 5V
31
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period
Power-up Timer Period
—
1024TOSC§
—
200 *
—
ms
ms
ns
TOSC = OSC1 period
VDD = 5V
32
33
34
40 *
96
—
MCLR to I/O hi-impedance
100 ‡
Depends on pin load
35
TmcL2adI MCLR to System Interface bus
(AD15:AD0>) invalid
—
—
—
120 *
—
ns
ns
36
TBOR
Brown-out Reset Pulse Width (low)
100 *
3.9V ≤ VDD ≤ 4.2V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
§
These parameters are for design guidance only and are not tested, nor characterized.
This specification ensured by design.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 19
PIC17LC75X-16/PTL16
FIGURE 3-6: TIMER0 EXTERNAL CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 3-4:
TIMER0 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width No Prescaler
0.5TCY + 20 §
—
—
ns
With Prescaler
Tt0L T0CKI Low Pulse Width No Prescaler
With Prescaler
10*
0.5TCY + 20 §
10*
—
—
—
—
—
—
—
—
ns
ns
ns
41
42
Tt0P T0CKI Period
GREATER OF:
20 NS OR TCY + 40 §
ns N = prescale value
(1, 2, 4, ..., 256)
N
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 3-7: TIMER1, TIMER2, AND TIMER3 EXTERNAL CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 3-5:
TIMER1, TIMER2, AND TIMER3 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
45
46
47
Tt123H TCLK12 and TCLK3 high time
0.5TCY + 20 §
0.5TCY + 20 §
—
—
—
ns
ns
Tt123L TCLK12 and TCLK3 low time
—
—
Tt123P TCLK12 and TCLK3 input period
TCY + 40 §
—
ns N = prescale value
(1, 2, 4, 8)
N
TckE2tmrI Delay from selected External Clock Edge to
Timer increment
2TOSC §
—
6TOSC §
—
48
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
DS30176A-page 20
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
FIGURE 3-8: CAPTURE TIMINGS
CAP pin
(Capture Mode)
50
51
52
TABLE 3-6:
CAPTURE REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
50
51
52
TccL Capture pin input low time
10 *
—
—
—
—
ns
ns
TccH
TccP
10 *
Capture pin input high time
Capture pin input period
2TCY §
N
—
—
ns N = prescale value (4
or 16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 3-9: PWM TIMINGS
PWM pin
(PWM Mode)
53
54
TABLE 3-7:
PWM REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
53
TccR PWM pin output rise time
—
—
10 * 35 *
10 * 35 *
ns
ns
TccF PWM pin output fall time
54
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 21
PIC17LC75X-16/PTL16
FIGURE 3-10: SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 3-2 for load conditions.
TABLE 3-8:
Param.
SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY *
—
—
ns
70
TscH
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30 *
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
71
40
1.25TCY + 30 *
40
Note 1
Note 1
71A
72
TscL
SCK input low time
(slave mode)
72A
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100 *
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40 *
—
—
—
—
ns
ns
Note 1
73A
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100 *
TdoR
TdoF
TscR
TscF
SDO data output rise time
—
—
—
—
—
10
10
10
10
—
25 *
25 *
25 *
25 *
50 *
ns
ns
ns
ns
ns
75
76
78
79
80
SDO data output fall time
SCK output rise time (master mode)
SCK output fall time (master mode)
SDO data output valid after SCK edge
TscH2doV,
TscL2doV
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30176A-page 22
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
FIGURE 3-11: SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 3-2 for load conditions.
TABLE 3-9:
Param.
SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Symbol
Characteristic
Min
Typ† Max Units
Conditions
No.
TscH
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30 *
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
71
40
1.25 TCY + 30 *
40
Note 1
71A
72
TscL
SCK input low time
(slave mode)
Note 1
Note 1
72A
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100 *
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40 *
—
—
—
—
ns
ns
73A
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100 *
TdoR
TdoF
TscR
TscF
SDO data output rise time
—
—
—
—
—
10
10
10
10
—
25 *
25 *
25 *
25 *
50 *
ns
ns
ns
ns
ns
75
76
78
79
80
SDO data output fall time
SCK output rise time (master mode)
SCK output fall time (master mode)
SDO data output valid after SCK edge
TscH2doV,
TscL2doV
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
TCY *
—
—
ns
81
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 23
PIC17LC75X-16/PTL16
FIGURE 3-12: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 3-2 for load conditions.
TABLE 3-10: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY *
—
—
ns
70
TscH
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30 *
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
71
40
1.25TCY + 30 *
40
Note 1
Note 1
71A
72
TscL
SCK input low time
(slave mode)
72A
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100 *
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40 *
—
—
—
—
ns
ns
Note 1
73A
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100 *
TdoR
SDO data output rise time
—
—
10
10
—
10
10
—
25 *
25 *
50 *
25 *
25 *
50 *
ns
ns
ns
ns
ns
ns
75
76
77
78
79
80
TdoF
SDO data output fall time
TssH2doZ
TscR
SS↑ to SDO output hi-impedance
SCK output rise time (master mode)
SCK output fall time (master mode)
SDO data output valid after SCK edge
10 *
—
TscF
—
TscH2doV,
TscL2doV
—
TscH2ssH,
TscL2ssH
SS ↑ after SCK edge
1.5TCY + 40 *
—
—
ns
83
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30176A-page 24
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
FIGURE 3-13: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 3-2 for load conditions.
TABLE 3-11: SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 1)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY *
—
—
ns
70
TscH
TscL
TB2B
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30 *
40
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
71
Note 1
71A
72
SCK input low time
(slave mode)
1.25TCY + 30 *
40
Note 1
Note 1
72A
73A
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40 *
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100 *
—
—
ns
74
TdoR
SDO data output rise time
—
—
10
10
—
—
25 *
25 *
50 *
50 *
ns
ns
ns
ns
75
76
77
80
TdoF
SDO data output fall time
TssH2doZ
SS↑ to SDO output hi-impedance
SDO data output valid after SCK edge
10 *
—
TscH2doV,
TscL2doV
TssL2doV
SDO data output valid after SS↓ edge
SS ↑ after SCK edge
—
—
—
50 *
—
ns
ns
82
83
TscH2ssH,
TscL2ssH
1.5TCY + 40 *
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 25
PIC17LC75X-16/PTL16
FIGURE 3-14: I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 3-2 for load conditions.
TABLE 3-12: I2C BUS START/STOP BITS REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ Max Units
Conditions
90
TSU:STA START condition 100 kHz mode
Setup time 400 kHz mode
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
2(TOSC)(BRG + 1) §
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated
START condition
ns
ns
ns
ns
(1)
1 MHz mode
THD:STA START condition 100 kHz mode
After this period the first
clock pulse is generated
91
92
93
Hold time
400 kHz mode
(1)
1 MHz mode
100 kHz mode
400 kHz mode
TSU:STO STOP condition
Setup time
(1)
1 MHz mode
100 kHz mode
400 kHz mode
THD:STO STOP condition
Hold time
(1)
1 MHz mode
§
This specification ensured by design.
2
Note 1: Maximum pin capacitance = 10 pF for all I C pins.
DS30176A-page 26
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
FIGURE 3-15: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 3-2 for load conditions.
TABLE 3-13: I2C BUS DATA REQUIREMENTS
Param No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode 2(TOSC)(BRG + 1) §
—
—
—
—
—
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
µs
µs
µs
pF
400 kHz mode 2(TOSC)(BRG + 1) §
(1)
1 MHz mode
2(TOSC)(BRG + 1) §
TLOW
TR
Clock low time
100 kHz mode 2(TOSC)(BRG + 1) §
101
102
103
90
400 kHz mode 2(TOSC)(BRG + 1) §
(1)
1 MHz mode
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1) §
—
SDA and SCL
rise time
—
1000 *
300 *
300 *
300 *
300 *
100 *
—
—
—
—
—
—
—
0.9 *
—
—
—
—
—
—
Cb is specified to be from
10 to 400 pF
20 + 0.1Cb *
(1)
1 MHz mode
100 kHz mode
400 kHz mode
—
TF
SDA and SCL
fall time
—
20 + 0.1Cb *
—
Cb is specified to be from
10 to 400 pF
(1)
1 MHz mode
TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) §
setup time 400 kHz mode 2(TOSC)(BRG + 1) §
Only relevant for repeated
START condition
(1)
1 MHz mode
2(TOSC)(BRG + 1) §
THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) §
After this period the first
clock pulse is generated
91
hold time
400 kHz mode 2(TOSC)(BRG + 1) §
(1)
1 MHz mode
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1) §
THD:DAT Data input
0
0
106
107
92
hold time
(1)
1 MHz mode
100 kHz mode
400 kHz mode
TBD *
250 *
100 *
TBD *
TSU:DAT Data input
Note 2
setup time
(1)
1 MHz mode
TSU:STO STOP condition
100 kHz mode 2(TOSC)(BRG + 1) §
setup time
400 kHz mode 2(TOSC)(BRG + 1) §
(1)
1 MHz mode
2(TOSC)(BRG + 1) §
—
TAA
TBUF
Cb
Output valid from 100 kHz mode
clock
—
—
—
4.7 ‡
1.3 ‡
TBD *
—
3500 *
1000 *
—
—
—
109
110
400 kHz mode
(1)
1 MHz mode
100 kHz mode
400 kHz mode
Bus free time
Time the bus must be free
before a new transmission
can start
(1)
1 MHz mode
Bus capacitive loading
—
400 *
D102 ‡
Note 3, 4
*
Characterized but not tested.
§
‡
This specification ensured by design.
These parameters are for design guidance only and are not tested, nor characterized.
2
Note 1: Maximum pin capacitance = 10 pF for all I C pins.
2
2
2: A fast-mode (400 kHz) I C-bus device can be used in a standard-mode I C-bus system, but the parameter # 107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
PARAMETER # 102 + # 107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released.
3: C is specified to be from 10-400pF. The minimum specifications are characterized with C =10pF. The rise time spec (t )
b
b
r
is characterized with R =R min. The minimum fall time specification (t ) is characterized with C =10pF, and R =R max.
p
p
f
b
p
p
These are only valid for fast mode operation (VDD=4.5-5.5V) and where the SPM bit (SSPSTAT<7>)=1.)
4: Max specifications for these parameters are valid for falling edge only. Specs are characterized with R =R min and
p
p
C =400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.
b
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 27
PIC17LC75X-16/PTL16
FIGURE 3-16: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TX/CK
pin
121
121
RX/DT
pin
122
120
TABLE 3-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
TckH2dtV SYNC XMIT (MASTER &
SLAVE)
PIC17LCXXX
—
—
75 *
ns
120
Clock high to data out valid
TckRF
Clock out rise time and fall time PIC17LCXXX
(Master Mode)
—
—
—
—
40 *
40 *
ns
ns
121
122
TdtRF
Data out rise time and fall time PIC17LCXXX
*
Characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 3-17: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TX/CK
pin
125
RX/DT
pin
126
TABLE 3-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data setup before CK↓ (DT setup time)
15
—
—
—
—
ns
ns
TckL2dtl
Data hold after CK↓ (DT hold time)
15
126
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30176A-page 28
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
FIGURE 3-18: USART ASYNCHRONOUS MODE START BIT DETECT
Start bit
RX
(RX/DT pin)
121A
x16 CLK
Q2, Q4 CLK
120A
123A
TABLE 3-16: USART ASYNCHRONOUS MODE START BIT DETECT REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
120A
TdtL2ckH
Time to ensure that the RX pin is sampled low
—
—
—
—
TCY §
ns
ns
121A
TdtRF
Data rise time and fall time
Receive
Transmit
Note 1
—
—
—
—
40 †
ns
ns
TckH2bckL Time from RX pin sampled low to first rising edge
of x16 clock
TCY §
123A
†
§
These parameters are for design guidance only and are not tested.
This specification ensured by design.
Note 1: Schmitt trigger will determine logic level.
FIGURE 3-19: USART ASYNCHRONOUS RECEIVE SAMPLING WAVEFORM
Start bit
Bit0
RX
(RX/DT pin)
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
126A
1
2
3
125A
Samples
TABLE 3-17: USART ASYNCHRONOUS RECEIVE SAMPLING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
125A
TdtL2ckH
Setup time of RX pin to first data
sampled
TCY §
—
—
ns
126A
TdtL2ckH
Hold time of RX pin from last data
sampled
TCY §
—
—
ns
§
This specification ensured by design.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 29
PIC17LC75X-16/PTL16
TABLE 3-18: A/D CONVERTER CHARACTERISTICS
Param.
No.
Sym Characteristic
NR Resolution
Min
Typ†
Max
Units
Conditions
VREF+ = VDD = 5.12V,
A01
—
—
10
bit
VSS ≤ VAIN ≤ VREF+
—
—
—
—
10*
bit
(VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
EABS Absolute error
< ±1
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
A02
A03
A04
A05
A06
—
—
—
—
< ±1*
< ±1
LSb (VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
EIL
EDL
EFS
Integral linearity error
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
—
—
—
—
< ±1*
< ±1
LSb (VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
Differential linearity error
Full scale error
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
—
—
—
—
< ±1*
< ±1
LSb (VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
—
—
—
—
< ±1*
< ±1
LSb (VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
EOFF Offset error
LSb VREF+ = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF+
LSb
—
—
—
< ±1*
—
(VREF+ — VREF-) ≥ 3.0V,
VREF- ≤ VAIN ≤ VREF+
—
Monotonicity
guaran-
teed
—
V
VSS ≤ VAIN ≤ VREF
A10
A20
A20A
A21
A22
A25
A30
A40
A50
(3)
VREF Reference voltage
(VREF+ — VREF-)
0V
—
—
—
—
—
—
90
—
—
—
VREF delta when changing voltage lev-
els on VREF inputs.
3V *
—
V
Absolute minimum electrical spec.
To ensure 10-bit accuracy
VREF+ Reference voltage High
VREF- Reference voltage Low
AVSS
+ 3.0V
AVDD +
0.3V
V
AVSS -
0.3V
AVDD -
3.0V
V
VAIN
ZAIN
IAD
Analog input voltage
AVSS -
0.3V
VREF +
0.3V
V
Recommended impedance of
analog voltage source
—
—
10
—
10.0
kΩ
µA
µA
µA
A/D conversion current (VDD)
—
Average current consumption when
A/D is on. (Note 1)
IREF
VREF input current (Note 2)
1000
10
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
During A/D conversion cycle
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RG0 and RG1 pins or AVDD and AVSS pins, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage and has no missing codes.
DS30176A-page 30
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
FIGURE 3-20: A/D CONVERSION TIMING
BSF ADCON0, GO
1 Tcy
(Tosc/2) (1)
131
Q4
130
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 3-19: A/D CONVERSION REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
3.0
—
6.0
—
—
µs
µs
TOSC based, VREF full range
TAD
A/D clock period
130
3.0 *
11 §
9.0 *
12 §
A/D RC Mode
TCNV
TACQ
Conversion time
(not including acquisition time) (Note 1)
TAD
131
132
Acquisition time
(Note 2)
10 *
20
—
—
—
µs
µs
The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e. 5 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
TGO
Q4 to ADCLK start
—
Tosc/2 §
—
—
If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
SLEEP instruction to be exe-
cuted.
134
*
These parameters are characterized but not tested.
†
§
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 16.1 of the PIC17C7XX Data Sheet (DS30289) for minimum conditions when input voltage has changed
more than 1 LSb.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 31
PIC17LC75X-16/PTL16
FIGURE 3-21: MEMORY INTERFACE WRITE TIMING
Q1
Q2
Q3
Q4
Q2
Q1
OSC1
ALE
OE
151
WR
150
addr out
154
data out
AD<15:0>
addr out
152
153
TABLE 3-20: MEMORY INTERFACE WRITE REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ†
Max Units Conditions
150
TadV2alL AD<15:0> (address) valid to ALE↓ (address 0.25TCY - 10*
—
—
ns
setup time)
TalL2adI
ALE↓ to address out invalid(address hold
time)
0*
—
—
ns
151
152
153
154
TadV2wrL (data setup time)
0.25TCY - 40*
—
—
—
—
ns
ns
ns
TwrH2adI WR↑ to data out invalid(data hold time)
—
—
0.25TCY§
0.25TCY§
TwrL
WR pulse width
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
DS30176A-page 32
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
FIGURE 3-22: MEMORY INTERFACE READ TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
OE
164
168
160
165
161
Data in
162
AD<15:0>
WR
Addr out
150
Addr out
151
163
167
'1'
'1'
TABLE 3-21: MEMORY INTERFACE READ REQUIREMENTS
Param.
No.
Condi-
tions
Sym
Characteristic
Min
Typ†
Max
Units
150
TadV2alL AD15:AD0 (address) valid to ALE↓
0.25TCY - 10*
—
—
—
ns
ns
(address setup time)
TalL2adI
ALE↓ to address out invalid(address hold
5*
—
151
time)
160
161
162
163
164
165
166
167
168
TadZ2oeL AD15:AD0 hi-impedance to OE↓
ToeH2adD OE↑ to AD15:AD0 driven
0*
0.25TCY - 15*
45*
—
—
—
—
—
—
ns
ns
ns
ns
ns
TadV2oeH Data in valid before OE↑ (data setup time)
ToeH2adI OE↑to data in invalid (data hold time)
0*
—
—
—
—
TalH
ToeL
ALE pulse width
OE pulse width
0.25TCY §
0.5TCY - 35 §
—
—
—
ns
ns
ns
TalH2alH ALE↑ to ALE↑(cycle time)
—
TCY §
Tacc
Toe
Address access time
—
—
—
—
0.75TCY - 45*
0.5TCY - 75*
Output enable access time(OE low to Data
Valid)
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 33
PIC17LC75X-16/PTL16
NOTES:
DS30176A-page 34
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
4.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Please refer to the PIC17C7XX Data Sheet (DS30289)
for the most current graphs and tables.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 35
PIC17LC75X-16/PTL16
NOTES:
DS30176A-page 36
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
64-Lead TQFP
Example
MMMMMMMMMM
MMMMMMMMMM
MMMMMMMMMM
PIC17C752
-16/PTL16
YYWWNNN
9917017
Legend: MM...M Microchip part number information
XX...X Customer specific information*
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 37
PIC17LC75X-16/PTL16
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
L
A2
φ
β
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
64
64
.020
16
0.50
16
Pins per Side
Overall Height
n1
A
.039
.043
.039
.006
.024
.039
3.5
.047
1.00
1.10
1.00
0.15
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.037
.002
.018
.041
.010
.030
0.95
0.05
0.45
1.05
0.25
0.75
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.005
.007
.025
5
7
.482
.482
.398
.398
.009
.011
.045
15
0
11.75
11.75
9.90
9.90
0.13
0.17
0.64
5
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.007
.009
.035
10
12.00
12.00
10.00
10.00
0.18
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
β
5
10
15
5
10
15
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
DS30176A-page 38
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
INDEX
A
A/D
Converter Characteristics ........................................... 30
Assembler
MPASM Assembler....................................................... 5
D
Development Support ........................................................... 5
E
Electrical Characteristics
Absolute Maximum Ratings .......................................... 9
Capture Timing ........................................................... 21
CLKOUT and I/O Timing............................................. 18
External Clock Timing................................................. 17
Memory Interface Read Timing................................... 33
Memory Interface Write Timing................................... 32
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing ............................. 19
Timer0 Clock Timing................................................... 20
Timer1, Timer2 and Timer3 Clock Timing................... 20
Timing Parameter Symbology..................................... 15
USART Module Synchronous Receive Timing ........... 28
USART Module Synchronous Transmission Timing... 28
Errata .................................................................................... 2
F
Family of Devices
PIC17C7XX................................................................... 4
M
MPLAB Integrated Development Environment Software ...... 5
P
Packaging Information ........................................................ 37
PICSTART Plus Entry Level Development System ........... 7
PRO MATE II Universal Programmer ................................ 6
S
Software Simulator (MPLAB-SIM) ........................................ 6
T
Timing Diagrams
A/D Conversion........................................................... 31
Capture Timing ........................................................... 21
CLKOUT and I/O......................................................... 18
External Clock............................................................. 17
2
I C Bus Data............................................................... 27
2
I C Bus Start/Stop bits................................................ 26
Memory Interface Read .............................................. 33
Memory Interface Write............................................... 32
PWM Timing ............................................................... 21
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer ......................................... 19
Timer0 Clock............................................................... 20
Timer1, Timer2 and Timer3 Clock .............................. 20
USART Module Synchronous Receive....................... 28
USART Module Synchronous Transmission............... 28
V
VDD...................................................................................... 11
W
WWW, On-Line Support ....................................................... 2
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 39
PIC17LC75X-16/PTL16
NOTES:
DS30176A-page 40
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
981103
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries. FlexROM, MPLAB and fuzzy-
LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
1999 Microchip Technology Inc.
Preliminary
DS30176A-page41
PIC17LC75X-16/PTL16
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
Reader Response
Total Pages Sent
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS30176A
Device:
PIC17LC75X-16/PTL16
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30176A-page42
Preliminary
1999 Microchip Technology Inc.
PIC17LC75X-16/PTL16
PIC17LC75X-16/PTL16 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Maximum
Frequency
Ordering Number
PIC17LC756A-16/PTL16
Package
Temperature
Other
16MHz
16MHz
16MHz
16MHz
64-TQFP
64-TQFP
64-TQFP
64-TQFP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIC17LC752-16/PTL16
PIC17LC756AT-16/PTL16
PIC17LC752T-16/PTL16
Tape and Reel
Tape and Reel
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS30176A-page 43
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
Microchip Technology Inc.
Microchip Technology Singapore Pte Ltd.
200 Middle Road
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
相关型号：
PIC17LC756T-08/PT
8-BIT, OTPROM, 8 MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, PLASTIC, TQFP-64
MICROCHIP
©2020 ICPDF网 联系我们和版权申明