PIC18C601I/PT [MICROCHIP]
High-Performance ROM-less Microcontrollers with External Memory Bus; 高性能ROM少微控制器与外部存储器总线
| 型号： | PIC18C601I/PT |
| 厂家： | 
MICROCHIP |
| 描述： | High-Performance ROM-less Microcontrollers with External Memory Bus |
| 文件： | 总320页 (文件大小：5367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18C601/801
High-Performance ROM-less Microcontrollers
with External Memory Bus
High Performance RISC CPU:
Advanced Analog Features:
• 10-bit Analog-to-Digital Converter module (A/D)
with:
• C compiler optimized architecture instruction set
• Linear program memory addressing up to 2 Mbytes
• Linear data memory addressing to 4 Kbytes
-
-
-
-
Fast sampling rate
Conversion available during SLEEP
DNL = ±1 LSb, INL = ±1 LSb
Up to 12 channels available
External Program Memory
On-Chip
On-Chip
• Programmable Low Voltage Detection (LVD)
module
Device
Maximum
Maximum
RAM (bytes)
Addressing Single Word
-
Supports interrupt on Low Voltage Detection
(bytes)
Instructions
PIC18C601
PIC18C801
256K
2M
128K
1M
1.5K
1.5K
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT),
and Oscillator Start-up Timer (OST)
• Up to 160 ns instruction cycle:
- DC - 25 MHz clock input
- 4 MHz - 6 MHz clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• Watchdog Timer (WDT) with its own on-chip RC
oscillator
• On-chip Boot RAM for boot loader application
• 8-bit or 16-bit external memory interface modes
• 8 x 8 Single Cycle Hardware Multiplier
• Up to two software programmable chip select sig-
nals (CS1 and CS2)
Peripheral Features:
• One programmable chip I/O select signal (CSIO)
for memory mapped I/O expansion
• High current sink/source 25 mA/25 mA
• Up to 47 I/O pins with individual direction control
• Three external interrupt pins
• Power saving SLEEP mode
• Different oscillator options, including:
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• Timer1 module: 16-bit timer/counter (time-base for
CCP)
CMOS Technology:
• Timer2 module: 8-bit timer/counter with 8-bit
period register
• Low power, high speed CMOS technology
• Fully static design
• Timer3 module: 16-bit timer/counter
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules
CCP pins can be configured as:
- Capture input: 16-bit, max. resolution 10 ns
- Compare is 16-bit, max. resolution 160 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit
Max. PWM freq. @:
8-bit resolution = 99 kHz
10-bit resolution = 24.4 kHz
• Master Synchronous Serial Port (MSSP) with two
modes of operation:
- 3-wire SPI™ (Supports all 4 SPI modes)
- I2C™ Master and Slave mode
• Addressable USART module: Supports Interrupt
on Address bit
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 1
PIC18C601/801
Pin Diagrams
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
VSS
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
2
3
4
5
6
RB5
7
RB6
8
VSS
PIC18C601
9
OSC2/CLKO
OSC1/CLKI
VDD
10
11
12
13
14
15
16
VDD
RF7/UB
RF6/LB
RB7
RF5/CS1
RF4/A16
RF3/CSIO
RF2/AN7
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS39541A-page 2
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Pin Diagrams (Cont.’d)
68-Pin PLCC
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
60
59
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
NC
12
13
14
15
16
17
18
19
20
21
58
57
56
55
54
53
52
51
50
49
RB5
RB6
VSS
PIC18C601
NC
VSS
VDD
OSC2/CLKO
OSC1/CLKI
VDD
RF7/UB
RF6/LB
22
23
24
25
26
48
47
46
45
44
RB7
RF5/CS1
RF4/A16
RF3/CSIO
RF2/AN7
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 3
PIC18C601/801
Pin Diagrams (Cont.’d)
80-Pin TQFP
80 79 78
77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RH2/A18
RJ5/D5
2
RH3/A19
RJ4/D4
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
3
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
VSS
4
5
6
7
RB5
8
RB6
9
VSS
10
11
12
13
14
15
16
17
18
19
20
OSC2/CLKO
OSC1/CLKI
VDD
PIC18C801
VDD
RF7/UB
RB7
RF6/LB
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RF5/CS1
RF4/CS2
RF3/CSIO
RF2/AN7
RJ3/D3
RJ2/D2
RH4/AN8
RH5/AN9
40
35 36 37 38 39
21 22 23 24 25 26 27 28 29 30 31 32 33 34
DS39541A-page 4
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Pin Diagrams (Cont.’d)
84-Pin PLCC
83 82 81
84
80
75
797877 76
11 10 9 8
7
6
5
4 3
2
1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RH2/A18
RH3/A19
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
NC
RJ5/D5
RJ4/D4
RB0/INT0
74
73
72
71
70
69
68
67
66
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
65
64
63
62
61
VSS
NC
PIC18C801
VSS
VDD
OSC2/CLKO
OSC1/CLKI
VDD
RF7/UB
RF6/LB
60
59
RB7
RF5/CS1
RF4/CS2
RF3/CSIO
RF2/AN7
RH4/AN8
RH5/AN9
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
58
57
56
55
54
RJ3/D3
RJ2/D2
3435 36 37 38 39 40 41 42 43
33
44
45 46
48 49
51
50
47
52 53
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 5
PIC18C601/801
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
Device Overview..................................................................................................................................................9
Oscillator Configurations....................................................................................................................................21
RESET...............................................................................................................................................................29
Memory Organization ........................................................................................................................................39
External Memory Interface.................................................................................................................................63
Table Reads/Table Writes .................................................................................................................................73
8 X 8 Hardware Multiplier ..................................................................................................................................85
Interrupts............................................................................................................................................................89
I/O Ports...........................................................................................................................................................103
10.0 Timer0 Module.................................................................................................................................................127
11.0 Timer1 Module.................................................................................................................................................130
12.0 Timer2 Module.................................................................................................................................................135
13.0 Timer3 Module.................................................................................................................................................137
14.0 Capture/Compare/PWM (CCP) Modules.........................................................................................................141
15.0 Master Synchronous Serial Port (MSSP) Module............................................................................................149
16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).....................................177
17.0 10-bit Analog-to-Digital Converter (A/D) Module .............................................................................................193
18.0 Low Voltage Detect..........................................................................................................................................203
19.0 Special Features of the CPU ...........................................................................................................................207
20.0 Instruction Set Summary .................................................................................................................................215
21.0 Development Support......................................................................................................................................259
22.0 Electrical Characteristics .................................................................................................................................265
23.0 DC and AC Characteristics Graphs and Tables ..............................................................................................295
24.0 Packaging Information.....................................................................................................................................297
Appendix A: Data Sheet Revision History..................................................................................................................303
Appendix B: Device Differences ................................................................................................................................303
Appendix C: Device Migrations..................................................................................................................................304
Appendix D: Migrating from other PICmicro Devices.................................................................................................304
Appendix E: Development Tool Version Requirements.............................................................................................305
Index ...........................................................................................................................................................................307
On-Line Support..........................................................................................................................................................315
Reader Response .......................................................................................................................................................316
Product Identification System......................................................................................................................................317
DS39541A-page 6
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
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2001 Microchip Technology Inc.
Advance Information
DS39541A-page 7
PIC18C601/801
NOTES:
DS39541A-page 8
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
An overview of features is shown in Table 1-1.
1.0
DEVICE OVERVIEW
Device block diagrams are provided in Figure 1-1 for
the 64/68-pin configuration, and Figure 1-2 for the 80/
84-pin configuration. The pinouts for both packages
are listed in Table 1-2.
This document contains device specific information for
the following two devices:
1. PIC18C601
2. PIC18C801
The PIC18C601 is available in 64-pin TQFP and 68-pin
PLCC packages. The PIC18C801 is available in 80-pin
TQFP and 84-pin PLCC packages.
TABLE 1-1:
DEVICE FEATURES
Features
PIC18C601
PIC18C801
Operating Frequency
DC - 25 MHz
256K
DC - 25 MHz
Bytes
2M
1M
External
Program Memory
Max. # of Single Word
Instructions
128K
Data Memory (Bytes)
Interrupt Sources
I/O Ports
1536
1536
15
15
Ports A - G
Ports A - H, J
Timers
4
2
4
2
Capture/Compare/PWM modules
MSSP,
Addressable USART
MSSP,
Addressable USART
Serial Communications
10-bit Analog-to-Digital Module
8 input channels
12 input channels
POR,
POR,
RESETS (and Delays)
RESETInstruction, Stack Full,
RESETInstruction, Stack Full,
Stack Underflow (PWRT, OST) Stack Underflow (PWRT, OST)
Programmable Low Voltage Detect
8-bit External Memory Interface
Yes
Yes
No
Yes
Yes
Yes
8-bit De-multiplexed External
Memory Interface
16-bit External Memory Interfaces
On-chip Chip Select Signals
On-chip I/O Chip Select Signal
Instruction Set
Yes
CS1
Yes
CS1, CS2
Yes
Yes
75 Instructions
75 Instructions
64-pin TQFP
68-pin PLCC
80-pin TQFP
84-pin PLCC
Packages
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 9
PIC18C601/801
FIGURE 1-1:
PIC18C601 BLOCK DIAGRAM
Data Bus<8>
PORTA
PORTB
AD7:AD0
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Table Pointer<21>
inc/dec logic
20
Data Latch
8
5
8
Data RAM
1 Kbyte
21
RA5/AN4/SS/LVDIN
21
21
Address Latch
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
RB7
PCLATU
PCLATH
12
Address<12>
PCH PCL
PCU
Program Counter
Address Latch
4
BSR
12
FSR0
4
Bank0,F
Program Memory
(up to 256 Kbytes)
FSR1
FSR2
31 Level Stack
Data Latch
16
12
PORTC
inc/dec
logic
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
Decode
Table Latch
8
ROM Latch
IR
RC6/TX1/CK1
RC7/RX1/DT1
A16, AD15:AD8
PORTD
PORTE
PORTF
8
Instruction
Decode &
Control
RD7:RD0/AD7:AD0
RE7:RE0/AD15:AD8
PRODH PRODL
8 x 8 Multiply
OSC2/CLKO
OSC1/CLKI
3
Power-up
Timer
8
Timing
Generation
Oscillator
Start-upTimer
T1OSI
T1OSO
WREG
8
BITOP
8
8
Power-on
Reset
8
Watchdog
Timer
ALU<8>
Low Voltage
Detect
8
RF0/AN5
RF1/AN6
RF2/AN7
RF3/CSIO
RF4/A16
RF5/CS1
RF6/LB
MCLR
VDD, VSS
RF7/UB
PORTG
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
RG4/BA0
Timer0
CCP1
Timer1
CCP2
Timer2
Timer3
Synchronous
Serial Port
USART1
10-bit A/D
DS39541A-page 10
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 1-2:
PIC18C801 BLOCK DIAGRAM
Data Bus<8>
PORTA
AD7:AD0
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
TablePointer<21>
Data Latch
8
5
8
Data RAM
1 Kbyte
21
RA5/AN4/SS/LVDIN
inc/dec logic
20
21
21
PORTB
Address Latch
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
RB7
PCLATU
PCLATH
12
Address<12>
PCH PCL
PCU
Program Counter
Address Latch
4
BSR
12
FSR0
4
Program Memory
(up to 2 Mbytes)
Bank0,F
FSR1
FSR2
31 Level Stack
Data Latch
16
12
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
inc/dec
logic
Decode
Table Latch
RC3/SCK/SCL
RC4/SDI/SDA
8
ROM Latch
IR
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
PORTD
A19:A16, AD15:AD0
8
Instruction
Decode &
Control
RD7:RD0/AD7:AD0
PRODH PRODL
8 x 8 Multiply
OSC2/CLKO
OSC1/CLKI
3
PORTE
Power-up
Timer
8
Timing
Generation
RE7:RE0/AD15:AD8
Oscillator
Start-upTimer
T1OSI
T1OSO
WREG
8
BITOP
8
8
Power-on
Reset
PORTF
8
Watchdog
Timer
RF0/AN5
RF1/AN6
RF2/AN7
RF3/CSIO
RF4/CS2
RF5/CS1
ALU<8>
Low Voltage
Detect
8
RF6/LB
RF7/UB
MCLR
VDD, VSS
PORTG
PORTH
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
RG4/BA0
Timer0
CCP1
Timer1
CCP2
Timer2
Timer3
RH3:RH0/A19:A16
RH4/AN8
RH5/AN9
RH6/AN10
RH7/AN11
Synchronous
Serial Port
PORTJ
USART1
RJ7:RJ0/D7:D0
10-bit A/D
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 11
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS
Pin Number
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
MCLR/VPP
MCLR
7
16
9
20
I
ST
—
Master clear (RESET) input. This pin is
an active low RESET to the device.
Programming voltage input.
VPP
NC
P
—
1, 18,
35, 52
—
1, 22,
43, 64
—
These pins should be left
unconnected.
OSC1/CLKI
OSC1
39
50
49
62
I
I
CMOS/ST
Oscillator crystal input or external clock
source input. ST buffer when in RC
mode. Otherwise CMOS.
External clock source input.
Always associated with pin function
OSC1 (see OSC1/CLKI, OSC2/CLKO
pins).
CLKI
CMOS
OSC2/CLKO
OSC2
40
51
50
63
O
O
—
—
Oscillator crystal output.
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the
CLKO
frequency of OSC1 and denotes the
instruction cycle rate.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS39541A-page 12
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18C601
PIC18C801
TQFP PLCC TQFP PLCC
Description
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
24
23
22
34
33
32
30
29
28
42
41
40
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (Low) input.
RA3/AN3/VREF+
RA3
21
28
27
31
39
38
27
34
33
39
47
46
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
AN3
VREF+
RA4/T0CKI
RA4
I/O
I
ST/OD
ST
Digital I/O – Open drain when
configured as output.
Timer0 external clock input.
T0CKI
RA5/AN4/SS/LVDIN
RA5
AN4
SS
I/O
TTL
Analog
ST
Digital I/O.
Analog input 4.
SPI slave select input.
Low voltage detect input.
I
I
I
LVDIN
Analog
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 13
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTB is a bi-directional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.
RB0/INT0
RB0
48
47
46
45
60
59
58
57
58
57
56
55
72
71
70
69
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/CCP2
RB3
I/O
I/O
TTL
ST
Digital I/O.
Capture2 input, Compare2 output,
PWM2 output.
CCP2
RB4
RB5
RB6
44
43
42
56
55
54
54
53
52
68
67
66
I/O
I/O
TTL
TTL
Digital I/O, Interrupt-on-change pin.
Digital I/O, Interrupt-on-change pin.
I/O
I
TTL
ST
Digital I/O, Interrupt-on-change pin.
ICSP programming clock.
RB7
37
48
47
60
I/O
I/O
TTL
ST
Digital I/O, Interrupt-on-change pin.
ICSP programming data.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS39541A-page 14
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18C601
PIC18C801
TQFP PLCC TQFP PLCC
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T13CKI
RC0
30
41
36
49
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI
RC1
29
33
40
44
35
43
48
56
I/O
I
ST
CMOS
Digital I/O.
Timer1 oscillator input.
T1OSI
RC2/CCP1
RC2
I/O
I/O
ST
ST
Digital I/O.
Capture1 input/Compare1
output/PWM1 output.
CCP1
RC3/SCK/SCL
RC3
34
35
45
46
44
45
57
58
I/O
I/O
ST
ST
Digital I/O.
SCK
Synchronous serial clock
input/output for SPI mode.
Synchronous serial clock
SCL
I/O
ST
2
input/output for I C mode.
RC4/SDI/SDA
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
SDI
SDA
2
I C data I/O.
RC5/SDO
RC5
36
31
47
42
46
37
59
50
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
ST
—
ST
Digital I/O.
USART asynchronous transmit.
USART synchronous clock.
RC7/RX/DT
32
43
38
51
RC7
RX
DT
I/O
I
I/O
ST
ST
ST
Digital I/O.
USART asynchronous receive.
USART synchronous data.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 15
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTD is a bi-directional I/O port. These
pins have TTL input buffers when external
memory is enabled.
RD0/AD0
RD0
58
55
54
53
52
51
50
49
3
72
69
68
67
66
65
64
63
3
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 0.
AD0
RD1/AD1
RD1
67
66
65
64
63
62
61
83
82
81
80
79
78
77
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 1.
AD1
RD2/AD2
RD2
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 2.
AD2
RD3/AD3
RD3
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 3.
AD3
RD4/AD4
RD4
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 4.
AD4
RD5/AD5
RD5
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 5.
AD5
RD6/AD6
RD6
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 6.
AD6
RD7/AD7
RD7
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 7.
AD7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS39541A-page 16
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18C601
PIC18C801
TQFP PLCC TQFP PLCC
Description
PORTE is a bi-directional I/O port.
RE0/AD8
RE0
2
11
10
9
4
15
14
9
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 8.
AD8
RE1/AD9
RE1
1
3
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 9.
AD9
RE2/AD10
RE2
64
63
62
61
60
59
78
77
76
75
74
73
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 10.
AD10
RE3/AD11
RE3
8
8
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 11.
AD11
RE4/AD12
RE4
7
7
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 12.
AD12
RE5/AD13
RE5
6
6
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 13.
AD13
RE6/AD14
RE6
5
5
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 14.
AD14
RE7/AD15
RE7
4
4
I/O
I/O
ST
ST
Digital I/O.
External memory address/data 15.
AD15
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 17
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTF is a bi-directional I/O port.
RF0/AN5
RF0
18
17
16
15
28
27
26
25
24
23
18
17
36
35
30
29
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
AN5
RF1/AN6
RF1
I/O
I
ST
Analog
Digital I/O.
Analog input 6.
AN6
RF2/AN7
RF2
I/O
I
ST
Analog
Digital I/O.
Analog input 7.
AN7
RF3/CSIO
RF3
I/O
I/O
ST
ST
Digital I/O.
System bus chip select I/O.
CSIO
RF4/A16
RF4/CS2
RF4
14
—
24
—
—
16
—
28
I/O
I/O
O
ST
TTL
TTL
Digital I/O.
External memory address 16.
Chip select 2.
A16
CS2
RF5/CS1
RF5
13
12
23
22
15
14
27
26
I/O
O
ST
TTL
Digital I/O.
Chip select 1.
CS1
RF6/LB
RF6
I/O
O
ST
TTL
Digital I/O.
Low byte select signal for external
memory interface.
LB
RF7/UB
RF7
11
21
13
25
I/O
O
ST
TTL
Digital I/O.
High byte select signal for external
memory interface.
UB
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS39541A-page 18
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18C601
PIC18C801
TQFP PLCC TQFP PLCC
Description
PORTG is a bi-directional I/O port.
RG0/ALE
RG0
3
4
5
6
8
12
13
14
15
17
5
6
16
17
18
19
21
I/O
O
ST
TTL
Digital I/O.
Address Latch Enable.
ALE
RG1/OE
RG1
I/O
O
ST
TTL
Digital I/O.
Output Enable.
OE
RG2/WRL
RG2
7
I/O
O
ST
TTL
Digital I/O.
Write Low control.
WRL
RG3/WRH
RG3
8
I/O
O
ST
TTL
Digital I/O.
Write High control.
WRH
RG4/BA0
RG4
10
I/O
O
ST
TTL
Digital I/O.
System bus byte address 0.
BA0
PORTH is a bi-directional I/O port.
RH0/A16
RH0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
79
80
1
10
11
12
13
31
32
33
34
I/O
O
ST
TTL
Digital I/O.
External memory address 16.
A16
RH1/A17
RH1
I/O
O
ST
—
Digital I/O.
External memory address 17.
A17
RH2/A18
RH2
I/O
O
ST
—
Digital I/O.
External memory address 18.
A18
RH3/A19
RH3
2
I/O
O
ST
—
Digital I/O.
External memory address 19.
A19
RH4/AN8
RH4
19
20
21
22
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RH5/AN9
RH5
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RH6/AN10
RH6
I/O
I
ST
Analog
Digital I/O.
Analog input 10.
AN10
RH7/AN11
RH7
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 19
PIC18C601/801
TABLE 1-2:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTJ is a bi-directional I/O port.
RJ0/D0
RJ0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
39
40
41
42
59
60
61
62
52
53
54
55
73
74
75
76
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 0.
D0
RJ1/D1
RJ1
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 1.
D1
RJ2/D2
RJ2
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 2.
D2
RJ3/D3
RJ3
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 3.
D3
RJ4/D4
RJ4
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 4.
D4
RJ5/D5
RJ5
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 5.
D5
RJ6/D6
RJ6
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 6.
D6
RJ7/D7
RJ7
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 7.
D7
VSS
VDD
9, 25, 19, 36, 11,31, 23, 44,
41, 56 53, 68 51, 70 65, 84
P
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
10,26, 2, 20, 12,32, 2, 24,
38, 57 37, 49 48, 71 45, 61
P
—
AVSS
AVDD
20
19
30
29
26
25
38
37
P
P
—
—
Ground reference for analog modules.
Positive supply for analog modules.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS39541A-page 20
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR LP OSC
2.0
2.1
OSCILLATOR
CONFIGURATIONS
CONFIGURATION)
Oscillator Types
(1)
PIC18C601/801 can be operated in one of four oscilla-
tor modes, programmable by configuration bits
FOSC1:FOSC0 in CONFIG1H register:
C1
OSC1
To
Internal
Logic
XTAL
(3)
1. LP
2. HS
3. RC
4. EC
Low Power Crystal
RF
High Speed Crystal/Resonator
External Resistor/Capacitor
External Clock
SLEEP
PIC18C601/801
(2)
RS
(1)
C2
OSC2
Note 1: See Table 2-1 and Table 2-2 for recom-
2.2
Crystal Oscillator/Ceramic
Resonators
mended values of C1 and C2.
2: A series resistor (RS) may be required for AT
In LP or HS oscillator modes, a crystal or ceramic res-
onator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 2-1 shows the pin connec-
tions. An external clock source may also be connected
to the OSC1 pin, as shown in Figure 2-3 and Figure 2-4.
strip cut crystals.
3: RF varies with the crystal chosen.
PIC18C601/801 oscillator design requires the use of a
parallel cut crystal.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 21
PIC18C601/801
TABLE 2-1:
CERAMIC RESONATORS
Ranges Tested:
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
Mode
Freq.
8.0 MHz
16.0 MHz
20.0 MHz
25.0 MHz
OSC1
OSC2
HS
10 - 68 pF
10 - 22 pF
TBD
10 - 68 pF
10 - 22 pF
TBD
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
4: Rs may be required in HS mode to avoid
overdriving crystals with low drive level
specification.
TBD
TBD
HS+PLL 4.0 MHz
TBD
TBD
These values are for design guidance only.
See notes on this page.
Resonators Used:
4.0 MHz Murata Erie CSA4.00MG
8.0 MHz Murata Erie CSA8.00MT
16.0 MHz Murata Erie CSA16.00MX
0.5%
0.5%
0.5%
2.3
RC Oscillator
For timing insensitive applications, the "RC" oscillator
mode offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 2-2 shows how the RC combination
is connected.
All resonators used did not have built-in capacitors.
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Crystal
Freq.
Cap. Range Cap.Range
Osc Type
C1
C2
LP
32.0 kHz
200 kHz
4.0 MHz
8.0 MHz
20.0 MHz
25.0 MHz
4.0 MHz
33 pF
15 pF
33 pF
15 pF
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
HS
15 pF
15 pF
15-33 pF
15-33 pF
TBD
15-33 pF
15-33 pF
TBD
FIGURE 2-2:
RC OSCILLATOR MODE
HS+PLL
15 pF
15 pF
These values are for design guidance only.
See notes on this page.
VDD
Crystals Used
REXT
Internal
OSC1
32.0 kHz Epson C-001R32.768K-A
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
Clock
200 kHz
1.0 MHz
4.0 MHz
STD XTL 200.000kHz
ECS ECS-10-13-1
ECS ECS-40-20-1
CEXT
VSS
PIC18C601/801
OSC2/CLKO
FOSC/4
or I/O
8.0 MHz EPSON CA-301 8.000M-C ± 30 PPM
20.0 MHz EPSON CA-301 20.000M-C ± 30 PPM
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
DS39541A-page 22
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
2.4
External Clock Input
2.5
HS4 (PLL)
The EC oscillator mode requires an external clock
source to be connected to the OSC1 pin. The feedback
device between OSC1 and OSC2 is turned off in these
modes to save current. There is no oscillator start-up
time required after a Power-on Reset or after a
recovery from SLEEP mode.
A Phase Lock Loop (PLL) circuit is provided as a soft-
ware programmable option for users that want to multi-
ply the frequency of the incoming crystal oscillator
signal by 4. For an input clock frequency of 6 MHz, the
internal clock frequency will be multiplied to 24 MHz.
This is useful for customers who are concerned with
EMI due to high frequency crystals.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
oscillator mode.
The PLL is enabled by configuring HS oscillator mode
and setting the PLLEN bit in the OSCON register. If HS
oscillator mode is not selected, or PLLEN bit in
OSCCON register is clear, the PLL is not enabled and
the system clock will come directly from OSC1. HS
oscillator mode is the default for PIC18C601/801. In all
other modes, the PLLEN bit and the SCS1 bit are
forced to ‘0’.
FIGURE 2-3:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out, referred to as TPLL.
OSC1
Clock from
ext. system
PIC18C601/801
OSC2
FOSC/4
FIGURE 2-4:
PLL BLOCK DIAGRAM
HS Osc
PLL Enable
OSCOUT
Phase
Comparator
CVCO
FIN
Crystal
Loop
Filter
VCO
Osc
FOUT
OSCIN
SYSCLK
Feedback Divider
3
2
1
0
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 23
PIC18C601/801
2.6.1
SYSTEM CLOCK SWITCH BIT
2.6
Oscillator Switching Feature
The system clock source switching is performed under
software control. The system clock switch bit, SCS0
(OSCCON register), controls the clock switching. When
the SCS0 bit is ’0’, the system clock source comes from
the main oscillator, selected by the FOSC2:FOSC0 con-
figuration bits in CONFIG1H register. When the SCS0 bit
is set, the system clock source will come from the Timer1
oscillator. The SCS0 bit is cleared on all forms of RESET.
PIC18C601/801 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For PIC18C601/801 devices, this alternate clock
source is the Timer1 oscillator. If a low frequency crys-
tal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low power
execution mode. Figure 2-5 shows a block diagram of
the system clock sources.
Note: The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 control register
(T1CON). If the Timer1 oscillator is not
enabled, any write to the SCS0 bit will be
ignored (SCS0 bit forced cleared) and the
main oscillator will continue to be the sys-
tem clock source.
FIGURE 2-5:
DEVICE CLOCK SOURCES
PIC18C601/801
Main Oscillator
OSC2
TOSC/4
4 x PLL
SLEEP
TSCLK
TOSC
TT1P
OSC1
Timer 1 Oscillator
T1OSO
Clock
Source
T1OSCEN
Enable
Oscillator
T1OSI
Clock Source option
for other modules
Note: I/O pins have diode protection to VDD and VSS.
DS39541A-page 24
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
REGISTER 2-1:
OSCCON REGISTER
U-0
U-0
U-0
U-0
R/W-0
LOCK
R/W-0
R/W-0
SCS1
R/W-0
SCS0
—
—
—
—
PLLEN
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as '0'
LOCK: Phase Lock Loop Lock Status bit
1= Phase Lock Loop output is stable as system clock
0= Phase Lock Loop output is not stable and cannot be used as system clock
bit 2
bit 1
PLLEN: Phase Lock Loop Enable bit
1= Enable Phase Lock Loop output as system clock
0= Disable Phase Lock Loop
SCS1: System Clock Switch bit 1
When PLLEN and LOCK bit are set:
1= Use PLL output
0= Use primary oscillator/clock input pin
When PLLEN bit or LOCK bit is cleared:
Bit is forced clear
bit 0
SCS0: System Clock Switch bit 0
When T1OSCEN bit is set:
1= Switch to Timer1 oscillator/clock pin
0= Use primary oscillator/clock input pin
When T1OSCEN is cleared:
Bit is forced clear
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
2.6.2
OSCILLATOR TRANSITIONS
PIC18C601/801 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.
If the main oscillator is configured for an external crys-
tal (HS, LP), the transition will take place after an oscil-
lator start-up time (TOST) has occurred. A timing
diagram indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS and LP modes is
shown in Figure 2-7.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-6.
The Timer1 oscillator is assumed to be running all the
time. After the SCS0 bit is set, the processor is frozen
at the next occurring Q1 cycle. After eight synchroniza-
tion cycles are counted from the Timer1 oscillator, oper-
ation resumes. No additional delays are required after
the synchronization cycles.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 25
PIC18C601/801
FIGURE 2-6:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
TT1P
1
2
3
4
5
6
7
8
T1OSI
OSC1
TSCS
TOSC
Internal
System
Clock
TDLY
SCS0
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note: Delay on internal system clock is eight oscillator cycles for synchronization.
FIGURE 2-7:
TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, LP)
Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q3
Q4
Q1
TT1P
T1OSI
OSC1
1
2
3
4
5
6
7
8
TOST
TSCS
OSC2
Internal System
Clock
TOSC
SCS0
(OSCCON<0>)
Program Counter
PC + 2
PC + 4
PC
Note: TOST = 1024TOSC (drawing not to scale).
DS39541A-page 26
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
If the main oscillator is configured for HS4 (PLL) mode
with SCS1 bit set to ‘1’, an oscillator start-up time
(TOST), plus an additional PLL time-out (TPLL) will
occur. The PLL time-out is typically 2 ms and allows the
PLL to lock to the main oscillator frequency. A timing
diagram indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS4 mode is shown in
Figure 2-8.
put is not used, so the system oscillator will come from
OSC1 directly and additional delay of TPLL is not
required. A timing diagram indicating the transition from
the Timer1 oscillator to the main oscillator for HS4
mode is shown in Figure 2-9.
If the main oscillator is configured in the RC or EC
modes, there is no oscillator start-up time-out. Opera-
tion will resume after eight cycles of the main oscillator
have been counted. A timing diagram indicating the
transition from the Timer1 oscillator to the main oscilla-
tor for RC and EC modes is shown in Figure 2-10.
If the main oscillator is configured for HS4 (PLL) mode,
with SCS1 bit set to ‘0’, only oscillator start-up time
(TOST) will occur. Since SCS1 bit is set to ‘0’, PLL out-
FIGURE 2-8:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS1 = 1)
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4
Q1
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
7
8
Internal System
Clock
SCS0
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 4
Note: TOST = 1024TOSC (drawing not to scale).
FIGURE 2-9:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS = 0)
Q1
Q2
Q3
Q4
Q1
Q2
TT1P
Q4
Q1
T1OSI
OSC1
TOSC
TOST
OSC2
TSCS
PLL
Clock
Output
TPLL
Internal
System
Clock
TDLY
SCS0
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note: TOST = 1024TOSC (drawing not to scale).
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 27
PIC18C601/801
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
TT1P
T1OSI
OSC1
TOSC
6
1
4
5
7
8
2
3
OSC2
Internal System
Clock
SCS0
(OSCCON<0>)
TSCS
Program Counter
PC
PC + 2
PC + 4
Note: RC oscillator mode assumed.
rent consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
2.6.3
SCS0, SCS1 PRIORITY
If both SCS0 and SCS1 are set to ‘1’ simultaneously,
the SCS0 bit has priority over the SCS1 bit. This means
that the low power option will take precedence over the
PLL option. If both bits are cleared simultaneously, the
system clock will come from OSC1, after a TOST time-
out. If only the SCS0 bit is cleared, the system clock will
come from the PLL output, following TOST and TPLL
time.
2.8
Power-up Delays
Power-up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see Section 3.0 RESET.
TABLE 2-3:
SCS0, SCS1 PRIORITY
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of TPWRT (parameter
#33) on power-up only. The second timer is the Oscil-
lator Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable.
SCS1
SCS0 Clock Source
0
0
1
1
0
1
0
1
Ext Oscillator OSC1
Timer1 Oscillator
HS + PLL
Timer1 Oscillator
PIC18C601/801 devices provide a configuration bit,
PWRTEN in CONFIG2L register, to enable or disable
the Power-up Timer. By default, the Power-up Timer is
enabled.
2.7
Effects of SLEEP Mode on the
On-Chip Oscillator
With the PLL enabled (HS4 oscillator mode), the time-out
sequence following a Power-on Reset is different from
other oscillator modes. The time-out sequence is as fol-
lows: the PWRT time-out is invoked after a POR time
delay has expired, then, the Oscillator Start-up Timer
(OST) is invoked. However, this is still not a sufficient
amount of time to allow the PLL to lock at high frequen-
cies. The PWRT timer is used to provide an additional
time-out, called TPLL (parameter #7), to allow the PLL
ample time to lock to the incoming clock frequency.
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP, will increase the cur-
TABLE 2-4:
OSC Mode
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC2 Pin
RC
EC
Floating, external resistor should pull high
Floating
At logic low
At logic low
LP and HS Feedback inverter disabled, at quiescent voltage level Feedback inverter disabled, at quiescent voltage level
Note: See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
DS39541A-page 28
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD
and POR, are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
3.0
RESET
PIC18C601/801 devices differentiate between various
kinds of RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset during normal
operation
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 3-1.
e) RESETInstruction
f) Stack Full Reset
PIC18C601/801 has a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
g) Stack Underflow Reset
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET”
state on Power-on Reset, MCLR, WDT Reset, MCLR
Reset during SLEEP, and by the RESETinstruction.
A WDT Reset does not drive MCLR pin low.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
External Reset
Stack
Pointer
MCLR
SLEEP
WDT
Time-out
Reset
WDT
Module
VDD Rise
Detect
Power-on Reset
VDD
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
Q
R
OSC1
PWRT
On-chip
10-bit Ripple Counter
(1)
RC OSC
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 29
PIC18C601/801
3.1
Power-on Reset (POR)
3.3
Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected. To take advantage of the POR cir-
cuitry, connect the MCLR pin directly (or through a
resistor) to VDD. This will eliminate external RC compo-
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified (param-
eter D004). For a slow rise time, see Figure 3-2.
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for LP, HS and HS4
modes and only on Power-on Reset or wake-up from
SLEEP.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met. Power-on Reset may be used to meet
the voltage start-up condition.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 1 ms and follows the oscillator start-
up time-out (OST).
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
3.5
Time-out Sequence
VDD
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired; then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
D
R
R1
MCLR
PIC18C601/801
C
Note 1: External Power-on Reset circuit is required only
if the VDD power-up slope is too slow. The diode
D helps discharge the capacitor quickly when
VDD powers down.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18C601/801 device
operating in parallel.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current flowing
into MCLR from external capacitor C, in the
event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all registers.
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT time delay allows VDD to rise to an
acceptable level. PIC18C601/801 devices are avail-
able with PWRT enabled or disabled.
The power-up time delay will vary from chip to chip, due
to VDD, temperature and process variation. See DC
parameter #33 for details.
DS39541A-page 30
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 3-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Wake-up from
SLEEP or
Oscillator
Configuration
Oscillator Switch(1)
PWRTEN = 0
PWRTEN = 1
HS with PLL enabled(1)
72 ms + 1024TOSC
72 ms + 1024TOSC
72 ms
1024TOSC
1024TOSC
—
1024TOSC + 1 ms
HS, LP
EC
External RC
1024TOSC
—
—
72 ms
—
Note 1: 1 ms is the nominal time required for the 4X PLL to lock. Maximum time is 2 ms.
2: 72 ms is the nominal Power-up Timer delay.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
U-0
r
U-0
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-1
POR
U-0
r
—
bit 7
bit 0
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE, AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD
POR STKFUL STKUNF
00000h
00000h
0r-1 110r
0r-u uuur
1
u
1
u
1
u
0
u
u
u
u
u
Power-on Reset
MCLR Reset during normal
operation
00000h
00000h
00000h
0r-0 uuur
0r-u uu1r
0r-u uu1r
0
u
u
u
u
u
u
u
u
u
1
1
u
u
1
u
1
u
Software Reset during normal
operation
Stack Full Reset during normal
operation
Stack Underflow Reset during normal
operation
00000h
00000h
PC + 2
0r-u 10ur
0r-u 01ur
ur-u 00ur
ur-u 00ur
u
u
u
u
1
0
0
0
0
1
0
0
u
u
u
u
u
u
u
u
u
u
u
u
MCLR Reset during SLEEP
WDT Reset
WDT Wake-up
Interrupt wake-up from SLEEP
PC + 2(1)
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0', r= reserved, maintain ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (000008h or 000018h).
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 31
PIC18C601/801
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
DS39541A-page 32
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TDEADTIME
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 33
PIC18C601/801
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Reset
WDT Reset
Reset Instruction
Stack Over/Underflow Reset
Applicable
Devices
Wake-up via WDT or
Interrupt
Register
Power-on Reset
TOSU
TOSH
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
(Note 5)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
(Note 5)
---u uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
(Note 5)
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
---- 0000
xxxx xxxx
xxxx xxxx
(Note 5)
---- 0000
uuuu uuuu
uuuu uuuu
(Note 5)
---- uuuu
uuuu uuuu
uuuu uuuu
(Note 5)
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
---- 0000
xxxx xxxx
---- 0000
(Note 5)
---- 0000
uuuu uuuu
---- 0000
(Note 5)
---- uuuu
uuuu uuuu
---- uuuu
(Note 5)
FSR1L
BSR
INDF2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain ‘0’
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (00008h or 00018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are
updated with the current value of the PC. The SKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: This is not a physical register. It is an indirect pointer that addresses another register. The contents
returned is the value contained in the addressed register.
DS39541A-page 34
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Applicable
Devices
Wake-up via WDT or
Interrupt
Power-on Reset
Reset Instruction
Stack Over/Underflow Reset
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
---- 0000
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
1111 1111
--00 0-00
--00 0101
---- 1111
0r-1 11qr
xxxx xxxx
xxxx xxxx
0-00 0000
xxxx xxxx
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
-000 0000
0--- -000
xxxx xxxx
xxxx xxxx
--00 0000
---- 0000
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
1111 1111
--uu u-u0
--00 0101
---- uuuu
0r-1 qqur
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
-000 0000
0--- -000
uuuu uuuu
uuuu uuuu
--00 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu u-uu
--uu uuuu
---- uuuu
ur-u qqur
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
-uuu uuuu
u--- -uuu
uuuu uuuu
uuuu uuuu
--uu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain ‘0’
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (00008h or 00018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are
updated with the current value of the PC. The SKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: This is not a physical register. It is an indirect pointer that addresses another register. The contents
returned is the value contained in the addressed register.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 35
PIC18C601/801
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Reset Instruction
Stack Over/Underflow Reset
Applicable
Devices
Wake-up via WDT or
Interrupt
Register
Power-on Reset
CCPR2H
CCPR2L
CCP2CON
TMR3H
TMR3L
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
IPR2
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 -01x
0000 000x
-1-- 1111
-1-- 0000
-1-- 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
0000 --00
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
---x xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 -01u
0000 000u
-1-- 1111
-1-- 0000
-1-- 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
0000 --00
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
-u-- uuuu
-u-- uuuu(1)
-u-- uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu(1)
-uuu uuuu(1)
uuuu uuuu
-uuu uuuu
uuuu --uu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATG
LATF
LATE
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain ‘0’
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (00008h or 00018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are
updated with the current value of the PC. The SKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: This is not a physical register. It is an indirect pointer that addresses another register. The contents
returned is the value contained in the addressed register.
DS39541A-page 36
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Applicable
Devices
Wake-up via WDT or
Interrupt
Power-on Reset
Reset Instruction
Stack Over/Underflow Reset
LATD
601
601
601
601
601
601
601
601
601
601
601
601
601
601
601
801
801
801
801
801
801
801
801
801
801
801
801
801
801
801
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
xxxx xxxx
0000 xxxx
---x xxxx
xxxx x000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--0x 0000
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
0000 uuuu
---u uuuu
uuuu u000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
LATC
LATB
LATA
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
CSEL2
CSELIO
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain ‘0’
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (00008h or 00018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are
updated with the current value of the PC. The SKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: This is not a physical register. It is an indirect pointer that addresses another register. The contents
returned is the value contained in the addressed register.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 37
PIC18C601/801
NOTES:
DS39541A-page 38
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2001 Microchip Technology Inc.
PIC18C601/801
4.1.1
“BOOT RAM” PROGRAM MEMORY
4.0
MEMORY ORGANIZATION
PIC18C601/801 devices have a provision for configur-
ing the last 512 bytes of general purpose user RAM as
program memory, called “Boot RAM”. This is achieved
by configuring the PGRM bit in the MEMCON register
to ‘1’. (Refer to Section 5.0, “External Memory Inter-
face” for more information.) When the PGRM bit is ‘1’,
the RAM located in data memory locations 400h
through 5FFh (bank 4 through 5) is mapped to program
memory locations 1FFE00h to 1FFFFFh.
There are two memory blocks in PIC18C601/801
devices. These memory blocks are:
• Program Memory
• Data Memory
Each block has its own bus so that concurrent access
can occur.
4.1
Program Memory Organization
When configured as program memory, the Boot RAM is
to be used as a temporary “boot loader” for program-
ming purposes. It can only be used for program execu-
tion. A read from locations 400h to 5FFh in data
memory returns all ‘0’s. Any attempt to write this RAM
as data memory when PGRM = 1, does not modify any
of these locations. TBLWT instructions to these loca-
tions will cause writes to occur on the external memory
bus. The boot RAM program memory cannot be modi-
fied using TBLWTinstruction. TBLRDinstructions from
boot RAM will read memory located on the external
memory bus, not from the on-board RAM. Constants
that are stored in boot RAM are retrieved using the
RETLWinstruction.
PIC18C601/801 devices have
a 21-bit program
counter that is capable of addressing up to 2 Mbyte of
external program memory space. The PIC18C601 has
an external program memory address space of 256
Kbytes. Any program fetch or TBLRDfrom a program
location greater than 256K will return all NOPs. The
PIC18C801 has an external program memory address
space of 2Mbytes. Refer to Section 5.0 (“External
Memory Interface”) for additional details.
The RESET vector address is mapped to 000000h and
the interrupt vector addresses are at 000008h and
000018h. PIC18C601/801 devices have a 31-level stack
to store the program counter values during subroutine
calls and interrupts. Figure 4-1 shows the program
memory map and stack for PIC18C601. Figure 4-2
shows the program memory map and stack for the
PIC18C801.
The default RESET state (power-up) for the PGRM bit
is ‘0’, which configures 1.5K of data RAM and all pro-
gram memory as external. The PGRM bit can be set
and cleared in the software.
When execution takes place from “Boot RAM”, the
external system bus and all of its control signals will be
deactivated. If execution takes place from outside of
“Boot RAM”, the external system bus and all of its con-
trol signals are activated again.
Figure 4-3 and Figure 4-4 show the program memory
map and stack for PIC18C601 and PIC18C801, when
the PGRM bit is set.
2001 Microchip Technology Inc.
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PIC18C601/801
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18C601 (PGRM = 0)
PIC18C801 (PGRM = 0)
PC<20:0>
PC<20:0>
21
21
Stack Level 1
Stack Level 1
•
•
•
•
•
•
Stack Level 31
RESET Vector
Stack Level 31
RESET Vector
0000h
0000h
High Priority Interrupt Vector
Low Priority Interrupt Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
0008h
0018h
External
Program Memory
External
Program Memory
3FFFFh
40000h
Read ’0’
1FFFFFh
1FFFFFh
DS39541A-page 40
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PIC18C601/801
FIGURE 4-3:
PROGRAM MEMORY MAP AND STACK FOR PIC18C601 (PGRM = 1)
PC<20:0>
21
Stack Level 1
•
•
•
Stack Level 31
0000h
0008h
RESET Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector 0018h
External
Program Memory
03FFFFh
040000h
Read ’0’
1FFDFFh
1FFE00h
1FFE00h
1FFFFFh
On-Chip
Boot RAM
1FFFFFh
INTERNAL MEMORY
EXTERNAL MEMORY
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PIC18C601/801
FIGURE 4-4:
PROGRAM MEMORY MAP AND STACK FOR PIC18C801 (PGRM = 1)
PC<20:0>
21
Stack Level 1
•
•
•
Stack Level 31
0000h
0008h
RESET Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector 0018h
External
Program Memory
1FFDFFh
1FFE00h
1FFE00h
1FFFFFh
External
Table Memory
On-Chip
Boot RAM
1FFFFFh
INTERNAL MEMORY
EXTERNAL MEMORY
DS39541A-page 42
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PIC18C601/801
4.1.2
BOOT LOADER
4.2.1
TOP-OF-STACK ACCESS
When configured as Program Memory, Boot RAM can
be used as a temporary “Boot Loader” for programming
purposes. If an external memory device is used as pro-
gram memory, any updates performed by the user pro-
gram will have to be performed in the “Boot RAM”,
because the user program cannot program and fetch
from external memory, simultaneously.
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, allow
access to the contents of the stack location indicated by
the STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALLor
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
A typical boot loader execution and external memory
programming sequence would be as follows:
• The boot loader program is transferred from the
external program memory to the last 2 banks of
data RAM by TBLRDand MOVWFinstructions.
The user should disable the global interrupt enable bits
during this time to prevent inadvertent stack operations.
• Once the “boot loader” program is loaded into
internal memory and verified, open combination
lock and set PGRM bit to configure the data RAM
into program RAM.
4.2.2
RETURN STACK POINTER
(STKPTR)
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
• Jump to beginning of Boot code in Boot RAM.
Program execution begins in Boot RAM to begin
programming the external memory. System bus
changes to an inactive state.
• Boot loader program performs the necessary
external TBLWTand TBLWRDinstructions to
perform programming functions.
• When the boot loader program is finished pro-
gramming external memory, jump to known valid
external program memory location and clear
PGRM bit in MEMCON register to set Boot RAM
as data memory, or reset the part.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR. Any subsequent push operation that causes
stack overflow will be ignored.
4.2
Return Address Stack
The action that takes place when the stack becomes
full, depends on the state of STVREN (stack overflow
RESET enable) configuration bit in CONFIG4L regis-
ter. Refer to Section 4.2.4 for more information. If
STVREN is set (default), stack over/underflow will set
the STKFUL bit, and reset the device. The STKFUL bit
will remain set and the stack pointer will be set to 0.
The return address stack allows any combination of up to
31 program calls and interrupts to occur. The PC (Pro-
gram Counter) is pushed onto the stack when a PUSH,
CALLor RCALLinstruction is executed, or an interrupt is
acknowledged. The PC value is pulled off the stack on a
RETURN, RETLWor a RETFIEinstruction. PCLATU and
PCLATH are not affected by any of the return instructions.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31. All
subsequent push attempts will be ignored and
STKPTR remains at 31.
The stack operates as a 31-word by 21-bit stack memory
and a five-bit stack pointer, with the stack pointer initial-
ized to 00000bafter all RESETS. There is no RAM asso-
ciated with stack pointer 00000b. This is only a RESET
value. During a CALL type instruction, causing a push
onto the stack, the stack pointer is first incremented and
the RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction, causing a pop from the stack, the contents of
the RAM location indicated by the STKPTR is transferred
to the PC and then the stack pointer is decremented.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software, or a POR occurs.
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appro-
priate actions can be taken.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the data on the top of the stack is readable and writable
through SFR registers. Status bits STKOVF and
STKUNF in STKPTR register, indicate whether stack
over/underflow has occurred or not.
2001 Microchip Technology Inc.
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PIC18C601/801
REGISTER 4-1:
STKPTR - STACK POINTER REGISTER
R/C-0
STKFUL
bit 7
R/C-0
U-0
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKUNF
—
bit 0
bit 7
bit 6
bit 5
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
Unimplemented: Read as '0'
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note: Bit 7 and bit 6 can only be cleared in user software, or by a POR.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared C = Clearable bit
’1’ = Bit is set
FIGURE 4-5:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
00010
TOSU
00h
TOSH
1Ah
TOSL
34h
00011
001A34h 00010
000D58h 00001
000000h 00000(1)
Top-of-Stack
Note 1: No RAM is associated with this address; always maintained ‘0’s.
DS39541A-page 44
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PIC18C601/801
4.2.3
PUSH AND POP INSTRUCTIONS
4.3
Fast Register Stack
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pop values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
A “fast return” option is available for interrupts and calls.
A fast register stack is provided for the STATUS, WREG
and BSR registers, and is only one layer in depth. The
stack is not readable or writable and is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. The values in the fast
register stack are then loaded back into the working reg-
isters, if the fast returninstruction is used to return
from the interrupt.
The POPinstruction discards the current TOS by decre-
menting the stack pointer. The previous value pushed
onto the stack then becomes the TOS value.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
4.2.4
STACK FULL/UNDERFLOW RESETS
These RESETS are enabled/disabled by programming
the STVREN configuration bit in CONFIG4L register.
If high priority interrupts are not disabled during low pri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
When the STVREN bit is disabled, a full or underflow
condition will set the appropriate STKFUL or STKUNF
bit, but not cause a RESET. When the STVREN bit is
enabled, a full or underflow will set the appropriate
STKFUL or STKUNF bit and then cause a RESET. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a fast call instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
•
•
SUB1
•
•
•
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
2001 Microchip Technology Inc.
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PIC18C601/801
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (See Section 4.8.1).
4.4
PCL, PCLATH and PCLATU
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
4.5
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1 or PLL output) is internally
divided by four to generate four non-overlapping
quadrature clocks, namely Q1, Q2, Q3 and Q4. Inter-
nally, the program counter (PC) is incremented every
Q1, the instruction is fetched from the program memory
and latched into the instruction register in Q4. The
instruction is decoded and executed during the follow-
ing Q1 through Q4. The clocks and instruction execu-
tion flow are shown in Figure 4-6.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSb of the PCL is fixed to a value of ’0’.
The PC increments by 2 to address sequential instruc-
tions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
FIGURE 4-6:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC
PC+2
PC+4
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-2)
Fetch INST (PC+2)
Execute INST (PC)
Fetch INST (PC+4)
Execute INST (PC+2)
DS39541A-page 46
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PIC18C601/801
4.6
Instruction Flow/Pipelining
4.7
Instructions in Program Memory
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
two cycles are required to complete the instruction
(Example 4-2).
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = ’0’). Figure 4-1 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’ (see Section 4.4).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
The CALLand GOTOinstructions have an absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-1 shows how the
instruction “GOTO 0x06” is encoded in the program
memory. Program branch instructions that encode a
relative address offset operate in the same manner.
The offset value stored in a branch instruction repre-
sents the number of single word instructions by which
the PC will be offset. Section 20.0 provides further
details of the instruction set.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
TABLE 4-1:
INSTRUCTIONS IN PROGRAM MEMORY
Instruction
Opcode
Memory
Address
—
—
—
000007h
000008h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h
000011h
000012h
MOVLW 055h
0E55h
55h
0Eh
03h
EFh
00h
F0h
23h
C1h
56h
F4h
—
GOTO 000006h
EF03h, F000h
C123h, F456h
—
MOVFF 123h, 456h
—
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PIC18C601/801
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
4.7.1
TWO-WORD INSTRUCTIONS
PIC18C601/801 devices have four two-word instruc-
tions: MOVFF, CALL, GOTOand LFSR. The second
word of these instructions has the four MSB’s set to 1’s
and is a special kind of NOPinstruction. The lower 12
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC and
skips one instruction. A program example that demon-
strates this concept is shown in Example 4-3. Refer to
Section 19.0 for further details of the instruction set.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
Warning: The LSb of the PCL is fixed to a value of ‘0’.
Hence, computed GOTOto an odd address
is not possible.
4.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored as 2 bytes per pro-
gram word by using table reads and writes. The table
pointer (TBLPTR) specifies the byte address and the
table latch (TABLAT) contains the data that is read
from, or written to, program memory. Data is trans-
ferred to/from program memory one byte at a time.
4.8
Lookup Tables
Lookup tables are implemented two ways:
• Computed GOTO
• Table Reads
A description of the Table Read/Table Write operation
is shown in Section 6.0.
4.8.1
COMPUTED GOTO
Note: If execution is taking place from Boot RAM
Program Memory, RETLW instructions
must be used to read lookup values from
the Boot RAM itself.
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table, before exe-
cuting a call to that table. The first instruction of the called
routine is the ADDWF PCLinstruction. The next instruc-
tion executed will be one of the RETLW 0xnn instruc-
tions that returns the value 0xnnto the calling function.
EXAMPLE 4-3:
Two-Word Instructions
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
TSTFSZ
MOVFF
REG1
; is RAM location 0?
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
TSTFSZ
MOVFF
REG1
; is RAM location 0?
REG1, REG2 ; Yes
; 2nd operand executed as NOP
REG3 ; continue code
ADDWF
DS39541A-page 48
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
4.9.1
GENERAL PURPOSE REGISTER
FILE
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address, allow-
ing up to 4096 bytes of data memory. Figure 4-8 shows
the data memory organization for PIC18C601/801
devices.
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
The data memory map is divided into banks that con-
tain 256 bytes each. The lower four bits of the Bank
Select Register (BSR<3:0>) select which bank will be
accessed. The upper 4 bits for the BSR are not imple-
mented.
PIC18C601/801 devices have banked memory in the
GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (0F80h to 0FFFh) contains
SFR’s. All other banks of data memory contain GPR
registers starting with bank 0.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFR’s are used for control and status of the controller
and peripheral functions, while GPR’s are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFR’s start at the last location of Bank 15
(0FFFh) and grow downwards. GPR’s start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ’0’s.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 4-2.
GPR banks 4 and 5 serve as a Program Memory called
“Boot RAM”, when PGRM bit in MEMCON is set. When
PGRM bit is set, any read from “Boot RAM” returns ‘0’s,
while any write to it is ignored.
The SFR’s can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSR). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking.
The SFRs are typically distributed among the peripher-
als whose functions they control.
The unused SFR locations are unimplemented and
read as '0's. See Table 4-2 for addresses for the SFRs.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing, or by the use of the MOVFFinstruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
4.9.3
SECURED ACCESS REGISTERS
PIC18C601/801 devices contain software program-
ming options for safety critical peripherals. Because
these safety critical peripherals can be programmed in
software, registers used to control these peripherals
are given limited access by the user code. This way,
errant code will not accidentally change settings in
peripherals that could cause catastrophic results.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access bank. Section 4.10 pro-
vides a detailed description of the Access bank.
The registers that are considered safety critical are the
Watchdog Timer register (WDTCON), the External
Memory Control register (MEMCON), the Oscillator
Control register (OSCCON) and the Chip Select regis-
ters (CSSEL2 and CSELIO).
Two bits called Combination Lock (CMLK) bits, located
in the lower two bits of the PSPCON register, must be
set in sequence by user code to gain access to
Secured Access registers.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 49
PIC18C601/801
REGISTER 4-2:
PSPCON REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
W-0
W-0
—
—
—
—
—
—
CMLK1
CMLK0
bit 7
bit 0
bit 7-2
bit 1-0
Unimplemented: Read as '0'
CMLK<1:0>: Combination Lock bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
The Combination Lock bits must be set sequentially,
meaning that as soon as Combination Lock bit CMLK1
is set, the second Combination Lock bit CMLK0 must be
set on the following instruction cycle. If user waits more
than one machine cycle to set the second bit after set-
ting the first, both bits will automatically be cleared in
hardware and the lock will remain closed. To satisfy this
condition, all interrupts must be disabled before attempt-
ing to unlock the Combination Lock. Once secured reg-
isters are modified, interrupts may be re-enabled.
When the Combination Lock is opened, the user will
have three instruction cycles to modify the safety criti-
cal register of choice. After three instruction cycles
have expired, the CMLK bits are cleared, the lock will
close and the user will have to set the CMLK bits again,
in order to open the lock. Since there are only three
instruction cycles allowed after the Combination Lock is
opened, if a subroutine is used to unlock Combination
Lock bits, user code must preload WREG with the
desired value, call unlock subroutine, and write to the
desired safety critical register itself.
Each instruction must only modify one combination lock
bit at a time. This means, user code must use the BSF
instruction to set CMLK bits in the PSPCON register.
Note: Successive attempts to unlock the Combi-
nation Lock must be separated by at least
three instruction cycles.
Note: The Combination Lock bits are write-only
bits. These bits will always return ‘0’ when
read.
EXAMPLE 4-4:
COMBINATION UNLOCK SUBROUTINE EXAMPLE CODE
MOVLW 5Ah
BCF INTCON, GIE
CALL UNLOCK
; Preload WREG with data to be stored in a safety critical register
; Disable all interrupts
; Now unlock it
; Write must take place in next instruction cycle
MOVWF OSCCON
; Lock is closed
BSF INTCON, GIE
; Re-enable interrupts
•
•
UNLOCK
BSF PSPCON, CMLK1
BSF PSPCON, CMLK0
RETURN
•
•
DS39541A-page 50
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
EXAMPLE 4-5:
COMBINATION UNLOCK MACRO EXAMPLE CODE
UNLOCK_N_MODIFY @REG
MACRO
BCF INTCON, GIE
BSF PSPCON, CMLK1
BSF PSPCON, CMLK0
MOVWF @REG
BSF INTCON, GIE
ENDM
; Disable interrupts
; Modify given register
; Enable interrupts
•
•
MOVLW 5Ah
UNLOCK_N_MODIFY OSCCON
; Preload WREG for OSCCON register
; Modify OSCCON
FIGURE 4-7:
THE DATA MEMORY MAP FOR PIC18C801/601 (PGRM = 0)
BSR<3:0>
Data Memory Map
000h
07Fh
080h
0FFh
100h
00h
Access GPR’s
= 0000b
Bank 0
GPR
FFh
00h
= 0001b
= 0010b
GPR
GPR
Bank 1
Bank 2
Bank 3
1FFh
200h
FFh
00h
2FFh
300h
FFh
00h
= 0011b
GPR
GPR
FFh
00h
3FFh
400h
= 0100b
= 0101b
Bank 4
Bank 5
Access RAM Bank
4FFh
500h
FFh
00h
00h
Access Bank Low
(GPR’s)
7Fh
80h
GPR
Access Bank High
FFh
5FFh
(SFR’s)
FFh
= 0110b
= 1110b
When a = 0,
Bank 6
to
Bank 14
Unused
the BSR is ignored and this
Access RAM bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The next 128 bytes are Special
Function Registers (from
Bank 15).
Read ’00h’
EFFh
F00h
F7Fh
F80h
FFFh
00h
FFh
Unused
= 1111b
Bank 15
Access SFR’s
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 51
PIC18C601/801
FIGURE 4-8:
DATA MEMORY MAP FOR PIC18C601/801 (PGRM = 1)
BSR<3:0>
Data Memory Map
000h
07Fh
080h
0FFh
00h
Access GPR’s
= 0000b
Bank 0
GPR
FFh
00h
100h
= 0001b
= 0010b
GPR
GPR
Bank 1
Bank 2
Bank 3
1FFh
200h
FFh
00h
2FFh
300h
FFh
00h
= 0011b
GPR
FFh
3FFh
Access RAM Bank
00h
Access Bank Low
(GPR’s)
Access Bank High
7Fh
80h
(SFR’s)
FFh
= 0100b
= 1110b
Bank 4
to
Bank 14
Unused
Read ’00h’
When a = 0,
the BSR is ignored and this
Access RAM bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The next 128 bytes are Special
Function Registers (from
Bank 15).
EFFh
F00h
F7Fh
F80h
FFFh
00h
FFh
Unused
= 1111b
Bank 15
Access SFR’s
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
DS39541A-page 52
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 4-9:
SPECIAL FUNCTION REGISTER MAP
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0 FCEh
POSTDEC0 FCDh
PREINC0
PLUSW0
FSR0H
FSR0L
FDFh
FDEh
FDDh
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
INDF2
POSTINC2 FBEh
POSTDEC2 FBDh
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
Reserved
OSCCON
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
FBFh
CCPR1H
CCPR1L
CCP1CON F9Dh
CCPR2H
CCPR2L
CCP2CON F9Ah
Reserved
Reserved
Reserved
—
F9Fh
F9Eh
IPR1
PIR1
PIE1
MEMCON
—
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
F9Ch
F9Bh
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
—
—
TMR3H
TMR3L
T3CON
PSPCON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
—
—
—
CSEL2
CSELIO
—
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
WREG
INDF1
POSTINC1 FC6h
POSTDEC1 FC5h
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
FC4h
FC3h
FC2h
FC1h
FC0h
—
—
IPR2
PIR2
PIE2
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 53
PIC18C601/801
TABLE 4-2:
REGISTER FILE SUMMARY - PIC18C601/801
Value on
all other
Value on
POR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(1)
FFFh TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 ---0 0000
0000 0000 0000 0000
0000 0000 0000 0000
00-0 0000 00-0 0000
---0 0000 ---0 0000
0000 0000 0000 0000
0000 0000 0000 0000
FFEh TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
FFDh TOSL
FFCh STKPTR
FFBh PCLATU
FFAh PCLATH
FF9h PCL
STKOVF
STKUNF
—
—
Return Stack Pointer
—
—
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
FF8h TBLPTRU
FF7h TBLPTRH
FF6h TBLPTRL
FF5h TABLAT
FF4h PRODH
FF3h PRODL
FF2h INTCON
FF1h INTCON2
FF0h INTCON3
FEFh INDF0
—
—
r
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --r0 0000 --r0 0000
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
1111 -1-1 1111 -1-1
11-0 0-00 11-0 0-00
Product Register High Byte
Product Register Low Byte
GIE/GIEH PEIE/GIEL
TMR0IE
INTEDG1
—
INT0E
INTEDG2
INT2E
RBIE
—
TMR0IF
T0IP
—
INT0F
—
RBIF
RBIP
INT1F
RBPU
INT2P
INTEDG0
INT1P
INT1E
INT2F
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
N/A
FEEh POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
FEDh POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented
(not a physical register)
FECh PREINC0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented
(not a physical register)
N/A
N/A
N/A
N/A
FEBh PLUSW0
Uses contents of FSR0 to address data memory -value of FSR0 offset by WREG
(not a physical register)
FEAh FSR0H
FE9h FSR0L
FE8h WREG
FE7h INDF1
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
N/A
N/A
N/A
N/A
FE6h POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented
(not a physical register)
FE5h POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented
(not a physical register)
N/A
N/A
FE4h PREINC1
FE3h PLUSW1
FE2h FSR1H
FE1h FSR1L
FE0h BSR
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 offset by WREG (not a physical register)
N/A
N/A
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
---- 0000 ---- 0000
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
FDFh INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
N/A
FDEh POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
FDDh POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented
(not a physical register)
FDCh PREINC2
FDBh PLUSW2
FDAh FSR2H
FD9h FSR2L
FD8h STATUS
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory -value of FSR2 offset by WREG (not a physical register)
N/A
N/A
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Legend
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition, r= reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
DS39541A-page 54
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 4-2:
REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED)
Value on
all other
Value on
POR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(1)
FD7h TMR0H
FD6h TMR0L
FD5h T0CON
FD4h Reserved
FD3h OSCCON(2)
FD2h LVDCON(2)
FD1h WDTCON(2)
FD0h RCON
FCFh TMR1H
FCEh TMR1L
FCDh T1CON
FCCh TMR2
Timer0 Register High Byte
Timer0 Register Low Byte
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
rrrr rrrr rrrr rrrr
---- 0000 ---- uuu0
--00 0101 --00 0101
TMR0ON
16BIT
T0CS
T0SE
T0PS3
T0PS2
T0PS1
T0PS0
—
—
—
—
—
r
—
IRVST
—
—
LVDEN
—
LOCK
LVV3
PLLEN
LVV2
SCS1
LVV1
SCS0
LVV0
—
WDPS2
TO
WDPS1
PD
WDPS0
POR
SWDTEN ---- 0000 ---- xxxx
IPEN
—
RI
r
00-1 11qq 00-q qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Timer1 Register High Byte
Timer1 Register Low Byte
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0-00 0000 u-uu uuuu
0000 0000 0000 0000
Timer2 Register
FCBh PR2
Timer2 Period Register
TOUTPS3
1111 1111 1111 1111
FCAh T2CON
FC9h SSPBUF
FC8h SSPADD
FC7h SSPSTAT
FC6h SSPCON1
FC5h SSPCON2
FC4h ADRESH
FC3h ADRESL
FC2h ADCON0
FC1h ADCON1
FC0h ADCON2
FBFh CCPR1H
FBEh CCPR1L
FBDh CCP1CON
FBCh CCPR2H
FBBh CCPR2L
FBAh CCP2CON
FB9h Reserved
FB8h Reserved
FB7h Reserved
FB6h
—
TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
SSP Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0 0000 0000 0000 0000
ACKEN
SEN
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
—
—
—
CHS3
VCFG1
—
CHS2
VCFG0
—
CHS1
PCFG3
—
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0 --00 0000 --00 0000
ADCS0 0--- -000 0--- -000
xxxx xxxx uuuu uuuu
ADFM
ADCS1
Capture/Compare/PWM Register1 High Byte
Capture/Compare/PWM Register1 Low Byte
xxxx xxxx uuuu uuuu
—
—
DC1B1
DC1B0
CCP1M3
CCP2M3
CCP1M2
CCP2M2
CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register2 High Byte
Capture/Compare/PWM Register2 Low Byte
xxxx xxxx uuuu uuuu
—
—
DC2B1
DC2B0
CCP2M1 CCP2M0 --00 0000 --uu uuuu
rrrr rrrr rrrr rrrr
rrrr rrrr rrrr rrrr
rrrr rrrr rrrr rrrr
FB5h
FB4h
FB3h TMR3H
FB2h TMR3L
FB1h T3CON
Timer3 Register High Byte
Timer3 Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3CCP2
T3CKPS1 T3CKPS0 T3CCP1
T3SYNC
TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition, r= reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 55
PIC18C601/801
TABLE 4-2:
REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED)
Value on
all other
Value on
POR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(1)
FB0h PSPCON
FAFh SPBRG
FAEh RCREG
FADh TXREG
FACh TXSTA
FABh RCSTA
FAAh
—
—
—
—
—
—
CMLK1
CMLK0 ---- --00 ---- --00
0000 0000 0000 0000
USART Baud Rate Generator
USART Receive Register
USART Transmit Register
0000 0000 0000 0000
0000 0000 0000 0000
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 -010 0000 -010
0000 000x 0000 000x
ADEN
FA9h
FA8h
FA7h CSEL2(2)
FA6h CSELIO(2)
FA5h
CSL7
CSL6
CSL5
CSL4
CSL3
CSL2
CSL1
CSL0
1111 1111 uuuu uuuu
1111 1111 uuuu uuuu
CSIO7
CSIO6
CSIO5
CSIO4
CSIO3
CSIO2
CSIO1
CSIO0
FA4h
FA3h
FA2h IPR2
FA1h PIR2
FA0h PIE2
F9Fh IPR1
F9Eh PIR1
F9Dh PIE1
F9Ch MEMCON(2)
F9Bh
—
—
—
—
—
—
—
—
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
—
LVDIP
LVDIF
LVDIE
CCP1IP
CCP1IF
CCP1IE
—
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
WM1
CCP2IP ---- 1111 ---- 1111
CCP2IF ---- 0000 ---- 0000
CCP2IE ---- 0000 ---- 0000
TMR1IP -111 1111 -111 1111
TMR1IF -000 0000 -000 0000
TMR1IE -000 0000 -000 0000
—
—
—
—
—
ADIP
ADIF
ADIE
PGRM
RCIP
RCIF
RCIE
WAIT1
TXIP
TXIF
TXIE
WAIT0
—
—
EBDIS
WM0
0000 --00 0000 --00
F9Ah TRISJ(3)
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
1111 1111 1111 1111
1111 1111 1111 1111
---1 1111 ---1 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
--11 1111 --11 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
xxxx xx00 uuuu uu00
F99h
F98h
F96h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
TRISH(3)
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ(3)
LATH(3)
—
—
—
Read PORTG Data Latch, Write PORTG Data Latch
Read PORTF Data Latch, Write PORTF Data Latch
Data Direction Control Register for PORTE
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
—
—
Data Direction Control Register for PORTA
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
F8Fh LATG
F8Eh LATF
F8Dh LATE
F8Ch LATD
F8Bh LATC
F8Ah LATB
—
—
—
Read PORTG Data Latch, Write PORTG Data Latch
Read PORTF Data Latch, Write PORTF Data Latch
Read PORTE Data Latch, Write PORTE Data Latch
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
F89h
F88h
F87h
F86h
LATA
—
—
Read PORTA Data Latch, Write PORTA Data Latch
PORTJ(3)
PORTH(3)
PORTG
PORTF
Read PORTJ Pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
—
—
—
Read PORTG pins, Write PORTG Data Latch
F85h
Read PORTF pins, Write PORTF Data Latch
Legend
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition, r= reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
DS39541A-page 56
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 4-2:
REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED)
Value on
all other
Value on
POR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS(1)
F84h
F83h
F82h
F81h
PORTE
PORTD
PORTC
PORTB
PORTA
Read PORTE Pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
F80h
—
—
Read PORTA pins, Write PORTA Data Latch
Legend
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition, r= reserved
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 57
PIC18C601/801
4.10 Access Bank
4.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement that
is very useful for C compiler code optimization. The
techniques used by the C compiler are also useful for
programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
A MOVLBinstruction has been provided in the instruc-
tion set to assist in selecting banks.
• Faster evaluation/control of SFR’s (no banking)
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFR’s) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access Bank
High and Access Bank Low, respectively. Figure 4-8
indicates the Access Bank areas.
Each Bank extends up to 0FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register, or in
the Access Bank.
A MOVFFinstruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = ’0’), the last
address in Access Bank Low is followed by the first
address in Access Bank High. Access Bank High maps
all Special Function Registers so that these registers
can be accessed without any software overhead.
FIGURE 4-10:
DIRECT ADDRESSING
Direct Addressing
(3)
from opcode
BSR<3:0>
7
0
(2)
(3)
bank select
location select
00h
000h
01h
100h
0Eh
E00h
0Fh
F00h
Data
Memory
(1)
0FFh
1FFh
Bank 1
EFFh
FFFh
Bank 0
Bank 14
Bank 15
Note 1: For register file map detail, see Table 4-2.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
DS39541A-page 58
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
If INDF0, INDF1, or INDF2 are read indirectly via an
FSR, all ’0’s are read (zero bit is set). Similarly, if
INDF0, INDF1, or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
STATUS bits are not affected.
4.12 Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. A SFR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-11
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
Indirect addressing is possible by using one of the
INDFn (0 ≤ n ≤ 2) registers. Any instruction using the
INDFn register actually accesses the register indicated
by the File Select Register, FSRn (0 ≤ n ≤ 2). Reading
the INDFn register itself indirectly (FSRn = ’0’), will read
00h. Writing to the INDFn register indirectly, results in a
no-operation. The FSRn register contains a 12-bit
address, which is shown in Figure 4-11.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
Example 4-6 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
• Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
EXAMPLE 4-6:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
LFSR FSR0, 100h
;
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
NEXTCLRF POSTINC0
; Clear INDF
; register
; & inc pointer
; All done
; with Bank1?
; NO, clear next
BTFSS FSR0H, 1
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
BRA
CONTINUE;
:
NEXT
; YES, continue
Adding these features allows the FSRn to be used as a
software stack pointer, in addition to its uses for table
operations in data memory.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the 2’s complement value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not changed.
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or post-
increment/decrement functions.
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
If an instruction writes a value to INDF0, the value will
be written to the address indicated by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
indicated by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 59
PIC18C601/801
FIGURE 4-11:
INDIRECT ADDRESSING
Indirect Addressing
FSR Register
7
11
8
0
FSRnH
FSRnL
Location Select
0000h
Data
Memory
(1)
0FFFh
Note 1: For register file map detail, see Table 4-2.
DS39541A-page 60
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
For example, CLRF STATUSwill clear all implemented
bits and set the Z bit. This leaves the STATUS register
as ---0 0100(where - = unimplemented).
4.13 STATUS Register
The STATUS register, shown in Register 4-3, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV, or N bits,
then the write to these five bits is disabled. These bits
are set or cleared according to the device logic. There-
fore, the result of an instruction with the STATUS regis-
ter as destination may be different than intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the STATUS register, because these instructions
do not affect the Z, C, DC, OV, or N bits from the
STATUS register. For other instructions which do not
affect the status bits, see Table 20-2.
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
REGISTER 4-3:
STATUS REGISTER
U-0
U-0
U-0
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
—
—
—
bit 7
bit 0
bit 7-5 Unimplemented: Read as '0'
bit 4
bit 3
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU
operation was negative (ALU MSb = 1).
1= Result was negative
0= Result was positive
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For arithmetic addition and subtraction instructions
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRCF, RRNCF, RLCF, and
RLNCF) instructions, this bit is loaded with either the bit 4, or bit 3 of the source
register.
bit 0
C: Carry/borrow bit
For arithmetic addition and subtraction instructions
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRCF, RLCF) instructions, this bit
is loaded with either the high, or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 61
PIC18C601/801
4.14 RCON Register
Note: It is recommended that the POR bit be set
after a Power-on Reset has been detected,
so that subsequent Power-on Resets may
be detected.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR
and RI bits. This register is readable and writable.
REGISTER 4-4:
RCON REGISTER
R/W-0
IPEN
U-0
r
U-0
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
U-0
r
—
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6
bit 5
bit 4
Reserved: Maintain as ‘0’
Unimplemented: Read as '0'
RI: RESETInstruction Flag bit
1 = The RESETinstruction was not executed
0 = The RESETinstruction was executed causing a device RESET
(must be set in software after RESETinstruction was executed)
bit 3
bit 2
bit 1
TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction
0 = A WDT time-out occurred
PD: Power-down Detection Flag bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0
Reserved: Maintain as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
r
= Reserved
DS39541A-page 62
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
These pins are multiplexed with I/O port pins, but the
I/O functions are only enabled when program execution
takes place in internal Boot RAM and the EBDIS bit in
the MEMCON register is set (see Register 5-1).
5.0
EXTERNAL MEMORY
INTERFACE
The External Memory Interface is a feature of the
PIC18C601/801 that allows the processor to access
external memory devices, such as FLASH, EPROM,
SRAM, etc. Memory mapped peripherals may also be
accessed.
5.1
Memory Control Register
(MEMCON)
Register 5-1 shows the Memory Control Register
(MEMCON). This register contains bits used to control
the operation of the External Memory Interface.
The External Memory Interface physical implementa-
tion includes up to 26 pins on the PIC18C601 and up to
38 pins on the PIC18C801. These pins are reserved for
external address/data bus functions.
REGISTER 5-1:
MEMCON REGISTER
R/W-0
EBDIS
R/W-0
PGRM
R/W-0
WAIT1
R/W-0
WAIT0
U-0
U-0
R/W-0
WM1
R/W-0
WM0
—
—
bit7
bit0
bit 7
bit 6
EBDIS: External Bus Disable
1= External system bus disabled, all external bus drivers are mapped as I/O ports
0= External system bus enabled, and I/O ports are disabled
PGRM: Program RAM Enable
1= 512 bytes of internal RAM enabled as internal program memory from location 1FFE00h to
1FFFFFh, external program memory at these locations is unused. Internal GPR memory
from 400h to 5FFh is disabled and returns 00h.
0= Internal RAM enabled as internal GPR memory from 400h to 5FFh. Program memory from
location 1FFE00h to 1FFFFFh is configured as external program memory.
bit 5-4
WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count
11= Table reads and writes will wait 0 TCY
10= Table reads and writes will wait 1 TCY
01= Table reads and writes will wait 2 TCY
00= Table reads and writes will wait 3 TCY
bit 3-2
bit 1-0
Unimplemented: Read as '0'
WM<1:0>: TABLWT Operation with 16-bit Bus
1X= Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when TABLAT1 written
01= Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB) will
activate
00= Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 63
PIC18C601/801
Therefore, the designer must choose external memory
devices according to timing calculations based on 1/2
Tcy (2 times instruction rate). For proper memory
speed selection, glue logic propagation delay times
must be considered along with setup and hold times.
5.2
8-bit Mode
The External Memory Interface can operate in 8-bit
mode. The mode selection is not software configurable,
but is programmable via the configuration bits.
There are two types of connections in 8-bit mode. They
are referred to as:
The Address Latch Enable (ALE) pin indicates that the
address bits A<7:0> are available on the External
Memory Interface bus. The OE output enable signal will
enable one byte of program memory for a portion of the
instruction cycle, then BA0 will change and the second
byte will be enabled to form the 16-bit instruction word.
The least significant bit of the address, BA0, must be
connected to the memory devices in this mode.
Figure 5-1 shows an example of 8-bit Multiplexed
mode on the PIC18C601. The control signals used in
8-bit Multiplexed mode are outlined in Table 5-1.
Register 5-2 describes 8-bit Multiplexed mode timing.
• 8-bit Multiplexed
• 8-bit De-Multiplexed
5.2.1
8-BIT MULTIPLEXED MODE
The 8-bit Multiplexed mode applies only to the
PIC18C601. Data and address lines are multiplexed on
port pins and must be decoded with glue logic.
For 8-bit Multiplexed mode on the PIC18C601, the
instructions will be fetched as two 8-bit bytes on a
shared data/address bus (PORTD). The two bytes are
sequentially fetched within one instruction cycle (TCY).
FIGURE 5-1:
8-BIT MULTIPLEXED MODE EXAMPLE
D<7:0>
A<17:0>
A<x:1>
AD<7:0>
ALE
373
A0
D<7:0>
PIC18C601
(2)
CE OE WR
BA0
A16, AD<15:8>
CS1
OE
WRL
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
TABLE 5-1:
8-BIT MULTIPLEXED MODE CONTROL SIGNALS
8-bit Mux
Mode
Name
Function
RG0/ALE
RG1/OE
ALE
OE
Address Latch Enable (ALE) control pin
Output Enable (OE) control pin
Write Low (WRL) control pin
Byte address bit 0
RG2/WRL
RG4/BA0
RF3/CSIO
RF5/CS1
WRL
BA0
CSIO
CS1
Chip Select I/O (See Section 5.4)
Chip Select 1 (See Section 5.4)
DS39541A-page 64
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 5-2:
8-BIT MULTIPLEXED MODE TIMING
Q4
Q1
Q2
Q3
03Ah
A16, AD<15:8>
0Eh
ABh
55h
AD<7:0>
BA0
ALE
OE
Opcode Fetch
MOVLW 55h
from 007556h
The Address Latch Enable (ALE) pin is left uncon-
nected, since glue logic is not necessary. The OE out-
put enable signal will enable one byte of program
memory for a portion of the instruction cycle, then BA0
will change and the second byte will be enabled to form
the 16-bit instruction word. The least significant bit of
the address, BA0, must be connected to the memory
devices in this mode. Figure 5-3 shows an example of
8-bit De-Multiplexed mode on the PIC18C801. The
control signals used in 8-bit De-Multiplexed mode are
outlined in Register 5-2. Register 5-4 describes 8-bit
De-Multiplexed mode timing.
5.2.2
8-BIT DE-MULTIPLEXED MODE
The 8-bit De-Multiplexed mode applies only to the
PIC18C801. Data and address lines are available sep-
arately. External components are not necessary in this
mode.
For 8-bit De-Multiplexed mode on the PIC18C801, the
instructions are fetched as two 8-bit bytes on a dedi-
cated data bus (PORTJ). The address will be pre-
sented for the entire duration of the fetch cycle on a
separate address bus. The two instruction bytes are
sequentially fetched within one instruction cycle (TCY).
Therefore, the designer must choose external memory
devices according to timing calculations, based on 1/2
TCY (2 times instruction rate). For proper memory speed
selection, setup and hold times must be considered.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 65
PIC18C601/801
FIGURE 5-3:
8-BIT DE-MULTIPLEXED MODE EXAMPLE
BA0
A0
A<20:0>
D<7:0>
A<x:1>
D<7:0>
A<19:16>, AD<15:0>
D<7:0>
PIC18C801
CE OE WR(1)
ALE
CS1
OE
WRL
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
TABLE 5-2:
8-BIT DE-MULTIPLEXED MODE CONTROL SIGNALS
Name
8-bit De-Mux Mode
Function
RG0/ALE
RG1/OE
ALE
OE
Address Latch Enable (ALE) control pin
Output Enable (OE) control pin
Write Low (WRL) control pin
Byte address bit 0
RG2/WRL
RG4/BA0
RF3/CSIO
RF4/CS2
RF5/CS1
WRL
BA0
CSIO
CS2
CS1
Chip Select I/O (See Section 5.4)
Chip Select 2 (See Section 5.4)
Chip Select 1 (See Section 5.4)
FIGURE 5-4:
8-BIT DE-MULTIPLEXED MODE TIMING
Q1
Q2
Q4
Q3
03Ah
A16, AD<15:8>
0Eh
55h
AD<7:0>
BA0
ALE
OE
Opcode Fetch
MOVLW 55h
from 007556h
DS39541A-page 66
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A<15:0> are avail-
able on the External Memory Interface bus. Following
the address latch, the output enable signal (OE ) will
enable both bytes of program memory at once to form
a 16-bit instruction word.
5.3
16-bit Mode
The External Memory Interface can operate in 16-bit
mode. The mode selection is not software configurable,
but is programmable via the configuration bits.
The WM<1:0> bits in the MEMCON register determine
three types of connections in 16-bit mode. They are
referred to as:
In Byte Select mode, JEDEC standard FLASH memo-
ries will require BA0 for the byte address line, and one
I/O line, to select between byte and word mode. The
other 16-bit modes do not need BA0. JEDEC standard
static RAM memories will use the UB or UL signals for
byte selection.
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
5.3.1
16-BIT BYTE WRITE MODE
Figure 5-5 shows an example of 16-bit Byte Write
mode for the PIC18C601/801.
FIGURE 5-5:
16-BIT BYTE WRITE MODE EXAMPLE
D<7:0>
(MSB)
A<x:0>
(LSB)
A<x:0>
PIC18C801
A<19:0>
D<15:8>
AD<15:8>
373
373
D<7:0>
D<7:0>
CE
D<7:0>
CE
AD<7:0>
ALE
(1)
(1)
OE WR
OE WR
A<19:16>
CS1
OE
WRH
WRL
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 67
PIC18C601/801
5.3.2
16-BIT WORD WRITE MODE
Figure 5-6 shows an example of 16-bit Word Write
mode for the PIC18C801.
FIGURE 5-6:
PIC18C801
16-BIT WORD WRITE MODE EXAMPLE
A<20:1>
JEDEC Word
EPROM Memory
AD<7:0>
373
A<x:0>
D<15:0>
D<15:0>
CE
(1)
OE
WR
AD<15:8>
373
ALE
A<19:16>
CS1
OE
WRH
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
5.3.3
16-BIT BYTE SELECT MODE
Figure 5-7 shows an example of 16-bit Byte Select
mode for the PIC18C801.
FIGURE 5-7:
16-BIT BYTE SELECT MODE EXAMPLE
PIC18C801
A<20:1>
AD<7:0>
373
373
JEDEC Word
FLASH Memory
A<x:1>
D<15:0>
D<15:0>
CE
A0
AD<15:8>
(1)
ALE
A<19:16>
OE
BYTE/WORD OE WR
WRH
A<20:1>
WRL
BA0
JEDEC Word
A<x:1>
SRAM Memory
I/O
CS1
CS2
LB
D<15:0>
D<15:0>
CE
LB
UB
(1)
UB
OE WR
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
DS39541A-page 68
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
5.3.4
16-BIT MODE CONTROL SIGNALS
Table 5-3 describes the 16-bit mode control signals for
the PIC18C601/801.
TABLE 5-3:
Name
PIC18C601/801 16-BIT MODE CONTROL SIGNALS
18C601 16-bit
Mode
18C801 16-bit
Mode
Function
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
RG4/BA0
RF3/CSIO
RF4/CS2
RF5/CS1
RF6/UB
RF7/LB
ALE
OE
ALE
OE
Address Latch Enable (ALE) control pin
Output Enable (OE) control pin
Write Low (WRL) control pin
WRL
WRH
BA0
CSIO
N/A
CS1
UB
WRL
WRH
BA0
CSIO
CS2
CS1
UB
Write High (WRH) control pin
Byte address bit 0
Chip Select I/O (See Section 5.4)
Chip Select 2 (See Section 5.4)
Chip Select 1 (See Section 5.4)
Upper Byte Enable (UB) control pin
Lower Byte Enable (LB) control pin
I/O as BYTE/WORD control pin for JEDEC FLASH
LB
LB
I/O
I/O
I/O
5.3.5
16-BIT MODE TIMING
Figure 5-8 describes the 16-bit mode timing for the
PIC18C601/801.
FIGURE 5-8:
16-BIT MODE TIMING
Q4
Q1
Q2
Q3
03Ah
A16, AD<15:8>
0E55h
3AABh
AD<7:0>
BA0
ALE
OE
WRH ‘1’
‘1’
WRL
Opcode Fetch
MOVLW 55h
from 007556h
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 69
PIC18C601/801
Two SFRs are used to control the chip select signals.
These are CSEL2 and CSELIO (see Register 5-2 and
Register 5-3). A chip select signal is asserted low when
the CPU makes an access to a dedicated range of
addresses specified in the chip select registers, CSEL2
and CSELIO. The 8-bit value found in either of these
registers is decoded as one of 256, 8K banks of pro-
gram memory. If both chip select registers are 00h, all
of the chip select signals are disabled and their corre-
sponding pins are configured as I/O. Since the last 512
bytes of program memory are dedicated to internal pro-
gram RAM, the chip select signals will not activate if the
program memory address falls in this range.
5.4
Chip Selects
Chip select signals are used to select regions of exter-
nal memory and I/O devices for access. The
PIC18C801 has three chip selects and all are program-
mable. The chip select signals are CS1, CS2 and
CSIO. CS1 and CS2 are general purpose chip selects
that are used to enable large portions of program mem-
ory. CSIO is used to enable external I/O expansion.
The PIC18C601uses two of these programmable chip
selects: CS1 and CSIO.
REGISTER 5-2:
CSEL2 REGISTER
R/W-1
CSL7
R/W-1
CSL6
R/W-1
CSL5
R/W-1
CSL4
R/W-1
CSL3
R/W-1
CSL2
R/W-1
CSL1
R/W-1
CSL0
bit 7
bit 0
bit 7-0
CSL<7:0>: Chip Select 2 Address Decode bits
XXh= All eight bits are compared to the Most Significant bits PC<20:13> of the program
counter. If PC<20:13> ≥ CSL<7:0> register, then the CS2 signal is low.
If PC<20:13> < CSL<7:0>, CS2 is high.
00h= CS2 is inactive
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
REGISTER 5-3:
CSELIO REGISTER
R/W-1
CSIO7
R/W-1
CSIO6
R/W-1
CSIO5
R/W-1
CSIO4
R/W-1
CSIO3
R/W-1
CSIO2
R/W-1
CSIO1
R/W-1
CSIO0
bit0
bit7
bit 7-0
CSIO<7:0>: Chip Select IO Address Decode bits
XXh=All eight bits are compared to the Most Significant bits PC<20:13> of the program
counter. If PC<20:13> = CSIO<7:0>, then the CSIO signal is low. If not, CSIO is high.
00h=CSIO is inactive
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS39541A-page 70
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
A 00h value in the CSEL2 register will disable the CS2
signal and will configure the RF4 pin as I/O. Figure 5-9
shows an example address map for CS2.
5.4.1
CHIP SELECT 1 (CS1)
CS1 is enabled by writing a value other than 00h into
either the CSEL2 register, or the CSELIO register. If
both of the chip select registers are programmed to
00h, the CS1 signal is not enabled and the RF5 pin is
configured as I/O.
5.4.3
CHIP SELECT I/O (CSIO)
CSIO is enabled for a fixed 8K address range starting
at the address defined by the 8-bit value contained in
CSELIO. If, for instance, the value contained in the
CSELIO register is 80h, then the CSIO signal will be
low for the address range between 100000h and
101FFFh.
CS1 is low for all addresses in which CS2 and CSELIO
are high. Therefore, if CSEL2 = 20h and CSELIO = 80h,
then the CS1 signal will be low for the address that falls
between 000000h and (2000h x 20h) - 1 = 03FFFFh.
CS1 will always be low for the lower 8K of program
memory. Figure 5-9 shows an example address map for
CS1.
If the 8K address block overlaps the address range
specified in the CSEL2 register, the CSIO signal will be
low, and the CS2 signal will be high, for that region.
5.4.2
CHIP SELECT 2 (CS2)
A 00h value in the CSELIO register will disable the
CSIO signal and will configure the RF3 pin as I/O.
Figure 5-9 shows an example address map for CSIO.
CS2 is enabled for program memory accesses, starting
at the address derived by the 8-bit value contained in
CSEL2. For example, if the value contained in the
CSEL2 register is 80h, then the CS2 signal will be
asserted low whenever the address is greater than or
equal to 2000h x 80h = 100000h.
FIGURE 5-9:
EXAMPLE CONFIGURATION ADDRESS MAP FOR CS1, CS2, AND CSIO
CSEL2 = FFh (DEFAULT)
CSELIO = FFh (DEFAULT)
CSEL2 = 80h
CSELIO = 00h
CSEL2 = 20h
CSELIO = 80h
PROGRAM MEMORY
000000h
PROGRAM MEMORY
PROGRAM MEMORY
000000h
000000h
03FFFFh
040000h
0FFFFFh
100000h
0FFFFFh
100000h
101FFFh
102000h
1FFDFFh
1FFE00h
1FFDFFh
1FFE00h
1FFDFFh
1FFE00h
1FFFFFh
1FFFFFh
1FFFFFh
= CS1 ACTIVE
= CS2 ACTIVE
= CSIO ACTIVE
= NO CHIP SELECT ACTIVE
INTERNAL EXECUTION IF
PGRM = 1
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 71
PIC18C601/801
5.5
External Wait Cycles
The external memory interface supports wait cycles.
Wait cycles only apply to Table Read and Table Write
operations over the external bus. See Section 6.0 for
more details.
Since the device execution is tied to instruction fetches,
there is no need to execute faster than the fetch rate.
So, if the program needs to be slowed, the processor
speed must be slowed with a different TCY time.
DS39541A-page 72
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Table Read operations retrieve data from external pro-
gram memory and place it into the data memory space.
Figure 6-1 shows the operation of a Table Read with
program and data memory.
6.0
TABLE READS/TABLE WRITES
PIC18C601/801 devices use two memory spaces: the
external program memory space and the data memory
space. Table Reads and Table Writes have been pro-
vided to move data between these two memory spaces
through an 8-bit register (TABLAT).
Table Write operations store data from the data mem-
ory space into external program memory. Figure 6-2
shows the operation of a Table Write with external pro-
gram and data memory.
The operations that allow the processor to move data
between the data and external program memory
spaces are:
Table operations work with byte entities. A table block
containing data is not required to be word aligned, so a
table block can start and end at any byte address. If a
Table Write is being used to write an executable pro-
gram to program memory, program instructions must
be word aligned.
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 6-1:
TABLE READ OPERATION
(1)
Table Latch (8-bit)
TABLAT
Table Pointer
TBLPTRU TBLPTRH TBLPTRL
External Program Memory
Program Memory
(TBLPTR)
Instruction: TBLRD*
Note 1: Table Pointer points to a byte in external program memory.
FIGURE 6-2:
TABLE WRITE OPERATION
(1)
Table Latch (8-bit)
TABLAT
Table Pointer
TBLPTRU TBLPTRH TBLPTRL
External Program Memory
External
Program Memory
Instruction: TBLWT*
(TBLPTR)
Note 1: Table Pointer points to a byte in external program memory.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 73
PIC18C601/801
6.1.2
TBLPTR - TABLE POINTER
REGISTER
6.1
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include:
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte and Low byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 21-bit
wide pointer. The 21-bits allow the device to address up
to 2 Mbytes of program memory space.
• TABLAT register
• TBLPTR registers
6.1.1
TABLAT - TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program mem-
ory and data memory.
The table pointer TBLPTR is used by the TBLRDand
TBLWRT instructions. These instructions can update
the TBLPTR in one of four ways, based on the table
operation. These operations are shown in Table 6-1.
These operations on the TBLPTR only affect the low
order 21-bits.
TABLE 6-1:
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
DS39541A-page 74
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Table Reads from external program memory are
performed one byte at a time. If the external interface is
8-bit, the bus interface circuitry in TABLAT will load the
external value into TABLAT. If the external interface is
16-bit, interface circuitry in TABLAT will select either the
high or low byte of the data from the 16-bit bus, based
on the least significant bit of the address.
6.2
Table Read
The TBLRD instruction is used to retrieve data from
external program memory and place it into data
memory.
TBLPTR points to a byte address in external program
memory space. Executing TBLRDplaces the byte into
TABLAT. In addition, TBLPTR can be modified auto-
matically for the next Table Read operation.
Example 6-1describes how to use TBLRD. Figure 6-3
and Figure 6-4 show Table Read timings for an 8-bit
external interface, and Figure 6-5 describes Table
Read timing for a 16-bit interface.
EXAMPLE 6-1:
TABLE READ CODE EXAMPLE
; Read a byte from location 0020h
CLRF
CLRF
MOVLW
MOVWF
TBLRD*
TBLPTRU
TBLPTRH
20h
; clear upper 5 bits of TBLPTR
; clear higher 8 bits of TBLPTR
; Load 20h into
; TBLPTRL
; Data is in TABLAT
TBLPTRL
FIGURE 6-3:
TBLRD EXTERNAL INTERFACE TIMING (8-BIT MULTIPLEXED MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
A<15:8>
03Ah
03Ah
CCFh
03Ah
AAh
08h 00h
ABh
55h 0Eh
33h
92h
ACh
55h 0Fh
AD<7:0>
BA0
ALE
OE
’1’
’1’
WRH
WRL
’1’
’1’
Memory
Cycle
Opcode Fetch
Opcode Fetch
MOVLW 55h
from 007556h
TABLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 007558h
TBLRD*
from 007554h
Instruction
Execution
INST(PC-2)
TBLRD Cycle1
TBLRD Cycle2
MOVLW
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 75
PIC18C601/801
FIGURE 6-4:
TBLRD EXTERNAL INTERFACE TIMING (8-BIT DE-MULTIPLEXED MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
A<15:8>
03AAAh
03AABh
CCF33h
03AACh
55h
08h 00h
55h 0Eh
92h
AD<7:0>
BA0
ALE
OE
’1’
’1’
’1’
WRH
WRL
’1’
Opcode Fetch
Memory
Cycle
Opcode Fetch
MOVLW 55h
from 007556h
TABLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 007558h
TBLRD*
from 007554h
Instruction
Execution
INST(PC-2)
TBLRD Cycle1
TBLRD Cycle2
MOVLW
FIGURE 6-5:
TBLRD EXTERNAL BUS TIMING (16-BIT MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
A<19:16>
0h
0h
Ch
0h
3AAAh
3AABh
0008h
0E55h
0F55h
3AACh
CF33h
9256h
AD<15:0>
BA0
ALE
OE
’1’
’1’
’1’
WRH
WRL
’1’
Memory
Cycle
Opcode Fetch
Opcode Fetch
MOVLW 55h
from 007556h
TABLRD 92h
from 199E67h
Opcode Fetch
ADDLW 55h
from 007558h
TBLRD*
from 007554h
Instruction
Execution
INST(PC-2)
TBLRD Cycle1
TBLRD Cycle2
MOVLW
DS39541A-page 76
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
6.3
Table Write
Table Write operations store data from the data mem-
ory space into external program memory.
PIC18C601/801devices perform Table Writes one byte
at a time. Table Writes to external memory are two-cycle
instructions, unless wait states are enabled. The last
cycle writes the data to the external memory location.
16-bit interface Table Writes depend on the type of
external device that is connected and the WM<1:0>
bits in the MEMCON register (See Figure 5-2).
Example 6-2 describes how to use TBLWT.
EXAMPLE 6-2:
TABLE WRITE CODE EXAMPLE
; Write a byte to location 0020h
CLRF
CLRF
TBLPTRU
TBLPTRH
20h
TBLPTRL
55h
; clear upper 5 bits of TBLPTR
; clear higher 8 bits of TBLPTR
; Load 20h into
; TBLPTRL
; Load 55h into
MOVLW
MOVWF
MOVLW
MOVWF
TBLWT*
TBLAT
; TBLAT
; Write it
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 77
PIC18C601/801
6.3.1
8-BIT EXTERNAL TABLE WRITES
When the external bus is 8-bit, the byte-wide Table
Write exactly corresponds to the bus length and there
are no special considerations required.
The WRL signal is used as the active write signal.
Figure 6-6 and Figure 6-7 show the timings associated
with the 8-bit modes.
FIGURE 6-6:
TBLWT EXTERNAL INTERACE TIMING (8-BIT MULTIPLEXED MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
A<19:8>
03Ah
03Ah
CCFh
03Ah
AAh
ABh
ACh
08h 00h
55h 0Eh
55h 0Fh
92h
33h
AD<7:0>
BA0
ALE
OE
’1’
WRH
WRL
Memory
Cycle
Opcode Fetch
Opcode Fetch
MOVLW 55h
from 007556h
TBLWT 92h
to 199E67h
Opcode Fetch
ADDLW 55h
from 007558h
TBLWT*
from 007554h
Instruction
Execution
INST(PC-2)
TBLWT Cycle1
TBLWT Cycle2
MOVLW
DS39541A-page 78
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 6-7:
TBLWT EXTERNAL INTERFACE TIMING (8-BIT DE-MULTIPLEXED MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
A<19:8>
03Ah
03Ah
CCFh
03Ah
08h 00h
55h
0Fh
55h 0Eh
AD<7:0>
BA0
92h
ALE
OE
’1’
WRH
WRL
Memory
Cycle
Opcode Fetch
MOVLW 55h
from 007556h
Opcode Fetch
TBLWT*
from 007554h
TBLWT 92h
to 199E67h
Opcode Fetch
ADDLW 55h
from 007558h
Instruction
Execution
INST(PC-2)
TBLWT Cycle1
TBLWT Cycle2
MOVLW
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 79
PIC18C601/801
6.3.2
16-BIT EXTERNAL TABLE WRITE
(BYTE WRITE MODE)
This mode allows Table Writes to byte-wide external
memories. During a TBLWTcycle, the TABLAT data is
presented on the upper and lower byte of the
AD<15:0> bus. The appropriate WRH or WRL line is
strobed based on the LSb of the TBLPTR. Figure 6-8
shows the timing associated with this mode.
FIGURE 6-8:
TBLWT EXTERNAL INTERFACE TIMING (16-BIT BYTE WRITE MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16>
0h
0h
Ch
0h
0h
Ch
3AAAh
3AABh
3AACh
CF33h
000Dh
6FF4h
000Ch
9292h
CF33h
3AADh
5656h
0E55h
AD<15:0>
BA0
ALE
OE
WRH
WRL
UB
LB
Opcode Fetch
Opcode Fetch
TBLWT 56h
to 199E66h
Opcode Fetch
Opcode Fetch
TBLWT 92h
to 199E67h
Memory
Cycle
TBLWT*+
from 007554h
MOVWF TABLAT
from 007556h
TBLWT*
from 007558h
MOVLW 55h
from 00755Ah
Instruction
Execution
INST(PC-2)
TBLWT*+ Cycle1
TBLWT* Cycle1
TBLWT*+ Cycle2
MOVWF
TBLWT* Cycle2
DS39541A-page 80
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
During a TBLWT cycle to an odd address, where
TBLPTR<0> = 1, the TABLAT data is presented on the
upper byte of the AD<15:0> bus. The contents of the
holding latch are presented on the lower byte of the
AD<15:0> bus. The WRH line is strobed for each
write cycle and the WRL line is unused. The BA0 line
indicates the LSb of TBLPTR, but it is unnecessary.
The UB and LB lines are active to select both bytes.
6.3.3
EXTERNAL TABLE WRITE IN 16-BIT
WORD WRITE MODE
This mode allows Table Writes to any type of word-
wide external memories.
This method makes a distinction between TBLWT
cycles to even or odd addresses.
During a TBLWT cycle to an even address, where
TBLPTR<0> = 0, the TABLAT data is transferred to a
holding latch and the external address data bus is tri-
stated for the data portion of the bus cycle. No write
signals are activated.
The obvious limitation to this method is that the TBLWT
must be done in pairs on a specific word boundary to
correctly write a word location.
Figure 6-9 shows the timing associated with this mode.
FIGURE 6-9:
TBLWT EXTERNAL INTERFACE TIMING (16-BIT WORD WRITE MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16>
0h
0h
Ch
0h
0h
Ch
3AAAh
3AABh
3AACh
CF33h
000Dh
6FF4h
000Ch
9256h
CF33h
3AADh
0E55h
AD<15:0>
BA0
ALE
OE
WRH
WRL
’1’
UB
LB
Opcode Fetch
Opcode Fetch
Opcode Fetch
TBLWT 56h
to 199E66h
Opcode Fetch
TBLWT 92h
to 199E67h
Memory
Cycle
TBLWT*+
from 007554h
MOVLW 55h
from 00755Ah
TBLWT*
from 007558h
MOVWF TABLAT
from 007556h
Instruction
Execution
INST(PC-2)
TBLWT*+ Cycle1
TBLWT* Cycle1
TBLWT*+ Cycle2
MOVWF
TBLWT* Cycle2
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 81
PIC18C601/801
WRL line is unused. The BA0 or UB or UL lines are
used to select the byte to be written, based on the LSb
of the TBLPTR.
6.3.4
16-BIT EXTERNAL TABLE WRITE
(BYTE SELECT MODE)
This mode allows Table Writes to word-wide external
memories that have byte selection capabilities. This
generally includes word-wide FLASH devices and
word-wide static RAM devices.
JEDEC standard flash memories will require a I/O port
line to become a BYTE/WORD input signal and will
use the BA0 signal as a byte address. JEDEC stan-
dard static RAM memories will use the UB or UL sig-
nals to select the byte.
During a TBLWTcycle, the TABLAT data is presented
on the upper and lower byte of the AD<15:0> bus.
The WRH line is strobed for each write cycle and the
Figure 6-10 shows the timing associated with this mode.
FIGURE 6-10:
TBLWT EXTERNAL INTERFACE TIMING (16-BIT BYTE SELECT MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16>
0h
0h
Ch
0h
0h
Ch
3AAAh
3AABh
3AACh
CF33h
000Dh
6FF4h
000Ch
9292h
CF33h
3AADh
5656h
0E55h
AD<15:0>
BA0
ALE
OE
WRH
WRL
’1’
UB
LB
Opcode Fetch
Opcode Fetch
TBLWT 56h
to 199E66h
Opcode Fetch
Opcode Fetch
TBLWT 92h
to 199E67h
Memory
Cycle
TBLWT*+
from 007554h
MOVLW 55h
from 00755Ah
TBLWT*
from 007558h
MOVWF TABLAT
from 007556h
Instruction
Execution
INST(PC-2)
TBLWT*+ Cycle1
TBLWT* Cycle1
TBLWT*+ Cycle2
MOVWF
TBLWT* Cycle2
DS39541A-page 82
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
The WAIT<1:0> bits in the MEMCON register will select
0, 1, 2, or 3 extra TCY cycles per TBLRD/TBWLTcycle.
The wait will occur on Q4.
6.4
Long Writes
Long writes will not be supported on the PIC18C601/801
to program FLASH configuration memory. The configu-
ration locations can only be programmed in ICSP mode.
The default setting of the wait on power-up is to assert
a maximum wait of 3TCY cycles. This insures that slow
memories will work in Microprocessor mode immedi-
ately after RESET.
6.5
External Wait Cycles
The Table Reads and Writes have the capability to
insert wait states when accessing external memory.
These wait states only apply to the execution of a Table
Read or Write to external memory and not to instruction
fetches out of external memory. The guidelines pre-
sented in Section 5.0 must be followed to select the
proper memory speed grade for the device operating
frequency.
Figure 6-11 shows 8-bit external bus timing for a Table
Read with 2 wait cycles. Figure 6-12 shows 16-bit
external bus timing for a Table Read with 1 wait cycle.
FIGURE 6-11:
EXTERNAL INTERFACE TIMING (8-BIT MODE)
Q4 Q4 Q4 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q4 Q4 Q4
Apparent Q
Actual Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:8>
03Ah
CCFh
ABh 55h
33h
92h
0Eh
AD<7:0>
BA0
ALE
OE
2TCY Wait
Opcode Fetch
Table Read
of 92h
from 199E67h
MOVLW 55h
from 007556h
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 83
PIC18C601/801
FIGURE 6-12:
EXTERNAL INTERFACE TIMING (16-BIT MODE)
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q4
Q1
Q4
Q2
Q4
Q3
Q4
Q4
Apparent Q
Actual Q
A<19:16>
0h
0Ch
3AABh
CF33h
0E55h
9256h
AD<15:0>
BA0
ALE
OE
WRH
’1’
’1’
’1’
WRL ’1’
1TCY Wait
Opcode Fetch
Table Read
of 92h
from 199E67h
MOVLW 55h
from 007556h
DS39541A-page 84
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
The performance increase allows the device to be used
in some applications previously reserved for Digital
Signal Processors.
7.0
8 X 8 HARDWARE MULTIPLIER
An 8 x 8 hardware multiplier is included in the ALU of
PIC18C601/801 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the STATUS register.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
TABLE 7-1:
Routine
PERFORMANCE COMPARISON
Program
Time
Cycles
(Max)
Multiply Method
Memory
(Words)
@ 25 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
11.0 µs
160.0 ns
14.6 µs
960.0 ns
38.7 µs
3.8 µs
27.6 µs
400.0 ns
36.4 µs
2.4 µs
96.8 µs
9.6 µs
69.0 µs
1.0 µs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91.0 µs
6.0 µs
242.0 µs
24.0 µs
254.0 µs
36.0 µs
Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
40.6 µs
5.8 µs
102.6 µs
14.4 µs
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 85
PIC18C601/801
EXAMPLE 7-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
7.1
Operation
Example 7-1 shows the sequence to perform an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
MOVFF
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
;
;
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
;
;
MOVFF
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
ARG1L, WREG
ARG2H
MOVFF
MULWF
ARG1, WREG
ARG2
;
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
;
MOVFF
MULWF
ARG1H, WREG
ARG2L
;
MOVFF
MULWF
ARG1, WREG
ARG2
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
BTFSC
SUBWF
ARG2, SB
PRODH
;
- ARG1
MOVFF
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 7-4 shows the sequence to perform a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs’ most significant bit (MSb)
is tested and the appropriate subtractions are done.
Example 7-3 shows the sequence to perform a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EQUATION 7-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
(ARG1H • ARG2H • 2 )+
RES3:RES0
8
(ARG1H • ARG2L • 2 )+
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 2
8
16
(ARG1L • ARG2H • 2 )+
)
+
+
+
+
8
(ARG1L • ARG2L)
(ARG1H • ARG2L • 2 )
(ARG1L • ARG2H • 2 )
(ARG1L • ARG2L)
8
16
16
(-1 • ARG2H<7> • ARG1H:ARG1L • 2
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
)
)
+
DS39541A-page 86
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
EXAMPLE 7-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVFF
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
PRODH:PRODL
;
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
;
;
;
;
MOVFF
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
;
;
;
PRODH:PRODL
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVFF
MULWF
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
;
;
PRODH:PRODL
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
; Add cross
;
;
;
;
products
;
MOVFF
MULWF
ARG1H, WREG
ARG2L
;
; ARG1H * ARG2L ->
;
;
PRODH:PRODL
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1
PRODH, W
RES2
WREG
RES3
; Add cross
;
;
;
;
products
;
;
BTFSS
GOTO
MOVFF
SUBWF
MOVFF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG
RES2
ARG1H, WREG
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
SIGN_ARG1
BTFSS
GOTO
MOVFF
SUBWF
MOVFF
SUBWFB
;
ARG1H, 7
CONT_CODE
ARG2L, WREG
RES2
ARG2H, WREG
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
CONT_CODE
:
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 87
PIC18C601/801
NOTES:
DS39541A-page 88
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are
compatible with PICmicro® mid-range devices. In Com-
patibility mode, the interrupt priority bits for each source
have no effect. The PEIE bit (INTCON register)
enables/disables all peripheral interrupt sources. The
GIE bit (INTCON register) enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
8.0
INTERRUPTS
PIC18C601/801 devices have 15 interrupt sources and
an interrupt priority feature that allows each interrupt
source to be assigned a high priority level, or a low pri-
ority level. The high priority interrupt vector is at
000008h and the low priority interrupt vector is at
000018h. High priority interrupt events will override any
low priority interrupts that may be in progress.
There are 10 registers that are used to control interrupt
operation. These registers are:
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt prior-
ity levels are used, this will be either the GIEH or GIEL
bit. High priority interrupt sources can interrupt a low
priority interrupt.
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts, to avoid recursive interrupts.
It is recommended that the Microchip header files sup-
plied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The "return from interrupt" instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
Each interrupt source has three bits to control its oper-
ation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON register). When interrupt priority is
enabled, there are two bits that enable interrupts glo-
bally. Setting the GIEH bit (INTCON register) enables
all interrupts that have the priority bit set. Setting the
GIEL bit (INTCON register) enables all interrupts that
have the priority bit cleared. When the interrupt flag,
enable bit and appropriate global interrupt enable bit
are set, the interrupt will vector immediately to address
000008h or 000018h, depending on the priority level.
Individual interrupts can be disabled through their cor-
responding enable bits.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 89
PIC18C601/801
FIGURE 8-1:
INTERRUPT LOGIC
Wake-up if in SLEEP mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0F
INT0E
Interrupt to CPU
Vector to location
0008h
INT1F
INT1E
INT1P
INT2F
INT2E
INT2P
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIEH/GIE
TMR1IF
TMR1IE
TMR1IP
IPEN
IPEN
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR0IF
TMR0IE
TMR0IP
Interrupt to CPU
Vector to Location
0018h
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
RBIP
XXXXIF
XXXXIE
XXXXIP
GIEL\PEIE
INT0F
INT0E
INT1F
INT1E
INT1P
Additional Peripheral Interrupts
INT2F
INT2E
INT2P
DS39541A-page 90
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
8.1.1
INTCON REGISTERS
8.1
Control Registers
The INTCON Registers are readable and writable
registers, which contain various enable, priority, and
flag bits.
This section contains the control and status registers.
REGISTER 8-1:
INTCON REGISTER
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
R/W-x
RBIF
GIE/GIEH PEIE/GIEL TMR0IE
bit 7
INT0IE
TMR0IF INT0IF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all high priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 91
PIC18C601/801
REGISTER 8-2:
INTCON2 REGISTER
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
U-0
R/W-1
U-0
R/W-1
RBIP
INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 3
bit 2
Unimplemented: Read as ’0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as ’0’
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
DS39541A-page 92
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
REGISTER 8-3:
INTCON3 REGISTER
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
—
INT2IE
INT1IE
—
bit 7
bit 0
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ’0’
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as ’0’
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 93
PIC18C601/801
8.1.2
PIR REGISTERS
8.1.3
PIE REGISTERS
The Peripheral Interrupt Request (PIR) registers con-
tain the individual flag bits for the peripheral interrupts
(Register 8-5). There are two Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2).
The Peripheral Interrupt Enable (PIE) registers contain
the individual enable bits for the peripheral interrupts
(Register 8-6). There are two two Peripheral Interrupt
Enable registers (PIE1, PIE2). When IPEN is clear, the
PEIE bit must be set to enable any of these peripheral
interrupts.
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON register).
8.1.4
IPR REGISTERS
The Interrupt Priority (IPR) registers contain the individ-
ual priority bits for the peripheral interrupts (Register 8-9).
There are two Peripheral Interrupt Priority registers
(IPR1, IPR2). The operation of the priority bits requires
that the Interrupt Priority Enable bit (IPEN) be set.
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
8.1.5
RCON REGISTER
The Reset Control (RCON) register contains the bit that
is used to enable prioritized interrupts (IPEN).
REGISTER 8-4:
RCON REGISTER
R/W-0
IPEN
U-0
r
U-0
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
U-0
r
—
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6
bit 5
bit 4
Reserved: Maintain as '0'
Unimplemented: Read as '0'
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-4
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-4
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-4
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-4
Reserved: Maintain as '0'
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 94
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
REGISTER 8-5:
PIR1 REGISTER
U-0
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
CCP1IF TMR2IF TMR1IF
bit 0
R/W-0
R/W-0
—
RCIF
TXIF
bit 7
bit 7
bit 6
Unimplemented: Read as ’0’
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
(must be cleared in software)
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
bit 5
bit 4
bit 3
bit 2
1= The USART receive buffer, RCREG, is full
(cleared when RCREG is read)
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer, TXREG, is empty
(cleared when TXREG is written)
0= The USART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete
(must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred
(must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred
(must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred
(must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed
(must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 95
PIC18C601/801
REGISTER 8-6:
PIR2 REGISTER
U-0
U-0
U-0
U-0
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
TMR3IF CCP2IF
bit 0
R/W-0
—
—
—
—
bit 7
Unimplemented: Read as’0’
bit 7-4
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred
(must be cleared in software)
0= No bus collision occurred
bit 2
bit 1
bit 0
LVDIF: Low Voltage Detect Interrupt Flag bit
1= A low voltage condition occurred
(must be cleared in software)
0= The device voltage is above the Low Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed
(must be cleared in software)
0= TMR3 register did not overflow
CCP2IF: CCPx Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred
(must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred
(must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 96
AdvanceInformation
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PIC18C601/801
REGISTER 8-7:
PIE1 REGISTER
U-0
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE TMR2IE TMR1IE
bit 0
R/W-0
R/W-0
—
bit 7
bit 7
bit 6
Unimplemented: Read as ’0’
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 97
PIC18C601/801
REGISTER 8-8:
PIE2 REGISTER
U-0
U-0
U-0
U-0
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
TMR3IE CCP2IE
bit 0
R/W-0
—
—
—
—
bit 7
bit 7-4
bit 3
Unimplemented: Read as '0'
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
bit 2
bit 1
bit 0
LVDIE: Low Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enables the TMR3 overflow interrupt
0= Disables the TMR3 overflow interrupt
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 98
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REGISTER 8-9:
IPR1 REGISTER
U-0
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
CCP1IP TMR2IP TMR1IP
bit 0
R/W-1
R/W-1
—
bit 7
bit 7
bit 6
Unimplemented: Read as ’0’
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCIP: USART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: USART Transmit Interrupt Priority bit
1= High priority
0= Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 99
PIC18C601/801
REGISTER 8-10: IPR2 REGISTER
U-0
U-0
U-0
U-0
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
TMR3IP CCP2IP
bit 0
R/W-1
—
—
—
—
bit 7
bit 7-4
bit 3
Unimplemented: Read as '0'
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
bit 2
bit 1
bit 0
LVDIP: Low Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 100
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PIC18C601/801
in the TMR0H:TMR0L registers will set flag bit TMR0IF.
The interrupt can be enabled/disabled by setting/clear-
ing enable bit TMR0IE (INTCON register). Interrupt prior-
ity for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2 register). See
Section 10.0 for further details on the Timer0 module.
8.1.6
INT INTERRUPTS
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising, if the
corresponding INTEDGx bit is set in the INTCON2 reg-
ister, or falling, if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxIF is set. This interrupt can be disabled by
clearing the corresponding enable bit INTxIE. Flag bit
INTxIF must be cleared in software in the Interrupt Ser-
vice Routine before re-enabling the interrupt. All exter-
nal interrupts (INT0, INT1 and INT2) can wake-up the
processor from SLEEP, if bit INTxIE was set prior to
going into SLEEP. If the global interrupt enable bit GIE
is set, the processor will branch to the interrupt vector
following wake-up.
8.1.8
PORTB INTERRUPT-ON-CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON register). The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE (INTCON
register). Interrupt priority for PORTB interrupt-on-
change is determined by the value contained in the
interrupt priority bit RBIP (INTCON2 register).
8.2
Context Saving During Interrupts
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits INT1IP
(INTCON3 register) and INT2IP (INTCON3 register).
There is no priority bit associated with INT0; it is always
a high priority interrupt source.
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR regis-
ters are saved on the fast return stack. If a fast return
from interrupt is not used (See Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved. Example 8-1
saves and restores the WREG, STATUS and BSR
registers during an Interrupt Service Routine.
8.1.7
TMR0 INTERRUPT
In 8-bit mode (which is the default), an overflow
(0FFh → 00h) in the TMR0 register will set flag bit
TMR0IF. In 16-bit mode, an overflow (0FFFFh → 0000h)
EXAMPLE 8-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in Low Access bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
2001 Microchip Technology Inc.
Advance Information
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PIC18C601/801
NOTES:
DS39541A-page 102
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
EXAMPLE 9-1:
INITIALIZING PORTA
9.0
I/O PORTS
CLRF
PORTA
LATA
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
Depending on the device selected, there are up to 9
ports available. Some pins of the I/O ports are multi-
plexed with an alternate function from the peripheral
features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general
purpose I/O pin.
CLRF
MOVLW 07h
; Configure A/D
MOVWF ADCON1
MOVLW 0CFh
; for digital inputs
; Value used to
; initialize data
; direction
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
MOVWF TRISA
; Set RA3:RA0 as inputs
; RA5:RA4 as outputs
• LAT register (output latch)
The data latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are driving.
FIGURE 9-1:
RA3:RA0 AND RA5 PINS
BLOCK DIAGRAM
9.1
PORTA, TRISA and LATA
Registers
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
On a Power-on Reset, these pins are configured as
analog inputs and read as '0'.
RD LATA
Data
Bus
D
Q
VDD
WR LATA
or
WR PORTA
Q
Data Latch
CK
P
I/O pin(1)
N
D
Q
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
WR TRISA
VSS
Analog
Q
CK
Read-modify-write operations on the LATA register,
reads and writes the latched output value for PORTA.
Input
Mode
TRIS Latch
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
TTL
Input
Buffer
RD TRISA
Q
D
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1). On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
EN
RD PORTA
SS Input (RA5 only)
To A/D Converter and LVD Modules
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Note 1: I/O pins have diode protection to VDD and VSS.
Note: On
a Power-on Reset, PORTA pins
RA3:RA0 and RA5 default to analog inputs.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 103
PIC18C601/801
FIGURE 9-2:
RA4/T0CKI PIN BLOCK
DIAGRAM
RD LATA
Data
Bus
Q
D
WR LATA
or
WR PORTA
CK
Q
I/O pin(1)
N
Data Latch
D
Q
Q
VSS
WR TRISA
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
Note 1: I/O pin has diode protection to VSS only.
TABLE 9-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
bit5
TTL
TTL
TTL
TTL
Input/output or analog input
Input/output or analog input
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Input/output or analog input or VREF-
Input/output or analog input or VREF+
ST/OD Input/output or external clock input for Timer0, output is open drain type
RA5/SS/AN4/LVDIN
TTL
Input/output or slave select input for synchronous serial port or analog
input or low voltage detect input
Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain
TABLE 9-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on Value on all
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
PORTA
LATA
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 --uu uuuu
-xxx xxxx -uuu uuuu
-111 1111 -111 1111
Latch A Data Output Register
PORTA Data Direction Register
TRISA
ADCON1
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
DS39541A-page 104
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2 register). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
9.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output ( i.e.,
put the contents of the output latch on the selected pin).
Pin RB3 is multiplexed with the CCP input/output. The
weak pull-up for RB3 is disabled when the RB3 pin is
configured as CCP pin. By disabling the weak pull-up
when pin is configured as CCP, allows the remaining
weak pull-up devices of PORTB to be used while the
CCP is being used.
Read-modify-write operations on the LATB register
read and write the latched output value for PORTB.
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’d together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON register).
EXAMPLE 9-2:
INITIALIZING PORTB
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
LATB
MOVLW
MOVWF
0CFh
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
TRISB
; Set RB3:RB0 as inputs
; RB5:RB4 as outputs
; RB7:RB6 as inputs
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
FIGURE 9-3:
RB7:RB4 PINS BLOCK
DIAGRAM
VDD
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
RBPU(2)
Data Bus
Weak
Pull-up
P
Data Latch
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
D
Q
I/O pin(1)
WR LATB
or
WR PORTB
CK
TRIS Latch
D
Q
WR TRISB
TTL
Input
Buffer
CK
ST
Buffer
RD TRISB
RD LATB
Latch
Q
Q
D
EN
Q1
RD PORTB
Set RBIF
D
From other
RB7:RB4 pins
RD PORTB
Q3
EN
RBx/INTx
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2 register).
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 105
PIC18C601/801
FIGURE 9-4:
RB2:RB0 PINS BLOCK
DIAGRAM
VDD
RBPU(2)
Weak
P
Pull-up
Data Latch
Data Bus
WR Port
D
Q
I/O pin(1)
CK
TRIS Latch
D
Q
TTL
WR TRIS
Input
CK
Buffer
RD TRIS
RD Port
Q
D
EN
Schmitt Trigger
Buffer
RBx/INTx
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
FIGURE 9-5:
RB3 PIN BLOCK DIAGRAM
VDD
Weak
RBPU(2)
CCP Enable
P
Pull-up
CCP Output
1
0
VDD
P
Enable
CCP Output
Data Latch
I/O pin(1)
Data Bus
D
Q
WR LATB or
WR PORTB
N
CK
TRIS Latch
VSS
Q
D
TTL
WR TRISB
Input
CK
Q
Buffer
RD TRISB
RD LATB
Q
D
EN
RD PORTB
RD PORTB
CCP2 Input
Schmitt Trigger
Buffer
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
DS39541A-page 106
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 9-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT0
bit0
TTL/ST(1) Input/output pin or external interrupt 0 input. Internal software
programmable weak pull-up.
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL/ST(1) Input/output pin or external interrupt 1 input. Internal software
programmable weak pull-up.
TTL/ST(1) Input/output pin or external interrupt 2 input. Internal software
programmable weak pull-up.
TTL/ST(3) Input/output pin or Capture2 input or Capture2 output or PWM2 output.
Internal software programmable weak pull-up.
TTL
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6
TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock.
TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data.
RB7
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This pin is a Schmitt Trigger input when configured as the external interrupt.
2: This pin is a Schmitt Trigger input when used in Serial Programming mode.
3: This pin is a Schmitt Trigger input when used in a Capture input.
TABLE 9-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 000x 0000 000u
1111 1111 1111 1111
1100 0000 1100 0000
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
LATB
LATB Data Output Register
PORTB Data Direction Register
TRISB
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INTCON2 RBPU
INTCON3 INT2IP
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTD.
INT0IE
RBIE
TMR0IF INT0IF RBIF
RBIP
INT2IF INT1IF
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT1IP INT2IE INT1IE
—
—
—
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 107
PIC18C601/801
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
9.3
PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
EXAMPLE 9-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
LATC
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
MOVLW
MOVWF
0CFh
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
TRISC
; Set RC3:RC0 as inputs
; RC5:RC4 as outputs
; RC7:RC6 as inputs
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to make
a pin an input. The user should refer to the correspond-
ing peripheral section for the correct TRIS bit settings.
FIGURE 9-6:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Peripheral Out Select
Peripheral Data Out
V
DD
0
1
P
(1)
I/O pin
RD LATC
Q
Data Bus
D
WR LATC
or
Q
CK
TRIS OVERRIDE
Pin Override Peripheral
WR PORTC
Data Latch
N
D
Q
Q
RC0
Yes
Timer1 OSC for
Timer1/Timer3
V
SS
WR TRISC
TRIS
Override
CK
RC1
Yes
Timer1 OSC for
Timer1/Timer3
TRIS Latch
RC2
RC3
No
—
Schmitt
Trigger
RD TRISC
2
Yes
Peripheral Enable
SPI/I C Master Clock
2
RC4
Yes
I C Data Out
Q
D
RC5
RC6
Yes
Yes
SPI Data Out
EN
USART Async Xmit,
Sync Clock
RD PORTC
Peripheral Data In
RC7
Yes
USART Sync Data Out
Note 1: I/O pins have diode protection to VDD and VSS.
DS39541A-page 108
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 9-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
RC0/T1OSO/T13CKI bit0
ST
Input/output port pin or Timer1 oscillator output or Timer1/Timer3
clock input.
RC1/T1OSI
RC2/CCP1
bit1
bit2
ST
ST
Input/output port pin, Timer1 oscillator input.
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
bit3
bit4
ST
ST
Input/output port pin or synchronous serial clock for SPI/I2C.
Input/output port pin or SPI Data in (SPI mode) or Data I/O
(I2C mode).
RC5/SDO
bit5
bit6
ST
ST
Input/output port pin or Synchronous Serial Port Data output.
RC6/TX/CK
Input/output port pin, Addressable USART Asynchronous Transmit, or
Addressable USART Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin, Addressable USART Asynchronous Receive, or
Addressable USART Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 9-6:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
POR,
Value on all
other
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
xxxx xxxx
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
1111 1111
PORTC
LATC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
LATC Data Output Register
PORTC Data Direction Register
TRISC
Legend: x= unknown, u= unchanged
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 109
PIC18C601/801
FIGURE 9-7:
PORTD BLOCK DIAGRAM
IN I/O MODE
9.4
PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISD bit (= 0) will
make the corresponding PORTD pin an output (i.e., put
the contents of the output latch on the selected pin).
RD LATD
Data Bus
D
Q
I/O pin
WR LATD
or
WR PORTD
CK
Data Latch
Read-modify-write operations on the LATD register
reads and writes the latched output value for PORTD.
D
Q
Schmitt
Trigger
Input
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
WR TRISD
CK
TRIS Latch
Buffer
PORTD is multiplexed with the system bus and is avail-
able only when the system bus is disabled, by setting
EBIDS bit in register MEMCON. When operating as
the system bus, PORTD is the low order byte of the
address/data bus (AD7:AD0), or as the low order
address byte (A15:A8) if the address and data buses
are de-multiplexed.
RD TRISD
Q
D
EN
RD PORTD
Note: On a Power-on Reset, PORTD defaults to
the system bus.
Note: I/O pins have diode protection to VDD and VSS.
EXAMPLE 9-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
CLRF
LATD
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0CFh
; Value used to
; initialize data
; direction
; Set RD3:RD0 as inputs
; RD5:RD4 as outputs
; RD7:RD6 as inputs
TRISD
DS39541A-page 110
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 9-8:
PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTD
RD LATD
(1)
I/O pin
Port
Data Bus
D
Q
0
1
Data
WR LATD
or
CK
PORTD
Data Latch
D
Q
WR TRISD
TTL
Input
Buffer
CK
TRIS Latch
RD TRISD
Bus Enable
Data/TRIS Out
Drive Bus
System Bus
Control
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 111
PIC18C601/801
TABLE 9-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
Function
RD0/AD0/A0(2)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin or system bus bit 0
Input/output port pin or system bus bit 1
Input/output port pin or system bus bit 2
Input/output port pin or system bus bit 3
Input/output port pin or system bus bit 4
Input/output port pin or system bus bit 5
Input/output port pin or system bus bit 6
Input/output port pin or system bus bit 7
RD1/AD1/A1(2)
RD2/AD2/A2(2)
RD3/AD3/A3(2)
RD4/AD4/A4(3)
RD5/AD5/A5(2)
RD6/AD6/A6(2)
RD7/AD7/A7(2)
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode.
2: RDx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an
address only for PIC18C801 in 8-bit mode.
TABLE 9-8:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
POR,
Value on all
other
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
BOR
RESETS
xxxx xxxx
xxxx xxxx
1111 1111
0000 --00
uuuu uuuu
uuuu uuuu
1111 1111
0000 --00
PORTD
LATD
RD7
RD6
RD5
RD4
RD3 RD2 RD1 RD0
LATD Data Output Register
TRISD
PORTD Data Direction Register
MEMCON
EBDIS
PGRM
WAIT1
WAIT0
—
—
WM1 WM0
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS39541A-page 112
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
byte of the address/data bus (AD15:AD8), or as the
high order address byte (A15:A8), if address and data
buses are de-multiplexed.
9.5
PORTE, TRISE and LATE
Registers
PORTE is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
Note: On Power-on Reset, PORTE defaults to
the system bus.
EXAMPLE 9-5:
INITIALIZING PORTE
CLRF
PORTE
LATE
03h
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
Read-modify-write operations on the LATE register
reads and writes the latched output value for PORTE.
CLRF
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with several peripheral
functions (Table 9-9).
MOVLW
MOVWF
TRISE
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
PORTE is multiplexed with the system bus and is avail-
able only when the system bus is disabled, by setting
EBDIS bit in register MEMCON. When operating as the
system bus, PORTE is configured as the high order
FIGURE 9-9:
PORTE BLOCK DIAGRAM IN I/O MODE
Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
(1)
I/O pin
RD LATE
Q
Data Bus
D
WR LATE
or
WR PORTE
CK
Q
Data Latch
N
D
Q
Q
TRIS OVERRIDE
Pin Override Peripheral
VSS
WR TRISE
TRIS
Override
CK
TRIS Latch
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
Schmitt
Trigger
RD TRISE
Peripheral Enable
Q
D
EN
RD PORTE
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 113
PIC18C601/801
FIGURE 9-10:
PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTE
RD LATD
I/O pin(1)
Port
Data Bus
D
Q
0
1
Data
WR LATE
or
PORTE
CK
Data Latch
TRIS Latch
D
Q
WR TRISE
TTL
Input
Buffer
CK
RD TRISE
External Enable
System Bus
Control
Data/Address Out
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
DS39541A-page 114
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 9-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/AD8/A8(2)
RE1/AD9/A9(2)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin or Address/Data bit 8
Input/output port pin or Address/Data bit 9
Input/output port pin or Address/Data bit 10
Input/output port pin or Address/Data bit 11
Input/output port pin or Address/Data bit 12
Input/output port pin or Address/Data bit 13
Input/output port pin or Address/Data bit 14
Input/output port pin or Address/Data bit 15
RE2/AD10/A10(2)
RE3/AD11/A11(2)
RE4/AD12/A12(2)
RE5/AD13/A13(2)
RE6/AD14/A14(2)
RE7/AD15/A15(2)
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode.
2: REx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an
address only for PIC18C801 in 8-bit mode.
TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
1111 1111
xxxx xxxx
xxxx xxxx
0000 --00
1111 1111
uuuu uuuu
uuuu uuuu
0000 --00
TRISE
PORTE
LATE
PORTE Data Direction Control Register
Read PORTE pin/Write PORTE Data Latch
Read PORTE Data Latch/Write PORTE Data Latch
EBDIS PGRM WAIT1 WAIT0
MEMCON
—
—
WM1
WM0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTE.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 115
PIC18C601/801
EXAMPLE 9-7:
PROGRAMMING CHIP
SELECT SIGNALS
9.6
PORTF, LATF, and TRISF
Registers
•
•
PORTF is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISF. Setting a
TRISF bit (= 1) will make the corresponding PORTF pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISF bit (= 0) will
make the corresponding PORTF pin an output (i.e., put
the contents of the output latch on the selected pin).
; Program chip select to activate CS1
; for all address less than 03FFFFh,
; while activate CS2 for rests of the
; addresses
; CSEL2 register is secured register.
; Before it can be modified it,
; combination lock must be opened
Read-modify-write operations on the LATF register
reads and writes the latched output value for PORTF.
MOVLW 20h
; Preload WREG with
; correct CSEL2 valu
; Disable interrupts
; Now unlock it
PORTF pins, RF2:RF0, are multiplexed with analog
inputs. The operation of these pins are selected by
ADCON0 and ADCON1 registers.
BCF INTCON, GIE
CALL UNLOCK
; Lock is open. Modify CSEL2...
MOVWF CSEL2
PORTF pins, RF3 and RF5, are multiplexed with two of
the integrated chip select signals CSIO and CS1. For
PIC18C801, pin RF4 is multiplexed with chip select sig-
nal CS2, while for PIC18C601, it is multiplexed with
system bus signal A16. For PIC18C801 devices, both
CSEL2 and CSELIO registers must set to all zero, to
enable these pins as I/O pins, while for PIC18C601
devices, only CSELIO register needs to be set to zero.
For PIC18C601 devices, pin RF4 can only be config-
ured as I/O when the EBDIS bit is set and execution is
taking place in internal Boot RAM.
; Lock is closed
BSF INTCON, GIE
; Chip select is programmed.
; Re-enable interrupts
•
•
UNLOCK
BSF PSPCON, CMLK1
BSF PSPCON, CMLK0
RETURN
•
•
PORTF pins, RF7:RF6, are multiplexed with the sys-
tem bus control signal UB and LB, respectively, when a
device with 16-bit bus execution is used. These pins
can be configured as I/O pins by setting WM bits in the
MEMCON register to any value other than ’01’.
FIGURE 9-11:
RF2:RF0 PINS BLOCK
DIAGRAM
Note 1: On Power-on Reset, PORTF pins
RD LATF
RF2:RF0 default to A/D inputs.
Data Bus
D
Q
2: On Power-on Reset, PORTF pins
RF7:RF3 for PIC18C801 and pins
RF7:RF5, RF3 for PIC18C601, default to
system bus signals.
VDD
P
WR LATF
or
WR PORTF
CK
Q
Data Latch
I/O pin
N
D
Q
EXAMPLE 9-6:
INITIALIZING PORTF
WR TRISF
VSS
Analog
CK
TRIS Latch
Q
CLRF
PORTF
; Initialize PORTF by
; clearing output
; data latches
Input
Mode
CLRF
LATF
; Alternate method
; to clear output
; data latches
ST
RD TRISF
Q
Input
Buffer
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
;
D
; Set PORTF as digital I/O
; Value used to
; initialize data
; direction
EN
RD PORTF
MOVWF
TRISF
; Set RF3:RF0 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
To A/D Converter
Note: I/O pins have diode protection to VDD and VSS.
DS39541A-page 116
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 9-12:
RF5:RF3 PINS BLOCK DIAGRAM
Q
D
EN
RD PORTF
RD LATF
I/O pin(1)
Port
Data Bus
D
Q
0
1
Data
WR LATF
or
CK
PORTF
Data Latch
TRIS Latch
D
Q
WR TRISF
CK
RD TRISF
CS Out
System Bus
Control
External Enable
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 9-13:
RF7:RF6 PINS BLOCK DIAGRAM
Q
D
EN
RD PORTF
RD LATF
I/O pin(1)
Data Bus
Port
D
Q
0
1
Data
WR LATF
or
PORTF
CK
Data Latch
TRIS Latch
D
Q
WR TRISF
CK
RD TRISF
UB/LB Out
System Bus
WM = ’01’
Control
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 117
PIC18C601/801
TABLE 9-11: PORTF FUNCTIONS
Name
Bit#
Buffer Type
Function
Input/output port pin or analog input
RF0/AN5
RF1/AN6
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output port pin or analog input
RF2/AN7
Input/output port pin or analog input
RF3/CSIO
RF4/A16/CS2(1)
RF5/CS1
Input/output port pin or I/O chip select
Input/output port pin or chip select 2 or address bit 16
Input/output port pin or chip select 1
RF6/LB
Input/output port pin or low byte select signal for external memory
Input/output port pin or high byte select signal for external memory
RF7/UB
Legend: ST = Schmitt Trigger input
Note 1: CS2 is available only on PIC18C801.
TABLE 9-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Value on:
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
1111 1111
xxxx xxxx
0000 0000
--00 0000
1111 1111
uuuu uuuu
uuuu uuuu
--00 0000
TRISF
PORTF
LATF
PORTF Data Direction Control Register
Read PORTF pin/Write PORTF Data Latch
Read PORTF Data Latch/Write PORTF Data Latch
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
PGRM WAIT1 WAIT0 WM1 WM0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTF.
ADCON1
—
—
0000 --00
0000 --00
MEMCON EBDIS
—
—
DS39541A-page 118
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 9-14:
PORTG BLOCK DIAGRAM
IN I/O MODE
9.7
PORTG, LATG, and TRISG
Registers
PORTG is a 5-bit wide, bi-directional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISG bit (= 0) will
make the corresponding PORTG pin an output (i.e., put
the contents of the output latch on the selected pin).
RD LATG
Data
Bus
D
Q
I/O pin(1)
WR LATG
or
PORTG
CK
Data Latch
Read-modify-write operations on the LATG register
read and write the latched output value for PORTG.
D
Q
PORTG is multiplexed with system bus control signals
ALE, OE, WRH, WRL and BA0. The WRH signal is the
only signal that is disabled and configured as a port pin
(RG3) during external program execution in 8-bit mode.
All other pins are by default, system bus control sig-
nals. PORTG can be configured as an I/O port by set-
ting EBDIS bit in the MEMCON register and when
execution is taking place in internal program RAM.
Schmitt
Trigger
Input
WR TRISG
CK
TRIS Latch
Buffer
RD TRISG
Q
D
Note: On Power-on Reset, PORTG defaults to
EN
system bus signals.
RD PORTG
EXAMPLE 9-8:
INITIALIZING PORTG
Note 1: I/O pins have diode protection to VDD and VSS.
CLRF
PORTG
LATG
04h
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
MOVLW
MOVWF
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as outputs
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 119
PIC18C601/801
FIGURE 9-15:
PORTG BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTG
RD LATG
I/O pin(1)
Data Bus
Port
D
Q
0
1
Data
WR LATG
or
PORTG
CK
Data Latch
D
Q
WR TRISG
CK
TRIS Latch
RD TRISG
Control Out
System Bus
Control
External Enable
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
TABLE 9-13: PORTG FUNCTIONS
Name
Bit#
Buffer Type
Function
RG0/ALE
RG1/OE
bit0
bit1
bit2
bit3
bit4
ST
ST
ST
ST
ST
Input/output port pin or Address Latch Enable signal for external memory
Input/output port pin or Output Enable signal for external memory
Input/output port pin or Write Low byte signal for external memory
Input/output port pin or Write High byte signal for external memory
Input/output port pin or Byte Address 0 signal for external memory
RG2/WRL
RG3/WRH
RG4/BA0
Legend: ST = Schmitt Trigger input
TABLE 9-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Value on:
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
BOR
RESETS
---1 1111
---x xxxx
---x xxxx
0000 --00
---1 1111
---u uuuu
---u uuuu
0000 --00
TRISG
PORTG
LATG
PORTG Data Direction Control Register
Read PORTG pin/Write PORTG Data Latch
Read PORTG Data Latch/Write PORTG Data Latch
EBDIS PGRM WAIT1 WAIT0
MEMCON
—
—
WM1 WM0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTG.
DS39541A-page 120
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 9-16:
RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE
9.8
PORTH, LATH, and TRISH
Registers
Note: PORTH is available only on PIC18C801
devices.
RD LATH
Data
Bus
PORTH is an 8-bit wide, bi-directional I/O port. The cor-
responding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISH bit (= 0) will
make the corresponding PORTH pin an output (i.e., put
the contents of the output latch on the selected pin).
D
Q
I/O pin(1)
WR LATH
or
PORTH
CK
Data Latch
D
Q
Read-modify-write operations on the LATH register
read and write the latched output value for PORTH.
Schmitt
Trigger
Input
WR TRISH
CK
TRIS Latch
Buffer
Pins RH7:RH4 are multiplexed with analog inputs
AN18:AN11, while pins RH3:RH0 are multiplexed with
system address bus A19:A16. By default, pins
RH7:RH4 will setup as A/D inputs and pins RH3:RH0
will setup as system address bus. Register ADCON1
configures RH7:RH4 as I/O or A/D inputs. Register
MEMCON configures RH3:RH0 as I/O or system bus
pins.
RD TRISH
Q
D
EN
RD PORTH
Note 1: On Power-on Reset, PORTH pins
RH7:RH4 default to A/D inputs and read
as ’0’.
Note 1: I/O pins have diode protection to VDD and VSS.
2: On Power-on Reset, PORTH pins
RH3:RH0 default to system bus signals.
FIGURE 9-17:
RH7:RH4 PINS BLOCK
DIAGRAM
EXAMPLE 9-9:
INITIALIZING PORTH
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
;
RD LATH
Data
Bus
D
Q
CLRF
LATH
I/O pin(1)
WR LATH
or
PORTH
CK
Data Latch
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
;
; Value used to
; initialize data
; direction
D
Q
Schmitt
Trigger
Input
WR TRISH
CK
TRIS Latch
MOVWF
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
Buffer
RD TRISH
Q
D
EN
RD PORTH
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 121
PIC18C601/801
FIGURE 9-18:
RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTH
RD LATD
I/O pin(1)
Data Bus
Port
D
Q
0
1
Data
WR LATH
or
PORTH
CK
Data Latch
D
Q
WR TRISH
TTL
Input
Buffer
CK
TRIS Latch
RD TRISH
External Enable.
Address Out
System Bus
Control
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
DS39541A-page 122
AdvanceInformation
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PIC18C601/801
TABLE 9-15: PORTH FUNCTIONS
Name
Bit#
Buffer Type
Function
RH0/A16(1)
RH1/A17(1)
RH2/A18(1)
RH3/A19(1)
RH4/AN8(1)
RH5/AN9(1)
RH6/AN10(1)
RH7/AN11(1)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output port pin or Address bit 16 for external memory interface
Input/output port pin or Address bit 17 for external memory interface
Input/output port pin or Address bit 18 for external memory interface
Input/output port pin or Address bit 19 for external memory interface
Input/output port pin or analog input channel 8
Input/output port pin or analog input channel 9
Input/output port pin or analog input channel 10
Input/output port pin or analog input channel 11
Legend: ST = Schmitt Trigger input
Note 1: PORTH is available only on PIC18C801 devices.
TABLE 9-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Value on:
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
1111 1111
xxxx xxxx
xxxx xxxx
--00 0000
0000 --00
1111 1111
uuuu uuuu
uuuu uuuu
--00 0000
0000 --00
TRISH
PORTH Data Direction Control Register
PORTH Read PORTH pin/Write PORTH Data Latch
LATH
Read PORTH Data Latch/Write PORTH Data Latch
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
WM1 WM0
ADCON1
—
—
MEMCON EBDIS PGRM WAIT1 WAIT0
—
—
Legend: x= unknown, u= unchanged, - = unimplemented. Shaded cells are not used by PORTH.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 123
PIC18C601/801
FIGURE 9-19:
PORTJ BLOCK DIAGRAM
IN I/O MODE
9.9
PORTJ, LATJ, and TRISJ
Registers
Note: PORTJ is available only on PIC18C801
devices.
RD LATJ
Data
Bus
PORTJ is an 8-bit wide, bi-directional I/O port. The cor-
responding data direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
D
Q
I/O pin(1)
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
Read-modify-write operations on the LATJ register
read and write the latched output value for PORTJ.
Schmitt
Trigger
Input
WR TRISJ
CK
TRIS Latch
Buffer
PORTJ is multiplexed with de-multiplexed system data
bus D7:D0, when device is configured in 8-bit execution
mode. Register MEMCON configures PORTJ as I/O or
system bus pins.
RD TRISJ
Note: On Power-on Reset, PORTJ defaults to
Q
D
system bus signals.
EN
RD PORTJ
EXAMPLE 9-10:
INITIALIZING PORTJ
Note 1: I/O pins have diode protection to VDD and VSS.
CLRF
PORTJ
; Initialize PORTJ by
; clearing output
; data latches
CLRF
LATJ
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0CFh
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as outputs
; RJ7:RJ6 as inputs
TRISJ
DS39541A-page 124
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 9-20:
PORTJ BLOCK DIAGRAM IN SYSTEM DATA BUS MODE
Q
D
EN
RD PORTJ
RD LATD
I/O pin(1)
Data Bus
Port
D
Q
0
1
Data
WR LATJ
or
PORTJ
CK
Data Latch
TRIS Latch
D
Q
WR TRISJ
TTL
Input
Buffer
CK
S
R
RD TRISJ
External Enable
Data Out
System Bus
Control
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 125
PIC18C601/801
TABLE 9-17: PORTJ FUNCTIONS
Name
Bit#
Buffer Type
Function
RJ0/D0(1)
RJ1/D1(1)
RJ2/D2(1)
RJ3/D3(1)
RJ4/D4(1)
RJ5/D5(1)
RJ6/D6(1)
RJ7/D7(1)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
Input/output port pin or Data bit 0 for external memory interface
Input/output port pin or Data bit 1 for external memory interface
Input/output port pin or Data bit 2 for external memory interface
Input/output port pin or Data bit 3 for external memory interface
Input/output port pin or Data bit 4 for external memory interface
Input/output port pin or Data bit 5 for external memory interface
Input/output port pin or Data bit 6 for external memory interface
Input/output port pin or Data bit 7 for external memory interface
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: PORTJ is available only on PIC18C801 devices.
TABLE 9-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Value on:
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
1111 1111
xxxx xxxx
xxxx xxxx
0000 --00
1111 1111
uuuu uuuu
uuuu uuuu
0000 --00
TRISJ
PORTJ
LATJ
PORTJ Data Direction Control Register
Read PORTJ pin/Write PORTJ Data Latch
Read PORTJ Data Latch/Write PORTJ Data Latch
MEMCON EBDIS PGRM WAIT1 WAIT0
—
—
WM1
WM0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTJ.
DS39541A-page 126
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Register 10-1 shows the Timer0 Control register
(T0CON).
10.0 TIMER0 MODULE
The Timer0 module has the following features:
Figure 10-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 10-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Software selectable as an 8-bit or 16-bit timer/
counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
The T0CON register is a readable and writable register
that controls all the aspects of Timer0, including the
prescale selection.
• Interrupt on overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
Note: Timer0 is enabled on POR.
• Edge select for external clock
REGISTER 10-1: T0CON REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
T08BIT
bit 0
bit 7
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
bit 6
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4
bit 3
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0
T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 prescale value
110= 1:128 prescale value
101= 1:64 prescale value
100= 1:32 prescale value
011= 1:16 prescale value
010= 1:8 prescale value
001= 1:4 prescale value
000= 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 127
PIC18C601/801
FIGURE 10-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
FOSC/4
0
1
8
0
Sync with
Internal
Clocks
TMR0L
RA4/T0CKI
pin(2)
Programmable
Prescaler
1
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS(1)
Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
2: I/O pins have diode protection to VDD and VSS.
FIGURE 10-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4
0
0
Sync with
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
Internal
Clocks
1
TMR0L
Programmable
Prescaler
RA4/T0CKI
pin(2)
1
8
(2 TCY delay)
T0SE
3
Read TMR0L
Write TMR0L
T0PS2, T0PS1, T0PS0
T0CS(1)
PSA
8
8
TMR0H
8
Data Bus<7:0>
Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
2: I/O pins have diode protection to VDD and VSS.
DS39541A-page 128
AdvanceInformation
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PIC18C601/801
10.2.1
SWITCHING PRESCALER
ASSIGNMENT
10.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0L reg-
ister is written, the increment is inhibited for the follow-
ing two instruction cycles. The user can work around
this by writing an adjusted value to the TMR0L register.
10.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IF bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut-off during SLEEP.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising, or falling edge, of pin RA4/T0CKI. The incre-
menting edge is determined by the Timer0 Source
Edge Select bit (T0SE). Clearing the T0SE bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
10.4 16-Bit Mode Timer Reads and
Writes
Timer0 can be set in 16-bit mode by clearing T0CON
T08BIT. Registers TMR0H and TMR0L are used to
access 16-bit timer value.
10.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 10-1). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16-bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0,
MOVWF TMR0, BSF TMR0, x.... etc.) will clear the
prescaler count.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of the buffered value of
TMR0H, when a write occurs to TMR0L. This allows all
16-bits of Timer0 to be updated at once.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 000x 0000 000u
1111 1111 1111 1111
--11 1111 --11 1111
TMR0L Timer0 Module’s Low Byte Register
TMR0H Timer0 Module’s High Byte Register
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
TRISA PORTA Data Direction Register
—
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 129
PIC18C601/801
Register 11-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module as well as contains the Timer1 oscillator enable
bit (T1OSCEN). Timer1 can be enabled/disabled by
setting/clearing control bit TMR1ON (T1CON register).
11.0 TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(Two 8-bit registers: TMR1H and TMR1L)
Figure 11-1 is a simplified block diagram of the Timer1
module.
• Readable and writable (both registers)
• Internal or external clock select
Note: Timer1 is disabled on POR.
• Interrupt on overflow from FFFFh to 0000h
• RESET from CCP module special event trigger
REGISTER 11-1: T1CON REGISTER
R/W-0
RD16
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register Read/Write of TImer1 in one 16-bit operation
0= Enables register Read/Write of Timer1 in two 8-bit operations
bit 6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1=Timer1 Oscillator is enabled
0=Timer1 Oscillator is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 130
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1 incre-
ments on every rising edge of the external clock input
or the Timer1 oscillator, if enabled.
11.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC<1:0> value is ignored.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
Timer1 also has an internal “RESET input”. This RESET
can be generated by the CCP module (Table 14.0).
Note: When Timer1 is configured in an Asyn-
chronous mode, care must be taken to
make sure that there is no incoming pulse
while Timer1 is being turned off. If there is
an incoming pulse while Timer1 is being
turned off, Timer1 value may become
unpredictable.
If an application requires that Timer1 be
turned off and if it is possible that Timer1
may receive an incoming pulse while being
turned off, synchronize the external clock
first, by clearing the T1SYNC bit of register
T1CON. Please note that this may cause
Timer1 to miss up to one count.
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag Bit
Synchronized
TMR1
CLR
0
Clock Input
TMR1L
TMR1H
T1OSC
1
TMR1ON
On/Off
T1SYNC
1
T13CKI/T1OSO
T1OSI
Synchronize
Prescaler
T1OSCEN
Enable
Oscillator
1, 2, 4, 8
det
FOSC/4
Internal
Clock
(1)
0
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 131
PIC18C601/801
FIGURE 11-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
Special Event Trigger
0
Synchronized
Clock Input
TMR1IF
Overflow
Interrupt
Flag bit
TMR1
8
Timer 1
High Byte
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
T13CKI/T1OSO
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
FOSC/4
Internal
Clock
Enable
0
(1)
T1OSI
Oscillator
2
SLEEP Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
DS39541A-page 132
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PIC18C601/801
11.2 Timer1 Oscillator
11.4 Resetting Timer1 using a CCP
Trigger Output
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON register). The
oscillator is a low power oscillator rated up to 200 kHz.
It will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 11-1 shows the
capacitor selection for the Timer1 oscillator.
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger"
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR registers).
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
Timer1 must be configured for either Timer, or Synchro-
nized Counter mode, to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
TABLE 11-1: CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR
In the event that a write to Timer1 coincides with a special
event trigger from CCP1, the write will take precedence.
Osc Type
Freq
C1
C2
LP
32 kHz
TBD(1)
TBD(1)
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair, effectively becomes the period register for
Timer1.
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A
20 PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
11.5 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit (T1CON
register) is set, the address for TMR1H is mapped to a
buffer register for the high byte of Timer1. A read from
TMR1L will load the contents of the high byte of Timer1
into the Timer1 high byte buffer. This provides the user
with the ability to accurately read all 16 bits of Timer1,
without having to determine whether a read of the high
byte followed by a read of the low byte is valid, due to
a rollover between reads.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
4: Capacitor values are for design guidance
only.
11.3 Timer1 Interrupt
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16-bits
to both the high and low bytes of Timer1 at once.
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR1IF (PIR regis-
ters). This interrupt can be enabled/disabled by setting/
clearing TMR1 interrupt enable bit TMR1IE (PIE
registers).
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 133
PIC18C601/801
TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PIE1
IPR1
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF
CCP1IE TMR2IE
CCP1IP TMR2IP
TMR1IF -000 0000 -000 0000
TMR1IE -000 0000 -000 0000
TMR1IP -000 0000 -000 0000
xxxx xxxx uuuu uuuu
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
DS39541A-page 134
AdvanceInformation
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12.1 Timer2 Operation
12.0 TIMER2 MODULE
Timer2 can be used as the PWM time-base for the PWM
mode of the CCP module. The TMR2 register is read-
able and writable, and is cleared on any device RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
1:4,
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON register). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2
interrupt (latched in flag bit TMR2IF, PIR registers).
• SSP module optional use of TMR2 output to
generate clock shift
The prescaler and postscaler counters are cleared
when any of the following occurs:
Register 12-1 shows the Timer2 Control register.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON register), to minimize power consumption.
Figure 12-1 is a simplified block diagram of the Timer2
module. The prescaler and postscaler selection of
Timer2 are controlled by this register.
• A write to the TMR2 register
• A write to the T2CON register
• Any device RESET (Power-on Reset, MCLR
Reset, or Watchdog Timer Reset)
TMR2 is not cleared when T2CON is written.
Note: Timer2 is disabled on POR.
REGISTER 12-1: T2CON REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 135
PIC18C601/801
12.2 Timer2 Interrupt
12.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The output of TMR2 (before the postscaler) is a clock
input to the Synchronous Serial Port module, which
optionally uses it to generate the shift clock.
FIGURE 12-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output(1)
Prescaler
RESET
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
2
Comparator
PR2
1:16
1:1 to
EQ
T2CKPS1:T2CKPS0
4
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PIE1
IPR1
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF
CCP1IE
CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR1IF -000 0000 -000 0000
TMR1IE -000 0000 -000 0000
TMR1IP -000 0000 -000 0000
0000 0000 0000 0000
TMR2 Timer2 Module’s Register
T2CON
PR2
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
DS39541A-page 136
AdvanceInformation
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PIC18C601/801
Figure 13-1 is a simplified block diagram of the Timer3
module.
13.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
Register 13-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
• 16-bit timer/counter
(Two 8-bit registers: TMR3H and TMR3L)
Register 11-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable bit (T1OSCEN), which can be a clock source for
Timer3.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• RESET from CCP module trigger
Note: Timer3 is disabled on POR.
REGISTER 13-1: T3CON REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable
1= Enables register Read/Write of Timer3 in one 16-bit operation
0= Enables register Read/Write of Timer3 in two 8-bit operations
bit 6,3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x=Timer3 is the clock source for compare/capture CCP modules
01=Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00=Timer1 is the clock source for compare/capture CCP modules
bit 5-4
bit 2
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first
falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 137
PIC18C601/801
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
13.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON register).
Timer3 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 13.0).
FIGURE 13-1:
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
TMR3IF
T3CCPx
Synchronized
Overflow
Interrupt
Flag bit
0
Clock Input
CLR
TMR3L
TMR3H
T1OSC
1
TMR3ON
On/Off
T3SYNC
(3)
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
Oscillator
T1OSI
2
SLEEP Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
FIGURE 13-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Trigger
T3CCPx
0
Synchronized
Clock Input
8
TMR3
TMR3IF Overflow
Interrupt Flag
bit
CLR
TMR3H
TMR3L
1
TMR3ON
On/Off
To Timer1 Clock Input
T3SYNC
T1OSC
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
SLEEP Input
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
DS39541A-page 138
AdvanceInformation
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PIC18C601/801
13.2 Timer1 Oscillator
13.4 Resetting Timer3 Using a CCP
Trigger Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN bit (T1CON Register). The oscillator is
a low power oscillator rated up to 200 kHz. Refer to
“Timer1 Module”, Section 11.0, for Timer1 oscillator
details.
If the CCP module is configured in Compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Note: The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR registers).
13.3 Timer3 Interrupt
Timer3 must be configured for either Timer, or Synchro-
nized Counter mode, to take advantage of this feature. If
Timer3 is running in Asynchronous Counter mode, this
RESET operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L registers pair
becomes the period register for Timer3. Refer to
Section 14.0, “Capture/Compare/PWM (CCP) Modules”,
for CCP details.
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR3IF (PIE
registers). This interrupt can be enabled/disabled by
setting/clearing TMR3 interrupt enable bit TMR3IE
(PIE registers).
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
PIE2
IPR2
—
—
—
—
—
—
—
—
—
—
—
—
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
CCP2IF ---- 0000 -0-- 0000
TMR3IE CCP2IE ---- 0000 -0-- 0000
TMR3IP CCP2IP ---- 0000 -0-- 0000
TMR3L Holding register for the Least Significant Byte of the 16-bit TMR3 register
TMR3H Holding register for the Most Significant Byte of the 16-bit TMR3 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
T3CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer3 module.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 139
PIC18C601/801
NOTES:
DS39541A-page 140
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module in the following sections is
described, with respect to CCP1.
14.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register that can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
Duty Cycle register. Table 14-1 shows the timer
resources of the CCP module modes.
Table 14-2 shows the interaction of the CCP modules.
Register 14-1 shows the CCPx Control registers
(CCPxCON). For the CCP1 module, the register is
called CCP1CON and for the CCP2 module, the regis-
ter is called CCP2CON.
REGISTER 14-1: CCP1CON REGISTER
CCP2CON REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP1CON
CCP2CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode,
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
1001= Compare mode,
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
1010= Compare mode,
Generate software interrupt on compare match
(CCPIF bit is set, CCP pin is unaffected)
1011= Compare mode,
Trigger special event (CCPIF bit is set, reset TMR1 or TMR3)
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 141
PIC18C601/801
14.1 CCP1 Module
14.3 Capture Mode
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers, when an event
occurs on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
14.2 CCP2 Module
• every 4th rising edge
• every 16th rising edge
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR registers) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old cap-
tured value will be lost.
TABLE 14-1: CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
14.3.1
CCP PIN CONFIGURATION
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Note: If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
14.3.2
TIMER1/TIMER3 MODE SELECTION
The timers used with the capture feature (either Timer1
and/or Timer3) must be running in Timer mode or Syn-
chronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer
used with each CCP module is selected in the T3CON
register.
TABLE 14-2: INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Capture
TMR1 or TMR3 time-base. Time-base can be different for each CCP.
Compare The compare could be configured for the special event trigger, which clears either TMR1
or TMR3, depending upon which time-base is used.
Compare
Compare The compare(s) could be configured for the special event trigger, which clears TMR1 or
TMR3, depending upon which time-base is used.
PWM
PWM
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
None.
Capture
Compare None.
DS39541A-page 142
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 14-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
14.3.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE registers) clear to avoid false interrupts
and should clear the flag bit CCP1IF, following any
such change in operating mode.
14.3.4
CCP PRESCALER
EXAMPLE 14-1:
CHANGING BETWEEN
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
CAPTURE PRESCALERS
CLRF
CCP1CON, F ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP1CON
; Load CCP1CON with
; this value
FIGURE 14-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
CCPR1L
TMR1L
RC2/CCP1 pin
Set Flag bit CCP1IF
T3CCP2
TMR3
Enable
Prescaler
÷ 1, 4, 16
RXB0IF or
RXB1IF
CCPR1H
TMR1
CCP1CON<3:0>
and
edge detect
T3CCP2
Enable
TMR1H
CCP1M3:CCP1M0
Q’s
Set Flag bit CCP2IF
T3CCP1
TMR3H
TMR3L
CCPR2L
TMR1L
T3CCP2
TMR3
Enable
Prescaler
÷ 1, 4, 16
RC1/CCP2 pin
CCPR2H
TMR1
and
edge detect
Enable
T3CCP2
T3CCP1
TMR1H
CCP2M3:CCP2M0
Q’s
Note: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 143
PIC18C601/801
14.4.2
TIMER1/TIMER3 MODE SELECTION
14.4 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value, or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
can have one of the following actions:
14.4.3
SOFTWARE INTERRUPT MODE
• Driven high
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
• Driven low
• Toggle output (high to low or low to high)
• Remains unchanged
14.4.4
SPECIAL EVENT TRIGGER
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set.
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
14.4.1
CCP PIN CONFIGURATION
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
The special trigger output of CCPx resets either the
TMR1, or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion, if the
A/D module is enabled.
Note: The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
FIGURE 14-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)
Set bit GO/DONE, which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
Match
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
RC2/CCP1
pin
TRISC<2>
Output Enable
1
CCP1M3:CCP1M0
Mode Select
0
T3CCP2
TMR1H TMR1L
TMR3H TMR3L
Special Event Trigger
Set Flag bit CCP2IF
T3CCP1
T3CCP2
0
1
Q
S
R
Output
Logic
Comparator
Match
RC1/CCP2
pin
TRISC<1>
Output Enable
CCPR2H CCPR2L
CCP2M3:CCP2M0
Mode Select
Note: I/O pins have diode protection to VDD and VSS.
DS39541A-page 144
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PIE1
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IP TMR2IP TMR1IP -000 0000 -000 0000
1111 1111 1111 1111
IPR1
TRISC
TMR1L
TMR1H
T1CON
PORTC Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
CCPR1L Capture/Compare/PWM Register1 (LSB)
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
CCPR2L Capture/Compare/PWM Register2 (LSB)
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
PIR2
—
—
—
—
—
—
—
—
DC2B1
—
DC2B0
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF ---- 0000 ---- 0000
TMR3IE CCP2IE ---- 0000 ---- 0000
TMR3IP CCP2IP ---- 0000 ---- 0000
PIE2
—
—
IPR2
—
—
TMR3L
TMR3H
T3CON
Holding register for the Least Significant Byte of the 16-bit TMR3 register
Holding register for the Most Significant Byte of the 16-bit TMR3 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 145
PIC18C601/801
14.5.1
PWM PERIOD
14.5 PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated by the
formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
where PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 14-3 shows a simplified block diagram of the
CCP module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step-by-step procedure on how to setup the CCP
module for PWM operation, see Section 14.5.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: The Timer2 postscaler (see Section 12.1)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a dif-
ferent frequency than the PWM output.
FIGURE 14-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L (Master)
14.5.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Comparator
Q
R
S
RC2/CCP1
(Note 1)
TMR2
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
TRISC<2>
Comparator
PR2
Clear Timer,
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
CCP1 pin and
latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, or
2 bits of the prescaler, to create 10-bit time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 14-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
FIGURE 14-4:
PWM OUTPUT
Period
FOSC
---------------
log
FPWM
PWM Resolution (max)
= ----------------------------- b i t s
log(2)
Duty Cycle
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
DS39541A-page 146
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2001 Microchip Technology Inc.
PIC18C601/801
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
14.5.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
1. Set the PWM period by writing to the PR2
register.
5. Configure the CCP1 module for PWM operation.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 25 MHz
PWM Frequency
1.53 kHz 6.10 kHz 24.41 kHz
97.66kHz 195.31 kHz 260.42 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.6
Maximum Resolution (bits)
TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PIE1
IPR1
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF
TMR1IF -000 0000 -000 0000
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IP TMR2IP TMR1IP -000 0000 -000 0000
1111 1111 1111 1111
TRISC PORTC Data Direction Register
TMR2
PR2
Timer2 Module’s Register
0000 0000 0000 0000
Timer2 Module’s Period Register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM Register1 (LSB)
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
CCPR2L Capture/Compare/PWM Register2 (LSB)
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
PIR2
—
—
—
—
—
—
—
—
DC2B1
—
DC2B0
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
CCP2IF ---- 0000 ---- 0000
PIE2
—
—
TMR3IE CCP2IE ---- 0000 ---- 0000
TMR3IP CCP2IP ---- 0000 ---- 0000
IPR2
—
—
Legend: x= unknown, u= unchanged, — = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 147
PIC18C601/801
NOTES:
DS39541A-page 148
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
15.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
15.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral InterfaceTM (SPI)
• Inter-Integrated CircuitTM (I2C)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
2001 Microchip Technology Inc.
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PIC18C601/801
Register 15-1 shows the MSSP Status Register
(SSPSTAT), Register 15-2 shows the MSSP Control
Register 1 (SSPCON1), and Register 15-3 shows the
MSSP Control Register 2 (SSPCON2).
15.2 Control Registers
The MSSP module has three associated registers.
These include a status register and two control registers.
REGISTER 15-1: SSPSTAT REGISTER
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
2
In I C Master or Slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select
CKP = 0:
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
CKP = 1:
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
2
bit 5
bit 4
D/A: Data/Address bit (I C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0= START bit was not detected last
2
R/W: Read/Write bit Information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or not ACK bit.
2
In I C Slave mode:
1= Read
0= Write
2
In I C Master mode:
1= Transmit is in progress
0= Transmit is not in progress.
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
2
bit 1
bit 0
UA: Update Address (10-bit I C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
2
Transmit (I C mode only):
1= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 150
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REGISTER 15-2: SSPCON1 REGISTER
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master mode:
2
1= A write to the SSPBUF register was attempted while the I C conditions were not valid for a
transmission to be started
0= No collision
Slave mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of
overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the
user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master
mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing
to the SSPBUF register. (Must be cleared in software.)
0= No overflow
2
In I C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
"don’t care" in Transmit mode. (Must be cleared in software.)
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
2
In I C mode:
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
2
In I C Slave mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
2
In I C Master mode:
Unused in this mode
bit 3 - 0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
2
0110= I C Slave mode, 7-bit address
2
2
0111= I C Slave mode, 10-bit address
1000= I C Master mode, clock = FOSC / (4 * (SSPADD+1) )
1001= Reserved
1010= Reserved
2
1011= I C firmware controlled Master mode (Slave idle)
1100= Reserved
1101= Reserved
2
1110= I C Slave mode, 7-bit address with START and STOP bit interrupts enabled
2
1111= I C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
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PIC18C601/801
REGISTER 15-3: SSPCON2 REGISTER
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
GCEN: General Call Enable bit (In I2C Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
bit 3
bit 2
RCEN: Receive Enable bit (In I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
PEN: STOP Condition Enable bit (In I2C Master mode only)
SCK release control
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0= STOP condition idle
bit 1
bit 0
RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1= Initiate Repeated START condition on SDA and SCL pins. Automatically cleared
by hardware.
0= Repeated START condition idle
SEN: START Condition Enabled bit (In I2C Master mode only)
1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0= START condition idle
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 152
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 15-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
15.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
Internal
Data Bus
Read
Write
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
SSPBUF reg
Additionally, a fourth pin may be used when in any
Slave mode of operation:
SSPSR reg
Shift
SDI
bit0
• Slave Select (SS) - RA5/SS/AN4
Clock
15.3.1
OPERATION
SDO
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits SSPCON1<5:0> and SSPSTAT<7:6>.
These control bits allow the following to be specified:
Control
SS
Enable
SS
Edge
Select
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock polarity (Idle state of SCK)
2
Clock Select
• Data input sample phase (middle or end of data
output time)
SSPM3:SSPM0
• Clock edge (output data on rising/falling edge of
SCK)
SMP:CKE
2
4
TMR2 Output
(
)
2
• Clock rate (Master mode only)
Edge
Select
TOSC
Prescaler
4, 16, 64
• Slave Select mode (Slave mode only)
SCK
Figure 15-1 shows the block diagram of the MSSP
module, when in SPI mode.
Data to TX/RX in SSPSR
TRIS bit
Note: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 153
PIC18C601/801
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF (SSPSTAT
register), and the interrupt flag bit, SSPIF (PIR regis-
ters), are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1 register), will be set. User software must
clear the WCOL bit so that it can be determined if the
following write(s) to the SSPBUF register completed
successfully.
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP status register (SSPSTAT
register) indicates the various status conditions.
15.3.2
ENABLING SPI I/O
To enable the serial port, SSP enable bit, SSPEN
(SSPCON1 register), must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, corresponding pins must have their data direction
bits (in the TRIS register) appropriately programmed.
That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
buffer full (BF) bit (SSPSTAT register) indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 15-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
• RA5 must be configured as digital I/O using
ADCON1 register
• SS must have TRISA<5> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
EXAMPLE 15-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF
BRA LOOP
;Has data been received (transmit complete)?
;No
MOVF SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS39541A-page 154
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1 register). This, then,
would give waveforms for SPI communication as
shown in Figure 15-2, Figure 15-4, and Figure 15-5,
where the MSb is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
15.3.3
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave is to broadcast data by the software
protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 25 MHz) of 6.25
Mbps.
Figure 15-2 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 15-2:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit6
bit6
bit2
bit2
bit5
bit5
bit4
bit4
bit1
bit1
bit0
bit0
SDO
(CKE = 0)
bit7
bit7
bit3
bit3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 155
PIC18C601/801
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
15.3.4
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Note 1: When the SPI is in Slave mode with SS
pin control enabled, (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times, as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level, or clearing the SSPEN bit.
15.3.5
SLAVE SELECT
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The data latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
FIGURE 15-3:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit7
bit7
bit0
bit0
SDO
bit7
SDI
(SMP = 0)
bit7
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
SSPSR to
SSPBUF
after Q2↓
DS39541A-page 156
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2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 15-4:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit3
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 15-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Required
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit7
bit3
SDI
(SMP = 0)
bit0
Input
Sample
(SMP = 0)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
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Advance Information
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PIC18C601/801
15.3.6
SLEEP OPERATION
15.3.8
BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 15-1 shows the compatibility between the stan-
dard SPI modes and the states of the CKP and CKE
control bits.
TABLE 15-1: SPI BUS MODES
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the
device from SLEEP.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
15.3.7
EFFECTS OF A RESET
There is also a SMP bit that controls when the data will
be sampled.
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
RESETS
0000 000x 0000 000u
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE
GIEL
RBIE
TMR0IF INT0IF
RBIF
PIR1
PIE1
IPR1
-000 0000 -000 0000
-000 0000 -000 0000
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
SSPIP CCP1IP TMR2IP TMR1IP
-000 0000 -000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
TRISC PORTC Data Direction Register
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON WCOL SSPOV SSPEN
TRISA
CKP
SSPM3 SSPM2 SSPM1 SSPM0
--11 1111 --11 1111
0000 0000 0000 0000
—
PORTA Data Direction Register
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'.
Shaded cells are not used by the MSSP in SPI mode.
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The SSPCON1 register allows control of the I2C oper-
ation. The SSPM3:SSPM0 mode selection bits
(SSPCON1 register) allow one of the following I2C
modes to be selected:
• I2C Master mode, clock = OSC/(4*(SSPADD +1))
• I2C Slave mode (7-bit address)
2
15.4 MSSP I C Operation
The MSSP module in I2C mode, fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (Multi-Master
mode). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
• I2C firmware controlled master operation, slave is
idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The MSSP module functions are enabled by setting
MSSP Enable bit SSPEN (SSPCON1 register).
The MSSP module has these six registers for I2C oper-
ation:
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
15.4.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
• MSSP Shift Register (SSPSR) - Not directly
accessible
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse and
load the SSPBUF register with the received value cur-
rently in the SSPSR register.
• MSSP Address Register (SSPADD)
FIGURE 15-6:
MSSP BLOCK DIAGRAM
(I2C MODE)
If either or both of the following conditions are true, the
MSSP module will not give this ACK pulse:
Internal
Data Bus
a) The buffer full bit BF (SSPCON1 register) was
set before the transfer was received.
Read
Write
b) The overflow bit SSPOV (SSPCON1 register)
was set before the transfer was received.
SSPBUF reg
RC3/SCK/SCL
Shift
Clock
In this event, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR registers) is set.
The BF bit is cleared by reading the SSPBUF register,
while bit SSPOV is cleared through software.
SSPSR reg
RC4/
SDI/
MSb
LSb
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, is shown in timing parameter #100 and
parameter #101.
SDA
Addr Match
Match Detect
SSPADD reg
START and
Set, RESET
S, P bits
(SSPSTAT reg)
STOP bit Detect
Note: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
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PIC18C601/801
15.4.1.1
Addressing
15.4.1.2
Reception
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the eight bits are shifted into the SSPSR register.
All incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT register) is
set or bit SSPOV (SSPCON1 register) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR registers) must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit BF is set.
c) An ACK pulse is generated.
15.4.1.3
Transmission
d) MSSP interrupt flag bit SSPIF (PIR registers) is
set on the falling edge of the ninth SCL pulse
(interrupt is generated, if enabled).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON1 register). The master must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
by stretching the clock. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 15-8).
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSb) of the first address byte, specify if this is a 10-bit
address. The R/W bit (SSPSTAT register) must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘1111 0 A9 A8 0’, where A9and A8are the
two MSb’s of the address.
The sequence of events for 10-bit addressing is as fol-
lows, with steps 7- 9 for slave-transmitter:
1. Receive first (high) byte of address (the SSPIF,
BF and UA bits (SSPSTAT register) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT reg-
ister) and the slave monitors for another occurrence of
the START bit. If the SDA line was low (ACK), the trans-
mit data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Pin RC3/SCK/SCL
should be enabled by setting bit CKP.
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated START condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
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PIC18C601/801
FIGURE 15-7:
I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
A7 A6 A5 A4
R/W = 0
Receiving Data
Receiving Data
ACK
Not ACK
D0
ACK
9
SDA
A3 A2 A1
D5
D2
D0
8
D5
D2
D7 D6
D4 D3
D1
7
D7 D6
D4 D3
D1
7
1
2
3
4
5
6
9
1
2
3
4
9
8
5
6
1
2
3
4
5
6
7
8
P
SCL
S
SSPIF
Bus Master
Terminates
Transfer
BF
Cleared in software
SSPBUF register is read
SSPOV
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
FIGURE 15-8:
I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
Receiving Address
A7 A6 A5 A4 A3 A2 A1
R/W = 1
ACK
Transmitting Data
Not ACK
SDA
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
SCL held low
while CPU
responds to SSPIF
Data in
Sampled
SSPIF
BF
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
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If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF bit is set (eighth bit),
and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
15.4.2
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT register). If the general call address
is sampled when the GCEN bit is set and while the
slave is configured in 10-bit address mode, then the
second half of the address is not necessary. The UA bit
will not be set, and the slave will begin receiving data
after the Acknowledge (Figure 15-9).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized (enabled) when
the General Call Enable (GCEN) bit is set (SSPCON2
register). Following a START bit detect, eight bits are
shifted into the SSPSR and the address is compared
against the SSPADD. It is also compared to the general
call address and fixed in hardware.
FIGURE 15-9:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
ACK
General Call Address
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF
Cleared in software
SSPBUF is read
SSPOV
GCEN
’0’
’1’
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PIC18C601/801
1. Assert a START condition on SDA and SCL.
15.4.3
MASTER MODE
2. Assert a Repeated START condition on SDA
and SCL.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I2C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
3. Write to the SSPBUF register initiating transmis-
sion of data/address.
4. Generate a STOP condition on SDA and SCL.
5. Configure the I2C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
Note: The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START condition
15.4.4
I2C MASTER MODE SUPPORT
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
2
FIGURE 15-10:
MSSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
SCL
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Note: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
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PIC18C601/801
I2C Master Mode Operation
A typical transmit sequence would go as follows:
15.4.4.1
a) The user generates a START condition by set-
ting the START enable (SEN) bit (SSPCON2
register).
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I2C bus will not be released.
b) SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
c) The user loads the SSPBUF with the address to
transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ’0’. Serial data is
transmitted eight bits at a time. After each byte is trans-
mitted, an Acknowledge bit is received. START and
STOP conditions are output to indicate the beginning
and the end of a serial transfer.
d) Address is shifted out the SDA pin until all eight
bits are transmitted.
e) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
f) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ’1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ’1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received eight bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. START and STOP conditions indicate the begin-
ning and end of transmission.
g) The user loads the SSPBUF with eight bits of
data.
h) Data is shifted out the SDA pin until all eight bits
are transmitted.
i) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The baud rate generator used for the SPI mode opera-
tion is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I2C operation. The
baud rate generator reload value is contained in the
lower 7 bits of the SSPADD register. The baud rate
generator will automatically begin counting on a write to
the SSPBUF. Once the given operation is complete
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.
k) The user generates a STOP condition by setting
the STOP enable bit PEN (SSPCON2 register).
l) Interrupt is generated once the STOP condition
is complete.
15.4.5
BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 15-11). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
remented twice per instruction cycle (TCY) on the Q2
and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically. If clock arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 15-12).
FIGURE 15-11:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
BRG Down Counter
CLKOUT
FOSC/4
DS39541A-page 164
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PIC18C601/801
FIGURE 15-12:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
reload
15.4.6
I2C MASTER MODE START
CONDITION TIMING
Note: If at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag
BCLIF is set, the START condition is
aborted, and the I2C module is reset into its
IDLE state.
To initiate a START condition, the user sets the START
Condition Enable (SEN) bit (SSPCON2 register). If the
SDA and SCL pins are sampled high, the baud rate
generator is re-loaded with the contents of
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the baud rate generator times
out (TBRG), the SDA pin is driven low. The action of the
SDA being driven low while SCL is high, is the START
condition, and causes the S bit (SSPSTAT register) to
be set. Following this, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
resumes its count. When the baud rate generator times
out (TBRG), the SEN bit (SSPCON2 register) will be
automatically cleared by hardware, the baud rate gen-
erator is suspended leaving the SDA line held low and
the START condition is complete.
15.4.6.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 15-13:
FIRST START BIT TIMING
Set S bit (SSPSTAT)
Write to SEN bit occurs here
SDA = 1,
At completion of START bit,
Hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
2nd bit
1st bit
SDA
TBRG
SCL
TBRG
S
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PIC18C601/801
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
15.4.7
I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated START condition occurs when the RSEN
bit (SSPCON2 register) is programmed high and the
I2C logic module is in the IDLE state. When the RSEN
bit is set, the SCL pin is asserted low. When the SCL
pin is sampled low, the baud rate generator is loaded
with the contents of SSPADD<5:0> and begins count-
ing. The SDA pin is released (brought high) for one
baud rate generator count (TBRG). When the baud rate
generator times out, if SDA is sampled high, the SCL pin
will be de-asserted (brought high). When SCL is sam-
pled high, the baud rate generator is re-loaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin (SDA
15.4.7.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
= 0) for one TBRG while SCL is high. Following this, the
,
RSEN bit (SSPCON2 register) will be automatically
cleared and the baud rate generator will not be reloaded,
leaving the SDA pin held low. As soon as a START con-
dition is detected on the SDA and SCL pins, the S bit
(SSPSTAT register) will be set. The SSPIF bit will not be
set until the baud rate generator has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs, if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 15-14:
REPEATED START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SDA = 1,
SCL = 1
At completion of START bit,
hardware clear RSEN bit
and set SSPIF
SCL (no change)
TBRG
TBRG
TBRG
1st Bit
SDA
Write to SSPBUF occurs here
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated START
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I2C MASTER MODE
TRANSMISSION
15.4.8.2 WCOL Status Flag
15.4.8
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address, is accomplished by sim-
ply writing a value to the SSPBUF register. This action
will set the Buffer Full bit, BF, and allow the baud rate
generator to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter 106). SCL
is held low for one baud rate generator rollover count
(TBRG). Data should be valid before SCL is released
high (see data setup time specification parameter 107).
When the SCL pin is released high, it is held that way
for TBRG. The data on the SDA pin must remain stable
for that duration and some hold time after the next fall-
ing edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF bit is cleared
and the master releases SDA, allowing the slave
device being addressed to respond with an ACK bit
during the ninth bit time, if an address match occurs, or
if data was received properly. The status of ACK is writ-
ten into the ACKDT bit on the falling edge of the ninth
clock. If the master receives an Acknowledge, the
Acknowledge Status bit, ACKSTAT, is cleared; if not,
the bit is set. After the ninth clock, the SSPIF bit is set
and the master clock (baud rate generator) is
suspended until the next data byte is loaded into the
SSPBUF, leaving SCL low and SDA unchanged
(Figure 15-15).
WCOL must be cleared in software.
15.4.8.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2
register) is cleared when the slave has sent an
Acknowledge (ACK = 0), and is set when the slave
does not Acknowledge (ACK = 1). A slave sends an
Acknowledge when it has recognized its address
(including a general call), or when the slave has
properly received its data.
15.4.9
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2 register).
Note: The MSSP module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.
The baud rate generator begins counting and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the RCEN bit is
automatically cleared, the contents of the SSPSR are
loaded into the SSPBUF, the BF bit is set, the SSPIF
flag bit is set and the baud rate generator is suspended
from counting, holding SCL low. The MSSP is now in
IDLE state, awaiting the next command. When the
buffer is read by the CPU, the BF bit is automatically
cleared. The user can then send an Acknowledge bit at
the end of reception, by setting the Acknowledge
Sequence Enable bit ACKEN (SSPCON2 register).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit, are completed. On the
falling edge of the eighth clock, the master will de-
assert the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2
register). Following the falling edge of the ninth clock
transmission of the address, the SSPIF is set, the BF
bit is cleared and the baud rate generator is turned off,
until another write to the SSPBUF takes place, holding
SCL low and allowing SDA to float.
15.4.9.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
15.4.9.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF bit is
already set from a previous reception.
15.4.8.1
BF Status Flag
In Transmit mode, the BF bit (SSPSTAT register) is set
when the CPU writes to SSPBUF, and is cleared when
all eight bits are shifted out.
15.4.9.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
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2
FIGURE 15-15:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS39541A-page 168
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2
FIGURE 15-16:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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15.4.10 ACKNOWLEDGE SEQUENCE
TIMING
15.4.11 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2 register). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT register) is set.
A TBRG later, the PEN bit is cleared and the SSPIF bit
is set (Figure 15-18).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence enable bit, ACKEN (SSPCON2
register). When this bit is set, the SCL pin is pulled low
and the contents of the Acknowledge Data bit (ACKDT)
is presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (TBRG) and the
SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for TBRG. The SCL pin is then pulled low. Fol-
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 15-17).
15.4.11.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the contents
of the buffer are unchanged (the write doesn’t occur).
15.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t occur).
FIGURE 15-17:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDA
SCL
D0
8
9
SSPIF
Cleared in
Set SSPIF at the end
of receive
Cleared in
software
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
FIGURE 15-18:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high, P bit (SSPSTAT) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to set up STOP condition
Note: TBRG = one baud rate generator period.
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15.4.12 CLOCK ARBITRATION
15.4.13 SLEEP OPERATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 15-19).
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
15.4.14 EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
FIGURE 15-19:
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1, load BRG with
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SSPADD<6:0> and start count
to measure high time interval
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (TOSC² 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
TBRG
TBRG
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SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag (BCLIF) and reset the
I2C port to its IDLE state. (Figure 15-20).
15.4.15 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET, or
when the MSSP module is disabled. Control of the I2C
bus may be taken when the P bit (SSPSTAT register) is
set, or the bus is idle, with both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the STOP condition
occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF bit is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
In Multi-Master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
Arbitration can be lost in the following states:
• Address transfer
• Data transfer
• A START condition
• A Repeated START condition
• An Acknowledge condition
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be
set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
15.4.16 MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
FIGURE 15-20:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by Master
SDA
Set bus collision
interrupt (BCLIF)
SCL
BCLIF
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If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 15-23). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pin is
sampled as '0', a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
15.4.16.1 Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 15-21).
b) SCL is sampled low before SDA is asserted low
(Figure 15-22).
During a START condition, both the SDA and the SCL
pins are monitored.
Note: The reason that bus collision is not a factor
during a START condition, is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted;
• the BCLIF flag is set, and
•
the MSSP module is reset to its IDLE state
(Figure 15-21).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 15-21:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable START
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
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FIGURE 15-22:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0 before SDA = 0,
Bus collision occurs, set BCLIF
SCL = 0 before BRG time-out,
Bus collision occurs, set BCLIF
BCLIF
Interrupt cleared
in software
S
’0’
’0’
’0’
’0’
SSPIF
FIGURE 15-23:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other Master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
BCLIF
’0’
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1
Set SSPIF
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reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
15.4.16.2 Bus Collision During a Repeated
START Condition
During a Repeated START condition, a bus collision
occurs if:
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ’1’ during the Repeated START condi-
tion (Figure 15-25).
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ’1’.
If, at the end of the BRG time-out both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to 0. The SCL pin is then de-asserted
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ’0’, see
Figure 15-24). If SDA is sampled high, the BRG is
FIGURE 15-24:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
'0'
S
'0'
SSPIF
FIGURE 15-25:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA.
BCLIF
RSEN
Set BCLIF, release SDA and SCL.
Interrupt cleared
in software
’0’
S
SSPIF
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The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ’0’ (Figure 15-26). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master attempt-
ing to drive a data ’0’ (Figure 15-27).
15.4.16.3 Bus Collision During a STOP
Condition
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
FIGURE 15-26:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
FIGURE 15-27:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
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The USART can be configured in the following modes:
16.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The SPEN (RCSTA register) and the TRISC<7> bits
have to be set, and the TRISC<6> bit must be
cleared, in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, serial EEPROMs, etc.
Register 16-1 shows the Transmit Status and Control
Register (TXSTA) and Register 16-2 shows the
Receive Status and Control Register (RCSTA).
REGISTER 16-1: TXSTA REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
R/W-0
BRGH
R-1
R/W-0
TX9D
—
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (Clock generated internally from BRG)
0= Slave mode (Clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
SREN/CREN overrides TXEN in SYNC mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data. Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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REGISTER 16-2: RCSTA REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave:
Unused in this mode
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enable interrupt and load of the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data. Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 178
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Example 16-1 shows the calculation of the baud rate
error for the following conditions:
16.1 USART Baud Rate Generator
(BRG)
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA register) also controls the
baud rate. In Synchronous mode, bit BRGH is ignored.
Table 16-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 16-1. From this, the error in
baud rate can be determined.
16.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 16-1:
CALCULATING BAUD RATE ERROR
Desired Baud Rate
Solving for X:
=
FOSC / (64 (X + 1))
X
X
X
=
=
=
( (FOSC / Desired Baud Rate) / 64 ) - 1
((16000000 / 9600) / 64) - 1
[25.042] = 25
Calculated Baud Rate
=
=
16000000 / (64 (25 + 1))
9615
Error
=
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
=
(9615 - 9600) / 9600
0.16%
TABLE 16-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate = FOSC/(16(X+1))
NA
Legend: X = value in SPBRG (0 to 255)
TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
0000 -010
0000 000x
0000 0000
0000 -010
0000 000x
0000 0000
TXSTA
RCSTA
CSRC
SPEN
TX9
RX9
TXEN SYNC
—
BRGH TRMT TX9D
SREN CREN ADDEN FERR OERR RX9D
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 179
PIC18C601/801
TABLE 16-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC =25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
value
SPBRG
value
(decimal)
%
%
KBAUD ERROR
KBAUD ERROR
(decimal)
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
-
-
2.4
NA
-
-
NA
-
-
9.6
NA
-
-
-
NA
-
-
19.2
76.8
96
NA
-
NA
-
-
77.16
96.15
297.62
480.77
6250
24.41
+0.47
+0.16
-0.79
-3.85
-
80
64
20
12
0
76.92
96.15
294.12
500
+0.16
64
51
16
9
+0.16
300
500
HIGH
LOW
-1.96
0
-
5000
19.53
0
-
255
-
255
FOSC = 16 MHz
SPBRG
10 MHz
%
7.15909 MHz
5.0688 MHz
%
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
%
%
value
KBAUD ERROR
KBAUD ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
-
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
+0.16
+0.16
-0.79
+2.56
0
-
NA
-
+0.16
-1.36
+0.16
+4.17
0
-
9.62
+0.23
+0.23
+1.32
-1.88
-0.57
-
185
92
22
18
5
9.60
19.20
74.54
97.48
NA
0
131
65
16
12
-
19.2
76.8
96
19.23
76.92
95.24
307.70
500
207
51
41
12
7
19.23
75.76
96.15
312.50
500
129
32
25
7
19.24
77.82
94.20
298.35
NA
0
-2.94
+1.54
300
500
HIGH
LOW
-
-
-
-
4
-
NA
-
4000
15.63
-
0
2500
9.77
-
0
1789.80
6.99
-
0
1267.20
4.95
0
-
255
-
255
-
255
255
FOSC = 4 MHz
3.579545 MHz
%
1 MHz
32.768 kHz
%
BAUD
RATE
(Kbps)
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
NA
NA
-
NA
NA
-
NA
1.20
2.40
9.62
19.23
NA
-
0.30
1.17
NA
+1.14
-
-
-
-
-
-
+0.16
207
103
25
12
-
-2.48
6
2.4
NA
-
NA
-
+0.16
-
-
-
-
-
-
-
-
-
-
9.6
9.62
19.23
76.92
1000
NA
+0.16
103
51
12
9
9.62
+0.23
-0.83
-2.90
+3.57
-0.57
-
92
46
11
8
+0.16
NA
-
19.2
76.8
96
+0.16
19.04
74.57
99.43
298.30
NA
+0.16
NA
-
+0.16
-
-
-
-
-
-
NA
-
+4.17
NA
-
NA
-
300
500
HIGH
LOW
-
0
-
-
2
NA
-
NA
-
-
500
1
-
NA
-
NA
1000
3.91
0
894.89
3.50
-
0
250
0.98
0
8.20
0.03
0
-
255
-
255
255
255
DS39541A-page 180
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 16-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
SPBRG
value
(decimal)
%
%
value
KBAUD ERROR
KBAUD
ERROR
(decimal)
0.3
1.2
NA
NA
-
NA
NA
-
-
-
162
40
19
4
-
-
129
32
15
3
2.4
2.40
9.53
19.53
78.13
97.66
NA
-0.15
2.40
9.47
19.53
78.13
NA
+0.16
9.6
-0.76
-1.36
19.2
76.8
96
+1.73
+1.73
+1.73
+1.73
+1.73
3
-
-
300
500
HIGH
LOW
-
-
-
-
-
312.50
NA
+4.17
0
NA
-
-
-
-
-
390.63
1.53
0
312.50
1.22
0
255
255
FOSC = 16 MHz
SPBRG
10 MHz
7.15909 MHz
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
%
%
%
%
value
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
NA
1.20
2.40
9.62
19.23
NA
-
NA
1.20
2.40
9.77
19.53
78.13
NA
-
NA
1.20
2.38
9.32
18.64
NA
-
NA
1.20
2.40
9.90
19.80
79.20
NA
-
+0.16
207
103
25
12
-
+0.16
129
64
15
7
+0.23
92
46
11
5
0
65
32
7
2.4
+0.16
+0.16
-0.83
0
9.6
+0.16
+1.73
-2.90
+3.13
19.2
76.8
96
+0.16
+1.73
-2.90
+3.13
3
-
-
-
-
-
-
+1.73
1
-
-
-
-
-
-
-
+3.13
0
NA
-
-
-
-
-
-
-
NA
-
-
-
-
-
-
-
300
500
HIGH
LOW
NA
-
NA
-
NA
-
NA
-
NA
-
NA
-
NA
-
NA
-
250
0.98
0
156.25
0.61
0
111.86
0.44
0
79.20
0.31
0
255
255
255
255
FOSC = 4 MHz
3.579545 MHz
1 MHz
32.768 kHz
%
BAUD
RATE
(Kbps)
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
0.30
1.20
2.40
NA
-0.16
0.30
1.19
2.43
9.32
18.64
NA
+0.23
0.30
1.20
NA
+0.16
NA
NA
-
-
-
-
-
-
-
-
-
-
-
+1.67
51
-0.83
46
+0.16
12
-
2.4
+1.67
25
+1.32
22
-
-
-
-
-
-
-
-
-
-
NA
-
9.6
-
-
-
-
-
-
-
-
-
-2.90
5
NA
-
NA
-
19.2
76.8
96
NA
-
-2.90
2
NA
-
NA
-
NA
-
-
-
-
-
-
-
-
NA
-
NA
-
NA
-
NA
-
NA
-
NA
-
300
500
HIGH
LOW
NA
-
-
NA
-
-
NA
-
-
NA
-
-
NA
NA
NA
NA
62.50
0.24
0
55.93
0.22
0
15.63
0.06
0
0.51
0.002
0
255
255
255
255
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 181
PIC18C601/801
TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
SPBRG
value
(decimal)
%
%
value
KBAUD ERROR
KBAUD ERROR
(decimal)
0.3
NA
-
NA
-
1.2
2.4
NA
NA
-
-
-
NA
NA
-
-
-
-
-
9.6
9.59
-0.15
+0.47
+1.73
+1.73
+4.17
+4.17
-
162
80
19
15
4
9.62
+0.16
+0.16
+1.73
+0.16
+4.17
-
129
64
15
12
3
19.2
76.8
96
19.30
78.13
97.66
312.50
520.83
1562.50
6.10
19.23
78.13
96.15
312.50
NA
300
500
HIGH
LOW
2
-
0
1250
4.88
-
0
-
255
-
255
FOSC = 16 MHz
SPBRG
10 MHz
7.15909 MHz
%
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
SPBRG
value
%
%
%
value
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
NA
-
NA
NA
-
NA
NA
-
NA
NA
-
-
-
-
-
-
-
-
-
185
46
22
5
-
-
131
32
16
3
2.4
NA
-
NA
-
2.41
9.52
19.45
74.57
NA
+0.23
2.40
9.60
18.64
79.20
NA
0
9.6
9.62
19.23
76.92
100
+0.16
103
51
12
9
9.62
18.94
78.13
NA
+0.16
64
32
7
-0.83
0
19.2
76.8
96
+0.16
-1.36
+1.32
-2.94
+0.16
+1.73
-2.90
+3.13
+4.17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300
500
HIGH
LOW
NA
-
0
-
-
312.50
NA
+4.17
1
NA
-
NA
-
500
1
-
-
-
-
NA
-
NA
-
1000
3.91
0
625
0
447.44
1.75
0
316.80
1.24
0
-
255
2.44
255
255
255
FOSC = 4 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
NA
1.20
2.40
9.62
19.23
NA
-
-
207
103
25
12
-
NA
1.20
2.41
9.73
18.64
74.57
NA
-
-
185
92
22
11
2
0.30
1.20
2.40
NA
+0.16
207
0.29
NA
-2.48
6
+0.16
+0.23
+0.16
51
-
-
-
-
-
-
-
-
-
-
-
2.4
+0.16
+0.23
+0.16
25
NA
-
9.6
+0.16
+1.32
-
-
-
-
-
-
-
-
-
NA
-
19.2
76.8
96
+0.16
-2.90
NA
-
NA
-
-
-
-
-
-
-
-2.90
NA
-
NA
-
NA
-
-
-
-
-
-
-
NA
-
NA
-
-
300
500
HIGH
LOW
NA
-
NA
-
NA
-
-
NA
NA
-
NA
-
NA
NA
-
250
0.98
0
55.93
0.22
0
62.50
0.24
0
2.05
0.008
0
255
255
255
255
DS39541A-page 182
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit TXIF (PIR registers) is set. This inter-
rupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE registers). Flag bit TXIF will be
set, regardless of the state of enable bit TXIE and can-
not be cleared in software. It will reset only when new
data is loaded into the TXREG register. While flag bit
TXIF indicated the status of the TXREG register,
another bit TRMT (TXSTA register) shows the status of
the TSR register. Status bit TRMT is a read only bit,
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
16.2 USART Asynchronous Mode
In this mode, data is transmitted in non-return-to-zero
(NRZ) format. Data consists of one START bit, eight or
nine data bits and one STOP bit. Data is transmitted in
serial fashion with LSb first. An on-chip 8-bit baud rate
generator can be programmed to generate the desired
baud rate. The baud rate generator produces a clock,
either x16 or x64 of the bit shift rate, depending on the
BRGH bit (TXSTA register). USART does not automat-
ically calculate the parity bit for the given data byte. If
parity is to be transmitted, USART must be pro-
grammed to transmit nine bits and software must set/
clear ninth data bit as parity bit. Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
Asynchronous mode is selected by clearing the SYNC
bit (TXSTA register).
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
The USART Asynchronous module consists of the fol-
lowing important elements:
is set.
Steps to follow when setting up an Asynchronous
Transmission:
• Baud Rate Generator
• Sampling Circuit
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
• Asynchronous Transmitter
• Asynchronous Receiver
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
16.2.1
USART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit TXIE.
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The TSR register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the STOP
bit has been transmitted from the previous load. As
soon as the STOP bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 16-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
8
TXIE
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
Note: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 183
PIC18C601/801
FIGURE 16-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
STOP Bit
TXIF bit
(Transmit Buffer
Register Empty Flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Register Empty Flag)
FIGURE 16-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
START Bit
Word 2
Bit 0
Bit 1
Bit 7/8
Bit 0
STOP Bit
Word 1
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
0000 000x 0000 000u
-000 0000 -000 0000
-000 0000 -000 0000
-000 0000 -000 0000
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
PIR1
PIE1
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
TXIF SSPIF CCP1IF TMR2IF TMR1IF
TXIE SSPIE CCP1IE TMR2IE TMR1IE
TXIP SSPIP CCP1IP TMR2IP TMR1IP
IPR1
—
RCSTA
SPEN
SREN CREN
—
FERR OERR
RX9D
TXREG USART Transmit Register
TXSTA CSRC TX9 TXEN SYNC ADDEN BRGH TRMT
TX9D
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
DS39541A-page 184
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
16.2.2
USART ASYNCHRONOUS
RECEIVER
16.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 16-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter, operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC. This mode would typi-
cally be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enable:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
Steps to follow when setting up an Asynchronous
Reception:
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. The RCIF bit will be set when reception is com-
plete. The interrupt will be acknowledged if the
RCIE and GIE bits are set.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
9. Read RCREG to determine if the device is being
addressed.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
FIGURE 16-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
or
÷ 16
RSR Register
LSb
MSb
0
Baud Rate Generator
1
7
STOP (8)
START
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
Note: I/O pins have diode protection to VDD and VSS.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 185
PIC18C601/801
FIGURE 16-5:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 16-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
0000 000x
0000 000u
-000 0000
-000 0000
-000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
PIR1
PIE1
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CREN
SSPIF CCP1IF TMR2IF TMR1IF -000 0000
SSPIE CCP1IE TMR2IE TMR1IE -000 0000
SSPIP CCP1IP TMR2IP TMR1IP -000 0000
IPR1
—
RCSTA
SPEN
—
FERR
OERR
RX9D
0000 -00x
0000 0000
0000 0010
0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9
TXEN
SYNC ADDEN BRGH
TRMT
TX9D
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
DS39541A-page 186
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2001 Microchip Technology Inc.
PIC18C601/801
bit TXIF (PIR registers) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE registers). Flag bit TXIF will be set, regardless of
the state of enable bit TXIE, and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA register) shows the status of the TSR register.
TRMT is a read only bit, which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty. The TSR is not mapped in data memory,
so it is not available to the user.
16.3 USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA register).
In addition, enable bit SPEN (RCSTA register) is set, in
order to configure the RC6/TX/CK and RC7/RX/DT I/O
pins to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA register).
Steps to follow when setting up a Synchronous Master
Transmission:
16.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
1. Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG is empty and interrupt
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
POR,
Value on all
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
—
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PIE1
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TMR2IF TMR1IF -000 0000 -000 0000
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IP TMR2IP TMR1IP -000 0000 -000 0000
IPR1
—
TXIP
RCSTA
SPEN
CREN
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
0000 0000 0000 0000
TXREG USART Transmit Register
TXSTA CSRC TX9
TXEN
SYNC ADDEN
BRGH
TRMT
TX9D
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 187
PIC18C601/801
FIGURE 16-6:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 0
Bit 1
Bit 2
Bit 7
Bit 0
Bit 1
Word 2
Bit 7
RC7/RX/DT
pin
Word 1
RC6/TX/CK
pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
’1’
’1’
TXEN bit
Note: Sync Master mode; SPBRG = ’0’; continuous transmission of two 8-bit words.
FIGURE 16-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit2
bit1
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS39541A-page 188
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2001 Microchip Technology Inc.
PIC18C601/801
3. Ensure bits CREN and SREN are clear.
16.3.2
USART SYNCHRONOUS MASTER
RECEPTION
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register), or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
When setting up a Synchronous Master reception, fol-
low these steps:
9. Read the 8-bit received data by reading the
RCREG register.
1. Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
10. If any error occurred, clear the error by clearing
bit CREN.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
POR,
BOR
Value on all
other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
—
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
-000 0000
-000 0000
-000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
PIR1
PIE1
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
CCP1IF TMR2IF TMR1IF -000 0000
CCP1IE TMR2IE TMR1IE -000 0000
CCP1IP TMR2IP TMR1IP -000 0000
IPR1
—
TXIP
RCSTA
SPEN
CREN
FERR
OERR
RX9D
0000 -00x
0000 0000
0000 0010
0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9
TXEN
SYNC
ADDEN
BRGH
TRMT
TX9D
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
FIGURE 16-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 189
PIC18C601/801
16.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
16.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master
mode, in that the shift clock is supplied externally at the
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA register).
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a "don’t care" in Slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector.
16.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
When setting up a Synchronous Slave Reception,
follow these steps:
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will be set.
5. Flag bit RCIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from SLEEP. If the global interrupt is enabled,
the program will branch to the interrupt vector.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
When setting up a Synchronous Slave Transmission,
follow these steps:
7. Read the 8-bit received data by reading the
RCREG register.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit CSRC.
8. If any error occurred, clear the error by clearing
bit CREN.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
POR,
Value on all
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CREN
SSPIF
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
—
—
PIE1
SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
SSPIP CCP1IP TMR2IP TMR1IP -000 0000 -000 0000
IPR1
—
RCSTA
TXREG
TXSTA
SPBRG
SPEN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
0000 0000 0000 0000
USART Transmit Register
CSRC TX9
TXEN
SYNC ADDEN
BRGH
TRMT
TX9D
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
DS39541A-page 190
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 16-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
POR,
BOR
Value on all
other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
—
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PIE1
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CREN
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IP TMR2IP TMR1IP -000 0000 -000 0000
IPR1
—
RCSTA
SPEN
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
0000 0000 0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9
TXEN
SYNC
ADDEN
BRGH
TRMT
TX9D
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 191
PIC18C601/801
NOTES:
DS39541A-page 192
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
The A/D module has five registers:
17.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
The analog-to-digital (A/D) converter module has 8
inputs for the PIC18C601 devices and 12 for the
PIC18C801 devices. This module has the ADCON0,
ADCON1, and ADCON2 registers.
The A/D allows conversion of an analog input signal
to a corresponding 10-bit digital number.
The ADCON0 register, shown in Register 17-1, controls
the operation of the A/D module. The ADCON1 register,
shown in Register 17-2, configures the functions of the
port pins. The ADCON2, shown in Register 16-3, config-
ures the A/D clock source and justification.
REGISTER 17-1: ADCON0 REGISTER
U-0
U-0
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
—
—
GO/DONE ADON
bit 7
bit 0
bit 7-6
bit 5-2
Unimplemented: Read as '0'
CHS3:CHS0: Analog Channel Select bits
0000= channel 00, (AN0)
0001= channel 01, (AN1)
0010= channel 02, (AN2)
0011= channel 03, (AN3)
0100= channel 04, (AN4)
0101= channel 05, (AN5)
0110= channel 06, (AN6)
0111= channel 07, (AN7)
1000= channel 08, (AN8)(1)
1001= channel 09, (AN9)(1)
1010= channel 10, (AN10)(1)
1011= channel 11, (AN11)(1)
1100= Reserved
1101= Reserved
1110= Reserved
1111= Reserved
These channels are not available on the PIC18C601 devices.
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress. Setting this bit starts an A/D conversion cycle. This bit is
automatically cleared by hardware when the A/D conversion is complete.
0= A/D conversion not in progress
bit 1
bit 0
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 193
PIC18C601/801
REGISTER 17-2: ADCON1 REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-6
bit 5-4
Unimplemented: Read as '0'
VCFG1:VCFG0: Voltage Reference Configuration bits
A/D VREF+
A/D VREF-
00
01
10
11
AVDD
AVSS
External VREF+
AVDD
AVSS
External VREF-
External VREF-
External VREF+
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits
AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Shaded cells = Additional A/D channels available on PIC18C801 devices.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 194
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2001 Microchip Technology Inc.
PIC18C601/801
REGISTER 17-3: ADCON2 REGISTER
R/W-0
ADFM
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
ADCS0
bit 0
—
—
—
—
ADCS2
ADCS1
bit 7
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6-3
bit 2-0
Unimplemented: Read as '0'
ADCS2:ADCS0: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC (clock derived from an internal RC oscillator = 1 MHz max)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC (clock derived from an internal RC oscillator = 1 MHz max)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
The analog reference voltage is software selectable to
either the device’s positive and negative supply
voltage (VDD and VSS), or the voltage level on the
RA3/AN3/VREF+ pin and RA2/AN2/VREF-.
Each port pin associated with the A/D converter can
be configured as an analog input (RA3 can also be a
voltage reference), or as a digital I/O.
The ADRESH and ADRESL registers contain the
result of the A/D conversion. When the A/D conver-
sion is complete, the result is loaded into the
ADRESH/ADRESL registers, the GO/DONE bit
(ADCON0 register) is cleared, and A/D interrupt flag
bit ADIF is set. The block diagram of the A/D module
is shown in Figure 17-1.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 195
PIC18C601/801
FIGURE 17-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
0111
0110
0101
0100
0011
0010
0001
0000
RF2/AN7
RF1/AN6
RF0/AN5
RA5/AN4
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
VIN
RA0/AN0
(Input voltage)
1011
1010
(1)
RH7/AN11
A/D
Converter
(1)
RH6/AN10
1001
1000
(1)
RH5/AN9
AVDD
(1)
RH4/AN8
VREF+
(Reference
Voltage)
VCFG0
VREF-
(Reference
Voltage)
AVSS
VCFG1
Note 1: These channels are not available on the PIC18C601 devices.
DS39541A-page 196
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/ADRESL
registers will contain unknown data after a Power-on
Reset.
2. Configure A/D interrupt (if desired):
•
•
•
Clear ADIF bit
Set ADIE bit
Set GIE bit
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 17.1.
After this acquisition time has elapsed, the A/D conver-
sion can be started. The following steps should be fol-
lowed to do an A/D conversion:
3. Wait the required acquisition time.
4. Start conversion:
•
Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
•
•
Polling for the GO/DONE bit to be cleared,
OR
Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
1. Configure the A/D module:
•
Configure analog pins, voltage reference
and digital I/O (ADCON1)
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
•
•
•
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON2)
Turn on A/D module (ADCON0)
FIGURE 17-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6 V
ANx
SS
RIC ≤ 1 k
RSS
Rs
CPIN
VAIN
I leakage
± 500 nA
CHOLD = 120 pF
VT = 0.6 V
5 pF
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
SS
= interconnect resistance
= sampling switch
2V
CHOLD
RSS
= sample/hold capacitance (from DAC)
= sampling switch resistance
5
6
7
8 9 10 11
Sampling Switch ( kΩ )
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 197
PIC18C601/801
To calculate the minimum acquisition time,
Equation 17-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
17.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 17-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
Example 17-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
=
=
≤
=
=
=
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
EQUATION 17-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 17-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS))
-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
)
EXAMPLE 17-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ
TC
=
=
2 µs + TC + [(Temp - 25°C)(0.05 µs/°C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 µs (-7.6241)
9.61 µs
TACQ
=
2 µs + 9.61 µs + [(50°C - 25°C)(0.05 µs/°C)]
11.61 µs + 1.25 µs
12.86 µs
DS39541A-page 198
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
17.2 Selecting the A/D Conversion
Clock
17.3 Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
• 2TOSC
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
• 4TOSC
• 8TOSC
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
• 16TOSC
• 32TOSC
• 64TOSC
• Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume current out of the device’s spec-
ification limits.
Table 17-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS2:ADCS0
PIC18C601/801
PIC18LC601/801(5)
2TOSC
4TOSC
8TOSC
16TOSC
32TOSC
64TOSC
RC
000
100
001
101
010
110
x11
1.25 MHz
2.50 MHz
5.00 MHz
10.0 MHz
20.0 MHz
—
666 kHz
1.33 MHz
2.67 MHz
5.33 MHz
10.67 MHz
—
—
—
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D
accuracy may be out of specification.
5: This column is for the LC devices only.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 199
PIC18C601/801
17.4 A/D Conversions
17.5 Use of the CCP2 Trigger
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011, and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/DONE
bit will be set, starting the A/D conversion and the Timer1
(or Timer3) counter will be reset to zero. Timer1 (or
Timer3) is reset to automatically repeat the A/D acquisi-
tion period with minimal software overhead (moving
ADRESH/ADRESL to the desired location). The appropri-
ate analog input channel must be selected and the mini-
mum acquisition done before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
Note: The GO/DONE bit should NOT be set in
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D mod-
ule, but will still reset the Timer1 (or Timer3) counter.
the same instruction that turns on the A/D.
FIGURE 17-3:
A/D CONVERSION TAD CYCLES
TCY - TAD
TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6
b9
b9
b4
b2
b0
b6
b5
b3
b1
b8
b7
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS39541A-page 200
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 17-2: SUMMARY OF A/D REGISTERS
Value on all
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
POR, BOR
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
-000 0000
-000 0000
-000 0000
-0-- 0000
---- 0000
---- 0000
uuuu uuuu
uuuu uuuu
0000 00-0
---- -000
0--- -000
--0u 0000
--11 1111
u000 0000
uuuu uuuu
1111 1111
0000 xxxx
uuuu uuuu
1111 1111
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
—
—
—
—
—
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSPIF CCP1IF
TMR2IF
TMR1IF -000 0000
SSPIE CCP1IE TMR2IE TMR1IE -000 0000
SSPIP CCP1IP TMR2IP TMR1IP -000 0000
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
TMR3IE
TMR3IP
CCP2IF -0-- 0000
CCP2IE ---- 0000
CCP2IP ---- 0000
xxxx xxxx
—
—
—
—
—
—
ADRESH A/D Result Register
ADRESL A/D Result Register
xxxx xxxx
ADCON0
ADCON1
ADCON2
PORTA
TRISA
—
—
—
—
—
—
CHS3
CHS3
CHS1
CHS0 GO/DONE ADON
0000 00-0
PCFG0 ---- -000
ADCS0 0--- -000
VCFG1 VCFG0 PCFG3 PCFG2
PCFG1
ADCS1
RA1
ADFM
—
—
—
—
ADCS2
RA2
RA5
RA4
RA3
RA0
--0x 0000
--11 1111
x000 0000
xxxx xxxx
1111 1111
0000 xxxx
xxxx xxxx
1111 1111
—
PORTA Data Direction Register
PORTF
LATF
RF7
LATF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
LATF6
LATF5
LATF4 LATF3
LATF2
LATF1
LATF0
TRISF
PORTF Data Direction Control Register
(1)
PORTH
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
(1)
LATH
LATH7
LATH6
LATH5 LATH4 LATH3 LATH2
LATH1
LATH0
(1)
TRISH
PORTH Data Direction Control Register
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Only available on PIC18C801 devices.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 201
PIC18C601/801
NOTES:
DS39541A-page 202
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Figure 18-2 shows the block diagram for the LVD mod-
ule. A comparator uses an internally generated refer-
ence voltage as the set point. When the selected tap
output of the device voltage crosses the set point (is
lower than), the LVDIF bit (PIR registers) is set.
18.0 LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do "housekeeping tasks", before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
Each node in the resister divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate,
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array (or external LVDIN input
pin) is equal to the voltage generated by the internal
voltage reference module. The comparator then gener-
ates an interrupt signal setting the LVDIF bit. This volt-
age is software programmable to any one of 16 values
(see Figure 18-2). The trip point is selected by
programming the LVDL3:LVDL0 bits (LVDCON<3:0>).
This module is software programmable circuitry, where
a device voltage trip point can be specified (internal ref-
erence voltage or external voltage input). When the
voltage of the device becomes lower than the specified
point, an interrupt flag is set. If the interrupt is enabled,
the program execution will branch to the interrupt vec-
tor address and the software can then respond to that
interrupt source.
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be "turned
off" by the software, which minimizes the current con-
sumption for the device.
FIGURE 18-2:
LOW VOLTAGE DETECT
(LVD) BLOCK DIAGRAM
VDD
Figure 18-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at time
TA. The application software then has the time, until the
device voltage is no longer in valid operating range, to
shut-down the system. Voltage point VB is the minimum
valid operating voltage specification. This occurs at time
TB. TB - TA is the total time for shut-down.
LVD Control
Register
FIGURE 18-1:
TYPICAL LOW VOLTAGE
DETECT APPLICATION
LVDIF
VA
VB
LVDIN
LVDEN
Internally Generated
Reference Voltage
TB
TA
Time
Legend:
VA = LVD trip point
VB = Minimum valid device operating range
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 203
PIC18C601/801
18.1 Control Register
The Low Voltage Detect Control register (Register 18-1)
controls the operation of the Low Voltage Detect
circuitry.
REGISTER 18-1: LVDCON REGISTER
U-0
U-0
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
—
—
IRVST
LVDEN
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as '0'
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0= Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.5V
1101= 4.2V
1100= 4.0V - Reserved on PIC18C601/801
1011= 3.8V - Reserved on PIC18C601/801
1010= 3.6V - Reserved on PIC18C601/801
1001= 3.5V - Reserved on PIC18C601/801
1000= 3.3V - Reserved on PIC18C601/801
0111= 3.0V - Reserved on PIC18C601/801
0110= 2.8V - Reserved on PIC18C601/801
0101= 2.7V - Reserved on PIC18C601/801
0100= 2.5V - Reserved on PIC18C601/801
0011= 2.4V - Reserved on PIC18C601/801
0010= 2.2V - Reserved on PIC18C601/801
0001= 2.0V - Reserved on PIC18C601/801
0000= Reserved on PIC18C601/801 and PIC18LC801/601
LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device
are not tested.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS39541A-page 204
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
The following steps are needed to setup the LVD
module:
18.2 Operation
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be con-
stantly operating. To decrease current consumption,
the LVD circuitry only needs to be enabled for short
periods, where the voltage is checked. After doing the
check, the LVD module may be disabled.
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register), which selects the desired
LVD trip point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 18-3 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 18-3:
LOW VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
50 ms
Internally Generated
Reference Stable
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
50 ms
Internally Generated
Reference Stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 205
PIC18C601/801
18.2.1
REFERENCE VOLTAGE SET POINT
18.3 External Analog Voltage Input
The Internal Reference Voltage of the LVD module may
be used by other internal circuitry (the programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires time to become stable before a low voltage con-
dition can be reliably detected. This time is invariant of
system clock speed. This start-up time is specified in
electrical specification parameter #36. The low voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 18-3.
The LVD module has an additional feature that allows
the user to supply the trip point voltage to the module
from an external source (the LVDIN pin). The LVDIN pin
is used as the trip point when the LVDL3:LVDL0 bits
equal ’1111’. This state connects the LVDIN pin volt-
age to the comparator. The other comparator input is
connected to an internal reference voltage source.
18.4 Operation During SLEEP
When enabled, the LVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from SLEEP. Device execution will continue from
the interrupt vector address, if interrupts have been
globally enabled.
18.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
18.5 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the LVD module to be turned off.
DS39541A-page 206
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
19.0 SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize
system reliability, minimize cost through elimination of
external components and provide power saving
operating modes:
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also available to allow the part to fit the
application. The RC oscillator option saves system
cost, while the LP crystal option saves power. By
default, HS oscillator mode is selected. There are two
main modes of operations for external memory inter-
face: 8-bit and 16-bit (default). A set of configuration
bits are used to select various options.
• OSC Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
19.1 Configuration Bits
• ID Locations
The configuration bits can be programmed (read as ’0’),
or left unprogrammed (read as ’1’), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
PIC18C601/801 devices have a Watchdog Timer,
which can be permanently enabled/disabled via the
configuration bits, or it can be software controlled. By
default, the Watchdog Timer is disabled to allow soft-
ware control. It runs off its own RC oscillator for cost
reduction. There are two timers that offer necessary
delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
TABLE 19-1: CONFIGURATION BITS AND DEVICE IDs
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300006h CONFIG4L
—
—
—
BW
—
—
—
—
—
—
—
—
—
FOSC1
FOSC0
---- --11
-1-- ---1
---- 1110
1--- ---1
0000 0000
0000 0000
—
PWRTEN
—
—
—
WDTPS2 WDTPS1 WDTPS0 WDTEN
r
—
—
—
—
—
—
STVREN
REV0
3FFFFEh
3FFFFFh
DEVID1
DEVID2
DEV2
DEV1
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
DEV10 DEV9
DEV3
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition, r = reserved, maintain ‘1’.
Shaded cells are unimplemented, read as ’0’.
2001 Microchip Technology Inc.
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PIC18C601/801
REGISTER 19-1: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 0300001h)
U-0
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
—
—
—
—
—
—
FOSC1
FOSC0
bit 7
bit 0
bit 7-2
bit 2-0
Unimplemented: Read as ’0’
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= EC oscillator
00= LP oscillator
Legend:
r = Reserved
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 19-2: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h)
U-0
R/P-1
BW
U-0
U-0
U-0
U-0
U-0
R/P-1
—
—
—
—
—
—
PWRTEN
bit 0
bit 7
bit 7
bit 6
Unimplemented: Read as ’0’
BW: External Bus Data Width bit
1= 16-bit external bus mode
0= 8-bit external bus mode
bit 5-1
bit 0
Unimplemented: Read as ’0’
PWRTEN: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
Legend:
r = Reserved
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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PIC18C601/801
REGISTER 19-3: CONFIGURATIONREGISTER2HIGH(CONFIG2H:BYTEADDRESS300003H)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 0
bit 7
Unimplemented: Read as ’0’
bit 7-4
bit 3-1
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
000=1:128
001=1:64
010=1:32
011=1:16
100=1:8
101=1:4
110=1:2
111=1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
r = Reserved
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 19-4: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006H)
R/P-1
r
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
STVREN
bit 0
—
—
—
—
—
—
bit 7
bit 7
Reserved: Maintain as ‘1’
Unimplemented: Read as ’0’
bit 6-1
bit 0
STVREN: Stack Full/Underflow RESET Enable bit
1= Stack Full/Underflow will cause RESET
0= Stack Full/Underflow will not cause RESET
Legend:
r = Reserved
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
2001 Microchip Technology Inc.
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PIC18C601/801
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned by
using configuration bits WDPS<3:1> in CONFIG2H
register. If the Watchdog Timer is disabled by configu-
ration, values for the WDT postscaler may be assigned
using the SWDPS bits in the WDTCON register.
19.2 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO
pins of the device has been stopped; for example, by
execution of a SLEEPinstruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
timing out and generating
RESET condition.
a device
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
By default, the Watchdog Timer is disabled by configu-
ration to allow software control over Watchdog Timer
operation. If the WDT is enabled by configuration, soft-
ware execution may not disable this function. When the
Watchdog Timer is disabled by configuration, the
SWDTEN bit in the WDTCON register enables/
disables the operation of the WDT.
19.2.1
CONTROL REGISTER
Register 19-5 shows the WDTCON register. This is a
readable and writable register. It contains control bits to
control the Watchdog Timer from user software. If the
Watchdog Timer is enabled by configuration, this regis-
ter setting is ignored.
REGISTER 19-5: WDTCON REGISTER
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
SWDPS2 SWDPS1 SWDPS0 SWDTEN
bit 0
bit 7
bit 7-4
bit 3-1
Unimplemented: Read as ’0’
SWDPS2:SWDPS0: Software Watchdog Timer Postscale Select bits
111= 1:128
110= 1:64
101= 1:32
100= 1:16
011= 1:8
010= 1:4
001= 1:2
000= 1:1
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is turned off if it is not disabled
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
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PIC18C601/801
the device will use predefined set postscaler value. If
the device has the Watchdog Timer disabled by config-
uration bits, user software can set desired postscaler
value. When the device has the Watchdog Timer
enabled by configuration bits, by default, Watchdog
postscaler of 1:128 is selected.
19.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler may be programmed by
the user software or is selected by configuration bits
WDTPS<2:0> in the CONFIG2H register. If the device
has the Watchdog Timer enabled by configuration bits,
FIGURE 19-1:
Watchdog Timer Block Diagram
WDT Timer
Postscaler
8
SWDTEN bit
8 - to - 1 MUX
WDTPS2:WDTPS0
WDT
Time-out
Note: WDPS2:WDPS0 are bits in a configuration register.
TABLE 19-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WDTPS2
TO
Bit 2
WDTPS1
PD
Bit 1
Bit 0
CONFIG2H
RCON
—
IPEN
—
—
r
—
—
—
—
RI
—
WDTPS0
POR
WDTEN
r
WDTCON
—
SWDPS2 SWDPS1 SWDPS0 SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
2001 Microchip Technology Inc.
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PIC18C601/801
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
19.3 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
Upon entering into Power-down mode, the following
actions are performed:
1. Watchdog Timer is cleared and kept running.
2. PD bit in RCON register is cleared.
3. TO bit in RCON register is set.
When the SLEEPinstruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
4. Oscillator driver is turned off.
5. I/O ports maintain the status they had before the
SLEEPinstruction was executed.
To achieve lowest current consumption, follow these
steps before switching to Power-down mode:
1. Place all I/O pins at either VDD or VSS and
ensure no external circuitry is drawing current
from I/O pin.
2. Power-down A/D and external clocks.
3. Pull all hi-impedance inputs to high or low,
externally.
19.3.2
WAKE-UP USING INTERRUPTS
4. Place T0CKI at VSS or VDD.
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
5. Current consumption by PORTB on-chip pull-
ups should be taken into account and disabled,
if necessary.
• If an interrupt condition (interrupt flag bit and inter-
rupt enable bits are set) occurs before the execu-
tion of a SLEEPinstruction, the SLEEPinstruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
The MCLR pin must be at a logic high level (VIHMC).
19.3.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
• If the interrupt condition occurs during or after
the execution of a SLEEPinstruction, the device
will immediately wake-up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or a
peripheral interrupt.
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
The following peripheral interrupts can wake the device
from SLEEP:
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
4. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
5. TMR3 interrupt. Timer3 must be operating as
an asynchronous counter.
6. CCP Capture mode interrupt.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
7. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
8. MSSP (START/STOP) bit detect interrupt.
9. MSSP transmit or receive in Slave mode
(SPI/I2C).
10. USART RX or TX (Synchronous Slave mode).
11. A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
DS39541A-page 212
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PIC18C601/801
FIGURE 19-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
CLKOUT(4)
INT pin
INTIF bit
GIEH bit
Interrupt Latency(3)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+2
PC+4
PC+4
PC + 4
0008h
000Ah
Instruction
Fetched
Inst(0008h)
Inst(PC + 2)
Inst(PC + 4)
Inst(000Ah)
Inst(PC) = SLEEP
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 2)
Inst(PC - 1)
Inst(0008h)
Note 1: HS or LP oscillator mode assumed.
2: GIE set is assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE is cleared, execution will continue in-line.
3: TOST = 1024TOSC (drawing not to scale). This delay will not occur for RC and EC osc modes.
4: CLKOUT is not available in these oscillator modes, but shown here for timing reference.
2001 Microchip Technology Inc.
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PIC18C601/801
NOTES:
DS39541A-page 214
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2001 Microchip Technology Inc.
PIC18C601/801
The literal instructions may use some of the following
operands:
20.0 INSTRUCTION SET SUMMARY
The PIC18C601/801 instruction set adds many
enhancements to the previous PICmicro® instruction
sets, while maintaining an easy migration path from
them.
• A literal value to be loaded into a file register
(represented by ’k’)
• The desired FSR register to load the literal value
into (represented by ’f’)
With few exceptions, instructions are a single program
memory word (16-bits). Each single word instruction is
divided into an OPCODE, which specifies the instruc-
tion type, and one or more operands which further
specify the operation of the instruction.
• No operand required
(specified by ’—’)
The control instructions may use some of the following
operands:
• A program memory address (represented by ’n’)
The instruction set is highly orthogonal and is grouped
into four basic categories:
• The mode of the Call or Return instructions
(represented by ’s’)
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• The mode of the Table Read and Table Write
instructions (represented by ’m’)
• No operand required
(specified by ’—’)
• Control operations
The PIC18C601/801 instruction set summary in
Table 20-2 lists byte-oriented, bit-oriented, literal
and control operations. Table 20-1 shows the opcode
field descriptions.
All instructions are a single word, except for four double
word instructions. These four instructions were made
double word instructions so that all the required infor-
mation is available in these 32 bits. In the second word,
the 4 MSbs are 1’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
Most byte-oriented instructions have three operands:
1. The file register (represented by ’f’)
2. The destination of the result
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.The double word instructions execute in two
instruction cycles.
(represented by ’d’)
3. The accessed memory
(represented by ’a’)
The file register designator ‘f’ specifies which file regis-
ter is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
Two word branch instructions (if true) would take 3 µs.
All bit-oriented instructions have three operands:
1. The file register (represented by ’f’)
Figure 20-1 shows the general formats that the instruc-
tions can have. All examples use the format ‘nnh’ to
represent a hexadecimal number, where ‘h’signifies
a hexadecimal digit.
2. The bit in the file register
(represented by ’b’)
3. The accessed memory
(represented by ’a’)
The Instruction Set Summary, shown in Table 20-2,
lists the instructions recognized by the Microchip
assembler (MPASMTM).
The bit field designator 'b' selects the number of the bit
affected by the operation, while the file register desig-
nator 'f' represents the number of the file in which the
bit is located.
Section 20.1 provides a description of each instruction.
2001 Microchip Technology Inc.
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DS39541A-page 215
PIC18C601/801
TABLE 20-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
ACCESS
BANKED
bbb
ACCESS = 0: RAM access bit symbol
BANKED = 1: RAM access bit symbol
Bit address within an 8-bit file register (0 to 7)
Bank Select Register. Used to select the current RAM bank.
BSR
d
Destination select bit;
d = 0: store result in WREG,
d = 1: store result in file register f.
dest
f
Destination either the WREG register or the specified register file location
8-bit Register file address (00h to FFh)
f
12-bit Register file address (000h to FFFh). This is the source address.
12-bit Register file address (000h to FFFh). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
Label name
The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
s
f
d
k
label
mm
*
No change to register (such as TBLPTR with Table reads and writes)
Post-Increment register (such as TBLPTR with Table reads and writes)
Post-Decrement register (such as TBLPTR with Table reads and writes)
Pre-Increment register (such as TBLPTR with Table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct
address for Call/Branch and Return instructions
PRODH
PRODL
s
Product of Multiply high byte (Register at address FF4h)
Product of Multiply low byte (Register at address FF3h)
Fast Call / Return mode select bit.
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged (Register at address FE8h)
W = 0: Destination select bit symbol
W
WREG
x
Working register (accumulator) (Register at address FE8h)
Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility
with all Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a Program Memory location) (Register at address FF6h)
TABLAT
8-bit Table Latch (Register at address FF5h)
TOS
Top-of-Stack
PC
Program Counter
PCL
Program Counter Low Byte (Register at address FF9h)
PCH
Program Counter High Byte
PCLATH
Program Counter High Byte Latch (Register at address FFAh)
PCLATU
Program Counter Upper Byte Latch (Register at address FFBh)
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer
TO
Time-out bit
PD
Power-down bit
C, DC, Z, OV, N
ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
[
]
)
Optional
Contents
(
→
< >
∈
Assigned to
Register bit field
In the set of
italics
User defined term (font is courier)
DS39541A-page 216
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PIC18C601/801
FIGURE 20-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
Example Instruction
15
10
9
d
8
7
0
OPCODE
a
f (FILE #)
ADDWF MYREG, W
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select Bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11
OPCODE b (BIT #)
9
8
7
0
a
f (FILE #)
BSF MYREG, bit
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select Bank
f = 8-bit file register address
Literal operations
15
8
7
0
OPCODE
k (literal)
MOVLW 7Fh
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
8 7
15
15
0
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
1111
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
15
OPCODE
n<10:0> (literal)
8 7
n<7:0> (literal)
15
6
4
0
LFSR FSR0, 100h
OPCODE
f
k<11:8>(lit.)
0
15
11
7
1111
0000
k<7:0> (literal)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 217
PIC18C601/801
TABLE 20-2: PIC18C601/801 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Status
Affected
Description
Cycles
Notes
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f [,d [,a]] Add WREG and f
1
1
1
1
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2, 6
0010 01da ffff ffff C, DC, Z, OV, N 1, 2, 6
0001 01da ffff ffff Z, N
0110 101a ffff ffff
0001 11da ffff ffff Z, N
ADDWFC f [,d [,a]] Add WREG and Carry bit to f
ANDWF
CLRF
COMF
f [,d [,a]] AND WREG with f
f [,a] Clear f
f [,d [,a]] Complement f
1,2, 6
2, 6
1, 2, 6
4, 6
4, 6
1, 2, 6
Z
CPFSEQ f [,a]
CPFSGT f [,a]
CPFSLT f [,a]
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
DECF
f [,d [,a]] Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6
DECFSZ f [,d [,a]] Decrement f, Skip if 0
DCFSNZ f [,d [,a]] Decrement f, Skip if Not 0
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4, 6
1, 2, 6
INCF
f [,d [,a]] Increment f
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6
INCFSZ
INFSNZ
IORWF
MOVF
f [,d [,a]] Increment f, Skip if 0
f [,d [,a]] Increment f, Skip if Not 0
f [,d [,a]] Inclusive OR WREG with f
f [,d [,a]] Move f
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4, 6
1, 2, 6
1, 2, 6
1, 6
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
f , f
Move f (source) to 1st word
s
d
s
f (destination)2nd word
d
MOVWF f [,a]
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N 1, 2, 6
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
6
6
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
f [,a]
f [,a]
f [,d [,a]] Rotate Left f through Carry
f [,d [,a]] Rotate Left f (No Carry)
f [,d [,a]] Rotate Right f through Carry
f [,d [,a]] Rotate Right f (No Carry)
6
1, 2, 6
6
6
6
f [,a]
Set f
SUBFWB f [,d [,a]] Subtract f from WREG with
borrow
0101 01da ffff ffff C, DC, Z, OV, N 1, 2, 6
SUBWF
f [,d [,a]] Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N
0101 10da ffff ffff C, DC, Z, OV, N 1, 2, 6
6
SUBWFB f [,d [,a]] Subtract WREG from f with
borrow
SWAPF
TSTFSZ f [,a]
XORWF f [,d [,a]] Exclusive OR WREG with f
BIT-ORIENTED FILE REGISTER OPERATIONS
f [,d [,a]] Swap nibbles in f
1
0011 10da ffff ffff None
4, 6
1, 2, 6
6
Test f, skip if 0
1 (2 or 3) 0110 011a ffff ffff None
1
0001 10da ffff ffff Z, N
BCF
BSF
BTFSC
BTFSS
BTG
f, b [,a] Bit Clear f
f, b [,a] Bit Set f
f, b [,a] Bit Test f, Skip if Clear
f, b [,a] Bit Test f, Skip if Set
f [,d [,a]] Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2, 6
1, 2, 6
3, 4, 6
3, 4, 6
1, 2, 6
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip’s MPASMTM Assembler automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’,
according to address of register being used.
DS39541A-page 218
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 20-2: PIC18C601/801 INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word
2nd word
1 (2)
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
CALL
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to address1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111
C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
1
1
1
1
2
1
2
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable
s
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip’s MPASMTM Assembler automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’,
according to address of register being used.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 219
PIC18C601/801
TABLE 20-2: PIC18C601/801 INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
1
1
1
2
0000 1111 kkkk kkkk C, DC, Z, OV, N
0000 1011 kkkk kkkk Z, N
0000 1001 kkkk kkkk Z, N
1110 1110 00ff kkkk None
1111 0000 kkkk kkkk
AND literal with WREG
Inclusive OR literal with WREG
Load FSR (f) with a 12-bit
literal (k)
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
0000 0001 0000 kkkk None
0000 1110 kkkk kkkk None
0000 1101 kkkk kkkk None
0000 1100 kkkk kkkk None
0000 1000 kkkk kkkk C, DC, Z, OV, N
0000 1010 kkkk kkkk Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000 1000 None
0000 0000 0000 1001 None
0000 0000 0000 1010 None
0000 0000 0000 1011 None
0000 0000 0000 1100 None
0000 0000 0000 1101 None
0000 0000 0000 1110 None
0000 0000 0000 1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2 (5)
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
6: Microchip’s MPASMTM Assembler automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’,
according to address of register being used.
DS39541A-page 220
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
20.1 Instruction Set
ADDLW
ADD literal to WREG
ADDWF
ADD WREG to f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ADDWF f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(WREG) + k → WREG
N,OV, C, DC, Z
Operation:
(WREG) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
Thecontents ofWREG are addedto
the 8-bit literal ’k’ and the result is
placed in WREG.
0010
01da
ffff
ffff
Description:
Add WREG to register ’f’. If ’d’ is 0,
the result is stored in WREG. If ’d’ is
1, theresultisstoredbackinregister
'f' (default). If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
BankwillbeselectedaspertheBSR
value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Words:
Cycles:
1
1
ADDLW
15h
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WREG
N
OV
C
DC
Z
=
=
=
=
=
=
10h
?
?
?
?
Decode
Read
register ’f’
Process
Data
Write to
destination
ADDWF
REG, W
Example:
?
Before Instruction
After Instruction
WREG
REG
N
=
17h
0C2h
WREG
=
=
=
=
=
=
25h
0
0
0
0
=
=
=
=
=
=
N
?
?
?
?
?
OV
C
OV
C
DC
Z
DC
Z
0
After Instruction
WREG
REG
N
OV
C
=
=
=
=
=
=
=
0D9h
0C2h
1
0
0
0
0
DC
Z
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 221
PIC18C601/801
ADDWFC
ADD WREG and Carry bit to f
ANDLW
AND literal with WREG
Syntax:
[ label ] ADDWFC f [,d [,a]]
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(WREG) .AND. k → WREG
N,Z
Operation:
(WREG) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
The contents of WREG are AND’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
0010
00da
ffff
ffff
Description:
Add WREG, the Carry Flag and data
memory location ’f’. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in data memory
location 'f'. If ’a’is 0, the Access Bank
will be selected. If ’a’ is 1, the Bank
will be selected as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to
WREG
’k’
Words:
Cycles:
1
1
ANDLW
5Fh
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WREG
N
Z
=
=
=
0A3h
?
?
Decode
Read
register ’f’
Process
Data
Write to
destination
After Instruction
ADDWFC
REG, W
Example:
WREG
=
=
=
03h
0
0
N
Z
Before Instruction
C
=
1
REG
WREG
N
OV
DC
Z
=
=
=
=
=
=
02h
4Dh
?
?
?
?
After Instruction
C
=
=
=
=
=
=
=
0
REG
WREG
N
OV
DC
Z
02h
50h
0
0
0
0
DS39541A-page 222
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
ANDWF
AND WREG with f
BC
Branch if Carry
Syntax:
[ label ] ANDWF f [,d [,a]]
Syntax:
[ label ] BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if carry bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(WREG) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ’1’, then the pro-
Description:
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result
is storedback in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected. If ’a’ is 1, the bank will be
selected as per the BSR value.
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
’n’
ANDWF
REG,
W
No
operation
No
operation
No
operation
No
operation
Example:
Before Instruction
If No Jump:
Q1
WREG
REG
N
=
17h
0C2h
?
Q2
Q3
Q4
=
=
=
Decode
Read literal
Process
Data
No
operation
Z
?
’n’
After Instruction
WREG
REG
N
=
=
=
=
02h
0C2h
0
HERE
BC
5
Example:
Before Instruction
PC
=
address (HERE)
Z
0
After Instruction
If Carry
=
=
=
=
1;
PC
If Carry
PC
address (HERE+12)
0;
address (HERE+2)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 223
PIC18C601/801
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
[ label ] BCF f, b [,a]
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if negative bit is ’1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ’1’, then the pro-
Description:
Bit 'b' in register 'f' is cleared. If ’a’ is
0, the Access Bank will be selected,
overriding the BSR value. If ’a’ = 1,
the Bank will be selected as per the
BSR value.
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Q1
Q2
Q3
Q4
BCF
FLAG_REG,
7
Decode
Read literal
Process
Data
Write to PC
Example:
’n’
Before Instruction
No
operation
No
operation
No
operation
No
operation
FLAG_REG = 0C7h
After Instruction
If No Jump:
Q1
FLAG_REG = 47h
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
’n’
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
If Negative
PC
DS39541A-page 224
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 ≤ n ≤ 127
if carry bit is ’0’
n
Syntax:
[ label ] BNN
-128 ≤ n ≤ 127
n
Operands:
Operation:
Operands:
Operation:
if negative bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ’0’, then the
Description:
If the Negative bit is ’0’, then the
program will branch.
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
Decode
Read literal
Process
Data
Write to PC
’n’
’n’
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
Decode
Read literal
Process
Data
No
operation
’n’
’n’
HERE
BNC Jump
HERE
BNN Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Negative
PC
If Carry
=
=
=
=
0;
=
=
=
=
0;
PC
If Carry
PC
address (Jump)
1;
address (HERE+2)
address (Jump)
1;
address (HERE+2)
If Negative
PC
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 225
PIC18C601/801
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
-128 ≤ n ≤ 127
n
Syntax:
[ label ] BNZ
-128 ≤ n ≤ 127
if zero bit is ’0’
n
Operands:
Operation:
Operands:
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ’0’, then the
Description:
If theZerobitis’0’, then the program
program will branch.
will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
Decode
Read literal
Process
Data
Write to PC
’n’
’n’
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
Decode
Read literal
Process
Data
No
operation
’n’
’n’
HERE
BNOV Jump
HERE
BNZ Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
If Overflow
PC
After Instruction
=
=
=
=
0;
If Zero
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
PC
If Zero
PC
address (Jump)
1;
address (HERE+2)
If Overflow
PC
DS39541A-page 226
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
Operands:
[ label ] BSF f, b [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Addthe2’scomplementnumber’2n’
to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a two-
cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit 'b' in register 'f' is set. If ’a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
BankwillbeselectedaspertheBSR
value (default).
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
’n’
Decode
Read
register ’f’
Process
Data
Write
register ’f’
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG
=
=
0Ah
Before Instruction
After Instruction
FLAG_REG
PC
=
=
address (HERE)
address (Jump)
8Ah
After Instruction
PC
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 227
PIC18C601/801
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f, b [,a]
Syntax:
[ label ] BTFSS f, b [,a]
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
None
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit 'b' in register ’f' is 0, then the next
instruction is skipped.
Description:
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a two-
cycle instruction. If ’a’is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
If bit 'b' is 1, then the next instruction
fetched during the current instruction
execution, is discarded and a NOPis
executed instead, making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
No
operation
Decode
Read
Process
Data
No
operation
register ’f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1
Example:
Before Instruction
PC
=
address (HERE)
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
=
=
=
=
0;
After Instruction
If FLAG<1>
PC
address (TRUE)
1;
address (FALSE)
=
=
=
=
0;
If FLAG<1>
PC
address (FALSE)
1;
address (TRUE)
If FLAG<1>
PC
DS39541A-page 228
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
Operands:
[ label ] BTG f, b [,a]
Syntax:
[ label ] BOV
-128 ≤ n ≤ 127
n
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
if overflow bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ’1’, then the pro-
Description:
Bit ’b’ in data memory location ’f’ is
inverted. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Q1
Q2
Q3
Q4
BTG
PORTC,
4
Decode
Read literal
Process
Data
Write to PC
Example:
’n’
Before Instruction:
No
operation
No
operation
No
operation
No
operation
PORTC
=
0111 0101[75h]
After Instruction:
If No Jump:
Q1
PORTC
=
0110 0101[65h]
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
’n’
HERE
BOV Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
If Overflow
PC
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 229
PIC18C601/801
BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
Operands:
Operation:
n
Syntax:
Operands:
[ label ] CALL k [,s]
-128 ≤ n ≤ 127
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
(WREG) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
Description:
If the Zero bit is ’1’, then the program
will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2M byte
memoryrange. First,returnaddress
(PC+ 4) is pushed onto the return
stack. If ’s’ = 1, the WREG, STATUS
and BSR registers are also pushed
into their respective shadow regis-
ters, WS, STATUSS and BSRS.
If 's' = 0, no update occurs
(default). Then the 20-bit value ’k’ is
loaded into PC<20:1>. CALLis a
two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write to PC
’n’
No
operation
No
No
No
operation
operation
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
No
operation
Q Cycle Activity:
Q1
’n’
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
HERE
BZ Jump
Example:
’k’<7:0>,
stack
’k’<19:8>,
Write to PC
Before Instruction
No
operation
No
operation
No
operation
No
operation
PC
=
address (HERE)
After Instruction
If Zero
=
=
=
=
1;
HERE
CALL THERE, FAST
Example:
PC
If Zero
PC
address (Jump)
0;
address (HERE+2)
Before Instruction
PC
=
Address (HERE)
After Instruction
PC
TOS
WS
=
=
=
=
Address (THERE)
Address (HERE + 4)
WREGREG
BSRS
BSR
STATUSS = STATUS
DS39541A-page 230
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
CLRF
Clear f
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
Operands:
[label] CLRF f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Decode
No
operation
Process
Data
No
operation
CLRF
FLAG_REG
CLRWDT
Example:
Example:
Before Instruction
Before Instruction
FLAG_REG
Z
=
=
5Ah
?
WDT counter
WDT postscaler
TO
=
=
=
=
?
?
?
?
After Instruction
PD
FLAG_REG
Z
=
=
00h
0
After Instruction
WDT counter
WDT postscaler
TO
=
=
=
=
00h
0
1
PD
1
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 231
PIC18C601/801
Compare f with WREG,
skip if f = WREG
CPFSEQ
COMF
Complement f
Syntax:
Operands:
[ label ] COMF f [,d [,a]]
Syntax:
[ label ] CPFSEQ f [,a]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (WREG),
Operation:
skip if (f) = (WREG)
(unsigned comparison)
(f) → dest
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ’f’ are com-
plemented. If ’d’ is 0 the result is
stored in WREG. If ’d’ is 1 the result
is stored back in register ’f’
Description:
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
If 'f' = WREG, then the fetched
instruction is discarded and a NOP
is executed instead making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
BankwillbeselectedaspertheBSR
value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ’f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
COMF
REG
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ’f’
Process
Data
No
operation
REG
=
13h
?
?
N
Z
=
=
If skip:
Q1
Q2
Q3
Q4
After Instruction
No
operation
No
operation
No
operation
No
operation
REG
WREG
N
=
=
=
=
13h
0ECh
1
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Z
0
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
WREG
=
=
=
HERE
?
?
REG
After Instruction
If REG
PC
If REG
PC
=
WREG;
Address (EQUAL)
WREG;
=
≠
=
Address (NEQUAL)
DS39541A-page 232
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Compare f with WREG,
skip if f > WREG
Compare f with WREG,
skip if f < WREG
CPFSGT
CPFSLT
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (WREG),
Operation:
(f) – (WREG),
skip if (f) > (WREG)
(unsigned comparison)
skip if (f) < (WREG)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data
memorylocation’f’tothecontentsof
the WREG by performing an
unsigned subtraction.
Description:
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If the contents of ’f’ are greater than
the contents of , then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
BankwillbeselectedaspertheBSR
value.
If the contents of 'f' are less than the
contents of WREG, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ’a’ is 0, the
AccessBankwillbeselected. If’a’is
1, the Bank will be selected as per
the BSR value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
No
operation
Decode
Read
register ’f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Example:
Before Instruction
PC
WREG
=
=
Address (HERE)
?
Before Instruction
PC
WREG
=
=
Address (HERE)
?
After Instruction
After Instruction
If REG
PC
If REG
PC
If REG
PC
If REG
PC
<
=
≥
=
WREG;
Address (LESS)
WREG;
>
WREG;
Address (GREATER)
WREG;
=
≤
=
Address (NLESS)
Address (NGREATER)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 233
PIC18C601/801
DECF
Decrement f
DAW
Decimal Adjust WREG Register
Syntax:
Operands:
[ label ] DECF f [,d [,a]]
Syntax:
[label] DAW
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
None
If [WREG<3:0> >9] or [DC = 1] then
(WREG<3:0>) + 6 → W<3:0>;
else
Operation:
(f) – 1 → dest
Status Affected:
Encoding:
C,DC,N,OV,Z
(WREG<3:0>) → W<3:0>;
0000
01da
ffff
ffff
If [WREG<7:4> >9] or [C = 1] then
Description:
Decrement register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register 'f'
(default). If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
(WREG<7:4>) + 6 → WREG<7:4>;
else
(WREG<7:4>) → WREG<7:4>;
Status Affected:
Encoding:
C
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in
WREG resulting from the earlier
addition of two variables (each in
packedBCDformat)andproducesa
correct packed BCD result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
register ’f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
DECF
CNT
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
Process
Data
Write
WREG
CNT
Z
=
=
01h
0
register WREG
DAW
Example1:
After Instruction
Before Instruction
CNT
=
00h
1
WREG
=
=
=
0A5h
0
0
Z
=
C
DC
After Instruction
WREG
C
DC
=
=
=
05h
1
0
Example 2:
Before Instruction
WREG
C
DC
=
=
=
0CEh
0
0
After Instruction
WREG
C
DC
=
=
=
34h
1
0
DS39541A-page 234
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
DECFSZ
Syntax:
Decrement f, skip if 0
DCFSNZ
Syntax:
Decrement f, skip if not 0
[ label ] DECFSZ f [,d [,a]]
[label] DCFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
Thecontentsofregister'f'aredecre-
mented. If 'd' is 0, the result is
Description:
Thecontentsofregister'f'aredecre-
mented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result
is placed back in register 'f' (default).
placed in WREG. If 'd' is 1, the result
is placed back in register 'f' (default).
If the result is 0, the next instruction,
which is already fetched, is dis-
carded, and a NOPis executed
instead, making it a two-cycle
If the result is not 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOPis executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bankwillbeselected, overridingthe
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
instruction. If ’a’ is 0, the Access
Bankwillbeselected, overridingthe
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Decode
Read
register ’f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT
LOOP
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
Example:
Example:
CONTINUE
Before Instruction
Before Instruction
TEMP
PC
=
Address (HERE)
=
?
After Instruction
After Instruction
TEMP
CNT
=
=
=
≠
=
CNT - 1
0;
Address (CONTINUE)
0;
=
=
=
≠
=
TEMP - 1,
0;
Address (ZERO)
0;
If CNT
If TEMP
PC
If TEMP
PC
PC
If CNT
PC
Address (HERE+2)
Address (NZERO)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 235
PIC18C601/801
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 1048575
k → PC<20:1>
None
INCF
Increment f
Syntax:
Syntax:
Operands:
[ label ] INCF f [,d [,a]]
Operands:
Operation:
Status Affected:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C,DC,N,OV,Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional
Description:
The contents of register ’f’ are incre-
mented. If’d’is0, theresult isplaced
in WREG. If ’d’ is 1, the result is
placedback inregister’f’(default). If
’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
branch anywhere within entire 2M
byte memory range. The 20-bit
value ’k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Words:
Cycles:
2
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
’k’<7:0>,
No
operation
Read literal
’k’<19:8>,
Q2
Q3
Q4
Write to PC
Decode
Read
register ’f’
Process
Data
Write to
destination
No
No
No
No
operation
operation
operation
operation
INCF
CNT
Example:
GOTO THERE
Example:
Before Instruction
After Instruction
CNT
=
0FFh
PC
=
Address (THERE)
Z
C
DC
=
=
=
0
?
?
After Instruction
CNT
Z
C
DC
=
=
=
=
00h
1
1
1
DS39541A-page 236
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
INCFSZ
Syntax:
Increment f, skip if 0
INFSNZ
Syntax:
Increment f, skip if not 0
[ label ] INCFSZ f [,d [,a]]
[label] INFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register ’f’ are incre-
mented. If’d’is 0, the result is placed
in WREG. If ’d’ is 1, the result is
placed back in register ’f’ (default).
Description:
The contents of register 'f' are incre-
mented. If'd' is0, theresult isplaced
in WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If the result is 0, the next instruction,
which is already fetched, is dis-
carded, and a NOPis executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
If the result is not 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOPis executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Decode
Read
register ’f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT
HERE
ZERO
NZERO
INFSNZ REG
Example:
Example:
Before Instruction
Before Instruction
PC
=
Address (HERE)
PC
=
Address (HERE)
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
REG
If REG
PC
If REG
PC
=
≠
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 237
PIC18C601/801
IORLW
Inclusive OR literal with WREG
IORWF
Inclusive OR WREG with f
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORWF f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(WREG) .OR. k → WREG
N,Z
Operation:
(WREG) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N,Z
The contents of WREG are OR’ed
with the eight bit literal 'k'. The result
is placed in WREG.
0001
00da
ffff
ffff
Description:
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Words:
Cycles:
1
1
IORLW
35h
Example:
Before Instruction
Q Cycle Activity:
Q1
WREG
=
=
=
9Ah
?
?
Q2
Q3
Q4
N
Z
Decode
Read
register ’f’
Process
Data
Write to
destination
After Instruction
WREG
N
Z
=
=
=
0BFh
1
0
IORWF RESULT, W
Example:
Before Instruction
RESULT =
13h
91h
?
WREG
=
=
=
N
Z
?
After Instruction
RESULT =
13h
93h
1
WREG
=
=
=
N
Z
0
DS39541A-page 238
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
LFSR
Load FSR
MOVF
Move f
Syntax:
Operands:
[ label ] LFSR f,k
Syntax:
Operands:
[ label ] MOVF f [,d [,a]]
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ’k’ is loaded into
the file select register pointed to
by ’f’.
Description:
The contents of register ’f’ is moved
to a destination dependent upon the
status of ’d’. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result
is placed back in register 'f'(default).
Location 'f' can be anywhere in the
256 byte Bank. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
’k’ MSB
Process
Data
Write
literal’k’MSB
to FSRfH
Words:
Cycles:
1
1
Decode
Read literal
’k’ LSB
Process
Data
Writeliteral’k’
to FSRfL
Q Cycle Activity:
Q1
Q2
Q3
Q4
LFSR FSR2, 3ABh
Example:
Decode
Read
register ’f’
Process
Data
Write
WREG
After Instruction
FSR2H
=
=
03h
0ABh
FSR2L
MOVF
REG, W
Example:
Before Instruction
REG
WREG
N
=
=
=
=
22h
0FFh
?
?
Z
After Instruction
REG
WREG
N
=
=
=
=
22h
22h
0
Z
0
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 239
PIC18C601/801
MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[label] MOVFF fs,fd
Syntax:
[ label ] MOVLB k
0 ≤ k ≤ 255
k → BSR
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
None
Operation:
(fs) → fd
0000
0001
kkkk
kkkk
Status Affected:
None
The 8-bit literal ’k’ is loaded into
the Bank Select Register (BSR).
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
1
1
Description:
The contents of source register ’fs’
aremovedtodestinationregister’fd’.
Location of source ’fs’ can be any-
where in the 4096 byte data space
(000htoFFFh),andlocationofdesti-
nation’fd’canalsobeanywherefrom
000h to FFFh.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
Process
Data
Write
literal ’k’ to
BSR
’k’
Either source or destination can be
WREG (a useful special situation).
MOVLB
05h
Example:
Before Instruction
MOVFFis particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
BSR register
=
=
02h
After Instruction
BSR register
05h
The MOVFFinstruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ’f’
(dest)
No dummy
read
MOVFF
REG1, REG2
Example:
Before Instruction
REG1
=
=
33h
11h
REG2
After Instruction
REG1
=
=
33h,
33h
REG2
DS39541A-page 240
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
MOVLW
Move literal to WREG
[ label ] MOVLW k
0 ≤ k ≤ 255
MOVWF
Syntax:
Move WREG to f
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
k → WREG
Operation:
(WREG) → f
None
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight bit literal ’k’ is loaded into
WREG.
Description:
MovedatafromWREGtoregister’f’.
Location ’f’ can be anywhere in the
256 byte Bank. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Q Cycle Activity:
Q1
MOVLW
5Ah
Example:
Q2
Q3
Q4
After Instruction
Decode
Read
register ’f’
Process
Data
Write
register ’f’
WREG
=
0x5A
MOVWF
REG
Example:
Before Instruction
WREG
=
4Fh
REG
=
0FFh
After Instruction
WREG
REG
=
=
4Fh
4Fh
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 241
PIC18C601/801
MULLW
Multiply Literal with WREG
MULWF
Syntax:
Multiply WREG with f
Syntax:
[ label ] MULLW
0 ≤ k ≤ 255
k
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(WREG) x k → PRODH:PRODL
Operation:
(WREG) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is
carried out between the contents
of WREG and the 8-bit literal ’k’.
The 16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
Description:
An unsigned multiplication is
carried out between the contents
of WREG and the register file
location ’f’. The 16-bit result is
stored in the PRODH:PRODL
register pair. PRODH contains
the high byte.
WREG is unchanged.
None of the status flags are
affected.
Both WREG and ’f’ are
unchanged.
Note that neither overflow nor
carry is possible in this operation.
A zero result is possible but not
detected.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this operation.
A zero result is possible but not
detected. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write
registers
PRODH:
PRODL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
MULLW
C4h
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ’f’
Process
Data
Write
WREG
PRODH
PRODL
=
=
=
0E2h
registers
PRODH:
PRODL
?
?
After Instruction
WREG
=
=
=
0E2h
0ADh
08h
MULWF
REG
Example:
PRODH
PRODL
Before Instruction
WREG
REG
PRODH
PRODL
=
=
=
=
0C4h
0B5h
?
?
After Instruction
WREG
=
=
=
=
0C4h
0B5h
8Ah
REG
PRODH
PRODL
94h
DS39541A-page 242
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
NEGF
Negate f
NOP
No Operation
[ label ] NOP
None
Syntax:
Operands:
[label] NEGF f [,a]
Syntax:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
No operation
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Words:
No operation.
Description:
Location ’f’ is negated using two’s
complement. The result is placed in
the data memory location 'f'. If ’a’ is
0, the Access Bank will be selected,
overriding the BSR value. If ’a’ is 1,
the Bank will be selected as per the
BSR value.
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
register ’f’
NEGF
REG
Example:
Before Instruction
REG
N
OV
C
DC
Z
=
=
=
=
=
=
0011 1010[3Ah]
?
?
?
?
?
After Instruction
REG
N
OV
C
DC
Z
=
=
=
=
=
=
1100 0110[0C6h]
1
0
0
0
0
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 243
PIC18C601/801
POP
Pop Top of Return Stack
[ label ] POP
None
PUSH
Push Top of Return Stack
[ label ] PUSH
None
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
(TOS) → bit bucket
None
(PC+2) → TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the previ-
ous value that was pushed onto the
return stack.
The PC+2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
Thisinstructionallowsimplementing
a software stack by modifying TOS,
and then push it onto the return
stack.
Thisinstructionisprovidedtoenable
the user to properly manage the
return stack to incorporate a soft-
ware stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Push PC+2
onto return
stack
No
operation
No
operation
Q2
Q3
Q4
Decode
No
operation
Pop TOS
value
No
operation
PUSH
Example:
POP
GOTO
Example:
Before Instruction
NEW
TOS
=
=
00345Ah
000124h
PC
Before Instruction
TOS
=
=
0031A2h
014332h
Stack (1 level down)
After Instruction
PC
TOS
=
=
=
000126h
000126h
00345Ah
After Instruction
Stack (1 level down)
TOS
PC
=
=
014332h
NEW
DS39541A-page 244
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 ≤ n ≤ 1023
(PC) + 2 → TOS,
n
Syntax:
[ label ] RESET
None
Operands:
Operation:
Operands:
Operation:
Reset all registers and flags that are
affected by a MCLR Reset.
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the new
address will be PC+2+2n. This
instruction is a two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Words:
Cycles:
1
2
RESET
Example:
After Instruction
Registers =
Q Cycle Activity:
Q1
Reset Value
Reset Value
Q2
Q3
Q4
Flags*
=
Decode
Read literal
Process
Data
Write to PC
’n’
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
HERE
RCALL
Jump
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
PC
=
Address (Jump)
TOS =
Address (HERE+2)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 245
PIC18C601/801
RETFIE
Return from Interrupt
RETLW
Return Literal to WREG
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
[ label ] RETFIE [s]
s ∈ [0,1]
Syntax:
Operands:
Operation:
Operands:
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → WREG,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight-bit literal
'k'. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Status Affected:
Encoding:
None
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting the either the
high or low priority global interrupt
enable bit. If ’s’ = 1, the contents
of the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STATUS and BSR. If
’s’ = 0, no update of these
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Pop PC from
stack, write to
WREG
No
No
No
No
operation
operation
operation
operation
registers occurs (default).
Words:
Cycles:
1
2
Example:
CALL TABLE ; WREG contains table
Q Cycle Activity:
Q1
;
;
;
offset value
WREG now has
table value
Q2
Q3
Q4
Decode
No
No
operation
Pop PC
from stack
:
operation
TABLE
Set GIEH or
GIEL
ADDWF PCL
RETLW k0
RETLW k1
:
; WREG = offset
; Begin table
;
No
No
No
operation
No
operation
operation
operation
:
RETLW kn
; End of table
RETFIE
1
Example:
After Interrupt
PC
Before Instruction
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
WREG
=
07h
WREG
BSR
STATUS
GIE/GIEH, PEIE/GIEL
After Instruction
WREG
=
value of kn
DS39541A-page 246
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN [s]
s ∈ [0,1]
RLCF
Rotate Left f through Carry
Syntax:
Operands:
[ label ] RLCF f [,d [,a]]
Operands:
Operation:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
Operation:
(f<n>) → dest<n+1>,
(f<7>) → C,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
(C) → dest<0>
Status Affected:
Encoding:
C,N,Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register 'f' are
rotated one bit to the left through the
Carry Flag. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result
is storedback inregister'f'(default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ’s’ = 1, the contents of
the shadow registers WS, STA-
TUSS and BSRS are loaded into
their corresponding registers,
WREG, STATUS and BSR. If
’s’ = 0, no update of these
register f
C
registers occurs (default).
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
operation
Process
Data
Pop PC
from stack
Decode
Read
register ’f’
Process
Data
Write to
destination
No
No
No
No
operation
operation
operation
operation
RLCF
REG, W
Example:
Before Instruction
REG
C
N
Z
=
1110 0110
RETURN
Example:
=
=
=
0
?
?
After Call
PC
=
TOS
After Instruction
RETURN FAST
REG
=
=
=
=
=
1110 0110
1100 1100
1
1
0
Before Instruction
WREG
WRG
STATUS =
BSR
=
04h
00h
00h
C
N
Z
=
After Instruction
WREG
STATUS =
BSR
PC
=
04h
00h
00h
TOS
=
=
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 247
PIC18C601/801
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f [,d [,a]]
Syntax:
Operands:
[ label ] RRCF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n+1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n-1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
C,N,Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ’f’ are
rotated one bit to the left. If ’d’ is 0
the result is placed in WREG. If ’d’ is
1, theresultisstored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
Description:
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result
isplacedbackinregister'f'(default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ’f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
Process
Write to
register ’f’
Data
destination
RLNCF
REG
Example:
Before Instruction
RRCF
REG, W
Example:
REG
=
1010 1011
N
Z
=
=
?
?
Before Instruction
REG
=
1110 0110
C
N
Z
=
=
=
0
?
?
After Instruction
REG
N
Z
=
=
=
0101 0111
0
0
After Instruction
REG
WREG
C
N
Z
=
=
=
=
=
1110 0110
0111 0011
0
0
0
DS39541A-page 248
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
RRNCF
Syntax:
Rotate Right f (no carry)
SETF
Set f
[ label ] RRNCF f [,d [,a]]
Syntax:
Operands:
[label] SETF f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n-1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N,Z
Description:
Thecontentsofthespecifiedregister
are set to FFh. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
0100
00da
ffff
ffff
Description:
The contents of register ’f’ are
rotated one bit to the right. If ’d’ is 0,
the result is placed in WREG. If ’d’ is
1, the result is placed back in regis-
ter 'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Words:
Cycles:
1
1
SETF
REG
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
=
5Ah
Q2
Q3
Q4
After Instruction
REG
Decode
Read
register ’f’
Process
Data
Write to
destination
0FFh
RRNCF
REG
Example 1:
Before Instruction
REG
N
Z
=
=
=
1101 0111
?
?
After Instruction
REG
N
Z
=
=
=
1110 1011
1
0
RRNCF
REG, 0, 0
Example 2:
Before Instruction
WREG
REG
N
=
=
=
=
?
1101 0111
?
?
Z
After Instruction
WREG
REG
N
=
=
=
=
1110 1011
1101 0111
1
0
Z
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 249
PIC18C601/801
SLEEP
SUBFWB
Syntax:
Enter SLEEP mode
[ label ] SLEEP
None
Subtract f from WREG with borrow
Syntax:
[ label ] SUBFWB f [,d [,a]]
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(WREG) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N,OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register 'f' and carry flag
(borrow) from WREG (2’s comple-
ment method). If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result
is stored in register 'f' (default) . If ’a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Description:
The power-down status bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
No
operation
Process
Data
Go to
sleep
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
SLEEP
Example:
Before Instruction
TO
=
?
PD
=
?
After Instruction
TO
=
1 †
PD
=
0
† If WDT causes wake-up, this bit is cleared.
DS39541A-page 250
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
SUBFWB (Cont.)
SUBLW
Subtract WREG from literal
[ label ] SUBLW k
0 ≤ k ≤ 255
SUBFWB
REG
Example 1:
Syntax:
Before Instruction
Operands:
Operation:
REG
WREG
C
=
=
=
3
2
1
k – (WREG) → WREG
Status Affected:
Encoding:
N,OV, C, DC, Z
After Instruction
0000
1000
kkkk
kkkk
REG
WREG
C
Z
N
=
=
=
=
=
0FFh
Description:
WREGissubtractedfromtheeight
bit literal 'k'. The result is placed in
WREG.
2
0
0
1
; result is negative
Words:
Cycles:
1
1
SUBFWB
REG
Example 2:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
REG
WREG
C
=
=
=
2
5
1
Decode
Read
literal ’k’
Process
Data
Write to
WREG
After Instruction
SUBLW 02h
Example 1:
REG
=
=
=
=
=
2
3
1
0
0
Before Instruction
WREG
WREG
C
=
=
1
?
C
Z
N
; result is positive
After Instruction
WREG
C
Z
=
=
=
=
1
SUBFWB
REG
Example 3:
1
0
0
; result is positive
Before Instruction
REG
WREG
C
=
=
=
1
2
0
N
SUBLW 02h
Example 2:
After Instruction
Before Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0
2
1
1
0
WREG
C
=
=
2
?
; result is zero
After Instruction
WREG
C
Z
=
=
=
=
0
1
1
0
; result is zero
N
SUBLW 02h
Example 3:
Before Instruction
WREG
C
=
=
3
?
After Instruction
WREG
C
Z
=
=
=
=
0FFh ; (2’s complement)
0
0
1
; result is negative
N
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 251
PIC18C601/801
SUBWF
Subtract WREG from f
SUBWF (Cont.)
SUBWF
REG
Syntax:
[ label ] SUBWF f [,d [,a]]
Example 1:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Before Instruction
REG
WREG
C
=
=
=
3
2
?
Operation:
(f) – (WREG) → dest
After Instruction
Status Affected:
Encoding:
N,OV, C, DC, Z
REG
WREG
C
Z
N
=
=
=
=
=
1
2
1
0
0
0101
11da
ffff
ffff
; result is positive
Description:
Subtract WREG from register 'f'
(2’scomplementmethod).If'd'is0,
the result is stored in WREG. If 'd'
is 1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
AccessBankwillbeselected,over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
SUBWF
REG, W
Example 2:
Before Instruction
REG
WREG
C
=
=
=
2
2
?
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
2
0
1
1
0
Words:
Cycles:
1
1
; result is zero
Q Cycle Activity:
Q1
Q2
Q3
Q4
SUBWF
REG
Example 3:
Decode
Read
register ’f’
Process
Data
Write to
destination
Before Instruction
REG
WREG
C
=
=
=
1
2
?
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0FFh ;(2’s complement)
2
0
0
1
; result is negative
DS39541A-page 252
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Subtract WREG from f with
Borrow
SUBWFB
SUBWFB (Cont.)
Example 1:
Before Instruction
SUBWFB REG
Syntax:
[ label ] SUBWFB f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
REG
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
WREG
C
Operation:
(f) – (WREG) – (C) → dest
After Instruction
Status Affected:
Encoding:
N,OV, C, DC, Z
REG
WREG
C
Z
N
=
=
=
=
=
0Ch
0Dh
1
0
0
(0000 1011)
(0000 1101)
0101
10da
ffff
ffff
Description:
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s com-
plement method). If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
; result is positive
Example 2:
Before Instruction
SUBWFB REG, W
REG
WREG
C
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
1Bh
00h
1
1
0
(0001 1011)
Words:
Cycles:
1
1
; result is zero
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example 3:
Before Instruction
SUBWFB REG
Decode
Read
register ’f’
Process
Data
Write to
destination
REG
WREG
C
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
After Instruction
REG
WREG
C
Z
N
=
=
=
=
=
0F5h
0Eh
0
0
1
(1111 0100) [2’s comp]
(0000 1101)
; result is negative
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 253
PIC18C601/801
SWAPF
Syntax:
Swap nibbles in f
[ label ] SWAPF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
None
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of reg-
ister ’f’ are exchanged. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in register ’f’
(default). If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
SWAPF
REG
Example:
Before Instruction
REG
=
53h
35h
After Instruction
REG
=
DS39541A-page 254
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TBLRD
Table Read
TBLRD (Cont.)
TBLRD *+ ;
Syntax:
[ label ] TBLRD ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(00A356h)
=
=
=
55h
00A356h
34h
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) +1 → TBLPTR;
if TBLRD *-,
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
TBLRD +* ;
Example 2:
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) -1 → TBLPTR;
if TBLRD +*,
(TBLPTR) +1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT;
Before Instruction
TABLAT
=
=
=
=
0AAh
01A357h
12h
TBLPTR
MEMORY(01A357h)
MEMORY(01A358h)
34h
After Instruction
Status Affected: None
TABLAT
TBLPTR
=
=
34h
01A358h
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
Description:
This instruction is used to read the con-
tents of Program Memory (P.M.). To
address the program memory, a pointer
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2 Mbyte address range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRDinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No
No
No
operation
operation
(Read
operation
operation
(Write
Program
Memory)
TABLAT)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 255
PIC18C601/801
TBLWT
Table Write
TBLWT (Cont.)
TBLWT *+;
Syntax:
[ label ]
TBLWT ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(00A356h)
=
=
=
55h
00A356h
0FFh
if TBLWT*,
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
TBLPTR - No Change;
if TBLWT*+,
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
(TBLPTR) +1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
(TBLPTR) -1 → TBLPTR;
if TBLWT+*,
After Instructions (table write completion)
TABLAT
TBLPTR
MEMORY(00A356h)
=
=
=
55h
00A357h
55h
TBLWT +*;
Example 2:
Before Instruction
TABLAT
TBLPTR
MEMORY(01389Ah)
MEMORY(01389Bh)
=
=
=
=
34h
01389Ah
0FFh
0FFh
(TBLPTR) +1 → TBLPTR;
(TABLAT) → Prog Mem (TBLPTR) or
Holding Register;
After Instruction (table write completion)
TABLAT
=
=
=
=
34h
TBLPTR
MEMORY(01389Ah)
MEMORY(01389Bh)
01389Bh
0FFh
34h
Status Affected:
Encoding:
None
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to program the
contents of Program Memory (P.M.).
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2 MByte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLWTinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2 (many if long write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
operation
No operation
(Read
TABLAT)
No
operation
No operation
(Write to Holding
Register or Memory)
DS39541A-page 256
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TSTFSZ
Syntax:
Test f, skip if 0
XORLW
Exclusive OR literal with WREG
[ label ] TSTFSZ f [,a]
Syntax:
[ label ]
XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(WREG) .XOR. k → WREG
Operation:
skip if f = 0
None
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
Description:
The contents of WREG are
XOR’edwiththe8-bitliteral'k'. The
result is placed in WREG.
Description:
If ’f’= 0, the next instruction, fetched
during the current instruction exe-
cution, is discarded and a NOPis
executed, making this a two-cycle
instruction. If ’a’ is 0, the Access
Bank willbeselected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
Write to
WREG
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction
Example:
XORLW 0AFh
Before Instruction
Q Cycle Activity:
Q1
WREG
N
Z
=
=
=
0B5h
?
?
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
No
operation
After Instruction
WREG
N
Z
=
=
=
1Ah
0
0
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ CNT
:
:
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
=
=
≠
=
00h,
Address (ZERO)
00h,
PC
If CNT
PC
Address (NZERO)
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 257
PIC18C601/801
XORWF
Syntax:
Exclusive OR WREG with f
[ label ] XORWF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(WREG) .XOR. (f) → dest
Status Affected:
Encoding:
N,Z
0001
10da
ffff
ffff
Description:
ExclusiveORthecontentsofWREG
with register ’f’. If ’d’is 0, the result is
stored in WREG. If ’d’ is 1, the result
is stored back in the register ’f’
(default). If’a’is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Example:
XORWF
REG
Before Instruction
REG
WREG
N
=
0AFh
0B5h
?
=
=
=
Z
?
After Instruction
REG
WREG
N
=
=
=
=
1Ah
0B5h
0
Z
0
DS39541A-page 258
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
The MPLAB IDE allows you to:
21.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
21.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD for PIC16F87X
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
21.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
21.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 259
PIC18C601/801
21.4 MPLINK Object Linker/
MPLIB Object Librarian
21.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
21.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
21.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS39541A-page 260
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
21.8 MPLAB ICD In-Circuit Debugger
21.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC16F87X and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. The MPLAB ICD utilizes
the in-circuit debugging capability built into the
PIC16F87X. This feature, along with Microchip’s
In-Circuit Serial ProgrammingTM protocol, offers cost-
effective in-circuit FLASH debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by watching variables, single-
stepping and setting break points. Running at full
speed enables testing hardware in real-time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
21.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
21.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
21.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 261
PIC18C601/801
21.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
21.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
21.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS39541A-page 262
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
TABLE 21-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t K l a i E d v n a s d r a B o o m D e
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 263
PIC18C601/801
NOTES:
DS39541A-page 264
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
22.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to VSS............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports (combined) ....................................................................................................200 mA
Maximum current sourced by all ports (combined) ...............................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 265
PIC18C601/801
FIGURE 22-1:
PIC18C601/801 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC18C601/801
4.2V
3.5 V
3.0 V
2.5 V
2.0 V
25 MHz
Frequency
FIGURE 22-2:
PIC18C601/801 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC18C601/801
4.2V
3.5 V
3.0 V
2.5 V
2.0 V
25 MHz
16 MHz
4 MHz
Frequency
FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz where VDDAPPMIN < 3
FMAX = (7.5 MHz/V) (VDDAPPMIN - 3.0 V) + 16 MHz where VDDAPPMIN > 3
Note: VDDAPP is the minimum voltage of the PICmicro® device in the application.
DS39541A-page 266
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
22.1 DC Characteristics
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18LC601/801
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18C601/801
(Industrial, Extended)
Param
No.
Symbol
Characteristic/
Device
Min
Typ
Max Units
Conditions
D001
VDD
Supply Voltage
PIC18LC601/801
PIC18C601/801
2.0
4.2
1.5
—
—
—
5.5
5.5
—
V
V
V
D001
D002
VDR
RAM Data Retention
Voltage(1)
D003
D004
VPOR
VDD Start Voltage to
ensure internal
Power-on Reset signal
—
—
—
0.7
V
See section on Power-on Reset
for details
SVDD
VDD Rise Rate to
ensure internal Power-
on Reset signal
0.05
—
V/ms See section on Power-on Reset
for details
Legend: Rows with industrial-extended data are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing
RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc option, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 267
PIC18C601/801
22.1 DC Characteristics (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18LC601/801
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18C601/801
(Industrial, Extended)
Param
No.
Symbol
Characteristic/
Device
Min
Typ
Max Units
Conditions
D010
IDD
Supply Current(2,4)
PIC18LC601/801
RC osc option
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
—
TBD
TBD
TBD
TBD
45
mA FOSC = 4 MHz, VDD = 2.5V
D010
PIC18C601/801
PIC18LC601/801
PIC18C601/801
PIC18LC601/801
PIC18C601/801
PIC18LC601/801
RC osc options
mA FOSC = 4 MHz, VDD = 4.2V
D010A
D010A
D010C
D010C
D013
LP osc option
µA
µA
FOSC = 32 kHz, VDD = 2.5V
LP osc option
FOSC = 32 kHz, VDD = 4.2V
EC osc option,
mA FOSC = 25 MHz, VDD = 5.5V
EC osc option,
mA FOSC = 25 MHz, VDD = 5.5V
45
HS osc options
—
—
—
—
TBD
50
mA FOSC = 6 MHz, VDD = 2.5V
mA FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc option
—
—
50
mA FOSC = 10 MHz, VDD = 5.5V
D013
PIC18C601/801
HS osc option
—
—
—
—
50
50
mA FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc option
mA FOSC = 10 MHz, VDD = 5.5V
D014
D014
PIC18LC601/801
PIC18C601/801
Timer1 osc option
FOSC = 32 kHz, VDD = 2.5V
FOSC = 32 kHz, VDD = 2.5V, 25°C
OSCB osc option
—
—
—
—
48
TBD
µA
µA
—
—
—
—
TBD
TBD
µA
µA
FOSC = 32 kHz, VDD = 4.2V
FOSC = 32 kHz, VDD = 4.2V, 25°C
Legend: Rows with industrial-extended data are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing
RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc option, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
DS39541A-page 268
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
22.1 DC Characteristics (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18LC601/801
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18C601/801
(Industrial, Extended)
Param
No.
Symbol
Characteristic/
Device
Min
Typ
Max Units
Conditions
D020
IPD
Power-down Current(3)
PIC18LC601/801
—
—
—
TBD
—
—
5
36
TBD
µA
µA
µA
VDD = 2.5V, -40°C to +85°C
VDD = 5.5V, -40°C to +85°C
VDD = 2.5V, 25°C
D020
PIC18C601/801
—
—
TBD
—
TBD
36
µA
µA
VDD = 4.2V, -40°C to +85°C
VDD = 5.5V, -40°C to +85°C
D020A
D021B
—
—
TBD
µA
µA
VDD = 4.2V, 25°C
VDD = 4.2V, -40°C to +125°C
VDD = 5.5V, -40°C to +125°C
—
—
TBD
—
TBD
42
D022
∆IWDT
Module Differential Current
PIC18LC801/601
Watchdog Timer
—
—
—
—
TBD
6.5
—
TBD
12
TBD
TBD
µA
µA
µA
µA
VDD = 2.5V
VDD = 3.0V
VDD = 5.5V
VDD = 2.5V, 25°C
—
D022
PIC18C601/801
Watchdog Timer
—
—
—
—
—
—
TBD
TBD
TBD
µA
µA
µA
VDD = 5.5V, -40°C to +85°C
VDD = 5.5V, -40°C to +125°C
VDD = 4.2V, 25°C
D022B
D022B
∆ILVD
PIC18LC801/601
Low Voltage Detect
—
—
—
—
50
TBD
µA
µA
µA
µA
µA
VDD = 2.5V
VDD = 2.5V, 25°C
PIC18C601/801
Low Voltage Detect
—
—
—
—
—
—
TBD
TBD
TBD
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
VDD = 4.2V, 25°C
D025
D025
∆IOSCB
PIC18LC801/601
Timer1 Oscillator
—
—
—
—
3
TBD
µA
µA
VDD = 2.5V
VDD = 2.5V, 25°C
PIC18C601/801
Timer1 Oscillator
—
—
—
—
—
—
TBD
TBD
TBD
µA
µA
µA
VDD = 4.2V, -40°C to +85°C
VDD = 4.2V, -40°C to +125°C
VDD = 4.2V, 25°C
Legend: Rows with industrial-extended data are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing
RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC osc option, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 269
PIC18C601/801
22.2 DC Characteristics:
PIC18C801 (Industrial, Extended)
PIC18LC601/801 (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param Symbol
No.
Characteristic/
Device
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
VSS
0.15VDD
0.8
V
V
VDD < 4.5V
—
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
0.2 VDD
0.3VDD
V
V
D032
MCLR
VSS
VSS
0.2 VDD
0.3VDD
V
V
D032A
OSC1 (in XT, HS and LP modes)
and T1OSI
D033
VIH
OSC1(in RC mode)(1)
Input High Voltage
I/O ports:
VSS
0.2 VDD
V
D040
D040A
D041
with TTL buffer
0.25VDD + 0.8V
2.0
VDD
VDD
V
V
VDD < 4.5V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
0.8VDD
0.7VDD
VDD
VDD
V
V
D042
MCLR
0.8VDD
0.7VDD
VDD
VDD
V
V
D042A
OSC1 (in HS and LP modes) and
T1OSI
D043
VHYS
D050
IIL
OSC1 (RC mode)(1)
0.9VDD
VDD
TBD
1
V
V
Hysteresis of Schmitt Trigger Inputs
TBD
Input Leakage Current(2,3)
D060
I/O ports
—
µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
MCLR
—
—
5
5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD
D063
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070 IPURB
50
400
µA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator option, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS39541A-page 270
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
22.2 DC Characteristics:
PIC18C801 (Industrial, Extended)
PIC18LC601/801 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param Symbol
No.
Characteristic/
Min
Max
Units
Conditions
Device
Output Low Voltage
I/O ports
VOL
D080
—
—
—
—
—
—
—
—
0.6
0.6
V
V
V
V
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
D080A
D083
OSC2/CLKO
(RC mode)
0.6
D083A
D084
0.6
System Bus mode
Control Signals
TBD
TBD
TBD
TBD
D084A
D085
D085A
-40°C to +125°C
VOH
Output High Voltage(3)
D090
I/O ports
VDD - 0.7
VDD - 0.7
VDD - 0.7
VDD - 0.7
TBD
—
—
—
—
—
—
—
—
V
V
V
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
D090A
D092
OSC2/CLKO
(RC mode)
D092A
D093
System Bus mode
Control Signals
D093A
D094
TBD
TBD
D094A
TBD
-40°C to +125°C
VOD
Open-drain High Voltage
D150
—
7.5
V
RA4 pin
Capacitive Loading Specs on Output Pins
D101 CIO
D102 CB
All I/O pins and OSC2
(in RC mode)
—
50
pF To meet the AC Timing
Specifications
pF In I2C mode
SCL, SDA
—
400
Note 1: In RC oscillator option, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 271
PIC18C601/801
FIGURE 22-3:
LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 22-1: LOW VOLTAGE DETECT CHARACTERISTICS
VCC = 2.0V to 5.5V
Commercial (C): TAMB = 0°C to +70°C
Industrial (I):
Symbol
VLVD
TAMB = -40°C to +85°C
Param
No.
Characteristic
Min Typ† Max Units
Conditions
D420
LVV = 0001
2.0
2.2
2.4
2.5
2.7
2.8
3.0
3.3
3.5
3.6
3.8
4.0
4.2
4.5
—
2.06
2.27
2.47
2.58
2.78
2.89
3.1
2.12
2.34
2.54
2.66
2.86
2.98
3.2
V
LVD Voltage on VDD
Transition High to
Low
LVV = 0010
LVV = 0011
LVV = 0100
LVV = 0101
LVV = 0110
LVV = 0111
LVV = 1000
LVV = 1001
LVV = 1010
LVV = 1011
LVV = 1100
LVV = 1101
LVV = 1110
V
V
V
V
V
V
3.41
3.61
3.72
3.92
4.13
4.33
4.64
15
3.52
3.72
3.84
4.04
4.26
4.46
4.78
50
V
V
V
V
V
V
V
D421
D422
D423
LVD Voltage Drift Temperature
Coefficient
TCVOUT
ppm/°C
Bandgap Voltage Drift with respect to
VDD Regulation
∆VBG/
∆VDD
VBG
—
—
—
50
µV/V
Bandgap Reference Voltage Value
1.22
V
Note: Production tested at TAMB = 25°C. Specifications over temperature limits guaranteed by characterization.
DS39541A-page 272
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
22.3 AC (Timing) Characteristics
22.3.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKO
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data-in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 273
PIC18C601/801
22.3.2
TIMING CONDITIONS
The temperature and voltages specified in Table 22-2
apply to all timing specifications, unless otherwise
noted. Figure 22-4 specifies the load conditions for the
timing specifications.
TABLE 22-2: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 22.1.
LC parts operate for industrial temperatures only.
FIGURE 22-4:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
DS39541A-page 274
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
22.3.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 22-5:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 22-3: EXTERNAL CLOCK TIMING REQUIREMENTS
Param No. Symbol Characteristic
FOSC External CLKI Frequency
Min
Typ
Max
Units
DC
DC
4
DC
DC
DC
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCY
—
—
—
—
4
25
6.25
25
200
4
25
6.25
200
—
MHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
kHz
ns
ns
ns
ns
µs
ns
ns
ns
µs
ns
µs
ns
ns
(Note 1)
Oscillator Frequency (Note 1)
Tosc External CLKI Period (Note 1)
4
5
1
250
40
40
160
5
250
40
160
5
160
2.5
10
—
—
—
—
—
Oscillator Period (Note 1)
—
100
100
—
DC
—
—
50
5
2
3
TCY
Instruction Cycle Time (Note 1)
TosL, External Clock in (OSC1) High or
TosH Low Time
4
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
ns
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based
on characterization data for that particular oscillator type under standard operating conditions, with the device exe-
cuting code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than
expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the
OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
TABLE 22-4: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
7
TPLL
PLL Start-up Time
—
2
ms
(Lock Time)
∆CLK
CLKOUT Stability (Jitter) using PLL
-2
+2
%
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 275
PIC18C601/801
FIGURE 22-6:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-5: CLKOUT AND I/O TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
(1)
10
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns
(1)
11
—
ns
(1)
12
13
14
15
16
17
18
18A
TckR
CLKOUT rise time
—
ns
(1)
TckF
CLKOUT fall time
—
ns
(1)
TckL2ioV CLKOUT ↓ to Port out valid
—
0.5TCY + 20
ns
(1)
TioV2ckH Port in valid before CLKOUT ↑
TckH2ioI Port in hold after CLKOUT ↑
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
TosH2ioI OSC1↑ (Q2 cycle) PIC18C601/801
0.25TCY + 25
—
—
ns
(1)
0
ns
—
150
—
ns
ns
ns
100
200
to Port input invalid
(I/O in hold time)
PIC18LC601/801
—
19
TioV2osH Port input valid to OSC1↑
0
—
—
ns
(I/O in setup time)
20
TioR
TioF
Port output rise
time
PIC18C601/801
—
—
10
—
10
—
—
—
25
60
25
60
—
—
ns
ns
ns
ns
ns
ns
20A
21
PIC18LC601/801
Port output fall time PIC18C601/801
PIC18LC601/801
—
21A
22††
23††
—
TINP
INT pin high or low time
TCY
TCY
TRBP
RB7:RB4 change INT high or low time
††These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO pin output is 4 x TOSC.
DS39541A-page 276
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-7:
PROGRAM MEMORY READ TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
Address
Data from external
Address
AD<15:0>
163
162
150
151
160
155
161
166
167
168
169
ALE
164
CS1
CS2
171
or CSIO
171A
OE
165
Operating Conditions: 2.0V <VCC <5.5V, -40°C <TA <125°C, unless otherwise stated.
TABLE 22-6: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
150
151
155
160
161
162
163
164
165
166
167
168
169
171
171A
TadV2alL Address out valid to ALE↓ (address setup time)
0.25TCY-10
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TalL2adl
TalL2oeL
ALE↓ to address out invalid (address hold time)
ALE ↓ to OE ↓
5
—
10
0.125TCY
—
—
TadZ2oeL AD high-Z to OE ↓ (bus release to OE)
ToeH2adD OE ↑ to AD driven
0
—
0.125TCY-5
—
—
TadV2oeH LS data valid before OE ↑ (data setup time)
ToeH2adl OE ↑ to data in invalid (data hold time)
20
—
—
0
—
—
—
TalH2alL
ALE pulse width
TCY
0.5TCY
0.25TCY
—
—
ToeL2oeH OE pulse width
0.5TCY-5
—
—
TalH2alH
Tacc
ALE↑ to ALE↑ (cycle time)
—
Address valid to data valid
0.75TCY-25
—
0.5TCY-25
0.625TCY+10
—
Toe
OE ↓ to data valid
—
TalL2oeH ALE ↓ to OE ↑
0.625TCY-10
0.25TCY-20
—
—
TalH2csL
Chip select active to ALE ↓
—
TubL2oeH AD valid to chip select active
—
10
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 277
PIC18C601/801
FIGURE 22-8:
8-BIT PROGRAM MEMORY FETCH TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
Address
Address
A<19:8>
166
150
151
161
Data
AD<7:0>
Data
Address
Address
162
162A
163
170
BA0
ALE
170A
CS1
CS2
or CSIO
OE
Operating Conditions: 2.0V <VCC <5.5V, -40°C <TA <125°C, FOSC max = 25MHz, unless otherwise stated.
TABLE 22-7: 8-BIT PROGRAM MEMORY FETCH TIMING REQUIREMENTS
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
150
151
TadV2alL Address out valid to ALE↓ (address setup time)
TalL2adl ALE↓ to address out invalid (address hold time)
0.25TCY-10
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
0.125TCY-5
20
161
ToeH2adD OE ↑ to AD driven
—
162
TadV2oeH LS data valid before OE ↑ (data setup time)
TadV2oeH MS data valid before OE ↑ (data setup time)
ToeH2adl OE ↑ to data in invalid (data hold time)
TalH2alH ALE↑ to ALE↑ (cycle time)
—
162A
163
0.25TCY+20
0
—
—
166
—
0.25TCY
—
170
TubH2oeH BA0 = 0 valid before OE ↑
0.25TCY-10
0.5TCY-10
170A
TubL2oeH BA0 = 1 valid before OE ↑
—
DS39541A-page 278
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-9:
PROGRAM MEMORY WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
Address
166
Data
Address
AD<15:0>
153
150
151
156
ALE
CS1, CS2,
or CSIO
154
WRH or
WRL
157A
157
UB or
LB
Operating Conditions: 2.0V <VCC <5.5V, -40°C <TA <125°C unless otherwise stated.
TABLE 22-8: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
150
151
153
154
156
157
157A
166
36
TadV2alL Address out valid to ALE↓ (address setup time)
TalL2adl ALE↓ to address out invalid (address hold time)
TwrH2adl WRn ↑ to data out invalid (data hold time)
0.25TCY-10
—
—
—
—
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
µs
5
5
—
TwrL
WRn pulse width
0.5TCY-5
0.5TCY-10
0.25TCY
0.125TCY-5
—
0.5TCY
—
TadV2wrH Data valid before WRn ↑ (data setup time)
TbsV2wrL Byte select valid before WRn ↓ (byte select setup time)
TwrH2bsI WRn ↑ to byte select invalid (byte select hold time)
TalH2alH ALE↑ to ALE↑ (cycle time)
—
—
0.25TCY
20
TIVRST
Time for Internal Reference Voltage to become stable
—
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 279
PIC18C601/801
FIGURE 22-10:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
7
—
—
µs
31
Watchdog Timer Time-out Period
(No Prescaler)
18
33
ms
32
33
34
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period
Power up Timer Period
—
28
—
—
72
2
1024TOSC
132
—
ms
µs
TOSC = OSC1 period
I/O Hi-Impedance from MCLR Low
or Watchdog Timer Reset
—
DS39541A-page 280
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-11:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-10: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
Tt0H
T0CKI High Pulse Width No Prescaler
With Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width No Prescaler
With Prescaler
0.5TCY + 20
10
T0CKI Period
No Prescaler
TCY + 10
With Prescaler
Greater of:
20 nS or TCY + 40
N
ns N = prescale value
(1, 2, 4,..., 256)
45
46
Tt1H
Tt1L
T1CKI Synchronous, no prescaler
0.5TCY + 20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
High
Time
Synchronous, PIC18C601/801
with prescaler
10
25
PIC18LC601/801
—
Asynchronous PIC18C601/801
30
—
PIC18LC601/801
50
—
T1CKI Synchronous, no prescaler
0.5TCY + 5
10
—
Low
Time
Synchronous, PIC18C601/801
with prescaler
—
PIC18LC601/801
25
—
Asynchronous PIC18C601/801
30
—
PIC18LC601/801
TBD
TBD
—
47
48
Tt1P
Ft1
T1CKI Synchronous
input
period
Greater of:
20 nS or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T1CKI oscillator input frequency range
Tcke2tmrI Delay from external T1CKI clock edge to
timer increment
2TOSC
7TOSC
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 281
PIC18C601/801
FIGURE 22-12:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture mode)
50
51
52
54
CCPx
(Compare or PWM mode)
53
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-11: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TccL
CCPx input low No Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
time
With
Prescaler
PIC18C601/801
PIC18LC601/801
10
20
0.5TCY + 20
10
51
TccH
CCPxinputhigh No Prescaler
time
With
Prescaler
PIC18C601/801
PIC18LC601/801
20
52
53
TccP
TccR
CCPx input period
3TCY + 40
N
N = prescale
value (1, 4 or 16)
CCPx output fall time
PIC18C601/801
PIC18LC601/801
PIC18C601/801
PIC18LC601/801
—
—
—
—
25
45
25
45
ns
ns
ns
ns
54
TccF
CCPx output fall time
DS39541A-page 282
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
Bit6 - - - - - -1
Bit6 - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
LSb In
73
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
ns
71
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25TCY + 30
40
ns (Note 1)
TscL
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge of
Byte2
1.5TCY + 40
100
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
ns
75
TdoR
SDO data output rise time
PIC18C601/801
PIC18LC601/801
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO data output fall time
SCK output rise time
(Master mode)
PIC18C601/801
PIC18LC601/801
79
80
TscF
SCK output fall time (Master mode)
TscH2doV, SDO data output valid after PIC18C601/801
TscL2doV SCK edge
PIC18LC601/801
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 283
PIC18C601/801
FIGURE 22-14:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
Bit6 - - - - - -1
Bit6 - - - -1
SDO
SDI
75, 76
MSb In
74
LSb In
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
Symbol
TscH
TscL
Characteristic
Min
Max Units Conditions
No.
71
SCK input high time
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25TCY + 30
40
ns (Note 1)
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40
100
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
ns
75
TdoR
SDO data output rise time PIC18C601/801
PIC18LC601/801
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO data output fall time
—
SCK output rise time
(Master mode)
PIC18C601/801
PIC18LC601/801
—
—
79
80
TscF
SCK output fall time (Master mode)
—
TscH2doV, SDO data output valid after PIC18C601/801
TscL2doV SCK edge
—
PIC18LC601/801
—
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.
DS39541A-page 284
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
Bit6 - - - - - -1
Bit6 - - - -1
77
75, 76
MSb In
74
LSb In
73
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-14: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Param
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
ns
71
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25TCY + 30
40
ns (Note 1)
TscL
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
ns
75
TdoR
SDO data output rise time
PIC18C601/801
PIC18LC601/801
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
77
78
TdoF
SDO data output fall time
—
10
—
TssH2doZ SS↑ to SDO output hi-impedance
TscR
SCK output rise time
(Master mode)
PIC18C601/801
PIC18LC601/801
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid after SCK PIC18C601/801
TscL2doV edge
PIC18LC601/801
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 285
PIC18C601/801
FIGURE 22-16:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
Bit6 - - - - - -1
Bit6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
LSb In
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-15: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
ns
71
TscH
TscL
TB2B
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
40
—
—
—
—
—
—
ns
71A
72
ns (Note 1)
ns
SCK input low time
(Slave mode)
1.25TCY + 30
40
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last clock edge of Byte1 to the 1st clock edge of Byte2
1.5TCY + 40
100
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
75
TdoR
SDO data output rise time
PIC18C601/801
PIC18LC601/801
—
25
45
25
50
25
45
25
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
76
77
78
TdoF
SDO data output fall time
—
TssH2doZ SS↑ to SDO output hi-impedance
TscR
10
SCK output rise time
(Master mode)
PIC18C601/801
PIC18LC601/801
—
—
79
80
TscF
SCK output fall time (Master mode)
—
TscH2doV, SDO data output valid after SCK
TscL2doV edge
PIC18C601/801
PIC18LC601/801
PIC18C601/801
PIC18LC601/901
—
—
100
50
82
83
TssL2doV SDO data output valid after SS↓
—
—
edge
100
—
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.
DS39541A-page 286
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-17:
I2C BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-16: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
START condition
91
92
93
THD:STA START condition
Hold time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
FIGURE 22-18:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 22-4 for load conditions.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 287
PIC18C601/801
TABLE 22-17: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock high time
4.0
—
µs
PIC18C601/801 must operate
at a minimum of 1.5 MHz
400 kHz mode
0.6
—
µs
PIC18C601/801 must operate
at a minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
µs
µs
PIC18C601/801 must operate
at a minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC18C601/801 must operate
at a minimum of 10 MHz
SSP module
1.5TCY
—
—
ns
ns
ns
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for Repeated
START condition
91
START condition hold 100 kHz mode
time
—
After this period the first clock
pulse is generated
400 kHz mode
—
106
107
92
Data input hold time
100 kHz mode
400 kHz mode
—
0
0.9
—
Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
STOPconditionsetup 100 kHz mode
time
—
400 kHz mode
—
109
110
Output valid from
clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
D102
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast mode I C bus device can be used in a standard mode I C bus system, but the requirement tsu;DAT ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
2
Before the SCL line is released, TR max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard mode I C bus
specification).
DS39541A-page 288
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-19:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-18: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
TSU:STA START condition
Setup time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for
Repeated START
condition
90
ns
ns
ns
ns
91
92
93
THD:STA START condition
Hold time
After this period, the first
clock pulse is generated
TSU:STO STOP condition
Setup time
THD:STO STOP condition
Hold time
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 22-20:
MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 22-4 for load conditions.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 289
PIC18C601/801
TABLE 22-19: MASTER SSP I2C BUS DATA REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock high time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
TLOW
TR
Clock low time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
101
102
103
90
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
1000
300
ms
SDA and SCL
rise time
100 kHz mode
400 kHz mode
—
ns Cb is specified to be
ns
from 10 to 400 pF
20 + 0.1Cb
1 MHz mode(1)
100 kHz mode
400 kHz mode
—
—
300
300
300
ns
TF
SDA and SCL
fall time
ns Cb is specified to be
ns
from 10 to 400 pF
20 + 0.1Cb
1 MHz mode(1)
—
100
—
—
ns
TSU:STA START condition 100 kHz mode
setup time
2(TOSC)(BRG + 1)
ms Only relevant for
ms
ms
ms After this period, the first
ms
Repeated START
condition
400 kHz mode
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
—
THD:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
91
hold time
clock pulse is generated
400 kHz mode
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
0.9
ms
ns
ms
THD:DAT Data input
hold time
100 kHz mode
400 kHz mode
0
0
106
107
92
1 MHz mode(1)
100 kHz mode
400 kHz mode
TBD
250
100
—
—
—
ns
TSU:DAT Data input
setup time
ns (Note 2)
ns
1 MHz mode(1)
TBD
—
—
—
ns
ms
ms
TSU:STO STOP condition 100 kHz mode
setup time
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
3500
1000
ms
ns
ns
TAA
Output validfrom 100 kHz mode
—
—
109
110
clock
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
—
4.7
1.3
—
—
—
ns
TBUF
Bus free time
ms Time the bus must be
ms
free before a new
transmission can start
1 MHz mode(1)
TBD
—
—
400
ms
pF
D102 Cb
Bus capacitive loading
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line. Before the SCL line is released, parameter #102 + parameter
#107 = 1000 + 250 = 1250 ns (for 100 kHz mode).
DS39541A-page 290
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-21:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 22-4 for load conditions.
122
TABLE 22-20: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units Conditions
No.
120
TckH2dtV SYNC XMIT (Master & Slave)
Clock high to data-out valid
PIC18C601/801
PIC18LC601/801
PIC18C601/801
PIC18LC601/801
PIC18C601/801
PIC18LC601/801
—
—
—
—
—
—
40
100
20
ns
ns
ns
ns
ns
ns
121
122
Tckrf
Tdtrf
Clock out rise time and fall time
(Master mode)
50
Data-out rise time and fall time
20
50
FIGURE 22-22:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 22-4 for load conditions.
TABLE 22-21: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (Master & Slave)
Data-hold before CK ↓ (DT hold time)
Data-hold after CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 291
PIC18C601/801
TABLE 22-22: A/D CONVERTER CHARACTERISTICS: PIC18C601/801 (INDUSTRIAL, EXTENDED)
PIC18LC601/801 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Resolution
Min
Typ
Max
Units
Conditions
A01
NR
—
—
—
—
10
TBD
bit VREF = VDD ≥ 3.0V
bit VREF = VDD < 3.0V
A03
A04
A05
A06
EIL
Integral linearity error
Differential linearity error
Full scale error
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
EDL
EFS
EOFF
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
Offset error
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
A10
A20
A20A
A21
A22
A25
A30
—
Monotonicity
guaranteed(3)
—
V
VSS ≤ VAIN ≤ VREF
VREF
Reference voltage
(VREFH - VREFL)
0
—
—
—
—
3
V
For 10-bit resolution
VREFH Reference voltage High
AVSS
—
—
—
—
AVDD + 0.3 V
AVDD
V
VREFL
VAIN
Reference voltage Low
Analog input voltage
AVSS - 0.3 V
AVSS - 0.3 V
—
V
VREF + 0.3 V
10.0
V
ZAIN
Recommended impedance of
analog voltage source
kΩ
A40
A50
IAD
A/D conversion PIC18C601/801
—
—
180
90
—
—
µA Average current
current (VDD)
consumption when
PIC18LC601/801
µA
A/D is on(1)
IREF
VREF input current(2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To
charge CHOLD, see
Section 17.0.
—
—
10
µA During A/D conversion
cycle.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is
selected as reference input.
2: Vss ≤ VAIN ≤ VREF
3: The A/D conversion result either increases or remains constant as the analog input increases.
DS39541A-page 292
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
FIGURE 22-23:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.This allows the
SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 22-23: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
20(5)
µs TOSC based, VREF ≥ 3.0V
130
TAD
A/D clock period
PIC18C601/801
1.6
PIC18LC601/801
PIC18C601/801
PIC18LC601/801
3.0
2.0
3.0
11
20(5)
6.0
9.0
12
µs TOSC based, VREF full range
µs A/D RC mode
µs A/D RC mode
TAD
131
132
TCNV Conversion time
(not including acquisition time)(1)
TACQ Acquisition time(3)
15
10
—
—
µs -40°C ≤ Temp ≤ 125°C
µs
0°C ≤ Temp ≤ 125°C
135
136
TSWC Switching time from convert → sample
TAMP Amplifier settling time(2)
—
(Note 4)
1
—
µs This may be used if the “new”
input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 17.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is
50Ω.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 293
PIC18C601/801
NOTES:
DS39541A-page 294
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
23.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables are not available at this time.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 295
PIC18C601/801
NOTES:
DS39541A-page 296
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
24.0 PACKAGING INFORMATION
24.1 Package Marking Information
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
PIC18C601-I/PT
YYWWNNN
0017017
68-Lead PLCC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC18C601-I/L
0017017
Example
80-Lead TQFP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18C801-I/PT
0017017
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 297
PIC18C601/801
Package Marking Information (Cont’d)
84-Lead PLCC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC18C801-I/L
0017017
DS39541A-page 298
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
L
A2
φ
β
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
64
64
.020
16
0.50
16
Pins per Side
Overall Height
n1
A
.039
.043
.039
.006
.024
.039
3.5
.047
1.00
1.10
1.00
0.15
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.037
.002
.018
.041
.010
.030
0.95
0.05
0.45
1.05
0.25
0.75
§
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.005
.007
.025
5
7
.482
.482
.398
.398
.009
.011
.045
15
0
11.75
11.75
9.90
9.90
0.13
0.17
0.64
5
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.007
.009
.035
10
12.00
12.00
10.00
10.00
0.18
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 299
PIC18C601/801
68-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D1 D
n 1 2
°
°
α
CH2 x 45
CH1 x 45
A3
A2
A
32°
c
B1
B
A1
p
β
D2
E2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
68
MAX
n
p
Number of Pins
Pitch
68
.050
17
1.27
17
Pins per Side
Overall Height
n1
A
.165
.173
.153
.028
.029
.045
.005
.990
.990
.954
.954
.920
.920
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
25.02
25.02
24.13
24.13
22.61
22.61
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
25.15
25.15
24.23
24.23
23.37
23.37
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.145
.020
.024
.040
.000
.985
.985
.950
.950
.890
.890
.008
.026
.013
0
.160
.035
.034
.050
.010
.995
.995
.958
.958
.930
.930
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
25.27
25.27
24.33
24.33
23.62
23.62
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-049
DS39541A-page 300
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
B
c
1
n
°
CH x 45
A
α
A2
φ
β
L
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
80
MAX
n
p
Number of Pins
Pitch
80
.020
20
0.50
20
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
Foot Length
Footprint (Reference)
Foot Angle
0
.541
.541
.463
.463
.004
.007
.025
5
7
.561
.561
.482
.482
.008
.011
.045
15
0
13.75
13.75
11.75
11.75
0.09
0.17
0.64
5
7
14.25
14.25
12.25
12.25
0.20
0.27
1.14
15
Overall Width
E
D
.551
.551
.472
.472
.006
.009
.035
10
14.00
14.00
12.00
12.00
0.15
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
CH
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-092
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 301
PIC18C601/801
84-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D1 D
n 1 2
α
CH2 x 45°
CH1 x 45°
A3
A2
A
32°
c
B1
B
A1
p
β
D2
E2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
68
MAX
n
p
Number of Pins
Pitch
68
.050
17
1.27
17
Pins per Side
Overall Height
n1
A
.165
.173
.153
.028
.029
.045
.005
.990
.990
.954
.954
.920
.920
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
25.02
25.02
24.13
24.13
22.61
22.61
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
25.15
25.15
24.23
24.23
23.37
23.37
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.145
.020
.024
.040
.000
.985
.985
.950
.950
.890
.890
.008
.026
.013
0
.160
.035
.034
.050
.010
.995
.995
.958
.958
.930
.930
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
25.27
25.27
24.33
24.33
23.62
23.62
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-093
DS39541A-page 302
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
APPENDIX A: DATA SHEET
REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
The differences between the PIC18C601/801 devices
listed in this data sheet are shown in Table B-1.
Revision A
This is a new data sheet.
TABLE B-1:
Feature
DEVICE DIFFERENCES
PIC18C601 PIC18C801
Maximum External
Program Memory
(Bytes)
256K
2M
Data Memory (Bytes)
A/D Channels
1.5K
8
1.5K
12
Package
Types
TQFP
PLCC
64-pin
68-pin
80-pin
84-pin
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 303
PIC18C601/801
APPENDIX C: DEVICE MIGRATIONS
APPENDIX D: MIGRATING FROM
OTHER PICmicro
This section is intended to describe the functional and
electrical specification differences when migrating
between functionally similar devices (such as from a
PIC16C74A to a PIC16C74B).
DEVICES
This discusses some of the issues in migrating from
other PICmicro devices to the PIC18CXXX family of
devices.
Not Applicable
D.1
PIC16CXXX to PIC18CXXX
See application note AN716.
D.2
PIC17CXXX to PIC18CXXX
See application note AN726.
DS39541A-page 304
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
APPENDIX E: DEVELOPMENT
TOOL VERSION
REQUIREMENTS
This lists the minimum requirements (software/
firmware) of the specified development tool to support
the devices listed in this data sheet.
MPLAB® IDE:
MPLAB® SIMULATOR:
MPLAB® ICE 3000:
TBD
TBD
PIC18C601/801 Processor Module:
Part Number - TBD
PIC18C601/801 Device Adapter:
Socket
Part Number
TBD
TBD
TBD
TBD
64-pin TQFP
68-pin PLCC
80-pin TQFP
84-pin PLCC
MPLAB® ICD:
PRO MATE® II:
PICSTART® Plus:
MPASMTM Assembler:
TBD
TBD
TBD
TBD
MPLAB® C18 C Compiler: TBD
Note: Please read all associated README.TXT
files that are supplied with the develop-
ment tools. These "read me" files will dis-
cuss product support and any known
limitations.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 305
PIC18C601/801
NOTES:
DS39541A-page 306
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
INDEX
Phase Lock Loop ...................................................... 23
PORTA
RA3:RA0 and RA5 Pins .................................. 103
RA4/T0CKI Pin ................................................ 104
PORTB
RB3 Pin ........................................................... 106
RB3:RB0 Port Pins .......................................... 106
RB7:RB4 Port Pins .......................................... 105
PORTC .................................................................... 108
PORTD
I/O Mode ......................................................... 110
System Bus Mode ........................................... 111
PORTD (In I/O Port Mode) ...................................... 124
PORTE
I/O Mode ......................................................... 113
System Bus Mode ........................................... 114
PORTF
RF2:RF0 Pins .................................................. 116
RF5:RF3 Pins .................................................. 117
RF7:RF6 Pins .................................................. 117
PORTG
I/O Mode ......................................................... 119
System Bus Mode ........................................... 120
PORTH
RH3:RH0 Pins (I/O Mode) ............................... 121
RH3:RH0 Pins (System Bus Mode) ................ 122
RH7:RH4 Pins ................................................. 121
PORTJ
I/O Mode ......................................................... 124
System Bus Mode ........................................... 125
Simplified PWM Diagram ........................................ 146
SSP (SPI Mode) ...................................................... 153
Timer0
16-bit Mode ..................................................... 128
8-bit Mode ....................................................... 128
Timer1 ..................................................................... 131
16-bit R/W Mode ............................................. 132
Timer2 ..................................................................... 136
Timer3 ..................................................................... 138
16-bit R/W Mode ............................................. 138
USART
A
A/D ................................................................................... 193
A/D Converter Flag (ADIF Bit) ................................. 195
A/D Converter Interrupt, Configuring ....................... 197
ADCON0 Register .......................................... 193, 195
ADCON1 Register .......................................... 193, 194
ADCON2 Register ................................................... 193
ADRES Register ............................................. 193, 195
Analog Port Pins, Configuring ................................. 199
Associated Registers ............................................... 201
Block Diagram ......................................................... 196
Block Diagram, Analog Input Model ........................ 197
Configuring the Module ........................................... 197
Conversion Clock (TAD) ........................................... 199
Conversion Status (GO/DONE Bit) .......................... 195
Conversions ............................................................. 200
Converter Characteristics ............................... 272, 292
Effects of a RESET .................................................. 206
Equations
Acquisition Time .............................................. 198
Minimum Charging Time ................................. 198
Operation During SLEEP ......................................... 206
Sampling Requirements .......................................... 198
Sampling Time ......................................................... 198
Special Event Trigger (CCP) .......................... 144, 200
Timing Diagram ....................................................... 293
Absolute Maximum Ratings ............................................. 265
Access Bank ...................................................................... 58
ADCON0 Register ........................................................... 193
GO/DONE Bit .......................................................... 195
Registers
ADCON2 (A/D Control 2) ................................. 195
ADCON1 Register .................................................. 193, 194
ADCON2 Register ........................................................... 193
ADDLW ............................................................................ 221
ADDWF ............................................................................ 221
ADDWFC ......................................................................... 222
ADRES Register ..................................................... 193, 195
AKS .................................................................................. 167
Analog-to-Digital Converter. See A/D
ANDLW ............................................................................ 222
ANDWF ............................................................................ 223
Assembler
Asynchronous Receive ................................... 185
Asynchronous Transmit .................................. 183
Watchdog Timer ...................................................... 211
BN ................................................................................... 224
BNC ................................................................................. 225
BNN ................................................................................. 225
BNOV .............................................................................. 226
BNZ ................................................................................. 226
BOV ................................................................................. 229
BRA ................................................................................. 227
BRG ................................................................................. 164
BSF ................................................................................. 227
BSR. See Bank Select Register.
MPASM Assembler ................................................. 259
B
Bank Select Register ......................................................... 58
Baud Rate Generator ....................................................... 164
Associated Registers ............................................... 179
BC .................................................................................... 223
BCF .................................................................................. 224
BF .................................................................................... 167
Block Diagram ................................................................. 119
Block Diagrams
BTFSC ............................................................................. 228
BTFSS ............................................................................. 228
BTG ................................................................................. 229
Bus .................................................................................. 176
Bus Collision During a RESTART Condition ................... 175
Bus Collision During a START Condition ........................ 173
Bus Collision During a STOP Condition .......................... 176
BZ .................................................................................... 230
A/D ........................................................................... 196
Baud Rate Generator .............................................. 164
Capture Mode Operation ......................................... 143
Compare Mode Operation ....................................... 144
Interrupt Logic ............................................................ 90
Low Voltage Detect ................................................. 203
MSSP
2
I C Mode ......................................................... 159
SPI Mode ......................................................... 153
On-Chip Reset Circuit, Simplified .............................. 29
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 307
PIC18C601/801
C
D
CALL ................................................................................230
Capture (CCP Module) ....................................................142
Block Diagram .........................................................143
CCP Pin Configuration .............................................142
CCPR1H:CCPR1L Registers ...................................142
Changing Between Capture Prescalers ...................143
Software Interrupt ....................................................143
Timer1 Mode Selection ............................................142
Capture/Compare/PWM (CCP) .......................................141
Capture Mode. See Capture
Data Memory ..................................................................... 49
General Purpose Registers ....................................... 49
Special Function Registers ........................................ 49
Data Memory Map
Program Bit Not Set .................................................. 51
Program Bit Set ......................................................... 52
DAW ................................................................................ 234
DC and AC Characteristics Graphs and Tables .............. 295
DCFSNZ .......................................................................... 235
DECF ............................................................................... 234
DECFSZ .......................................................................... 235
Development Support ...................................................... 259
Development Tool Version Requirements ....................... 305
Device Differences .......................................................... 303
Device Migrations ............................................................ 304
Direct Addressing .............................................................. 60
CCP1 .......................................................................142
CCPR1H Register ...........................................142
CCPR1L Register ............................................142
CCP2 .......................................................................142
CCPR2H Register ...........................................142
CCPR2L Register ............................................142
Compare Mode. See Compare
Interaction of Two CCP Modules .............................142
PWM Mode. See PWM
Registers Associated with Capture
E
Electrical Characteristics ................................................. 265
Errata ................................................................................... 7
External Wait Cycles ......................................................... 72
and Compare ...........................................145
Timer Resources .....................................................142
Timing Diagram .......................................................282
Chip Select
Chip Select 2 (CS2) ...................................................71
Chip Select I/O (CSIO) ......................................................71
Chip Selects
F
Fast Register Stack ........................................................... 45
Firmware Instructions ...................................................... 215
G
General Call Address Sequence ..................................... 162
General Call Address Support ......................................... 162
GOTO .............................................................................. 236
Chip Select 1 (CS1) ...................................................71
Clocking Scheme ...............................................................46
CLRF ...............................................................................231
CLRWDT .........................................................................231
Code Examples ...............................................................154
Changing Between Capture Prescalers ...................143
Clearing RAM Using Indirect Addressing ..................59
Combination Unlock (Macro) .....................................51
Combination Unlock (Subroutine) ..............................50
Fast Register Stack ...................................................45
Initializing PORTA ....................................................103
Initializing PORTB ....................................................105
Initializing PORTC ...................................................108
Initializing PORTD ...................................................110
Initializing PORTE ....................................................113
Initializing PORTF ....................................................116
Initializing PORTG ...................................................119
Initializing PORTH ...................................................121
Initializing PORTJ ....................................................124
Programming Chip Select Signals ...........................116
Saving STATUS, WREG and BSR Registers ..........101
Table Read ................................................................75
Table Write ................................................................77
COMF ..............................................................................232
Compare (CCP Module) ..................................................144
Block Diagram .........................................................144
CCP Pin Configuration .............................................144
CCPR1H:CCPR1L Registers ...................................144
Software Interrupt ....................................................144
Special Event Trigger ....................133, 139, 144, 200
Timer1 Mode Selection ............................................144
Configuration Address Map, Example ...............................71
Configuration Bits ............................................................207
Table ........................................................................207
Context Saving During Interrupts .....................................101
CPFSEQ ..........................................................................232
CPFSGT ..........................................................................233
CPFSLT ...........................................................................233
I
I/O Mode .......................................................................... 119
I/O Ports .......................................................................... 103
2
I C (SSP Module) ............................................................ 159
ACK Pulse .......................................................159, 160
Addressing .............................................................. 160
Block Diagram ......................................................... 159
Read/Write Bit Information (R/W Bit) ....................... 160
Reception ................................................................ 160
Serial Clock (RC3/SCK/SCL) .................................. 160
Slave Mode ............................................................. 159
Timing Diagram, Data ............................................. 287
Timing Diagram, START/STOP Bits ....................... 287
Transmission ........................................................... 160
2
I C Master Mode Reception ............................................ 167
2
I C Master Mode RESTART Condition ........................... 166
2
I C Module
Acknowledge Sequence Timing .............................. 170
Baud Rate Generator .............................................. 164
Block Diagram ................................................. 164
BRG Reset due to SDA Collision ............................ 174
BRG Timing ............................................................. 165
Bus Collision
Acknowledge ................................................... 172
RESTART Condition ....................................... 175
RESTART Condition Timing (Case1) .............. 175
RESTART Condition Timing (Case2) .............. 175
START Condition ............................................ 173
START Condition Timing ........................173, 174
STOP Condition .............................................. 176
STOP Condition Timing (Case1) ..................... 176
STOP Condition Timing (Case2) ..................... 176
Transmit Timing .............................................. 172
Bus Collision Timing ................................................ 172
DS39541A-page 308
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Clock Arbitration ...................................................... 171
Clock Arbitration Timing (Master Transmit) ............. 171
General Call Address Support ................................. 162
Master Mode 7-bit Reception Timing ....................... 169
Master Mode Operation ........................................... 164
Master Mode START Condition ............................... 165
Master Mode Transmission ..................................... 167
Master Mode Transmit Sequence ........................... 164
Multi-Master Mode ................................................... 172
Repeated START Condition Timing ........................ 166
STOP Condition Receive or Transmit Timing .......... 170
STOP Condition Timing ........................................... 170
Waveforms for 7-bit Reception ................................ 161
Waveforms for 7-bit Transmission ........................... 161
ICEPIC In-Circuit Emulator .............................................. 260
INCF ................................................................................ 236
INCFSZ ............................................................................ 237
In-Circuit Serial Programming (ICSP) .............................. 207
Indirect Addressing ............................................................ 60
FSR Register ............................................................. 59
INFSNZ ............................................................................ 237
Initialization Conditions for All Registers ............................ 34
Instruction Cycle ................................................................ 46
Instruction Flow/Pipelining ................................................. 47
Instruction Format ............................................................ 217
Instruction Set .................................................................. 215
ADDLW .................................................................... 221
ADDWF ................................................................... 221
ADDWFC ................................................................. 222
ANDLW .................................................................... 222
ANDWF ................................................................... 223
BC ............................................................................ 223
BCF ......................................................................... 224
BN ............................................................................ 224
BNC ......................................................................... 225
BNN ......................................................................... 225
BNOV ...................................................................... 226
BNZ ......................................................................... 226
BOV ......................................................................... 229
BRA ......................................................................... 227
BSF .......................................................................... 227
BTFSC ..................................................................... 228
BTFSS ..................................................................... 228
BTG ......................................................................... 229
BZ ............................................................................ 230
CALL ........................................................................ 230
CLRF ....................................................................... 231
CLRWDT ................................................................. 231
COMF ...................................................................... 232
CPFSEQ .................................................................. 232
CPFSGT .................................................................. 233
CPFSLT ................................................................... 233
DAW ........................................................................ 234
DCFSNZ .................................................................. 235
DECF ....................................................................... 234
DECFSZ .................................................................. 235
GOTO ...................................................................... 236
INCF ........................................................................ 236
INCFSZ .................................................................... 237
INFSNZ .................................................................... 237
IORLW ..................................................................... 238
IORWF ..................................................................... 238
LFSR ....................................................................... 239
MOVF ...................................................................... 239
MOVFF .................................................................... 240
MOVLB .................................................................... 240
MOVLW ................................................................... 241
MOVWF .................................................................. 241
MULLW ................................................................... 242
MULWF ................................................................... 242
NEGF ...................................................................... 243
NOP ........................................................................ 243
POP ......................................................................... 244
PUSH ...................................................................... 244
RCALL ..................................................................... 245
RESET .................................................................... 245
RETFIE ................................................................... 246
RETLW .................................................................... 246
RETURN ................................................................. 247
RLCF ....................................................................... 247
RLNCF .................................................................... 248
RRCF ...................................................................... 248
RRNCF .................................................................... 249
SETF ....................................................................... 249
SLEEP ..................................................................... 250
SUBFWB .........................................................250, 251
SUBLW ................................................................... 251
SUBWF ................................................................... 252
SUBWFB ................................................................. 253
SWAPF ................................................................... 254
TBLRD .................................................................... 255
TBLWT .................................................................... 256
TSTFSZ ................................................................... 257
XORLW ................................................................... 257
XORWF ................................................................... 258
Instruction Set, Summary ................................................ 218
INT Interrupt (RB0/INT). See Interrupt Sources
INTCON Register
RBIF Bit ................................................................... 105
2
Inter-Integrated Circuit. See I C
Interrupt Control Registers ................................................ 91
INTCON Register ...................................................... 91
INTCON2 Register .................................................... 92
INTCON3 Register .................................................... 93
IPR Registers ............................................................ 99
PIE Registers ............................................................ 97
PIR Registers ............................................................ 95
RCON Register ......................................................... 94
Interrupt Sources .......................................................89, 207
A/D Conversion Complete ....................................... 197
Capture Complete (CCP) ........................................ 143
Compare Complete (CCP) ...................................... 144
Interrupt-on-Change (RB7:RB4) ............................. 105
RB0/INT Pin, External ............................................. 101
SSP Receive/Transmit Complete ............................ 149
TMR0 Overflow ....................................................... 129
TMR1 Overflow ...............................................130, 133
TMR2 to PR2 Match ................................................ 136
TMR2 to PR2 Match (PWM) ...........................135, 146
TMR3 Overflow ...............................................137, 139
USART Receive/Transmit Complete ....................... 177
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ..................................... 143
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) ................................. 195
CCP1 Flag (CCP1IF Bit) ........................ 142, 143, 144
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ................................................ 105
IORLW ............................................................................. 238
IORWF ............................................................................ 238
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 309
PIC18C601/801
K
P
KEELOQ Evaluation and Programming Tools ...................262
Packaging ........................................................................ 297
Phase Lock Loop
Block Diagram ........................................................... 23
Time-out .................................................................... 30
PICDEM 1 Low Cost PICmicro
Demonstration Board .............................................. 261
PICDEM 17 Demonstration Board .................................. 262
PICDEM 2 Low Cost PIC16CXX
Demonstration Board .............................................. 261
PICDEM 3 Low Cost PIC16CXXX
L
LFSR ................................................................................239
Loading the SSPBUF (SSPSR) Registers .......................154
Low Voltage Detect ..........................................................203
Block Diagram .........................................................203
LVDCON Register ...................................................204
LVD. See Low Voltage Detect.
M
Demonstration Board .............................................. 262
PICSTART Plus Entry Level
MEMCOM. See Memory Control Register
Memory ..............................................................................39
Memory Control Register (MEMCOM) ...............................63
Memory Organization ........................................................39
Data Memory .............................................................49
Program Memory .......................................................39
Migrating from other PICmicro Devices ...........................304
MOVF ..............................................................................239
MOVFF ............................................................................240
MOVLB ............................................................................240
MOVLW ...........................................................................241
MOVWF ...........................................................................241
MPLAB C17 and MPLAB C18 C Compilers ....................259
MPLAB ICD In-Circuit Debugger .....................................261
MPLAB ICE High Performance Universal
Development Programmer ...................................... 261
Pin Functions
AVDD .......................................................................... 20
AVSS .......................................................................... 20
MCLR/VPP ................................................................. 12
OSC1/CLKI ................................................................ 12
OSC2/CLKO .............................................................. 12
RA0/AN0 ................................................................... 13
RA1/AN1 ................................................................... 13
RA2/AN2/VREF- ......................................................... 13
RA3/AN3/VREF+ ........................................................ 13
RA4/T0CKI ................................................................ 13
RA5/AN4/SS/LVDIN .................................................. 13
RB0/INT0 ................................................................... 14
RB1/INT1 ................................................................... 14
RB2/INT2 ................................................................... 14
RB3/INT3 ................................................................... 14
RB4 ........................................................................... 14
RB5 ........................................................................... 14
RB6 ........................................................................... 14
RB7 ........................................................................... 14
RC0/T1OSO/T1CKI ................................................... 15
RC1/T1OSI ................................................................ 15
RC2/CCP1 ................................................................. 15
RC3/SCK/SCL ........................................................... 15
RC4/SDI/SDA ............................................................ 15
RC5/SDO .................................................................. 15
RC6/TX/CK ................................................................ 15
RC7/RX/DT ............................................................... 15
RD0/AD0 ................................................................... 16
RD0/PSP0 ................................................................. 16
RD1/AD1 ................................................................... 16
RD2/AD2 ................................................................... 16
RD3/AD3 ................................................................... 16
RD4/AD4 ................................................................... 16
RD5/AD5 ................................................................... 16
RD6/AD6 ................................................................... 16
RD7/AD7 ................................................................... 16
RE0/ALE .................................................................... 17
RE1/OE ..................................................................... 17
RE2/CS ........................................................17, 18, 19
RE2/WRL .................................................................. 17
RE3/WRH .................................................................. 17
RE4 ........................................................................... 17
RE5 ........................................................................... 17
RE6 ........................................................................... 17
RE7/CCP2 ................................................................. 17
RF0/AN5 .................................................................... 18
RF1/AN6 .................................................................... 18
RF2/AN7 .................................................................... 18
RF3/AN8 .................................................................... 18
RF4/AN9 .................................................................... 18
In-Circuit Emulator with MPLAB IDE .......................260
MPLAB Integrated Development
Environment Software .............................................259
MPLINK Object Linker/MPLIB Object Librarian ...............260
MULLW ............................................................................242
Multi-Master Mode ...........................................................172
Multiplication Algorithm
16 x 16 Signed ...........................................................86
16 x 16 Unsigned .......................................................86
Multiply Examples
16 x 16 Signed Routine .............................................87
16 x 16 Unsigned Routine .........................................86
8 x 8 Signed Routine .................................................86
8 x 8 Unsigned Routine .............................................86
MULWF ............................................................................242
N
NEGF ...............................................................................243
NOP .................................................................................243
O
On-Chip Reset Circuit ........................................................29
OPTION_REG Register .....................................................62
PS2:PS0 Bits ...........................................................129
PSA Bit ....................................................................129
T0CS Bit ..................................................................129
T0SE Bit ...................................................................129
OSCCON Register .............................................................25
Oscillator Configuration ...................................................207
Oscillator Configurations ....................................................21
HS ..............................................................................21
LP ..............................................................................21
RC ....................................................................... 21, 22
Oscillator, Timer1 ............................................130, 133, 137
Oscillator, Timer3 .............................................................139
Oscillator, WDT ................................................................210
DS39541A-page 310
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
RF5/AN10 .................................................................. 18
RF6/AN11 .................................................................. 18
RF7 ............................................................................ 18
RG0/CANTX1 ............................................................ 19
RG1/CANTX2 ............................................................ 19
RG2/CANRX .............................................................. 19
RG3 ........................................................................... 19
RG4 ........................................................................... 19
RH1/A17 .................................................................... 19
RH2/A18 .................................................................... 19
RH3/A19 .................................................................... 19
RH4/AN12 ................................................................. 19
RH5/AN13 ................................................................. 19
RH6/AN14 ................................................................. 19
RH7/AN15 ................................................................. 19
RJ0/AD8 .................................................................... 20
RJ1/AD9 .................................................................... 20
RJ2/AD10 .................................................................. 20
RJ3/AD11 .................................................................. 20
RJ4/AD12 .................................................................. 20
RJ5/AD13 .................................................................. 20
RJ6/AD14 .................................................................. 20
RJ7/AD15 .................................................................. 20
VDD ............................................................................ 20
VSS ............................................................................ 20
POP ................................................................................. 244
POR. See Power-on Reset
PORTE
Associated Registers .............................................. 115
Block Diagram
I/O Mode ......................................................... 113
System Bus Mode ........................................... 114
Functions ................................................................. 115
Initialization ............................................................. 113
PORTE Register ..................................................... 113
TRISE Register ....................................................... 113
PORTF
Associated Registers .............................................. 118
Block Diagram
RF2:RF0 Pins .................................................. 116
RF5:RF3 Pins .................................................. 117
RF7:RF6 Pins .................................................. 117
Functions ................................................................. 118
Initialization ............................................................. 116
PORTF Register ...................................................... 116
TRISF ...................................................................... 116
PORTG ............................................................................ 119
Associated Registers .............................................. 120
Block Diagram
System Bus Mode ........................................... 120
Functions ................................................................. 120
Initialization ............................................................. 119
PORTG Register ..................................................... 119
TRISG ..................................................................... 119
PORTH
PORTA
Associated Registers ............................................... 104
Block Diagram
Associated Registers .............................................. 123
Block Diagram .................................................121, 122
Functions ................................................................. 123
Initialization ............................................................. 121
PORTH Register ..................................................... 121
TRISH ..................................................................... 121
PORTJ
RA3:RA0 and RA5 Pins ................................... 103
RA4/T0CKI Pin ................................................ 104
Functions ................................................................. 104
Initialization .............................................................. 103
PORTA Register ...................................................... 103
TRISA Register ........................................................ 103
PORTB
Associated Registers .............................................. 126
Block Diagram
Associated Registers ............................................... 107
Block Diagram
I/O Mode ......................................................... 124
System Bus Mode ........................................... 125
Functions ................................................................. 126
Initialization ............................................................. 124
PORTJ Register ...................................................... 124
TRISJ ...................................................................... 124
Postscaler, WDT
Assignment (PSA Bit) .............................................. 129
Rate Select (PS2:PS0 Bits) ..................................... 129
Switching Between Timer0 and WDT ..................... 129
Power-down Mode. See SLEEP
Power-on Reset (POR) .............................................30, 207
Oscillator Start-up Timer (OST) ........................30, 207
Power-up Timer (PWRT) ...................................30, 207
Time-out Sequence ................................................... 30
Time-out Sequence on Power-up .......................32, 33
Timing Diagram ....................................................... 280
Prescaler, Capture .......................................................... 143
Prescaler, Timer0 ............................................................ 129
Assignment (PSA Bit) .............................................. 129
Rate Select (PS2:PS0 Bits) ..................................... 129
Switching Between Timer0 and WDT ..................... 129
Prescaler, Timer1 ............................................................ 131
Prescaler, Timer2 ............................................................ 146
PRO MATE II Universal Device Programmer .................. 261
Product Identification System .......................................... 317
RB3 Pin ........................................................... 106
RB3:RB0 Port Pins .......................................... 106
RB7:RB4 Port Pins .......................................... 105
Functions ................................................................. 107
Initialization .............................................................. 105
PORTB Register ...................................................... 105
RB0/INT Pin, External ............................................. 101
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ....... 105
TRISB Register ........................................................ 105
PORTC
Associated Registers ............................................... 109
Block Diagram ......................................................... 108
Functions ................................................................. 109
Initialization .............................................................. 108
PORTC Register ...................................................... 108
RC3/SCK/SCL Pin ................................................... 160
RC7/RX/DT Pin ....................................................... 179
TRISC Register .............................................. 108, 177
PORTD
Associated Registers ............................................... 112
Block Diagram
I/O Mode .......................................................... 110
System Bus Mode ........................................... 111
Functions ................................................................. 112
Initialization .............................................................. 110
PORTD Register ...................................................... 110
TRISD Register ....................................................... 110
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 311
PIC18C601/801
Program Counter
RCSTA (Receive Status and Control) ..................... 178
SSPCON1 (SSP Control 1) ..................................... 151
SSPCON2 (SSP Control 2) ...................................... 152
SSPSTAT (SSP Status) .......................................... 150
STATUS .................................................................... 61
STKPTR (Stack Pointer) ........................................... 44
T0CON (Timer0 Control) ......................................... 127
T1CON (Timer1 Control) ......................................... 130
T2CON (Timer2 Control) ......................................... 135
T3CON (Timer3 Control) ......................................... 137
TXSTA (Transmit Status and Control) ..................... 177
WDTCON (Watchdog Timer Control) ...................... 210
RESET .............................................................29, 207, 245
Timing Diagram ....................................................... 280
RETFIE ............................................................................ 246
RETLW ............................................................................ 246
RETURN ......................................................................... 247
Revision History .............................................................. 303
RH3:RH0 Pins (I/O Mode) ............................................... 121
RH3:RH0 Pins (System Bus Mode) ................................ 122
RH7:RH4 Pins ................................................................. 121
RLCF ............................................................................... 247
RLNCF ............................................................................ 248
RRCF .............................................................................. 248
RRNCF ............................................................................ 249
PCL Register .............................................................46
PCLATH Register ......................................................46
Program Memory ...............................................................39
Boot Loader ...............................................................43
Memory Map, PIC18C601
Program Bit Not Set ...........................................40
Program Bit Set .................................................41
Memory Map, PIC18C801
Program Bit Not Set ...........................................40
Program Bit Set .................................................42
Program Memory Map
PIC18C601 ................................................................40
Program Bit Set .................................................41
PIC18C801 ................................................................40
Program Bit Set .................................................42
Programming, Device Instructions ...................................215
PUSH ...............................................................................244
PWM (CCP Module) ........................................................146
Block Diagram .........................................................146
CCPR1H:CCPR1L Registers ...................................146
Duty Cycle ...............................................................146
Example Frequencies/Resolutions ..........................147
Output Diagram .......................................................146
Period ......................................................................146
Registers Associated with PWM ..............................147
Setup for PWM Operation ........................................147
TMR2 to PR2 Match ....................................... 135, 146
S
Sales and Support ........................................................... 317
SCI. See USART
Q
SCK ................................................................................. 153
SDI .................................................................................. 153
SDO ................................................................................. 153
Serial Clock, SCK ............................................................ 153
Serial Communication Interface. See USART
Q Clock ............................................................................146
R
RAM. See Data Memory
RCALL .............................................................................245
RCSTA Register
Serial Data In, SDI ........................................................... 153
Serial Data Out, SDO ...................................................... 153
Serial Peripheral Interface. See SPI
SETF ............................................................................... 249
Slave Select Synchronization .......................................... 156
Slave Select, SS .............................................................. 153
SLEEP ............................................................207, 212, 250
Software Simulator (MPLAB SIM) ................................... 260
Special Event Trigger. See Compare
Special Features of the CPU ........................................... 207
Special Function Register Map ......................................... 53
Special Function Registers ................................................ 49
SPI
Associated Registers ............................................... 158
Master Mode ........................................................... 155
Serial Clock ............................................................. 153
Serial Data In ........................................................... 153
Serial Data Out ........................................................ 153
Slave Select ............................................................ 153
SPI Clock ................................................................. 155
SPI Mode ................................................................. 153
SPI Module
SPEN Bit ..................................................................177
Reader Response ............................................................316
Register File .......................................................................49
Register File Summary ......................................................54
Registers
ADCON0 (A/D Control 0)..........................................193
ADCON1 (A/D Control 1) .........................................194
CCP1CON and CCP2CON (CCP Control) ..............141
CONFIG1H (Configuration Register 1 High) ............208
CONFIG2H (Configuration Register 2 High) ............209
CONFIG2L (Configuration Register 2 Low) .............208
CONFIG4L (Configuration Register 4 Low) .............209
CSEL2 (Chip Select 2) ...............................................70
CSELIO (Chip Select I/O) ..........................................70
INTCON (Interrupt Control) ........................................91
INTCON2 (Interrupt Control 2) ...................................92
INTCON3 (Interrupt Control 3) ...................................93
IPR (Interrupt Priority) ................................................99
LVDCON (LVD Control) ...........................................204
MEMCON (Memory Control) .....................................63
OSCCON (Oscillator Control) ....................................25
PIE (Peripheral Interrupt Enable) ...............................97
PIR (Peripheral Interrupt Request) ............................95
PSPCON (PSP Control) ............................................50
RCON (Register Control) ...........................................94
RCON (RESET Control) ..................................... 31, 62
Slave Mode ............................................................. 156
Slave Select Synchronization .................................. 156
Slave Synch Timing ................................................. 156
Slave Timing with CKE = 0 ...................................... 157
Slave Timing with CKE = 1 ...................................... 157
SS .................................................................................... 153
DS39541A-page 312
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
SSP .................................................................................. 149
Block Diagram
Prescaler. See Prescaler, Timer1
Special Event Trigger (CCP) ...........................133, 144
T1CON Register ...................................................... 130
Timing Diagram ....................................................... 281
TMR1H Register ..................................................... 130
TMR1L Register ...................................................... 130
TMR3L Register ...................................................... 137
SPI Mode ......................................................... 153
Block Diagram (SPI Mode) ...................................... 153
2
2
I C Mode. See I C
SPI Mode ................................................................. 153
SPI Mode. See SPI
SSPBUF .................................................................. 155
SSPCON1 ............................................................... 151
SSPCON2 ............................................................... 152
SSPSR .................................................................... 155
SSPSTAT ................................................................ 150
TMR2 Output for Clock Shift ........................... 135, 136
Timer2
Associated Registers .............................................. 136
Block Diagram ......................................................... 136
Postscaler. See Postscaler, Timer2
PR2 Register ...................................................135, 146
Prescaler. See Prescaler, Timer2
SSP Module
SSP Clock Shift ...............................................135, 136
T2CON Register ...................................................... 135
TMR2 Register ........................................................ 135
TMR2 to PR2 Match Interrupt ................ 135, 136, 146
Timer3 ............................................................................. 137
Associated Registers .............................................. 139
Block Diagram ......................................................... 138
16-bit R/W Mode ............................................. 138
Oscillator .........................................................137, 139
Overflow Interrupt ............................................137, 139
Special Event Trigger (CCP) ................................... 139
T3CON Register ...................................................... 137
TMR3H Register ..................................................... 137
Timing Diagrams
SPI Master Mode ..................................................... 155
SPI Slave Mode ....................................................... 156
SSPCON1 Register ......................................................... 151
SSPCON2 Register ......................................................... 152
SSPOV ............................................................................ 167
SSPSTAT Register .......................................................... 150
R/W Bit .................................................................... 160
SUBFWB ................................................................ 250, 251
SUBLW ............................................................................ 251
SUBWF ............................................................................ 252
SUBWFB ......................................................................... 253
SWAPF ............................................................................ 254
Synchronous Serial Port. See SSP
Acknowledge Sequence Timing .............................. 170
Baud Rate Generator with Clock Arbitration ........... 165
BRG Reset Due to SDA Collision ........................... 174
Bus Collision
START Condition Timing ................................ 173
Bus Collision During a RESTART Condition
(Case 1) .................................................. 175
Bus Collision During a RESTART Condition
(Case 2) .................................................. 175
Bus Collision During a START Condition
T
Table Pointer Register ....................................................... 74
Table Read ........................................................................ 75
Table Read/Write Control Registers .................................. 74
Table Write ........................................................................ 77
16-bit External
16-bit Word Write Mode ..................................... 81
Byte Select Mode .............................................. 82
Byte Write Mode ................................................ 80
8-bit External ............................................................. 78
Table Writes
Long Writes ............................................................... 83
TBLRD ............................................................................. 255
TBLWT ............................................................................. 256
Timer0 .............................................................................. 127
Associated Registers ............................................... 129
Block Diagram
(SCL = 0) ................................................. 174
Bus Collision During a STOP Condition .................. 176
Bus Collision for Transmit and Acknowledge .......... 172
2
I C Bus Data ........................................................... 289
2
I C Master Mode First START Bit Timing ............... 165
2
I C Master Mode Reception Timing ........................ 169
2
I C Master Mode Transmission Timing ................... 168
Master Mode Transmit Clock Arbitration ................. 171
Repeated START Condition .................................... 166
Slave Synchronization ............................................. 156
Slow Rise Time ......................................................... 33
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram ......................... 155
SPI Mode Timing (Slave Mode with CKE = 0) ........ 157
SPI Mode Timing (Slave Mode with CKE = 1) ........ 157
STOP Condition Receive or Transmit ..................... 170
Time-out Sequence on Power-up ............................. 32
USART Asynchronous Master Transmission .......... 184
USART Asynchronous Reception ........................... 186
USART Synchronous Reception ............................. 189
USART Synchronous Transmission ........................ 188
Wake-up from SLEEP via Interrupt ......................... 213
16-bit Mode ...................................................... 128
8-bit Mode ........................................................ 128
Clock Source Edge Select (T0SE Bit) ..................... 129
Clock Source Select (T0CS Bit) .............................. 129
Interrupt ................................................................... 101
Overflow Interrupt .................................................... 129
Prescaler. See Prescaler, Timer0
T0CON Register ...................................................... 127
Timing Diagram ....................................................... 281
Timer1 .............................................................................. 130
Associated Registers ............................................... 134
Block Diagram ......................................................... 131
16-bit R/W Mode .............................................. 132
Oscillator ......................................................... 130, 133
Overflow Interrupt ........................................... 130, 133
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 313
PIC18C601/801
Timing Diagrams and Specifications ...............................275
A/D Conversion ........................................................293
Capture/Compare/PWM (CCP) ...............................282
CLKOUT and I/O .....................................................276
External Clock ..........................................................275
W
Wake-up from SLEEP .............................................207, 212
Timing Diagram ....................................................... 213
Watchdog Timer (WDT) ..........................................207, 210
Associated Registers ............................................... 211
Block Diagram ......................................................... 211
Postscaler. See Postscaler, WDT
Programming Considerations .................................. 210
RC Oscillator ........................................................... 210
Time-out Period ....................................................... 210
Timing Diagram ....................................................... 280
WDTCON Register .................................................. 210
Waveform for General Call Address Sequence .............. 162
WCOL .............................................................165, 167, 170
WCOL Status Flag .......................................................... 165
Worldwide Sales and Service .......................................... 318
WWW, On-Line Support ..............................................7, 315
2
I C Bus Data ............................................................287
2
I C Bus START/STOP Bits ......................................287
Oscillator Start-up Timer (OST) ...............................280
Power-up Timer (PWRT) .........................................280
RESET .....................................................................280
Timer0 and Timer1 ..................................................281
USART Synchronous Receive
(Master/Slave) .........................................291
USART Synchronous Transmission
(Master/Slave) .........................................291
Watchdog Timer (WDT) ...........................................280
TRISE Register ................................................................113
TSTFSZ ...........................................................................257
Two-Word Instructions .......................................................48
TXSTA Register ...............................................................177
BRGH Bit .................................................................179
X
XORLW ........................................................................... 257
XORWF ........................................................................... 258
U
Universal Synchronous Asynchronous
Receiver Transmitter. See USART
USART .............................................................................177
Asynchronous Mode ................................................183
Master Transmission .......................................184
Receive Block Diagram ...................................185
Reception ........................................................186
Registers Associated with Reception ..............186
Registers Associated with Transmission .........184
Transmit Block Diagram ..................................183
Baud Rate Generator (BRG) ...................................179
Baud Rate Error, Calculating ...........................179
Baud Rate Formula .........................................179
High Baud Rate Select (BRGH Bit) .................179
Sampling ..........................................................179
Serial Port Enable (SPEN Bit) .................................177
Synchronous Master Mode ......................................187
Reception ........................................................189
Registers Associated with Reception ..............189
Registers Associated with Transmission .........187
Timing Diagram,
Synchronous Receive .....................291
Timing Diagram,
Synchronous Transmission .............291
Transmission ...................................................188
Synchronous Slave Mode ........................................190
Registers Associated with Reception ..............191
Registers Associated with Transmission .........190
DS39541A-page 314
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
001024
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL,
MPLAB and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
Total Endurance, ICSP, In-Circuit Serial Programming,
FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM,
MPLINK, MPLIB, PICDEM, ICEPIC and Migratable
Memory are trademarks and SQTP is a service mark of
Microchip in the U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
All other trademarks mentioned herein are the property of
their respective companies.
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 315
PIC18C601/801
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Literature Number:
DS39541A
Device:
PIC18C601/801
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS39541A-page 316
Advance Information
2001 Microchip Technology Inc.
PIC18C601/801
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
XXX
a)
PIC18LC601 - I/L = Industrial temp., PLCC
Temperature Package
Range
Pattern
package, Extended VDD limits, 16-bit data bus.
PIC18LC801 - E/PT = Extended temp., TQFP
package, Extended VDD limits, 16-bit data bus.
b)
Device
PIC18C601/801(1), PIC18C601/801T(2)
:
VDD range, 4.2V to 5.5V
PIC18LC601/801(1), PIC18LC601/801T(2)
VDD range, 2.5V to 5.5V
Temperature Range
Package
I
E
=
=
-40°C to +70°C (Industrial)
-40°C to +125°C (Extended)
PT
L
=
=
TQFP
PLCC
Note 1: C = Standard Voltage Range
LC = Wide Voltage Range
2: T =
In tape and reel (both PLCC and
TQFP packages)
Pattern
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices.
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 317
PIC18C601/801
NOTES:
DS39541A-page 318
AdvanceInformation
2001 Microchip Technology Inc.
PIC18C601/801
NOTES:
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 319
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC (continued)
Corporate Office
China - Beijing
Microchip Technology Beijing Office
Unit 915
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
New China Hong Kong Manhattan Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Rocky Mountain
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
China - Shanghai
Microchip Technology Shanghai Office
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
500 Sugar Mill Road, Suite 200B
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Tel: 770-640-0034 Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
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Tel: 978-692-3848 Fax: 978-692-3821
EUROPE
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
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Tel: 45 4420 9895 Fax: 45 4420 9910
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Hong Kong
Microchip Asia Pacific
RM 2101, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
France
India
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Microchip Technology Inc.
India Liaison Office
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Divyasree Chambers
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
4570 Westgrove Drive, Suite 160
Addison, TX 75001
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
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Dayton
Two Prestige Place, Suite 130
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Tel: 949-263-1888 Fax: 949-263-1338
Tel: 82-2-554-7200 Fax: 82-2-558-5934
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
10/01/00
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 1/01
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS39541A-page 320
Advance Information
2001 Microchip Technology Inc.
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