PIC18F13K22T-I/SS_技术文档

PIC18(L)F1XK22

20-Pin Flash Microcontrollers with XLP Technology

High-Performance RISC CPU

Analog Features

• Analog-to-Digital Converter (ADC) module

- 10-bit resolution, 12 channels

- Auto-acquisition capability

• C Compiler Optimized Architecture:

- Optional extended instruction set designed to

optimize re-entrant code

- Conversion available during Sleep

• Analog Comparator module:

- Two rail-to-rail analog comparators

- Independent input multiplexing

- Inputs and outputs externally accessible

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive Digital-to-Analog

Converter (DAC) with positive and negative

reference selection

• 256 bytes Data EEPROM

• Up to 16 Kbytes Linear Program Memory

Addressing

• Up to 512 bytes Linear Data Memory Addressing

• Up to 16 MIPS Operation

• 16-bit Wide Instructions, 8-bit Wide Data Path

• Priority Levels for Interrupts

• 31-Level, Software Accessible Hardware Stack

• 8 x 8 Single-Cycle Hardware Multiplier

Flexible Oscillator Structure

• Precision 16 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%

- Software selectable frequencies range of

31 kHz to 16 MHz

- 64 MHz performance available using PLL –

no external components required

• Four Crystal modes up to 64 MHz

• Two External Clock modes up to 64 MHz

• 4X Phase Lock Loop (PLL)

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor

- Allows for safe shutdown if peripheral clock

stops

Peripheral Highlights

• 17 I/O Pins and 1 Input-only Pin:

- High current sink/source 25 mA/25 mA

- Programmable weak pull-ups

- Programmable interrupt-on- change

- Three external interrupt pins

• Four Timer modules:

- Three 16-bit timers/counters with prescaler

- One 8-bit timer/counter with 8-bit period

register, prescaler and postscaler

- Dedicated, low-power Timer1 oscillator

• Enhanced Capture/Compare/PWM (ECCP)

module:

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and Auto-restart

- PWM output steering control

• Master Synchronous Serial Port (MSSP) module

- 3-wire SPI (supports all four SPI modes)

- I²C Master and Slave modes (Slave mode

address masking)

• Enhanced Universal Synchronous Asynchronous

Receiver Transmitter module (EUSART)

- Supports RS-232, RS-485 and LIN 2.0

- Auto-Baud Detect

• Two-Speed Oscillator Start-up

Special Microcontroller Features

• 2.3V - 5.5V Operation – PIC18F1XK22

• 1.8V-3.6V Operation – PIC18LF1XK22

• Self-reprogrammable under Software Control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Programmable Brown-out Reset (BOR)

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via

two pins

• In-Circuit Debug via Two Pins

- Auto Wake-up on Break

• SR Latch (555 Timer) module with:

- Configurable inputs and outputs

- Supports mTouch^®capacitive sensing

applications

Extreme Low-Power Management

PIC18LF1XK22 with XLP Technology

• Sleep mode: 34 nA

• Watchdog Timer: 460 nA

• Timer1 Oscillator: 650 nA @ 32 kHz

 2009-2016 Microchip Technology Inc.

DS40001365F-page 1

PIC18(L)F1XK22

PIC18(L)F1XK22 Family Types

Program Memory

Data Memory

Data

(1)

Device

Pins I/O

SRAM

Bytes

Words

EEPROM

(bytes)

PIC18(L)F13K22

PIC18(L)F14K22

(1)

8K

4K

8K

256

512

256

20

18

12-ch

2

1 / 3

1

Yes

16K

Note 1: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document)

1. DS40001365 PIC18(L)F1XK22 20-Pin Flash Microcontrollers with XLP Technology

Note:

For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

Pin Diagrams

FIGURE 1:

20-PIN PDIP, SSOP, SOIC

VDD

RA5

RA4

1

2

3

4

5

6

7

8

9

VSS

20

19 RA0/PGD

18 RA1/PGC

17 RA2

RA3/MCLR/VPP

RC5

RC0

15 RC1

14

13 RB4

16

RC4

RC3/PGM

RC6

RC2

RC7

RB7

RB5

RB6

12

11

10

Note: See Table 1 for location of all peripheral functions.

FIGURE 2:

20-PIN QFN (4x4)

20191817 16

RA3/MCLR/VPP

1

2

RA1/PGC

14 RA2

15

RC5

RC4 3

RC3/PGM

PIC18(L)F13K22

PIC18(L)F14K22

13

12

11

RC0

RC1

RC2

4

RC6 5

6 7 8 9 10

Note: See Table 1 for location of all peripheral functions.

DS40001365F-page 2

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 1:

20-PIN ALLOCATION TABLE (PIC18(L)F1XK22)

RA0

RA1

19

18

16

15

AN0

C1IN+

VREF-/

CVREF(DAC1OUT)

—

IOC/INT0

IOC/INT1

Y

PGD

AN1 C12IN0-

VREF+

PGC

—

RA2

RA3

17

4

14

1

AN2

—

C1OUT

—

SRQ

—

T0CKI

—

IOC/INT2

IOC

Y

MCLR/VPP

RA4

3

20

AN3

—

IOC

Y

OSC2/CLKOUT

RA5

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

—

2

13

12

11

10

16

15

14

7

19

10

9

—

AN10

AN11

—

T13CKI

—

IOC

—

Y

OSC1/CLKIN

—

SDI/SDA

—

RX/DT

—

SCL/SCK

—

Y

8

—

Y

—

7

—

TX/CK

—

Y

—

13

12

11

4

AN4

C2IN+

—

AN5 C12IN1-

AN6 C12IN2-

AN7 C12IN3-

—

P1D

P1C

P1B

CCP1/P1A

—

PGM

—

6

3

—

C2OUT

—

SRNQ

—

5

2

—

8

5

AN8

AN9

—

SS

—

9

6

—

SDO

—

1

18

17

—

VDD

VSS

—

20

—

 2009-2016 Microchip Technology Inc.

DS40001365F-page 3

PIC18(L)F1XK22

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 6

2.0 Oscillator Module........................................................................................................................................................................ 12

3.0 Memory Organization................................................................................................................................................................. 24

4.0 Flash Program Memory.............................................................................................................................................................. 45

5.0 Data EEPROM Memory ............................................................................................................................................................. 54

6.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 58

7.0 Interrupts .................................................................................................................................................................................... 60

8.0 I/O Ports ..................................................................................................................................................................................... 73

9.0 Timer0 Module ........................................................................................................................................................................... 91

10.0 Timer1 Module ........................................................................................................................................................................... 94

11.0 Timer2 Module ......................................................................................................................................................................... 100

12.0 Timer3 Module ......................................................................................................................................................................... 102

13.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 106

14.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 127

15.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 170

16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 197

17.0 Comparator Module.................................................................................................................................................................. 210

18.0 Power-Managed Modes ........................................................................................................................................................... 222

19.0 SR Latch................................................................................................................................................................................... 228

20.0 Fixed Voltage Reference (FVR)................................................................................................................................................ 231

21.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 233

22.0 Reset........................................................................................................................................................................................ 237

23.0 Special Features of the CPU.................................................................................................................................................... 249

24.0 Instruction Set Summary.......................................................................................................................................................... 265

25.0 Development Support............................................................................................................................................................... 315

26.0 Electrical Specifications............................................................................................................................................................ 319

27.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 356

28.0 Packaging Information.............................................................................................................................................................. 372

Appendix A: Revision History............................................................................................................................................................. 382

Appendix B: Device Differences......................................................................................................................................................... 383

The Microchip WebSite...................................................................................................................................................................... 384

Customer Change Notification Service .............................................................................................................................................. 384

Customer Support.............................................................................................................................................................................. 384

Product Identification System............................................................................................................................................................. 385

Worldwide Sales and Service ............................................................................................................................................................ 387

DS40001365F-page 4

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

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enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Website; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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 2009-2016 Microchip Technology Inc.

DS40001365F-page 5

PIC18(L)F1XK22

1.1.2

MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

1.0

DEVICE OVERVIEW

This family offers the advantages of all PIC18

microcontrollers namely, high computational

performance with the addition of high-endurance,

Flash program memory. On top of these features, the

All of the devices in the PIC18(L)F1XK22 family offer

ten different oscillator options, allowing users a wide

range of choices in developing application hardware.

These include:

–

PIC18(L)F1XK22

family

introduces

design

enhancements that make these microcontrollers a

logical choice for many high-performance, power

sensitive applications.

• Four Crystal modes, using crystals or ceramic

resonators

• External Clock modes, offering the option of using

two pins (oscillator input and a divide-by-4 clock

output) or one pin (oscillator input, with the

second pin reassigned as general I/O)

1.1

New Core Features

1.1.1

XLP TECHNOLOGY

• External RC Oscillator modes with the same pin

options as the External Clock modes

All of the devices in the PIC18(L)F1XK22 family

incorporate a range of features that can significantly

reduce power consumption during operation. Key

items include:

• An internal oscillator block which contains a

16 MHz HFINTOSC oscillator and a 31 kHz

LFINTOSC oscillator which together provide eight

user selectable clock frequencies, from 31 kHz to

16 MHz. This option frees the two oscillator pins

for use as additional general purpose I/O.

• Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active. In these states, power consumption can be

reduced even further, to as little as 4% of normal

operation requirements.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the high-speed crystal and

internal oscillator modes, which allows clock

speeds of up to 64 MHz. Used with the internal

oscillator, the PLL gives users a complete

selection of clock speeds, from 31 kHz to 64 MHz

– all without using an external crystal or clock

circuit.

• On-the-fly Mode Switching: The

power-managed modes are invoked by user code

during operation, allowing the user to incorporate

power-saving ideas into their application’s

software design.

• Low Consumption in Key Modules: The

power requirements for both Timer1 and the

Watchdog Timer are minimized. See

Section 26.0 “Electrical Specifications”

for values.

Besides its availability as a clock source, the internal

oscillator block provides a stable reference source that

gives the family additional features for robust

operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a

reference signal provided by the LFINTOSC. If a

clock failure occurs, the controller is switched to

the internal oscillator block, allowing for continued

operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset, or wake-up from Sleep

mode, until the primary clock source is available.

DS40001365F-page 6

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

1.2

Other Special Features

1.3

Details on Individual Family

Members

• Memory Endurance: The Flash cells for both

program memory and data EEPROM are rated to

last for many thousands of erase/write cycles – up to

10K for program memory and 100K for EEPROM.

Data retention without refresh is conservatively

estimated to be greater than 40 years.

Devices in the PIC18(L)F1XK22 family are available in

20-pin packages. Block diagrams for the two groups

are shown in Figure 1-1.

The devices are differentiated from each other in the

following ways:

• Self-programmability: These devices can write

to their own program memory spaces under

internal software control. Using a bootloader

routine located in the code protected Boot Block,

it is possible to create an application that can

update itself in the field.

1. Flash program memory:

• 8 Kbytes for PIC18(L)F13K22

• 16 Kbytes for PIC18(L)F14K22

All other features for devices in this family are identical.

These are summarized in Table 1-1.

• Extended Instruction Set: The PIC18(L)F1XK22

family introduces an optional extension to the

PIC18 instruction set, which adds eight new

instructions and an Indexed Addressing mode.

This extension has been specifically designed to

optimize re-entrant application code originally

developed in high-level languages, such as C.

The pinouts for all devices are listed in Table 1 and I/O

description are in Table 1-2.

• Enhanced CCP module: In PWM mode, this

module provides one, two or four modulated

outputs for controlling half-bridge and full-bridge

drivers. Other features include:

- Auto-Shutdown, for disabling PWM outputs

on interrupt or other select conditions

- Auto-Restart, to reactivate outputs once the

condition has cleared

- Output steering to selectively enable one or

more of four outputs to provide the PWM

signal.

• Enhanced Addressable USART: This serial

communication module is capable of standard

RS-232 operation and provides support for the LIN

bus protocol. Other enhancements include

automatic baud rate detection and a 16-bit Baud

Rate Generator for improved resolution.

• 10-bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period and

thus, reduce code overhead.

• Extended Watchdog Timer (WDT): This

enhanced version incorporates a 16-bit

postscaler, allowing an extended time-out range

that is stable across operating voltage and

temperature. See Section 26.0 “Electrical

Specifications” for time-out periods.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 7

PIC18(L)F1XK22

TABLE 1-1:

DEVICE FEATURES FOR THE PIC18(L)F1XK22 (20-PIN DEVICES)

Features PIC18F13K22 PIC18LF13K22 PIC18F14K22 PIC18LF14K22

2.3-5.5V 1.8V-3.6V 2.3-5.5V 1.8V-3.6V

Voltage Range (1.8 - 5.5V)

Program Memory (Bytes)

Program Memory (Instructions)

Data Memory (Bytes)

Operating Frequency

Interrupt Sources

8K

4096

256

16K

8192

512

DC – 64 MHz

30

I/O Ports

Ports A, B, C

Timers

4

1

Enhanced Capture/ Compare/PWM Modules

Serial Communications

10-Bit Analog-to-Digital Module

Resets (and Delays)

MSSP, Enhanced USART

12 Input Channels

POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT

(PWRT, OST)

Instruction Set

Packages

75 Instructions, 83 with Extended Instruction Set Enabled

20-Pin PDIP, SSOP, SOIC

QFN (4x4x0.9mm)

DS40001365F-page 8

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 1-1:

PIC18(L)F1XK22 BLOCK DIAGRAM

Data Bus<8>

Table Pointer<21>

Data Latch

8

PORTA

inc/dec logic

21

RA0

RA1

RA3

RA4

RA5

Data Memory

(512/768 bytes)

PCLATH

PCLATU

Address Latch

20

PCU PCH PCL

Program Counter

12

Data Address<12>

31-Level Stack

STKPTR

4

BSR

12

FSR0

FSR1

FSR2

4

Address Latch

Program Memory

Data Latch

Access

Bank

12

PORTB

RB4

RB5

RB6

RB7

inc/dec

logic

8

Table Latch

Address

Decode

ROM Latch

IR

Instruction Bus <16>

8

State machine

control signals

Instruction

Decode and

Control

PRODH PRODL

8 x 8 Multiply

PORTC

RC0

RC1

3

8

RC2

RC3

RC4

RC5

RC6

RC7

W

BITOP

8

Power-up

Timer

Internal

Oscillator

Block

OSC1⁽²⁾

8

Oscillator

Start-up Timer

LFINTOSC

Oscillator

OSC2⁽²⁾

ALU<8>

8

Power-on

Reset

16 MHz

Oscillator

MCLR⁽¹⁾

VDD, VSS

Watchdog

Timer

Single-Supply

Programming

Precision

FVR

Fail-Safe

Clock Monitor

Band Gap

Reference

DAC

Data

EEPROM

BOR

Timer0

MSSP

Timer1

Timer2

Timer3

FVR

CVREF/DAC1

FVR

ADC

10-bit

Comparator

ECCP1

EUSART

CVREF/DAC1

Note 1: RA3 is only available when MCLR functionality is disabled.

2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used

as digital I/O. Refer to Section 2.0 “Oscillator Module” for additional information.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 9

PIC18(L)F1XK22

TABLE 1-2:

PIC18(L)F1XK22 PIN SUMMARY

Number

Type

Buffer

Type

Pin Name

Description

RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD

19

16

RA0

AN0

I/O

TTL

Analog

ST

Digital I/O

ADC channel 0

DAC reference voltage output

ADC and DAC reference voltage (low) input

Comparator C1 noninverting input

External interrupt 0

I

O

I

CVREF/DAC1OUT

VREF-

C1IN+

INT0

PGD

I/O

ST

ICSP™ programming data pin

RA1/AN1/C12IN0-/VREF+/INT1/PGC

18

17

15

14

RA1

AN1

C12IN0-

VREF+

INT1

I/O

I

1

I

TTL

Analog

ST

Digital I/O

ADC channel 1

Comparator C1 and C2 inverting input

ADC and DAC reference voltage (high) input

External interrupt 1

PGC

I/O

ST

ICSP programming clock pin

RA2/AN2/C1OUT/T0CKI/INT2/SRQ

I/O

I

—

I

O

RA2

AN2

C1OUT

T0CKI

INT2

ST

Analog

CMOS

ST

CMOS

Digital I/O

ADC channel 2

Comparator C1 output

Timer0 external clock input

External interrupt 2

SR latch output

SRQ

4

3

1

RA3/MCLR/VPP

RA3

I

P

ST

—

Digital input

Active-low Master Clear with internal pull-up

High voltage programming input

MCLR

VPP

20

RA4/AN3/OSC2/CLKOUT

RA4

AN3

OSC2

I/O

I

O

TTL

Analog

XTAL

Digital I/O

ADC channel 3

Oscillator crystal output. Connect to crystal or resonator

in Crystal Oscillator mode

CLKOUT

O

CMOS

In RC mode, OSC2 pin outputs CLKOUT which

has 1/4 the frequency of OSC1 and denotes

the instruction cycle rate

2

19

RA5/OSC1/CLKIN/T13CKI

RA5

OSC1

I/O

I

TTL

XTAL

Digital I/O

Oscillator crystal input or external clock input

ST buffer when configured in RC mode; analog other

wise

CLKIN

I

CMOS

ST

External clock source input. Always associated with the

pin function OSC1 (See related OSC1/CLKIN, OSC2,

CLKOUT pins

T13CKI

Timer0 and Timer3 external clock input

13

10

RB4/AN10/SDI/SDA

RB4

AN10

SDI

I/O

I

TTL

Analog

ST

Digital I/O

ADC channel 10

SPI data in

2

SDA

I/O

ST

I C data I/O

Legend: TTL

=

TTL compatible input

Schmitt Trigger input

Output

CMOS

I

P

=

CMOS compatible input or output

Input

Power

ST

O

XTAL= Crystal Oscillator

DS40001365F-page 10

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 1-2:

PIC18(L)F1XK22 PIN SUMMARY (CONTINUED)

Number

Type

Buffer

Type

Pin Name

Description

12

9

RB5/AN11/RX/DT

RB5

AN11

RX

I/O

I

TLL

Analog

ST

Digital I/O

ADC channel 11

EUSART asynchronous receive

EUSART synchronous data (see related RX/TX)

DT

I/O

ST

11

10

8

7

RB6/SCK/SCL

RB6

I/O

TLL

ST

Digital I/O

SCK

SCL

Synchronous serial clock input/output for SPI mode

Synchronous serial clock input/output for I C mode

2

RB7/TX/CK

RB7

TX

CK

I/O

O

I/O

TLL

CMOS

ST

Digital I/O

EUSART asynchronous transmit

EUSART synchronous clock (see related RX/DT)

RC0/AN4/C2IN+

RC0

16

15

14

13

12

11

I/O

I

ST

Analog

Digital I/O

ADC channel 4

Comparator C2 noninverting input

AN4

C2IN+

RC1/AN5/C12IN-

RC1

I/O

I

ST

Analog

Digital I/O

ADC channel 5

Comparator C1 and C2 inverting input

AN5

C12IN-

RC2/AN6/C12IN2-/P1D

RC2

I/O

ST

Digital I/O

AN6

C12IN2-

P1D

I

O

Analog

CMOS

ADC channel 6

Comparator C1 and C2 inverting input

Enhanced CCP1 PWM output

RC3/AN7/C12IN3-/P1C/PGM

7

6

4

3

RC3

AN7

C12IN3-

P1C

PGM

I/O

I

O

I/O

ST

Digital I/O

ADC channel 7

Comparator C1 and C2 inverting input

Enhanced CCP1 PWM output

Low-Voltage ICSP Programming enable pin

Analog

CMOS

ST

RC4/C2OUT/P1B/SRNQ

RC4

C2OUT

P1B

I/O

O

ST

Digital I/O

CMOS

Comparator C2 output

Enhanced CCP1 PWM output

SR latch inverted output

SRNQ

O

RC5/CCP1/P1A

RC5

5

8

9

2

5

6

I/O

O

ST

CMOS

Digital I/O

CCP1

P1A

Capture 1 input/Compare 1 output/PWM 1 output

Enhanced CCP1 PWM output

RC6/AN8/SS

RC6

I/O

I

ST

Analog

TTL

Digital I/O

ADC channel 8

SPI slave select input

AN8

SS

RC7/AN9/SDO

RC7

I/O

I

O

ST

Analog

CMOS

Digital I/O

ADC channel 9

SPI data out

AN9

SDO

VSS

VDD

20

1

17

18

P

—

Ground reference for logic and I/O pins

Positive supply for logic and I/O pins

Legend: TTL

=

TTL compatible input

Schmitt Trigger input

Output

CMOS

I

P

=

CMOS compatible input or output

Input

Power

ST

O

XTAL= Crystal Oscillator

 2009-2016 Microchip Technology Inc.

DS40001365F-page 11

PIC18(L)F1XK22

2.3

System Clock Selection

2.0

2.1

OSCILLATOR MODULE

Overview

The SCS bits of the OSCCON register select between

the following clock sources:

The oscillator module has a variety of clock sources

and features that allow it to be used in a wide range of

applications, maximizing performance and minimizing

power consumption. Figure 2-1 illustrates a block

diagram of the oscillator module.

• Primary External Oscillator

• Secondary External Oscillator

• Internal Oscillator

Note:

The frequency of the system clock will be

referred to as FOSC throughout this

document.

Key features of the oscillator module include:

• System Clocks

• System Clock Selection

- Primary External Oscillator

- Secondary External Oscillator

- Internal Oscillator

TABLE 2-1:

SYSTEM CLOCK SELECTION

Selection

Configuration

SCS <1:0>

System Clock

1x

01

00

Internal Oscillator

• Oscillator Start-up Timer

• System Clock Selection

• Clock Switching

Secondary External Oscillator

Oscillator defined by

(Default after Reset) FOSC<3:0>

• 4x Phase Lock Loop Frequency Multiplier

• CPU Clock Divider

The default state of the SCS bits sets the system clock

to be the oscillator defined by the FOSC bits of the

CONFIG1H Configuration register. The system clock

will always be defined by the FOSC bits until the SCS

bits are modified in software.

• Two-Speed Start-up Mode

• Fail-Safe Clock Monitoring

2.2

System Clocks

When the Internal Oscillator is selected as the system

clock, the IRCF bits of the OSCCON register and the

INTSRC bit of the OSCTUNE register will select either

the LFINTOSC or the HFINTOSC. The LFINTOSC is

selected when the IRCF<2:0> = 000and the INTSRC

bit is clear. All other combinations of the IRCF bits and

the INTSRC bit will select the HFINTOSC as the

system clock.

The PIC18(L)F1XK22 can be operated in 13 different

oscillator modes. The user can program these using

the available Configuration bits. In addition, clock

support functions such as Fail-Safe and two Start-up

can also be configured.

The available Primary oscillator options include:

• External Clock, low power (ECL)

• External Clock, medium power (ECM)

• External Clock, high power (ECH)

2.4

Primary External Oscillator

The Primary External Oscillator’s mode of operation is

selected by setting the FOSC<3:0> bits of the

CONFIG1H Configuration register. The oscillator can

be set to the following modes:

• External Clock, low power, CLKOUT function on

RA4/OSC2 (ECCLKOUTL)

• External Clock, medium power, CLKOUT function

on RA4/OSC2 (ECCLKOUTM)

• LP: Low-Power Crystal

• External Clock, high power, CLKOUT function on

RA4/OSC2 (ECCLKOUTH)

• XT: Crystal/Ceramic Resonator

• HS: High-Speed Crystal Resonator

• RC: External RC Oscillator

• EC: External Clock

• External Crystal (XT)

• High-speed Crystal (HS)

• Low-power crystal (LP)

• External Resistor/Capacitor (EXTRC)

• External RC, CLKOUT function on RA4/OSC2

• 31.25 kHz – 16 MHz internal oscillator (INTOSC)

Additionally, the Primary External Oscillator may be

shut down under firmware control to save power.

• 31.25 kHz – 16 MHz internal oscillator, CLKOUT

function on RA4/OSC2

Additionally, the 4x PLL may be enabled in hardware or

software (under certain conditions) for increased

oscillator speed.

DS40001365F-page 12

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 2-1:

PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

Primary

Oscillator,

External

PIC18(L)F1XK22

and

Timer1/Timer3

Secondary

OSC1/T13CKI

OSC2

Oscillator

Sleep

IDLEN

Sleep

PCLKEN

PRI_SD

LP, XT, HS, RC, EC,

Secondary Osc.

4 x PLL

1

0

0x

1x

FOSC<3:0>

Peripherals

CPU

T1OSCEN

PLL_EN

PLLEN

Internal Osc.

System

Clock

IRCF<2:0>

16 MHz

Sleep

8 MHz

110

Internal

Oscillator

Block

4 MHz

101

2 MHz

FOSC<3:0>

SCS<1:0>

100

1 MHz

16 MHz

HFINTOSC

Clock

Control

011

500 kHz

010

31 kHz

LFINTOSC

250 kHz

001

1

0

31 kHz

000

INTSRC

Fail-Safe

Clock

Watchdog

Timer

Two-Speed

Start-up

Note:

If using a low-frequency external oscillator

and want to multiple it by 4 via PLL, the

ideal input frequency is from 4 MHz to

16 MHz.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 13

PIC18(L)F1XK22

2.4.1

PRIMARY EXTERNAL OSCILLATOR

SHUTDOWN

FIGURE 2-2:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

The Primary External Oscillator can be enabled or

disabled via software. To enable software control of the

Primary External Oscillator, the PCLKEN bit of the

CONFIG1H Configuration register must be set. With

the PCLKEN bit set, the Primary External Oscillator is

controlled by the PRI_SD bit of the OSCCON2 register.

The Primary External Oscillator will be enabled when

the PRI_SD bit is set, and disabled when the PRI_SD

bit is clear.

PIC^®MCU

OSC1/CLKIN

C1

To Internal

Logic

Quartz

Crystal

(2)

Sleep

RF

Note:

The Primary External Oscillator cannot be

shut down when it is selected as the

System Clock. To shut down the oscillator,

the system clock source must be either

the Secondary Oscillator or the Internal

Oscillator.

OSC2/CLKOUT

(1)

C2

RS

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

2.4.2

LP, XT AND HS OSCILLATOR

MODES

Note 1: Quartz

crystal

characteristics

vary

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 2-2). The mode selects a low,

medium or high gain setting of the internal inverter-

amplifier to support various resonator types and speed.

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is best suited

to drive resonators with a low drive level specification, for

example, tuning fork type crystals.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and

PICmicro^®Devices (DS00826)

• AN849, Basic PICmicro^®Oscillator

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

Design (DS00849)

• AN943, Practical PICmicro^®Oscillator

Analysis and Design (DS00943)

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require a high drive setting.

• AN949, Making Your Oscillator Work

(DS00949)

Figure 2-2 and Figure 2-3 show typical circuits for

quartz crystal and ceramic resonators, respectively.

DS40001365F-page 14

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

The RC oscillator frequency is a function of the supply

voltage, the resistor REXT, the capacitor CEXT and the

operating temperature. Other factors affecting the

oscillator frequency are:

FIGURE 2-3:

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

PIC^®MCU

• Input threshold voltage variation

• Component tolerances

OSC1/CLKIN

• Variation in capacitance due to packaging

C1

To Internal

Logic

2.4.4

EXTERNAL CLOCK

The External Clock (EC) mode allows an externally

generated logic level clock to be used as the system’s

clock source. When operating in this mode, the

external clock source is connected to the OSC1

allowing OSC2 to be configured as an I/O or as

CLKOUT. The CLKOUT function is selected by the

FOSC bits of the CONFIG1H Configuration register.

When OSC2 is configured as CLKOUT, the frequency

at the pin is the frequency of the EC oscillator divided

by 4.

(3)

(2)

RP

RF

Sleep

OSC2/CLKOUT

(1)

C2

RS

Ceramic

Resonator

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

Three different power settings are available for EC

mode. The power settings allow for a reduced IDD of the

device, if the EC clock is known to be in a specific

range. If there is an expected range of frequencies for

the EC clock, select the power mode for the highest

frequency.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

2.4.3

EXTERNAL RC

The External Resistor-Capacitor (RC) mode supports

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. In RC mode, the RC circuit connects to OSC1,

allowing OSC2 to be configured as an I/O or as

CLKOUT. The CLKOUT function is selected by the

FOSC bits of the CONFIG1H Configuration register.

When OSC2 is configured as CLKOUT, the frequency

at the pin is the frequency of the RC oscillator divided by

4. Figure 2-4 shows the external RC mode connections.

EC

Low power

Medium power 250 kHz – 4 MHz

High power 4 – 64 MHz

0 – 250 kHz

2.5

Secondary External Oscillator

The Secondary External Oscillator is designed to drive

an external 32.768 kHz crystal. This oscillator is

enabled or disabled by the T1OSCEN bit of the T1CON

register. See Section 10.0 “Timer1 Module” for more

information.

FIGURE 2-4:

EXTERNAL RC MODES

VDD

PIC^®MCU

REXT

OSC1/CLKIN

Internal

Clock

CEXT

VSS

(1)

FOSC/4 or

I/O

OSC2/CLKOUT

(2)

Recommended values: 10 k  REXT  100 k

CEXT > 20 pF

Note 1: Alternate pin functions are listed in

Section 1.0 “Device Overview”.

2: Output depends upon RC or RCIO clock mode.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 15

PIC18(L)F1XK22

2.6.2

HFINTOSC

2.6

Internal Oscillator

The High-Frequency Internal Oscillator (HFINTOSC) is

a precision oscillator that is factory-calibrated to

operate at 16 MHz. The output of the HFINTOSC

connects to a postscaler and a multiplexer (see

Figure 2-1). One of eight frequencies can be selected

using the IRCF<2:0> bits of the OSCCON register. The

following frequencies are available from the

HFINTOSC:

The internal oscillator module contains two independent

oscillators which are:

• LFINTOSC: Low-Frequency Internal Oscillator

• HFINTOSC: High-Frequency Internal Oscillator

When operating with either oscillator, OSC1 will be an

I/O and OSC2 will be either an I/O or CLKOUT. The

CLKOUT function is selected by the FOSC bits of the

CONFIG1H Configuration register. When OSC2 is

configured as CLKOUT, the frequency at the pin is the

frequency of the Internal Oscillator divided by 4.

• 16 MHZ

• 8 MHZ

• 4 MHZ

• 2 MHZ

2.6.1

LFINTOSC

• 1 MHZ (Default after Reset)

• 500 kHz

The Low-Frequency Internal Oscillator (LFINTOSC) is

a 31 kHz internal clock source. The LFINTOSC

oscillator is the clock source for:

• 250 kHz

• 31 kHz

• Power-up Timer

• Watchdog Timer

The HFIOFS bit of the OSCCON register indicates

whether the HFINTOSC is stable.

• Fail-Safe Clock Monitor

The LFINTOSC is enabled when any of the following

conditions are true:

Note 1: Selecting 31 kHz from the HFINTOSC

oscillator requires IRCF<2:0> = 000and

the INTSRC bit of the OSCTUNE register

to be set. If the INTSRC bit is clear, the

system clock will come from the

LFINTOSC.

• Power-up Timer is enabled (PWRTEN = 0)

• Watchdog Timer is enabled (WDTEN = 1)

• Watchdog Timer is enabled by software

(WDTEN = 0and SWDTEN = 1)

2: Additional adjustments to the frequency

of the HFINTOSC can made via the

OSCTUNE registers. See Register 2-3

for more details.

• Fail-Safe Clock Monitor is enabled (FCMEM = 1)

• SCS1 = 1and IRCF<2:0> = 000and INTSRC = 0

• FOSC<3:0> selects the internal oscillator as the

primary clock and IRCF<2:0> = 000and

INTSRC = 0

The HFINTOSC is enabled if any of the following

conditions are true:

• IESO = 1(Two-Speed Start-up) and

IRCF<2:0> = 000and INTSRC = 0

• SCS1 = 1and IRCF<2:0>  000

• SCS1 = 1and IRCF<2:0> = 000and INTSRC = 1

• FOSC<3:0> selects the internal oscillator as the

primary clock and

- IRCF<2:0>  000or

- IRCF<2:0> = 000and INTSRC = 1

• IESO = 1(Two-Speed Start-up) and

- IRCF<2:0>  000or

- IRCF<2:0> = 000and INTSRC = 1

• FCMEM = 1(Fail-Safe Clock Monitoring) and

- IRCF<2:0>  000or

- IRCF<2:0> = 000and INTSRC = 1

DS40001365F-page 16

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

2.7

Oscillator Control

The Oscillator Control (OSCCON) (Register 2-1) and the

Oscillator Control 2 (OSCCON2) (Register 2-2) registers

control the system clock and frequency selection

options.

REGISTER 2-1:

R/W-0

OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0

IRCF2

R/W-1

IRCF1

R/W-1

IRCF0

R-q

OSTS⁽¹⁾

R-0

R/W-0

SCS1

R/W-0

SCS0

IDLEN

HFIOFS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

q = depends on condition

x = Bit is unknown

bit 7

IDLEN: Idle Enable bit

1= Device enters Idle mode on SLEEPinstruction

0= Device enters Sleep mode on SLEEPinstruction

bit 6-4

IRCF<2:0>: Internal Oscillator Frequency Select bits

111= 16 MHz

110= 8 MHz

101= 4 MHz

100= 2 MHz

011= 1 MHz⁽³⁾

010= 500 kHz

001= 250 kHz

000= 31 kHz⁽²⁾

bit 3

OSTS: Oscillator Start-up Time-out Status bit⁽¹⁾

1= Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register

0= Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

bit 2

HFIOFS: HFINTOSC Frequency Stable bit

1= HFINTOSC frequency is stable

0= HFINTOSC frequency is not stable

bit 1-0

SCS<1:0>: System Clock Select bits

1x= Internal oscillator block

01= Secondary (Timer1) oscillator

00= Primary clock (determined by CONFIG1H[FOSC<3:0>]).

Note 1: Reset state depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit of the OSCTUNE register, see text.

3: Default output frequency of HFINTOSC on Reset.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 17

PIC18(L)F1XK22

REGISTER 2-2:

OSCCON2: OSCILLATOR CONTROL REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

R-x

PRI_SD

HFIOFL

LFIOFS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

q = depends on condition

x = Bit is unknown

bit 7-3

bit 2

Unimplemented: Read as ‘0’

PRI_SD: Primary Oscillator Drive Circuit shutdown bit

1= Oscillator drive circuit on

0= Oscillator drive circuit off (zero power)

bit 1

bit 0

HFIOFL: HFINTOSC Frequency Locked bit

1= HFINTOSC is in lock

0= HFINTOSC has not yet locked

LFIOFS: LFINTOSC Frequency Stable bit

1= LFINTOSC is stable

0= LFINTOSC is not stable

DS40001365F-page 18

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

2.7.1

OSCTUNE REGISTER

The HFINTOSC is factory-calibrated, but can be

adjusted in software by writing to the TUN<5:0> bits of

the OSCTUNE register (Register 2-3).

The OSCTUNE register also implements the INTSRC

and PLLEN bits, which control certain features of the

internal oscillator block.

The default value of the TUN<5:0> is ‘000000’. The

value is a 6-bit two’s complement number.

The INTSRC bit allows users to select which internal

oscillator provides the clock source when the 31 kHz

frequency option is selected. This is covered in greater

detail in Section 2.6.1 “LFINTOSC”.

When the OSCTUNE register is modified, the

HFINTOSC frequency will begin shifting to the new

frequency. Code execution continues during this shift,

while giving no indication that the shift has occurred.

The PLLEN bit controls the operation of the frequency

multiplier. For more details about the function of the

PLLEN bit see Section 2.10 “4x Phase Lock Loop

Frequency Multiplier”.

OSCTUNE does not affect the LFINTOSC frequency.

The operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

REGISTER 2-3:

R/W-0

OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0

TUN5

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

INTSRC

PLLEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

INTSRC: Internal Oscillator Low-Frequency Source Select bit

1= 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)

0= 31 kHz device clock derived directly from LFINTOSC internal oscillator

PLLEN: Frequency Multiplier PLL bit

1= PLL enabled (for HFINTOSC 8 MHz and 16 MHz only)

0= PLL disabled

bit 5-0

TUN<5:0>: Frequency Tuning bits

011111= Maximum frequency

011110=

• • •

000001=

000000= Oscillator module is running at the factory-calibrated frequency.

111111=

• • •

100000= Minimum frequency

 2009-2016 Microchip Technology Inc.

DS40001365F-page 19

PIC18(L)F1XK22

2.8

Oscillator Start-up Timer

2.9

Clock Switching

The Primary External Oscillator, when configured for

LP, XT or HS modes, incorporates an Oscillator Start-up

Timer (OST). The OST ensures that the oscillator starts

and provides a stable clock to the oscillator module.

The OST times out when 1024 oscillations on OSC1

have occurred. During the OST period, with the system

clock set to the Primary External Oscillator, the program

counter does not increment suspending program

execution. The OST period will occur following:

The device contains circuitry to prevent clock “glitches”

due to a change of the system clock source. To

accomplish this, a short pause in the system clock

occurs during the clock switch. If the new clock source

is not stable (e.g., OST is active), the device will

continue to execute from the old clock source until the

new clock source becomes stable. The timing of a

clock switch is as follows:

1. SCS<1:0> bits of the OSCCON register are

modified.

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Wake-up from Sleep

2. The system clock will continue to operate from

the old clock until the new clock is ready.

3. Clock switch circuitry waits for two consecutive

rising edges of the old clock after the new clock

is ready.

• Oscillator being enabled

• Expiration of Power-up Timer (PWRT)

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Start-up

mode can be selected. See Section 2.11 “Two-Speed

Start-up Mode” for more information.

4. The system clock is held low, starting at the next

falling edge of the old clock.

5. Clock switch circuitry waits for an additional two

rising edges of the new clock.

6. On the next falling edge of the new clock, the

low hold on the system clock is release and the

new clock is switched in as the system clock.

7. Clock switch is complete.

Refer to Figure 2-5 for more details.

FIGURE 2-5:

High Speed

CLOCK SWITCH TIMING

Low Speed

Old Clock

(1)

Start-up Time

Clock Sync

Running

New Clock

New Clk Ready

IRCF <2:0>

Select Old

Select New

System Clock

Low Speed

High Speed

Old Clock

(1)

Start-up Time

Clock Sync

Running

New Clock

New Clk Ready

IRCF <2:0>

Select Old

Select New

System Clock

Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.

DS40001365F-page 20

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 2-2:

EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING

Switch From

Switch To

Oscillator Delay

Sleep/POR

LFINTOSC

HFINTOSC

Oscillator Warm-up Delay (TWARM)

Sleep/POR

LP, XT, HS

EC, RC

1024 clock cycles

8 Clock Cycles

2.10 4x Phase Lock Loop Frequency

Multiplier

2.11 Two-Speed Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

Oscillator Start-up Timer (OST) and code execution. In

applications that make heavy use of the Sleep mode,

Two-Speed Start-up will remove the OST period, which

can reduce the overall power consumption of the

device.

A Phase Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower-frequency

external oscillator or to operate at 32 MHz or 64 MHz

with the HFINTOSC. The PLL is designed for an input

frequency from 4 MHz to 16 MHz. The PLL multiplies

its input frequency by a factor of four when the PLL is

enabled. This may be useful for customers who are

concerned with EMI, due to high-frequency crystals.

Two-Speed Start-up mode is enabled by setting the

IESO bit of the CONFIG1H Configuration register. With

Two-Speed Start-up enabled, the device will execute

instructions using the internal oscillator during the

Primary External Oscillator OST period.

Two bits control the PLL: the PLL_EN bit of the

CONFIG1H Configuration register and the PLLEN bit of

the OSCTUNE register. The PLL is enabled when the

PLL_EN bit is set and it is under software control when

the PLL_EN bit is cleared. Refer to Table 2-3 and

Table 2-4 for more information.

When the system clock is set to the Primary External

Oscillator and the oscillator is configured for LP, XT or

HS modes, the device will not execute code during the

OST period. The OST will suspend program execution

until 1024 oscillations are counted. Two-Speed Start-up

mode minimizes the delay in code execution by

operating from the internal oscillator while the OST is

active. The system clock will switch back to the Primary

External Oscillator after the OST period has expired.

TABLE 2-3:

PLL_EN

PLL CONFIGURATION

PLLEN

PLL Status

1

0

x

1

0

PLL enabled

PLL disabled

Two-speed Start-up will become active after:

• Power-on Reset (POR)

• Power-up Timer (PWRT), if enabled

• Wake-up from Sleep

TABLE 2-4:

PLL CONFIG1H/SOFTWARE

ENABLE CLOCK SOURCE

RESTRICTIONS

The OSTS bit of the OSCCON register reports which

oscillator the device is currently using for operation.

The device is running from the oscillator defined by the

FOSC bits of the CONFIG1H Configuration register

when the OSTS bit is set. The device is running from

the internal oscillator when the OSTS bit is clear.

PLL CONFIG1H

PLL Software

Mode

Enable (PLL_EN) Enable (PLLEN)

LP

XT

Yes

No

HS

Yes

No

EC

Yes

No

EXTRC

LF INTOSC

HF INTOSC

Yes

No

8/16 MHz

 2009-2016 Microchip Technology Inc.

DS40001365F-page 21

PIC18(L)F1XK22

2.12.3

FAIL-SAFE CONDITION CLEARING

2.12 Fail-Safe Clock Monitor

The Fail-Safe condition is cleared by either one of the

following:

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

CONFIG1H Configuration register. The FSCM is

applicable to all external oscillator modes (LP, XT, HS,

EC and RC).

• Any Reset

• By toggling the SCS1 bit of the OSCCON register

Both of these conditions restart the OST. While the

OST is running, the device continues to operate from

the INTOSC selected in OSCCON. When the OST

times out, the Fail-Safe condition is cleared and the

device automatically switches over to the external clock

source. The Fail-Safe condition need not be cleared

before the OSCFIF flag is cleared.

FIGURE 2-6:

FSCM BLOCK DIAGRAM

Clock Monitor

Latch

External

Clock

2.12.4

RESET OR WAKE-UP FROM SLEEP

S

Q

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled. Therefore, the device will always be executing

code while the OST is operating.

LFINTOSC

Oscillator

÷ 64

R

Q

31 kHz

(~32 s)

488 Hz

(~2 ms)

Sample Clock

Clock

Failure

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit of the OSCCON register to verify

the oscillator start-up and that the system

Detected

2.12.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 2-6. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire half-

cycle of the sample clock elapses before the primary

clock goes low.

clock

switchover

has

successfully

completed.

2.12.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit

flag OSCFIF of the PIR2 register. The OSCFIF flag will

generate an interrupt if the OSCFIE bit of the PIE2

register is also set. The device firmware can then take

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation. An automatic

transition back to the failed clock source will not occur.

The internal clock source chosen by the FSCM is

determined by the IRCF<2:0> bits of the OSCCON

register. This allows the internal oscillator to be

configured before a failure occurs.

DS40001365F-page 22

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PIC18(L)F1XK22

FIGURE 2-7:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSCFIF

Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

TABLE 2-5:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values on

page

CONFIG1H

INTCON

OSCCON

OSCCON2

OSCTUNE

IPR2

IESO

FCMEN

PCLKEN

TMR0IE

IRCF1

—

PLL_EN

INT0IE

IRCF0

—

FOSC3

RABIE

OSTS

—

FOSC2

TMR0IF

HFIOFS

PRI_SD

TUN2

—

FOSC1

INT0IF

SCS1

FOSC0

RABIF

SCS0

LFIOFS

TUN0

—

251

245

246

248

246

GIE/GIEH PEIE/GIEL

IDLEN

—

IRCF2

—

HFIOFL

TUN1

INTSRC

OSCFIP

OSCFIE

OSCFIF

RD16

PLLEN

C1IP

TUN5

C2IP

TUN4

EEIP

TUN3

BCLIP

BCLIE

BCLIF

TMR3IP

TMR3IE

TMR3IF

PIE2

C1IE

C2IE

EEIE

—

PIR2

C1IF

C2IF

EEIF

—

T1CON

T1RUN

T1CKPS1

T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

Legend:

x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 23

PIC18(L)F1XK22

3.1

Program Memory Organization

3.0

MEMORY ORGANIZATION

PIC18 microcontrollers implement a 21-bit program

counter, which is capable of addressing a 2-Mbyte

Program Memory (PC) space. Accessing a location

between the upper boundary of the physically

implemented memory and the 2-Mbyte address will

return all ‘0’s (a NOPinstruction).

There are three types of memory in PIC18 Enhanced

microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard architecture devices, the data and program

memories use separate busses; this allows for

concurrent access of the two memory spaces. The data

EEPROM, for practical purposes, can be regarded as

a peripheral device, since it is addressed and accessed

through a set of control registers.

This family of devices contain the following:

• PIC18(L)F13K22: 8 Kbytes of Flash Memory, up to

4,096 single-word instructions

• PIC18(L)F14K22: 16 Kbytes of Flash Memory, up

to 8,192 single-word instructions

PIC18 devices have two interrupt vectors and one

Reset vector. The Reset vector address is at 0000h

and the interrupt vector addresses are at 0008h and

0018h.

Additional detailed information on the operation of the

Flash program memory is provided in Section 4.0

“Flash Program Memory”. Data EEPROM is

discussed separately in Section 5.0 “Data EEPROM

Memory”.

The program memory map for PIC18(L)F1XK22

devices is shown in Figure 3-1. Memory block details

are shown in Figure 3-2.

FIGURE 3-1:

PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F1XK22 DEVICES

PC<20:0>

21

CALL,RCALL,RETURN

RETFIE,RETLW

Stack Level 1



Stack Level 31

0000h

Reset Vector

High Priority Interrupt Vector

Low Priority Interrupt Vector

0008h

0018h

On-Chip

Program Memory

On-Chip

Program Memory

1FFFh

2000h

3FFFh

4000h

PIC18(L)F13K22

PIC18(L)F14K22

Read ‘0’

1FFFFFh

200000h

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PIC18(L)F1XK22

The stack operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, STKPTR. The stack space is not

part of either program or data space. The Stack Pointer

is readable and writable and the address on the top of

the stack is readable and writable through the Top-of-

Stack (TOS) Special File Registers. Data can also be

pushed to, or popped from the stack, using these

registers.

3.1.1

PROGRAM COUNTER

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21-bit wide

and is contained in three separate 8-bit registers. The

low byte, known as the PCL register, is both readable

and writable. The high byte, or PCH register, contains

the PC<15:8> bits; it is not directly readable or writable.

Updates to the PCH register are performed through the

PCLATH register. The upper byte is called PCU. This

register contains the PC<20:16> bits; it is also not

directly readable or writable. Updates to the PCU

register are performed through the PCLATU register.

A CALLtype instruction causes a push onto the stack;

the Stack Pointer is first incremented and the location

pointed to by the Stack Pointer is written with the

contents of the PC (already pointing to the instruction

following the CALL). A RETURNtype instruction causes

a pop from the stack; the contents of the location

pointed to by the STKPTR are transferred to the PC

and then the Stack Pointer is decremented.

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes

PCL. Similarly, the upper two bytes of the program

counter are transferred to PCLATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 3.1.4.1 “Computed

GOTO”).

The Stack Pointer is initialized to ‘00000’ after all

Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘00000’; this

is only a Reset value. Status bits indicate if the stack is

full or has overflowed or has underflowed.

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Significant bit (LSb) of PCL is

fixed to a value of ‘0’. The PC increments by 2 to

address sequential instructions in the program

memory.

3.1.2.1

Top-of-Stack Access

Only the top of the return address stack (TOS) is readable

and writable. A set of three registers, TOSU:TOSH:TOSL,

hold the contents of the stack location pointed to by the

STKPTR register (Figure 3-2). This allows users to

implement a software stack if necessary. After a CALL,

RCALL or interrupt, the software can read the pushed

value by reading the TOSU:TOSH:TOSL registers. These

values can be placed on a user defined software stack. At

return time, the software can return these values to

TOSU:TOSH:TOSL and do a return.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

3.1.2

RETURN ADDRESS STACK

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC is

pushed onto the stack when a CALL or RCALL

instruction is executed or an interrupt is Acknowledged.

The PC value is pulled off the stack on a RETURN,

RETLWor a RETFIEinstruction. PCLATU and PCLATH

are not affected by any of the RETURN or CALL

instructions.

The user must disable the global interrupt enable bits

while accessing the stack to prevent inadvertent stack

corruption.

FIGURE 3-2:

RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack <20:0>

11111

11110

11101

Top-of-Stack Registers

Stack Pointer

STKPTR<4:0>

TOSU

00h

TOSH

1Ah

TOSL

34h

00010

00011

00010

00001

00000

001A34h

000D58h

Top-of-Stack

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PIC18(L)F1XK22

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the Stack

Pointer remains at zero. The STKUNF bit will remain

set until cleared by software or until a POR occurs.

3.1.2.2

Return Stack Pointer (STKPTR)

The STKPTR register (Figure 3-1) contains the Stack

Pointer value, the STKFUL (Stack Full) bit and the

STKUNF (Stack Underflow) bits. The value of the Stack

Pointer can be 0 through 31. The Stack Pointer

increments before values are pushed onto the stack

and decrements after values are popped off the stack.

On Reset, the Stack Pointer value will be zero. The

user may read and write the Stack Pointer value. This

feature can be used by a Real-Time Operating System

(RTOS) for return stack maintenance.

Note:

Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken. This is

not the same as a Reset, as the contents

of the SFRs are not affected.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKOVF bit is cleared by software or by a

POR.

3.1.2.3

PUSHand POPInstructions

Since the Top-of-Stack is readable and writable, the

ability to push values onto the stack and pull values off

the stack without disturbing normal program execution

is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

TOSU, TOSH and TOSL can be modified to place data

or a return address on the stack.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack

Overflow Reset Enable) Configuration bit. (Refer to

Section 23.1 “Configuration Bits” for a description of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKOVF bit and reset the

device. The STKOVF bit will remain set and the Stack

Pointer will be set to zero.

The PUSHinstruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

If STVREN is cleared, the STKOVF bit will be set on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

The POP instruction discards the current TOS by

decrementing the Stack Pointer. The previous value

pushed onto the stack then becomes the TOS value.

REGISTER 3-1:

STKPTR: STACK POINTER REGISTER

R/C-0

STKOVF⁽¹⁾

R/C-0

STKUNF⁽¹⁾

U-0

—

R/W-0

SP4

R/W-0

SP3

R/W-0

SP2

R/W-0

SP1

R/W-0

SP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented

‘0’ = Bit is cleared

C = Clearable only bit

x = Bit is unknown

-n = Value at POR

bit 7

bit 6

STKOVF: Stack Overflow Flag bit⁽¹⁾

1= Stack became full or overflowed

0= Stack has not become full or overflowed

STKUNF: Stack Underflow Flag bit⁽¹⁾

1= Stack underflow occurred

0= Stack underflow did not occur

bit 5

Unimplemented: Read as ‘0’

bit 4-0

SP<4:0>: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

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PIC18(L)F1XK22

3.1.2.4

Stack Overflow and Underflow

Resets

3.1.4

LOOK-UP TABLES IN PROGRAM

MEMORY

Device Resets on Stack Overflow and Stack Underflow

conditions are enabled by setting the STVREN bit in

Configuration Register 4L. When STVREN is set, a full

or underflow will set the appropriate STKOVF or

STKUNF bit and then cause a device Reset. When

STVREN is cleared, a full or underflow condition will set

the appropriate STKOVF or STKUNF bit but not cause

a device Reset. The STKOVF or STKUNF bits are

cleared by the user software or a Power-on Reset.

There may be programming situations that require the

creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables

can be implemented in two ways:

• Computed GOTO

• Table Reads

3.1.4.1

Computed GOTO

A computed GOTOis accomplished by adding an offset

to the program counter. An example is shown in

Example 3-2.

3.1.3

FAST REGISTER STACK

A fast register stack is provided for the STATUS,

WREG and BSR registers, to provide a “fast return”

option for interrupts. The stack for each register is only

one level deep and is neither readable nor writable. It is

loaded with the current value of the corresponding

register when the processor vectors for an interrupt. All

interrupt sources will push values into the stack

registers. The values in the registers are then loaded

back into their associated registers if the

RETFIE, FAST instruction is used to return from the

interrupt.

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW nninstructions. The

W register is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCLinstruction. The next

instruction executed will be one of the RETLW nn

instructions that returns the value ‘nn’ to the calling

function.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be multiples of 2 (LSb = 0).

If both low and high priority interrupts are enabled, the

stack registers cannot be used reliably to return from

low priority interrupts. If a high priority interrupt occurs

while servicing a low priority interrupt, the stack register

values stored by the low priority interrupt will be

overwritten. In these cases, users must save the key

registers by software during a low priority interrupt.

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

EXAMPLE 3-2:

COMPUTED GOTO USING

AN OFFSET VALUE

If interrupt priority is not used, all interrupts may use the

fast register stack for returns from interrupt. If no

interrupts are used, the fast register stack can be used

to restore the STATUS, WREG and BSR registers at

the end of a subroutine call. To use the fast register

stack for a subroutine call, a CALL label, FAST

instruction must be executed to save the STATUS,

WREG and BSR registers to the fast register stack. A

RETURN, FASTinstruction is then executed to restore

these registers from the fast register stack.

MOVF

CALL

OFFSET, W

TABLE

ORG

TABLE

nn00h

ADDWF

RETLW

.

PCL

nnh

.

Example 3-1 shows a source code example that uses

the fast register stack during a subroutine call and

return.

3.1.4.2

Table Reads and Table Writes

A better method of storing data in program memory

allows two bytes of data to be stored in each instruction

location.

EXAMPLE 3-1:

FAST REGISTER STACK

CODE EXAMPLE

Look-up table data may be stored two bytes per

program word by using table reads and writes. The

Table Pointer (TBLPTR) register specifies the byte

address and the Table Latch (TABLAT) register

contains the data that is read from or written to program

memory. Data is transferred to or from program

memory one byte at a time.

CALL SUB1, FAST

;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK



SUB1



Table read and table write operations are discussed

further in Section 4.1 “Table Reads and Table

Writes”.

RETURN, FAST

;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

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DS40001365F-page 27

PIC18(L)F1XK22

3.2.2

INSTRUCTION FLOW/PIPELINING

3.2

PIC18 Instruction Cycle

An “Instruction Cycle” consists of four Q cycles: Q1

through Q4. The instruction fetch and execute are

pipelined in such a manner that a fetch takes one

instruction cycle, while the decode and execute take

another instruction cycle. However, due to the

pipelining, each instruction effectively executes in one

cycle. If an instruction causes the program counter to

change (e.g., GOTO), then two cycles are required to

complete the instruction (Example 3-3).

3.2.1

CLOCKING SCHEME

The microcontroller clock input, whether from an

internal or external source, is internally divided by four

to generate four non-overlapping quadrature clocks

(Q1, Q2, Q3 and Q4). Internally, the program counter is

incremented on every Q1; the instruction is fetched

from the program memory and latched into the

instruction register during Q4. The instruction is

decoded and executed during the following Q1 through

Q4. The clocks and instruction execution flow are

shown in Figure 3-3.

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-3:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

Internal

Phase

Clock

PC

PC + 2

PC + 4

OSC2/CLKOUT

(RC mode)

Execute INST (PC – 2)

Fetch INST (PC)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 2)

Fetch INST (PC + 4)

EXAMPLE 3-3:

INSTRUCTION PIPELINE FLOW

TCY0

TCY1

TCY2

TCY3

TCY4

TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3 (Forced NOP)

Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS40001365F-page 28

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PIC18(L)F1XK22

The CALL and GOTO instructions have the absolute

program memory address embedded into the

instruction. Since instructions are always stored on word

boundaries, the data contained in the instruction is a

word address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 3-4 shows how the

instruction GOTO 0006h is encoded in the program

memory. Program branch instructions, which encode a

relative address offset, operate in the same manner. The

offset value stored in a branch instruction represents the

number of single-word instructions that the PC will be

offset by. Section 24.0 “Instruction Set Summary”

provides further details of the instruction set.

3.2.3

INSTRUCTIONS IN PROGRAM

MEMORY

The program memory is addressed in bytes.

Instructions are stored as either two bytes or four bytes

in program memory. The Least Significant Byte (LSB)

of an instruction word is always stored in a program

memory location with an even address (LSb = 0). To

maintain alignment with instruction boundaries, the PC

increments in steps of 2 and the LSb will always read

‘0’ (see Section 3.1.1 “Program Counter”).

Figure 3-4 shows an example of how instruction words

are stored in the program memory.

FIGURE 3-4:

INSTRUCTIONS IN PROGRAM MEMORY

Word Address

LSB = 1

LSB = 0



Program Memory

^{Byte Locations}

000000h

000002h

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000014h

Instruction 1:

Instruction 2:

MOVLW

GOTO

055h

0006h

0Fh

EFh

F0h

C1h

F4h

55h

03h

00h

23h

56h

Instruction 3:

MOVFF

123h, 456h

and used by the instruction sequence. If the first word

is skipped for some reason and the second word is

executed by itself, a NOP is executed instead. This is

necessary for cases when the two-word instruction is

preceded by a conditional instruction that changes the

PC. Example 3-4 shows how this works.

3.2.4

TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word

instructions: CALL, MOVFF, GOTO and LSFR. In all

cases, the second word of the instruction always has

‘1111’ as its four Most Significant bits (MSb); the other

12 bits are literal data, usually a data memory address.

Note:

See Section 3.6 “PIC18 Instruction

Execution and the Extended Instruc-

tion Set” for information on two-word

instructions in the extended instruction set.

The use of ‘1111’ in the 4 MSbs of an instruction

specifies a special form of NOP. If the instruction is

executed in proper sequence – immediately after the

first word – the data in the second word is accessed

EXAMPLE 3-4:

CASE 1:

TWO-WORD INSTRUCTIONS

Source Code

Object Code

0110 0110 0000 0000 TSTFSZ

REG1

REG1, REG2 ; No, skip this word

; Execute this word as a NOP

; continue code

; is RAM location 0?

1100 0001 0010 0011

1111 0100 0101 0110

0010 0100 0000 0000

CASE 2:

MOVFF

ADDWF

REG3

Object Code

Source Code

TSTFSZ

0110 0110 0000 0000

1100 0001 0010 0011

1111 0100 0101 0110

0010 0100 0000 0000

REG1

; is RAM location 0?

MOVFF

REG1, REG2 ; Yes, execute this word

; 2nd word of instruction

ADDWF

REG3

; continue code

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PIC18(L)F1XK22

3.3.1

BANK SELECT REGISTER (BSR)

3.3

Data Memory Organization

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address does not need to be provided for each read or

write operation. For PIC18 devices, this is

accomplished with a RAM banking scheme. This

divides the memory space into 16 contiguous banks of

256 bytes. Depending on the instruction, each location

can be addressed directly by its full 12-bit address, or

an 8-bit low-order address and a 4-bit Bank Pointer.

Note:

The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 3.5 “Data Memory and the

Extended Instruction Set” for more

information.

The data memory in PIC18 devices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4096 bytes of data

memory. The memory space is divided into as many as

16 banks that contain 256 bytes each. Figure 3-5 and

Figure 3-6 show the data memory organization for the

PIC18(L)F1XK22 devices.

Most instructions in the PIC18 instruction set make use

of the Bank Pointer, known as the Bank Select Register

(BSR). This SFR holds the 4 Most Significant bits of a

location’s address; the instruction itself includes the

8 Least Significant bits. Only the four lower bits of the

BSR are implemented (BSR<3:0>). The upper four bits

are unused; they will always read ‘0’ and cannot be

written to. The BSR can be loaded directly by using the

MOVLBinstruction.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratchpad operations in the user’s

application. Any read of an unimplemented location will

read as ‘0’s.

The value of the BSR indicates the bank in data

memory; the 8 bits in the instruction show the location

in the bank and can be thought of as an offset from the

bank’s lower boundary. The relationship between the

BSR’s value and the bank division in data memory is

shown in Figure 3-5 and Figure 3-6.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

subsection.

Since up to 16 registers may share the same low-order

address, the user must always be careful to ensure that

the proper bank is selected before performing a data

read or write. For example, writing what should be

program data to an 8-bit address of F9h while the BSR

is 0Fh will end up resetting the program counter.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle, PIC18

devices implement an Access Bank. This is a 256-byte

memory space that provides fast access to SFRs and

the lower portion of GPR Bank 0 without using the Bank

Select Register (BSR). Section 3.3.2 “Access Bank”

provides a detailed description of the Access RAM.

While any bank can be selected, only those banks that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Even

so, the STATUS register will still be affected as if the

operation was successful. The data memory maps in

Figure 3-5 and Figure 3-6 indicate which banks are

implemented.

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source and target registers. This instruction ignores the

BSR completely when it executes. All other instructions

include only the low-order address as an operand and

must use either the BSR or the Access Bank to locate

their target registers.

DS40001365F-page 30

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 3-5:

DATA MEMORY MAP FOR PIC18(L)F13K22 DEVICES

When ‘a’ = 0:

The BSR is ignored and the

BSR<3:0>

Data Memory Map

Access Bank is used.

000h

05Fh

060h

0FFh

100h

00h

Access RAM

GPR

= 0000

= 0001

= 0010

The first 96 bytes are

general purpose RAM

(from Bank 0).

Bank 0

FFh

00h

The second 160 bytes are

Special Function Registers

(from Bank 15).

Bank 1

Bank 2

1FFh

200h

FFh

00h

FFh

00h

2FFh

300h

When ‘a’ = 1:

= 0011

The BSR specifies the Bank

used by the instruction.

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

3FFh

400h

FFh

00h

= 0100

= 0101

4FFh

500h

FFh

00h

5FFh

600h

FFh

00h

= 0110

= 0111

Access Bank

FFh

00h

6FFh

700h

00h

Access RAM Low

5Fh

Access RAM High

Unused

Read 00h

60h

FFh

00h

7FFh

800h

(SFRs)

= 1000

= 1001

FFh

8FFh

900h

FFh

00h

9FFh

A00h

FFh

00h

= 1010

= 1011

= 1100

= 1101

AFFh

B00h

FFh

00h

BFFh

C00h

FFh

00h

CFFh

D00h

FFh

00h

DFFh

E00h

FFh

00h

= 1110

= 1111

Bank 14

Bank 15

EFFh

F00h

FFh

00h

Unused

SFR⁽¹⁾

F53h

F5Fh

F60h

SFR

FFFh

FFh

Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 31

PIC18(L)F1XK22

FIGURE 3-6:

DATA MEMORY MAP FOR PIC18(L)F14K22 DEVICES

When ‘a’ = 0:

The BSR is ignored and the

BSR<3:0>

Data Memory Map

Access Bank is used.

000h

05Fh

060h

0FFh

100h

00h

Access RAM

GPR

= 0000

= 0001

= 0010

The first 96 bytes are

general purpose RAM

(from Bank 0).

Bank 0

FFh

00h

The second 160 bytes are

Special Function Registers

(from Bank 15).

GPR

Bank 1

Bank 2

1FFh

200h

FFh

00h

FFh

00h

2FFh

300h

When ‘a’ = 1:

= 0011

The BSR specifies the Bank

used by the instruction.

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

3FFh

400h

FFh

00h

= 0100

= 0101

4FFh

500h

FFh

00h

5FFh

600h

FFh

00h

= 0110

= 0111

Access Bank

FFh

00h

6FFh

700h

00h

Access RAM Low

5Fh

Access RAM High

60h

FFh

00h

7FFh

800h

(SFRs)

= 1000

= 1001

FFh

Unused

Read 00h

8FFh

900h

FFh

00h

9FFh

A00h

FFh

00h

= 1010

= 1011

= 1100

= 1101

AFFh

B00h

FFh

00h

BFFh

C00h

FFh

00h

CFFh

D00h

FFh

00h

DFFh

E00h

FFh

00h

= 1110

= 1111

Bank 14

Bank 15

EFFh

F00h

FFh

00h

Unused

SFR⁽¹⁾

F53h

F5Fh

F60h

SFR

FFFh

FFh

Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank.

DS40001365F-page 32

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 3-7:

USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

Memory

Data

(2)

(1)

From Opcode

BSR

7

0

7

0

000h

100h

00h

Bank 0

1

0

1

0

FFh

00h

Bank 1

Bank 2

(2)

Bank Select

FFh

00h

200h

300h

FFh

00h

Bank 3

through

Bank 13

FFh

00h

E00h

Bank 14

Bank 15

FFh

00h

F00h

FFFh

FFh

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 33

PIC18(L)F1XK22

3.3.2

ACCESS BANK

3.3.3

GENERAL PURPOSE REGISTER

FILE

While the use of the BSR with an embedded 8-bit

address allows users to address the entire range of

data memory, it also means that the user must always

ensure that the correct bank is selected. Otherwise,

data may be read from or written to the wrong location.

This can be disastrous if a GPR is the intended target

of an operation, but an SFR is written to instead.

Verifying and/or changing the BSR for each read or

write to data memory can become very inefficient.

PIC18 devices may have banked memory in the GPR

area. This is data RAM, which is available for use by all

instructions. GPRs start at the bottom of Bank 0

(address 000h) and grow upwards towards the bottom of

the SFR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other Resets.

3.3.4

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. SFRs start at the top of

data memory (FFFh) and extend downward to occupy

the top portion of Bank 15 (F60h to FFFh). A list of

these registers is given in Table 3-1 and Table 3-2.

To streamline access for the most commonly used data

memory locations, the data memory is configured with

an Access Bank, which allows users to access a

mapped block of memory without specifying a BSR.

The Access Bank consists of the first 96 bytes of

memory (00h-5Fh) in Bank 0 and the last 160 bytes of

memory (60h-FFh) in Block 15. The lower half is known

as the “Access RAM” and is composed of GPRs. This

upper half is also where the device’s SFRs are mapped.

These two areas are mapped contiguously in the

Access Bank and can be addressed in a linear fashion

by an 8-bit address (Figure 3-5 and Figure 3-6).

The SFRs can be classified into two sets: those

associated with the “core” device functionality (ALU,

Resets and interrupts) and those related to the

peripheral functions. The Reset and Interrupt registers

are described in their respective chapters, while the

ALU’s STATUS register is described later in this

section. Registers related to the operation of a

peripheral feature are described in the chapter for that

peripheral.

The Access Bank is used by core PIC18 instructions

that include the Access RAM bit (the ‘a’ parameter in

the instruction). When ‘a’ is equal to ‘1’, the instruction

uses the BSR and the 8-bit address included in the

opcode for the data memory address. When ‘a’ is ‘0’,

however, the instruction is forced to use the Access

Bank address map; the current value of the BSR is

ignored entirely.

The SFRs are typically distributed among the

peripherals whose functions they control. Unused SFR

locations are unimplemented and read as ‘0’s.

Using this “forced” addressing allows the instruction to

operate on a data address in a single cycle, without

updating the BSR first. For 8-bit addresses of 60h and

above, this means that users can evaluate and operate

on SFRs more efficiently. The Access RAM below 60h

is a good place for data values that the user might need

to access rapidly, such as immediate computational

results or common program variables. Access RAM

also allows for faster and more code efficient context

saving and switching of variables.

The mapping of the Access Bank is slightly different

when the extended instruction set is enabled (XINST

Configuration bit = 1). This is discussed in more detail

in Section 3.5.3 “Mapping the Access Bank in

Indexed Literal Offset Mode”.

DS40001365F-page 34

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 3-1:

SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F1XK22 DEVICES

Address

Name

Address

Name

Address

Name

Address

Name

Address

Name

(2)

FFFh

FFEh

FFDh

FFCh

FFBh

FFAh

FF9h

TOSU

TOSH

FD7h

FD6h

FD5h

FD4h

TMR0H

TMR0L

T0CON

FAFh

FAEh

FADh

FACh

FABh

FAAh

FA9h

FA8h

SPBRG

RCREG

TXREG

TXSTA

RCSTA

F87h

F86h

F85h

F84h

F83h

F82h

F81h

F80h

F7Fh

F7Eh

F7Dh

F7Ch

F7Bh

F7Ah

F79h

F78h

F77h

F76h

F75h

F74h

F73h

F72h

F71h

F70h

—

F5Fh

F5Eh

F5Dh

F5Ch

F5Bh

F5Ah

F59h

F58h

F57h

F56h

F55h

F54h

F53h

—

(2)

—

(2)

TOSL

—

(2)

STKPTR

PCLATU

PCLATH

PCL

—

(2)

FD3h OSCCON

FD2h OSCCON2

FD1h WDTCON

—

(2)

—

PORTC

PORTB

PORTA

ANSELH

ANSEL

—

(2)

EEADR

—

(2)

FF8h

FF7h

FF6h

FF5h

FF4h

FF3h

FF2h

FF1h

FF0h

FEFh

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

FD0h

FCFh

FCEh

FCDh

FCCh

FCBh

FCAh

FC9h

FC8h

RCON

TMR1H

TMR1L

T1CON

TMR2

EEDATA

—

(1)

(2)

FA7h EECON2

—

(2)

FA6h

FA5h

FA4h

FA3h

FA2h

FA1h

FA0h

F9Fh

F9Eh

F9Dh

F9Ch

EECON1

—

(2)

—

(2)

PRODH

—

(2)

PRODL

PR2

—

INTCON

INTCON2

INTCON3

T2CON

SSPBUF

SSPADD

IPR2

PIR2

PIE2

IPR1

PIR1

PIE1

IOCB

IOCA

WPUB

WPUA

SLRCON

(1)

INDF0

FC7h SSPSTAT

FC6h SSPCON1

FC5h SSPCON2

(1)

FEEh POSTINC0

(2)

FEDh POSTDEC0

—

(1)

(2)

FECh PREINC0

FC4h

FC3h

FC2h

FC1h

FC0h

FBFh

FBEh

ADRESH

ADRESL

ADCON0

ADCON1

ADCON2

CCPR1H

CCPR1L

—

(1)

(2)

FEBh PLUSW0

F9Bh OSCTUNE

—

(2)

FEAh

FE9h

FE8h

FE7h

FSR0H

FSR0L

WREG

F9Ah

F99h

F98h

F97h

F96h

F95h

F94h

F93h

F92h

F91h

F90h

F8Fh

F8Eh

F8Dh

F8Ch

F8Bh

F8Ah

F89h

F88h

—

(2)

—

(2)

—

(1)

INDF1

F6Fh SSPMASK

(1)

(2)

FE6h POSTINC1

F6Eh

—

FE5h POSTDEC1

FBDh CCP1CON

FBCh VREFCON2

FBBh VREFCON1

FBAh VREFCON0

FB9h PSTRCON

FB8h BAUDCON

FB7h PWM1CON

F6Dh CM1CON0

F6Ch CM2CON1

(1)

FE4h PREINC1

TRISC

TRISB

TRISA

(1)

FE3h PLUSW1

F6Bh CM2CON0

(2)

FE2h

FE1h

FE0h

FDFh

FSR1H

FSR1L

BSR

F6Ah

F69h

F68h

F67h

F66h

F65h

F64h

F63h

F62h

F61h

F60h

—

(2)

—

SRCON1

SRCON0

(2)

—

(1)

(2)

INDF2

—

(1)

(2)

FDEh POSTINC2

FB6h ECCP1AS

—

(2)

FDDh POSTDEC2

FB5h

FB4h

FB3h

FB2h

FB1h

FB0h

—

(1)

(2)

FDCh PREINC2

—

(1)

(2)

FDBh PLUSW2

TMR3H

TMR3L

LATC

LATB

LATA

—

(2)

FDAh

FD9h

FSR2H

FSR2L

—

(2)

T3CON

SPBRGH

—

(2)

FD8h

STATUS

—

Legend:

= Unimplemented data memory locations, read as ‘0’,

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 35

PIC18(L)F1XK22

TABLE 3-2:

File Name

TOSU

REGISTER FILE SUMMARY (PIC18(L)F1XK22)

Details

on

page:

Value on

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

—

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000 245, 25

0000 0000 245, 25

00-0 0000 245, 26

---0 0000 245, 25

0000 0000 245, 25

---0 0000 245, 48

0000 0000 245, 48

xxxx xxxx 245, 58

0000 000x 245, 62

1111 -1-1 245, 63

11-0 0-00 245, 64

TOSH

Top-of-Stack, High Byte (TOS<15:8>)

Top-of-Stack, Low Byte (TOS<7:0>)

TOSL

STKPTR

PCLATU

PCLATH

PCL

STKOVF

—

STKUNF

—

SP4

SP3

SP2

SP1

SP0

Holding Register for PC<20:16>

Holding Register for PC<15:8>

PC, Low Byte (PC<7:0>)

TBLPTRU

—

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>)

TBLPTRL

TABLAT

PRODH

PRODL

Program Memory Table Pointer, Low Byte (TBLPTR<7:0>)

Program Memory Table Latch

Product Register, High Byte

Product Register, Low Byte

INTCON

INTCON2

INTCON3

INDF0

GIE/GIEH

RABPU

INT2IP

PEIE/GIEL

INTEDG0

INT1IP

TMR0IE

INTEDG1

—

INT0IE

INTEDG2

INT2IE

RABIE

—

TMR0IF

TMR0IP

—

INT0IF

—

RABIF

RABIP

INT1IF

INT1IE

INT2IF

Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)

N/A

245, 41

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)

PREINC0

PLUSW0

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value

of FSR0 offset by W

N/A

245, 41

FSR0H

FSR0L

WREG

INDF1

—

Indirect Data Memory Address Pointer 0, High Byte

---- 0000 245, 41

xxxx xxxx 245, 41

xxxx xxxx 245

Indirect Data Memory Address Pointer 0, Low Byte

Working Register

Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)

N/A

245, 41

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)

PREINC1

PLUSW1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value

of FSR1 offset by W

N/A

245, 41

FSR1H

FSR1L

BSR

—

Indirect Data Memory Address Pointer 1, High Byte

---- 0000 246, 41

xxxx xxxx 246, 41

---- 0000 246, 30

Indirect Data Memory Address Pointer 1, Low Byte

—

Bank Select Register

INDF2

Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)

N/A

246, 41

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)

PREINC2

PLUSW2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value

of FSR2 offset by W

N/A

246, 41

FSR2H

FSR2L

STATUS

—

Indirect Data Memory Address Pointer 2, High Byte

---- 0000 246, 41

xxxx xxxx 246, 41

---x xxxx 246, 39

Indirect Data Memory Address Pointer 2, Low Byte

—

N

OV

Z

DC

C

Legend:

x= unknown, u= unchanged, —= unimplemented, q= value depends on condition

Note 1:

The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See

Section 22.4 “Brown-out Reset (BOR)”.

2:

3:

The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is

read-only.

Unimplemented, read as ‘1’.

DS40001365F-page 36

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 3-2:

REGISTER FILE SUMMARY (PIC18(L)F1XK22) (CONTINUED)

Details

on

page:

Value on

POR, BOR

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMR0H

Timer0 Register, High Byte

Timer0 Register, Low Byte

0000 0000 246, 92

xxxx xxxx 246, 92

1111 1111 246, 91

0011 qq00 246, 17

---- -10x 246, 18

--- ---0 246, 260

TMR0L

T0CON

TMR0ON

IDLEN

—

T08BIT

IRCF2

—

T0CS

IRCF1

—

T0SE

IRCF0

—

PSA

OSTS

—

T0PS2

HFIOFS

PRI_SD

—

T0PS1

SCS1

HFIOFL

—

T0PS0

SCS0

OSCCON

OSCCON2

WDTCON

LFIOFS

SWDTEN

—

237,

0q-1 11q0

246, 71

RCON

IPEN

SBOREN⁽¹⁾

—

RI

TO

PD

POR

BOR

TMR1H

TMR1L

T1CON

TMR2

Timer1 Register, High Byte

Timer1 Register, Low Bytes

xxxx xxxx 246, 94

RD16

T1RUN

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR2ON

TMR1CS

T2CKPS1

TMR1ON 0000 0000 246, 94

0000 0000 246, 100

Timer2 Register

PR2

Timer2 Period Register

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0

1111 1111 246, 100

T2CON

—

T2CKPS0 -000 0000 246, 100

246,

xxxx xxxx

128, 130

SSPBUF

SSPADD

SSP Receive Buffer/Transmit Register

SSP Address Register in I²C Slave Mode. SSP Baud Rate Reload Register in I²C Master Mode.

0000 0000 246, 147

246,

128, 137

SSPSTAT

SSPCON1

SMP

CKE

D/A

P

S

R/W

UA

BF

0000 0000

246,

128, 138

WCOL

GCEN

SSPOV

SSPEN

ACKDT

CKP

SSPM3

RCEN

SSPM2

PEN

SSPM1

RSEN

SSPM0

SEN

SSPCON2

ADRESH

ADRESL

ACKSTAT

ACKEN

0000 0000 246, 139

xxxx xxxx 247, 197

A/D Result Register, High Byte

A/D Result Register, Low Byte

—

ADCON0

CHS3

—

CHS2

—

CHS1

PVCFG1

ACQT0

CHS0

PVCFG0

ADCS2

GO/DONE

NVCFG1

ADCS1

ADON

--00 0000 247, 203

NVCFG0 ---- 0000 247, 204

ADCON1

ADCON2

CCPR1H

CCPR1L

CCP1CON

ADFM

ACQT2

ACQT1

ADCS0

0-00 0000 247, 205

xxxx xxxx 247, 126

Capture/Compare/PWM Register 1, High Byte

Capture/Compare/PWM Register 1, Low Byte

P1M1

P1M0

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

—

CCP1M0 0000 0000 247, 106

---0 0000 247, 236

DAC1R<4:0>

VREFCON2

VREFCON1

—

D1EN

D1LPS

DAC1OE

---

D1PSS<1:0>

D1NSS

000- 00-0 247, 235

FVR1EN

—

FVR1ST

—

FVR1S<1:0>

—

STRC

—

0001 ---- 247, 232

---0 0001 247, 123

0100 0-00 247, 181

0000 0000 247, 122

VREFCON0

PSTRCON

BAUDCON

PWM1CON

ECCP1AS

TMR3H

—

STRSYNC

CKTXP

STRD

STRB

WUE

STRA

ABDEN

PDC0

ABDOVF

PRSEN

ECCPASE

RCIDL

PDC6

DTRXP

PDC5

BRG16

PDC3

PDC4

PDC2

PSSAC0

PDC1

PSSBD1

ECCPAS2

ECCPAS1

ECCPAS0

PSSAC1

PSSBD0 0000 0000 247, 118

xxxx xxxx 247, 102

Timer3 Register, High Byte

Timer3 Register, Low Byte

TMR3L

xxxx xxxx 247, 102

RD16

—

T3CKPS1

T3CKPS0

T3CCP1

T3SYNC

TMR3CS

TMR3ON 0-00 0000

247, 102

T3CON

Legend:

x= unknown, u= unchanged, —= unimplemented, q= value depends on condition

Note 1:

The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See

Section 22.4 “Brown-out Reset (BOR)”.

2:

3:

The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is

read-only.

Unimplemented, read as ‘1’.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 37

PIC18(L)F1XK22

TABLE 3-2:

REGISTER FILE SUMMARY (PIC18(L)F1XK22) (CONTINUED)

Details

on

page:

Value on

POR, BOR

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPBRGH

SPBRG

RCREG

TXREG

TXSTA

EUSART Baud Rate Generator Register, High Byte

EUSART Baud Rate Generator Register, Low Byte

EUSART Receive Register

0000 0000 247, 182

0000 0000 247, 175

0000 0000 247, 172

0000 0010 247, 179

0000 000x 247, 180

247, 45,

EUSART Transmit Register

CSRC

SPEN

TX9

RX9

TXEN

SREN

SYNC

CREN

SENDB

ADDEN

BRGH

FERR

TRMT

OERR

TX9D

RX9D

RCSTA

EEADR

EEADR7

EEADR6

EEADR5

EEADR4

EEADR3

EEADR2

EEADR1

EEADR0 0000 0000

54

247, 45,

54

EEDATA

EECON2

EECON1

EEPROM Data Register

EEPROM Control Register 2 (not a physical register)

0000 0000

247, 45,

54

0000 0000

247, 45,

54

EEPGD

CFGS

—

FREE

WRERR

WREN

WR

RD

xx-0 x000

IPR2

OSCFIP

OSCFIF

OSCFIE

—

C1IP

C1IF

C2IP

C2IF

EEIP

EEIF

BCLIP

BCLIF

BCLIE

SSPIP

SSPIF

SSPIE

TUN3

TRISC3

—

TMR3IP

TMR3IF

TMR3IE

TMR2IP

TMR2IF

TMR2IE

TUN1

TRISC1

—

1111 1-1- 248, 70

0000 0-0- 248, 66

0000 0-0- 248, 68

-111 1111 248, 69

-000 0000 248, 65

-000 0000 248, 67

0000 0000 248, 19

1111 1111 248, 84

1111 ---- 248, 80

--11 1111 248, 75

xxxx xxxx 248, 85

xxxx ---- 248, 80

--xx -xxx 248, 76

xxxx xxxx 248, 84

xxxx ---- 248, 80

--xx xxxx 248, 75

---- 1111 248, 89

1111 1111 248, 88

0000 ---- 248, 81

--00 0000 248, 76

1111 ---- 248, 81

--11 1111 245, 76

---- -111 248, 90

1111 1111 248, 146

0000 0000 248, 216

PIR2

PIE2

C1IE

C2IE

EEIE

—

IPR1

ADIP

ADIF

ADIE

PLLEN

TRISC6

TRISB6

—

RCIP

TXIP

CCP1IP

CCP1IF

CCP1IE

TUN2

TRISC2

—

TMR1IP

TMR1IF

TMR1IE

TUN0

TRISC0

—

PIR1

—

RCIF

TXIF

PIE1

—

RCIE

TXIE

OSCTUNE

TRISC

TRISB

INTSRC

TRISC7

TRISB7

—

TUN5

TRISC5

TRISB5

TRISA5

LATC5

LATB5

LATA5

RC5

TUN4

TRISC4

TRISB4

TRISA4

LATC4

LATB4

LATA4

RC4

(3)

TRISA

—

TRISA2

LATC2

—

TRISA1

LATC1

—

TRISA0

LATC0

—

LATC

LATC7

LATB7

—

LATC6

LATB6

—

LATC3

—

LATB

LATA

—

LATA2

RC2

LATA1

RC1

LATA0

RC0

PORTC

PORTB

PORTA

ANSELH

ANSEL

IOCB

RC7

RC6

RC3

RB7

RB6

RB5

RB4

—

RA5

RA4

RA3⁽²⁾

ANS11

ANS3

—

RA2

RA1

RA0

—

ANS10

ANS2

—

ANS9

ANS1

—

ANS8

ANS0

—

ANS7

IOCB7

—

ANS6

IOCB6

—

ANS5

IOCB5

IOCA5

WPUB5

WPUA5

—

ANS4

IOCB4

IOCA4

WPUB4

WPUA4

—

IOCA

IOCA3

—

IOCA2

—

IOCA1

—

IOCA0

—

WPUB

WPUA

SLRCON

SSPMSK

CM1CON0

CM2CON1

CM2CON0

SRCON1

SRCON0

WPUB7

—

WPUB6

—

WPUA3

—

WPUA2

SLRC

MSK2

C1R

WPUA1

SLRB

MSK1

C1CH1

C1SYNC

C2CH1

SRRC2E

SRPS

WPUA0

SLRA

MSK0

C1CH0

—

MSK7

C1ON

MC1OUT

C2ON

SRSPE

SRLEN

MSK6

C1OUT

MC2OUT

C2OUT

SRSCKE

SRCLK2

MSK5

C1OE

C1RSEL

C2OE

SRSC2E

SRCLK1

MSK4

C1POL

C2RSEL

C2POL

SRSC1E

SRCLK0

MSK3

C1SP

C1HYS

C2SP

SRRPE

SRQEN

C2HYS

C2R

C2SYNC 0000 0000 248, 220

C2CH0 0000 0000 248, 217

SRRC1E 0000 0000 248, 230

SRPR 0000 0000 248, 229

SRRCKE

SRNQEN

Legend:

x= unknown, u= unchanged, —= unimplemented, q= value depends on condition

Note 1:

The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See

Section 22.4 “Brown-out Reset (BOR)”.

2:

3:

The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is

read-only.

Unimplemented, read as ‘1’.

DS40001365F-page 38

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PIC18(L)F1XK22

It is recommended that only BCF, BSF, SWAPF, MOVFF

and MOVWFinstructions are used to alter the STATUS

register, because these instructions do not affect the Z,

C, DC, OV or N bits in the STATUS register.

3.3.5

STATUS REGISTER

The STATUS register, shown in Register 3-2, contains

the arithmetic status of the ALU. As with any other SFR,

it can be the operand for any instruction.

For other instructions that do not affect Status bits, see

the instruction set summaries in Table 24-2 and

Table 24-3.

If the STATUS register is the destination for an

instruction that affects the Z, DC, C, OV or N bits, the

results of the instruction are not written; instead, the

STATUS register is updated according to the

instruction performed. Therefore, the result of an

instruction with the STATUS register as its destination

may be different than intended. As an example, CLRF

STATUS will set the Z bit and leave the remaining

Status bits unchanged (‘000u u1uu’).

Note:

The C and DC bits operate as the borrow

and digit borrow bits, respectively, in

subtraction.

REGISTER 3-2:

STATUS: STATUS REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

N

R/W-x

OV

R/W-x

Z

R/W-x

DC⁽¹⁾

R/W-x

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4

Unimplemented: Read as ‘0’

N: Negative bit

This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative

(ALU MSB = 1).

1= Result was negative

0= Result was positive

bit 3

bit 2

OV: Overflow bit

This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit

magnitude which causes the sign bit (bit 7 of the result) to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

bit 1

bit 0

DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 39

PIC18(L)F1XK22

Purpose Register File”) or a location in the Access

Bank (Section 3.3.2 “Access Bank”) as the data

source for the instruction.

3.4

Data Addressing Modes

Note:

The execution of some instructions in the

core PIC18 instruction set are changed

when the PIC18 extended instruction set is

enabled. See Section 3.5 “Data Memory

and the Extended Instruction Set” for

more information.

The Access RAM bit ‘a’ determines how the address is

interpreted. When ‘a’ is ‘1’, the contents of the BSR

(Section 3.3.1 “Bank Select Register (BSR)”) are

used with the address to determine the complete 12-bit

address of the register. When ‘a’ is ‘0’, the address is

interpreted as being a register in the Access Bank.

Addressing that uses the Access RAM is sometimes

also known as Direct Forced Addressing mode.

While the program memory can be addressed in only

one way – through the program counter – information

in the data memory space can be addressed in several

ways. For most instructions, the addressing mode is

fixed. Other instructions may use up to three modes,

depending on which operands are used and whether or

not the extended instruction set is enabled.

A few instructions, such as MOVFF, include the entire

12-bit address (either source or destination) in their

opcodes. In these cases, the BSR is ignored entirely.

The destination of the operation’s results is determined

by the destination bit ‘d’. When ‘d’ is ‘1’, the results are

stored back in the source register, overwriting its

original contents. When ‘d’ is ‘0’, the results are stored

in the W register. Instructions without the ‘d’ argument

have a destination that is implicit in the instruction; their

destination is either the target register being operated

on or the W register.

The addressing modes are:

• Inherent

• Literal

• Direct

• Indirect

An additional addressing mode, Indexed Literal Offset,

is available when the extended instruction set is

enabled (XINST Configuration bit = 1). Its operation is

discussed in greater detail in Section 3.5.1 “Indexed

Addressing with Literal Offset”.

3.4.3

INDIRECT ADDRESSING

Indirect addressing allows the user to access a location

in data memory without giving a fixed address in the

instruction. This is done by using File Select Registers

(FSRs) as pointers to the locations which are to be read

or written. Since the FSRs are themselves located in

RAM as Special File Registers, they can also be

directly manipulated under program control. This

makes FSRs very useful in implementing data

structures, such as tables and arrays in data memory.

3.4.1

INHERENT AND LITERAL

ADDRESSING

Many PIC18 control instructions do not need any

argument at all; they either perform an operation that

globally affects the device or they operate implicitly on

one register. This addressing mode is known as

Inherent Addressing. Examples include SLEEP, RESET

and DAW.

The registers for indirect addressing are also

implemented with Indirect File Operands (INDFs) that

permit automatic manipulation of the pointer value with

auto-incrementing, auto-decrementing or offsetting

with another value. This allows for efficient code, using

loops, such as the example of clearing an entire RAM

bank in Example 3-5.

Other instructions work in a similar way but require an

additional explicit argument in the opcode. This is

known as Literal Addressing mode because they

require some literal value as an argument. Examples

include ADDLWand MOVLW, which respectively, add or

move a literal value to the W register. Other examples

include CALL and GOTO, which include a 20-bit

program memory address.

EXAMPLE 3-5:

HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

FSR0, 100h ;

3.4.2

DIRECT ADDRESSING

LFSR

POSTINC0

; Clear INDF

Direct addressing specifies all or part of the source

and/or destination address of the operation within the

opcode itself. The options are specified by the

arguments accompanying the instruction.

; register then

; inc pointer

; All done with

; Bank1?

; NO, clear next

; YES, continue

BTFSS

BRA

FSR0H, 1

oriented instructions use some version of direct

addressing by default. All of these instructions include

some 8-bit literal address as their Least Significant

Byte. This address specifies either a register address in

one of the banks of data RAM (Section 3.3.3 “General

CONTINUE

DS40001365F-page 40

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PIC18(L)F1XK22

3.4.3.1

FSR Registers and the INDF

Operand

3.4.3.2

FSR Registers and POSTINC,

POSTDEC, PREINC and PLUSW

At the core of indirect addressing are three sets of

registers: FSR0, FSR1 and FSR2. Each represents a

pair of 8-bit registers, FSRnH and FSRnL. Each FSR

pair holds a 12-bit value, therefore the four upper bits

of the FSRnH register are not used. The 12-bit FSR

value can address the entire range of the data memory

in a linear fashion. The FSR register pairs, then, serve

as pointers to data memory locations.

In addition to the INDF operand, each FSR register pair

also has four additional indirect operands. Like INDF,

these are “virtual” registers which cannot be directly

read or written. Accessing these registers actually

accesses the location to which the associated FSR

register pair points, and also performs a specific action

on the FSR value. They are:

• POSTDEC: accesses the location to which the

FSR points, then automatically decrements the

FSR by 1 afterwards

Indirect addressing is accomplished with a set of

Indirect File Operands, INDF0 through INDF2. These

can be thought of as “virtual” registers: they are

mapped in the SFR space but are not physically

implemented. Reading or writing to a particular INDF

register actually accesses its corresponding FSR

register pair. A read from INDF1, for example, reads

the data at the address indicated by FSR1H:FSR1L.

Instructions that use the INDF registers as operands

actually use the contents of their corresponding FSR as

a pointer to the instruction’s target. The INDF operand

is just a convenient way of using the pointer.

• POSTINC: accesses the location to which the

FSR points, then automatically increments the

FSR by 1 afterwards

• PREINC: automatically increments the FSR by 1,

then uses the location to which the FSR points in

the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses

the location to which the result points in the

operation.

Because indirect addressing uses a full 12-bit address,

data RAM banking is not necessary. Thus, the current

contents of the BSR and the Access RAM bit have no

effect on determining the target address.

In this context, accessing an INDF register uses the

value in the associated FSR register without changing

it. Similarly, accessing a PLUSW register gives the

FSR value an offset by that in the W register; however,

neither W nor the FSR is actually changed in the

operation. Accessing the other virtual registers

changes the value of the FSR register.

FIGURE 3-8:

INDIRECT ADDRESSING

000h

Using an instruction with one of the

indirect addressing registers as the

operand....

Bank 0

Bank 1

ADDWF, INDF1, 1

100h

200h

300h

Bank 2

FSR1H:FSR1L

...uses the 12-bit address stored in

the FSR pair associated with that

register....

7

0

7

0

Bank 3

through

Bank 13

x x x x 1 1 1 0

1 1 0 0 1 1 0 0

...to determine the data memory

location to be used in that operation.

E00h

In this case, the FSR1 pair contains

ECCh. This means the contents of

location ECCh will be added to that

of the W register and stored back in

ECCh.

Bank 14

Bank 15

F00h

FFFh

Data Memory

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DS40001365F-page 41

PIC18(L)F1XK22

Operations on the FSRs with POSTDEC, POSTINC

and PREINC affect the entire register pair; that is,

rollovers of the FSRnL register from FFh to 00h carry

over to the FSRnH register. On the other hand, results

of these operations do not change the value of any

flags in the STATUS register (e.g., Z, N, OV, etc.).

3.5.1

INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of indirect addressing using the FSR2

register pair within Access RAM. Under the proper

conditions, instructions that use the Access Bank – that

is, most bit-oriented and byte-oriented instructions –

can invoke a form of indexed addressing using an

offset specified in the instruction. This special

addressing mode is known as Indexed Addressing with

Literal Offset, or Indexed Literal Offset mode.

The PLUSW register can be used to implement a form

of indexed addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

When using the extended instruction set, this

addressing mode requires the following:

3.4.3.3

Operations by FSRs on FSRs

• The use of the Access Bank is forced (‘a’ = 0) and

• The file address argument is less than or equal to

5Fh.

Indirect addressing operations that target other FSRs

or virtual registers represent special cases. For

example, using an FSR to point to one of the virtual

registers will not result in successful operations. As a

specific case, assume that FSR0H:FSR0L contains

FE7h, the address of INDF1. Attempts to read the

value of the INDF1 using INDF0 as an operand will

return 00h. Attempts to write to INDF1 using INDF0 as

the operand will result in a NOP.

Under these conditions, the file address of the

instruction is not interpreted as the lower byte of an

address (used with the BSR in direct addressing), or as

an 8-bit address in the Access Bank. Instead, the value

is interpreted as an offset value to an Address Pointer,

specified by FSR2. The offset and the contents of

FSR2 are added to obtain the target address of the

operation.

On the other hand, using the virtual registers to write to

an FSR pair may not occur as planned. In these cases,

the value will be written to the FSR pair but without any

incrementing or decrementing. Thus, writing to either

the INDF2 or POSTDEC2 register will write the same

value to the FSR2H:FSR2L.

3.5.2

INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use direct

addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set.

Instructions that only use Inherent or Literal Addressing

modes are unaffected.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, particularly if their code

uses indirect addressing.

Additionally, byte-oriented and bit-oriented instructions

are not affected if they do not use the Access Bank

(Access RAM bit is ‘1’), or include a file address of 60h

or above. Instructions meeting these criteria will

continue to execute as before. A comparison of the

different possible addressing modes when the

extended instruction set is enabled is shown in

Figure 3-9.

Similarly, operations by indirect addressing are generally

permitted on all other SFRs. Users should exercise the

appropriate caution that they do not inadvertently change

settings that might affect the operation of the device.

3.5

Data Memory and the Extended

Instruction Set

Enabling the PIC18 extended instruction set (XINST

Configuration bit = 1) significantly changes certain

aspects of data memory and its addressing.

Specifically, the use of the Access Bank for many of the

core PIC18 instructions is different; this is due to the

introduction of a new addressing mode for the data

memory space.

Those who desire to use byte-oriented or bit-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 24.2.1

“Extended Instruction Syntax”.

What does not change is just as important. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect addressing

with FSR0 and FSR1 also remain unchanged.

DS40001365F-page 42

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PIC18(L)F1XK22

FIGURE 3-9:

COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

000h

When ‘a’ = 0 and f  60h:

060h

The instruction executes in

Bank 0

Direct Forced mode. ‘f’ is

interpreted as a location in the

Access RAM between 060h

and 0FFh. This is the same as

locations F60h to FFFh

(Bank 15) of data memory.

100h

00h

60h

Bank 1

through

Bank 14

Valid range

for ‘f’

Locations below 60h are not

available in this addressing

mode.

FFh

Access RAM

F00h

Bank 15

SFRs

F60h

FFFh

Data Memory

When ‘a’ = 0 and f5Fh:

000h

060h

100h

The instruction executes in

Indexed Literal Offset mode. ‘f’

is interpreted as an offset to the

address value in FSR2. The

two are added together to

obtain the address of the target

register for the instruction. The

address can be anywhere in

the data memory space.

Bank 0

001001da ffffffff

Bank 1

through

Bank 14

FSR2H

FSR2L

F00h

F60h

Note that in this mode, the

correct syntax is now:

Bank 15

SFRs

ADDWF [k], d

where ‘k’ is the same as ‘f’.

FFFh

Data Memory

BSR

000h

060h

100h

00000000

When ‘a’ = 1 (all values of f):

The instruction executes in

Direct mode (also known as

Direct Long mode). ‘f’ is

interpreted as a location in

one of the 16 banks of the data

memory space. The bank is

designated by the Bank Select

Register (BSR). The address

can be in any implemented

bank in the data memory

space.

Bank 0

001001da ffffffff

Bank 1

through

Bank 14

F00h

F60h

Bank 15

SFRs

FFFh

Data Memory

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PIC18(L)F1XK22

Remapping of the Access Bank applies only to

operations using the Indexed Literal Offset mode.

Operations that use the BSR (Access RAM bit is ‘1’) will

continue to use direct addressing as before.

3.5.3

MAPPING THE ACCESS BANK IN

INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode

effectively changes how the first 96 locations of Access

RAM (00h to 5Fh) are mapped. Rather than containing

just the contents of the bottom section of Bank 0, this

mode maps the contents from a user defined “window”

that can be located anywhere in the data memory

space. The value of FSR2 establishes the lower

boundary of the addresses mapped into the window,

while the upper boundary is defined by FSR2 plus 95

(5Fh). Addresses in the Access RAM above 5Fh are

mapped as previously described (see Section 3.3.2

“Access Bank”). An example of Access Bank

remapping in this addressing mode is shown in

Figure 3-10.

3.6

PIC18 Instruction Execution and

the Extended Instruction Set

Enabling the extended instruction set adds eight

additional commands to the existing PIC18 instruction

set. These instructions are executed as described in

Section 24.2 “Extended Instruction Set”.

FIGURE 3-10:

REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET

ADDRESSING

Example Situation:

000h

ADDWF f, d, a

FSR2H:FSR2L = 120h

Bank 0

Locations in the region

from the FSR2 pointer

(120h) to the pointer plus

05Fh (17Fh) are mapped

to the bottom of the

Access RAM (000h-05Fh).

100h

120h

17Fh

Bank 1

Window

00h

Bank 1

Bank 1 “Window”

200h

5Fh

60h

Special File Registers at

F60h through FFFh are

mapped to 60h through

FFh, as usual.

Bank 2

through

Bank 14

SFRs

Bank 0 addresses below

5Fh can still be addressed

by using the BSR.

FFh

Access Bank

F00h

Bank 15

SFRs

F60h

FFFh

Data Memory

DS40001365F-page 44

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PIC18(L)F1XK22

4.1

Table Reads and Table Writes

4.0

FLASH PROGRAM MEMORY

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

• Table Read (TBLRD)

• Table Write (TBLWT)

A read from program memory is executed one byte at

a time. A write to program memory is executed on

blocks of 16 or 8 bytes at a time depending on the

specific device (See Table 4-1). Program memory is

erased in blocks of 64 bytes at a time. The difference

between the write and erase block sizes requires from

4 to 8 block writes to restore the contents of a single

block erase. A Bulk Erase operation can not be issued

from user code.

The program memory space is 16-bit wide, while the

data RAM space is 8-bit wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

The table read operation retrieves one byte of data

directly from program memory and places it into the

TABLAT register. Figure 4-1 shows the operation of a

table read.

TABLE 4-1:

WRITE/ERASE BLOCK SIZES

The table write operation stores one byte of data from the

TABLAT register into a write block holding register. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 4.5 “Writing

to Flash Program Memory”. Figure 4-2 shows the

operation of a table write with program memory and data

RAM.

Write Block

Size (bytes)

Erase Block

Size (bytes)

Device

PIC18(L)F13K22

PIC18(L)F14K22

8

64

16

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

Table operations work with byte entities. Tables

containing data, rather than program instructions, are

not required to be word-aligned. Therefore, a table can

start and end at any byte address. If a table write is being

used to write executable code into program memory,

program instructions will need to be word-aligned.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

FIGURE 4-1:

TABLE READ OPERATION

Instruction: TBLRD*

Program Memory

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer register points to a byte in program memory.

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FIGURE 4-2:

TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Holding Registers

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR<MSBs>)

Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL

actually point to an address within the write block holding registers. The MSBs of the Table Pointer

determine where the write block will eventually be written. The process for writing the holding registers

to the program memory array is discussed in Section 4.5 “Writing to Flash Program Memory”.

The FREE bit allows the program memory erase

operation. When FREE is set, an erase operation is

initiated on the next WR command. When FREE is

clear, only writes are enabled.

4.2

Control Registers

Several control registers are used in conjunction with

the TBLRDand TBLWTinstructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

The WREN bit, when set, will allow a write operation.

The WREN bit is clear on power-up.

The WRERR bit is set by hardware when the WR bit is

set and cleared when the internal programming timer

expires and the write operation is complete.

4.2.1

EECON1 AND EECON2 REGISTERS

Note:

During normal operation, the WRERR is

read as ‘1’. This can indicate that a write

operation was prematurely terminated by

The EECON1 register (Register 4-1) is the control

register for memory accesses. The EECON2 register is

not a physical register; it is used exclusively in the

memory write and erase sequences. Reading

EECON2 will read all ‘0’s.

a

Reset, or

a write operation was

attempted improperly.

The WR control bit initiates write operations. The WR

bit cannot be cleared, only set, by firmware. Then WR

bit is cleared by hardware at the completion of the write

operation.

The EEPGD control bit determines if the access will be

a program or data EEPROM memory access. When

EEPGD is clear, any subsequent operations will

operate on the data EEPROM memory. When EEPGD

is set, any subsequent operations will operate on the

program memory.

Note:

The EEIF interrupt flag bit of the PIR2

register is set when the write is complete.

The EEIF flag stays set until cleared by

firmware.

The CFGS control bit determines if the access will be

to the Configuration/Calibration registers or to program

memory/data EEPROM memory. When CFGS is set,

subsequent operations will operate on Configuration

registers regardless of EEPGD (see Section 23.0

“Special Features of the CPU”). When CFGS is clear,

memory selection access is determined by EEPGD.

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REGISTER 4-1:

R/W-x

EECON1: DATA EEPROM CONTROL 1 REGISTER

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

S = Bit can be set by software, but not cleared

-n = Value at POR ‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

EEPGD: Flash Program or Data EEPROM Memory Select bit

1= Access Flash program memory

0= Access data EEPROM memory

CFGS: Flash Program/Data EEPROM or Configuration Select bit

1= Access Configuration registers

0= Access Flash program or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as ‘0’

FREE: Flash Row (Block) Erase Enable bit

1= Erase the program memory block addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write-only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit⁽¹⁾

1= A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0= The write operation completed

bit 2

bit 1

WREN: Flash Program/Data EEPROM Write Enable bit

1= Allows write cycles to Flash program/data EEPROM

0= Inhibits write cycles to Flash program/data EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) by software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only

be set (not cleared) by software. RD bit cannot be set when EEPGD = 1or CFGS = 1.)

0= Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the

error condition.

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4.2.2

TABLAT – TABLE LATCH REGISTER

4.2.4

TABLE POINTER BOUNDARIES

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch register is used to

hold 8-bit data during data transfers between program

memory and data RAM.

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRDis executed, all 22 bits of the TBLPTR

determine which byte is read from program memory

directly into the TABLAT register.

4.2.3

TBLPTR – TABLE POINTER

REGISTER

When a TBLWT is executed the byte in the TABLAT

register is written, not to Flash memory but, to a holding

register in preparation for a program memory write. The

holding registers constitute a write block which varies

depending on the device (See Table 4-1).The 3, 4, or 5

LSbs of the TBLPTRL register determine which specific

address within the holding register block is written to.

The MSBs of the Table Pointer have no effect during

TBLWToperations.

The Table Pointer (TBLPTR) register addresses a byte

within the program memory. The TBLPTR is comprised

of three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL).

These

three

registers join to form a 22-bit wide pointer. The low-

order 21 bits allow the device to address up to 2 Mbytes

of program memory space. The 22nd bit allows access

to the device ID, the user ID and the Configuration bits.

When a program memory write is executed the entire

holding register block is written to the Flash memory at

the address determined by the MSbs of the TBLPTR.

The 3, 4, or 5 LSBs are ignored during Flash memory

writes. For more detail, see Section 4.5 “Writing to

Flash Program Memory”.

The Table Pointer register, TBLPTR, is used by the

TBLRDand TBLWTinstructions. These instructions can

update the TBLPTR in one of four ways based on the

table operation. These operations are shown in

Table 4-2. These operations on the TBLPTR affect only

the low-order 21 bits.

When an erase of program memory is executed, the

16 MSbs of the Table Pointer register (TBLPTR<21:6>)

point to the 64-byte block that will be erased. The Least

Significant bits (TBLPTR<5:0>) are ignored.

Figure 4-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 4-2:

Example

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLRD*-

TBLWT*-

TBLRD+*

TBLWT+*

FIGURE 4-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

21

16 15

TBLPTRH

8

7

TBLPTRL

0

TBLPTRU

TABLE ERASE/WRITE

TBLPTR<21:n+1>

TABLE WRITE

TBLPTR<n:0>

(1)

TABLE READ – TBLPTR<21:0>

Note 1: n = 3, 4, 5, or 6 for block sizes of 8, 16, 32 or 64 bytes, respectively.

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The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 4-4

shows the interface between the internal program

memory and the TABLAT.

4.3

Reading the Flash Program

Memory

The TBLRD instruction retrieves data from program

memory and places it into data RAM. Table reads from

program memory are performed one byte at a time.

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next table read operation.

FIGURE 4-4:

READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

(Odd Byte Address)

TBLPTR = xxxxx1

TBLPTR = xxxxx0

Instruction Register

(IR)

TABLAT

Read Register

FETCH

TBLRD

EXAMPLE 4-1:

READING A FLASH PROGRAM MEMORY WORD

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; Load TBLPTR with the base

; address of the word

READ_WORD

TBLRD*+

MOVF

MOVWF

TBLRD*+

MOVFW

MOVF

; read into TABLAT and increment

; get data

TABLAT, W

WORD_EVEN

; read into TABLAT and increment

; get data

TABLAT, W

WORD_ODD

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4.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

4.4

Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer, or through

ICSP control, can larger blocks of program memory be

bulk erased. Word erase in the Flash array is not

supported.

The sequence of events for erasing a block of internal

program memory is:

1. Load Table Pointer register with address of

block being erased.

When initiating an erase sequence from the

Microcontroller itself, a block of 64 bytes of program

memory is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased. The

TBLPTR<5:0> bits are ignored.

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable interrupts.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the Flash

program memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the block erase

cycle.

The write initiate sequence for EECON2, shown as

steps 4 through 6 in Section 4.4.1 “Flash Program

Memory Erase Sequence”, is used to guard against

accidental writes. This is sometimes referred to as a

long write.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Re-enable interrupts.

A long write is necessary for erasing the internal

Flash. Instruction execution is halted during the long

write cycle. The long write is terminated by the internal

programming timer.

EXAMPLE 4-2:

ERASING A FLASH PROGRAM MEMORY BLOCK

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; load TBLPTR with the base

; address of the memory block

ERASE_BLOCK

BSF

BCF

BSF

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

EECON1, FREE

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

INTCON, GIE

; point to Flash program memory

; access Flash program memory

; enable write to memory

; enable block Erase operation

; disable interrupts

BCF

Required

Sequence

MOVLW

MOVWF

MOVLW

MOVWF

BSF

; write 55h

; write 0AAh

; start erase (CPU stall)

; re-enable interrupts

BSF

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The long write is necessary for programming the

internal Flash. Instruction execution is halted during a

long write cycle. The long write will be terminated by

the internal programming timer.

4.5

Writing to Flash Program Memory

The programming block size is 8 or 16 bytes,

depending on the device (See Table 4-1). Word or byte

programming is not supported.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are only as many holding registers as there are bytes

in a write block (See Table 4-1).

Note:

The default value of the holding registers on

device Resets and after write operations is

FFh. A write of FFh to a holding register

does not modify that byte. This means that

individual bytes of program memory may

be modified, provided that the change does

not attempt to change any bit from a ‘0’ to a

‘1’. When modifying individual bytes, it is

not necessary to load all holding registers

before executing a long write operation.

Since the Table Latch (TABLAT) is only a single byte,

the TBLWTinstruction may need to be executed 8, or 16

times, depending on the device, for each programming

operation. All of the table write operations will

essentially be short writes because only the holding

registers are written. After all the holding registers have

been written, the programming operation of that block

of memory is started by configuring the EECON1

register for a program memory write and performing the

long write sequence.

FIGURE 4-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

8

(1)

TBLPTR = xxxx00

TBLPTR = xxxx01

TBLPTR = xxxx02

TBLPTR = xxxxYY

Holding Register

Program Memory

Note 1: YY = x7 or xF for 8 or 16 byte write blocks, respectively.

8. Disable interrupts.

4.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.

The sequence of events for programming an internal

program memory location should be:

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for duration of the write (about

2 ms using internal timer).

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

13. Re-enable interrupts.

3. Load Table Pointer register with address being

erased.

14. Repeat steps 6 to 13 for each block until all 64

bytes are written.

4. Execute the block erase procedure.

15. Verify the memory (table read).

5. Load Table Pointer register with address of first

byte being written.

This procedure will require about 6 ms to update each

write block of memory. An example of the required code

is given in Example 4-3.

6. Write the 8 or 16 byte block into the holding

registers with auto-increment.

7. Set the EECON1 register for the write operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

Note:

Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the bytes in the

holding registers.

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EXAMPLE 4-3:

WRITING TO FLASH PROGRAM MEMORY

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

D'64’

COUNTER

BUFFER_ADDR_HIGH

FSR0H

BUFFER_ADDR_LOW

FSR0L

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; number of bytes in erase block

; point to buffer

; Load TBLPTR with the base

; address of the memory block

READ_BLOCK

TBLRD*+

MOVF

MOVWF

DECFSZ

BRA

; read into TABLAT, and inc

; get data

; store data

; done?

TABLAT, W

POSTINC0

COUNTER

READ_BLOCK

; repeat

MODIFY_WORD

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BUFFER_ADDR_HIGH

FSR0H

BUFFER_ADDR_LOW

FSR0L

NEW_DATA_LOW

POSTINC0

NEW_DATA_HIGH

INDF0

; point to buffer

; update buffer word

ERASE_BLOCK

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

EECON1, FREE

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

INTCON, GIE

; load TBLPTR with the base

; address of the memory block

; point to Flash program memory

; access Flash program memory

; enable write to memory

; enable Erase operation

; disable interrupts

Required

Sequence

; write 55h

; write 0AAh

; start erase (CPU stall)

; re-enable interrupts

; dummy read decrement

; point to buffer

BSF

TBLRD*-

MOVLW

MOVWF

MOVLW

MOVWF

BUFFER_ADDR_HIGH

FSR0H

BUFFER_ADDR_LOW

FSR0L

WRITE_BUFFER_BACK

MOVLW

MOVWF

MOVLW

MOVWF

BlockSize

COUNTER

D’64’/BlockSize

COUNTER2

; number of bytes in holding register

; number of write blocks in 64 bytes

WRITE_BYTE_TO_HREGS

MOVF

MOVWF

TBLWT+*

POSTINC0, W

TABLAT

; get low byte of buffer data

; present data to table latch

; write data, perform a short write

; to internal TBLWT holding register.

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EXAMPLE 4-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

DECFSZ COUNTER

; loop until holding registers are full

BRA

WRITE_WORD_TO_HREGS

PROGRAM_MEMORY

BSF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

DCFSZ

BRA

BSF

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

COUNTER2

; point to Flash program memory

; access Flash program memory

; enable write to memory

; disable interrupts

Required

Sequence

; write 55h

; write 0AAh

; start program (CPU stall)

; repeat for remaining write blocks

;

; re-enable interrupts

; disable write to memory

WRITE_BYTE_TO_HREGS

INTCON, GIE

EECON1, WREN

BCF

4.5.2

WRITE VERIFY

4.5.4

PROTECTION AGAINST

SPURIOUS WRITES

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 23.0 “Special Features of the

CPU” for more detail.

4.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

4.6

Flash Program Operation During

Code Protection

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and

reprogrammed if needed. If the write operation is

interrupted by a MCLR Reset or a WDT Time-out Reset

during normal operation, the WRERR bit will be set

which the user can check to decide whether a rewrite

of the location(s) is needed.

See Section 23.3 “Program Verification and Code

Protection” for details on code protection of Flash

program memory.

TABLE 4-3:

Name

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Reset

Valueson

page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

WR

RD

247

245

248

245

EECON2 EEPROM Control Register 2 (not a physical register)

INTCON

IPR2

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RABIE

BCLIP

BCLIE

BCLIF

TMR0IF

INT0IF

TMR3IP

TMR3IE

TMR3IF

RABIF

—

OSCFIP

OSCFIE

OSCFIF

C1IP

C1IE

C1IF

C2IP

C2IE

C2IF

EEIP

EEIE

EEIF

—

PIE2

—

PIR2

—

TABLAT

Program Memory Table Latch

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

TBLPTRU bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

—

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

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5.2

EECON1 and EECON2 Registers

5.0

DATA EEPROM MEMORY

Access to the data EEPROM is controlled by two

registers: EECON1 and EECON2. These are the same

registers which control access to the program memory

and are used in a similar manner for the data

EEPROM.

The data EEPROM is a nonvolatile memory array,

separate from the data RAM and program memory,

which is used for long-term storage of program data. It

is not directly mapped in either the register file or

program memory space but is indirectly addressed

through the Special Function Registers (SFRs). The

EEPROM is readable and writable during normal

operation over the entire VDD range.

The EECON1 register (Register 5-1) is the control

register for data and program memory access. Control

bit EEPGD determines if the access will be to program

or data EEPROM memory. When the EEPGD bit is

clear, operations will access the data EEPROM

memory. When the EEPGD bit is set, program memory

is accessed.

Four SFRs are used to read and write to the data

EEPROM as well as the program memory. They are:

• EECON1

• EECON2

• EEDATA

• EEADR

Control bit, CFGS, determines if the access will be to

the Configuration registers or to program memory/data

EEPROM memory. When the CFGS bit is set,

subsequent operations access Configuration registers.

When the CFGS bit is clear, the EEPGD bit selects

either program Flash or data EEPROM memory.

The data EEPROM allows byte read and write. When

interfacing to the data memory block, EEDATA holds

the 8-bit data for read/write and the EEADR register

holds the address of the EEPROM location being

accessed.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear.

The EEPROM data memory is rated for high erase/write

cycle endurance. A byte write automatically erases the

location and writes the new data (erase-before-write).

The write time is controlled by an on-chip timer; it will

vary with voltage and temperature as well as from chip-

to-chip. Please refer to parameter US122 (Table 26-24)

for exact limits.

The WRERR bit is set by hardware when the WR bit is

set and cleared when the internal programming timer

expires and the write operation is complete.

Note:

During normal operation, the WRERR

may read as ‘1’. This can indicate that a

write

terminated by

operation was attempted improperly.

operation

was

Reset, or

prematurely

a

write

5.1

EEADR Register

The WR control bit initiates write operations. The bit

can be set but not cleared by software. It is cleared only

by hardware at the completion of the write operation.

The EEADR register is used to address the data

EEPROM for read and write operations. The 8-bit

range of the register can address a memory range of

256 bytes (00h to FFh).

Note:

The EEIF interrupt flag bit of the PIR2

register is set when the write is complete.

It must be cleared by software.

Control bits, RD and WR, start read and erase/write

operations, respectively. These bits are set by firmware

and cleared by hardware at the completion of the

operation.

The RD bit cannot be set when accessing program

memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 4.1 “Table Reads

and Table Writes” regarding table reads.

The EECON2 register is not a physical register. It is

used exclusively in the memory write and erase

sequences. Reading EECON2 will read all ‘0’s.

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REGISTER 5-1:

R/W-x

EECON1: DATA EEPROM CONTROL 1 REGISTER

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

S = Bit can be set by software, but not cleared

-n = Value at POR ‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

EEPGD: Flash Program or Data EEPROM Memory Select bit

1= Access Flash program memory

0= Access data EEPROM memory

CFGS: Flash Program/Data EEPROM or Configuration Select bit

1= Access Configuration registers

0= Access Flash program or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as ‘0’

FREE: Flash Row (Block) Erase Enable bit

1= Erase the program memory block addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write-only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit⁽¹⁾

1= A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0= The write operation completed

bit 2

bit 1

WREN: Flash Program/Data EEPROM Write Enable bit

1= Allows write cycles to Flash program/data EEPROM

0= Inhibits write cycles to Flash program/data EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) by software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only

be set (not cleared) by software. RD bit cannot be set when EEPGD = 1or CFGS = 1.)

0= Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the

error condition.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 55

PIC18(L)F1XK22

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code

execution (i.e., runaway programs). The WREN bit

should be kept clear at all times, except when updating

the EEPROM. The WREN bit is not cleared by

hardware.

5.3

Reading the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD

control bit of the EECON1 register and then set control

bit, RD. The data is available on the very next

instruction cycle; therefore, the EEDATA register can

be read by the next instruction. EEDATA will hold this

value until another read operation, or until it is written to

by the user (during a write operation).

After a write sequence has been initiated, EECON1,

EEADR and EEDATA cannot be modified. The WR bit

will be inhibited from being set unless the WREN bit is

set. Both WR and WREN cannot be set with the same

instruction.

The basic process is shown in Example 5-1.

At the completion of the write cycle, the WR bit is

cleared by hardware and the EEPROM Interrupt Flag

bit, EEIF, is set. The user may either enable this

interrupt or poll this bit. EEIF must be cleared by

software.

5.4

Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be written to the EEADR register and the data

written to the EEDATA register. The sequence in

Example 5-2 must be followed to initiate the write cycle.

5.5

Write Verify

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

The write will not begin if this sequence is not exactly

followed (write 55h to EECON2, write 0AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

EXAMPLE 5-1:

DATA EEPROM READ

MOVLW

MOVWF

BCF

DATA_EE_ADDR

EEADR

EECON1, EEPGD ; Point to DATA memory

;

; Data Memory Address to read

BCF

BSF

MOVF

EECON1, CFGS

EECON1, RD

EEDATA, W

; Access EEPROM

; EEPROM Read

; W = EEDATA

EXAMPLE 5-2:

DATA EEPROM WRITE

MOVLW

MOVWF

MOVLW

MOVWF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

DATA_EE_ADDR_LOW

EEADR

DATA_EE_DATA

EEDATA

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

INTCON, GIE

;

; Data Memory Address to write

;

; Data Memory Value to write

; Point to DATA memory

; Access EEPROM

; Enable writes

; Disable Interrupts

;

; Write 55h

;

; Write 0AAh

; Set WR bit to begin write

; Enable Interrupts

Required

Sequence

BSF

; User code execution

BCF

EECON1, WREN

; Disable writes on write complete (EEIF set)

DS40001365F-page 56

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

5.6

Operation During Code-Protect

5.8

Using the Data EEPROM

Data EEPROM memory has its own code-protect bits in

Configuration Words. External read and write

operations are disabled if code protection is enabled.

The data EEPROM is a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated often).

When variables in one section change frequently, while

variables in another section do not change, it is possible

to exceed the total number of write cycles to the

EEPROM without exceeding the total number of write

cycles to a single byte. If this is the case, then an array

refresh must be performed. For this reason, variables

that change infrequently (such as constants, IDs,

calibration, etc.) should be stored in Flash program

memory.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 23.0

“Special Features of the CPU” for additional

information.

5.7

Protection Against Spurious Write

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been implemented. On power-up, the WREN bit is

cleared. In addition, writes to the EEPROM are blocked

during the Power-up Timer period (TPWRT,

parameter 33).

A simple data EEPROM refresh routine is shown in

Example 5-3.

Note:

If data EEPROM is only used to store

constants and/or data that changes rarely,

an array refresh is likely not required. See

specification.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch or software malfunction.

EXAMPLE 5-3:

CLRF

DATA EEPROM REFRESH ROUTINE

EEADR

; Start at address 0

; Set for memory

; Set for Data EEPROM

; Disable interrupts

; Enable writes

; Loop to refresh array

; Read current address

;

BCF

BSF

EECON1, CFGS

EECON1, EEPGD

INTCON, GIE

EECON1, WREN

Loop

BSF

EECON1, RD

55h

MOVLW

MOVWF

MOVLW

MOVWF

BSF

EECON2

0AAh

; Write 55h

;

EECON2

EECON1, WR

$-2

; Write 0AAh

; Set WR bit to begin write

; Wait for write to complete

BTFSC

BRA

INCFSZ

BRA

EEADR, F

LOOP

; Increment address

; Not zero, do it again

BCF

BSF

EECON1, WREN

INTCON, GIE

; Disable writes

; Enable interrupts

TABLE 5-1:

Name

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0

Reset

Values

on page

Bit 0

EEADR

EECON1

EECON2

EEDATA

INTCON

IPR2

EEADR7

EEPGD

247

245

248

CFGS

—

FREE

WRERR

WREN

WR

RD

EEPROM Control Register 2 (not a physical register)

EEPROM Data Register

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

EEIP

EEIE

EEIF

RABIE

BCLIP

BCLIE

BCLIF

TMR0IF

INT0IF

TMR3IP

TMR3IE

TMR3IF

RABIF

—

OSCFIP

OSCFIE

OSCFIF

C1IP

C1IE

C1IF

C2IP

C2IE

C2IF

—

PIE2

—

PIR2

—

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 57

PIC18(L)F1XK22

EXAMPLE 6-1:

8 x 8 UNSIGNED

MULTIPLY ROUTINE

6.0

6.1

8 x 8 HARDWARE MULTIPLIER

Introduction

MOVF

MULWF

ARG1, W

ARG2

;

; ARG1 * ARG2 ->

; PRODH:PRODL

All PIC18 devices include an 8 x 8 hardware multiplier

as part of the ALU. The multiplier performs an unsigned

operation and yields a 16-bit result that is stored in the

product register pair, PRODH:PRODL. The multiplier’s

operation does not affect any flags in the STATUS

register.

EXAMPLE 6-2:

8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF

MULWF

ARG1, W

ARG2

Making multiplication a hardware operation allows it to

be completed in a single instruction cycle. This has the

advantages of higher computational throughput and

reduced code size for multiplication algorithms and

allows the PIC18 devices to be used in many

applications previously reserved for digital signal

processors. A comparison of various hardware and

software multiply operations, along with the savings in

memory and execution time, is shown in Table 6-1.

; ARG1 * ARG2 ->

; PRODH:PRODL

; Test Sign Bit

; PRODH = PRODH

BTFSC

SUBWF

ARG2, SB

PRODH, F

;

- ARG1

MOVF

BTFSC

SUBWF

ARG2, W

ARG1, SB

PRODH, F

; Test Sign Bit

; PRODH = PRODH

;

- ARG2

6.2

Operation

Example 6-1 shows the instruction sequence for an 8 x 8

unsigned multiplication. Only one instruction is required

when one of the arguments is already loaded in the

WREG register.

Example 6-2 shows the sequence to do an 8 x 8 signed

multiplication. To account for the sign bits of the

arguments, each argument’s Most Significant bit (MSb)

is tested and the appropriate subtractions are done.

TABLE 6-1:

Routine

PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Program

Memory

(Words)

Time

Cycles

(Max)

Multiply Method

@ 40 MHz @ 10 MHz @ 4 MHz

Without hardware multiply

Hardware multiply

13

1

69

1

6.9 s

100 ns

9.1 s

600 ns

24.2 s

2.8 s

25.4 s

4.0 s

27.6 s

400 ns

36.4 s

2.4 s

69 s

1 s

8 x 8 unsigned

8 x 8 signed

Without hardware multiply

Hardware multiply

33

6

91

6

91 s

6 s

Without hardware multiply

Hardware multiply

21

28

52

35

242

28

254

40

96.8 s

11.2 s

102.6 s

16.0 s

242 s

28 s

254 s

40 s

16 x 16 unsigned

16 x 16 signed

Without hardware multiply

Hardware multiply

DS40001365F-page 58

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

Example 6-3 shows the sequence to do a 16 x 16

unsigned multiplication. Equation 6-1 shows the

algorithm that is used. The 32-bit result is stored in four

registers (RES<3:0>).

EQUATION 6-2:

16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L

16

= (ARG1H  ARG2H  2 ) +

(ARG1H  ARG2L  2 ) +

(ARG1L  ARG2H  2 ) +

(ARG1L  ARG2L) +

(-1  ARG2H<7>  ARG1H:ARG1L  2 ) +

(-1  ARG1H<7>  ARG2H:ARG2L  2

8

EQUATION 6-1:

16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

8

16

RES3:RES0

=

ARG1H:ARG1L  ARG2H:ARG2L

16

)

16

(ARG1H  ARG2H  2 ) +

8

(ARG1H  ARG2L  2 ) +

8

(ARG1L  ARG2H  2 ) +

EXAMPLE 6-4:

16 x 16 SIGNED

MULTIPLY ROUTINE

(ARG1L  ARG2L)

MOVF

MULWF

ARG1L, W

ARG2L

; ARG1L * ARG2L ->

; PRODH:PRODL

;

EXAMPLE 6-3:

16 x 16 UNSIGNED

MULTIPLY ROUTINE

MOVFF

PRODH, RES1

PRODL, RES0

MOVF

MULWF

ARG1L, W

ARG2L

; ARG1L * ARG2L->

; PRODH:PRODL

;

MOVF

MULWF

ARG1H, W

ARG2H

MOVFF

PRODH, RES1

PRODL, RES0

; ARG1H * ARG2H ->

; PRODH:PRODL

;

MOVFF

PRODH, RES3

PRODL, RES2

MOVF

MULWF

ARG1H, W

ARG2H

; ARG1H * ARG2H->

; PRODH:PRODL

;

MOVF

MULWF

ARG1L, W

ARG2H

MOVFF

PRODH, RES3

PRODL, RES2

; ARG1L * ARG2H ->

; PRODH:PRODL

;

; Add cross

; products

;

MOVF

ADDWF

MOVF

ADDWFC RES2, F

CLRF WREG

ADDWFC RES3, F

PRODL, W

RES1, F

PRODH, W

MOVF

MULWF

ARG1L, W

ARG2H

; ARG1L * ARG2H->

; PRODH:PRODL

;

; Add cross

; products

;

MOVF

ADDWF

MOVF

PRODL, W

RES1, F

PRODH, W

;

ADDWFC RES2, F

CLRF WREG

ADDWFC RES3, F

MOVF

MULWF

ARG1H, W

ARG2L

;

; ARG1H * ARG2L ->

; PRODH:PRODL

;

; Add cross

; products

;

MOVF

ADDWF

MOVF

ADDWFC RES2, F

CLRF WREG

ADDWFC RES3, F

PRODL, W

RES1, F

PRODH, W

MOVF

MULWF

ARG1H, W

ARG2L

;

; ARG1H * ARG2L->

; PRODH:PRODL

;

; Add cross

; products

;

MOVF

ADDWF

MOVF

PRODL, W

RES1, F

PRODH, W

;

ADDWFC RES2, F

CLRF WREG

ADDWFC RES3, F

BTFSS

BRA

MOVF

SUBWF

MOVF

ARG2H, 7

SIGN_ARG1

ARG1L, W

RES2

; ARG2H:ARG2L neg?

; no, check ARG1

;

Example 6-4 shows the sequence to do a 16 x 16

signed multiply. Equation 6-2 shows the algorithm

used. The 32-bit result is stored in four registers

(RES<3:0>). To account for the sign bits of the

arguments, the MSb for each argument pair is tested

and the appropriate subtractions are done.

ARG1H, W

SUBWFB RES3

SIGN_ARG1

BTFSS

BRA

ARG1H, 7

CONT_CODE

ARG2L, W

RES2

; ARG1H:ARG1L neg?

; no, done

;

MOVF

SUBWF

MOVF

ARG2H, W

SUBWFB RES3

;

CONT_CODE

:

 2009-2016 Microchip Technology Inc.

DS40001365F-page 59

PIC18(L)F1XK22

7.2

Interrupt Priority

7.0

INTERRUPTS

The interrupt priority feature is enabled by setting the

IPEN bit of the RCON register. When interrupt priority

is enabled the GIE and PEIE global interrupt enable

bits of Compatibility mode are replaced by the GIEH

high priority, and GIEL low priority, global interrupt

enables. When set, the GIEH bit of the INTCON

register enables all interrupts that have their associated

IPRx register or INTCONx register priority bit set (high

priority). When clear, the GIEL bit disables all interrupt

sources including those selected as low priority. When

clear, the GIEL bit of the INTCON register disables only

the interrupts that have their associated priority bit

cleared (low priority). When set, the GIEL bit enables

the low priority sources when the GIEH bit is also set.

The PIC18(L)F1XK22 devices have multiple interrupt

sources and an interrupt priority feature that allows

most interrupt sources to be assigned a high priority

level or a low priority level. The high priority interrupt

vector is at 0008h and the low priority interrupt vector is

at 0018h. A high priority interrupt event will interrupt a

low priority interrupt that may be in progress.

There are twelve registers which are used to control

interrupt operation. These registers are:

• RCON

• INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2

When the interrupt flag, enable bit and appropriate

global interrupt enable bit are all set, the interrupt will

vector immediately to address 0008h for high priority,

or 0018h for low priority, depending on level of the

interrupting source’s priority bit. Individual interrupts

can be disabled through their corresponding interrupt

enable bits.

It is recommended that the Microchip header files

supplied with MPLAB^®IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

7.3

Interrupt Response

In general, interrupt sources have three bits to control

their operation. They are:

When an interrupt is responded to, the global interrupt

enable bit is cleared to disable further interrupts. The

GIE bit is the global interrupt enable when the IPEN bit

is cleared. When the IPEN bit is set, enabling interrupt

priority levels, the GIEH bit is the high priority global

interrupt enable and the GIEL bit is the low priority

global interrupt enable. High-priority interrupt sources

can interrupt a low-priority interrupt. Low-priority

interrupts are not processed while high-priority

interrupts are in progress.

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

7.1

Mid-Range Compatibility

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address (0008h

or 0018h). Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits in the INTCONx and PIRx

registers. The interrupt flag bits must be cleared by

software before re-enabling interrupts to avoid

repeating the same interrupt.

When the IPEN bit is cleared (default state), the interrupt

priority feature is disabled and interrupts are compatible

with PIC^®microcontroller mid-range devices. In

Compatibility mode, the interrupt priority bits of the IPRx

registers have no effect. The PEIE bit of the INTCON

register is the global interrupt enable for the peripherals.

The PEIE bit disables only the peripheral interrupt

sources and enables the peripheral interrupt sources

when the GIE bit is also set. The GIE bit of the INTCON

register is the global interrupt enable which enables all

non-peripheral interrupt sources and disables all

interrupt sources, including the peripherals. All interrupts

branch to address 0008h in Compatibility mode.

The “return-from-interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or

the PORTB interrupt-on-change, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one-cycle or two-cycle

instructions. Individual interrupt flag bits are set,

regardless of the status of their corresponding enable

bits or the global interrupt enable bit.

DS40001365F-page 60

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

Note:

Do not use the MOVFF instruction to

modify any of the interrupt control

registers while any interrupt is enabled.

Doing

so

may

cause

erratic

microcontroller behavior.

FIGURE 7-1:

PIC18 INTERRUPT LOGIC

Wake-up if in

Idle or Sleep modes

TMR0IF

TMR0IE

TMR0IP

RABIF

(1)

RABIE

RABIP

INT0IF

INT0IE

Interrupt to CPU

Vector to Location

0008h

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

SSPIF

SSPIE

SSPIP

GIEH/GIE

ADIF

ADIE

ADIP

IPEN

GIEL/PEIE

RCIF

RCIE

RCIP

IPEN

Additional Peripheral Interrupts

High Priority Interrupt Generation

Low Priority Interrupt Generation

SSPIF

SSPIE

SSPIP

Interrupt to CPU

Vector to Location

0018h

TMR0IF

TMR0IE

TMR0IP

ADIF

ADIE

ADIP

(1)

RABIF

RABIE

RABIP

GIEH/GIE

GIEL/PEIE

RCIF

RCIE

RCIP

INT1IF

INT1IE

INT1IP

Additional Peripheral Interrupts

INT2IF

INT2IE

INT2IP

Note 1: The RABIF interrupt also requires the individual pin IOCA and IOCB enable.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 61

PIC18(L)F1XK22

7.4

INTCON Registers

The INTCON registers are readable and writable

registers, which contain various enable, priority and

flag bits.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

REGISTER 7-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

GIE/GIEH

bit 7

R/W-0

INT0IF

R/W-x

RABIF

PEIE/GIEL

TMR0IE

INT0IE

RABIE

TMR0IF

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1= Enables all unmasked interrupts

0= Disables all interrupts including peripherals

When IPEN = 1:

1= Enables all high priority interrupts

0= Disables all interrupts including low priority

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN = 0:

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

When IPEN = 1:

1= Enables all low priority interrupts

0= Disables all low priority interrupts

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TMR0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 overflow interrupt

0= Disables the TMR0 overflow interrupt

INT0IE: INT0 External Interrupt Enable bit

1= Enables the INT0 external interrupt

0= Disables the INT0 external interrupt

RABIE: RA and RB Port Change Interrupt Enable bit⁽²⁾

1= Enables the RA and RB port change interrupt

0= Disables the RA and RB port change interrupt

TMR0IF: TMR0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed (must be cleared by software)

0= TMR0 register did not overflow

INT0IF: INT0 External Interrupt Flag bit

1= The INT0 external interrupt occurred (must be cleared by software)

0= The INT0 external interrupt did not occur

RABIF: RA and RB Port Change Interrupt Flag bit⁽¹⁾

1= At least one of the RA <5:0> or RB<7:4> pins changed state (must be cleared by software)

0= None of the RA<5:0> or RB<7:4> pins have changed state

Note 1:

2:

A mismatch condition will continue to set the RABIF bit. Reading PORTA and PORTB will end the mismatch condition and allow the bit to

be cleared.

RA and RB port change interrupts also require the individual pin IOCA and IOCB enable.

DS40001365F-page 62

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

REGISTER 7-2:

R/W-1

INTCON2: INTERRUPT CONTROL 2 REGISTER

R/W-1

U-0

—

R/W-1

U-0

—

R/W-1

RABIP

RABPU

INTEDG0

INTEDG1

INTEDG2

TMR0IP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

RABPU: PORTA and PORTB Pull-up Enable bit

1= PORTA and PORTB pull-ups are disabled

0= PORTA and PORTB pull-ups are enabled provided that the pin is an input and the corresponding

WPUA and WPUB bits are set.

bit 6

bit 5

bit 4

INTEDG0: External Interrupt 0 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG1: External Interrupt 1 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG2: External Interrupt 2 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

bit 3

bit 2

Unimplemented: Read as ‘0’

TMR0IP: TMR0 Overflow Interrupt Priority bit

1= High priority

0= Low priority

bit 1

bit 0

Unimplemented: Read as ‘0’

RABIP: RA and RB Port Change Interrupt Priority bit

1= High priority

0= Low priority

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software might ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 63

PIC18(L)F1XK22

REGISTER 7-3:

R/W-1

INTCON3: INTERRUPT CONTROL 3 REGISTER

R/W-1

U-0

—

R/W-0

U-0

—

R/W-0

INT2IF

R/W-0

INT1IF

INT2IP

INT1IP

INT2IE

INT1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

INT2IP: INT2 External Interrupt Priority bit

1= High priority

0= Low priority

INT1IP: INT1 External Interrupt Priority bit

1= High priority

0= Low priority

bit 5

bit 4

Unimplemented: Read as ‘0’

INT2IE: INT2 External Interrupt Enable bit

1= Enables the INT2 external interrupt

0= Disables the INT2 external interrupt

bit 3

INT1IE: INT1 External Interrupt Enable bit

1= Enables the INT1 external interrupt

0= Disables the INT1 external interrupt

bit 2

bit 1

Unimplemented: Read as ‘0’

INT2IF: INT2 External Interrupt Flag bit

1= The INT2 external interrupt occurred (must be cleared by software)

0= The INT2 external interrupt did not occur

bit 0

INT1IF: INT1 External Interrupt Flag bit

1= The INT1 external interrupt occurred (must be cleared by software)

0= The INT1 external interrupt did not occur

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software might ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

DS40001365F-page 64

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PIC18(L)F1XK22

7.5

PIR Registers

Note 1: Interrupt flag bits are set when an

interrupt condition occurs, regardless of

the state of its corresponding enable bit or

the Global Interrupt Enable bit, GIE of the

INTCON register.

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Request Flag registers (PIR1 and PIR2).

2: User software might ensure the

appropriate interrupt flag bits are cleared

prior to enabling an interrupt and after

servicing that interrupt.

REGISTER 7-4:

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

U-0

—

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

RCIF

TXIF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

ADIF: A/D Converter Interrupt Flag bit

1= An A/D conversion completed (must be cleared by software)

0= The A/D conversion is not complete or has not been started

bit 5

bit 4

bit 3

bit 2

RCIF: EUSART Receive Interrupt Flag bit

1= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)

0= The EUSART receive buffer is empty

TXIF: EUSART Transmit Interrupt Flag bit

1= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0= The EUSART transmit buffer is full

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1= The transmission/reception is complete (must be cleared by software)

0= Waiting to transmit/receive

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared by software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared by software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1

bit 0

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1= TMR2 to PR2 match occurred (must be cleared by software)

0= No TMR2 to PR2 match occurred

TMR1IF: TMR1 Overflow Interrupt Flag bit

1= TMR1 register overflowed (must be cleared by software)

0= TMR1 register did not overflow

Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.

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DS40001365F-page 65

PIC18(L)F1XK22

REGISTER 7-5:

R/W-0

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

R/W-0

C1IF

R/W-0

C2IF

R/W-0

EEIF

R/W-0

BCLIF

U-0

—

R/W-0

U-0

—

OSCFIF

TMR3IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

OSCFIF: Oscillator Fail Interrupt Flag bit

1= Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software)

0= Device clock operating

C1IF: Comparator C1 Interrupt Flag bit

1= Comparator C1 output has changed (must be cleared by software)

0= Comparator C1 output has not changed

C2IF: Comparator C2 Interrupt Flag bit

1= Comparator C2 output has changed (must be cleared by software)

0= Comparator C2 output has not changed

EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1= The write operation is complete (must be cleared by software)

0= The write operation is not complete or has not been started

BCLIF: Bus Collision Interrupt Flag bit

1= A bus collision occurred (must be cleared by software)

0= No bus collision occurred

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR3IF: TMR3 Overflow Interrupt Flag bit

1= TMR3 register overflowed (must be cleared by software)

0= TMR3 register did not overflow

bit 0

Unimplemented: Read as ‘0’

DS40001365F-page 66

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PIC18(L)F1XK22

7.6

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are two Peripheral

Interrupt Enable registers (PIE1 and PIE2). When IPEN

= 0, the PEIE bit must be set to enable any of these

peripheral interrupts.

REGISTER 7-6:

PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1

U-0

—

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

ADIE: A/D Converter Interrupt Enable bit

1= Enables the A/D interrupt

0= Disables the A/D interrupt

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RCIE: EUSART Receive Interrupt Enable bit

1= Enables the EUSART receive interrupt

0= Disables the EUSART receive interrupt

TXIE: EUSART Transmit Interrupt Enable bit

1= Enables the EUSART transmit interrupt

0= Disables the EUSART transmit interrupt

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1= Enables the MSSP interrupt

0= Disables the MSSP interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the TMR2 to PR2 match interrupt

0= Disables the TMR2 to PR2 match interrupt

TMR1IE: TMR1 Overflow Interrupt Enable bit

1= Enables the TMR1 overflow interrupt

0= Disables the TMR1 overflow interrupt

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DS40001365F-page 67

PIC18(L)F1XK22

REGISTER 7-7:

R/W-0

PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2

R/W-0

C1IE

R/W-0

C2IE

R/W-0

EEIE

R/W-0

BCLIE

U-0

—

R/W-0

U-0

—

OSCFIE

TMR3IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

OSCFIE: Oscillator Fail Interrupt Enable bit

1= Enabled

0= Disabled

C1IE: Comparator C1 Interrupt Enable bit

1= Enabled

0= Disabled

C2IE: Comparator C2 Interrupt Enable bit

1= Enabled

0= Disabled

EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit

1= Enabled

0= Disabled

BCLIE: Bus Collision Interrupt Enable bit

1= Enabled

0= Disabled

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR3IE: TMR3 Overflow Interrupt Enable bit

1= Enabled

0= Disabled

bit 0

Unimplemented: Read as ‘0’

DS40001365F-page 68

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PIC18(L)F1XK22

7.7

IPR Registers

The IPR registers contain the individual priority bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Priority registers (IPR1 and IPR2). Using the priority bits

requires that the Interrupt Priority Enable (IPEN) bit be

set.

REGISTER 7-8:

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

U-0

—

R/W-1

ADIP

R/W-1

RCIP

R/W-1

TXIP

R/W-1

SSPIP

R/W-1

CCP1IP

TMR2IP

TMR1IP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

ADIP: A/D Converter Interrupt Priority bit

1= High priority

0= Low priority

bit 5

bit 4

RCIP: EUSART Receive Interrupt Priority bit

1= High priority

0= Low priority

TXIP: EUSART Transmit Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

bit 0

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1= High priority

0= Low priority

CCP1IP: CCP1 Interrupt Priority bit

1= High priority

0= Low priority

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1= High priority

0= Low priority

TMR1IP: TMR1 Overflow Interrupt Priority bit

1= High priority

0= Low priority

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DS40001365F-page 69

PIC18(L)F1XK22

REGISTER 7-9:

R/W-1

IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2

R/W-1

C1IP

R/W-1

C2IP

R/W-1

EEIP

R/W-1

BCLIP

U-0

—

R/W-1

U-0

—

OSCFIP

TMR3IP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

OSCFIP: Oscillator Fail Interrupt Priority bit

1= High priority

0= Low priority

C1IP: Comparator C1 Interrupt Priority bit

1= High priority

0= Low priority

C2IP: Comparator C2 Interrupt Priority bit

1= High priority

0= Low priority

EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit

1= High priority

0= Low priority

BCLIP: Bus Collision Interrupt Priority bit

1= High priority

0= Low priority

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR3IP: TMR3 Overflow Interrupt Priority bit

1= High priority

0= Low priority

bit 0

Unimplemented: Read as ‘0’

DS40001365F-page 70

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PIC18(L)F1XK22

7.8

RCON Register

The RCON register contains flag bits which are used to

determine the cause of the last Reset or wake-up from

Idle or Sleep modes. RCON also contains the IPEN bit

which enables interrupt priorities.

The operation of the SBOREN bit and the Reset flag

bits is discussed in more detail in Section 22.1 “RCON

Register”.

REGISTER 7-10: RCON: RESET CONTROL REGISTER

R/W-0

IPEN

R/W-1

SBOREN⁽¹⁾

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR⁽²⁾

R/W-0

BOR⁽³⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

SBOREN: BOR Software Enable bit⁽¹⁾

If BOREN<1:0> = 01:

1= BOR is enabled

0= BOR is disabled

If BOREN<1:0> = 00, 10or 11:

Bit is disabled and read as ‘0’.

bit 5

bit 4

Unimplemented: Read as ‘0’

RI: RESETInstruction Flag bit

1= The RESETinstruction was not executed (set by firmware or Power-on Reset)

0= The RESET instruction was executed causing a device Reset (must be set in firmware after a

code-executed Reset occurs)

bit 3

bit 2

bit 1

bit 0

TO: Watchdog Time-out Flag bit

1= Set by power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT Time-out occurred

PD: Power-down Detection Flag bit

1= Set by power-up or by the CLRWDTinstruction

0= Set by execution of the SLEEPinstruction

POR: Power-on Reset Status bit⁽²⁾

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit⁽³⁾

1= A Brown-out Reset has not occurred (set by firmware only)

0= A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this

register and Section 22.6 “Reset State of Registers” for additional information.

3: See Table 22-3.

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DS40001365F-page 71

PIC18(L)F1XK22

7.9

INTx Pin Interrupts

7.10 TMR0 Interrupt

External interrupts on the INT0, INT1 and INT2 pins are

edge-triggered. If the corresponding INTEDGx bit in the

INTCON2 register is set (= 1), the interrupt is triggered

by a rising edge; if the bit is clear, the trigger is on the

falling edge. When a valid edge appears on the INTx

pin, the corresponding flag bit, INTxF, is set. This

interrupt can be disabled by clearing the corresponding

enable bit, INTxE. Flag bit, INTxF, must be cleared by

software in the Interrupt Service Routine before re-

enabling the interrupt.

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh  00h) will set flag bit, TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L

register pair (FFFFh 0000h) will set TMR0IF. The

interrupt can be enabled/disabled by setting/clearing

enable bit, TMR0IE of the INTCON register. Interrupt

priority for Timer0 is determined by the value contained

in the interrupt priority bit, TMR0IP of the INTCON2

register. See Section 9.0 “Timer0 Module” for further

details on the Timer0 module.

All external interrupts (INT0, INT1 and INT2) can wake-

up the processor from Idle or Sleep modes if bit INTxE

was set prior to going into those modes. If the Global

Interrupt Enable bit, GIE, is set, the processor will

branch to the interrupt vector following wake-up.

7.11 PORTA and PORTB Interrupt-on-

Change

An input change on PORTA or PORTB sets flag bit,

RABIF of the INTCON register. The interrupt can be

enabled/disabled by setting/clearing enable bit, RABIE

of the INTCON register. Pins must also be individually

enabled with the IOCA and IOCB register. Interrupt

priority for PORTA and PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RABIP of the INTCON2 register.

Interrupt priority for INT1 and INT2 is determined by

the value contained in the interrupt priority bits,

INT1IP and INT2IP of the INTCON3 register. There is

no priority bit associated with INT0. It is always a high-

priority interrupt source.

7.12 Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (see Section 3.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 7-1 saves and restores the WREG,

STATUS and BSR registers during an Interrupt Service

Routine.

EXAMPLE 7-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

MOVFF

;

W_TEMP

STATUS, STATUS_TEMP

BSR, BSR_TEMP

; W_TEMP is in virtual bank

; STATUS_TEMP located anywhere

; BSR_TMEP located anywhere

; USER ISR CODE

;

MOVFF

MOVF

MOVFF

BSR_TEMP, BSR

W_TEMP, W

STATUS_TEMP, STATUS

; Restore BSR

; Restore WREG

; Restore STATUS

DS40001365F-page 72

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PIC18(L)F1XK22

8.1

PORTA, TRISA and LATA Registers

8.0

I/O PORTS

PORTA is a 6-bit wide, bidirectional port, with the

exception of RA3, which is input-only and its TRIS bit

will always read as ‘1’. The corresponding data

direction register is TRISA. Setting a TRISA bit (= 1)

will make the corresponding PORTA pin an input (i.e.,

disable the output driver). Clearing a TRISA bit (= 0)

will make the corresponding PORTA pin an output (i.e.,

enable the output driver and put the contents of the

output latch on the selected pin).

There are up to three ports available. Some pins of the

I/O ports are multiplexed with an alternate function from

the peripheral features on the device. In general, when

a peripheral is enabled, that pin may not be used as a

general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

• PORT register (reads the levels on the pins of the

device)

Reading the PORTA register reads the status of the

pins, whereas writing to it, will write to the PORT latch.

• LAT register (output latch)

The PORTA Data Latch (LATA) register is also memory

mapped. Read-modify-write operations on the LATA

register read and write the latched output value for

PORTA.

The PORTA Data Latch (LATA register) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 8-1.

All of the PORTA pins are individually configurable as

interrupt-on-change pins. Control bits in the IOCA

register enable (when set) or disable (when clear) the

interrupt function for each pin.

FIGURE 8-1:

GENERIC I/O PORT

OPERATION

When set, the RABIE bit of the INTCON register

enables interrupts on all pins which also have their

corresponding IOCA bit set. When clear, the RABIE

bit disables all interrupt-on-changes.

RD LAT

Data

Bus

Only pins configured as inputs can cause this interrupt

to occur (i.e., any pin configured as an output is

excluded from the interrupt-on-change comparison).

D

Q

I/O pin⁽¹⁾

WR LAT

or

Port

CK

Data Latch

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTA. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTA Change Interrupt flag

bit (RABIF) in the INTCON register.

D

Q

WR TRIS

RD TRIS

CK

TRIS Latch

Input

Buffer

Q

D

EN

RD Port

Note 1: I/O pins have diode protection to VDD and VSS.

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DS40001365F-page 73

PIC18(L)F1XK22

This interrupt can wake the device from the Sleep mode,

or any of the Idle modes. The user, in the Interrupt

Service Routine, can clear the interrupt in the following

manner:

Pins RA4 and RA5 are multiplexed with the main

oscillator pins; they are enabled as oscillator or I/O pins

by the selection of the main oscillator in the

Configuration

register

(see

Section 23.1

“Configuration Bits” for details). When they are not

used as port pins, RA4 and RA5 and their associated

TRIS and LAT bits read as ‘0’.

a) Any read or write of PORTA to clear the

mismatch condition (except when PORTA is the

source or destination of a MOVFF instruction).

RA<4,2:0> are pins multiplexed with analog inputs. The

operation of pins RA<4,2:0> as analog are selected by

setting the ANS<3:0> bits in the ANSEL register, which

is the default setting after a Power-on Reset.

b) Clear the flag bit, RABIF.

A mismatch condition will continue to set the RABIF flag

bit. Reading or writing PORTA will end the mismatch

condition and allow the RABIF bit to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After either one of these Resets, the

RABIF flagwillcontinuetobeset if amismatch ispresent.

EXAMPLE 8-1:

INITIALIZING PORTA

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

CLRF

LATA

; Alternate method

; to clear output

; data latches

; Value used to

; initialize data

; direction

Note 1: If a change on the I/O pin should occur

when the read operation is being

executed (start of the Q2 cycle), then the

RABIF interrupt flag may not get set.

Furthermore, since a read or write on a

port affects all bits of that port, care must

be taken when using multiple pins in

Interrupt-on-Change mode. Changes on

one pin may not be seen while servicing

changes on another pin.

MOVLW

MOVWF

030h

TRISA

; Set RA<5:4> as output

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTA is only used for the interrupt-on-change

feature. Polling of PORTA is not recommended while

using the interrupt-on-change feature.

Each of the PORTA pins has an individually controlled

weak internal pull-up. When set, each bit of the WPUA

register enables the corresponding pin pull-up. When

cleared, the RABPU bit of the INTCON2 register

enables pull-ups on all pins which also have their

corresponding WPUA bit set. When set, the RABPU bit

disables all weak pull-ups. The weak pull-up is

automatically turned off when the port pin is configured

as an output. The pull-ups are disabled on a Power-on

Reset.

RA3 is an input only pin. Its operation is controlled by

the MCLRE bit of the CONFIG3H register. When

selected as a port pin (MCLRE = 0), it functions as a

digital input only pin; as such, it does not have TRIS or

LAT bits associated with its operation.

Note:

On a Power-on Reset, RA3 is enabled as

a digital input only if Master Clear

functionality is disabled.

DS40001365F-page 74

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PIC18(L)F1XK22

REGISTER 8-1:

PORTA: PORTA REGISTER

U-0

—

U-0

—

R/W-x

RA5

R/W-x

RA4

R-x

R/W-x

RA2

R/W-x

RA1

R/W-x

RA0

RA3

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RA<5:0>: PORTA I/O Pin bit⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0).

Otherwise, RA3 reads as ‘0’. This bit is read-only.

REGISTER 8-2:

TRISA: PORTA TRI-STATE REGISTER

U-0

—

U-0

—

R/W-1

U-1

—

R/W-1

TRISA0

bit 0

TRISA5

TRISA4

TRISA2

TRISA1

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

TRISA<5:4>: PORTA Tri-State Control bit⁽¹⁾

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

bit 3

Unimplemented: Read as ‘1’

bit 2-0

TRISA<2:0>: PORTA Tri-State Control bit⁽¹⁾

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

Note 1: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

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DS40001365F-page 75

PIC18(L)F1XK22

REGISTER 8-3:

LATA: PORTA DATA LATCH REGISTER

U-0

—

U-0

—

R/W-x

LATA5

R/W-x

LATA4

U-0

—

R/W-x

LATA2

R/W-x

LATA1

R/W-x

LATA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

bit 3

Unimplemented: Read as ‘0’

LATA<5:4>: RA<5:4> Port I/O Output Latch Register bits

Unimplemented: Read as ‘0’

bit 2-0

LATA<2:0>: RA<2:0> Port I/O Output Latch Register bits

REGISTER 8-4:

WPUA: WEAK PULL-UP PORTA REGISTER

U-0

—

U-0

—

R/W-1

(1)

WPUA5

WPUA4

WPUA3

WPUA2

WPUA1

WPUA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

WPUA<5:0>: Weak Pull-up Enable bit

1= Pull-up enabled

0= Pull-up disabled

Note 1: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.

REGISTER 8-5:

IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER

U-0

—

U-0

—

R/W-0

IOCA5

R/W-0

IOCA4

R/W-0

IOCA3

R/W-0

IOCA2

R/W-0

IOCA1

R/W-0

IOCA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOCA<5:0>: PORTA I/O Pin bit

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

DS40001365F-page 76

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 8-1:

PORTA I/O SUMMARY

TRIS

Setting

I/O

Type

Function

I/O

Description

RA0/AN0/CVREF/

DAC1OUT/VREF-/

C1IN+/INT0/PGD

0

1

x

O

I

DIG LATA<0> data output.

RA0

TTL PORTA<0> data input; Programmable weak pull-up.

ANA ADC channel 0 input.

AN0

I

CVREF/

O

ANA DAC reference voltage output.

DAC1OUT

VREF-

C1IN+

INT0

I

ANA ADC and DAC reference voltage (low) input.

DIG Comparator C1 noninverting input.

1

x

0

1

x

0

1

0

1

0

I

ST

DIG Serial execution data output for ICSP™.

ST Serial execution data input for ICSP.

External interrupt 0.

PGD

O

I

RA1/AN1/C12IN0-/

VREF+/INT1/PGC

O

I

DIG LATA<1> data output.

RA1

TTL PORTA<1> data input; Programmable weak pull-up.

ANA ADC channel 1.

AN1

C12IN0-

VREF+

INT1

I

ANA Comparator C1 and C2 inverting input channel 0.

ANA ADC and DAC reference voltage (high) input

I

ST

DIG Serial execution clock output for ICSP™.

ST Serial execution clock input for ICSP.

External interrupt 1.

PGC

O

I

RA2/AN2/C1OUT/

T0CKI/INT2/SRQ

O

I

DIG LATA<2> data output.

RA2

TTL PORTA<2> data input; Programmable weak pull-up.

ANA ADC channel 2.

AN2

C1OUT

T0CKI

INT2

I

O

I

DIG Comparator C1 output.

ST

Timer0 external clock input.

External interrupt 2.

I

SRQ

O

DIG SR latch output.

(1)

RA3/MCLR/VPP

RA3

—

I

ST

PORTA<37> data input; Programmable weak pull-up.

Active-low Master Clear with internal pull-up.

High-voltage programming input.

MCLR

VPP

—

0

I

O

I

ANA

RA4/AN3/OSC2/

CLKOUT

RA4

DIG LATA<4> data output.

1

TTL PORTA<4> data input; Programmable weak pull-up.

1

I

ANA

DIG

AN3

A/D input channel 3.

x

O

OSC2

Main oscillator feedback output connection (XT, HS and LP modes).

System instruction cycle clock output.

CLKOUT

RA5/OSC1/CLKIN/

T13CKI

RA5

0

1

x

O

I

DIG LATA<5> data output.

TTL PORTA<5> data input; Programmable weak pull-up.

ANA Main oscillator input connection.

I

OSC1

CLKIN

T13CKI

x

1

I

ANA Main clock input connection.

ST

Timer1 and Timer3 external clock input.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 77

PIC18(L)F1XK22

TABLE 8-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Reset

Valueson

page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSEL

INTCON

INTCON2

IOCA

ANS7

ANS6

ANS5

ANS4

ANS3

RABIE

—

ANS2

TMR0IF

TMR0IP

IOCA2

LATA2

RA2

ANS1

INT0IF

—

ANS0

RABIF

RABIP

IOCA0

LATA0

RA0

247

244

247

244

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RABPU INTEDG0 INTEDG1 INTEDG2

IOCA3⁽²⁾

IOCA1

LATA1

RA1

—

IOCA5

LATA5⁽¹⁾LATA4⁽¹⁾

RA5⁽¹⁾

—

TRISA5⁽¹⁾TRISA4⁽¹⁾

IOCA4

LATA

—

PORTA

SLRCON

TRISA

RA4⁽¹⁾

—

RA3⁽²⁾

—

SLRC

SLRB

TRISA1

WPUA1

SLRA

(3)

—

TRISA2

WPUA2

TRISA0

WPUA0

WPUA3⁽²⁾

WPUA

WPUA5

WPUA4

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.

Note 1: RA<5:4> and their associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

2: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

3: Unimplemented, read as ‘1’.

DS40001365F-page 78

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

A mismatch condition will continue to set the RABIF flag

bit. Reading or writing PORTB will end the mismatch

condition and allow the RABIF bit to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After either one of these Resets, the

RABIF flagwillcontinue tobeset if amismatchispresent.

8.2

PORTB, TRISB and LATB

Registers

PORTB is an 4-bit wide, bidirectional port. The

corresponding data direction register is TRISB. Setting

a TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., disable the output driver). Clearing a

TRISB bit (= 0) will make the corresponding PORTB

pin an output (i.e., enable the output driver and put the

contents of the output latch on the selected pin).

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RABIF

interrupt flag may not get set. Furthermore,

since a read or write on a port affects all

bits of that port, care must be taken when

using multiple pins in Interrupt-on-Change

mode. Changes on one pin may not be

seen while servicing changes on another

pin.

The PORTB Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

register read and write the latched output value for

PORTB.

EXAMPLE 8-2:

INITIALIZING PORTB

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

CLRF

LATB

MOVLW

MOVWF

0F0h

; Value used to

; initialize data

; direction

All PORTB pins have individually controlled weak

internal pull-up. When set, each bit of the WPUB

register enables the corresponding pin pull-up. When

cleared, the RABPU bit of the INTCON2 register

enables pull-ups on all pins which also have their

corresponding WPUB bit set. When set, the RABPU bit

disables all weak pull-ups. The weak pull-up is

automatically turned off when the port pin is configured

as an output. The pull-ups are disabled on a Power-on

Reset.

TRISB

; Set RB<7:4> as outputs

All PORTB pins are individually configurable as

interrupt-on-change pins. Control bits in the IOCB

register enable (when set) or disable (when clear) the

interrupt function for each pin.

When set, the RABIE bit of the INTCON register

enables interrupts on all pins which also have their

corresponding IOCB bit set. When clear, the RABIE

bit disables all interrupt-on-changes.

Note:

On a Power-on Reset, RB<5:4> are

configured as analog inputs by default and

read as ‘0’.

Only pins configured as inputs can cause this interrupt

to occur (i.e., any pin configured as an output is

excluded from the interrupt-on-change comparison).

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTB. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTB Change Interrupt flag

bit (RABIF) in the INTCON register.

This interrupt can wake the device from the Sleep

mode, or any of the Idle modes. The user, in the

Interrupt Service Routine, can clear the interrupt in the

following manner:

a) Any read or write of PORTB to clear the

mismatch condition (except when PORTB is the

source or destination of a MOVFF instruction).

b) Clear the flag bit, RABIF.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 79

PIC18(L)F1XK22

REGISTER 8-6:

PORTB: PORTB REGISTER

R/W-x

RB7

R/W-x

RB6

R/W-x

RB5

R/W-x

RB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

RB<7:4>: PORTB I/O Pin bit

1= Port pin is >VIH

0= Port pin is <VIL

Unimplemented: Read as ‘0’

REGISTER 8-7:

R/W-1

TRISB: PORTB TRI-STATE REGISTER

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

TRISB7

TRISB6

TRISB5

TRISB4

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

TRISB<7:4>: PORTB Tri-State Control bit

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

Unimplemented: Read as ‘0’

REGISTER 8-8:

R/W-x

LATB: PORTB DATA LATCH REGISTER

R/W-x

LATB6

R/W-x

LATB5

R/W-x

LATB4

U-0

—

U-0

—

U-0

—

U-0

—

LATB7

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

LATB<7:4>: RB<7:4> Port I/O Output Latch Register bits

Unimplemented: Read as ‘0’

DS40001365F-page 80

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

REGISTER 8-9:

R/W-1

WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

WPUB7

WPUB6

WPUB5

WPUB4

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

WPUB<7:4>: Weak Pull-up Enable bit

1= Pull-up enabled

0= Pull-up disabled

Unimplemented: Read as ‘0’

REGISTER 8-10: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER

R/W-0

IOCB7

R/W-0

IOCB6

R/W-0

IOCB5

R/W-0

IOCB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

IOCB<7:4>: Interrupt-on-change bits

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

Unimplemented: Read as ‘0’

 2009-2016 Microchip Technology Inc.

DS40001365F-page 81

PIC18(L)F1XK22

TABLE 8-3:

PORTB I/O SUMMARY

TRIS

Setting

I/O

Type

Function

I/O

Description

RB4/AN10/SDI/

SDA

RB4

0

1

0

1

O

I

DIG LATB<4> data output.

TTL PORTB<4> data input; Programmable weak pull-up.

ANA ADC input channel 10.

AN10

SDI

I

ST

SPI data input (MSSP module).

2

SDA

O

I

DIG I C data output (MSSP module).

2

I C

I C data input (MSSP module); input type depends on module setting.

RB5/AN11/RX/DT

RB5

O

I

DIG LATB<5> data output.

TTL PORTB<5> data input; Programmable weak pull-up.

ANA ADC input channel 11.

AN11

RX

I

ST

Asynchronous serial receive data input (USART module).

DT

O

DIG

Synchronous serial data output (USART module); takes priority over

PORT data.

1

I

ST

Synchronous serial data input (USART module). User must configure

as an input.

RB6/SCK/SCL

RB6

SCK

SCL

RB7

0

1

0

1

0

1

0

1

O

I

DIG LATB<6> data output.

TTL PORTB<6> data input; Programmable weak pull-up.

DIG SPI clock output (MSSP module).

O

I

ST

SPI clock input (MSSP module).

2

O

I

DIG I C clock output (MSSP module).

2

I C

I C clock input (MSSP module); input type depends on module setting.

RB7/TX/CK

O

I

DIG LATB<7> data output.

TTL PORTB<7> data input; Programmable weak pull-up.

TX

CK

O

I

DIG

ST

Asynchronous serial transmit data output (USART module).

Synchronous serial clock output (USART module).

Synchronous serial clock input (USART module).

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

I C = Schmitt Trigger input with I C; x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

2

DS40001365F-page 82

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 8-4:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Reset

Values

on page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELH

INTCON

INTCON2

IOCB

—

ANS11

RABIE

—

ANS10

TMR0IF

TMR0IP

ANS9

INT0IF

—

ANS8

RABIF

RABIP

247

244

247

246

247

245

247

246

247

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RABPU

IOCB7

LATB7

RB7

INTEDG0 INTEDG1 INTEDG2

IOCB6

LATB6

RB6

IOCB5

LATB5

RB5

IOCB4

LATB4

RB4

LATB

—

PORTB

RCSTA

SLRCON

SSPCON1

TRISB

SPEN

—

RX9

SREN

—

CREN

—

ADDEN

—

FERR

SLRC

SSPM2

—

OERR

SLRB

SSPM1

—

RX9D

SLRA

SSPM0

—

WCOL

TRISB7

CSRC

WPUB7

SSPOV

TRISB6

TX9

SSPEN

CKP

SSPM3

—

TRISB5 TRISB4

TXEN SYNC

WPUB5 WPUB4

TXSTA

SENDB

—

BRGH

—

TRMT

—

TX9D

—

WPUB

WPUB6

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 83

PIC18(L)F1XK22

All the pins on PORTC are implemented with Schmitt

Trigger input buffer. Each pin is individually

configurable as an input or output.

8.3

PORTC, TRISC and LATC

Registers

PORTC is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC. Setting

a TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., disable the output driver). Clearing a

TRISC bit (= 0) will make the corresponding PORTC

pin an output (i.e., enable the output driver and put the

contents of the output latch on the selected pin).

Note:

On a Power-on Reset, RC<7:6> and

RC<3:0> are configured as analog inputs

and read as ‘0’.

EXAMPLE 8-3:

CLRF

INITIALIZING PORTC

PORTC

; Initialize PORTC by

; clearing output

; data latches

The PORTC Data Latch register (LATC) is also

memory mapped. Read-modify-write operations on the

LATC register read and write the latched output value

for PORTC.

CLRF

LATC

; Alternate method

; to clear output

; data latches

MOVLW

MOVWF

0CFh

; Value used to

; initialize data

; direction

; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

TRISC

REGISTER 8-11: PORTC: PORTC REGISTER

R/W-x

RC7

R/W-x

RC6

R/W-x

RC5

R/W-x

RC4

R/W-x

RC3

R/W-x

RC2

R/W-x

RC1

R/W-x

RC0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

RC<7:0>: PORTC I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 8-12: TRISC: PORTC TRI-STATE REGISTER

R/W-1

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

DS40001365F-page 84

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

REGISTER 8-13: LATC: PORTC DATA LATCH REGISTER

R/W-x

LATC5

R/W-x

LATC2

R/W-x

LATC1

R/W-x

LATC7

LATC6

LATC4

LATC3

LATC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

LATC<7:0>: RB<7:0> Port I/O Output Latch Register bits

 2009-2016 Microchip Technology Inc.

DS40001365F-page 85

PIC18(L)F1XK22

TABLE 8-5:

PORTC I/O SUMMARY

TRIS

I/O

Type

Function

I/O

Description

Setting

RC0/AN4/C2IN+

RC0

0

1

0

1

0

1

0

1

0

x

O

I

DIG

ST

LATC<0> data output.

PORTC<0> data input.

A/D input channel 4.

AN4

C2IN+

RC1

I

ANA

DIG

ST

I

Comparators C2 noninverting input.

LATC<1> data output.

RC1/AN5/

C12IN1-

O

I

PORTC<1> data input.

AN5

C12IN1-

RC2

I

ANA

DIG

ST

A/D input channel 5.

I

Comparators C1 and C2 inverting input, channel 1.

LATC<2> data output.

RC2/AN6/

C12IN2-/P1D

O

I

PORTC<2> data input.

AN6

C12IN2-

P1D

I

ANA

DIG

ST

A/D input channel 6.

I

Comparators C1 and C2 inverting input, channel 2.

ECCP1 Enhanced PWM output, channel D.

LATC<3> data output.

O

I

RC3/AN7/

C12IN3-/P1C/

PGM

RC3

PORTC<3> data input.

AN7

C12IN3-

P1C

I

ANA

DIG

ST

A/D input channel 7.

I

Comparators C1 and C2 inverting input, channel 3.

ECCP1 Enhanced PWM output, channel C.

O

I

Single-Supply Programming mode entry (ICSP™). Enabled by LVP

Configuration bit; all other pin functions disabled.

PGM

RC4

RC4/C2OUT/P1B/

SRNQ

0

1

0

1

0

1

0

1

0

1

0

O

I

DIG

ST

LATC<4> data output.

PORTC<4> data input.

C2OUT

P1B

O

I

DIG

ST

Comparator 2 output.

ECCP1 Enhanced PWM output, channel B.

SR Latch inverted output

LATC<5> data output.

SRNQ

RC5

RC5/CCP1/P1A

PORTC<5> data input.

CCP1

O

I

DIG

ST

ECCP1 compare or PWM output.

ECCP1 capture input.

P1A

RC6

0

O

I

DIG

ST

ECCP1 Enhanced PWM output, channel A.

LATC<6> data output.

RC6/AN8/SS

PORTC<6> data input.

AN8

SS

I

ANA

TTL

DIG

ST

A/D input channel 8.

I

Slave select input for SSP (MSSP module)

LATC<7> data output.

RC7/AN9/SDO

RC7

O

I

PORTC<7> data input.

AN9

I

ANA

DIG

A/D input channel 9.

SDO

O

SPI data output (MSSP module).

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

DS40001365F-page 86

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 8-6:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Reset

Values

on page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSEL

ANS7

—

ANS6

—

ANS5

—

ANS4

—

ANS3

ANS2

ANS1

ANS9

ANS0

ANS8

247

246

244

247

246

247

245

247

245

246

ANSELH

CCP1CON

ANS11

ANS10

P1M1

P1M0

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0

INTCON

INTCON2

INTCON3

LATC

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RABIE TMR0IF INT0IF

RABIF

RABIP

INT1IF

LATC0

RC0

RABPU

INT2IP

LATC7

RC7

INTEDG0 INTEDG1 INTEDG2

—

TMR0IP

—

INT1IP

LATC6

RC6

—

LATC5

RC5

INT2IE

LATC4

RC4

INT1IE

LATC3

RC3

INT2IF

LATC1

RC1

LATC2

RC2

PORTC

PSTRCON

VREFCON1

SLRCON

SSPCON1

TRISC

—

STRSYNC STRD

STRC

STRB

---

STRA

D1NSS

SLRA

D1EN

—

D1LPS

—

DAC1OE

—

---

—

D1PSS1 D1PSS0

SLRC

—

SLRB

WCOL

TRISC7

RD16

SSPOV

TRISC6

T1RUN

—

SSPEN

TRISC5

CKP

TRISC4

SSPM3 SSPM2 SSPM1

SSPM0

TRISC3 TRISC2 TRISC1 TRISC0

T1CON

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

T3CON

 2009-2016 Microchip Technology Inc.

DS40001365F-page 87

PIC18(L)F1XK22

registers. Setting an ANSx bit high will disable the

associated digital input buffer and cause all reads of

that pin to return ‘0’ while allowing analog functions of

that pin to operate correctly.

8.4

Port Analog Control

Some port pins are multiplexed with analog functions

such as the Analog-to-Digital Converter and

comparators. When these I/O pins are to be used as

analog inputs it is necessary to disable the digital input

buffer to avoid excessive current caused by improper

biasing of the digital input. Individual control of the

digital input buffers on pins which share analog

functions is provided by the ANSEL and ANSELH

The state of the ANSx bits has no affect on digital

output functions. A pin with the associated TRISx bit

clear and ANSx bit set will still operate as a digital

output but the Input mode will be analog.

REGISTER 8-14: ANSEL: ANALOG SELECT REGISTER

R/W-1

ANS7

R/W-1

ANS6

R/W-1

ANS5

R/W-1

ANS4

R/W-1

ANS3

R/W-1

ANS2

R/W-1

ANS1

R/W-1

ANS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

ANS7: RC3 Analog Select Control bit

1= Digital input buffer of RC3 is disabled

0= Digital input buffer of RC3 is enabled

ANS6: RC2 Analog Select Control bit

1= Digital input buffer of RC2 is disabled

0= Digital input buffer of RC2 is enabled

ANS5: RC1 Analog Select Control bit

1= Digital input buffer of RC1 is disabled

0= Digital input buffer of RC1 is enabled

ANS4: RC0 Analog Select Control bit

1= Digital input buffer of RC0 is disabled

0= Digital input buffer of RC0 is enabled

ANS3: RA4 Analog Select Control bit

1= Digital input buffer of RA4 is disabled

0= Digital input buffer of RA4 is enabled

ANS2: RA2 Analog Select Control bit

1= Digital input buffer of RA2 is disabled

0= Digital input buffer of RA2 is enabled

ANS1: RA1 Analog Select Control bit

1= Digital input buffer of RA1 is disabled

0= Digital input buffer of RA1 is enabled

ANS0: RA0 Analog Select Control bit

1= Digital input buffer of RA0 is disabled

0= Digital input buffer of RA0 is enabled

DS40001365F-page 88

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PIC18(L)F1XK22

REGISTER 8-15: ANSELH: ANALOG SELECT HIGH REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

ANS11

R/W-1

ANS9

R/W-1

ANS8

ANS10

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3

Unimplemented: Read as ‘0’

ANS11: RB5 Analog Select Control bit

1= Digital input buffer of RB5 is disabled

0= Digital input buffer of RB5 is enabled

bit 2

bit 1

bit 0

ANS10: RB4 Analog Select Control bit

1= Digital input buffer of RB4 is disabled

0= Digital input buffer of RB4 is enabled

ANS9: RC7 Analog Select Control bit

1= Digital input buffer of RC7 is disabled

0= Digital input buffer of RC7 is enabled

ANS8: RC6 Analog Select Control bit

1= Digital input buffer of RC6 is disabled

0= Digital input buffer of RC6 is enabled

 2009-2016 Microchip Technology Inc.

DS40001365F-page 89

PIC18(L)F1XK22

8.5

Port Slew Rate Control

The output slew rate of each port is programmable to

select either the standard transition rate or a reduced

transition rate of 0.1 times the standard to minimize

EMI. The reduced transition time is the default slew

rate for all ports.

REGISTER 8-16: SLRCON: SLEW RATE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

SLRC

R/W-1

SLRB

R/W-1

SLRA

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-3

bit 2

Unimplemented: Read as ‘0’

SLRC: PORTC Slew Rate Control bit

1= All outputs on PORTC slew at 0.1 times the standard rate

0= All outputs on PORTC slew at the standard rate

bit 1

bit 0

SLRB: PORTB Slew Rate Control bit

1= All outputs on PORTB slew at 0.1 times the standard rate

0= All outputs on PORTB slew at the standard rate

SLRA: PORTA Slew Rate Control bit

1= All outputs on PORTA slew at 0.1 times the standard rate⁽¹⁾

0= All outputs on PORTA slew at the standard rate

Note 1: The slew rate of RA4 defaults to standard rate when the pin is used as CLKOUT.

DS40001365F-page 90

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PIC18(L)F1XK22

The T0CON register (Register 9-1) controls all aspects

of the module’s operation, including the prescale

selection. It is both readable and writable.

9.0

TIMER0 MODULE

The Timer0 module incorporates the following features:

• Software selectable operation as a timer or

counter in both 8-bit or 16-bit modes

A simplified block diagram of the Timer0 module in 8-bit

mode is shown in Figure 9-1. Figure 9-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

• Readable and writable registers

• Dedicated 8-bit, software programmable

prescaler

• Selectable clock source (internal or external)

• Edge select for external clock

• Interrupt-on-overflow

REGISTER 9-1:

R/W-1

T0CON: TIMER0 CONTROL REGISTER

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

T0PS2

R/W-1

T0PS1

R/W-1

T0PS0

TMR0ON

bit 7

T08BIT

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

TMR0ON: Timer0 On/Off Control bit

1= Enables Timer0

0= Stops Timer0

T08BIT: Timer0 8-bit/16-bit Control bit

1= Timer0 is configured as an 8-bit timer/counter

0= Timer0 is configured as a 16-bit timer/counter

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (CLKOUT)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Timer0 Prescaler Assignment bit

1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

T0PS<2:0>: Timer0 Prescaler Select bits

111= 1:256 prescale value

110= 1:128 prescale value

101= 1:64 prescale value

100= 1:32 prescale value

011= 1:16 prescale value

010= 1:8 prescale value

001= 1:4 prescale value

000= 1:2 prescale value

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DS40001365F-page 91

PIC18(L)F1XK22

9.1

Timer0 Operation

9.2

Timer0 Reads and Writes in

16-Bit Mode

Timer0 can operate as either a timer or a counter; the

mode is selected with the T0CS bit of the T0CON

register. In Timer mode (T0CS = 0), the module

increments on every clock by default unless a different

prescaler value is selected (see Section 9.3

“Prescaler”). Timer0 incrementing is inhibited for two

instruction cycles following a TMR0 register write. The

user can work around this by adjusting the value written

to the TMR0 register to compensate for the anticipated

missing increments.

TMR0H is not the actual high byte of Timer0 in 16-bit

mode; it is actually a buffered version of the real high

byte of Timer0 which is neither directly readable nor

writable (refer to Figure 9-2). TMR0H is updated with

the contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without the need to verify that the read of the

high and low byte were valid. Invalid reads could

otherwise occur due to a rollover between successive

reads of the high and low byte.

The Counter mode is selected by setting the T0CS bit

(= 1). In this mode, Timer0 increments either on every

rising or falling edge of the T0CKI pin. The

incrementing edge is determined by the Timer0 Source

Edge Select bit, T0SE of the T0CON register; clearing

this bit selects the rising edge. Restrictions on the

external clock input are discussed below.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. Writing

to TMR0H does not directly affect Timer0. Instead, the

high byte of Timer0 is updated with the contents of

TMR0H when a write occurs to TMR0L. This allows all

16 bits of Timer0 to be updated at once.

An external clock source can be used to drive Timer0;

however, it must meet certain requirements (see

Table 26-17) to ensure that the external clock can be

synchronized with the internal phase clock (TOSC).

There is a delay between synchronization and the

onset of incrementing the timer/counter.

FIGURE 9-1:

TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FOSC/4

0

1

0

Set

TMR0IF

on Overflow

Sync with

Internal

Clocks

TMR0L

8

Programmable

Prescaler

T0CKI pin

(2 TCY Delay)

T0SE

T0CS

3

T0PS<2:0>

PSA

8

Internal Data Bus

Note:

Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI. TMR0 Prescaler is set to maximum (1:256),

but on Reset is not assigned to the timer.

DS40001365F-page 92

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 9-2:

TIMER0 BLOCK DIAGRAM (16-BIT MODE)

FOSC/4

0

1

Sync with

Internal

Clocks

Set

TMR0

High Byte

1

TMR0L

TMR0IF

Programmable

Prescaler

on Overflow

T0CKI pin

0

8

(2 TCY Delay)

T0SE

T0CS

3

Read TMR0L

Write TMR0L

T0PS<2:0>

PSA

8

TMR0H

8

Internal Data Bus

Note:

Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI. TMR0 Prescaler is set to maximum (1:256), but on Reset

is not assigned to the timer.

9.3.1

SWITCHING PRESCALER

ASSIGNMENT

9.3

Prescaler

An 8-bit counter is available as a prescaler for the Timer0

module. The prescaler is not directly readable or writable;

its value is set by the PSA and T0PS<2:0> bits of the

T0CON register which determine the prescaler

assignment and prescale ratio.

The prescaler assignment is fully under software

control and can be changed “on-the-fly” during program

execution.

9.4

Timer0 Interrupt

Clearing the PSA bit assigns the prescaler to the

Timer0 module. When the prescaler is assigned,

prescale values from 1:2 through 1:256 in integer

power-of-2 increments are selectable.

The TMR0 interrupt is generated when the TMR0

register overflows from FFh to 00h in 8-bit mode, or

from FFFFh to 0000h in 16-bit mode. This overflow sets

the TMR0IF flag bit. The interrupt can be masked by

clearing the TMR0IE bit of the INTCON register. Before

re-enabling the interrupt, the TMR0IF bit must be

cleared by software in the Interrupt Service Routine.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0, etc.) clear the prescaler count.

Note:

Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count but will not change the prescaler

assignment.

Since Timer0 is shut down in Sleep mode, the TMR0

interrupt cannot awaken the processor from Sleep.

TABLE 9-1:

Name

REGISTERS ASSOCIATED WITH TIMER0

Reset

Values

on page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PORTA

TMR0H

TMR0L

TRISA

GIE/GIEH PEIE/GIEL TMR0IE

RA7 RA6 RA5

INT0IE

RA4

RABIE

RA3

TMR0IF

RA2

INT0IF

RA1

RABIF

RA0

245

248

246

248

246

Timer0 Register, High Byte

Timer0 Register, Low Byte

(1)

—

TRISA5

T0CS

TRISA4

T0SE

—

TRISA2

T0PS2

TRISA1

T0PS1

TRISA0

T0PS0

T0CON

TMR0ON

T08BIT

PSA

Legend: Shaded cells are not used by Timer0.

Note: Unimplemented, read as’1’.

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DS40001365F-page 93

PIC18(L)F1XK22

A simplified block diagram of the Timer1 module is

shown in Figure 10-1. A block diagram of the module’s

operation in Read/Write mode is shown in Figure 10-2.

10.0 TIMER1 MODULE

The Timer1 timer/counter module incorporates the

following features:

Timer1 can also be used to provide Real-Time Clock

(RTC) functionality to applications with only a minimal

addition of external components and code overhead.

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR1H

and TMR1L)

Timer1 is controlled through the T1CON Control

register (Register 10-1). It also contains the Timer1

Oscillator Enable bit (T1OSCEN). Timer1 can be

enabled or disabled by setting or clearing control bit,

TMR1ON of the T1CON register.

• Selectable internal or external clock source and

Timer1 oscillator options

• Interrupt-on-overflow

• Reset on CCP Special Event Trigger

• Device clock status flag (T1RUN)

REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

RD16

R-0

R/W-0

T1RUN

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register read/write of TImer1 in one 16-bit operation

0= Enables register read/write of Timer1 in two 8-bit operations

bit 6

T1RUN: Timer1 System Clock Status bit

1= Main system clock is derived from Timer1 oscillator

0= Main system clock is derived from another source

bit 5-4

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T1OSCEN: Timer1 Oscillator Enable bit

1= Timer1 oscillator is enabled

0= Timer1 oscillator is shut off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from the T13CKI pin (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

DS40001365F-page 94

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PIC18(L)F1XK22

10.1 Timer1 Operation

Timer1 can operate in one of the following modes:

• Timer

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR1CS of the T1CON register. When TMR1CS is

cleared (= 0), Timer1 increments on every internal

instruction cycle (FOSC/4). When the bit is set, Timer1

increments on every rising edge of either the Timer1

external clock input or the Timer1 oscillator, if enabled.

When the Timer1 oscillator is enabled, the digital

circuitry associated with the OSC1 and OSC2 pins is

disabled. This means the values of TRISA<5:4> are

ignored and the pins are read as ‘0’.

FIGURE 10-1:

TIMER1 BLOCK DIAGRAM

Timer1 Oscillator

Timer1 Clock Input

1

On/Off

OSC1/T13CKI

OSC2

1

Synchronize

Prescaler

1, 2, 4, 8

0

FOSC/4

Internal

Clock

Detect

0

2

Sleep Input

Timer1

TMR1CS

INTOSC

On/Off

Without CLKOUT

T1OSCEN⁽¹⁾

T1CKPS<1:0>

T1SYNC

TMR1ON

Set

TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

TMR1L

TMR1IF

on Overflow

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 95

PIC18(L)F1XK22

FIGURE 10-2:

TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator

Timer1 Clock Input

1

0

OSC1/T13CKI

OSC2

1

0

Synchronize

Detect

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

2

Sleep Input

TMR1CS

INTOSC

Without CLKOUT

T1OSCEN⁽¹⁾

Timer1

On/Off

T1CKPS<1:0>

T1SYNC

TMR1ON

Set

TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

TMR1L

TMR1IF

on Overflow

8

Read TMR1L

Write TMR1L

8

TMR1H

8

Internal Data Bus

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

DS40001365F-page 96

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PIC18(L)F1XK22

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC without CLKOUT),

Timer1 can use the LP oscillator as a clock source.

10.2 Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 10-2). When the RD16 control bit of the

T1CON register is set, the address for TMR1H is

mapped to a buffer register for the high byte of Timer1.

A read from TMR1L will load the contents of the high

byte of Timer1 into the Timer1 high byte buffer. This

provides the user with the ability to accurately read all

16 bits of Timer1 without the need to determine

whether a read of the high byte, followed by a read of

the low byte, has become invalid due to a rollover or

carry between reads.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON= 1) when T1CKI

is low.

Writing to TMR1H does not directly affect Timer1.

Instead, the high byte of Timer1 is updated with the

contents of TMR1H when a write occurs to TMR1L.

This allows all 16 bits of Timer1 to be updated at once.

Note:

See Figure 9-2.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

10.4 Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated

between pins OSC1 (input) and OSC2 (amplifier output).

It is enabled by setting the Timer1 Oscillator Enable bit,

T1OSCEN of the T1CON register. The oscillator is a

low-power circuit rated for 32 kHz crystals. It will

continue to run during all power-managed modes. The

circuit for a typical LP oscillator is shown in Figure 10-3.

Table 10-1 shows the capacitor selection for the Timer1

oscillator.

10.3 Clock Source Selection

The TMR1CS bit of the T1CON register is used to select

the clock source. When TMR1CS = 0, the clock source

is FOSC/4. When TMR1CS = 1, the clock source is

supplied externally.

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is derived from the internal

oscillator or when the oscillator is in the LP mode. The

user must provide a software time delay to ensure

proper oscillator start-up.

Clock

Source

FOSC

Mode

T1OSCEN

TMR1CS

FOSC/4

x

0

1

xxx

0

1

T1CKI pin

T1LPOSC

FIGURE 10-3:

EXTERNAL

LP or

INTOSCIO

COMPONENTS FOR THE

TIMER1 LP OSCILLATOR

10.3.1

INTERNAL CLOCK SOURCE

C1

27 pF

PIC^®MCU

OSC1

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

XTAL

32.768 kHz

10.3.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

OSC2

C2

27 pF

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run asynchronously.

Note:

See the Notes with Table 10-1 for additional

information about capacitor selection.

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DS40001365F-page 97

PIC18(L)F1XK22

TABLE 10-1: CAPACITOR SELECTION FOR

THE TIMER OSCILLATOR

10.7 Using Timer1 as a Real-Time Clock

Adding an external LP oscillator to Timer1 (such as the

one described in Section 10.4 “Timer1 Oscillator”

above) gives users the option to include RTC

functionality to their applications. This is accomplished

with an inexpensive watch crystal to provide an

accurate time base and several lines of application

code to calculate the time. When operating in Sleep

mode and using a battery or supercapacitor as a power

source, it can completely eliminate the need for a

separate RTC device and battery backup.

Osc Type

Freq.

C1

C2

LP

32 kHz

27 pF⁽¹⁾

Note 1: Microchip suggests these values only as

a starting point in validating the oscillator

circuit.

2: Higher capacitance increases the

stability of the oscillator but also

increases the start-up time.

The application code routine, RTCisr, shown in

Example 10-1, demonstrates a simple method to

increment a counter at one-second intervals using an

Interrupt Service Routine. Incrementing the TMR1

register pair to overflow triggers the interrupt and calls

the routine, which increments the seconds counter by

one; additional counters for minutes and hours are

incremented on overflows of the less significant

counters.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

4: Capacitor values are for design guidance

only.

10.5 Timer1 Interrupt

Since the register pair is 16-bit wide, a 32.768 kHz

clock source will take two seconds to count up to

overflow. To force the overflow at the required

one-second intervals, it is necessary to pre-load it; the

simplest method is to set the MSb of TMR1H with a

BSFinstruction. Note that the TMR1L register is never

preloaded or altered; doing so may introduce

cumulative error over many cycles.

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow,

which is latched in the TMR1IF interrupt flag bit of the

PIR1 register. This interrupt can be enabled or disabled

by setting or clearing the TMR1IE Interrupt Enable bit

of the PIE1 register.

For this method to be accurate, Timer1 must operate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1), as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

10.6 Resetting Timer1 Using the CCP

Special Event Trigger

If either of the CCP modules is configured to use Timer1

and generate a Special Event Trigger in Compare mode

(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will

reset Timer1. The trigger from CCP2 will also start an

A/D conversion if the A/D module is enabled (see

Section 13.3.4 “Special Event Trigger” for more

information).

The module must be configured as either a timer or a

synchronous counter to take advantage of this feature.

When used this way, the CCPRH:CCPRL register pair

effectively becomes a period register for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special Event Trigger, the write operation will take

precedence.

Note:

The Special Event Triggers from the

CCP2 module will not set the TMR1IF

interrupt flag bit of the PIR1 register.

DS40001365F-page 98

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

EXAMPLE 10-1:

IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

RTCinit

MOVLW

MOVWF

CLRF

80h

TMR1H

TMR1L

; Preload TMR1 register pair

; for 1 second overflow

MOVLW

MOVWF

CLRF

b’00001111’

T1CON

secs

; Configure for external clock,

; Asynchronous operation, external oscillator

; Initialize timekeeping registers

;

CLRF

mins

MOVLW

MOVWF

BSF

.12

hours

PIE1, TMR1IE

; Enable Timer1 interrupt

RETURN

RTCisr

BSF

BCF

INCF

MOVLW

CPFSGT

RETURN

CLRF

TMR1H, 7

PIR1, TMR1IF

secs, F

.59

; Preload for 1 sec overflow

; Clear interrupt flag

; Increment seconds

; 60 seconds elapsed?

secs

; No, done

secs

mins, F

.59

; Clear seconds

; Increment minutes

; 60 minutes elapsed?

INCF

MOVLW

CPFSGT

RETURN

CLRF

mins

; No, done

mins

hours, F

.23

; clear minutes

; Increment hours

; 24 hours elapsed?

INCF

MOVLW

CPFSGT

RETURN

CLRF

hours

; No, done

; Reset hours

; Done

hours

RETURN

TABLE 10-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

IPR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIP

TXIE

TXIF

RABIE

SSPIP

SSPIE

SSPIF

TMR0IF

CCP1IP

CCP1IE

CCP1IF

INT0IF

TMR2IP

TMR2IE

TMR2IF

RABIF

TMR1IP

TMR1IE

TMR1IF

245

248

246

248

246

—

ADIP

ADIE

ADIF

RCIP

RCIE

RCIF

PIE1

PIR1

TMR1H

TMR1L

TRISA

T1CON

Timer1 Register, High Byte

Timer1 Register, Low Byte

(1)

—

TRISA5

TRISA4

—

TRISA2

TRISA1

TRISA0

RD16

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Note 1: Unimplemented, read as’1’.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 99

PIC18(L)F1XK22

11.1 Timer2 Operation

11.0 TIMER2 MODULE

In normal operation, TMR2 is incremented from 00h on

each clock (FOSC/4). A 4-bit counter/prescaler on the

clock input gives direct input, divide-by-4 and

divide-by-16 prescale options; these are selected by

the prescaler control bits, T2CKPS<1:0> of the T2CON

register. The value of TMR2 is compared to that of the

period register, PR2, on each clock cycle. When the

two values match, the comparator generates a match

signal as the timer output. This signal also resets the

value of TMR2 to 00h on the next cycle and drives the

output counter/postscaler (see Section 11.2 “Timer2

Interrupt”).

The Timer2 module timer incorporates the following

features:

• 8-bit timer and period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4 and

1:16)

• Software programmable postscaler (1:1 through

1:16)

• Interrupt on TMR2-to-PR2 match

• Optional use as the shift clock for the MSSP

module

The TMR2 and PR2 registers are both directly readable

and writable. The TMR2 register is cleared on any

device Reset, whereas the PR2 register initializes to

FFh. Both the prescaler and postscaler counters are

cleared on the following events:

The module is controlled through the T2CON register

(Register 11-1), which enables or disables the timer

and configures the prescaler and postscaler. Timer2

can be shut off by clearing control bit, TMR2ON of the

T2CON register, to minimize power consumption.

• a write to the TMR2 register

• a write to the T2CON register

A simplified block diagram of the module is shown in

Figure 11-1.

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 11-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

R/W-0

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0

TMR2ON

T2CKPS1

T2CKPS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-3

T2OUTPS<3:0>: Timer2 Output Postscale Select bits

0000= 1:1 Postscale

0001= 1:2 Postscale

•

1111= 1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

DS40001365F-page 100

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

11.2 Timer2 Interrupt

11.3 Timer2 Output

Timer2 can also generate an optional device interrupt.

The Timer2 output signal (TMR2-to-PR2 match)

The unscaled output of TMR2 is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode.

provides

the

input

for

the

4-bit

output

counter/postscaler. This counter generates the TMR2

match interrupt flag which is latched in TMR2IF of the

PIR1 register. The interrupt is enabled by setting the

TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1

register.

Timer2 can be optionally used as the shift clock source

for the MSSP module operating in SPI mode.

Additional information is provided in Section 14.0

“Master Synchronous Serial Port (MSSP) Module”.

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, T2OUTPS<3:0> of the T2CON register.

FIGURE 11-1:

TIMER2 BLOCK DIAGRAM

4

1:1 to 1:16

Set TMR2IF

Postscaler

T2OUTPS<3:0>

T2CKPS<1:0>

2

TMR2 Output

(to PWM or MSSP)

TMR2/PR2

Match

Reset

1:1, 1:4, 1:16

Prescaler

PR2

FOSC/4

Comparator

TMR2

8

Internal Data Bus

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIP

TXIE

TXIF

RABIE

SSPIP

SSPIE

SSPIF

TMR0IF

CCP1IP

CCP1IE

CCP1IF

INT0IF

TMR2IP

TMR2IE

TMR2IF

RABIF

TMR1IP

TMR1IE

TMR1IF

245

248

246

IPR1

—

ADIP

ADIE

ADIF

RCIP

RCIE

RCIF

PIE1

PIR1

PR2

Timer2 Period Register

Timer2 Register

TMR2

T2CON

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 101

PIC18(L)F1XK22

A simplified block diagram of the Timer3 module is

shown in Figure 12-1. A block diagram of the module’s

operation in Read/Write mode is shown in Figure 12-2.

12.0 TIMER3 MODULE

The Timer3 module timer/counter incorporates these

features:

The Timer3 module is controlled through the T3CON

register (Register 12-1). It also selects the clock source

options for the CCP modules (see Section 13.1.1

“CCP Module and Timer Resources” for more

information).

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR3H

and TMR3L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

• Module Reset on CCP Special Event Trigger

REGISTER 12-1: T3CON: TIMER3 CONTROL REGISTER

R/W-0

RD16

U-0

—

R/W-0

T3CKPS1

T3CKPS0

T3CCP1

T3SYNC

TMR3CS

TMR3ON

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register read/write of Timer3 in one 16-bit operation

0= Enables register read/write of Timer3 in two 8-bit operations

bit 6

Unimplemented: Read as ‘0’

bit 5-4

T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T3CCP1: Timer3 and Timer1 to CCP1 Enable bits

1= Timer3 is the clock source for compare/capture of ECCP1

0= Timer1 is the clock source for compare/capture of ECCP1

T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the device clock comes from Timer1/Timer3.)

When TMR3CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1

bit 0

TMR3CS: Timer3 Clock Source Select bit

1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first

falling edge)

0= Internal clock (FOSC/4)

TMR3ON: Timer3 On bit

1= Enables Timer3

0= Stops Timer3

DS40001365F-page 102

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

12.1 Timer3 Operation

Timer3 can operate in one of three modes:

• Timer

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR3CS of the T3CON register. When TMR3CS is

cleared (= 0), Timer3 increments on every internal

instruction cycle (FOSC/4). When the bit is set, Timer3

increments on every rising edge of the Timer1 external

clock input or the Timer1 oscillator, if enabled.

As with Timer1, the digital circuitry associated with the

OSC1 and OSC2 pins is disabled when the Timer1

oscillator is enabled. This means the values of

TRISA<5:4> are ignored and the pins are read as ‘0’.

FIGURE 12-1:

TIMER3 BLOCK DIAGRAM

Timer1 Oscillator

Timer1 Clock Input

1

OSC1/T13CKI

OSC2

1

0

Synchronize

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

0

Detect

2

Sleep Input

Timer3

On/Off

TMR3CS

INTOSC

Without CLKOUT

T1OSCEN⁽¹⁾

T3CKPS<1:0>

T3SYNC

TMR3ON

CCP1 Special Event Trigger

CCP1 Select from T3CON<3>

Clear TMR3

Set

TMR3

High Byte

TMR3L

TMR3IF

on Overflow

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 103

PIC18(L)F1XK22

FIGURE 12-2:

TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator

Timer1 Clock Input

1

0

OSC1/T1OSI

OSC2

1

0

Synchronize

Detect

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

2

Sleep Input

TMR3CS

INTOSC

Without CLKOUT

T1OSCEN⁽¹⁾

Timer3

On/Off

T3CKPS<1:0>

T3SYNC

TMR3ON

CCP1 Special Event Trigger

CCP1 Select from T3CON<3>

Clear TMR3

Set

TMR3

High Byte

TMR3L

TMR3IF

on Overflow

8

Read TMR1L

Write TMR1L

8

TMR3H

8

Internal Data Bus

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

DS40001365F-page 104

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

12.2 Timer3 16-Bit Read/Write Mode

12.4 Timer3 Interrupt

Timer3 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit of the

T3CON register is set, the address for TMR3H is

mapped to a buffer register for the high byte of Timer3.

A read from TMR3L will load the contents of the high

byte of Timer3 into the Timer3 High Byte Buffer register.

This provides the user with the ability to accurately read

all 16 bits of Timer1 without having to determine

whether a read of the high byte, followed by a read of

the low byte, has become invalid due to a rollover

between reads.

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and overflows to 0000h. The

Timer3 interrupt, if enabled, is generated on overflow

and is latched in interrupt flag bit, TMR3IF of the PIR2

register. This interrupt can be enabled or disabled by

setting or clearing the Timer3 Interrupt Enable bit,

TMR3IE of the PIE2 register.

12.5 Resetting Timer3 Using the CCP

Special Event Trigger

If CCP1 module is configured to use Timer3 and to

generate a Special Event Trigger in Compare mode

(CCP1M<3:0>), this signal will reset Timer3. It will also

start an A/D conversion if the A/D module is enabled

(see Section 16.2.8 “Special Event Trigger” for more

information).

A write to the high byte of Timer3 must also take place

through the TMR3H Buffer register. The Timer3 high

byte is updated with the contents of TMR3H when a

write occurs to TMR3L. This allows a user to write all

16 bits to both the high and low bytes of Timer3 at once.

The high byte of Timer3 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer3 High Byte Buffer register.

The module must be configured as either a timer or

synchronous counter to take advantage of this feature.

When used this way, the CCPR1H:CCPR1L register

pair effectively becomes a period register for Timer3.

Writes to TMR3H do not clear the Timer3 prescaler.

The prescaler is only cleared on writes to TMR3L.

If Timer3 is running in Asynchronous Counter mode,

the Reset operation may not work.

12.3 Using the Timer1 Oscillator as the

Timer3 Clock Source

In the event that a write to Timer3 coincides with a

Special Event Trigger from a CCP module, the write will

take precedence.

The Timer1 internal oscillator may be used as the clock

source for Timer3. The Timer1 oscillator is enabled by

setting the T1OSCEN bit of the T1CON register. To use

it as the Timer3 clock source, the TMR3CS bit must

also be set. As previously noted, this also configures

Timer3 to increment on every rising edge of the

oscillator source.

The Timer1 oscillator is described in Section 10.0

“Timer1 Module”.

TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

IPR2

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

EEIP

EEIE

EEIF

RABIE

BCLIP

BCLIE

BCLIF

TMR0IF

INT0IF

TMR3IP

TMR3IE

TMR3IF

RABIF

—

245

248

247

248

246

247

OSCFIP

OSCFIE

OSCFIF

C1IP

C1IE

C1IF

C2IP

C2IE

C2IF

—

PIE2

—

PIR2

—

TMR3H

TMR3L

TRISA

T1CON

T3CON

Timer3 Register, High Byte

Timer3 Register, Low Byte

(1)

—

TRISA5

TRISA4

—

TRISA2

TRISA1

TRISA0

RD16

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

—

T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

Note 1: Unimplemented, read as ‘1’.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 105

PIC18(L)F1XK22

CCP1 is implemented as a standard CCP module with

enhanced PWM capabilities. These include:

13.0 ENHANCED

CAPTURE/COMPARE/PWM

(ECCP) MODULE

• Provision for two or four output channels

• Output steering

PIC18(L)F1XK22

devices

have

one

ECCP

• Programmable polarity

(Capture/Compare/PWM) module. The module

contains a 16-bit register which can operate as a 16-bit

Capture register, a 16-bit Compare register or a PWM

Master/Slave Duty Cycle register.

• Programmable dead-band control

• Automatic shutdown and restart

The enhanced features are discussed in detail in

Section 13.4 “PWM (Enhanced Mode)”.

REGISTER 13-1: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER

R/W-0

P1M1

R/W-0

P1M0

R/W-0

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

P1M<1:0>: Enhanced PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

xx= P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:

00= Single output: P1A, P1B, P1C and P1D controlled by steering (See Section 13.4.7 “Pulse Steering

Mode”).

01= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive

10= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins

11= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in

CCPR1L.

bit 3-0

CCP1M<3:0>: Enhanced CCP Mode Select bits

0000= Capture/Compare/PWM off (resets ECCP module)

0001= Reserved

0010= Compare mode, toggle output on match

0011= Reserved

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)

1001= Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)

1010= Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state

1011= Compare mode, trigger special event (ECCP resets TMR1 or TMR3, start A/D conversion, sets

CC1IF bit)

1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low

DS40001365F-page 106

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

In addition to the expanded range of modes available

through the CCP1CON register and ECCP1AS

register, the ECCP module has two additional registers

associated with Enhanced PWM operation and

auto-shutdown features. They are:

13.2 Capture Mode

In Capture mode, the CCPR1H:CCPR1L register pair

captures the 16-bit value of the TMR1 or TMR3

registers when an event occurs on the corresponding

CCP1 pin. An event is defined as one of the following:

• PWM1CON (Dead-band delay)

• PSTRCON (Output steering)

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

13.1 ECCP Outputs and Configuration

The enhanced CCP module may have up to four PWM

outputs, depending on the selected operating mode.

These outputs, designated P1A through P1D, are

multiplexed with I/O pins on PORTC. The outputs that

are active depend on the CCP operating mode

selected. The pin assignments are summarized in

Table 13-2.

The event is selected by the mode select bits,

CCP1M<3:0> of the CCP1CON register. When a

capture is made, the interrupt request flag bit, CCP1IF,

is set; it must be cleared by software. If another capture

occurs before the value in register CCPR1 is read, the

old captured value is overwritten by the new captured

value.

To configure the I/O pins as PWM outputs, the proper

PWM mode must be selected by setting the P1M<1:0>

and CCP1M<3:0> bits. The appropriate TRISC

direction bits for the port pins must also be set as

outputs.

13.2.1

CCP PIN CONFIGURATION

In Capture mode, the appropriate CCP1 pin should be

configured as an input by setting the corresponding

TRIS direction bit.

13.1.1

CCP MODULE AND TIMER

RESOURCES

Note:

If the CCP1 pin is configured as an output,

a write to the port can cause a capture

condition.

The CCP modules utilize Timers 1, 2 or 3, depending

on the mode selected. Timer1 and Timer3 are available

to modules in Capture or Compare modes, while

Timer2 is available for modules in PWM mode.

13.2.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode or

Synchronized Counter mode. In Asynchronous Counter

mode, the capture operation may not work. The timer to

be used with each CCP module is selected in the T3CON

register (see Section 13.1.1 “CCP Module and Timer

Resources”).

TABLE 13-1: CCP MODE – TIMER

RESOURCE

CCP/ECCP Mode

Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

13.2.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP1IE interrupt enable bit clear to avoid false

interrupts. The interrupt flag bit, CCP1IF, should also

be cleared following any such change in operating

mode.

The assignment of a particular timer to a module is

determined by the Timer-to-CCP enable bits in the

T3CON register (Register 12-1). The interactions

between the two modules are summarized in

Figure 13-1. In Asynchronous Counter mode, the

capture operation will not work reliably.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 107

PIC18(L)F1XK22

13.2.4

CCP PRESCALER

There are four prescaler settings in Capture mode; they

are specified as part of the operating mode selected by

the mode select bits (CCP1M<3:0>). Whenever the

CCP module is turned off or Capture mode is disabled,

the prescaler counter is cleared. This means that any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

a

non-zero prescaler. Example 13-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 13-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF

CCP1CON

; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP1CON

; Load CCP1CON with

; this value

FIGURE 13-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

TMR3H

TMR3

TMR3L

CCPR1L

TMR1L

Set CCP1IF

T3CCP1

Enable

CCP1 pin

Prescaler

 1, 4, 16

and

Edge Detect

CCPR1H

TMR1

Enable

T3CCP1

TMR1H

4

CCP1CON<3:0>

Q1:Q4

4

DS40001365F-page 108

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

13.3.2

TIMER1/TIMER3 MODE SELECTION

13.3 Compare Mode

Timer1 and/or Timer3 must be running in Timer mode

or Synchronized Counter mode if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation will not work reliably.

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against either the TMR1 or TMR3

register pair value. When a match occurs, the CCP1

pin can be:

• Driven high

13.3.3

SOFTWARE INTERRUPT MODE

• Driven low

When the Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the CCP1 pin is not affected.

Only the CCP1IF interrupt flag is affected.

• Toggled (high-to-low or low-to-high)

• Remain unchanged (that is, reflects the state of

the I/O latch)

13.3.4

SPECIAL EVENT TRIGGER

The action on the pin is based on the value of the mode

select bits (CCP1M<3:0>). At the same time, the

interrupt flag bit, CCP1IF, is set.

The CCP module is equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Compare mode to trigger actions by other modules.

The Special Event Trigger is enabled by selecting

the Compare Special Event Trigger mode

(CCP1M<3:0> = 1011).

13.3.1

CCP PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the appropriate TRIS bit.

The Special Event Trigger resets the timer register pair

for whichever timer resource is currently assigned as the

module’s time base. This allows the CCPR1 registers to

serve as a programmable period register for either timer.

Note:

Clearing the CCP1CON register will force

the CCP1 compare output latch

(depending on device configuration) to the

default low level. This is not the PORTC

I/O DATA latch.

The Special Event Trigger can also start an A/D

conversion. In order to do this, the A/D converter must

already be enabled.

FIGURE 13-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

TMR1H

TMR1L

TMR3L

0

1

Special Event Trigger

(Timer1/Timer3 Reset, A/D Trigger)

TMR3H

T3CCP1

Set CCP1IF

CCP1 pin

S

R

Q

Compare

Match

Output

Logic

Comparator

TRIS

Output Enable

4

CCPR1H

CCPR1L

CCP1CON<3:0>

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DS40001365F-page 109

PIC18(L)F1XK22

The PWM outputs are multiplexed with I/O pins and are

designated P1A, P1B, P1C and P1D. The polarity of the

PWM pins is configurable and is selected by setting the

CCP1M bits in the CCP1CON register appropriately.

13.4 PWM (Enhanced Mode)

The Enhanced PWM mode can generate a PWM signal

on up to four different output pins with up to 10-bits of

resolution. It can do this through four different PWM

output modes:

Table 13-1 shows the pin assignments for each

Enhanced PWM mode.

• Single PWM

Figure 13-3 shows an example of a simplified block

diagram of the Enhanced PWM module.

• Half-Bridge PWM

• Full-Bridge PWM, Forward mode

• Full-Bridge PWM, Reverse mode

Note:

To prevent the generation of an

incomplete waveform when the PWM is

first enabled, the ECCP module waits until

the start of a new PWM period before

generating a PWM signal.

To select an Enhanced PWM mode, the P1M bits of the

CCP1CON register must be set appropriately.

FIGURE 13-3:

EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

DC1B<1:0>

P1M<1:0>

CCP1M<3:0>

4

Duty Cycle Registers

2

CCPR1L

CCP1/P1A

P1B

TRIS

CCPR1H (Slave)

Comparator

P1B

Output

Controller

R

S

Q

P1C

(1)

TMR2

P1D

Comparator

PR2

Clear Timer2,

toggle PWM pin and

latch duty cycle

PWM1CON

Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit

time base.

Note 1: The TRIS register value for each PWM

output must be configured appropriately.

2: Any pin not used by an Enhanced PWM

mode is available for alternate pin

functions.

TABLE 13-2: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

ECCP Mode

P1M<1:0>

CCP1/P1A

P1B

P1C

P1D

Single

00

10

01

11

Yes⁽¹⁾

Yes

Yes⁽¹⁾

Yes

Yes⁽¹⁾

No

Yes⁽¹⁾

No

Half-Bridge

Full-Bridge, Forward

Full-Bridge, Reverse

Yes

Note 1: Outputs are enabled by pulse steering in Single mode. See Register 13-4.

DS40001365F-page 110

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 13-4:

EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)

PR2+1

Pulse

Width

0

Signal

P1M<1:0>

Period

P1A Modulated

(Single Output)

00

10

Delay⁽¹⁾

P1A Modulated

P1B Modulated

P1A Active

(Half-Bridge)

P1B Inactive

(Full-Bridge,

Forward)

01

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

(Full-Bridge,

Reverse)

11

P1D Inactive

Relationships:

•

Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

Delay = 4 * TOSC * (PWM1CON<6:0>)

Note 1: Dead-band delay is programmed using the PWM1CON register (Section 13.4.6 “Programmable Dead-Band Delay

Mode”).

 2009-2016 Microchip Technology Inc.

DS40001365F-page 111

PIC18(L)F1XK22

FIGURE 13-5:

EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

PR2+1

Pulse

Width

0

Signal

P1M<1:0>

Period

P1A Modulated

P1B Modulated

P1A Active

(Single Output)

00

10

Delay⁽¹⁾

(Half-Bridge)

(Full-Bridge,

Forward)

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

01

(Full-Bridge,

Reverse)

11

P1D Inactive

Relationships:

•

Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

Delay = 4 * TOSC * (PWM1CON<6:0>)

Note 1: Dead-band delay is programmed using the PWM1CON register (Section 13.4.6 “Programmable Dead-Band Delay

Mode”).

DS40001365F-page 112

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PIC18(L)F1XK22

Since the P1A and P1B outputs are multiplexed with

the PORT data latches, the associated TRIS bits must

be cleared to configure P1A and P1B as outputs.

13.4.1

HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to

drive push-pull loads. The PWM output signal is output

on the CCP1/P1A pin, while the complementary PWM

output signal is output on the P1B pin (see

Figure 13-6). This mode can be used for half-bridge

applications, as shown in Figure 13-7, or for full-bridge

applications, where four power switches are being

modulated with two PWM signals.

FIGURE 13-6:

EXAMPLE OF

HALF-BRIDGE PWM

OUTPUT

Period

Pulse Width

In Half-Bridge mode, the programmable dead-band delay

can be used to prevent shoot-through current in

half-bridge power devices. The value of the PDC<6:0>

bits of the PWM1CON register sets the number of

instruction cycles before the output is driven active. If the

value is greater than the duty cycle, the corresponding

output remains inactive during the entire cycle. See

Section 13.4.6 “Programmable Dead-Band Delay

Mode” for more details of the dead-band delay

operations.

(2)

P1A

td

P1B

(1)

td = Dead-Band Delay

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

FIGURE 13-7:

EXAMPLE OF HALF-BRIDGE APPLICATIONS

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

+

-

P1A

Load

FET

Driver

+

-

P1B

Half-Bridge Output Driving a Full-Bridge Circuit

V+

FET

Driver

FET

Driver

P1A

Load

FET

Driver

P1B

 2009-2016 Microchip Technology Inc.

DS40001365F-page 113

PIC18(L)F1XK22

13.4.2

FULL-BRIDGE MODE

In Full-Bridge mode, all four pins are used as outputs.

An example of Full-Bridge application is shown in

Figure 13-8.

In the Forward mode, pin CCP1/P1A is driven to its

active state, pin P1D is modulated, while P1B and P1C

will be driven to their inactive state as shown in

Figure 13-9.

In the Reverse mode, P1C is driven to its active state,

pin P1B is modulated, while P1A and P1D will be driven

to their inactive state as shown Figure 13-9.

P1A, P1B, P1C and P1D outputs are multiplexed with

the PORT data latches. The associated TRIS bits must

be cleared to configure the P1A, P1B, P1C and P1D

pins as outputs.

FIGURE 13-8:

EXAMPLE OF FULL-BRIDGE APPLICATION

V+

QC

QA

FET

Driver

FET

Driver

P1A

P1B

Load

FET

Driver

FET

Driver

P1C

P1D

QD

QB

V-

DS40001365F-page 114

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PIC18(L)F1XK22

FIGURE 13-9:

EXAMPLE OF FULL-BRIDGE PWM OUTPUT

Forward Mode

Period

(2)

P1A

Pulse Width

(2)

P1B

(2)

P1C

(2)

P1D

(1)

Reverse Mode

Period

Pulse Width

(2)

P1A

(2)

P1B

(2)

P1C

(2)

P1D

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

2: Output signal is shown as active-high.

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PIC18(L)F1XK22

The Full-Bridge mode does not provide dead-band

delay. As one output is modulated at a time, dead-band

delay is generally not required. There is a situation

where dead-band delay is required. This situation

occurs when both of the following conditions are true:

13.4.2.1

Direction Change in Full-Bridge

Mode

In the Full-Bridge mode, the P1M1 bit in the CCP1CON

register allows users to control the forward/reverse

direction. When the application firmware changes this

direction control bit, the module will change to the new

direction on the next PWM cycle.

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, including

the power device and driver circuit, is greater

than the turn on time.

A direction change is initiated in software by changing

the P1M1 bit of the CCP1CON register. The following

sequence occurs prior to the end of the current PWM

period:

Figure 13-11 shows an example of the PWM direction

changing from forward to reverse, at a near 100% duty

cycle. In this example, at time t1, the output P1A and

P1D become inactive, while output P1C becomes

active. Since the turn off time of the power devices is

longer than the turn on time, a shoot-through current

will flow through power devices QC and QD (see

Figure 13-8) for the duration of ‘t’. The same

phenomenon will occur to power devices QA and QB

for PWM direction change from reverse to forward.

• The modulated outputs (P1B and P1D) are placed

in their inactive state.

• The associated unmodulated outputs (P1A and

P1C) are switched to drive in the opposite

direction.

• PWM modulation resumes at the beginning of the

next period.

See Figure 13-10 for an illustration of this sequence.

If changing PWM direction at high duty cycle is required

for an application, two possible solutions for eliminating

the shoot-through current are:

1. Reduce PWM duty cycle for one PWM period

before changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

FIGURE 13-10:

EXAMPLE OF PWM DIRECTION CHANGE

(1)

Period

Signal

P1A (Active-High)

P1B (Active-High)

Pulse Width

P1C (Active-High)

P1D (Active-High)

(2)

Pulse Width

Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.

2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The

modulated P1B and P1D signals are inactive at this time. The length of this time is (1/FOSC)  TMR2 prescale

value.

DS40001365F-page 116

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 13-11:

EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period

Reverse Period

t1

P1A

P1B

PW

P1C

P1D

PW

TON

External Switch C

External Switch D

TOFF

Potential

T = TOFF – TON

Shoot-Through Current

Note 1: All signals are shown as active-high.

2: TON is the turn on delay of power switch QC and its driver.

3: TOFF is the turn off delay of power switch QD and its driver.

The P1A, P1B, P1C and P1D output latches may not be

in the proper states when the PWM module is

initialized. Enabling the PWM pin output drivers at the

same time as the Enhanced PWM modes may cause

damage to the application circuit. The Enhanced PWM

modes must be enabled in the proper Output mode and

complete a full PWM cycle before enabling the PWM

pin output drivers. The completion of a full PWM cycle

is indicated by the TMR2IF bit of the PIR1 register

being set as the second PWM period begins.

13.4.3

START-UP CONSIDERATIONS

When any PWM mode is used, the application

hardware must use the proper external pull-up and/or

pull-down resistors on the PWM output pins.

Note:

When the microcontroller is released from

Reset, all of the I/O pins are in the

high-impedance state. The external

circuits must keep the power switch

devices in the Off state until the

microcontroller drives the I/O pins with the

proper signal levels or activates the PWM

output(s).

The CCP1M<1:0> bits of the CCP1CON register allow

the user to choose whether the PWM output signals are

active-high or active-low for each pair of PWM output pins

(P1A/P1C and P1B/P1D). The PWM output polarities

must be selected before the PWM pin output drivers are

enabled. Changing the polarity configuration while the

PWM pin output drivers are enable is not recommended

since it may result in damage to the application circuits.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 117

PIC18(L)F1XK22

When a shutdown event occurs, two things happen:

13.4.4

ENHANCED PWM

AUTO-SHUTDOWN MODE

The ECCPASE bit is set to ‘1’. The ECCPASE will

remain set until cleared in firmware or an auto-restart

occurs (see Section 13.4.5 “Auto-Restart Mode”).

The PWM mode supports an Auto-Shutdown mode that

will disable the PWM outputs when an external

shutdown event occurs. Auto-Shutdown mode places

the PWM output pins into a predetermined state. This

mode is used to help prevent the PWM from damaging

the application.

The enabled PWM pins are asynchronously placed in

their shutdown states. The PWM output pins are

grouped into pairs [P1A/P1C] and [P1B/P1D]. The state

of each pin pair is determined by the PSSAC and

PSSBD bits of the ECCPAS register. Each pin pair may

be placed into one of three states:

The auto-shutdown sources are selected using the

ECCPAS<2:0> bits of the ECCPAS register. A shutdown

event may be generated by:

• Drive logic ‘1’

• A logic ‘0’ on the INT0 pin

• Drive logic ‘0’

• A logic ‘1’ on a comparator (Cx) output

• Tri-state (high-impedance)

A shutdown condition is indicated by the ECCPASE

(Auto-Shutdown Event Status) bit of the ECCPAS

register. If the bit is a ‘0’, the PWM pins are operating

normally. If the bit is a ‘1’, the PWM outputs are in the

shutdown state.

REGISTER 13-2: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN

CONTROL REGISTER

R/W-0

ECCPASE

ECCPAS2

ECCPAS1

ECCPAS0

PSSAC1

PSSAC0

PSSBD1

PSSBD0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

ECCPASE: ECCP Auto-Shutdown Event Status bit

1= A shutdown event has occurred; ECCP outputs are in shutdown state

0= ECCP outputs are operating

bit 6-4

ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits

000= Auto-Shutdown is disabled

001= Comparator C1OUT output is high

010= Comparator C2OUT output is high

011= Either Comparator C1OUT or C2OUT is high

100= VIL on INT0 pin

101= VIL on INT0 pin or Comparator C1OUT output is high

110= VIL on INT0 pin or Comparator C2OUT output is high

111= VIL on INT0 pin or Comparator C1OUT or Comparator C2OUT is high

bit 3-2

bit 1-0

PSSACn: Pins P1A and P1C Shutdown State Control bits

00= Drive pins P1A and P1C to ‘0’

01= Drive pins P1A and P1C to ‘1’

10= Pins 1A and P1C tri-state

11= Reserved, do not use

PSSBDn: Pins P1B and P1D Shutdown State Control bits

00= Drive pins P1B and P1D to ‘0’

01= Drive pins P1B and P1D to ‘1’

10= Pins P1B and P1D tri-state

11= Reserved, do not use

DS40001365F-page 118

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

Note 1: The auto-shutdown condition is

a

level-based signal, not an edge-based

signal. As long as the level is present, the

auto-shutdown will persist.

2: Writing to the ECCPASE bit is disabled

while an auto-shutdown condition

persists.

3: Once the auto-shutdown condition has

been removed and the PWM restarted

(either through firmware or auto-restart)

the PWM signal will always restart at the

beginning of the next PWM period.

4: Prior to an auto-shutdown event caused

by a comparator output or INT pin event,

a software shutdown can be triggered in

firmware by setting the CCPxASE bit to a

‘1’. The Auto-Restart feature tracks the

active status of a shutdown caused by a

comparator output or INT pin event only,

so if it is enabled at this time, it will

immediately clear this bit and restart the

ECCP module at the beginning of the

next PWM period.

FIGURE 13-12:

PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)

PWM Period

Shutdown Event

ECCPASE bit

PWM Activity

Normal PWM

ECCPASE

Cleared by

Firmware

Start of

Shutdown

PWM

PWM Period

Event Occurs Event Clears

Resumes

 2009-2016 Microchip Technology Inc.

DS40001365F-page 119

PIC18(L)F1XK22

13.4.5

AUTO-RESTART MODE

The Enhanced PWM can be configured to

automatically restart the PWM signal once the

auto-shutdown condition has been removed.

Auto-restart is enabled by setting the PRSEN bit in the

PWM1CON register.

If auto-restart is enabled, the ECCPASE bit will remain

set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the

ECCPASE bit will be cleared via hardware and normal

operation will resume.

FIGURE 13-13:

PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)

PWM Period

Shutdown Event

ECCPASE bit

PWM Activity

Normal PWM

Start of

PWM Period

Shutdown

Event Occurs Event Clears

Shutdown

PWM

Resumes

DS40001365F-page 120

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

13.4.6

PROGRAMMABLE DEAD-BAND

DELAY MODE

FIGURE 13-14:

EXAMPLE OF

HALF-BRIDGE PWM

OUTPUT

In half-bridge applications where all power switches are

modulated at the PWM frequency, the power switches

normally require more time to turn off than to turn on. If

both the upper and lower power switches are switched

at the same time (one turned on, and the other turned

off), both switches may be on for a short period of time

until one switch completely turns off. During this brief

interval, a very high current (shoot-through current) will

flow through both power switches, shorting the bridge

supply. To avoid this potentially destructive

shoot-through current from flowing during switching,

turning on either of the power switches is normally

delayed to allow the other switch to completely turn off.

Period

Pulse Width

(2)

P1A

td

P1B

(1)

td = Dead-Band Delay

Note 1: At this time, the TMR2 register is equal to the

In Half-Bridge mode,

a

digitally programmable

PR2 register.

dead-band delay is available to avoid shoot-through

current from destroying the bridge power switches. The

delay occurs at the signal transition from the non-active

state to the active state. See Figure 13-14 for

illustration. The lower seven bits of the associated

PWM1CON register (Register 13-3) sets the delay

period in terms of microcontroller instruction cycles

(TCY or 4 TOSC).

2: Output signals are shown as active-high.

FIGURE 13-15:

EXAMPLE OF HALF-BRIDGE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

+

V

-

P1A

Load

FET

Driver

+

V

-

P1B

V-

 2009-2016 Microchip Technology Inc.

DS40001365F-page 121

PIC18(L)F1XK22

REGISTER 13-3: PWM1CON: ENHANCED PWM CONTROL REGISTER

R/W-0

PDC6

R/W-0

PDC5

R/W-0

PDC4

R/W-0

PDC3

R/W-0

PDC2

R/W-0

PDC1

R/W-0

PDC0

PRSEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

PRSEN: PWM Restart Enable bit

1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes

away; the PWM restarts automatically

0= Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM

bit 6-0

PDC<6:0>: PWM Delay Count bits

PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active

DS40001365F-page 122

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PIC18(L)F1XK22

13.4.7

PULSE STEERING MODE

In Single Output mode, pulse steering allows any of the

PWM pins to be the modulated signal. Additionally, the

same PWM signal can be simultaneously available on

multiple pins.

Note:

The associated TRIS bits must be set to

output (‘0’) to enable the pin output driver

in order to see the PWM signal on the pin.

Once the Single Output mode is selected

(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the

CCP1CON register), the user firmware can bring out

the same PWM signal to one, two, three or four output

pins by setting the appropriate STR<D:A> bits of the

PSTRCON register, as shown in Table 13-2.

While the PWM Steering mode is active, CCP1M<1:0>

bits of the CCP1CON register select the PWM output

polarity for the P1<D:A> pins.

The PWM auto-shutdown operation also applies to

PWM Steering mode as described in Section 13.4.4

“Enhanced PWM Auto-shutdown mode”. An

auto-shutdown event will only affect pins that have

PWM outputs enabled.

REGISTER 13-4: PSTRCON: PULSE STEERING CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

STRD

R/W-0

STRC

R/W-0

STRB

R/W-1

STRA

STRSYNC

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4

Unimplemented: Read as ‘0’

STRSYNC: Steering Sync bit

1= Output steering update occurs on next PWM period

0= Output steering update occurs at the beginning of the instruction cycle boundary

bit 3

bit 2

bit 1

bit 0

STRD: Steering Enable bit D

1= P1D pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1D pin is assigned to port pin

STRC: Steering Enable bit C

1= P1C pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1C pin is assigned to port pin

STRB: Steering Enable bit B

1= P1B pin has the PWM waveform with polarity control from CCP1M<1:0>

0 = P1B pin is assigned to port pin

STRA: Steering Enable bit A

1= P1A pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1A pin is assigned to port pin

Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11and

P1M<1:0> = 00.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 123

PIC18(L)F1XK22

FIGURE 13-16:

SIMPLIFIED STEERING

BLOCK DIAGRAM

STRA

P1A Signal

CCP1M1

P1A pin

1

0

PORT Data

STRB

TRIS

P1B pin

P1C pin

P1D pin

CCP1M0

1

0

PORT Data

STRC

1

0

CCP1M1

PORT Data

STRD

1

0

CCP1M0

PORT Data

Note 1: Port outputs are configured as shown when

the CCP1CON register bits P1M<1:0> = 00

and CCP1M<3:2> = 11.

2: Single PWM output requires setting at least

one of the STRx bits.

DS40001365F-page 124

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When the STRSYNC bit is ‘1’, the effective steering

update will happen at the beginning of the next PWM

period. In this case, steering on/off the PWM output will

always produce a complete PWM waveform.

13.4.7.1

Steering Synchronization

The STRSYNC bit of the PSTRCON register gives the

user two selections of when the steering event will

happen. When the STRSYNC bit is ‘0’, the steering

event will happen at the end of the instruction that

writes to the PSTRCON register. In this case, the

output signal at the P1<D:A> pins may be an

incomplete PWM waveform. This operation is useful

when the user firmware needs to immediately remove

a PWM signal from the pin.

Figures 13-17 and 13-18 illustrate the timing diagrams

of the PWM steering depending on the STRSYNC

setting.

FIGURE 13-17:

EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)

PWM Period

PWM

STRn

P1<D:A>

PORT Data

P1n = PWM

FIGURE 13-18:

EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(STRSYNC = 1)

PWM

STRn

P1<D:A>

PORT Data

P1n = PWM

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13.4.8

OPERATION IN POWER-MANAGED

MODES

13.4.8.1

Operation with Fail-Safe

Clock Monitor

If the Fail-Safe Clock Monitor is enabled, a clock failure

will force the device into the RC_RUN Power-Managed

mode and the OSCFIF bit of the PIR2 register will be

set. The ECCP will then be clocked from the internal

oscillator clock source, which may have a different

clock frequency than the primary clock.

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the ECCP pin is driving a value, it will

continue to drive that value. When the device wakes

up, it will continue from this state. If Two-Speed

Start-ups are enabled, the initial start-up frequency

from HFINTOSC and the postscaler may not be stable

immediately.

See the previous section for additional details.

13.4.9

EFFECTS OF A RESET

In PRI_IDLE mode, the primary clock will continue to

clock the ECCP module without change. In all other

power-managed modes, the selected power-managed

mode clock will clock Timer2. Other power-managed

mode clocks will most likely be different than the

primary clock frequency.

Both Power-on Reset and subsequent Resets will force

all ports to Input mode and the CCP registers to their

Reset states.

This forces the enhanced CCP module to reset to a

state compatible with the standard CCP module.

TABLE 13-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CCPR1H

CCPR1L

CCP1CON

Capture/Compare/PWM Register 1, High Byte

Capture/Compare/PWM Register 1, Low Byte

247

245

248

246

247

246

247

248

246

247

P1M1

P1M0

DC1B1

DC1B0

CCP1M3

PSSAC1

RABIE

SSPIP

BCLIP

SSPIE

BCLIE

SSPIF

BCLIF

CCP1M2 CCP1M1 CCP1M0

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0

PSSAC0

TMR0IF

CCP1IP

PSSBD1

INT0IF

PSSBD0

RABIF

INTCON

IPR1

GIE/GIEH PEIE/GIEL

TMR0IE

RCIP

C2IP

INT0IE

TXIP

EEIP

TXIE

EEIE

TXIF

EEIF

ADIP

C1IP

ADIE

C1IE

ADIF

C1IF

TMR2IP

TMR3IP

TMR2IE

TMR3IE

TMR2IF

TMR3IF

TMR1IP

—

IPR2

OSCFIP

—

PIE1

RCIE

C2IE

CCP1IE

TMR1IE

—

PIE2

OSCFIE

—

PIR1

RCIF

C2IF

CCP1IF

TMR1IF

—

PIR2

OSCFIF

—

PR2

Timer2 Period Register

PWM1CON

RCON

TMR1H

TMR1L

TMR2

TMR3H

TMR3L

TRISC

T1CON

T2CON

T3CON

PRSEN

IPEN

PDC6

PDC5

—

PDC4

RI

PDC3

TO

PDC2

PD

PDC1

POR

PDC0

BOR

SBOREN

Timer1 Register, High Byte

Timer1 Register, Low Byte

Timer2 Register

Timer3 Register, High Byte

Timer3 Register, Low Byte

TRISC7

RD16

—

TRISC6

T1RUN

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

—

RD16

T3CKPS1 T3CKPS0

T3CCP1

T3SYNC TMR3CS TMR3ON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.

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14.2 SPI Mode

14.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

The SPI mode allows eight bits of data to be

synchronously transmitted and received

simultaneously. All four modes of SPI are supported. To

accomplish communication, typically three pins are

used:

14.1 Master SSP (MSSP) Module

Overview

• Serial Data Out – SDO

• Serial Data In – SDI

• Serial Clock – SCK

The Master Synchronous Serial Port (MSSP) module is

a serial interface, useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers,

display drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select – SS

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C)

- Full Master mode

Figure 14-1 shows the block diagram of the MSSP

module when operating in SPI mode.

FIGURE 14-1:

MSSP BLOCK DIAGRAM

(SPI MODE)

- Slave mode (with general address call)

The I²C interface supports the following modes in

hardware:

Internal

Data Bus

• Master mode

• Multi-Master mode

• Slave mode

Read

Write

SSPBUF Reg

SSPSR Reg

SDI/SDA

SDO

Shift

Clock

bit 0

SS

Control

Enable

SS

Edge

Select

2

Clock Select

SSPM<3:0>

4

TMR2 Output

(

)

2

SCK/SCL

Edge

Select

TOSC

Prescaler

4, 16, 64

TRIS bit

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SSPSR is the shift register used for shifting data in and

out. SSPBUF provides indirect access to the SSPSR

register. SSPBUF is the buffer register to which data

bytes are written, and from which data bytes are read.

14.2.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

• SSPCON1 – Control Register

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

• SSPSTAT – STATUS register

• SSPBUF – Serial Receive/Transmit Buffer

• SSPSR – Shift Register (Not directly accessible)

SSPCON1 and SSPSTAT are the control and STATUS

registers in SPI mode operation. The SSPCON1

register is readable and writable. The lower six bits of

the SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

During

transmission,

the

SSPBUF

is

not

double-buffered. A write to SSPBUF will write to both

SSPBUF and SSPSR.

REGISTER 14-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

SMP: Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6

CKE: SPI Clock Select bit⁽¹⁾

1= Transmit occurs on transition from active to Idle clock state

0= Transmit occurs on transition from Idle to active clock state

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D/A: Data/Address bit

Used in I²C mode only.

P: Stop bit

Used in I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

S: Start bit

Used in I²C mode only.

R/W: Read/Write Information bit

Used in I²C mode only.

UA: Update Address bit

Used in I²C mode only.

BF: Buffer Full Status bit (Receive mode only)

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Note 1: Polarity of clock state is set by the CKP bit of the SSPCON1 register.

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PIC18(L)F1XK22

REGISTER 14-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

WCOL: Write Collision Detect bit (Transmit mode only)

1= The SSPBUF register is written while it is still transmitting the previous word

(must be cleared by software)

0= No collision

bit 6

SSPOV: Receive Overflow Indicator bit⁽¹⁾

SPI Slave mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case of

overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read

the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared by

software).

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit⁽²⁾

1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level

0= Idle state for clock is a low level

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits⁽³⁾

0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011= SPI Master mode, clock = TMR2 output/2

0010= SPI Master mode, clock = FOSC/64

0001= SPI Master mode, clock = FOSC/16

0000= SPI Master mode, clock = FOSC/4

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPBUF register.

2: When enabled, these pins must be properly configured as input or output.

3: Bit combinations not specifically listed here are either reserved or implemented in I²C mode only.

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PIC18(L)F1XK22

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF of the SSPSTAT register, indicates

when SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. If the interrupt method is not going to

be used, then software polling can be done to ensure

that a write collision does not occur. Example 14-1

shows the loading of the SSPBUF (SSPSR) for data

transmission.

14.2.2

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP STATUS register (SSPSTAT)

indicates the various status conditions.

• Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

register. Then, the Buffer Full detect bit, BF of the

SSPSTAT register, and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored and the write collision detect bit WCOL

of the SSPCON1 register, will be set. User software

must clear the WCOL bit to allow the following write(s)

to the SSPBUF register to complete successfully.

EXAMPLE 14-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP

BTFSS

BRA

SSPSTAT, BF

LOOP

;Has data been received (transmit complete)?

;No

MOVF

SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF

RXDATA

;Save in user RAM, if data is meaningful

MOVF

MOVWF

TXDATA, W

SSPBUF

;W reg = contents of TXDATA

;New data to xmit

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14.2.3

ENABLING SPI I/O

14.2.4

TYPICAL CONNECTION

To enable the serial port, SSP Enable bit, SSPEN of the

SSPCON1 register, must be set. To reset or

reconfigure SPI mode, clear the SSPEN bit, reinitialize

the SSPCON registers and then set the SSPEN bit.

This configures the SDI, SDO, SCK and SS pins as

serial port pins. For the pins to behave as the serial port

function, some must have their data direction bits (in

the TRIS register) appropriately programmed as

follows:

Figure 14-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their

programmed clock edge and latched on the opposite

edge of the clock. Both processors should be

programmed to the same Clock Polarity (CKP), then

both controllers would send and receive data at the

same time. Whether the data is meaningful (or dummy

data) depends on the application software. This leads

to three scenarios for data transmission:

• SDI is automatically controlled by the SPI module

• SDO must have corresponding TRIS bit cleared

• Master sends data–Slave sends dummy data

• Master sends data–Slave sends data

• SCK (Master mode) must have corresponding

TRIS bit cleared

• Master sends dummy data–Slave sends data

• SCK (Slave mode) must have corresponding

TRIS bit set

• SS must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

FIGURE 14-2:

TYPICAL SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xx

SPI Slave SSPM<3:0> = 010x

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

SS

Slave Select

(optional)

General I/O

Processor 2

Processor 1

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The clock polarity is selected by appropriately

programming the CKP bit of the SSPCON1 register.

This then, would give waveforms for SPI

communication as shown in Figure 14-3, Figure 14-5

and Figure 14-6, where the MSB is transmitted first. In

Master mode, the SPI clock rate (bit rate) is user

programmable to be one of the following:

14.2.5

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 14-2) is to

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be

disabled (programmed as an input). The SSPSR

register will continue to shift in the signal present on the

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and Status bits

appropriately set).

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 64 MHz) of

16.00 Mbps.

Figure 14-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

FIGURE 14-3:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

(CKE = 0)

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPIF

SSPSR to

SSPBUF

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PIC18(L)F1XK22

14.2.6

SLAVE MODE

14.2.7

SLAVE SELECT

SYNCHRONIZATION

In Slave mode, the data is transmitted and received as

external clock pulses appear on SCK. When the last bit

is latched, the SSPIF interrupt flag bit is set.

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSPCON1<3:0> = 0100). When the SS pin is low,

transmission and reception are enabled and the SDO

pin is driven. When the SS pin goes high, the SDO pin

is no longer driven, even if in the middle of a transmitted

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCK pin. The Idle state is

determined by the CKP bit of the SSPCON1 register.

byte and becomes

a floating output. External

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

pull-up/pull-down resistors may be desirable

depending on the application.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPCON<3:0> = 0100),

the SPI module will reset if the SS pin is

set to VDD.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

2: When the SPI is used in Slave mode with

CKE set the SS pin control must also be

enabled.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

FIGURE 14-4:

SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 7

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

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PIC18(L)F1XK22

FIGURE 14-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 3

bit 1

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

FIGURE 14-6:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit 6

bit 3

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

SSPSR to

SSPBUF

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PIC18(L)F1XK22

Transmit/Receive Shift register. When all eight bits

have been received, the MSSP interrupt flag bit will be

set and if enabled, will wake the device.

14.2.8

OPERATION IN POWER-MANAGED

MODES

In SPI Master mode, module clocks may be operating

at a different speed than when in Full Power mode; in

the case of the Sleep mode, all clocks are halted.

14.2.9

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

In all Idle modes, a clock is provided to the peripherals.

That clock could be from the primary clock source, the

secondary clock (Timer1 oscillator at 32.768 kHz) or

the INTOSC source. See Section 18.0 “Power-Man-

aged Modes” for additional information.

14.2.10 BUS MODE COMPATIBILITY

Table 14-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

In most cases, the speed that the master clocks SPI

data is not important; however, this should be

evaluated for each system.

TABLE 14-1: SPI BUS MODES

When MSSP interrupts are enabled, after the master

completes sending data, an MSSP interrupt will wake

the controller:

Control Bits State

Standard SPI Mode

Terminology

CKP

CKE

• From Sleep, in Slave mode

0, 0

0, 1

1, 0

1, 1

0

1

0

1

0

• From Idle, in Slave or Master mode

If an exit from Sleep or Idle mode is not desired, MSSP

interrupts should be disabled.

In SPI Master mode, when the Sleep mode is selected,

There is also an SMP bit which controls when the data

is sampled.

all

module

clocks

are

halted

and

the

transmission/reception will remain in that state until the

device wakes. After the device returns to Run mode,

the module will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

register operates asynchronously to the device. This

allows the device to be placed in any Power-Managed

mode and data to be shifted into the SPI

TABLE 14-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

IPR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIP

RABIE

SSPIP

SSPIE

SSPIF

—

TMR0IF

CCP1IP

CCP1IE

CCP1IF

—

INT0IF

RABIF

245

248

246

—

ADIP

ADIE

RCIP

RCIE

TMR2IP TMR1IP

TMR2IE TMR1IE

PIE1

TXIE

—

PIR1

ADIF

RCIF

TXIF

TMR2IF

—

TMR1IF

—

TRISB

TRISB7

TRISC7

TRISB6

TRISC6

TRISB5

TRISC5

TRISB4

TRISC4

TRISC

SSPBUF

SSPCON1

SSPSTAT

TRISC3

TRISC2

TRISC1

TRISC0

SSP Receive Buffer/Transmit Register

WCOL

SMP

SSPOV

CKE

SSPEN

D/A

CKP

P

SSPM3

S

SSPM2

R/W

SSPM1

UA

SSPM0

BF

Legend: Shaded cells are not used by the MSSP in SPI mode.

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PIC18(L)F1XK22

2

14.3.1

REGISTERS

14.3 I C Mode

The MSSP module has seven registers for I²C

operation. These are:

The MSSP module in I²C mode fully implements all

master and slave functions (including general call

support) and provides interrupts on Start and Stop bits

in hardware to determine a free bus (multi-master

function). The MSSP module implements the standard

mode specifications as well as 7-bit and 10-bit

addressing.

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 2 (SSPCON2)

• MSSP Status register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

Two pins are used for data transfer:

• MSSP Shift Register (SSPSR) – Not directly

accessible

• Serial clock – SCL

• Serial data – SDA

• MSSP Address Register (SSPADD)

• MSSP Address Mask (SSPMSK)

Note:

The user must configure these pins as

inputs with the corresponding TRIS bits.

SSPCON1, SSPCON2 and SSPSTAT are the control

and STATUS registers in I²C mode operation. The

SSPCON1 and SSPCON2 registers are readable and

writable. The lower six bits of the SSPSTAT are

read-only. The upper two bits of the SSPSTAT are

read/write.

FIGURE 14-7:

MSSP BLOCK DIAGRAM

(I²C MODE)

Internal

Data Bus

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

Read

Write

SSPBUF Reg

SCK/SCL

SDI/SDA

When the MSSP is configured in Master mode, the

SSPADD register acts as the Baud Rate Generator

reload value. When the MSSP is configured for I²C

Slave mode the SSPADD register holds the slave

device address. The MSSP can be configured to

respond to a range of addresses by qualifying selected

bits of the address register with the SSPMSK register.

Shift

Clock

SSPSR Reg

MSb

LSb

SSPMSK Reg

Match Detect

SSPADD Reg

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

Addr Match

During

transmission,

the

SSPBUF

is

not

double-buffered. A write to SSPBUF will write to both

SSPBUF and SSPSR.

Set, Reset

S, P bits

(SSPSTAT Reg)

Start and

Stop bit Detect

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REGISTER 14-3: SSPSTAT: MSSP STATUS REGISTER (I²C MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P⁽¹⁾

R-0

S⁽¹⁾

R-0

R/W^{(2, 3)}

R-0

UA

R-0

BF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control disabled for standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6

bit 5

CKE: SMBus Select bit

In Master or Slave mode:

1= Enable SMBus specific inputs

0= Disable SMBus specific inputs

D/A: Data/Address bit

In Master mode:

Reserved.

In Slave mode:

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received was an address

bit 4

bit 3

bit 2

P: Stop bit⁽¹⁾

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

S: Start bit⁽¹⁾

1= Indicates that a Start bit has been detected last

0= Start bit was not detected last

R/W: Read/Write Information bit (I²C mode only)^{(2, 3)}

In Slave mode:

1= Read

0= Write

In Master mode:

1= Transmit is in progress

0= Transmit is not in progress

bit 1

bit 0

UA: Update Address bit (10-bit Slave mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

In Transmit mode:

1= SSPBUF is full

0= SSPBUF is empty

In Receive mode:

1= SSPBUF is full (does not include the ACK and Stop bits)

0= SSPBUF is empty (does not include the ACK and Stop bits)

Note 1: This bit is cleared on Reset and when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or not ACK bit.

3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the Master mode is active.

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REGISTER 14-4: SSPCON1: MSSP CONTROL 1 REGISTER (I²C MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

WCOL: Write Collision Detect bit

In Master Transmit mode:

1= A write to the SSPBUF register was attempted while the I²C conditions were not valid for a

transmission to be started (must be cleared by software)

0= No collision

In Slave Transmit mode:

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared by

software)

0= No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6

SSPOV: Receive Overflow Indicator bit

In Receive mode:

1= A byte is received while the SSPBUF register is still holding the previous byte (must be cleared

by software)

0= No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode.

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables the serial port and configures the SDA and SCL pins as the serial port pins

0= Disables serial port and configures these pins as I/O port pins

When enabled, the SDA and SCL pins must be properly configured as inputs.

CKP: SCK Release Control bit

In Slave mode:

1= Release clock

0= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode.

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1011= I²C Firmware Controlled Master mode (Slave Idle)

1000= I²C Master mode, clock = FOSC/(4 * (SSPADD + 1))

0111= I²C Slave mode, 10-bit address

0110= I²C Slave mode, 7-bit address

Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

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REGISTER 14-5: SSPCON2: MSSP CONTROL REGISTER (I²C MODE)

R/W-0

GCEN

R/W-0

ACKDT⁽²⁾

R/W-0

ACKEN⁽¹⁾

R/W-0

RCEN⁽¹⁾

R/W-0

PEN⁽¹⁾

R/W-0

RSEN⁽¹⁾

R/W-0

SEN⁽¹⁾

ACKSTAT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (Slave mode only)

1= Generate interrupt when a general call address 0x00 or 00h is received in the SSPSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1= Acknowledge was not received from slave

0= Acknowledge was received from slave

ACKDT: Acknowledge Data bit (Master Receive mode only)⁽²⁾

1= Not Acknowledge

0= Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)⁽¹⁾

1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence Idle

bit 3

bit 2

RCEN: Receive Enable bit (Master mode only)⁽¹⁾

1= Enables Receive mode for I²C

0= Receive Idle

PEN: Stop Condition Enable bit (Master mode only)⁽¹⁾

1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0= Stop condition Idle

bit 1

bit 0

RSEN: Repeated Start Condition Enable bit (Master mode only)⁽¹⁾

1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Repeated Start condition Idle

SEN: Start Condition Enable/Stretch Enable bit⁽¹⁾

In Master mode:

1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Start condition Idle

In Slave mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0= Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the Idle mode, these bits may not

be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

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14.3.2

OPERATION

14.3.3.1

Addressing

The MSSP module functions are enabled by setting

SSPEN bit of the SSPCON1 register.

The SSPCON1 register allows control of the I²C

operation. Four mode selection bits of the SSPCON1

register allow one of the following I²C modes to be

selected:

• I²C Master mode, clock = (FOSC/(4*(SSPADD + 1))

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

• I²C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled

• I²C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled

• I²C Firmware Controlled Master mode, slave is

Idle

Once the MSSP module has been enabled, it waits for

a Start condition to occur. Following the Start condition,

the eight bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match and the BF

and SSPOV bits are clear, the following events occur:

1. The SSPSR register value is loaded into the

SSPBUF register.

2. The Buffer Full bit, BF, is set.

3. An ACK pulse is generated.

4. MSSP Interrupt Flag bit, SSPIF of the PIR1

register, is set (interrupt is generated, if enabled)

on the falling edge of the ninth SCL pulse.

Selection of any I²C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain,

provided these pins are programmed to inputs by

setting the appropriate TRIS bits

In 10-bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W of the SSPSTAT register must specify

a write so the slave device will receive the second

address byte. For a 10-bit address, the first byte would

equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two

MSbs of the address. The sequence of events for 10-bit

address is as follows, with steps 7 through 9 for the

slave-transmitter:

Note:

To ensure proper operation of the module,

pull-up resistors must be provided

externally to the SCL and SDA pins.

14.3.3

SLAVE MODE

In Slave mode, the SCL and SDA pins must be

configured as inputs. The MSSP module will override

the input state with the output data when required

(slave-transmitter).

The I²C Slave mode hardware will always generate an

interrupt on an address match. Through the mode

select bits, the user can also choose to interrupt on

Start and Stop bits

1. Receive first (high) byte of address (bits SSPIF,

BF and UA of the SSPSTAT register are set).

2. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

3. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

4. Receive second (low) byte of address (bits

SSPIF, BF and UA are set). If the address

matches then the SCL is held until the next step.

Otherwise the SCL line is not held.

When an address is matched, or the data transfer after

an address match is received, the hardware

automatically will generate the Acknowledge (ACK)

pulse and load the SSPBUF register with the received

value currently in the SSPSR register.

5. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

6. Update the SSPADD register with the first (high)

byte of address. (This will clear bit UA and

release a held SCL line.)

• The Buffer Full bit, BF bit of the SSPSTAT

register, is set before the transfer is received.

7. Receive Repeated Start condition.

• The overflow bit, SSPOV bit of the SSPCON1

register, is set before the transfer is received.

8. Receive first (high) byte of address with R/W bit

set (bits SSPIF, BF, R/W are set).

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF of the PIR1 register is

set. The BF bit is cleared by reading the SSPBUF

register, while bit SSPOV is cleared through software.

9. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

10. Load SSPBUF with byte the slave is to transmit,

sets the BF bit.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I²C specification, as well as the requirement of the

MSSP module, are shown in Section 26.0 “Electrical

Specifications”.

11. Set the CKP bit to release SCL.

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14.3.3.2

Reception

14.3.3.3

Transmission

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register and the SDA line is held low

(ACK).

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin SCK/SCL is held low

regardless of SEN (see Section 14.3.4 “Clock

Stretching” for more detail). By stretching the clock,

the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data. The

transmit data must be loaded into the SSPBUF register

which also loads the SSPSR register. Then pin

SCK/SCL should be released by setting the CKP bit of

the SSPCON1 register. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time

(Figure 14-9).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF bit of the SSPSTAT

register is set, or bit SSPOV bit of the SSPCON1

register is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF of the PIR1 register, must be

cleared by software.

When the SEN bit of the SSPCON2 register is set, SCL

will be held low (clock stretch) following each data

transfer. The clock must be released by setting the

CKP bit of the SSPCON1 register. See Section 14.3.4

“Clock Stretching” for more detail.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is complete.

In this case, when the ACK is latched by the slave, the

slave logic is reset (resets SSPSTAT register) and the

slave monitors for another occurrence of the Start bit. If

the SDA line was low (ACK), the next transmit data must

be loaded into the SSPBUF register. Again, pin

SCK/SCL must be released by setting bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared by software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

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PIC18(L)F1XK22

2

FIGURE 14-8:

I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

DS40001365F-page 142

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PIC18(L)F1XK22

2

FIGURE 14-9:

I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

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DS40001365F-page 143

PIC18(L)F1XK22

FIGURE 14-10:

I²C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

DS40001365F-page 144

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PIC18(L)F1XK22

2

FIGURE 14-11:

I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

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DS40001365F-page 145

PIC18(L)F1XK22

This register must be initiated prior to setting

SSPM<3:0> bits to select the I²C Slave mode (7-bit or

10-bit address).

14.3.3.4

SSP Mask Register

An SSP Mask (SSPMSK) register is available in I²C

Slave mode as a mask for the value held in the

SSPSR register during an address comparison

operation. A zero (‘0’) bit in the SSPMSK register has

the effect of making the corresponding bit in the

SSPSR register a “don’t care”.

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP operation until written with a mask value.

REGISTER 14-6: SSPMSK: SSP MASK REGISTER

R/W-1

MSK7

R/W-1

MSK6

R/W-1

MSK5

R/W-1

MSK4

R/W-1

MSK3

R/W-1

MSK2

R/W-1

MSK1

R/W-1

MSK0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

bit 0

MSK<7:1>: Mask bits

1= The received address bit n is compared to SSPADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK<0>: Mask bit for I²C Slave mode, 10-bit Address⁽¹⁾

I²C Slave mode, 10-bit Address (SSPM<3:0> = 0111):

1= The received address bit 0 is compared to SSPADD<0> to detect I²C address match

0= The received address bit 0 is not used to detect I²C address match

Note 1: The MSK0 bit is used only in 10-bit Slave mode. In all other modes, this bit has no effect.

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REGISTER 14-7: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I²C MODE)

R/W-0

ADD7

R/W-0

ADD6

R/W-0

ADD5

R/W-0

ADD4

R/W-0

ADD3

R/W-0

ADD2

R/W-0

ADD1

R/W-0

ADD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Master mode:

bit 7-0

ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC

10-Bit Slave mode — Most Significant Address Byte:

bit 7-3

Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care.” Bit

pattern sent by master is fixed by I²C specification and must be equal to ‘11110’. However, those bits

are compared by hardware and are not affected by the value in this register.

bit 2-1

bit 0

ADD<9:8>: Two Most Significant bits of 10-bit address

Not used: Unused in this mode. Bit state is a “don’t care.”

10-Bit Slave mode — Least Significant Address Byte:

bit 7-0

ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1

bit 0

ADD<6:0>: 7-bit address

Not used: Unused in this mode. Bit state is a “don’t care.”

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14.3.4

CLOCK STRETCHING

14.3.4.3

Clock Stretching for 7-bit Slave

Transmit Mode

Both 7-bit and 10-bit Slave modes implement

automatic clock stretching during a transmit sequence.

7-bit Slave Transmit mode implements clock stretching

by clearing the CKP bit after the falling edge of the

ninth clock. This occurs regardless of the state of the

SEN bit.

The SEN bit of the SSPCON2 register allows clock

stretching to be enabled during receives. Setting SEN

will cause the SCL pin to be held low at the end of

each data receive sequence.

The user’s ISR must set the CKP bit before

transmission is allowed to continue. By holding the

SCL line low, the user has time to service the ISR and

load the contents of the SSPBUF before the master

device can initiate another data transfer sequence

(see Figure 14-9).

14.3.4.1

Clock Stretching for 7-bit Slave

Receive Mode (SEN = 1)

In 7-bit Slave Receive mode, on the falling edge of the

ninth clock at the end of the ACK sequence if the BF

bit is set, the CKP bit of the SSPCON1 register is

automatically cleared, forcing the SCL output to be

held low. The CKP being cleared to ‘0’ will assert the

SCL line low. The CKP bit must be set in the user’s

ISR before reception is allowed to continue. By holding

the SCL line low, the user has time to service the ISR

and read the contents of the SSPBUF before the

master device can initiate another data transfer

sequence. This will prevent buffer overruns from

occurring (see Figure 14-13).

Note 1: If the user loads the contents of SSPBUF,

setting the BF bit before the falling edge

of the ninth clock, the CKP bit will not be

cleared and clock stretching will not

occur.

2: The CKP bit can be set by software

regardless of the state of the BF bit.

14.3.4.4

Clock Stretching for 10-bit Slave

Transmit Mode

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

In 10-bit Slave Transmit mode, clock stretching is

controlled during the first two address sequences by

the state of the UA bit, just as it is in 10-bit Slave

Receive mode. The first two addresses are followed

by a third address sequence which contains the

high-order bits of the 10-bit address and the R/W bit

set to ‘1’. After the third address sequence is

performed, the UA bit is not set, the module is now

configured in Transmit mode and clock stretching is

automatic with the hardware clearing CKP, as in 7-bit

Slave Transmit mode (see Figure 14-11).

2: The CKP bit can be set by software

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

14.3.4.2

Clock Stretching for 10-bit Slave

Receive Mode (SEN = 1)

In 10-bit Slave Receive mode during the address

sequence, clock stretching automatically takes place

but CKP is not cleared. During this time, if the UA bit is

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

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14.3.4.5

Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCL output is forced

to ‘0’. However, clearing the CKP bit will not assert the

SCL output low until the SCL output is already

sampled low. Therefore, the CKP bit will not assert the

SCL line until an external I²C master device has

already asserted the SCL line. The SCL output will

remain low until the CKP bit is set and all other

devices on the I²C bus have deasserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 14-12).

FIGURE 14-12:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX – 1

Master device

asserts clock

CKP

Master device

deasserts clock

WR

SSPCON1

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2

FIGURE 14-13:

I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

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PIC18(L)F1XK22

FIGURE 14-14:

I²C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 151

PIC18(L)F1XK22

If the general call address matches, the SSPSR is

transferred to the SSPBUF, the BF flag bit is set (eighth

bit) and on the falling edge of the ninth bit (ACK bit), the

SSPIF interrupt flag bit is set.

14.3.5

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I²C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed by

the master. The exception is the general call address

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

When the interrupt is serviced, the source for the

interrupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match and the UA

bit of the SSPSTAT register is set. If the general call

address is sampled when the GCEN bit is set, while the

slave is configured in 10-bit Address mode, then the

second half of the address is not necessary, the UA bit

will not be set and the slave will begin receiving data

after the Acknowledge (Figure 14-15).

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all ‘0’s with R/W = 0.

The general call address is recognized when the

GCEN bit of the SSPCON2 is set. Following a Start bit

detect, eight bits are shifted into the SSPSR and the

address is compared against the SSPADD. It is also

compared to the general call address and fixed in

hardware.

FIGURE 14-15:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data

D5 D4 D3 D2 D1

ACK

R/W = 0

General Call Address

ACK

9

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

9

S

SSPIF

BF (SSPSTAT<0>)

Cleared by software

SSPBUF is read

SSPOV (SSPCON1<6>)

GCEN (SSPCON2<7>)

‘0’

‘1’

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14.3.6

MASTER MODE

Note:

The MSSP module, when configured in

I²C Master mode, does not allow queueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission before the Start

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP module is disabled.

Control of the I²C bus may be taken when the P bit is

set, or the bus is Idle, with both the S and P bits clear.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP interrupt, if enabled):

In Firmware Controlled Master mode, user code

conducts all I²C bus operations based on Start and

Stop bit conditions.

• Start condition

• Stop condition

Once Master mode is enabled, the user has six

options.

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

1. Assert a Start condition on SDA and SCL.

2. Assert a Repeated Start condition on SDA and

SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Configure the I²C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a Stop condition on SDA and SCL.

2

FIGURE 14-16:

MSSP BLOCK DIAGRAM (I C MASTER MODE)

Internal

Data Bus

SSPM<3:0>

SSPADD<6:0>

Read

Write

SSPBUF

SSPSR

Baud

Rate

Generator

SDA

Shift

Clock

SDA In

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate

SCL

Start bit Detect

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCL In

Bus Collision

Set/Reset, S, P, WCOL

Set SSPIF, BCLIF

Reset ACKSTAT, PEN

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I²C Master Mode Operation

A typical transmit sequence would go as follows:

14.3.6.1

1. The user generates a Start condition by setting

the SEN bit of the SSPCON2 register.

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPBUF with the slave

address to transmit.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (seven bits) and the Read/Write (R/W)

bit. In this case, the R/W bit will be logic ‘0’. Serial data

is transmitted eight bits at a time. After each byte is

transmitted, an Acknowledge bit is received. Start and

Stop conditions are output to indicate the beginning

and the end of a serial transfer.

4. Address is shifted out the SDA pin until all 8 bits

are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

6. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received 8 bits at a time. After

each byte is received, an Acknowledge bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is shifted out the SDA pin until all 8 bits are

transmitted.

9. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPCON2 register.

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

A Baud Rate Generator is used to set the clock

frequency output on SCL. See Section 14.3.7 “Baud

Rate” for more detail.

11. The user generates a Stop condition by setting

the PEN bit of the SSPCON2 register.

12. Interrupt is generated once the Stop condition is

complete.

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Table 14-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

14.3.7

BAUD RATE

In I²C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the SSPADD register

(Figure 14-17). When a write occurs to SSPBUF, the

Baud Rate Generator will automatically begin counting.

EQUATION 14-1: CLOCK RATES

Once the given operation is complete (i.e.,

transmission of the last data bit is followed by ACK), the

internal clock will automatically stop counting and the

SCL pin will remain in its last state.

FOSC

FSCL = ----------------------------------------------

SSPADD + 14

FIGURE 14-17:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0>

SSPADD<7:0>

SSPM<3:0>

SCL

Reload

Control

Reload

BRG Down Counter

CLKOUT

FOSC/2

TABLE 14-3: I²C CLOCK RATE W/BRG

FSCL

FOSC

FCY

BRG Value

(2 Rollovers of BRG)

48 MHz

40 MHz

16 MHz

4 MHz

12 MHz

10 MHz

4 MHz

1 MHz

0Bh

1Dh

77h

18h

1Fh

63h

09h

0Ch

27h

02h

09h

00h

1 MHz⁽¹⁾

400 kHz

100 kHz

400 kHz⁽¹⁾

312.5 kHz

100 kHz

400 kHz⁽¹⁾

308 kHz

100 kHz

333 kHz⁽¹⁾

4 MHz

100 kHz

1 MHz⁽¹⁾

4 MHz

Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

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14.3.7.1

Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

deasserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCL pin is actually sampled high. When the

SCL pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and

begins counting. This ensures that the SCL high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 14-18).

FIGURE 14-18:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX – 1

SCL allowed to transition high

SCL deasserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count

BRG

Reload

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14.3.8

I²C MASTER MODE START

CONDITION TIMING

Note:

If at the beginning of the Start condition,

the SDA and SCL pins are already

sampled low, or if during the Start

condition, the SCL line is sampled low

before the SDA line is driven low, a bus

collision occurs, the Bus Collision Interrupt

Flag, BCLIF, is set, the Start condition is

aborted and the I²C module is reset into its

Idle state.

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSPCON2 register. If the

SDA and SCL pins are sampled high, the Baud Rate

Generator is reloaded with the contents of

SSPADD<6:0> and starts its count. If SCL and SDA are

both sampled high when the Baud Rate Generator

times out (TBRG), the SDA pin is driven low. The action

of the SDA being driven low while SCL is high is the

Start condition and causes the S bit of the SSPSTAT1

register to be set. Following this, the Baud Rate

Generator is reloaded with the contents of

SSPADD<7:0> and resumes its count. When the Baud

Rate Generator times out (TBRG), the SEN bit of the

SSPCON2 register will be automatically cleared by

hardware; the Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

14.3.8.1

WCOL Status Flag

If the user writes the SSPBUF when a Start sequence

is in progress, the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

Note:

Because queuing of events is not allowed,

writing to the lower five bits of SSPCON2

is disabled until the Start condition is

complete.

FIGURE 14-19:

FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

At completion of Start bit,

Write to SEN bit occurs here

SDA = 1,

SCL = 1

hardware clears SEN bit

and sets SSPIF bit

TBRG

Write to SSPBUF occurs here

1st bit

2nd bit

SDA

TBRG

SCL

TBRG

S

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14.3.9

I²C MASTER MODE REPEATED

START CONDITION TIMING

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

A Repeated Start condition occurs when the RSEN bit

of the SSPCON2 register is programmed high and the

I²C logic module is in the Idle state. When the RSEN bit

is set, the SCL pin is asserted low. When the SCL pin

is sampled low, the Baud Rate Generator is loaded and

begins counting. The SDA pin is released (brought

high) for one Baud Rate Generator count (TBRG). When

the Baud Rate Generator times out, if SDA is sampled

high, the SCL pin will be deasserted (brought high).

When SCL is sampled high, the Baud Rate Generator

is reloaded and begins counting. SDA and SCL must

be sampled high for one TBRG. This action is then

followed by assertion of the SDA pin (SDA = 0) for one

TBRG while SCL is high. Following this, the RSEN bit of

the SSPCON2 register will be automatically cleared

and the Baud Rate Generator will not be reloaded,

leaving the SDA pin held low. As soon as a Start

condition is detected on the SDA and SCL pins, the S

bit of the SSPSTAT register will be set. The SSPIF bit

will not be set until the Baud Rate Generator has timed

out.

2: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL goes

from low-to-high.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

Immediately following the SSPIF bit getting set, the user

may write the SSPBUF with the 7-bit address in 7-bit

mode or the default first address in 10-bit mode. After the

first eight bits are transmitted and an ACK is received,

the user may then transmit an additional eight bits of

address (10-bit mode) or eight bits of data (7-bit mode).

14.3.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Repeated Start

sequence is in progress, the WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

Note:

Because queueing of events is not

allowed, writing of the lower 5 bits of SSP-

CON2 is disabled until the Repeated Start

condition is complete.

FIGURE 14-20:

REPEAT START CONDITION WAVEFORM

S bit set by hardware

Write to SSPCON2

occurs here.

SDA = 1,

SCL (no change).

SDA = 1,

SCL = 1

At completion of Start bit,

hardware clears RSEN bit

and sets SSPIF

TBRG

1st bit

SDA

RSEN bit set by hardware

on falling edge of ninth clock,

end of Xmit

Write to SSPBUF occurs here

TBRG

SCL

TBRG

Sr = Repeated Start

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14.3.10 I²C MASTER MODE

TRANSMISSION

14.3.10.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSPCON2

register is cleared when the slave has sent an

Acknowledge (ACK = 0) and is set when the slave

does not Acknowledge (ACK = 1). A slave sends an

Acknowledge when it has recognized its address

(including a general call), or when the slave has

properly received its data.

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the Buffer Full flag bit, BF, and allow the Baud Rate

Generator to begin counting and start the next

transmission. Each bit of address/data will be shifted

out onto the SDA pin after the falling edge of SCL is

asserted (see data hold time specification

parameter SP106). SCL is held low for one Baud Rate

Generator rollover count (TBRG). Data should be valid

before SCL is released high (see data setup time

specification parameter SP107). When the SCL pin is

released high, it is held that way for TBRG. The data on

the SDA pin must remain stable for that duration and

some hold time after the next falling edge of SCL. After

the eighth bit is shifted out (the falling edge of the eighth

clock), the BF flag is cleared and the master releases

SDA. This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received

properly. The status of ACK is written into the ACKDT

bit on the falling edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSPIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 14-21).

14.3.11 I²C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN bit of the SSPCON2

register.

Note:

The MSSP module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPSR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the

contents of the SSPSR are loaded into the SSPBUF,

the BF flag bit is set, the SSPIF flag bit is set and the

Baud Rate Generator is suspended from counting,

holding SCL low. The MSSP is now in Idle state

awaiting the next command. When the buffer is read by

the CPU, the BF flag bit is automatically cleared. The

user can then send an Acknowledge bit at the end of

reception by setting the Acknowledge Sequence

Enable, ACKEN bit of the SSPCON2 register.

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

deassert the SDA pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

clock, the master will sample the SDA pin to see if the

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT Status bit of the

SSPCON2 register. Following the falling edge of the

ninth clock transmission of the address, the SSPIF is

set, the BF flag is cleared and the Baud Rate Generator

is turned off until another write to the SSPBUF takes

place, holding SCL low and allowing SDA to float.

14.3.11.1 BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

14.3.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

14.3.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write doesn’t occur).

14.3.10.1 BF Status Flag

In Transmit mode, the BF bit of the SSPSTAT register

is set when the CPU writes to SSPBUF and is cleared

when all 8 bits are shifted out.

14.3.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared by software before the next

transmission.

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2

FIGURE 14-21:

I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

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2

FIGURE 14-22:

I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

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14.3.12 ACKNOWLEDGE SEQUENCE

TIMING

14.3.13 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN bit of the SSPCON2 register. At the end of a

receive/transmit, the SCL line is held low after the

falling edge of the ninth clock. When the PEN bit is set,

the master will assert the SDA line low. When the SDA

line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCL pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDA pin will be deasserted. When the SDA

pin is sampled high while SCL is high, the P bit of the

SSPSTAT register is set. A TBRG later, the PEN bit is

cleared and the SSPIF bit is set (Figure 14-24).

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the

SSPCON2 register. When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCL pin is deasserted (pulled high).

When the SCL pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCL pin

is then pulled low. Following this, the ACKEN bit is

automatically cleared, the Baud Rate Generator is

turned off and the MSSP module then goes into Idle

mode (Figure 14-23).

14.3.13.1 WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

14.3.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 14-23:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

write to SSPCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDA

SCL

D0

8

9

SSPIF

Cleared in

SSPIF set at

the end of receive

software

Cleared in

software

SSPIF set at the end

of Acknowledge sequence

Note: TBRG = one Baud Rate Generator period.

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FIGURE 14-24:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1for TBRG, followed by SDA = 1for TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

Write to SSPCON2,

set PEN

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

Falling edge of

9th clock

TBRG

SCL

SDA

ACK

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

14.3.14 SLEEP OPERATION

14.3.17 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

While in Sleep mode, the I²C Slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

ARBITRATION

Multi-Master mode support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDA pin, arbitration takes place when the

master outputs a ‘1’ on SDA, by letting SDA float high

and another master asserts a ‘0’. When the SCL pin

floats high, data should be stable. If the expected data

on SDA is a ‘1’ and the data sampled on the SDA pin =

0, then a bus collision has taken place. The master will

set the Bus Collision Interrupt Flag, BCLIF and reset

the I²C port to its Idle state (Figure 14-25).

14.3.15 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

14.3.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I²C bus may

be taken when the P bit of the SSPSTAT register is set,

or the bus is Idle, with both the S and P bits clear. When

the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSPBUF can be written to. When the user services the

bus collision Interrupt Service Routine and if the I²C

bus is free, the user can resume communication by

asserting a Start condition.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCLIF bit.

If a Start, Repeated Start, Stop or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are deasserted and the respective control bits in

the SSPCON2 register are cleared. When the user

services the bus collision Interrupt Service Routine and

if the I²C bus is free, the user can resume

communication by asserting a Start condition.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be set.

• A Repeated Start Condition

• An Acknowledge Condition

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I²C

bus can be taken when the P bit is set in the SSPSTAT

register, or the bus is Idle and the S and P bits are

cleared.

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FIGURE 14-25:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data doesn’t match what is driven

by the master.

Data changes

while SCL = 0

SDA line pulled low

by another source

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCLIF)

BCLIF

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If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 14-28). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to 0; if the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

14.3.17.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 14-26).

b) SCL is sampled low before SDA is asserted low

(Figure 14-27).

During a Start condition, both the SDA and the SCL

pins are monitored.

Note:

The reason that bus collision is not a

factor during a Start condition is that no

two bus masters can assert a Start

condition at the exact same time.

Therefore, one master will always assert

SDA before the other. This condition does

not cause a bus collision because the two

masters must be allowed to arbitrate the

first address following the Start condition.

If the address is the same, arbitration

must be allowed to continue into the data

portion, Repeated Start or Stop

conditions.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted,

• the BCLIF flag is set and

•

the MSSP module is reset to its Idle state

(Figure 14-26).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded and counts down. If the

SCL pin is sampled low while SDA is high, a bus

collision occurs because it is assumed that another

master is attempting to drive a data ‘1’ during the Start

condition.

FIGURE 14-26:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,

S bit and SSPIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.

SSP module reset into Idle state.

SDA sampled low before

Start condition. Set BCLIF.

S bit and SSPIF set because

SDA = 0, SCL = 1.

BCLIF

SSPIF and BCLIF are

cleared by software

S

SSPIF

SSPIF and BCLIF are

cleared by software

 2009-2016 Microchip Technology Inc.

DS40001365F-page 165

PIC18(L)F1XK22

FIGURE 14-27:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG

SDA

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

SCL

SEN

SCL = 0before SDA = 0,

bus collision occurs. Set BCLIF.

SCL = 0before BRG time-out,

bus collision occurs. Set BCLIF.

BCLIF

Interrupt cleared

by software

S

‘0’

SSPIF

FIGURE 14-28:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

time-out

SEN

Set SEN, enable START

sequence if SDA = 1, SCL = 1

‘0’

BCLIF

S

SSPIF

Interrupts cleared

by software

SDA = 0, SCL = 1,

set SSPIF

DS40001365F-page 166

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PIC18(L)F1XK22

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 14-29).

If SDA is sampled high, the BRG is reloaded and begins

counting. If SDA goes from high-to-low before the BRG

times out, no bus collision occurs because no two

masters can assert SDA at exactly the same time.

14.3.17.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition,

see Figure 14-30.

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user deasserts SDA and the pin is allowed to

float high, the BRG is loaded with SSPADD and counts

down to 0. The SCL pin is then deasserted and when

sampled high, the SDA pin is sampled.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

FIGURE 14-29:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared by software

‘0’

S

‘0’

SSPIF

FIGURE 14-30:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

set BCLIF. Release SDA and SCL.

BCLIF

RSEN

Interrupt cleared

by software

‘0’

S

SSPIF

 2009-2016 Microchip Technology Inc.

DS40001365F-page 167

PIC18(L)F1XK22

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPADD and

counts down to 0. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 14-31). If the SCL pin is

sampled low before SDA is allowed to float high, a bus

collision occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 14-32).

14.3.17.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high.

FIGURE 14-31:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

low after TBRG,

set BCLIF

TBRG

SDA

SDA asserted low

SCL

PEN

BCLIF

P

‘0’

SSPIF

FIGURE 14-32:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high,

set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

‘0’

SSPIF

DS40001365F-page 168

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PIC18(L)F1XK22

TABLE 14-4: SUMMARY OF REGISTERS ASSOCIATED WITH I²C

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IPR1

—

OSCFIP

—

ADIP

C1IP

ADIE

C1IE

ADIF

C1IF

RCIP

C2IP

RCIE

C2IE

RCIF

C2IF

TXIP

EEIP

TXIE

EEIE

TXIF

EEIF

SSPIP

BCLIP

SSPIE

BCLIE

SSPIF

BCLIF

CCP1IP

—

TMR2IP

TMR3IP

TMR2IE

TMR3IE

TMR2IF

TMR1IP

—

248

246

248

246

248

IPR2

PIE1

CCP1IE

—

TMR1IE

—

PIE2

OSCFIE

—

PIR1

CCP1IF

—

TMR1IF

—

PIR2

OSCFIF

TMR3IF

2

SSPADD

SSPBUF

SSPCON1

SSPCON2

SSPMSK

SSPSTAT

TRISB

SSP Address Register in I C Slave Mode. SSP Baud Rate Reload Register in I C Master Mode.

SSP Receive Buffer/Transmit Register

WCOL

GCEN

MSK7

SMP

SSPOV

ACKSTAT

MSK6

SSPEN

ACKDT

MSK5

D/A

CKP

ACKEN

MSK4

P

SSPM3

RCEN

MSK3

S

SSPM2

PEN

MSK2

R/W

SSPM1

RSEN

MSK1

UA

SSPM0

SEN

MSK0

BF

CKE

TRISB7

TRISB6

TRISB5

TRISB4

—

2

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by I C.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 169

PIC18(L)F1XK22

The EUSART module includes the following capabilities:

15.0 ENHANCED UNIVERSAL

SYNCHRONOUS

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock and data polarity

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

system.

Full-Duplex

mode

is

useful

for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 15-1 and Figure 15-2.

FIGURE 15-1:

EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIE

Interrupt

TXIF

TXREG Register

8

TX/CK pin

MSb

(8)

LSb

0

Pin Buffer

and Control

• • •

Transmit Shift Register (TSR)

TXEN

TRMT

SPEN

Baud Rate Generator

BRG16

FOSC

÷ n

TX9

n

+ 1

Multiplier x4

x16 x64

TX9D

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

SPBRGH

SPBRG

DS40001365F-page 170

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PIC18(L)F1XK22

FIGURE 15-2:

EUSART RECEIVE BLOCK DIAGRAM

SPEN

CREN

OERR

RCIDL

RX/DT pin

RSR Register

MSb

Stop (8)

LSb

0

START

Pin Buffer

and Control

Data

Recovery

7

1

• • •

Baud Rate Generator

FOSC

RX9

÷ n

BRG16

n

+ 1

Multiplier

x4

x16 x64

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

FIFO

SPBRGH

SPBRG

X

RX9D

FERR

RCREG Register

8

Data Bus

RCIF

RCIE

Interrupt

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCTL)

These registers are detailed in Register 15-1,

Register 15-2 and Register 15-3, respectively.

For all modes of EUSART operation, the TRIS control

bits corresponding to the RX/DT and TX/CK pins should

be set to ‘1’. The EUSART control will automatically

reconfigure the pin from input to output, as needed.

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DS40001365F-page 171

PIC18(L)F1XK22

15.1 EUSART Asynchronous Mode

Note 1: When the SPEN bit is set the RX/DT I/O

pin is automatically configured as an input,

regardless of the state of the

corresponding TRIS bit and whether or not

the EUSART receiver is enabled. The

RX/DT pin data can be read via a normal

PORT read but PORT latch data output is

precluded.

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH Mark state which

represents a ‘1’ data bit, and a VOL Space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the Mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is 8 bits. Each transmitted bit persists for a period

of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud

Rate Generator is used to derive standard baud rate

frequencies from the system oscillator. See Table 15-5

for examples of baud rate configurations.

2: The TXIF transmitter interrupt flag is set

when the TXEN enable bit is set.

15.1.1.2

Transmitting Data

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

15.1.1

EUSART ASYNCHRONOUS

TRANSMITTER

15.1.1.3

Transmit Data Polarity

The EUSART transmitter block diagram is shown in

Figure 15-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

The polarity of the transmit data can be controlled with

the CKTXP bit of the BAUDCON register. The default

state of this bit is ‘0’ which selects high true transmit

idle and data bits. Setting the CKTXP bit to ‘1’ will invert

the transmit data resulting in low true idle and data bits.

The CKTXP bit controls transmit data polarity only in

Asynchronous mode. In Synchronous mode the

CKTXP bit has a different function.

15.1.1.1

Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

15.1.1.4

Transmit Interrupt Flag

• TXEN = 1

• SYNC = 0

• SPEN = 1

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execution. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

All other EUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART and automatically

configures the TX/CK I/O pin as an output. If the TX/CK

pin is shared with an analog peripheral the analog I/O

function must be disabled by clearing the corresponding

ANSEL bit.

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

DS40001365F-page 172

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PIC18(L)F1XK22

15.1.1.5

TSR Status

15.1.1.7

Asynchronous Transmission Set-up

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user needs to

poll this bit to determine the TSR status.

1. Initialize the SPBRGH:SPBRG register pair and

the BRGH and BRG16 bits to achieve the desired

baud rate (see Section 15.3 “EUSART Baud

Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9

control bit. A set ninth data bit will indicate that

the 8 Least Significant data bits are an address

when the receiver is set for address detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

4. Set the CKTXP control bit if inverted transmit

data polarity is desired.

15.1.1.6

Transmitting 9-Bit Characters

5. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set, the

EUSART will shift 9 bits out for each character

transmitted. The TX9D bit of the TXSTA register is the

ninth, and Most Significant, data bit. When transmitting

9-bit data, the TX9D data bit must be written before

writing the 8 Least Significant bits into the TXREG. All

nine bits of data will be transferred to the TSR shift

register immediately after the TXREG is written.

6. If interrupts are desired, set the TXIE interrupt

enable bit. An interrupt will occur immediately

provided that the GIE and PEIE bits of the

INTCON register are also set.

7. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 15.1.2.8 “Address

Detection” for more information on the Address mode.

8. Load 8-bit data into the TXREG register. This

will start the transmission.

FIGURE 15-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RB7/TX/CK

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

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DS40001365F-page 173

PIC18(L)F1XK22

FIGURE 15-4:

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

RB7/TX/CK

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

Word 2

1 TCY

Word 1

TXIF bit

(Interrupt Reg. Flag)

1 TCY

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg

Note:

This timing diagram shows two consecutive transmissions.

TABLE 15-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

INTCON

IPR1

ABDOVF

RCIDL

DTRXP

CKTXP

INT0IE

TXIP

BRG16

RABIE

SSPIP

SSPIE

SSPIF

ADDEN

—

WUE

ABDEN

RABIF

247

245

248

247

GIE/GIEH PEIE/GIEL TMR0IE

TMR0IF

INT0IF

—

ADIP

ADIE

ADIF

RX9

RCIP

RCIE

RCIF

SREN

CCP1IP TMR2IP TMR1IP

CCP1IE TMR2IE TMR1IE

PIE1

TXIE

PIR1

—

TXIF

CCP1IF

FERR

TMR2IF

OERR

TMR1IF

RX9D

RCSTA

SPBRG

SPBRGH

TXREG

TXSTA

SPEN

CREN

EUSART Baud Rate Generator Register, Low Byte

EUSART Baud Rate Generator Register, High Byte

EUSART Transmit Register

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

DS40001365F-page 174

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

15.1.2

EUSART ASYNCHRONOUS

RECEIVER

15.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 15.1.2.5 “Receive Framing

Error” for more information on framing errors.

The Asynchronous mode would typically be used in

RS-232 systems. The receiver block diagram is shown

in Figure 15-2. The data is received on the RX/DT pin

and drives the data recovery block. The data recovery

block is actually a high-speed shifter operating at 16

times the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all 8 or 9

bits of the character have been shifted in, they are

immediately transferred to

a

two character

First-In-First-Out (FIFO) memory. The FIFO buffering

allows reception of two complete characters and the

start of a third character before software must start

servicing the EUSART receiver. The FIFO and RSR

registers are not directly accessible by software.

Access to the received data is via the RCREG register.

15.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART. The RX/DT I/O

pin must be configured as an input by setting the

corresponding TRIS control bit. If the RX/DT pin is

shared with an analog peripheral the analog I/O function

must be disabled by clearing the corresponding ANSEL

bit.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 15.1.2.6

“Receive Overrun Error” for more

information on overrun errors.

15.1.2.3

Receive Data Polarity

The polarity of the receive data can be controlled with

the DTRXP bit of the BAUDCON register. The default

state of this bit is ‘0’ which selects high true receive idle

and data bits. Setting the DTRXP bit to ‘1’ will invert the

receive data resulting in low true idle and data bits. The

DTRXP bit controls receive data polarity only in

Asynchronous mode. In Synchronous mode the

DTRXP bit has a different function.

Note:

When the SPEN bit is set the TX/CK I/O

pin is automatically configured as an

output, regardless of the state of the

corresponding TRIS bit and whether or

not the EUSART transmitter is enabled.

The PORT latch is disconnected from the

output driver so it is not possible to use the

TX/CK pin as a general purpose output.

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DS40001365F-page 175

PIC18(L)F1XK22

15.1.2.4

Receive Interrupts

15.1.2.7

Receiving 9-bit Characters

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set, the EUSART

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

RCIF interrupts are enabled by setting the following

bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE peripheral interrupt enable bit of the

INTCON register

15.1.2.8

Address Detection

• GIE global interrupt enable bit of the INTCON

register

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

register.

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit. All other characters will be ignored.

15.1.2.5

Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the EUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

15.1.2.6

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated If a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTA register.

DS40001365F-page 176

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

15.1.2.9

Asynchronous Reception Set-up

15.1.2.10 9-bit Address Detection Mode Set-up

1. Initialize the SPBRGH:SPBRG register pair and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 15.3 “EUSART

Baud Rate Generator (BRG)”).

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 15.3 “EUSART

Baud Rate Generator (BRG)”).

2. Enable the serial port by setting the SPEN bit

and the RX/DT pin TRIS bit. The SYNC bit must

be clear for asynchronous operation.

3. If interrupts are desired, set the RCIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

4. If 9-bit reception is desired, set the RX9 bit.

3. If interrupts are desired, set the RCIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

5. Set the DTRXP if inverted receive polarity is

desired.

6. Enable reception by setting the CREN bit.

4. Enable 9-bit reception by setting the RX9 bit.

7. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

5. Enable address detection by setting the ADDEN

bit.

6. Set the DTRXP if inverted receive polarity is

desired.

8. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

7. Enable reception by setting the CREN bit.

8. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

9. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

9. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register. Software determines if this is the

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 15-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

RCIDL

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 177

PIC18(L)F1XK22

TABLE 15-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON ABDOVF

RCIDL

DTRXP

CKTXP

INT0IE

TXIP

BRG16

RABIE

SSPIP

SSPIE

SSPIF

—

WUE

ABDEN

RABIF

247

245

248

247

248

247

INTCON

IPR1

GIE/GIEH PEIE/GIEL TMR0IE

TMR0IF

INT0IF

—

ADIP

ADIE

ADIF

RCIP

RCIE

RCIF

CCP1IP TMR2IP TMR1IP

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIE1

TXIE

PIR1

TXIF

RCREG

RCSTA

SPBRG

SPBRGH

TRISC

TXSTA

EUSART Receive Register

SPEN RX9 SREN

CREN

ADDEN

FERR

OERR

RX9D

EUSART Baud Rate Generator Register, Low Byte

EUSART Baud Rate Generator Register, High Byte

TRISC7

CSRC

TRISC6

TX9

TRISC5

TXEN

TRISC4

SYNC

TRISC3

SENDB

TRISC2

BRGH

TRISC1 TRISC0

TRMT TX9D

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

DS40001365F-page 178

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

The first (preferred) method uses the OSCTUNE

register to adjust the HFINTOSC output. Adjusting the

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See Section 2.7.1

“OSCTUNE Register” for more information.

15.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block

output (HFINTOSC). However, the HFINTOSC

frequency may drift as VDD or temperature changes,

and this directly affects the asynchronous baud rate.

Two methods may be used to adjust the baud rate

clock, but both require a reference clock source of

some kind.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 15.3.1

“Auto-Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

REGISTER 15-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

R/W-0

TX9

R/W-0

SYNC

R/W-0

BRGH

R-1

R/W-0

TX9D

(1)

TXEN

SENDB

TRMT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

bit 3

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

(1)

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

SYNC: EUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send Sync Break on next transmission (cleared by hardware upon completion)

0= Sync Break transmission completed

Synchronous mode:

Don’t care

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 179

PIC18(L)F1XK22

REGISTER 15-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

DS40001365F-page 180

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

REGISTER 15-3: BAUDCON: BAUD RATE CONTROL REGISTER

R-0

R-1

R/W-0

U-0

—

R/W-0

WUE

R/W-0

ABDOVF

RCIDL

DTRXP

CKTXP

BRG16

ABDEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1= Auto-baud timer overflowed

0= Auto-baud timer did not overflow

Synchronous mode:

Don’t care

RCIDL: Receive Idle Flag bit

Asynchronous mode:

1= Receiver is Idle

0= Start bit has been detected and the receiver is active

Synchronous mode:

Don’t care

DTRXP: Data/Receive Polarity Select bit

Asynchronous mode:

1= Receive data (RX) is inverted (active-low)

0= Receive data (RX) is not inverted (active-high)

Synchronous mode:

1= Data (DT) is inverted (active-low)

0= Data (DT) is not inverted (active-high)

bit 4

CKTXP: Clock/Transmit Polarity Select bit

Asynchronous mode:

1= Idle state for transmit (TX) is low

0= Idle state for transmit (TX) is high

Synchronous mode:

1= Data changes on the falling edge of the clock and is sampled on the rising edge of the clock

0= Data changes on the rising edge of the clock and is sampled on the falling edge of the clock

bit 3

BRG16: 16-bit Baud Rate Generator bit

1= 16-bit Baud Rate Generator is used (SPBRGH:SPBRG)

0= 8-bit Baud Rate Generator is used (SPBRG)

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the falling

edge. WUE will automatically clear on the rising edge.

0= Receiver is operating normally

Synchronous mode:

Don’t care

bit 0

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0= Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

 2009-2016 Microchip Technology Inc.

DS40001365F-page 181

PIC18(L)F1XK22

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is Idle before

changing the system clock.

15.3 EUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDCON register selects 16-bit

mode.

EXAMPLE 15-1:

CALCULATING BAUD

RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

The SPBRGH:SPBRG register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXSTA

register and the BRG16 bit of the BAUDCON register. In

Synchronous mode, the BRGH bit is ignored.

FOSC

Desired Baud Rate = --------------------------------------------------------------------

64[SPBRGH:SPBRG] + 1

Solving for SPBRGH:SPBRG:

FOSC

-1

X =

=

Table 15-3 contains the formulas for determining the

baud rate. Example 15-1 provides a sample calculation

for determining the baud rate and baud rate error.

(

)

64* (Desired Baud Rate)

16,000,000

64* 9600

-1

)

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 15-5. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

= 25.042 = 25

16000000

Calculated Baud Rate = --------------------------

6425 + 1

= 9615

Writing a new value to the SPBRGH, SPBRG register

pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow

before outputting the new baud rate.

Calc. Baud Rate – Desired Baud Rate

Error = --------------------------------------------------------------------------------------------

Desired Baud Rate

9615 – 9600

= ---------------------------------- = 0 . 1 6 %

9600

TABLE 15-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

BRG/EUSART Mode

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend:

x= Don’t care, n = value of SPBRGH, SPBRG register pair

TABLE 15-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Reset Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON ABDOVF RCIDL

DTRXP

SREN

CKTXP

CREN

BRG16

ADDEN

—

WUE

ABDEN

RX9D

247

RCSTA

SPBRG

SPEN

RX9

FERR

OERR

EUSART Baud Rate Generator Register, Low Byte

SPBRGH EUSART Baud Rate Generator Register, High Byte

TXSTA CSRC TX9 TXEN SYNC SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

DS40001365F-page 182

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 18.432 MHz FOSC = 12.000 MHz

FOSC = 48.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

—

77

71

38

—

239

119

29

—

1202

2404

9375

10417

18.75k

—

0.16

-2.34

0.00

-2.34

—

155

77

19

17

9

—

143

71

17

16

8

1200

2400

9600

10286

19.20k

0.00

-1.26

0.00

—

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

—

9600

9615

10417

19.23k

0.16

0.00

0.16

10417

19.2k

57.6k

115.2k

27

14

—

2

57.69k

—

0.16

—

12

—

57.60k

—

7

57.60k

—

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

0.00

—

300

1200

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

300

1200

2400

9600

—

191

47

23

5

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

10417

—

0.00

—

2

—

19.20k

0.00

—

0

—

57.60k

—

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 18.432 MHz FOSC = 12.000 MHz

FOSC = 48.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

2400

9600

10417

19.2k

57.6k

—

77

71

38

12

—

71

65

35

11

5

—

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

119

110

59

19

9

9615

10417

19.23k

57.69k

—

0.16

0.00

0.16

—

9600

0.00

0.53

0.00

—

10473

19.20k

57.60k

115.2k

19.23k

57.69k

0.16

155

51

25

115.2k 115.38k

 2009-2016 Microchip Technology Inc.

DS40001365F-page 183

PIC18(L)F1XK22

TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 8.000 MHz

FOSC = 4.000 MHz

FOSC = 3.6864 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

—

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

191

95

23

21

11

3

300

1202

2404

—

0.16

—

207

51

25

—

5

0.16

0.00

0.16

—

1200

0.00

0.53

0.00

2400

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 18.432 MHz FOSC = 12.000 MHz

FOSC = 48.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRGH

:SPBRG

(decimal)

SPBRGH

:SPBRG

(decimal)

SPBRGH

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

:SPBRG

(decimal)

:SPBRG

(decimal)

Error

300

1200

2400

9600

10417

19.2k

57.6k

300.0

1200.1

2400

0.00

0.16

0.00

0.16

9999

2499

1249

311

287

155

51

300.0

1200

0.00

-0.37

0.00

3839

959

479

119

110

59

300

1200

2404

9615

10417

19.23k

57.69k

—

0.00

0.16

0.00

0.16

—

2499

624

311

77

300.0

1200

0.00

0.53

0.00

2303

575

287

71

2400

9615

9600

10417

19.23k

57.69k

10378

19.20k

57.60k

115.2k

71

10473

19.20k

57.60k

115.2k

65

38

35

19

12

11

115.2k 115.38k

25

9

—

5

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRGH

:SPBRG

(decimal)

SPBRGH

:SPBRG

(decimal)

SPBRGH

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

:SPBRG

(decimal)

:SPBRG

(decimal)

Error

300

1200

299.9

1199

-0.02

-0.08

0.16

0.00

0.16

-3.55

—

1666

416

207

51

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

300.0

1200

0.00

0.53

0.00

767

191

95

23

21

11

3

300.5

1202

2404

—

0.16

—

207

51

25

—

5

2400

2404

9615

10417

19.23k

55556

—

2400

9600

10417

19.2k

57.6k

115.2k

47

23

10473

19.20k

57.60k

115.2k

10417

—

0.00

—

25

12

—

8

—

1

—

DS40001365F-page 184

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 18.432 MHz FOSC = 12.000 MHz

FOSC = 48.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRGH

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

:SPBRG

(decimal)

:SPBRG

(decimal)

:SPBRG

(decimal)

:SPBRG

(decimal)

Error

300

1200

2400

9600

10417

19.2k

57.6k

300

1200

0.00

0.16

39999

9999

4999

1249

1151

624

300.0

1200

0.00

0.08

0.00

15359

3839

1919

479

441

239

79

300

1200

0.00

0.16

0.00

0.16

9999

2499

1249

311

287

155

51

300.0

1200

0.00

0.16

0.00

9215

2303

1151

287

264

143

47

2400

9600

9615

9600

10417

19.20k

57.69k

10425

19.20k

57.60k

115.2k

10417

19.23k

57.69k

115.38k

10433

19.20k

57.60k

115.2k

207

115.2k 115.38k

103

39

25

23

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRGH

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

:SPBRG

(decimal)

:SPBRG

(decimal)

:SPBRG

(decimal)

:SPBRG

(decimal)

Error

300

1200

300.0

1200

0.00

-0.02

0.04

0.16

0.00

0.16

-0.79

2.12

6666

1666

832

207

191

103

34

300.0

1200

0.01

0.04

0.08

0.16

0.00

0.16

2.12

-3.55

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

3071

767

383

95

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

2400

2401

2398

2400

9600

9615

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.14k

117.6k

10417

19.23k

58.82k

111.1k

10473

19.20k

57.60k

115.2k

87

23

51

47

12

16

15

—

16

8

7

—

 2009-2016 Microchip Technology Inc.

DS40001365F-page 185

PIC18(L)F1XK22

and SPBRG registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the

average bit time when clocked at full speed.

15.3.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

Section 15.3.3 “Auto-Wake-up on

Break”).

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”), which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

Setting the ABDEN bit of the BAUDCON register starts

the auto-baud calibration sequence (Figure 15-6).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Table 15-6. The fifth rising edge will occur on the RX pin

at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPBRGH:SPBRG register pair, the ABDEN

bit is automatically cleared, and the RCIF interrupt flag

is set. A read operation on the RCREG needs to be

performed to clear the RCIF interrupt. RCREG content

should be discarded. When calibrating for modes that

do not use the SPBRGH register the user can verify

that the SPBRG register did not overflow by checking

for 00h in the SPBRGH register.

3: During the auto-baud process, the

auto-baud counter starts counting at 1.

Upon completion of the auto-baud

sequence, to achieve maximum accuracy,

subtract 1 from the SPBRGH:SPBRG

register pair.

TABLE 15-6:

BRG COUNTER CLOCK RATES

BRG Base

Clock

BRG ABD

Clock

BRG16 BRGH

0

1

FOSC/64

FOSC/16

FOSC/512

FOSC/128

1

0

1

FOSC/16

FOSC/4

FOSC/128

FOSC/32

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 15-6. During ABD,

both the SPBRGH and SPBRG registers are used as a

16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

Note:

During the ABD sequence, SPBRG and

SPBRGH registers are both used as a 16-bit

counter, independent of BRG16 setting.

FIGURE 15-6:

AUTOMATIC BAUD RATE CALIBRATION

XXXXh

0000h

001Ch

BRG Value

Edge #5

Stop bit

Edge #1

bit 1

Edge #2

bit 3

Edge #3

bit 5

Edge #4

bit 7

bit 6

RX pin

Start

bit 0

bit 2

bit 4

BRG Clock

Auto Cleared

Set by User

ABDEN bit

RCIDL

RCIF bit

(Interrupt)

Read

RCREG

XXh

1Ch

00h

SPBRG

SPBRGH

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

DS40001365F-page 186

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

15.3.2

AUTO-BAUD OVERFLOW

15.3.3.1

Special Considerations

During the course of automatic baud detection, the

ABDOVF bit of the BAUDCON register will be set if the

baud rate counter overflows before the fifth rising edge

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in the 16 bits of the SPBRGH:SPBRG register

pair. After the ABDOVF has been set, the counter

continues to count until the fifth rising edge is detected

on the RX pin. Upon detecting the fifth RX edge, the

hardware will set the RCIF Interrupt Flag and clear the

ABDEN bit of the BAUDCON register. The RCIF flag

can be subsequently cleared by reading the RCREG

register. The ABDOVF flag of the BAUDCON register

can be cleared by software directly.

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be 10 or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

To terminate the auto-baud process before the RCIF

flag is set, clear the ABDEN bit then clear the ABDOVF

bit of the BAUDCON register. The ABDOVF bit will

remain set if the ABDEN bit is not cleared first.

Oscillator Start-up Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the EUSART.

15.3.3

AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

WUE Bit

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCON register. Once set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a

wake-up event independent of the CPU mode. A

wake-up event consists of a high-to-low transition on the

RX/DT line. (This coincides with the start of a Sync Break

or a wake-up signal character for the LIN protocol.)

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared by

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared by software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 15-7), and asynchronously if

the device is in Sleep mode (Figure 15-8). The interrupt

condition is cleared by reading the RCREG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 187

PIC18(L)F1XK22

FIGURE 15-7:

AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4

OSC1

Auto Cleared

Bit set by user

WUE bit

RX/DT Line

RCIF

Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 15-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q4

Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3

Q1

Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4

Auto Cleared

OSC1

Bit Set by User

WUE bit

RX/DT Line

Note 1

RCIF

Cleared due to User Read of RCREG

Sleep Command Executed

Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

DS40001365F-page 188

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

15.3.4

BREAK CHARACTER SEQUENCE

15.3.5

RECEIVING A BREAK CHARACTER

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘0’ bits and a Stop bit.

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCSTA register and the Received data

as indicated by RCREG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

To send a Break character, set the SENDB and TXEN

bits of the TXSTA register. The Break character

transmission is then initiated by a write to the TXREG.

The value of data written to TXREG will be ignored and

all ‘0’s will be transmitted.

A Break character has been received when;

• RCIF bit is set

• FERR bit is set

• RCREG = 00h

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

The second method uses the Auto-Wake-up feature

described in Section 15.3.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RCIF interrupt, and receive the next data byte followed

by another interrupt.

The TRMT bit of the TXSTA register indicates when the

transmit operation is active or Idle, just as it does during

normal transmission. See Figure 15-9 for the timing of

the Break character sequence.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCON register before placing the EUSART in

Sleep mode.

15.3.4.1

Break and Sync Transmit Sequence

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

FIGURE 15-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

Dummy Write

BRG Output

(Shift Clock)

TX (pin)

Start bit

bit 0

bit 1

Break

bit 11

Stop bit

TXIF bit

(Transmit

interrupt Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB Sampled Here

Auto Cleared

SENDB

(send Break

control bit)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 189

PIC18(L)F1XK22

15.4.1.2

Clock Polarity

15.4 EUSART Synchronous Mode

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the CKTXP

bit of the BAUDCON register. Setting the CKTXP bit

sets the clock Idle state as high. When the CKTXP bit

is set, the data changes on the falling edge of each

clock and is sampled on the rising edge of each clock.

Clearing the CKTXP bit sets the Idle state as low. When

the CKTXP bit is cleared, the data changes on the

rising edge of each clock and is sampled on the falling

edge of each clock.

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary

circuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and

transmit shift registers. Since the data line is

bidirectional, synchronous operation is half-duplex

only. Half-duplex refers to the fact that master and

slave devices can receive and transmit data but not

both simultaneously. The EUSART can operate as

either a master or slave device.

15.4.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are

automatically enabled when the EUSART is configured

for synchronous master transmit operation.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character the new character data is held in the

TXREG until the last bit of the previous character has

been transmitted. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR. The transmission of the

character commences immediately following the

transfer of the data to the TSR from the TXREG.

Start and Stop bits are not used in synchronous

transmissions.

15.4.1

SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART

for synchronous master operation:

• SYNC = 1

• CSRC = 1

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

15.4.1.4

Data Polarity

The polarity of the transmit and receive data can be

controlled with the DTRXP bit of the BAUDCON

register. The default state of this bit is ‘0’ which selects

high true transmit and receive data. Setting the DTRXP

bit to ‘1’ will invert the data resulting in low true transmit

and receive data.

The TRIS bits corresponding to the RX/DT and TX/CK

pins should be set.

15.4.1.1

Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a master transmits the clock on the TX/CK line. The

TX/CK pin output driver is automatically enabled when

the EUSART is configured for synchronous transmit or

receive operation. Serial data bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One clock cycle is generated for each data bit.

Only as many clock cycles are generated as there are

data bits.

DS40001365F-page 190

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

3. Disable Receive mode by clearing bits SREN

and CREN.

15.4.1.5

Synchronous Master Transmission

Set-up

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

1. Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 15.3 “EUSART

Baud Rate Generator (BRG)”).

6. If interrupts are desired, set the TXIE, GIE and

PEIE interrupt enable bits.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC. Set the

TRIS bits corresponding to the RX/DT and

TX/CK I/O pins.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. Start transmission by loading data to the TXREG

register.

FIGURE 15-10:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

FIGURE 15-11:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

 2009-2016 Microchip Technology Inc.

DS40001365F-page 191

PIC18(L)F1XK22

TABLE 15-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON ABDOVF

RCIDL

DTRXP

CKTXP

INT0IE

TXIP

BRG16

RABIE

SSPIP

SSPIE

SSPIF

ADDEN

—

WUE

ABDEN

RABIF

247

245

248

247

248

247

INTCON

IPR1

GIE/GIEH PEIE/GIEL TMR0IE

TMR0IF

INT0IF

—

ADIP

ADIE

ADIF

RX9

RCIP

RCIE

RCIF

SREN

CCP1IP TMR2IP TMR1IP

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIE1

TXIE

PIR1

—

TXIF

RCSTA

SPBRG

SPBRGH

TRISC

TXREG

TXSTA

SPEN

CREN

FERR

OERR

RX9D

EUSART Baud Rate Generator Register, Low Byte

EUSART Baud Rate Generator Register, High Byte

TRISC7

EUSART Transmit Register

CSRC TX9 TXEN

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

BRGH

TRISC1

TRMT

TRISC0

TX9D

SYNC

SENDB

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

15.4.1.6 Synchronous Master Reception 15.4.1.7 Slave Clock

Data is received at the RX/DT pin. The RX/DT pin

output driver must be disabled by setting the

corresponding TRIS bits when the EUSART is

configured for synchronous master receive operation.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The

TX/CK pin output driver must be disabled by setting the

associated TRIS bit when the device is configured for

synchronous slave transmit or receive operation. Serial

data bits change on the leading edge to ensure they are

valid at the trailing edge of each clock. One data bit is

transferred for each clock cycle. Only as many clock

cycles should be received as there are data bits.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial

character is discarded. If SREN and CREN are both

set, then SREN is cleared at the completion of the first

character and CREN takes precedence.

15.4.1.8

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register or by clearing the

SPEN bit which resets the EUSART.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

Register (RSR). When a complete character is

received into the RSR, the RCIF bit is set and the

character is automatically transferred to the two

character receive FIFO. The Least Significant eight bits

of the top character in the receive FIFO are available in

RCREG. The RCIF bit remains set as long as there are

unread characters in the receive FIFO.

DS40001365F-page 192

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

3. Ensure bits CREN and SREN are clear.

15.4.1.9

Receiving 9-bit Characters

4. If using interrupts, set the GIE and PEIE bits of

the INTCON register and set RCIE.

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

5. If 9-bit reception is desired, set bit RX9.

6. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

7. Interrupt flag bit RCIF will be set when reception

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

15.4.1.10 Synchronous Master Reception

Set-up

9. Read the 8-bit received data by reading the

RCREG register.

1. Initialize the SPBRGH, SPBRG register pair for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

10. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC. Disable

RX/DT and TX/CK output drivers by setting the

corresponding TRIS bits.

FIGURE 15-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RXREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 193

PIC18(L)F1XK22

TABLE 15-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON ABDOVF

RCIDL

DTRXP

CKTXP

INT0IE

TXIP

BRG16

RABIE

SSPIP

SSPIE

SSPIF

—

WUE

ABDEN

RABIF

247

245

248

247

INTCON

IPR1

GIE/GIEH PEIE/GIEL TMR0IE

TMR0IF

CCP1IP

CCP1IE

CCP1IF

INT0IF

—

ADIP

ADIE

ADIF

RCIP

RCIE

RCIF

TMR2IP TMR1IP

TMR2IE TMR1IE

TMR2IF TMR1IF

PIE1

TXIE

PIR1

TXIF

RCREG

RCSTA

SPBRG

EUSART Receive Register

SPEN RX9 SREN

CREN

ADDEN

FERR

OERR

RX9D

EUSART Baud Rate Generator Register, Low Byte

SPBRGH EUSART Baud Rate Generator Register, High Byte

TXSTA CSRC TX9 TXEN SYNC SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

DS40001365F-page 194

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

15.4.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for synchronous slave operation:

1. The first character will immediately transfer to

the TSR register and transmit.

• SYNC = 1

2. The second word will remain in TXREG register.

3. The TXIF bit will not be set.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

15.4.2.2

Synchronous Slave Transmission

Set-up

1. Set the SYNC and SPEN bits and clear the

CSRC bit. Set the TRIS bits corresponding to

the RX/DT and TX/CK I/O pins.

RX/DT and TX/CK pin output drivers must be disabled

by setting the corresponding TRIS bits.

2. Clear the CREN and SREN bits.

3. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

TXIE bit.

15.4.2.1

EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes are identical (see Section 15.4.1.3

“Synchronous Master Transmission”), except in the

4. If 9-bit transmission is desired, set the TX9 bit.

5. Enable transmission by setting the TXEN bit.

6. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

case of the Sleep mode.

7. Start transmission by writing the Least

Significant eight bits to the TXREG register.

TABLE 15-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON ABDOVF

RCIDL

DTRXP

CKTXP

INT0IE

TXIP

BRG16

RABIE

SSPIP

SSPIE

SSPIF

ADDEN

—

WUE

ABDEN

RABIF

247

245

248

247

248

247

INTCON

IPR1

GIE/GIEH PEIE/GIEL TMR0IE

TMR0IF

INT0IF

—

ADIP

ADIE

ADIF

RX9

RCIP

RCIE

RCIF

SREN

CCP1IP TMR2IP TMR1IP

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

PIE1

TXIE

PIR1

—

TXIF

RCSTA

SPBRG

SPBRGH

TRISC

TXREG

TXSTA

SPEN

CREN

FERR

OERR

RX9D

EUSART Baud Rate Generator Register, Low Byte

EUSART Baud Rate Generator Register, High Byte

TRISC7

EUSART Transmit Register

CSRC TX9 TXEN

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

BRGH

TRISC1

TRMT

TRISC0

TX9D

SYNC

SENDB

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 195

PIC18(L)F1XK22

15.4.2.3

EUSART Synchronous Slave

Reception

15.4.2.4

Synchronous Slave Reception

Set-up

The operation of the Synchronous Master and Slave

modes is identical (Section 15.4.1.6 “Synchronous

Master Reception”), with the following exceptions:

1. Set the SYNC and SPEN bits and clear the

CSRC bit. Set the TRIS bits corresponding to

the RX/DT and TX/CK I/O pins.

2. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

RCIE bit.

• Sleep

• CREN bit is always set, therefore the receiver is

never Idle

3. If 9-bit reception is desired, set the RX9 bit.

4. Set the CREN bit to enable reception.

• SREN bit, which is a “don't care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

5. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

6. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

7. Retrieve the eight Least Significant bits from the

receive FIFO by reading the RCREG register.

8. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON ABDOVF

RCIDL

DTRXP

CKTXP

INT0IE

TXIP

BRG16

RABIE

SSPIP

SSPIE

SSPIF

—

WUE

ABDEN

RABIF

247

245

248

247

INTCON

IPR1

GIE/GIEH PEIE/GIEL TMR0IE

TMR0IF

INT0IF

—

ADIP

ADIE

ADIF

RCIP

RCIE

RCIF

CCP1IP TMR2IP TMR1IP

CCP1IE TMR2IE TMR1IE

PIE1

TXIE

PIR1

TXIF

CCP1IF

TMR2IF TMR1IF

RCREG

RCSTA

SPBRG

SPBRGH

TXSTA

EUSART Receive Register

SPEN RX9 SREN

CREN

ADDEN

FERR

OERR

RX9D

EUSART Baud Rate Generator Register, Low Byte

EUSART Baud Rate Generator Register, High Byte

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

DS40001365F-page 196

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

16.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESL and ADRESH).

The ADC voltage reference is software selectable to

either VDD, or a voltage applied to the external reference

pins.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

Figure 16-1 shows the block diagram of the ADC.

FIGURE 16-1:

ADC BLOCK DIAGRAM

NVCFG[1:0] = 00

AVSS

NVCFG[1:0] = 01

AVDD

VREF-

PVCFG[1:0] = 00

PVCFG[1:0] = 01

PVCFG[1:0] = 10

VREF+

FVR

0000

0001

0010

0011

0100

0101

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

ADC

10

GO/DONE

0= Left Justify

1= Right Justify

ADFM

ADON

10

Unused

DAC

VSS

ADRESH ADRESL

FVR

CHS<3:0>

 2009-2016 Microchip Technology Inc.

DS40001365F-page 197

PIC18(L)F1XK22

16.1.4

SELECTING AND CONFIGURING

ACQUISITION TIME

16.1 ADC Configuration

When configuring and using the ADC the following

functions must be considered:

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set.

• Port configuration

• Channel selection

Acquisition time is set with the ACQT<2:0> bits of the

ADCON2 register. Acquisition delays cover a range of

2 to 20 TAD. When the GO/DONE bit is set, the A/D

module continues to sample the input for the selected

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

acquisition time, then automatically begins

a

• Results formatting

conversion. Since the acquisition time is programmed,

there is no need to wait for an acquisition time between

selecting a channel and setting the GO/DONE bit.

16.1.1

PORT CONFIGURATION

The ANSEL, ANSELH, TRISA, TRISB and TRISE

registers all configure the A/D port pins. Any port pin

needed as an analog input should have its

corresponding ANSx bit set to disable the digital input

buffer and TRISx bit set to disable the digital output

driver. If the TRISx bit is cleared, the digital output level

(VOH or VOL) will be converted.

Manual

acquisition

is

selected

when

ACQT<2:0> = 000. When the GO/DONE bit is set,

sampling is stopped and a conversion begins. The user

is responsible for ensuring the required acquisition time

has passed between selecting the desired input

channel and setting the GO/DONE bit. This option is

also the default Reset state of the ACQT<2:0> bits and

is compatible with devices that do not offer

programmable acquisition times.

The A/D operation is independent of the state of the

ANSx bits and the TRIS bits.

Note 1: When reading the PORT register, all pins

with their corresponding ANSx bit set

read as cleared (a low level). However,

analog conversion of pins configured as

digital inputs (ANSx bit cleared and

TRISx bit set) will be accurately

converted.

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. When an acquisition time is programmed, there

is no indication of when the acquisition time ends and

the conversion begins.

16.1.5

CONVERSION CLOCK

2: Analog levels on any pin with the

corresponding ANSx bit cleared may

cause the digital input buffer to consume

current out of the device’s specification

limits.

The source of the conversion clock is software

selectable via the ADCS bits of the ADCON2 register.

There are seven possible clock options:

• FOSC/2

• FOSC/4

16.1.2

CHANNEL SELECTION

• FOSC/8

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

• FOSC/16

• FOSC/32

When changing channels, a delay is required before

starting the next conversion. Refer to Section 16.2

“ADC Operation” for more information.

• FOSC/64

• FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11 TAD periods

as shown in Figure 16-3.

16.1.3

ADC VOLTAGE REFERENCE

The PVCFG and NVCFG bits of the ADCON1 register

provide independent control of the positive and

negative voltage references, respectively. The positive

voltage reference can be either VDD, FVR or an

external voltage source. The negative voltage

reference can be either VSS or an external voltage

source.

For correct conversion, the appropriate TAD specification

must be met. See A/D conversion requirements in

Table 26-20 for more information. Table 16-1 gives

examples of appropriate ADC clock selections.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

DS40001365F-page 198

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the global interrupt must be disabled. If the

global interrupt is enabled, execution will switch to the

Interrupt Service Routine. Please see Section 16.1.6

“Interrupts” for more information.

16.1.6

INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

Conversion. The ADC interrupt flag is the ADIF bit in

the PIR1 register. The ADC interrupt enable is the ADIE

bit in the PIE1 register. The ADIF bit must be cleared by

software.

Note:

The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

TABLE 16-1: ADC CLOCK PERIOD (TAD) vs. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD)

ADC Clock Source ADCS<2:0>

Device Frequency (FOSC)

48 MHz

16 MHz

4 MHz

1 MHz

FOSC/2

FOSC/4

FOSC/8

FOSC/16

FOSC/32

FOSC/64

FRC

000

100

001

101

010

110

x11

41.67 ns⁽²⁾

83.33 ns⁽²⁾

167 ns⁽²⁾

333 ns⁽²⁾

667 ns⁽²⁾

1.33 s

125 ns⁽²⁾

250 ns⁽²⁾

500 ns⁽²⁾

1.0 s

500 ns⁽²⁾

1.0 s

2.0 s

4.0 s

2.0 s

8.0 s⁽³⁾

16.0 s⁽³⁾

32.0 s⁽³⁾

64.0 s⁽³⁾

1-4 s^(1,4)

4.0 s

2.0 s

8.0 s⁽³⁾

16.0 s⁽³⁾

1-4 s^(1,4)

4.0 s

1-4 s^(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 1.7 s.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

16.1.7

RESULT FORMATTING

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON2 register controls the output format.

Figure 16-2 shows the two output formats.

FIGURE 16-2:

10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

ADRESL

(ADFM = 0)

MSB

bit 7

LSB

bit 0

bit 7

bit 0

10-bit A/D Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 7

bit 0

Unimplemented: Read as ‘0’

10-bit A/D Result

 2009-2016 Microchip Technology Inc.

DS40001365F-page 199

PIC18(L)F1XK22

Figure 16-3 shows the operation of the A/D converter

after the GO bit has been set and the ACQT<2:0> bits

are cleared. A conversion is started after the following

instruction to allow entry into SLEEP mode before the

conversion begins.

16.2 ADC Operation

16.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will,

depending on the ACQT bits of the ADCON2 register,

either immediately start the Analog-to-Digital

conversion or start an acquisition delay followed by the

Analog-to-Digital conversion.

Figure 16-4 shows the operation of the A/D converter

after the GO bit has been set and the ACQT<2:0> bits

are set to ‘010’ which selects a 4 TAD acquisition time

before the conversion starts.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 16.2.9 “A/D Conver-

sion Procedure”.

FIGURE 16-3:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY - TAD

TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 2 TAD

TAD1 TAD2 TAD3 TAD4 TAD5

b7

b6

b4

b1

b0

b9

b8

b5

b3

b2

Conversion starts

Discharge

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

On the following cycle:

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 16-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

TAD Cycles

TACQT Cycles

7

8

9

10

b1

11 2 TAD

b0

1

2

3

4

1

2

3

4

5

6

b7

b6

b3

b2

b8

b5

b4

b9

Automatic

Acquisition

Time

Discharge

Conversion starts

(Holding capacitor is disconnected from analog input)

Set GO bit

(Holding capacitor continues

acquiring input)

On the following cycle:

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

DS40001365F-page 200

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

16.2.2

COMPLETION OF A CONVERSION

16.2.7

ADC OPERATION DURING SLEEP

When the conversion is complete, the ADC module will:

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

• Clear the GO/DONE bit

• Set the ADIF flag bit

• Update the ADRESH:ADRESL registers with new

conversion result

16.2.3

DISCHARGE

The discharge phase is used to initialize the value of

the capacitor array. The array is discharged after every

sample. This feature helps to optimize the unity-gain

amplifier, as the circuit always needs to charge the

capacitor array, rather than charge/discharge based on

previous measure values.

When the ADC clock source is something other than

FRC,

a SLEEP instruction causes the present

conversion to be aborted and the ADC module is

turned off, although the ADON bit remains set.

16.2.4

TERMINATING A CONVERSION

16.2.8

SPECIAL EVENT TRIGGER

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared by software. The

ADRESH:ADRESL registers will be updated with the

partially complete Analog-to-Digital conversion

sample. Unconverted bits will match the last bit

converted.

The CCP1 Special Event Trigger allows periodic ADC

measurements without software intervention. When

this trigger occurs, the GO/DONE bit is set by hardware

and the Timer1 or Timer3 counter resets to zero.

Using the Special Event Trigger does not assure proper

ADC timing. It is the user’s responsibility to ensure that

the ADC timing requirements are met.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

See Section 13.3.4 “Special Event Trigger” for more

information.

16.2.5

DELAY BETWEEN CONVERSIONS

After the A/D conversion is completed or aborted, a

2 TAD wait is required before the next acquisition can

be started. After this wait, the currently selected

channel is reconnected to the charge holding capacitor

commencing the next acquisition.

16.2.6

ADC OPERATION IN POWER-

MANAGED MODES

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a

power-managed mode, the ACQT<2:0> and

ADCS<2:0> bits in ADCON2 should be updated in

accordance with the clock source to be used in that

mode. After entering the mode, an A/D acquisition or

conversion may be started. Once started, the device

should continue to be clocked by the same clock

source until the conversion has been completed.

If desired, the device may be placed into the

corresponding Idle mode during the conversion. If the

device clock frequency is less than 1 MHz, the A/D FRC

clock source should be selected.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 201

PIC18(L)F1XK22

16.2.9

A/D CONVERSION PROCEDURE

EXAMPLE 16-1:

A/D CONVERSION

;This code block configures the ADC

;for polling, Vdd and Vss as reference, Frc

clock and AN4 input.

;

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

1. Configure Port:

• Disable pin output driver (See TRIS register)

• Configure pin as analog

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Select result format

;Conversion start & polling for completion

; are included.

;

MOVLW

MOVWF

MOVLW

MOVWF

BSF

B’10101111’ ;right justify, Frc,

ADCON2 ; & 12 TAD ACQ time

B’00000000’ ;ADC ref = Vdd,Vss

ADCON1

;

TRISC,0

ANSEL,4

;Set RC0 to input

;Set RC0 to analog

BSF

MOVLW

MOVWF

BSF

ADCPoll:

BTFSC

BRA

B’00010001’ ;AN4, ADC on

• Select acquisition delay

ADCON0

;

• Turn on ADC module

ADCON0,GO

;Start conversion

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

ADCON0,GO

ADCPoll

;Is conversion done?

;No, test again

; Result is complete - store 2 MSbits in

; RESULTHI and 8 LSbits in RESULTLO

MOVFF

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

ADRESH,RESULTHI

ADRESL,RESULTLO

.

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Software delay required if ACQT bits are

set to zero delay. See Section 16.3 “A/D

Acquisition Requirements”.

DS40001365F-page 202

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PIC18(L)F1XK22

16.2.10 ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

Note:

Analog pin control is performed by the

ANSEL and ANSELH registers. For

ANSEL and ANSELH registers, see

Register 8-14

respectively.

and

Register 8-15,

REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0

U-0

—

U-0

—

R/W-0

CHS3

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-2

Unimplemented: Read as ‘0’

CHS<3:0>: Analog Channel Select bits

0000= AN0

0001= AN1

0010= AN2

0011= AN3

0100= AN4

0101= AN5

0110= AN6

0111= AN7

1000= AN8

1001= AN9

1010= AN10

1011= AN11

1100= Reserved

1101= Reserved

1110= DAC⁽²⁾

1111= FVR⁽²⁾

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

Note 1: Selecting reserved channels will yield unpredictable results as unimplemented input channels are left

floating.

2: See Section 20.0 “Fixed Voltage Reference (FVR)” for more information.

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DS40001365F-page 203

PIC18(L)F1XK22

REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PVCFG1

PVCFG0

NVCFG1

NVCFG0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-2

Unimplemented: Read as ‘0’

PVCFG<1:0>: Positive Voltage Reference select bit

00= Positive voltage reference supplied internally by VDD.

01= Positive voltage reference supplied externally through VREF+ pin.

10= Positive voltage reference supplied internally through FVR.

11= Reserved.

bit 1-0

NVCFG<1:0>: Negative Voltage Reference select bit

00= Negative voltage reference supplied internally by VSS.

01= Negative voltage reference supplied externally through VREF- pin.

10= Reserved.

11= Reserved.

DS40001365F-page 204

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PIC18(L)F1XK22

REGISTER 16-3: ADCON2: A/D CONTROL REGISTER 2

R/W-0

ADFM

U-0

—

R/W-0

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

ADFM: A/D Conversion Result Format Select bit

1= Right justified

0= Left justified

bit 6

Unimplemented: Read as ‘0’

bit 5-3

ACQT<2:0>: A/D Acquisition Time Select bits. Acquisition time is the duration that the A/D charge

holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until

conversions begins.

000= 0⁽¹⁾

001= 2 TAD

010= 4 TAD

011= 6 TAD

100= 8 TAD

101= 12 TAD

110= 16 TAD

111= 20 TAD

bit 2-0

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

011= FRC⁽¹⁾(clock derived from a dedicated internal oscillator = 600 kHz nominal)

100= FOSC/4

101= FOSC/16

110= FOSC/64

111= FRC⁽¹⁾(clock derived from a dedicated internal oscillator = 600 kHz nominal)

Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction

cycle after the GO/DONE bit is set to allow the SLEEPinstruction to be executed.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 205

PIC18(L)F1XK22

REGISTER 16-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x

ADRES9

ADRES8

ADRES7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 16-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

ADRES1

ADRES0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

Reserved: Do not use.

REGISTER 16-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

ADRES9

ADRES8

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1-0

Reserved: Do not use.

ADRES<9:8>: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

REGISTER 16-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x

ADRES7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

DS40001365F-page 206

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PIC18(L)F1XK22

sources is 10 k.. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 16-1 may be used. This equation

assumes that 1/2 LSb error is used (1024 steps for the

ADC). The 1/2 LSb error is the maximum error allowed

for the ADC to meet its specified resolution.

16.3 A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 16-5. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 16-5.

The maximum recommended impedance for analog

EQUATION 16-1: ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k 3.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 5µs + TC + Temperature - 25°C0.05µs/°C

The value for TC can be approximated with the following equations:

1

2047





;[1] VCHOLD charged to within 1/2 lsb

^VAPPLIED^{1 – ----------- = VCHOLD}



–TC

---------





RC

;[2] VCHOLD charge response to VAPPLIED

V^APPLIED1 – e

= V^CHOLD









–Tc

--------

RC









1







;combining [1] and [2]

^{= VAPPLIED}^{1 – -----------}

2047

VAPPLIED 1 – e





Solving for TC:

TC = –CHOLDRIC + RSS + RS ln(1/2047)

= –13.5pF1k + 700 + 10k ln(0.0004885)

= 1.20µs

Therefore:

TACQ = 5µs + 1.20µs + 50°C- 25°C0.05µs/°C

= 7.45µs

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels

itself out.

2: The charge holding capacitor (CHOLD) is

discharged after each conversion.

3: The maximum recommended impedance

for analog sources is 10 k. This is

required to meet the pin

leakage specification.

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DS40001365F-page 207

PIC18(L)F1XK22

FIGURE 16-5:

ANALOG INPUT MODEL

VDD

VT = 0.6V

Sampling

Switch

ANx

SS

RIC  1k

Rss

Rs

CHOLD = 13.5 pF

VSS/VREF-

(1)

CPIN

5 pF

VA

I LEAKAGE

VT = 0.6V

Discharge

Switch

3.5V

3.0V

2.5V

2.0V

1.5V

Legend: CPIN

= Input Capacitance

= Threshold Voltage

VT

I LEAKAGE = Leakage current at the pin due to

various junctions

= Interconnect Resistance

= Sampling Switch

RIC

SS

100

.1

1

10

CHOLD

= Sample/Hold Capacitance

Rss (k)

Note 1: See Section 26.0 “Electrical Specifications”.

FIGURE 16-6:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

1/2 LSB ideal

Full-Scale

Transition

004h

003h

002h

001h

000h

Analog Input Voltage

1/2 LSB ideal

Zero-Scale

Transition

VDD/VREF+

VSS/VREF-

DS40001365F-page 208

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PIC18(L)F1XK22

TABLE 16-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADRESH

ADRESL

ADCON0

ADCON1

A/D Result Register, High Byte

A/D Result Register, Low Byte

247

—

CHS3

CHS2

CHS1

CHS0 GO/DONE ADON

PVCFG1 PVCFG0 NVCFG1 NVCFG0

—

ADFM

ANS7

—

ACQT2

ANS5

—

ACQT1

ANS4

—

ADCON2

ANSEL

ANSELH

INTCON

IPR1

ACQT0

ANS3

ADCS2

ANS2

ADCS1

ANS1

ADCS0

ANS0

247

248

245

248

ANS6

—

ANS11

RABIE

SSPIP

SSPIE

SSPIF

ANS10

TMR0IF

CCP1IP

CCP1IE

CCP1IF

ANS9

ANS8

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIP

TXIE

TXIF

INT0IF

TMR2IP

TMR2IE

TMR2IF

RABIF

TMR1IP

TMR1IE

TMR1IF

ADIP

ADIE

ADIF

—

RCIP

RCIE

RCIF

—

PIE1

PIR1

(1)

TRISA

—

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA2

—

TRISA1

—

TRISA0

—

TRISB

TRISC

248

—

TRISB7

TRISC7

TRISB6

TRISC6

TRISC3

TRISC2

TRISC1

TRISC0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

Note 1: Unimplemented, read as ‘1’.

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DS40001365F-page 209

PIC18(L)F1XK22

FIGURE 17-1:

SINGLE COMPARATOR

17.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

The comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of the program execution. The Analog

Comparator module includes the following features:

VIN+

VIN-

+

Output

–

VIN-

VIN+

• Independent comparator control

• Programmable input selection

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-Change

Output

• Wake-up from Sleep

• Programmable Speed/Power optimization

• PWM shutdown

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

• Programmable and fixed voltage reference

17.1

Comparator Overview

A single comparator is shown in Figure 17-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

DS40001365F-page 210

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PIC18(L)F1XK22

FIGURE 17-2:

COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM

C1CH<1:0>

2

To

Data Bus

D

Q

Q1

C12IN0-

C12IN1-

C12IN2-

C12IN3-

EN

0

RD_CM1CON0

Set C1IF

1

MUX

2

3

D

Q

Q3*RD_CM1CON0

NReset

EN

CL

(1)

C1ON

C1

C1R

C1VIN-

C1VIN+

-

C1IN+

0

MUX

1

To PWM Logic

C1OE

C1OUT

+

DAC Output

0

C1SP

C1POL

C1SYNC

MUX

1

FVR

C1VREF

0

1

C1RSEL

D

Q

C1OUT

SYNCC1OUT

(4)

From TMR1L[0]

Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

4: Positive going pulse generated on both falling and rising edges of the bit.

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DS40001365F-page 211

PIC18(L)F1XK22

FIGURE 17-3:

COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM

To

Data Bus

D

Q

Q1

EN

RD_CM2CON0

C2CH<1:0>

Set C2IF

2

D

Q

Q3*RD_CM2CON0

EN

(1)

C2ON

C2

C12IN0-

0

CL

NRESET

C2OUT

C12IN1-

C12IN2-

C12IN3-

1

MUX

2

3

C2VIN-

C2VIN+

To PWM Logic

C2SP

C2SYNC

C20E

C2POL

C2R

C2OUT pin

0

1

C2IN+

0

D

Q

MUX

DAC Output

1

(4)

From TMR1L[0]

0

SYNCC2OUT

MUX

1

FVR

C2VREF

C2RSEL

Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

4: Positive going pulse generated on both falling and rising edges of the bit.

DS40001365F-page 212

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PIC18(L)F1XK22

17.2 Comparator Control

Note 1: The CxOE bit overrides the PORT data

latch. Setting the CxON has no impact on

the port override.

Each comparator has

Configuration register: CM1CON0 for Comparator C1

and CM2CON0 for Comparator C2. In addition,

a

separate control and

Comparator C2 has

CM2CON1, for controlling the interaction with Timer1 and

simultaneous reading of both comparator outputs.

a

second control register,

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

The CM1CON0 and CM2CON0 registers (see Registers

17-1 and 17-2, respectively) contain the control and

status bits for the following:

17.2.5

COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

• Enable

• Input selection

• Reference selection

• Output selection

• Output polarity

• Speed selection

Table 17-1 shows the output state versus input

conditions, including polarity control.

TABLE 17-1: COMPARATOR OUTPUT

STATE vs. INPUT

17.2.1

COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

CONDITIONS

Input Condition

CxPOL

CxOUT

CxVIN- > CxVIN+

CxVIN- < CxVIN+

CxVIN- > CxVIN+

CxVIN- < CxVIN+

0

1

0

1

0

17.2.2

COMPARATOR INPUT SELECTION

The CxCH<1:0> bits of the CMxCON0 register direct

one of four analog input pins to the comparator

inverting input.

17.2.6

COMPARATOR SPEED SELECTION

Note:

To use CxIN+ and C12INx- pins as analog

inputs, the appropriate bits must be set in

The trade-off between speed or power can be

optimized during program execution with the CxSP

control bit. The default state for this bit is ‘1’ which

selects the normal speed mode. Device power

consumption can be optimized at the cost of slower

comparator propagation delay by clearing the CxSP bit

to ‘0’.

the

ANSEL

register

and

the

corresponding TRIS bits must also be set

to disable the output drivers.

17.2.3

COMPARATOR REFERENCE

SELECTION

Setting the CxR bit of the CMxCON0 register directs an

internal voltage reference or an analog input pin to the

noninverting input of the comparator. See Section 20.0

“Fixed Voltage Reference (FVR)” for more

information on the Internal Voltage Reference module.

17.3 Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Reference Specifications in Section 26.0

“Electrical Specifications” for more details.

17.2.4

COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CM2CON1 register. In order

to make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

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DS40001365F-page 213

PIC18(L)F1XK22

17.4.1

PRESETTING THE MISMATCH

LATCHES

17.4 Comparator Interrupt Operation

The comparator interrupt flag can be set whenever

there is a change in the output value of the comparator.

Changes are recognized by means of a mismatch

circuit which consists of two latches and an exclusive-

or gate (see Figure 17-2 and Figure 17-3). One latch is

updated with the comparator output level when the

CMxCON0 register is read. This latch retains the value

until the next read of the CMxCON0 register or the

occurrence of a Reset. The other latch of the mismatch

circuit is updated on every Q1 system clock. A

mismatch condition will occur when a comparator

output change is clocked through the second latch on

the Q1 clock cycle. At this point the two mismatch

latches have opposite output levels which is detected

by the exclusive-or gate and fed to the interrupt

circuitry. The mismatch condition persists until either

the CMxCON0 register is read or the comparator

output returns to the previous state.

The comparator mismatch latches can be preset to the

desired state before the comparators are enabled.

When the comparator is off the CxPOL bit controls the

CxOUT level. Set the CxPOL bit to the desired CxOUT

non-interrupt level while the CxON bit is cleared. Then,

configure the desired CxPOL level in the same

instruction that the CxON bit is set. Since all register

writes are performed as a Read-Modify-Write, the

mismatch latches will be cleared during the instruction

Read phase and the actual configuration of the CxON

and CxPOL bits will be occur in the final Write phase.

FIGURE 17-4:

COMPARATOR

INTERRUPT TIMING W/O

CMxCON0 READ

Q1

Q3

Note 1: A write operation to the CMxCON0

register will also clear the mismatch

condition because all writes include a read

operation at the beginning of the write

cycle.

CxIN+

TRT

CxIN

Set CxIF (edge)

CxIF

Reset by Software

2: Comparator interrupts will operate

correctly regardless of the state of CxOE.

FIGURE 17-5:

COMPARATOR

INTERRUPT TIMING WITH

CMxCON0 READ

The comparator interrupt is set by the mismatch edge

and not the mismatch level. This means that the

interrupt flag can be reset without the additional step of

reading or writing the CMxCON0 register to clear the

mismatch registers. When the mismatch registers are

cleared, an interrupt will occur upon the comparator’s

return to the previous state, otherwise no interrupt will

be generated.

Q1

Q3

CxIN+

TRT

CxOUT

Set CxIF (edge)

CxIF

Software will need to maintain information about the

status of the comparator output, as read from the

CMxCON0 register, or CM2CON1 register, to determine

the actual change that has occurred. See Figures 17-4

and 17-5.

Cleared by CMxCON0 Read

Reset by Software

The CxIF bit of the PIR2 register is the comparator

interrupt flag. This bit must be reset by software by

clearing it to ‘0’. Since it is also possible to write a ‘1’ to

this register, an interrupt can be generated.

Note 1: If a change in the CMxCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the

Q2 cycle), then the CxIF interrupt flag of

the PIR2 register may not get set.

In mid-range Compatibility mode the CxIE bit of the

PIE2 register and the PEIE and GIE bits of the INTCON

register must all be set to enable comparator interrupts.

If any of these bits are cleared, the interrupt is not

enabled, although the CxIF bit of the PIR2 register will

still be set if an interrupt condition occurs.

2: When either comparator is first enabled,

bias circuitry in the comparator module

may cause an invalid output from the

comparator until the bias circuitry is

stable. Allow about 1 s for bias settling

then clear the mismatch condition and

interrupt flags before enabling comparator

interrupts.

DS40001365F-page 214

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PIC18(L)F1XK22

17.5 Operation During Sleep

The comparator, if enabled before entering Sleep mode,

remains active during Sleep. The additional current

consumed by the comparator is shown separately in

Section 26.0 “Electrical Specifications”. If the

comparator is not used to wake the device, power

consumption can be minimized while in Sleep mode by

turning off the comparator. Each comparator is turned off

by clearing the CxON bit of the CMxCON0 register.

A change to the comparator output can wake-up the

device from Sleep. To enable the comparator to wake

the device from Sleep, the CxIE bit of the PIE2 register

and the PEIE bit of the INTCON register must be set.

The instruction following the SLEEPinstruction always

executes following a wake from Sleep. If the GIE bit of

the INTCON register is also set, the device will then

execute the Interrupt Service Routine.

17.6 Effects of a Reset

A device Reset forces the CMxCON0 and CM2CON1

registers to their Reset states. This forces both

comparators and the voltage references to their Off

states.

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DS40001365F-page 215

PIC18(L)F1XK22

REGISTER 17-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0

R/W-0

C1ON

R-0

R/W-0

C1OE

R/W-0

C1SP

R/W-0

C1R

R/W-0

C1OUT

C1POL

C1CH1

C1CH0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

C1ON: Comparator C1 Enable bit

1= Comparator C1 is enabled

0= Comparator C1 is disabled

C1OUT: Comparator C1 Output bit

If C1POL = 1(inverted polarity):

C1OUT = 0when C1VIN+ > C1VIN-

C1OUT = 1when C1VIN+ < C1VIN-

If C1POL = 0(non-inverted polarity):

C1OUT = 1when C1VIN+ > C1VIN-

C1OUT = 0when C1VIN+ < C1VIN-

bit 5

bit 4

bit 3

bit 2

bit 1-0

C1OE: Comparator C1 Output Enable bit

1= C1OUT is present on the C1OUT pin⁽¹⁾

0= C1OUT is internal only

C1POL: Comparator C1 Output Polarity Select bit

1= C1OUT logic is inverted

0= C1OUT logic is not inverted

C1SP: Comparator C1 Speed/Power Select bit

1= C1 operates in normal power, higher speed mode

0= C1 operates in low-power, low-speed mode

C1R: Comparator C1 Reference Select bit (noninverting input)

1= C1VIN+ connects to C1VREF output

0= C1VIN+ connects to C12IN+ pin

C1CH<1:0>: Comparator C1 Channel Select bit

00= C12IN0- pin of C1 connects to C1VIN-

01= C12IN1- pin of C1 connects to C1VIN-

10= C12IN2- pin of C1 connects to C1VIN-

11= C12IN3- pin of C1 connects to C1VIN-

Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1and corresponding port

TRIS bit = 0.

DS40001365F-page 216

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

REGISTER 17-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0

R/W-0

C2ON

R-0

R/W-0

C2OE

R/W-0

C2SP

R/W-0

C2R

R/W-0

C2OUT

C2POL

C2CH1

C2CH0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

C2ON: Comparator C2 Enable bit

1= Comparator C2 is enabled

0= Comparator C2 is disabled

C2OUT: Comparator C2 Output bit

If C2POL = 1(inverted polarity):

C2OUT = 0when C2VIN+ > C2VIN-

C2OUT = 1when C2VIN+ < C2VIN-

If C2POL = 0(non-inverted polarity):

C2OUT = 1when C2VIN+ > C2VIN-

C2OUT = 0when C2VIN+ < C2VIN-

bit 5

bit 4

bit 3

bit 2

bit 1-0

C2OE: Comparator C2 Output Enable bit

1= C2OUT is present on C2OUT pin⁽¹⁾

0= C2OUT is internal only

C2POL: Comparator C2 Output Polarity Select bit

1= C2OUT logic is inverted

0= C2OUT logic is not inverted

C2SP: Comparator C2 Speed/Power Select bit

1= C2 operates in normal power, higher speed mode

0= C2 operates in low-power, low-speed mode

C2R: Comparator C2 Reference Select bits (noninverting input)

1= C2VIN+ connects to C2VREF

0= C2VIN+ connects to C2IN+ pin

C2CH<1:0>: Comparator C2 Channel Select bits

00= C12IN0- pin of C2 connects to C2VIN-

01= C12IN1- pin of C2 connects to C2VIN-

10= C12IN2- pin of C2 connects to C2VIN-

11= C12IN3- pin of C2 connects to C2VIN-

Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1and corresponding port

TRIS bit = 0.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 217

PIC18(L)F1XK22

17.7 Analog Input Connection

Considerations

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

A simplified circuit for an analog input is shown in

Figure 17-6. Since the analog input pins share their

connection with a digital input, they have reverse

biased ESD protection diodes to VDD and VSS. The

analog input, therefore, must be between VSS and VDD.

If the input voltage deviates from this range by more

than 0.6V in either direction, one of the diodes is

forward biased and a latch-up may occur.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

FIGURE 17-6:

ANALOG INPUT MODEL

VDD

VT  0.6V

RIC

Rs < 10K

AIN

(1)

ILEAKAGE

CPIN

5 pF

VA

VT  0.6V

Vss

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

VT

= Threshold Voltage

Note 1: See Section 26.0 “Electrical Specifications”.

DS40001365F-page 218

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

17.8.3

COMPARATOR HYSTERESIS

17.8 Additional Comparator Features

The Comparator Cx have selectable hysteresis. The

hysteresis can be enabled by setting the CxHYS bit of

the CM2CON1 register. See Section 26.0 “Electrical

Specifications” for more details.

There are four additional comparator features:

• Simultaneous read of comparator outputs

• Internal reference selection

• Hysteresis selection

17.8.4

SYNCHRONIZING COMPARATOR

OUTPUT TO TIMER 1

• Output Synchronization

17.8.1

SIMULTANEOUS COMPARATOR

OUTPUT READ

The Comparator Cx output can be synchronized with

Timer1 by setting the CxSYNC bit of the CM2CON1

register. When enabled, the Cx output is latched on

the rising edge of the Timer1 source clock. If a

prescaler is used with Timer1, the comparator output

is latched after the prescaling function. To prevent a

race condition, the comparator output is latched on

the rising edge of the Timer1 clock source and Timer1

increments on the rising edge of its clock source. See

the Comparator Block Diagram (Figure 17-2 and

Figure 17-3) and the Timer1 Block Diagram

(Figure 17-2) for more information.

The MC1OUT and MC2OUT bits of the CM2CON1

register are mirror copies of both comparator outputs.

The ability to read both outputs simultaneously from a

single register eliminates the timing skew of reading

separate registers.

Note 1: Obtaining the status of C1OUT or

C2OUT by reading CM2CON1 does not

affect the comparator interrupt mismatch

registers.

17.8.2

INTERNAL REFERENCE

SELECTION

There are two internal voltage references available to

the noninverting input of each comparator. One of

these is the Fixed Voltage Reference (FVR) and the

other is the variable Digital-to-Analog Converter

(CVREF/DAC). The CxRSEL bit of the CM2CON

register determines which of these references is routed

to

the

Digital-to-Analog

Converter

output

(CVREF/DAC). Further routing to the comparator is

accomplished by the CxR bit of the CMxCON0 register.

See 20.0 “Fixed Voltage Reference (FVR)” and

Figure 17-2 and Figure 17-3 for more detail.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 219

PIC18(L)F1XK22

REGISTER 17-3: CMCON0: COMPARATOR 2 CONTROL REGISTER 1

R-0

R/W-0

MC1OUT

MC2OUT

C1RSEL

C2RSEL

C1HYS

C2HYS

C1SYNC

C2SYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

MC1OUT: Mirror Copy of C1OUT bit

MC2OUT: Mirror Copy of C2OUT bit

C1RSEL: Comparator C1 Reference Select bit

1= FVR routed to C1VREF input

0= CVREF/DAC1OUT routed to C1VREF input

C2RSEL: Comparator C2 Reference Select bit

1= FVR routed to C2VREF input

bit 4

0= CVREF/DAC1OUT routed to C2VREF input

C1HYS: Comparator C1 Hysteresis Enable bit

bit 3

bit 2

bit 1

bit 0

1= Comparator C1 hysteresis enabled

0= Comparator C1 hysteresis disabled

C2HYS: Comparator C2 Hysteresis Enable bit

1= Comparator C2 hysteresis enabled

0= Comparator C2 hysteresis disabled

C1SYNC: C1 Output Synchronous Mode bit

1= C1 output is synchronous to rising edge to TMR1 clock

0= C1 output is asynchronous

C2SYNC: C2 Output Synchronous Mode bit

1= C2 output is synchronous to rising edge to TMR1 clock

0= C2 output is asynchronous

DS40001365F-page 220

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PIC18(L)F1XK22

TABLE 17-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSEL

ANS7

C1ON

ANS6

C1OUT

C2OUT

MC2OUT

PEIE/GIEL

C1IP

ANS5

C1OE

ANS4

C1POL

C2POL

C2RSEL

INT0IE

EEIP

ANS3

C1SP

ANS2

C1R

ANS1

C1CH1

C2CH1

C1SYNC

INT0IF

ANS0

C1CH0

C2CH0

C2SYNC

RABIF

248

245

248

CM1CON0

CM2CON0

CM2CON1

INTCON

IPR2

C2ON

C2OE

C2SP

C2R

MC1OUT

GIE/GIEH

OSCFIP

C1RSEL

TMR0IE

C2IP

C1HYS

RABIE

BCLIP

C2HYS

TMR0IF

TMR3IP

—

LATC2

—

LATC0

—

LATC

248

LATC7

LATC6

C1IE

LATC5

C2IE

LATC4

EEIE

LATC3

BCLIE

LATC1

PIE2

OSCFIE

TMR3IE

PIR2

OSCFIF

C1IF

C2IF

RC5

EEIF

RC4

BCLIF

RC3

—

TMR3IF

RC1

—

PORTC

VREFCON0

RC7

RC6

RC2

RC0

248

247

FVR1EN

FVR1ST

FVR1S<1:0>

—

D1EN

D1LPS

DAC1OE

---

D1PSS<1:0>

D1NSS

247

VREFCON1

TRISA

—

(1)

—

TRISA5

TRISC5

TRISA4

TRISC4

—

TRISA2

TRISC2

TRISA1

TRISC1

TRISA0

TRISC0

248

TRISC

TRISC7

TRISC6

TRISC3

Legend:

— = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.

Note 1: Unimplemented, read as ‘1’.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 221

PIC18(L)F1XK22

18.1.1

CLOCK SOURCES

18.0 POWER-MANAGED MODES

The SCS<1:0> bits allow the selection of one of three

clock sources for power-managed modes. They are:

PIC18(L)F1XK22 devices offer a total of seven

operating modes for more efficient power

management. These modes provide a variety of

options for selective power conservation in applications

where resources may be limited (i.e., battery-powered

devices).

• The primary clock, as defined by the FOSC<3:0>

Configuration bits

• The secondary clock (the Timer1 oscillator)

• The internal oscillator block

There are three categories of power-managed modes:

18.1.2

ENTERING POWER-MANAGED

MODES

• Run modes

• Idle modes

• Sleep mode

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS<1:0> bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. Refer to

Section 2.9 “Clock Switching” for more information.

These categories define which portions of the device

are clocked and sometimes, what speed. The Run and

Idle modes may use any of the three available clock

sources (primary, secondary or internal oscillator

block); the Sleep mode does not use a clock source.

The power-managed modes include several power-

saving features offered on previous PIC^®microcontroller

devices. One is the clock switching feature which allows

the controller to use the Timer1 oscillator in place of the

primary oscillator. Also included is the Sleep mode,

offered by all PIC microcontroller devices, where all

device clocks are stopped.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEPinstruction. The

actual mode that results depends on the status of the

IDLEN bit of the OSCCON register.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator select

bits, or changing the IDLEN bit, prior to issuing a SLEEP

instruction. If the IDLEN bit is already configured

correctly, it may only be necessary to perform a SLEEP

instruction to switch to the desired mode.

18.1 Selecting Power-Managed Modes

Selecting

decisions:

a power-managed mode requires two

• Whether or not the CPU is to be clocked

• The selection of a clock source

The IDLEN bit of the OSCCON register controls CPU

clocking, while the SCS<1:0> bits of the OSCCON

register select the clock source. The individual modes,

bit settings, clock sources and affected modules are

summarized in Table 18-1.

TABLE 18-1: POWER-MANAGED MODES

OSCCON Bits

Module Clocking

Mode

Available Clock and Oscillator Source

IDLEN⁽¹⁾SCS<1:0>

CPU

Peripherals

Sleep

0

N/A

Off

None – All clocks are disabled

PRI_RUN

N/A

00

Clocked

Primary – LP, XT, HS, RC, EC and Internal

Oscillator Block⁽²⁾

.

This is the normal full power execution mode.

Secondary – Timer1 Oscillator

Internal Oscillator Block⁽²⁾

SEC_RUN

RC_RUN

PRI_IDLE

SEC_IDLE

RC_IDLE

N/A

1

01

1x

00

01

1x

Clocked

Off

Clocked

Primary – LP, XT, HS, HSPLL, RC, EC

Secondary – Timer1 Oscillator

Internal Oscillator Block⁽²⁾

1

Off

1

Off

Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.

2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.

DS40001365F-page 222

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PIC18(L)F1XK22

18.1.3

MULTIPLE FUNCTIONS OF THE

SLEEP COMMAND

18.2.3

RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator. In this mode, the

primary external oscillator is shut down. RC_RUN

mode provides the best power conservation of all the

Run modes when the LFINTOSC is the system clock.

The power-managed mode that is invoked with the

SLEEP instruction is determined by the setting of the

IDLEN bit of the OSCCON register at the time the

instruction is executed. All clocks stop and minimum

power is consumed when SLEEPis executed with the

IDLEN bit cleared. The system clock continues to

supply a clock to the peripherals but is disconnected

from the CPU when SLEEPis executed with the IDLEN

bit set.

RC_RUN mode is entered by setting the SCS1 bit.

When the clock source is switched from the primary

oscillator to the internal oscillator, the primary oscillator

is shut down and the OSTS bit is cleared. The IRCF bits

may be modified at any time to immediately change the

clock speed.

18.2 Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

18.2.1

PRI_RUN MODE

The PRI_RUN mode is the normal, full power execution

mode of the microcontroller. This is also the default

mode upon a device Reset, unless Two-Speed Start-up

is enabled (see Section 2.11 “Two-Speed Start-up

Mode” for details). In this mode, the device operated

off the oscillator defined by the FOSC bits of the

CONFIGH Configuration register.

18.2.2

SEC_RUN MODE

In SEC_RUN mode, the CPU and peripherals are

clocked from the secondary external oscillator. This

gives users the option of lower power consumption

while still using a high accuracy clock source.

SEC_RUN mode is entered by setting the SCS<1:0>

bits of the OSCCON register to ‘01’. When SEC_RUN

mode is active all of the following are true:

• The main clock source is switched to the

secondary external oscillator

• Primary external oscillator is shut down

• T1RUN bit of the T1CON register is set

• OSTS bit is cleared.

Note:

The secondary external oscillator should

already be running prior to entering

SEC_RUN mode. If the T1OSCEN bit is

not set when the SCS<1:0> bits are set to

‘01’, entry to SEC_RUN mode will not

occur until T1OSCEN bit is set and

secondary external oscillator is ready.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 223

PIC18(L)F1XK22

18.3 Sleep Mode

18.4 Idle Modes

The

Power-Managed

Sleep

mode

in

the

The Idle modes allow the controller’s CPU to be

selectively shut down while the peripherals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

PIC18(L)F1XK22 devices is identical to the legacy

Sleep mode offered in all other PIC microcontroller

devices. It is entered by clearing the IDLEN bit of the

OSCCON register and executing the SLEEPinstruction.

This shuts down the selected oscillator (Figure 18-1)

and all clock source status bits are cleared.

If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is

executed, the peripherals will be clocked from the clock

source selected by the SCS<1:0> bits; however, the CPU

will not be clocked. The clock source status bits are not

affected. Setting IDLEN and executing a SLEEP

instruction provides a quick method of switching from a

given Run mode to its corresponding Idle mode.

Entering the Sleep mode from either Run or Idle mode

does not require a clock switch. This is because no

clocks are needed once the controller has entered

Sleep. If the WDT is selected, the LFINTOSC source

will continue to operate. If the Timer1 oscillator is

enabled, it will also continue to run.

If the WDT is selected, the LFINTOSC source will

continue to operate. If the Timer1 oscillator is enabled,

it will also continue to run.

When a wake event occurs in Sleep mode (by interrupt,

Reset or WDT time-out), the device will not be clocked

until the clock source selected by the SCS<1:0> bits

becomes ready (see Figure 18-2), or it will be clocked

from the internal oscillator block if either the Two-Speed

Start-up or the Fail-Safe Clock Monitor are enabled

(see Section 23.0 “Special Features of the CPU”). In

either case, the OSTS bit is set when the primary clock

is providing the device clocks. The IDLEN and SCS bits

are not affected by the wake-up.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

time-out, or a Reset. When a wake event occurs, CPU

execution is delayed by an interval of TCSD while it

becomes ready to execute code. When the CPU

begins executing code, it resumes with the same clock

source for the current Idle mode. For example, when

waking from RC_IDLE mode, the internal oscillator

block will clock the CPU and peripherals (in other

words, RC_RUN mode). The IDLEN and SCS bits are

not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS<1:0> bits.

FIGURE 18-1:

TRANSITION TIMING FOR ENTRY TO SLEEP MODE

Q1 Q2 Q3 Q4 Q1

OSC1

CPU

Clock

Peripheral

Clock

Sleep

Program

Counter

PC

PC + 2

FIGURE 18-2:

TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q2 Q3 Q4 Q1 Q2

Q1

OSC1

(1)

TOST

TPLL

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

PC + 4

PC + 6

Wake Event

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

OSTS bit set

DS40001365F-page 224

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

18.4.1

PRI_IDLE MODE

18.4.2

SEC_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm-up” or transition from another

oscillator.

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator. This mode is entered from SEC_RUN by

setting the IDLEN bit and executing

a SLEEP

instruction. If the device is in another Run mode, set the

IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and

execute SLEEP. When the clock source is switched to

the Timer1 oscillator, the primary oscillator is shut

down, the OSTS bit is cleared and the T1RUN bit is set.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing

a SLEEP

instruction. If the device is in another Run mode, set

IDLEN first, then clear the SCS bits and execute

SLEEP. Although the CPU is disabled, the peripherals

continue to be clocked from the primary clock source

specified by the FOSC<3:0> Configuration bits. The

OSTS bit remains set (see Figure 18-3).

When a wake event occurs, the peripherals continue

to be clocked from the Timer1 oscillator. After an

interval of TCSD following the wake event, the CPU

begins executing code being clocked by the Timer1

oscillator. The IDLEN and SCS bits are not affected by

the wake-up; the Timer1 oscillator continues to run

(see Figure 18-4).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become ready to execute instructions. After the wake-

up, the OSTS bit remains set. The IDLEN and SCS bits

are not affected by the wake-up (see Figure 18-4).

Note:

The Timer1 oscillator should already be

running prior to entering SEC_IDLE

mode. If the T1OSCEN bit is not set when

the SLEEP instruction is executed, the

main system clock will continue to operate

in the previously selected mode and the

corresponding IDLE mode will be entered

(i.e., PRI_IDLE or RC_IDLE).

FIGURE 18-3:

TRANSITION TIMING FOR ENTRY TO IDLE MODE

Q3

Q4

Q1

Q2

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

FIGURE 18-4:

TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Q1

Q3

Q4

Q2

OSC1

TCSD

CPU Clock

Peripheral

Clock

Program

Counter

PC

Wake Event

 2009-2016 Microchip Technology Inc.

DS40001365F-page 225

PIC18(L)F1XK22

18.4.3

RC_IDLE MODE

18.5 Exiting Idle and Sleep Modes

In RC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the internal

oscillator block from the HFINTOSC multiplexer output.

This mode allows for controllable power conservation

during Idle periods.

An exit from Sleep mode or any of the Idle modes is

triggered by any one of the following:

• An interrupt

• A Reset

• A Watchdog Time-out

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If the

device is in another Run mode, first set IDLEN, then set

the SCS1 bit and execute SLEEP. It is recommended

that SCS0 also be cleared, although its value is

ignored, to maintain software compatibility with future

devices. The HFINTOSC multiplexer may be used to

select a higher clock frequency by modifying the IRCF

bits before executing the SLEEPinstruction. When the

clock source is switched to the HFINTOSC multiplexer,

the primary oscillator is shut down and the OSTS bit is

cleared.

This section discusses the triggers that cause exits

from power-managed modes. The clocking subsystem

actions are discussed in each of the power-managed

modes

(see

Section 18.2

“Run

Modes”,

Section 18.3 “Sleep Mode” and Section 18.4 “Idle

Modes”).

18.5.1

EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit from an Idle mode or the Sleep mode to

a Run mode. To enable this functionality, an interrupt

source must be enabled by setting its enable bit in one

of the INTCON or PIE registers. The PEIE bit must also

be set If the desired interrupt enable bit is in a PIE

register. The exit sequence is initiated when the

corresponding interrupt flag bit is set.

If the IRCF bits are set to any non-zero value, or the

INTSRC bit is set, the HFINTOSC output is enabled.

The IOSF bit becomes set, after the HFINTOSC output

becomes stable, after an interval of TIOBST. Clocks to

the peripherals continue while the HFINTOSC source

stabilizes. If the IRCF bits were previously at a non-

zero value, or INTSRC was set before the SLEEP

instruction was executed and the HFINTOSC source

was already stable, the IOSF bit will remain set. If the

IRCF bits and INTSRC are all clear, the HFINTOSC

output will not be enabled, the IOSF bit will remain clear

and there will be no indication of the current clock

source.

The instruction immediately following the SLEEP

instruction is executed on all exits by interrupt from Idle

or Sleep modes. Code execution then branches to the

interrupt vector if the GIE/GIEH bit of the INTCON

register is set, otherwise code execution continues

without branching (see Section 7.0 “Interrupts”).

A fixed delay of interval TCSD following the wake event

is required when leaving Sleep and Idle modes. This

delay is required for the CPU to prepare for execution.

Instruction execution resumes on the first clock cycle

following this delay.

When a wake event occurs, the peripherals continue to

be clocked from the HFINTOSC multiplexer output.

After a delay of TCSD following the wake event, the CPU

begins executing code being clocked by the

HFINTOSC multiplexer. The IDLEN and SCS bits are

not affected by the wake-up. The LFINTOSC source

will continue to run if either the WDT or the Fail-Safe

Clock Monitor is enabled.

18.5.2

EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending

on which power-managed mode the device is in when

the time-out occurs.

If the device is not executing code (all Idle modes and

Sleep mode), the time-out will result in an exit from the

power-managed mode (see Section 18.2 “Run

Modes” and Section 18.3 “Sleep Mode”). If the

device is executing code (all Run modes), the time-out

will result in

a WDT Reset (see Section 23.2

“Watchdog Timer (WDT)”).

The WDT timer and postscaler are cleared by any one

of the following:

• Executing a SLEEPinstruction

• Executing a CLRWDTinstruction

• The loss of the currently selected clock source

when the Fail-Safe Clock Monitor is enabled

• Modifying the IRCF bits in the OSCCON register

when the internal oscillator block is the device

clock source

DS40001365F-page 226

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

18.5.3

EXIT BY RESET

18.5.4

EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Exiting Sleep and Idle modes by Reset causes code

execution to restart at address 0. See Section 22.0

“Reset” for more details.

Certain exits from power-managed modes do not

invoke the OST at all. There are two cases:

The exit delay time from Reset to the start of code

execution depends on both the clock sources before

and after the wake-up and the type of oscillator. Exit

delays are summarized in Table 18-2.

• PRI_IDLE mode, where the primary clock source

is not stopped and

• The primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these instances, the primary clock source either

does not require an oscillator start-up delay since it is

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (RC, EC, INTOSC,

and INTOSCIO modes). However, a fixed delay of

interval TCSD following the wake event is still required

when leaving Sleep and Idle modes to allow the CPU

to prepare for execution. Instruction execution resumes

on the first clock cycle following this delay.

TABLE 18-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up

Clock Source

after Wake-up

Clock Ready Status

Bit (OSCCON)

Exit Delay

LP, XT, HS

HSPLL

OSTS

IOSF

OSTS

IOSF

OSTS

IOSF

OSTS

IOSF

Primary Device Clock

(PRI_IDLE mode)

(1)

TCSD

EC, RC

HFINTOSC⁽²⁾

LP, XT, HS

HSPLL

(3)

TOST

(3)

TOST + t_PLL

T1OSC or LFINTOSC⁽¹⁾

(1)

EC, RC

TCSD

HFINTOSC⁽¹⁾

LP, XT, HS

HSPLL

TIOBST

(4)

TOST

(3)

TOST + t_PLL

HFINTOSC⁽²⁾

(1)

EC, RC

TCSD

HFINTOSC⁽¹⁾

LP, XT, HS

HSPLL

None

(3)

TOST

TOST + t_PLL

None

(Sleep mode)

(1)

EC, RC

HFINTOSC⁽¹⁾

TCSD

(4)

TIOBST

Note 1: TCSD is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other

required delays (see Section 18.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.

2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.

3: TOST is the Oscillator Start-up Timer. t_PLLis the PLL Lock-out Timer (parameter F12).

4: Execution continues during the HFINTOSC stabilization period, TIOBST.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 227

PIC18(L)F1XK22

19.2 Latch Output

19.0 SR LATCH

The SRQEN and SRNQEN bits of the SRCON0 register

control the latch output selection. Both of the SR latch’s

outputs may be directly output to an independent I/O

pin. Control is determined by the state of bits SRQEN

and SRNQEN in registers SRCON0.

The module consists of a single SR latch with multiple

Set and Reset inputs as well as selectable latch output.

The SR latch module includes the following features:

• Programmable input selection

• SR latch output is available internally/externally

• Selectable Q and Q output

• Firmware Set and Reset

The applicable TRIS bit of the corresponding port must

be cleared to enable the port pin output driver.

• SR Latch

19.3 Effects of a Reset

Upon any device Reset, the SR latch is not initialized.

The user’s firmware is responsible to initialize the latch

output before enabling it to the output pins.

19.1 Latch Operation

The latch is a Set-Reset latch that does not depend on a

clock source. Each of the Set and Reset inputs are

active-high. The latch can be Set or Reset by CxOUT,

INT1 pin, or variable clock. Additionally the SRPS and

the SRPR bits of the SRCON0 register may be used to

Set or Reset the SR latch, respectively. The latch is

reset-dominant, therefore, if both Set and Reset inputs

are high the latch will go to the Reset state. Both the

SRPS and SRPR bits are self resetting which means

that a single write to either of the bits is all that is

necessary to complete a latch Set or Reset operation.

FIGURE 19-1:

SR LATCH SIMPLIFIED BLOCK DIAGRAM

SRPS

Pulse

SRLEN

SRQEN

Gen⁽²⁾

INT1

(3)

S

Q

SRSPE

SRCLK

SRQ pin

SRSCKE

(4)

SYNCC2OUT

SRSC2E

(4)

SYNCC1OUT

SRSC1E

SR

Latch

(1)

SRPR

Pulse

Gen⁽²⁾

INT1

(3)

SRRPE

SRCLK

R

Q

SRNQ pin

SRRCKE

SRLEN

SRNQEN

(4)

SYNCC2OUT

SRRC2E

(4)

SYNCC1OUT

SRRC1E

Note 1: If R = 1and S = 1simultaneously, Q = 0, Q = 1

2: Pulse generator causes a 2 Q-state pulse width.

3: Output shown for reference only. See I/O port pin block diagram for more detail.

4: Name denotes the source of connection at the comparator output.

DS40001365F-page 228

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 19-1: SRCLK FREQUENCY TABLE

SRCLK

Divider

FOSC = 20 MHz

FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz

FOSC = 1 MHz

111

110

101

100

011

010

001

000

512

256

128

64

32

16

8

25.6 s

12.8 s

6.4 s

3.2 s

1.6 s

0.8 s

0.4 s

0.2 s

32 s

16 s

8 s

64 s

32 s

16 s

8 s

128 s

64 s

32 s

16 s

8 s

512 s

256 s

128 s

64 s

32 s

16 s

8 s

4 s

2 s

4 s

1 s

2 s

4 s

0.5 s

0.25 s

1 s

2 s

4

0.5 s

1 s

4 s

REGISTER 19-1: SRCON0: SR LATCH CONTROL REGISTER

R/W-0

SRPS

R/W-0

SRPR

bit 0

SRLEN

SRCLK2

SRCLK1

SRCLK0

SRQEN

SRNQEN

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented

‘0’ = Bit is cleared

C = Clearable only bit

x = Bit is unknown

-n = Value at POR

bit 7

SRLEN: SR Latch Enable bit⁽¹⁾

1= SR latch is enabled

0= SR latch is disabled

bit 6-4

SRCLK<2:0>⁽¹⁾: SR Latch Clock divider bits

000 = 1/4 Peripheral cycle clock

001 = 1/8 Peripheral cycle clock

010 = 1/16 Peripheral cycle clock

011 = 1/32 Peripheral cycle clock

100 = 1/64 Peripheral cycle clock

101 = 1/128 Peripheral cycle clock

110 = 1/256 Peripheral cycle clock

111 = 1/512 Peripheral cycle clock

bit 3

bit 2

bit 1

bit 0

SRQEN: SR Latch Q Output Enable bit

1= Q is present on the SRQ pin

0= Q is internal only

SRNQEN: SR Latch Q Output Enable bit

1= Q is present on the SRNQ pin

0= Q is internal only

SRPS: Pulse Set Input of the SR Latch bit

1= Pulse input

0= Always reads back ‘0’

SRPR: Pulse Reset Input of the SR Latch bit

1= Pulse input

0= Always reads back ‘0’

Note 1: Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset

inputs of the latch.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 229

PIC18(L)F1XK22

REGISTER 19-2: SRCON1: SR LATCH CONTROL REGISTER 1

R/W-0

SRSPE

SRSCKE

SRSC2E

SRSC1E

SRRPE

SRRCKE

SRRC2E

SRRC1E

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented

‘0’ = Bit is cleared

C = Clearable only bit

x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SRSPE: SR Latch Peripheral Set Enable bit

1= INT1 pin status sets SR latch

0= INT1 pin status has no effect on SR latch

SRSCKE: SR Latch Set Clock Enable bit

1= Set input of SR latch is pulsed with SRCLK

0= Set input of SR latch is not pulsed with SRCLK

SRSC2E: SR Latch C2 Set Enable bit

1= C2 Comparator output sets SR latch

0= C2 Comparator output has no effect on SR latch

SRSC1E: SR Latch C1 Set Enable bit

1= C1 Comparator output sets SR latch

0= C1 Comparator output has no effect on SR latch

SRRPE: SR Latch Peripheral Reset Enable bit

1= INT1 pin resets SR latch

0= INT1 pin has no effect on SR latch

SRRCKE: SR Latch Reset Clock Enable bit

1= Reset input of SR latch is pulsed with SRCLK

0= Reset input of SR latch is not pulsed with SRCLK

SRRC2E: SR Latch C2 Reset Enable bit

1= C2 Comparator output resets SR latch

0= C2 Comparator output has no effect on SR latch

SRRC1E: SR Latch C1 Reset Enable bit

1= C1 Comparator output resets SR latch

0= C1 Comparator output has no effect on SR latch

TABLE 19-2: REGISTERS ASSOCIATED WITH THE SR LATCH

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CM2CON1

INTCON3

SRCON0

SRCON1

TRISC

MC1OUT MC2OUT C1RSEL C2RSEL C1HYS

C2HYS C1SYNC C2SYNC

248

245

248

INT2IP

SRLEN

INT1IP

—

INT2IE

INT1IE

—

INT2IF

SRPS

INT1IF

SRPR

SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN

SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

Legend: Shaded cells are not used with the SR Latch module.

DS40001365F-page 230

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

20.1 Independent Gain Amplifiers

20.0 FIXED VOLTAGE REFERENCE

(FVR)

The output of the FVR supplied to the ADC,

Comparators and DAC is routed through an

independent programmable gain amplifier. The

amplifier can be configured to amplify the 1.024V

reference voltage by 1x, 2x or 4x, to produce the three

possible voltage levels.

The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,

2.048V or 4.096V selectable output levels. The output

of the FVR can be configured to supply a reference

voltage to the following:

The FVR1S<1:0> bits of the VREFCON0 register are

used to enable and configure the gain amplifier settings

for the reference supplied to the DAC and Comparator

modules. When the ADC module is configured to use

the FVR output, (FVR1BUF2) the reference is buffered

through an additional unity gain amplifier. This buffer is

disabled if the ADC is not configured to use the FVR.

• ADC input channel

• ADC positive reference

• Comparator positive input

• Digital-to-Analog Converter (DAC)

The FVR can be enabled by setting the FVR1EN bit of

the VREFCON0 register.

For specific use of the FVR, refer to the specific module

sections: Section 16.0 “Analog-to-Digital Converter

(ADC) Module”, Section 21.0 “Digital-to-Analog

Converter (DAC) Module” and Section 17.0 “Com-

parator Module”.

20.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to

stabilize. Once the circuits stabilize and are ready for use,

the FVR1ST bit of the VREFCON0 register will be set.

See Table 26-23 for the minimum delay requirement.

FIGURE 20-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

FVR_buf2_enable⁽¹⁾

FVR1BUF2

FVR1BUF1

x1

x2

x4

to ADC module

FVR1S<1:0>

2

x1

x2

x4

to Comparators, DAC

1.024V

+

-

FVR1EN

Fixed

Voltage

FVR1ST

Reference

Note 1: FVR_buf2_enable = ‘1’ when (ADON = ‘1’)AND [(PVCFG<1:0> = ‘10’) OR ( CHS<4:0> = ‘11111’)]

 2009-2016 Microchip Technology Inc.

DS40001365F-page 231

PIC18(L)F1XK22

20.3 Register Definitions: FVR Control

REGISTER 20-1: VREFCON0: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

R/W-1

U-0

—

FVR1EN

FVR1ST

FVR1S<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

FVR1EN: Fixed Voltage Reference Enable bit

0= Fixed Voltage Reference is disabled

1= Fixed Voltage Reference is enabled

bit 6

FVR1ST: Fixed Voltage Reference Ready Flag bit

0= Fixed Voltage Reference output is not ready or not enabled

1= Fixed Voltage Reference output is ready for use

bit 5-4

FVR1S<1:0>: Fixed Voltage Reference Selection bits

00= Fixed Voltage Reference Peripheral output is off

01= Fixed Voltage Reference Peripheral output is 1x (1.024V)

10= Fixed Voltage Reference Peripheral output is 2x (2.048V)⁽¹⁾

11= Fixed Voltage Reference Peripheral output is 4x (4.096V)⁽¹⁾

bit 3-2

bit 1-0

Reserved: Read as ‘0’. Maintain these bits clear.

Unimplemented: Read as ‘0’.

Note 1: Fixed Voltage Reference output cannot exceed VDD.

TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Valueson

Page

—

VREFCON0

FVR1EN

FVR1ST

FVR1S<1:0>

232

Legend:

— = unimplemented locations, read as ‘0’. Shaded bits are not used by the FVR module.

DS40001365F-page 232

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

The negative voltage source is disabled by setting the

D1LPS bit in the VREFCON1 register. Clearing the

D1LPS bit in the VREFCON1 register disables the

positive voltage source.

21.0 DIGITAL-TO-ANALOG

CONVERTER (DAC) MODULE

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,

with 32 selectable output levels.

21.4 Output Clamped to Positive

Voltage Source

The input of the DAC can be connected to:

• External VREF pins

The DAC output voltage can be set to VSRC+ with the

least amount of power consumption by performing the

following:

• VDD supply voltage

• FVR (Fixed Voltage Reference)

• Clearing the D1EN bit in the VREFCON1 register.

• Setting the D1LPS bit in the VREFCON1 register.

The output of the DAC can be configured to supply a

reference voltage to the following:

• Configuring the D1PSS bits to the proper positive

source.

• Comparator positive input

• ADC input channel

• DAC1OUT pin

• Configuring the DAC1Rx bits to ‘11111’ in the

VREFCON2 register.

The Digital-to-Analog Converter (DAC) can be enabled

by setting the D1EN bit of the VREFCON1 register.

This is also the method used to output the voltage level

from the FVR to an output pin. See Section 21.6 “DAC

Voltage Reference Output” for more information.

21.1 Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels

are set with the DAC1R<4:0> bits of the VREFCON2

register.

21.5 Output Clamped to Negative

Voltage Source

The DAC output voltage can be set to VSRC- with the

least amount of power consumption by performing the

following:

The DAC output voltage is determined by the following

equations:

• Clearing the D1EN bit in the VREFCON1 register.

• Clearing the DAC1R bit in the VREFCON1 register.

EQUATION 21-1: DAC OUTPUT VOLTAGE

DACR<4:0>







+ VSRC-

VOUT = VSRC+ – VSRC-  ------------------------------

• Configuring the D1PSS bits to the proper negative

source.



5

2

• Configuring the DAC1Rx bits to ‘00000’ in the

VREFCON2 register.

VSRC+ = VDD, VREF+ or FVR1

VSRC- = VSS or VREF-

This allows the comparator to detect a zero-crossing

while not consuming additional current through the DAC

module.

21.6 DAC Voltage Reference Output

21.2 Ratiometric Output Level

The DAC can be output to the DAC1OUT (CVREF) pin by

setting the DAC1OE bit of the VREFCON1 register to ‘1’.

Selecting the DAC reference voltage for output on the

DAC1OUT pin automatically overrides the digital output

buffer and digital input threshold detector functions of

that pin. Reading the DAC1OUT pin when it has been

configured for DAC reference voltage output will always

return a ‘0’.

The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage

of either input source fluctuates, a similar fluctuation will

result in the DAC output value.

The value of the individual resistors within the ladder

can be found in Section 26.0 “Electrical

Specifications”.

Due to the limited current drive capability, a buffer must

be used on the DAC voltage reference output for

external connections to DAC1OUT. Figure 21-2 shows

an example buffering technique.

21.3 Low-Power Voltage State

In order for the DAC module to consume the least

amount of power, one of the two voltage reference input

sources to the resistor ladder must be disconnected.

Either the positive voltage source, (VSRC+), or the

negative voltage source, (VSRC-) can be disabled.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 233

PIC18(L)F1XK22

FIGURE 21-1:

DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

Digital-to-Analog Converter (DAC)

Reserved

FVR1BUF1

VREF+

11

10

VSRC+

DAC1R<4:0>

01

00

5

VDD

R

2

11111

R

D1PSS<1:0>

11110

R

D1EN

D1LPS

R

32

Steps

DAC Output

(to Comparators and

ADC Modules)

R

00001

CVREF/DAC1OUT

DAC1OE

R

00000

D1NSS

1

VREF-

VSS

VSRC-

0

FIGURE 21-2:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC^®MCU

DAC

Module

R

+

–

Buffered DAC Output

DAC1OUT

Voltage

Reference

Output

Impedance

DS40001365F-page 234

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

21.7 Operation During Sleep

21.8 Effects of a Reset

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the VREFCON1 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

A device Reset affects the following:

• DAC is disabled

• DAC output voltage is removed from the

DAC1OUT pin

• The DAC1R<4:0> range select bits are cleared

21.9 Register Definitions: DAC Control

REGISTER 21-1: VREFCON1: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0

D1EN

R/W-0

U-0

R/W-0

U-0

R/W-0

—

D1LPS

DAC1OE

D1PSS<1:0>

D1NSS

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

D1EN: DAC Enable bit

1= DAC is enabled

0= DAC is disabled

D1LPS: DAC Low-Power Voltage Source Select bit

1= DAC Positive reference source selected

0= DAC Negative reference source selected

bit 5

DAC1OE: DAC Voltage Output Enable bit

1= DAC voltage level is also an output on the DAC1OUT (CVREF) pin

0= DAC voltage level is disconnected from the DAC1OUT (CVREF) pin

bit 4

Unimplemented: Read as ‘0’

bit 3-2

D1PSS<1:0>: DAC Positive Source Select bits

00= VDD

01= VREF+

10= FVR1BUF1 output

11= Reserved, do not use

bit 1

bit 0

Unimplemented: Read as ‘0’

D1NSS: DAC Negative Source Select bits

1= VREF-

0= VSS

 2009-2016 Microchip Technology Inc.

DS40001365F-page 235

PIC18(L)F1XK22

REGISTER 21-2: VREFCON2: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0

R/W-0

—

DAC1R<4:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

DAC1R<4:0>: DAC Voltage Output Select bits

VOUT = ((VSRC+) - (VSRC-))*(DAC1R<4:0>/(2⁵)) + VSRC-

TABLE 21-1: REGISTERS ASSOCIATED WITH DAC MODULE

Reset

Valueson

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VREFCON0

VREFCON1

VREFCON2

Legend:

FVR1EN

D1EN

—

FVR1ST

D1LPS

—

FVR1S<1:0>

—

232

235

236

DAC1OE

—

D1PSS<1:0>

DAC1R<4:0>

D1NSS

— = Unimplemented locations, read as ‘0’. Shaded bits are not used by the DAC module.

DS40001365F-page 236

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 22-1.

22.0 RESET

The PIC18(L)F1XK22 devices differentiate between

various kinds of Reset:

22.1 RCON Register

a) Power-on Reset (POR)

Device Reset events are tracked through the RCON

register (Register 22-1). The lower five bits of the

register indicate that a specific Reset event has

occurred. In most cases, these bits can only be cleared

by the event and must be set by the application after

the event. The state of these flag bits, taken together,

can be read to indicate the type of Reset that just

occurred. This is described in more detail in

Section 22.6 “Reset State of Registers”.

b) MCLR Reset during normal operation

c) MCLR Reset during power-managed modes

d) Watchdog Timer (WDT) Reset (during

execution)

e) Programmable Brown-out Reset (BOR)

f) RESETInstruction

g) Stack Full Reset

h) Stack Underflow Reset

The RCON register also has control bits for setting

interrupt priority (IPEN) and software control of the

BOR (SBOREN). Interrupt priority is discussed in

Section 7.0 “Interrupts”. BOR is covered in

Section 22.4 “Brown-out Reset (BOR)”.

This section discusses Resets generated by MCLR,

POR and BOR and covers the operation of the various

start-up timers. Stack Reset events are covered in

Section 3.1.2.4 “Stack Overflow and Underflow

Resets”. WDT Resets are covered in Section 23.2

“Watchdog Timer (WDT)”.

FIGURE 22-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack Full/Underflow Reset

Stack

Pointer

External Reset

MCLRE

MCLR

( )_IDLE

Sleep

WDT

Time-out

VDD Rise

Detect

POR Pulse

VDD

Brown-out

Reset

S

BOREN

OST/PWRT

OST

(2)

1024 Cycles

Chip_Reset

10-bit Ripple Counter

R

Q

OSC1

32 s

(2)

65.5 ms

PWRT

LFINTOSC

11-bit Ripple Counter

Enable PWRT

(1)

Enable OST

Note 1: See Table 22-2 for time-out situations.

2: PWRT and OST counters are reset by POR and BOR. See Sections 22.3 and 22.4.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 237

PIC18(L)F1XK22

REGISTER 22-1: RCON: RESET CONTROL REGISTER

R/W-0

IPEN

R/W-1

SBOREN⁽¹⁾

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR⁽²⁾

R/W-0

BOR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

SBOREN: BOR Software Enable bit⁽¹⁾

If BOREN<1:0> = 01:

1= BOR is enabled

0= BOR is disabled

If BOREN<1:0> = 00, 10or 11:

Bit is disabled and read as ‘0’.

bit 5

bit 4

Unimplemented: Read as ‘0’

RI: RESETInstruction Flag bit

1= The RESETinstruction was not executed (set by firmware or Power-on Reset)

0= The RESET instruction was executed causing a device Reset (must be set in firmware after a

code-executed Reset occurs)

bit 3

bit 2

bit 1

bit 0

TO: Watchdog Time-out Flag bit

1= Set by power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down Detection Flag bit

1= Set by power-up or by the CLRWDTinstruction

0= Set by execution of the SLEEPinstruction

POR: Power-on Reset Status bit⁽²⁾

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit⁽³⁾

1= A Brown-out Reset has not occurred (set by firmware only)

0= A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this

register and Section 22.6 “Reset State of Registers” for additional information.

3: See Table 22-3.

DS40001365F-page 238

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 22-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

22.2 Master Clear (MCLR)

The MCLR pin provides a method for triggering an

external Reset of the device. A Reset is generated by

holding the pin low. These devices have a noise filter in

the MCLR Reset path which detects and ignores small

pulses.

VDD

PIC^®MCU

The MCLR pin is not driven low by any internal Resets,

including the WDT.

D

R

R1

MCLR

In PIC18(L)F1XK22 devices, the MCLR input can be

disabled with the MCLRE Configuration bit. When

MCLR is disabled, the pin becomes a digital input. See

Section 8.1 “PORTA, TRISA and LATA Registers”

for more information.

C

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

22.3 Power-on Reset (POR)

A

Power-on Reset pulse is generated on-chip

2: R < 40 k is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

3: R1  1 k will limit any current flowing into

MCLR from external capacitor C, in the event

of MCLR/VPP pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

To take advantage of the POR circuitry, tie the MCLR

pin through a resistor (1 k to 10 k) to VDD. This will

eliminate external RC components usually needed to

create a Power-on Reset delay.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters

(voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

POR events are captured by the POR bit of the RCON

register. The state of the bit is set to ‘0’ whenever a

POR occurs; it does not change for any other Reset

event. POR is not reset to ‘1’ by any hardware event.

To capture multiple events, the user must manually set

the bit to ‘1’ by software following any POR.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 239

PIC18(L)F1XK22

Placing the BOR under software control gives the user

the additional flexibility of tailoring the application to its

environment without having to reprogram the device to

change BOR configuration. It also allows the user to

tailor device power consumption in software by

eliminating the incremental current that the BOR

consumes. While the BOR current is typically very small,

it may have some impact in low-power applications.

22.4 Brown-out Reset (BOR)

PIC18(L)F1XK22 devices implement a BOR circuit that

provides the user with a number of configuration and

power-saving options. The BOR is controlled by the

BORV<1:0> and BOREN<1:0> bits of the CONFIG2L

Configuration register. There are a total of four BOR

configurations which are summarized in Table 22-1.

The BOR threshold is set by the BORV<1:0> bits. If

BOR is enabled (any values of BOREN<1:0>, except

‘00’), any drop of VDD below VBOR for greater than

TBOR will reset the device. A Reset may or may not

occur if VDD falls below VBOR for less than TBOR. The

chip will remain in Brown-out Reset until VDD rises

above VBOR.

Note:

Even when BOR is under software

control, the BOR Reset voltage level is still

set by the BORV<1:0> Configuration bits.

It cannot be changed by software.

22.4.2

DETECTING BOR

When BOR is enabled, the BOR bit always resets to ‘0’

on any BOR or POR event. This makes it difficult to

determine if a BOR event has occurred just by reading

the state of BOR alone. A more reliable method is to

simultaneously check the state of both POR and BOR.

This assumes that the POR and BOR bits are reset to

‘1’ by software immediately after any POR event. If

BOR is ‘0’ while POR is ‘1’, it can be reliably assumed

that a BOR event has occurred.

If the Power-up Timer is enabled, it will be invoked after

VDD rises above VBOR; it then will keep the chip in

Reset for an additional time delay, TPWRT. If VDD drops

below VBOR while the Power-up Timer is running, the

chip will go back into a Brown-out Reset and the

Power-up Timer will be initialized. Once VDD rises

above VBOR, the Power-up Timer will execute the

additional time delay.

BOR and the Power-on Timer (PWRT) are

independently configured. Enabling BOR Reset does

not automatically enable the PWRT.

22.4.3

DISABLING BOR IN SLEEP MODE

When BOREN<1:0> = 10, the BOR remains under

hardware control and operates as previously

described. Whenever the device enters Sleep mode,

however, the BOR is automatically disabled. When the

device returns to any other operating mode, BOR is

automatically re-enabled.

22.4.1

SOFTWARE ENABLED BOR

When BOREN<1:0> = 01, the BOR can be enabled or

disabled by the user in software. This is done with the

SBOREN control bit of the RCON register. Setting

SBOREN enables the BOR to function as previously

described. Clearing SBOREN disables the BOR

entirely. The SBOREN bit operates only in this mode;

otherwise it is read as ‘0’.

This mode allows for applications to recover from

brown-out situations, while actively executing code,

when the device requires BOR protection the most. At

the same time, it saves additional power in Sleep mode

by eliminating the small incremental BOR current.

TABLE 22-1: BOR CONFIGURATIONS

BOR Configuration

Status of

SBOREN

(RCON<6>)

BOR Operation

BOREN1

BOREN0

0

1

0

1

0

Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.

Available BOR enabled by software; operation controlled by SBOREN.

Unavailable BOR enabled by hardware in Run and Idle modes, disabled during

Sleep mode.

1

Unavailable BOR enabled by hardware; must be disabled by reprogramming the

Configuration bits.

DS40001365F-page 240

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PIC18(L)F1XK22

The OST time-out is invoked only for XT, LP, HS and

HSPLL modes and only on Power-on Reset, or on exit

from all power-managed modes that stop the external

oscillator.

22.5 Device Reset Timers

PIC18(L)F1XK22 devices incorporate three separate

on-chip timers that help regulate the Power-on Reset

process. Their main function is to ensure that the

device clock is stable before code is executed. These

timers are:

22.5.3

PLL LOCK TIME-OUT

With the PLL enabled in its PLL mode, the time-out

sequence following a Power-on Reset is slightly

different from other oscillator modes. A separate timer

is used to provide a fixed time-out that is sufficient for

the PLL to lock to the main oscillator frequency. This

PLL lock time-out (TPLL) is typically 2 ms and follows

the oscillator start-up time-out.

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• PLL Lock Time-out

22.5.1

POWER-UP TIMER (PWRT)

The Power-up Timer (PWRT) of PIC18(L)F1XK22

devices is an 11-bit counter which uses the

LFINTOSC source as the clock input. This yields an

approximate time interval of 2048 x 32 s = 65.6 ms.

While the PWRT is counting, the device is held in

Reset.

22.5.4

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

1. After the POR pulse has cleared, PWRT time-out

is invoked (if enabled).

The power-up time delay depends on the LFINTOSC

clock and will vary from chip-to-chip due to temperature

and process variation. See Section 26.0 “Electrical

Specifications” for details.

2. Then, the OST is activated.

The total time-out will vary based on oscillator

configuration and the status of the PWRT. Figure 22-3,

Figure 22-4, Figure 22-5, Figure 22-6 and Figure 22-7

all depict time-out sequences on power-up, with the

Power-up Timer enabled and the device operating in

HS Oscillator mode. Figures 22-3 through 22-6 also

apply to devices operating in XT or LP modes. For

devices in RC mode and with the PWRT disabled, on

the other hand, there will be no time-out at all.

The PWRT is enabled by clearing the PWRTEN

Configuration bit.

22.5.2

OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, all time-outs will expire, after

which, bringing MCLR high will allow program

execution to begin immediately (Figure 22-5). This is

useful for testing purposes or to synchronize more than

one PIC18(L)F1XK22 device operating in parallel.

TABLE 22-2: TIME-OUT IN VARIOUS SITUATIONS

Oscillator

Power-up⁽²⁾and Brown-out

Exit from

Configuration

Power-Managed Mode

PWRTEN = 0

PWRTEN = 1

HSPLL

66 ms⁽¹⁾+ 1024 TOSC + 2 ms⁽²⁾

66 ms⁽¹⁾+ 1024 TOSC

66 ms⁽¹⁾

1024 TOSC + 2 ms⁽²⁾

HS, XT, LP

EC, ECIO

RC, RCIO

INTIO1, INTIO2

1024 TOSC

—

66 ms⁽¹⁾

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the PLL to lock.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 241

PIC18(L)F1XK22

FIGURE 22-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 22-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 22-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

DS40001365F-page 242

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 22-6:

SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

5V

0V

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 22-7:

TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

TPLL

PLL TIME-OUT

INTERNAL RESET

Note:

TOST = 1024 clock cycles.

TPLL  2 ms max. First three stages of the PWRT timer.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 243

PIC18(L)F1XK22

22.6 Reset State of Registers

Some registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. All other registers are forced to a “Reset state”

depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal

operation. Status bits from the RCON register, RI, TO,

PD, POR and BOR, are set or cleared differently in

different Reset situations, as indicated in Table 22-3.

These bits are used by software to determine the

nature of the Reset.

Table 22-4 describes the Reset states for all of the

Special Function Registers. These are categorized by

Power-on and Brown-out Resets, Master Clear and

WDT Resets and WDT wake-ups.

TABLE 22-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

RCON Register

STKPTR Register

Program

Counter

Condition

SBOREN

RI

TO

PD POR BOR STKOVF STKUNF

Power-on Reset

0000h

1

0

1

u

1

u

1

u

1

u

0

u

0

u

0

u

0

u

0

u

RESETInstruction

u⁽²⁾

Brown-out Reset

MCLR during Power-Managed

Run Modes

MCLR during Power-Managed

Idle Modes and Sleep Mode

0000h

u⁽²⁾

u

1

0

u

0

u

WDT Time-out during Full Power

or Power-Managed Run Mode

MCLR during Full Power

Execution

Stack Full Reset (STVREN = 1)

0000h

u⁽²⁾

u

1

u

1

Stack Underflow Reset

(STVREN = 1)

Stack Underflow Error (not an

actual Reset, STVREN = 0)

0000h

u⁽²⁾

u

0

u

0

u

1

u

WDT Time-out during

Power-Managed Idle or Sleep

Modes

PC + 2

Interrupt Exit from

PC + 2⁽¹⁾

u⁽²⁾

u

0

u

Power-Managed Modes

Legend: u= unchanged

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (008h or 0018h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN<1:0> Configuration bits = 01and SBOREN = 1). Otherwise, the Reset state is ‘0’.

DS40001365F-page 244

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PIC18(L)F1XK22

TABLE 22-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR Resets,

Power-on Reset,

Brown-out Reset

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Register

Address

(3)

---0 0000

0000 0000

00-0 0000

---0 0000

0000 0000

---0 0000

0000 0000

xxxx xxxx

0000 000x

1111 -1-1

11-0 0-00

N/A

---0 0000

0000 0000

uu-0 0000

---0 0000

0000 0000

---0 0000

0000 0000

uuuu uuuu

0000 000u

1111 -1-1

11-0 0-00

N/A

---0 uuuu

TOSU

FFFh

FFEh

FFDh

FFCh

FFBh

FFAh

FF9h

FF8h

FF7h

FF6h

FF5h

FF4h

FF3h

FF2h

FF1h

FF0h

FEFh

FEEh

FEDh

FECh

FEBh

FEAh

FE9h

FE8h

FE7h

FE6h

FE5h

FE4h

FE3h

(3)

TOSH

uuuu uuuu

(3)

TOSL

uuuu uuuu

(3)

STKPTR

PCLATU

PCLATH

PCL

uu-u uuuu

---u uuuu

uuuu uuuu

(2)

PC + 2

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

---u uuuu

uuuu uuuu

(1)

INTCON

INTCON2

INTCON3

INDF0

uuuu uuuu

(1)

uuuu -u-u

(1)

uu-u u-uu

N/A

POSTINC0

POSTDEC0

PREINC0

PLUSW0

FSR0H

N/A

---- 0000

xxxx xxxx

N/A

---- 0000

uuuu uuuu

N/A

---- uuuu

uuuu uuuu

N/A

FSR0L

WREG

INDF1

POSTINC1

POSTDEC1

PREINC1

PLUSW1

N/A

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 22-3 for Reset value for specific condition.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 245

PIC18(L)F1XK22

TABLE 22-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

Power-on Reset,

Brown-out Reset

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Register

Address

FSR1H

---- 0000

xxxx xxxx

---- 0000

N/A

---- 0000

uuuu uuuu

---- 0000

N/A

---- uuuu

uuuu uuuu

---- uuuu

N/A

FE2h

FE1h

FE0h

FDFh

FDEh

FDDh

FDCh

FDBh

FDAh

FD9h

FD8h

FD7h

FD6h

FD5h

FD3h

FD2h

FD1h

FD0h

FCFh

FCEh

FCDh

FCCh

FCBh

FCAh

FC9h

FC8h

FC7h

FC6h

FC5h

FSR1L

BSR

INDF2

POSTINC2

POSTDEC2

PREINC2

PLUSW2

FSR2H

N/A

---- 0000

xxxx xxxx

---x xxxx

0000 0000

xxxx xxxx

1111 1111

0011 qq00

---- -10x

---- ---0

0q-1 11q0

xxxx xxxx

0000 0000

1111 1111

-000 0000

xxxx xxxx

0000 0000

---- 0000

uuuu uuuu

---u uuuu

0000 0000

uuuu uuuu

1111 1111

0011 qq00

---- -10x

---- ---0

0q-q qquu

uuuu uuuu

u0uu uuuu

0000 0000

1111 1111

-000 0000

uuuu uuuu

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

---- -uuu

---- ---u

uq-u qquu

uuuu uuuu

1111 1111

-uuu uuuu

uuuu uuuu

FSR2L

STATUS

TMR0H

TMR0L

T0CON

OSCCON

OSCCON2

WDTCON

(4)

RCON

TMR1H

TMR1L

T1CON

TMR2

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 22-3 for Reset value for specific condition.

DS40001365F-page 246

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PIC18(L)F1XK22

TABLE 22-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Address

ADRESH

xxxx xxxx

--00 0000

---- 0000

0-00 0000

xxxx xxxx

0000 0000

---0 0000

000- 00-0

0001 ----

---0 0001

0100 0-00

0000 0000

xxxx xxxx

0-00 0000

0000 0000

0000 0010

0000 000x

0000 0000

xx-0 x000

uuuu uuuu

--00 0000

---- 0000

0-00 0000

uuuu uuuu

0000 0000

---0 0000

000- 00-0

0001 ----

---0 0001

0100 0-00

0000 0000

uuuu uuuu

u-uu uuuu

0000 0000

0000 0010

0000 000x

0000 0000

uu-0 u000

uuuu uuuu

--uu uuuu

---- uuuu

u-uu uuuu

uuuu uuuu

---u uuuu

uuu- uu-u

uuuu ----

---u uuuu

uuuu u-uu

uuuu uuuu

u-uu uuuu

uuuu uuuu

0000 0000

uu-0 u000

FC4h

FC3h

FC2h

FC1h

FC0h

FBFh

FBEh

FBDh

FBCh

FBBh

FBAh

FB9h

FB8h

FB7h

FB6h

FB3h

FB2h

FB1h

FB0h

FAFh

FAEh

FADh

FACh

FABh

FAAh

FA8h

FA7h

FA6h

ADRESL

ADCON0

ADCON1

ADCON2

CCPR1H

CCPR1L

CCP1CON

VREFCON2

VREFCON1

VREFCON0

PSTRCON

BAUDCON

PWM1CON

ECCP1AS

TMR3H

TMR3L

T3CON

SPBRGH

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADR

EEDATA

EECON2

EECON1

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 22-3 for Reset value for specific condition.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 247

PIC18(L)F1XK22

TABLE 22-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

Power-on Reset,

Brown-out Reset

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Register

Address

IPR2

1111 1-1-

0000 0-0-

-111 1111

-000 0000

0000 0000

1111 1111

1111 ----

--11 1111

xxxx xxxx

xxxx ----

--xx xxxx

xxxx xxxx

xxxx ----

--xx xxxx

---- 1111

1111 1111

0000 ----

--00 0000

1111 ----

--11 1111

---- -111

1111 1111

0000 0000

1111 1-1-

0000 0-0-

-111 1111

-000 0000

0000 0000

1111 1111

1111 ----

--11 1111

uuuu uuuu

uuuu ----

--uu uuuu

uuuu uuuu

uuuu ----

--xx xxxx

---- 1111

1111 1111

0000 ----

--00 0000

1111 ----

--11 1111

---- -111

1111 1111

0000 0000

uuuu u-u-

FA2h

FA1h

FA0h

F9Fh

F9Eh

F9Dh

F9Bh

F95h

F94h

F93h

F8Bh

F8Ah

F89h

F82h

F81h

F80h

F7Fh

F7Eh

F7Ah

F79h

F78h

F77h

F76h

F6Fh

F6Dh

F6Ch

F6Bh

F69h

F68h

(1)

PIR2

PIE2

IPR1

uuuu u-u-

-uuu uuuu

(1)

-uuu uuuu

PIR1

-uuu uuuu

uuuu uuuu

uuuu ----

--uu uuuu

uuuu uuuu

uuuu ----

--uu uuuu

uuuu uuuu

uuuu ----

--uu uuuu

---- uuuu

uuuu uuuu

uuuu ----

--uu uuuu

uuuu ----

--uu uuuu

---- -uuu

uuuu uuuu

PIE1

OSCTUNE

TRISC

TRISB

TRISA

LATC

LATB

LATA

PORTC

PORTB

PORTA

ANSELH

ANSEL

IOCB

IOCA

WPUB

WPUA

SLRCON

SSPMSK

CM1CON0

CM2CON1

CM2CON0

SRCON1

SRCON0

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 22-3 for Reset value for specific condition.

DS40001365F-page 248

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PIC18(L)F1XK22

23.0 SPECIAL FEATURES OF

THE CPU

PIC18(L)F1XK22 devices include several features

intended to maximize reliability and minimize cost through

elimination of external components. These are:

• Oscillator Selection

• Resets:

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Code Protection

• ID Locations

• In-Circuit Serial Programming™

The oscillator can be configured for the application

depending on frequency, power, accuracy and cost. All

of the options are discussed in detail in Section 2.0

“Oscillator Module”.

A complete discussion of device Resets and interrupts

is available in previous sections of this data sheet.

In addition to their Power-up and Oscillator Start-up

Timers provided for Resets, PIC18(L)F1XK22 devices

have a Watchdog Timer, which is either permanently

enabled via the Configuration bits or software controlled

(if configured as disabled).

The inclusion of an internal RC oscillator also provides

the additional benefits of a Fail-Safe Clock Monitor

(FSCM) and Two-Speed Start-up. FSCM provides for

background monitoring of the peripheral clock and

automatic switchover in the event of its failure. Two-

Speed Start-up enables code to be executed almost

immediately on start-up, while the primary clock source

completes its start-up delays.

All of these features are enabled and configured by

setting the appropriate Configuration register bits.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 249

PIC18(L)F1XK22

23.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’) or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped starting

at program memory location 300000h.

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h-3FFFFFh), which

can only be accessed using table reads and table writes.

Programming the Configuration registers is done in a

manner similar to programming the Flash memory. The

WR bit in the EECON1 register starts a self-timed write

to the Configuration register. In normal operation mode,

a TBLWT instruction with the TBLPTR pointing to the

Configuration register sets up the address and the data

for the Configuration register write. Setting the WR bit

starts a long write to the Configuration register. The

Configuration registers are written a byte at a time. To

write or erase a configuration cell, a TBLWTinstruction

can write a ‘1’ or a ‘0’ into the cell. For additional details

on Flash programming, refer to Section 4.5 “Writing

to Flash Program Memory”.

TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs

Default/

Unprogrammed

Value

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300001h CONFIG1H IESO

FCMEN PCLKEN PLL_EN

FOSC3

BORV0

FOSC2

FOSC1

FOSC0

0010 0111

---1 1111

1--- 1---

300002h CONFIG2L

300003h CONFIG2H

—

BORV1

BOREN1 BOREN0 PWRTEN

WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN

300005h CONFIG3H MCLRE

—

HFOFST

—

LVP

—

STVREN

CP0

BKBUG

—

300006h CONFIG4L

300008h CONFIG5L

300009h CONFIG5H

30000Ah CONFIG6L

ENHCPU

—

BBSIZ

—

-0-- 01-1

---- --11

11-- ----

---- --11

111- ----

---- --11

-1-- ----

CP1

—

CPD

—

CPB

—

WRT1

—

WRT0

—

30000Bh CONFIG6H WRTD

WRTB

—

WRTC

—

30000Ch CONFIG7L

30000Dh CONFIG7H

—

EBTR1

—

EBTR0

—

EBTRB

DEV1

DEV9

—

(1)

3FFFFEh DEVID1

DEV2

DEV10

DEV0

DEV8

REV4

DEV7

REV3

DEV6

REV2

DEV5

REV1

DEV4

REV0

DEV3

qqqq qqqq

(1)

3FFFFFh DEVID2

0000 1100

Legend:

x= unknown, u= unchanged, – = unimplemented, q= value depends on condition.

Shaded cells are unimplemented, read as ‘0’

Note 1: See Register 23-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.

DS40001365F-page 250

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PIC18(L)F1XK22

REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH

R/P-0

IESO

R/P-0

R/P-1

R/P-0

R/P-1

FCMEN

PCLKEN

PLL_EN

FOSC3

FOSC2

FOSC1

FOSC0

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

-n = Value when device is unprogrammed

bit 7

bit 6

bit 5

bit 4

bit 3-0

IESO: Internal/External Oscillator Switchover bit

1= Oscillator Switchover mode enabled

0= Oscillator Switchover mode disabled

FCMEN: Fail-Safe Clock Monitor Enable bit

1= Fail-Safe Clock Monitor enabled

0= Fail-Safe Clock Monitor disabled

PCLKEN: Primary Clock Enable bit

1= Primary Clock enabled

0= Primary Clock is under software control

PLL_EN: 4 X PLL Enable bit

1= Oscillator multiplied by 4

0= PLL is under software control

FOSC<3:0>: Oscillator Selection bits

1111= External RC oscillator, CLKOUT function on OSC2

1110= External RC oscillator, CLKOUT function on OSC2

1101= EC (low)

1100= EC, CLKOUT function on OSC2 (low)

1011= EC (medium)

1010= EC, CLKOUT function on OSC2 (medium)

1001= Internal RC oscillator, CLKOUT function on OSC2

1000= Internal RC oscillator

0111= External RC oscillator

0110= External RC oscillator, CLKOUT function on OSC2

0101= EC (high)

0100= EC, CLKOUT function on OSC2 (high)

0011= External RC oscillator, CLKOUT function on OSC2

0010= HS oscillator

0001= XT oscillator

0000= LP oscillator

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DS40001365F-page 251

PIC18(L)F1XK22

REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW

U-0

—

U-0

—

U-0

—

R/P-1

BORV1⁽¹⁾

R/P-1

BORV0⁽¹⁾

R/P-1

BOREN1⁽²⁾BOREN0⁽²⁾PWRTEN⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

-n = Value when device is unprogrammed

bit 7-5

bit 4-3

Unimplemented: Read as ‘0’

BORV<1:0>: Brown-out Reset Voltage bits⁽¹⁾

11= VBOR set to 1.9V nominal

10= VBOR set to 2.2V nominal

01= VBOR set to 2.5V nominal

00= VBOR set to 2.85V nominal

bit 2-1

BOREN<1:0>: Brown-out Reset Enable bits⁽²⁾

11= Brown-out Reset enabled in hardware only (SBOREN is disabled)

10= Brown-out Reset enabled in hardware only and disabled in Sleep mode

(SBOREN is disabled)

01= Brown-out Reset enabled and controlled by software (SBOREN is enabled)

00= Brown-out Reset disabled in hardware and software

bit 0

PWRTEN: Power-up Timer Enable bit⁽²⁾

1= PWRT disabled

0= PWRT enabled

Note 1: See Table 26-1 for specifications.

2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently

controlled.

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PIC18(L)F1XK22

REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH

U-0

—

U-0

—

U-0

—

R/P-1

WDTPS3

WDTPS2

WDTPS1

WDTPS0

WDTEN

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

-n = Value when device is unprogrammed

bit 7-5

bit 4-1

Unimplemented: Read as ‘0’

WDTPS<3:0>: Watchdog Timer Postscale Select bits

1111= 1:32,768

1110= 1:16,384

1101= 1:8,192

1100= 1:4,096

1011= 1:2,048

1010= 1:1,024

1001= 1:512

1000= 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

bit 0

WDTEN: Watchdog Timer Enable bit

1= WDT is always enabled. SWDTEN bit has no effect

0= WDT is controlled by SWDTEN bit of the WDTCON register

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DS40001365F-page 253

PIC18(L)F1XK22

REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH

R/P-1

U-0

—

U-0

—

U-0

—

R/P-1

U-0

—

U-0

—

U-0

—

MCLRE

HFOFST

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

-n = Value when device is unprogrammed

bit 7

MCLRE: MCLR Pin Enable bit

1= MCLR pin enabled; RA3 input pin disabled

0= RA3 input pin enabled; MCLR disabled

bit 6-4

bit 3

Unimplemented: Read as ‘0’

HFOFST: HFINTOSC Fast Start-up bit

1= HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize.

0= The system clock is held off until the HFINTOSC is stable.

bit 2-0

Unimplemented: Read as ‘0’

REGISTER 23-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW

R/W-1⁽¹⁾

R/W-0

U-0

—

U-0

—

R/P-0

R/P-1

LVP

U-0

—

R/P-1

BBSIZ

BKBUG

ENHCPU

STVREN

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

-n = Value when device is unprogrammed

bit 7

bit 6

BKBUG: Background Debugger Enable bit⁽¹⁾

1= Background Debugger disabled

0= Background Debugger functions enabled

ENHCPU: Enhanced CPU Enable bit

1= Enhanced CPU enabled

0= Enhanced CPU disabled

bit 5-4

bit 3

Unimplemented: Read as ‘0’

BBSIZ: Boot BLock Size Select bit

1= 2 kW boot block size for PIC18(L)F14K22 (1 kW boot block size for

PIC18(L)F13K22)

0= 1 kW boot block size for PIC18(L)F14K22 (512 W boot block size for

PIC18(L)F13K22)

bit 2

LVP: Single-Supply ICSP™ Enable bit

1= Single-Supply ICSP enabled

0= Single-Supply ICSP disabled

bit 1

bit 0

Unimplemented: Read as ‘0’

STVREN: Stack Full/Underflow Reset Enable bit

1= Stack full/underflow will cause Reset

0= Stack full/underflow will not cause Reset

Note 1: BKBUG is only used for ICD device. Otherwise, this bit is unimplemented and reads as ‘1’.

DS40001365F-page 254

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PIC18(L)F1XK22

REGISTER 23-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

CP1

R/C-1

CP0

bit 7

bit 0

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

C = Clearable only bit

-n = Value when device is unprogrammed

bit 7-2

bit 1

Unimplemented: Read as ‘0’

CP1: Code Protection bit

1= Block 1 not code-protected

0= Block 1 code-protected

bit 0

CP0: Code Protection bit

1= Block 0 not code-protected

0= Block 0 code-protected

REGISTER 23-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH

R/C-1

CPD

R/C-1

CPB

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

C = Clearable only bit

-n = Value when device is unprogrammed

bit 7

CPD: Data EEPROM Code Protection bit

1= Data EEPROM not code-protected

0= Data EEPROM code-protected

bit 6

CPB: Boot Block Code Protection bit

1= Boot block not code-protected

0= Boot block code-protected

bit 5-0

Unimplemented: Read as ‘0’

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DS40001365F-page 255

PIC18(L)F1XK22

REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

WRT1

R/C-1

WRT0

bit 7

bit 0

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

C = Clearable only bit

-n = Value when device is unprogrammed

bit 7-2

bit 1

Unimplemented: Read as ‘0’

WRT1: Write Protection bit

1= Block 1 not write-protected

0= Block 1 write-protected

bit 0

WRT0: Write Protection bit

1= Block 0 not write-protected

0= Block 0 write-protected

REGISTER 23-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH

R/C-1

R-1

WRTC⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

WRTD

WRTB

bit 7

bit 0

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

C = Clearable only bit

-n = Value when device is unprogrammed

bit 7

WRTD: Data EEPROM Write Protection bit

1= Data EEPROM not write-protected

0= Data EEPROM write-protected

bit 6

WRTB: Boot Block Write Protection bit

1= Boot block not write-protected

0= Boot block write-protected

bit 5

WRTC: Configuration Register Write Protection bit⁽¹⁾

1= Configuration registers not write-protected

0= Configuration registers write-protected

bit 4-0

Unimplemented: Read as ‘0’

Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.

DS40001365F-page 256

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PIC18(L)F1XK22

REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

EBTR1

EBTR0

bit 7

bit 0

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

C = Clearable only bit

-n = Value when device is unprogrammed

bit 7-2

bit 1

Unimplemented: Read as ‘0’

EBTR1: Table Read Protection bit

1= Block 1 not protected from table reads executed in other blocks

0= Block 1 protected from table reads executed in other blocks

bit 0

EBTR0: Table Read Protection bit

1= Block 0 not protected from table reads executed in other blocks

0= Block 0 protected from table reads executed in other blocks

REGISTER 23-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH

U-0

—

R/C-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

EBTRB

bit 7

bit 0

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

C = Clearable only bit

-n = Value when device is unprogrammed

bit 7

bit 6

Unimplemented: Read as ‘0’

EBTRB: Boot Block Table Read Protection bit

1= Boot block not protected from table reads executed in other blocks

0= Boot block protected from table reads executed in other blocks

bit 5-0

Unimplemented: Read as ‘0’

 2009-2016 Microchip Technology Inc.

DS40001365F-page 257

PIC18(L)F1XK22

REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18(L)F1XK22

R

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

bit 7

bit 0

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

C = Clearable only bit

-n = Value when device is unprogrammed

bit 7-5

DEV<2:0>: Device ID bits

010= PIC18(L)F13K22

011= PIC18(L)F14K22

bit 4-0

REV<4:0>: Revision ID bits

These bits are used to indicate the device revision.

REGISTER 23-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18(L)F1XK22

R

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

bit 7

bit 0

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

C = Clearable only bit

-n = Value when device is unprogrammed

bit 7-0 DEV<10:3>: Device ID bits

These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the

part number.

0010 0000= PIC18F13K22/PIC18F14K22 devices⁽¹⁾

Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified

by using the entire DEV<10:0> bit sequence.

DS40001365F-page 258

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PIC18(L)F1XK22

23.2 Watchdog Timer (WDT)

For PIC18(L)F1XK22 devices, the WDT is driven by the

LFINTOSC source. When the WDT is enabled, the

clock source is also enabled. The nominal WDT period

is 4 ms and has the same stability as the LFINTOSC

oscillator.

The 4-millisecond period of the WDT is multiplied by a

16-bit postscaler. Any output of the WDT postscaler is

selected by a multiplexer, controlled by bits in

Configuration register 2H. Available periods range from

4 ms to 131.072 seconds (2.18 minutes). The WDT and

postscaler are cleared when any of the following events

occur: a SLEEPor CLRWDTinstruction is executed, the

IRCF bits of the OSCCON register are changed or a

clock failure has occurred.

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: Changing the setting of the IRCF bits of

the OSCCON register clears the WDT

and postscaler counts.

FIGURE 23-1:

WDT BLOCK DIAGRAM

Enable WDT

SWDTEN

WDTEN

WDT Counter

Wake-up

from Power

Managed Modes

128

LFINTOSC Source

Change on IRCF bits

CLRWDT

WDT

Reset

Programmable Postscaler

1:1 to 1:32,768

All Device Resets

4

WDTPS<3:0>

Sleep

 2009-2016 Microchip Technology Inc.

DS40001365F-page 259

PIC18(L)F1XK22

23.2.1

CONTROL REGISTER

Register 23-14 shows the WDTCON register. This is a

readable and writable register which contains a control

bit that allows software to override the WDT enable

Configuration bit, but only if the Configuration bit has

disabled the WDT.

REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SWDTEN⁽¹⁾

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

bit 0

Unimplemented: Read as ‘0’

SWDTEN: Software Enable or Disable the Watchdog Timer bit⁽¹⁾

1= WDT is turned on

0= WDT is turned off (Reset value)

Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.

TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CONFIG2H

—

WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN

253

246

RCON

IPEN

—

SBOREN

—

RI

—

TO

—

PD

—

POR

—

BOR

SWDTEN

WDTCON

246

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

Figure 23-2 shows the program memory organization

for 8, 16 and 32-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 23-3.

23.3 Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other PIC

microcontroller devices.

The user program memory is divided into five blocks.

One of these is a boot block of 0.5K or 2K bytes,

depending on the device. The remainder of the

memory is divided into individual blocks on binary

boundaries.

Each of the five blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

DS40001365F-page 260

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PIC18(L)F1XK22

FIGURE 23-2:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18(L)F1XK22

Device

Address (from/to)

14K22

13K22

BBSIZ = 1

BBSIZ = 0

BBSIZ = 1

Boot Block, 2 KB

BBSIZ = 0

0000h

03FFh

Boot Block, 4 KB

Boot Block, 2 KB

Boot Block, 1 KB CPB,

WRTB, EBTRB

CPB, WRTB, EBTRB CPB, WRTB, EBTRB CPB, WRTB, EBTRB

0400h

07FFh

Block 0

1.512 KB

CP0, WRT0, EBTR0

0800h

0BFFh

Block 0

6 KB

Block 0

2 KB

CP0, WRT0, EBTR0 CP0, WRT0, EBTR0

0C00h

0FFFh

1000h

1FFFh

Block 0

4 KB

Block 1

4 KB

Block 1

4 KB

CP0, WRT0, EBTR0

CP1, WRT1, EBTR1

2000h

3FFFh

Block 1

8 KB

Block 1

8 KB

Reads all ‘0’s

CP1, WRT1, EBTR1 CP1, WRT1, EBTR1

4000h

4FFEh

Reads all ‘0’s Reads all ‘0’s

5000h

5FFEh

6000h

6FFEh

7000h

7FFEh

8000h

8FFEh

9000h

9FFEh

A000h

AFFEh

B000h

BFFEh

C000h

CFFEh

D000h

DFFEh

E000h

EFFEh

F000h

FFFEh

H000h

HFFEh

Note:

Refer to the test section for requirements on test memory mapping.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 261

PIC18(L)F1XK22

TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h CONFIG5L

300009h CONFIG5H

30000Ah CONFIG6L

—

CPD

—

CPB

—

CP1

—

CP0

—

WRT1

WRT0

—

30000Bh CONFIG6H WRTD

WRTB

—

WRTC⁽¹⁾

—

30000Ch CONFIG7L

30000Dh CONFIG7H

—

EBTR1

EBTR0

—

EBTRB

—

Legend: Shaded cells are unimplemented.

Note 1: Unimplemented in PIC18F13K22 and PIC18F14K22 devices; maintain this bit set.

instruction that executes from a location outside of that

block is not allowed to read and will result in reading ‘0’s.

Figures 23-3 through 23-5 illustrate table write and table

read protection.

23.3.1

PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

Note:

Code protection bits may only be written

to a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code

protection bits are only set to ‘1’ by a full

chip erase or block erase function. The full

chip erase and block erase functions can

only be initiated via ICSP or an external

programmer.

In normal execution mode, the CPn bits have no direct

effect. CPn bits inhibit external reads and writes. A block

of user memory may be protected from table writes if the

WRTn Configuration bit is ‘0’. The EBTRn bits control

table reads. For a block of user memory with the EBTRn

bit cleared to ‘0’, a table READinstruction that executes

from within that block is allowed to read. A table read

FIGURE 23-3:

TABLE WRITE (WRTn) DISALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

0007FFh

WRTB, EBTRB = 11

000800h

TBLPTR = 0008FFh

PC = 001FFEh

WRT0, EBTR0 = 01

TBLWT*

001FFFh

002000h

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

003FFFh

004000h

PC = 005FFEh

005FFFh

006000h

007FFFh

Results: All table writes disabled to Blockn whenever WRTn = 0.

DS40001365F-page 262

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PIC18(L)F1XK22

FIGURE 23-4:

EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB, EBTRB = 11

0007FFh

000800h

TBLPTR = 0008FFh

PC = 003FFEh

WRT0, EBTR0 = 10

001FFFh

002000h

TBLRD*

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

003FFFh

004000h

005FFFh

006000h

WRT3, EBTR3 = 11

007FFFh

Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.

TABLAT register returns a value of ‘0’.

FIGURE 23-5:

EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

0007FFh

000800h

TBLPTR = 0008FFh

PC = 001FFEh

TBLRD*

001FFFh

002000h

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

003FFFh

004000h

005FFFh

006000h

007FFFh

Results: Table reads permitted within Blockn, even when EBTRBn = 0.

TABLAT register returns the value of the data at the location TBLPTR.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 263

PIC18(L)F1XK22

To use the In-Circuit Debugger function of the

microcontroller, the design must implement In-Circuit

Serial Programming connections to the following pins:

23.3.2

DATA EEPROM

CODE PROTECTION

The entire data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of data EEPROM.

WRTD inhibits internal and external writes to data

EEPROM. The CPU can always read data EEPROM

under normal operation, regardless of the protection bit

settings.

• MCLR/VPP/RA3

• VDD

• VSS

• RA0

• RA1

This will interface to the In-Circuit Debugger module

available from Microchip or one of the third party

development tool companies.

23.3.3

CONFIGURATION REGISTER

PROTECTION

The Configuration registers can be write-protected.

The WRTC bit controls protection of the Configuration

registers. In normal execution mode, the WRTC bit is

readable only. WRTC can only be written via ICSP or

an external programmer.

23.7 Single-Supply ICSP Programming

The LVP Configuration bit enables Single-Supply ICSP

Programming (formerly known as Low-Voltage ICSP

Programming or LVP). When Single-Supply

Programming is enabled, the microcontroller can be

programmed without requiring high voltage being

applied to the MCLR/VPP/RA3 pin, but the RC3/PGM

pin is then dedicated to controlling Program mode entry

and is not available as a general purpose I/O pin.

23.4 ID Locations

Eight memory locations (200000h-200007h) are

designated as ID locations, where the user can store

checksum or other code identification numbers. These

locations are both readable and writable during normal

execution through the TBLRD and TBLWT instructions

or during program/verify. The ID locations can be read

when the device is code-protected.

While programming, using Single-Supply Programming

mode, VDD is applied to the MCLR/VPP/RA3 pin as in

normal execution mode. To enter Programming mode,

VDD is applied to the PGM pin.

Note 1: High-voltage programming is always

available, regardless of the state of the

LVP bit or the PGM pin, by applying VIHH

to the MCLR pin.

23.5

In-Circuit Serial Programming

PIC18(L)F1XK22 devices can be serially programmed

while in the end application circuit. This is simply done

with two lines for clock and data and three other lines

for power, ground and the programming voltage. This

allows customers to manufacture boards with

unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

2: By default, Single-Supply ICSP is

enabled in unprogrammed devices (as

supplied from Microchip) and erased

devices.

3: When Single-Supply Programming is

enabled, the RC3 pin can no longer be

used as a general purpose I/O pin.

4: When LVP is enabled, externally pull the

PGM pin to VSS to allow normal program

execution.

23.6 In-Circuit Debugger

When the DEBUG Configuration bit is programmed to

a ‘0’, the In-Circuit Debugger functionality is enabled.

This function allows simple debugging functions when

used with MPLAB^®IDE. When the microcontroller has

this feature enabled, some resources are not available

for general use. Table 23-4 shows which resources are

required by the background debugger.

If Single-Supply ICSP Programming mode will not be

used, the LVP bit can be cleared. RC3/PGM then

becomes available as the digital I/O pin, RC3. The LVP

bit may be set or cleared only when using standard

high-voltage programming (VIHH applied to the MCLR/

VPP/RA3 pin). Once LVP has been disabled, only the

standard high-voltage programming is available and

must be used to program the device.

TABLE 23-4: DEBUGGER RESOURCES

I/O pins:

RA0, RA1

2 levels

Memory that is not code-protected can be erased using

either a block erase, or erased row by row, then written

at any specified VDD. If code-protected memory is to be

erased, a block erase is required.

Stack:

Program Memory:

Data Memory:

512 bytes

10 bytes

DS40001365F-page 264

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PIC18(L)F1XK22

The literal instructions may use some of the following

operands:

24.0 INSTRUCTION SET SUMMARY

PIC18(L)F1XK22 devices incorporate the standard set

of 75 PIC18 core instructions, as well as an extended set

of eight new instructions, for the optimization of code that

is recursive or that utilizes a software stack. The

extended set is discussed later in this section.

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand required

(specified by ‘—’)

24.1 Standard Instruction Set

The control instructions may use some of the following

operands:

The standard PIC18 instruction set adds many

enhancements to the previous PIC^®MCU instruction

sets, while maintaining an easy migration from these

PIC MCU instruction sets. Most instructions are a

single program memory word (16 bits), but there are

four instructions that require two program memory

locations.

• A program memory address (specified by ‘n’)

• The mode of the CALLor RETURNinstructions

(specified by ‘s’)

• The mode of the table read and table write

instructions (specified by ‘m’)

Each single-word instruction is a 16-bit word divided

into an opcode, which specifies the instruction type and

one or more operands, which further specify the

operation of the instruction.

• No operand required

(specified by ‘—’)

All instructions are a single word, except for four

double-word instructions. These instructions were

made double-word to contain the required information

in 32 bits. In the second word, the 4 MSbs are ‘1’s. If

this second word is executed as an instruction (by

itself), it will execute as a NOP.

The instruction set is highly orthogonal and is grouped

into four basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

All single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the

instruction. In these cases, the execution takes two

instruction cycles, with the additional instruction

cycle(s) executed as a NOP.

• Control operations

The PIC18 instruction set summary in Table 24-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 24-1 shows the opcode field

descriptions.

The double-word instructions execute in two instruction

cycles.

Most byte-oriented instructions have three operands:

1. The file register (specified by ‘f’)

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1s. If a conditional test is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2s.

Two-word branch instructions (if true) would take 3s.

2. The destination of the result (specified by ‘d’)

3. The accessed memory (specified by ‘a’)

The file register designator ‘f’ specifies which file

register is to be used by the instruction. The destination

designator ‘d’ specifies where the result of the

operation is to be placed. If ‘d’ is zero, the result is

placed in the WREG register. If ‘d’ is one, the result is

placed in the file register specified in the instruction.

Figure 24-1 shows the general formats that the

instructions can have. All examples use the convention

‘nnh’ to represent a hexadecimal number.

The Instruction Set Summary, shown in Table 24-2,

lists the standard instructions recognized by the

Microchip Assembler (MPASM^TM).

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The bit in the file register (specified by ‘b’)

3. The accessed memory (specified by ‘a’)

Section 24.1.1 “Standard Instruction Set” provides

a description of each instruction.

The bit field designator ‘b’ selects the number of the bit

affected by the operation, while the file register

designator ‘f’ represents the number of the file in which

the bit is located.

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PIC18(L)F1XK22

TABLE 24-1: OPCODE FIELD DESCRIPTIONS

Field

Description

a

RAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb

Bit address within an 8-bit file register (0 to 7).

BSR

Bank Select Register. Used to select the current RAM bank.

ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.

C, DC, Z, OV, N

d

Destination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest

f

Destination: either the WREG register or the specified register file location.

8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).

12-bit Register file address (000h to FFFh). This is the source address.

12-bit Register file address (000h to FFFh). This is the destination address.

Global Interrupt Enable bit.

f

s

d

GIE

k

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

Label name.

label

mm

The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

*

No change to register (such as TBLPTR with table reads and writes)

Post-Increment register (such as TBLPTR with table reads and writes)

Post-Decrement register (such as TBLPTR with table reads and writes)

Pre-Increment register (such as TBLPTR with table reads and writes)

*+

*-

+*

n

The relative address (2’s complement number) for relative branch instructions or the direct address for

CALL/BRANCHand RETURNinstructions.

PC

Program Counter.

PCL

Program Counter Low Byte.

Program Counter High Byte.

Program Counter High Byte Latch.

Program Counter Upper Byte Latch.

Power-down bit.

PCH

PCLATH

PCLATU

PD

PRODH

PRODL

s

Product of Multiply High Byte.

Product of Multiply Low Byte.

Fast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR

TABLAT

TO

21-bit Table Pointer (points to a Program Memory location).

8-bit Table Latch.

Time-out bit.

TOS

u

Top-of-Stack.

Unused or unchanged.

Watchdog Timer.

WDT

WREG

x

Working register (accumulator).

Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for

compatibility with all Microchip software tools.

z

{

7-bit offset value for indirect addressing of register files (source).

7-bit offset value for indirect addressing of register files (destination).

Optional argument.

s

d

}

[text]

(text)

[expr]<n>



Indicates an indexed address.

The contents of text.

Specifies bit nof the register indicated by the pointer expr.

Assigned to.

< >

Register bit field.



In the set of.

italics

User defined term (font is Courier).

DS40001365F-page 266

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PIC18(L)F1XK22

FIGURE 24-1:

GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

Example Instruction

15

10

OPCODE

9

8

7

0

ADDWF MYREG, W, B

d

a

f (FILE #)

d = 0for result destination to be WREG register

d = 1for result destination to be file register (f)

a = 0to force Access Bank

a = 1for BSR to select bank

f = 8-bit file register address

Byte to Byte move operations (2-word)

15

12 11

0

OPCODE

f (Source FILE #)

MOVFF MYREG1, MYREG2

15

12 11

1111

f (Destination FILE #)

f = 12-bit file register address

Bit-oriented file register operations

15 12 11 9 8

OPCODE b (BIT #)

7

0

BSF MYREG, bit, B

a

f (FILE #)

b = 3-bit position of bit in file register (f)

a = 0to force Access Bank

a = 1for BSR to select bank

f = 8-bit file register address

Literal operations

15

8

7

0

MOVLW 7Fh

OPCODE

k (literal)

k = 8-bit immediate value

Control operations

CALL, GOTO and Branch operations

15

8 7

0

GOTO Label

OPCODE

12 11

n<7:0> (literal)

15

0

1111

n<19:8> (literal)

n = 20-bit immediate value

15

8

7

0

CALL MYFUNC

OPCODE

12 11

n<7:0> (literal)

S

0

1111

n<19:8> (literal)

S = Fast bit

15

11 10

0

BRA MYFUNC

BC MYFUNC

OPCODE

n<10:0> (literal)

15

OPCODE

8 7

n<7:0> (literal)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 267

PIC18(L)F1XK22

TABLE 24-2: PIC18FXXXX INSTRUCTION SET

16-Bit Instruction Word

MSb LSb

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

BYTE-ORIENTED OPERATIONS

ADDWF f, d, a Add WREG and f

ADDWFC f, d, a Add WREG and CARRY bit to f

1

0010 01da

ffff

ffff C, DC, Z, OV, N

ffff Z, N

1, 2

2

1, 2

4

1, 2

1, 2, 3, 4

1, 2

1, 2, 3, 4

4

1, 2

1

0010 00da

0001 01da

0110 101a

0001 11da

ANDWF

CLRF

COMF

f, d, a AND WREG with f

f, a Clear f

f, d, a Complement f

ffff

Z

ffff Z, N

ffff None

ffff C, DC, Z, OV, N

ffff None

ffff C, DC, Z, OV, N

ffff None

ffff Z, N

ffff None

ffff

ffff None

CPFSEQ

CPFSGT

CPFSLT

DECF

f, a

Compare f with WREG, skip =

Compare f with WREG, skip >

Compare f with WREG, skip <

1 (2 or 3) 0110 001a

1 (2 or 3) 0110 010a

1 (2 or 3) 0110 000a

f, d, a Decrement f

1

0000 01da

DECFSZ

DCFSNZ

INCF

f, d, a Decrement f, Skip if 0

f, d, a Decrement f, Skip if Not 0

f, d, a Increment f

1 (2 or 3) 0010 11da

1 (2 or 3) 0100 11da

1

1 (2 or 3) 0011 11da

1 (2 or 3) 0100 10da

1

2

0010 10da

INCFSZ

INFSNZ

IORWF

MOVF

f, d, a Increment f, Skip if 0

f, d, a Increment f, Skip if Not 0

f, d, a Inclusive OR WREG with f

f, d, a Move f

0001 00da

0101 00da

1100 ffff

1111 ffff

0110 111a

0000 001a

0110 110a

0011 01da

0100 01da

0011 00da

0100 00da

0110 100a

0101 01da

MOVFF

f , f

Move f (source) to 1st word

s

d

s

f (destination) 2nd word

d

MOVWF

MULWF

NEGF

f, a

Move WREG to f

Multiply WREG with f

Negate f

1

1, 2

ffff C, DC, Z, OV, N

ffff C, Z, N

ffff Z, N

ffff C, Z, N

ffff Z, N

RLCF

RLNCF

RRCF

RRNCF

SETF

f, d, a Rotate Left f through Carry

f, d, a Rotate Left f (No Carry)

f, d, a Rotate Right f through Carry

f, d, a Rotate Right f (No Carry)

f, a

Set f

ffff None

ffff C, DC, Z, OV, N

1, 2

SUBFWB f, d, a Subtract f from WREG with

borrow

SUBWF

f, d, a Subtract WREG from f

1

0101 11da

0101 10da

ffff

ffff C, DC, Z, OV, N

SUBWFB f, d, a Subtract WREG from f with

borrow

SWAPF

TSTFSZ

XORWF

f, d, a Swap nibbles in f

f, a Test f, skip if 0

f, d, a Exclusive OR WREG with f

1

0011 10da

ffff

ffff None

ffff Z, N

4

1, 2

1 (2 or 3) 0110 011a

0001 10da

1

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

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PIC18(L)F1XK22

TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BIT-ORIENTED OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a Bit Clear f

f, b, a Bit Set f

f, b, a Bit Test f, Skip if Clear

f, b, a Bit Test f, Skip if Set

f, b, a Bit Toggle f

1

1001 bbba

1000 bbba

ffff

ffff None

1, 2

3, 4

1, 2

1 (2 or 3) 1011 bbba

1 (2 or 3) 1010 bbba

1

0111 bbba

CONTROL OPERATIONS

BC

BN

n

Branch if Carry

1 (2)

2

1110 0010

1110 0110

1110 0011

1110 0111

1110 0101

1110 0001

1110 0100

1101 0nnn

1110 0000

1110 110s

1111 kkkk

0000 0000

1110 1111

1111 kkkk

0000 0000

1111 xxxx

0000 0000

1101 1nnn

0000 0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

nnnn None

kkkk None

kkkk

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

Call subroutine 1st word

2nd word

Clear Watchdog Timer

Decimal Adjust WREG

Go to address 1st word

2nd word

BNC

BNN

BNOV

BNZ

BOV

BRA

BZ

n

k, s

1 (2)

2

CALL

CLRWDT

DAW

GOTO

—

k

1

2

0100 TO, PD

0111

C

kkkk None

kkkk

NOP

POP

PUSH

RCALL

RESET

RETFIE

—

n

No Operation

1

2

1

2

0000 None

xxxx None

0110 None

0101 None

nnnn None

1111 All

4

Pop top of return stack (TOS)

Push top of return stack (TOS)

Relative Call

Software device Reset

Return from interrupt enable

s

000s GIE/GIEH,

PEIE/GIEL

RETLW

RETURN

SLEEP

k

s

—

Return with literal in WREG

Return from Subroutine

Go into Standby mode

2

1

0000 1100

0000 0000

kkkk

0001

0000

kkkk None

001s None

0011 TO, PD

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

 2009-2016 Microchip Technology Inc.

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PIC18(L)F1XK22

TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

k

f, k

Add literal and WREG

AND literal with WREG

Inclusive OR literal with WREG

Move literal (12-bit) 2nd word

1

2

0000 1111 kkkk

0000 1011 kkkk

0000 1001 kkkk

1110 1110 00ff

1111 0000 kkkk

0000 0001 0000

0000 1110 kkkk

0000 1101 kkkk

0000 1100 kkkk

0000 1000 kkkk

0000 1010 kkkk

kkkk C, DC, Z, OV, N

kkkk Z, N

kkkk None

kkkk

kkkk None

kkkk C, DC, Z, OV, N

kkkk Z, N

to FSR(f)

1st word

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

k

Move literal to BSR<3:0>

Move literal to WREG

Multiply literal with WREG

Return with literal in WREG

Subtract WREG from literal

Exclusive OR literal with WREG

1

2

1

DATA MEMORY  PROGRAM MEMORY OPERATIONS

TBLRD*

Table Read

2

0000 0000 0000

1000 None

1001 None

1010 None

1011 None

1100 None

1101 None

1110 None

1111 None

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

2

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

DS40001365F-page 270

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PIC18(L)F1XK22

24.1.1

STANDARD INSTRUCTION SET

ADDLW

ADD literal to W

ADDWF

ADD W to f

Syntax:

ADDLW

k

Syntax:

ADDWF

f {,d {,a}}

Operands:

Operation:

Status Affected:

Encoding:

Description:

0  k  255

Operands:

0  f  255

d  [0,1]

a  [0,1]

(W) + k  W

N, OV, C, DC, Z

Operation:

(W) + (f)  dest

0000

1111

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

W.

0010

01da

ffff

Description:

Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

Words:

Cycles:

1

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

ADDLW

15h

Before Instruction

10h

After Instruction

25h

W

=

Words:

Cycles:

1

W

=

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

ADDWF

REG, 0, 0

Before Instruction

W

=

17h

REG

=

0C2h

After Instruction

W

REG

=

0D9h

0C2h

Note:

All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

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PIC18(L)F1XK22

ADDWFC

ADD W and CARRY bit to f

ANDLW

AND literal with W

Syntax:

ADDWFC

f {,d {,a}}

Syntax:

ANDLW

k

Operands:

0  f  255

d [0,1]

a [0,1]

Operands:

Operation:

Status Affected:

Encoding:

Description:

0  k  255

(W) .AND. k  W

N, Z

Operation:

(W) + (f) + (C)  dest

0000

1011

kkkk

Status Affected:

Encoding:

N,OV, C, DC, Z

The contents of W are AND’ed with the

8-bit literal ‘k’. The result is placed in W.

0010

00da

ffff

Description:

Add W, the CARRY flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘k’

Process

Data

Write to W

Example:

ANDLW

05Fh

Before Instruction

W

=

A3h

03h

After Instruction

W

=

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

ADDWFC

REG, 0, 1

Before Instruction

CARRY bit =

1

02h

4Dh

REG

W

=

After Instruction

CARRY bit =

0

02h

50h

REG

W

=

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ANDWF

AND W with f

BC

Branch if Carry

Syntax:

ANDWF

f {,d {,a}}

Syntax:

BC

n

Operands:

0  f  255

d [0,1]

a [0,1]

Operands:

Operation:

-128  n  127

if CARRY bit is ‘1’

(PC) + 2 + 2n  PC

Operation:

(W) .AND. (f)  dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

1110

0010

nnnn

0001

01da

ffff

Description:

If the CARRY bit is ‘1’, then the program

will branch.

Description:

The contents of W are AND’ed with

register ‘f’. If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

2-cycle instruction.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Words:

1

Cycles:

No

operation

Q Cycle Activity:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

ANDWF

REG, 0, 0

Example:

HERE

BC

5

Before Instruction

W

REG

=

17h

C2h

PC

=

address (HERE)

1;

address (HERE + 12)

0;

address (HERE + 2)

After Instruction

If CARRY

PC

If CARRY

PC

=

W

REG

=

02h

C2h

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PIC18(L)F1XK22

BCF

Bit Clear f

BN

Branch if Negative

Syntax:

BCF f, b {,a}

Syntax:

BN

n

Operands:

0  f  255

0  b  7

a [0,1]

Operands:

Operation:

-128  n  127

if NEGATIVE bit is ‘1’

(PC) + 2 + 2n  PC

Operation:

0  f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0110

nnnn

1001

bbba

ffff

Description:

If the NEGATIVE bit is ‘1’, then the

program will branch.

Description:

Bit ‘b’ in register ‘f’ is cleared.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

2-cycle instruction.

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Words:

Cycles:

1

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Q Cycle Activity:

Q1

Q2

Q3

Q4

No

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

operation

If No Jump:

Q1

Q2

Q3

Q4

Example:

BCF

FLAG_REG, 7, 0

C7h

47h

Decode

Read literal

‘n’

Process

Data

No

operation

Before Instruction

FLAG_REG =

After Instruction

FLAG_REG =

Example:

HERE

BN Jump

Before Instruction

PC

=

address (HERE)

After Instruction

If NEGATIVE

PC

If NEGATIVE

PC

=

1;

address (Jump)

0;

address (HERE + 2)

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BNC

Branch if Not Carry

BNN

Branch if Not Negative

Syntax:

BNC

n

Syntax:

BNN

n

Operands:

Operation:

-128  n  127

Operands:

Operation:

-128  n  127

if CARRY bit is ‘0’

(PC) + 2 + 2n  PC

if NEGATIVE bit is ‘0’

(PC) + 2 + 2n  PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0011

nnnn

1110

0111

nnnn

Description:

If the CARRY bit is ‘0’, then the program

will branch.

Description:

If the NEGATIVE bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

2-cycle instruction.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

2-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

HERE

BNC Jump

Example:

HERE

BNN Jump

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If CARRY

PC

If CARRY

PC

=

0;

If NEGATIVE

PC

If NEGATIVE

PC

=

0;

address (Jump)

1;

address (Jump)

1;

address (HERE + 2)

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PIC18(L)F1XK22

BNOV

Branch if Not Overflow

BNZ

Branch if Not Zero

Syntax:

BNOV

n

Syntax:

BNZ

n

Operands:

Operation:

-128  n  127

Operands:

Operation:

-128  n  127

if OVERFLOW bit is ‘0’

(PC) + 2 + 2n  PC

if ZERO bit is ‘0’

(PC) + 2 + 2n  PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0101

nnnn

1110

0001

nnnn

Description:

If the OVERFLOW bit is ‘0’, then the

program will branch.

Description:

If the ZERO bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

2-cycle instruction.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

2-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

HERE

BNOV Jump

Example:

HERE

BNZ Jump

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If OVERFLOW =

PC

0;

If ZERO

PC

If ZERO

PC

=

0;

=

address (Jump)

1;

address (Jump)

1;

If OVERFLOW =

PC

=

address (HERE + 2)

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BRA

Unconditional Branch

BSF

Bit Set f

Syntax:

BRA

n

Syntax:

BSF f, b {,a}

Operands:

Operation:

-1024  n  1023

Operands:

0  f  255

0  b  7

a [0,1]

(PC) + 2 + 2n  PC

Status Affected: None

Operation:

1  f

Encoding:

1101

0nnn

nnnn

Status Affected:

Encoding:

None

1000

Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Description:

Add the 2’s complement number ‘2n’ to

the PC. Since the PC will have incre-

mented to fetch the next instruction, the

new address will be PC + 2 + 2n. This

instruction is a 2-cycle instruction.

bbba

ffff

Description:

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

1

Q Cycle Activity:

Q1

Example:

HERE

BRA Jump

Q2

Q3

Q4

Before Instruction

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

PC

=

address (HERE)

address (Jump)

After Instruction

PC

Example:

BSF

FLAG_REG, 7, 1

0Ah

8Ah

Before Instruction

FLAG_REG

After Instruction

FLAG_REG

=

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PIC18(L)F1XK22

BTFSC

Bit Test File, Skip if Clear

BTFSS

Bit Test File, Skip if Set

Syntax:

BTFSC f, b {,a}

Syntax:

BTFSS f, b {,a}

Operands:

0  f  255

0  b  7

a [0,1]

Operands:

0  f  255

0  b < 7

a [0,1]

Operation:

skip if (f) = 0

Operation:

skip if (f) = 1

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1011

bbba

ffff

1010

bbba

ffff

Description:

If bit ‘b’ in register ‘f’ is ‘0’, then the next

instruction is skipped. If bit ‘b’ is ‘0’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOPis executed instead, making

this a 2-cycle instruction.

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the next

instruction is skipped. If bit ‘b’ is ‘1’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOPis executed instead, making

this a 2-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing

mode whenever f 95 (5Fh).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh).

See Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

See Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

No

operation

Decode

Read

register ‘f’

Process

Data

No

operation

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

Example:

HERE

FALSE

TRUE

BTFSC

:

FLAG, 1, 0

Example:

HERE

FALSE

TRUE

BTFSS

:

FLAG, 1, 0

Before Instruction

PC

Before Instruction

PC

=

address (HERE)

=

address (HERE)

After Instruction

If FLAG<1>

PC

If FLAG<1>

PC

=

0;

If FLAG<1>

PC

If FLAG<1>

PC

=

0;

address (TRUE)

1;

address (FALSE)

1;

address (FALSE)

address (TRUE)

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BTG

Bit Toggle f

BOV

Branch if Overflow

Syntax:

BTG f, b {,a}

Syntax:

BOV

n

Operands:

0  f  255

0  b < 7

a [0,1]

Operands:

Operation:

-128  n  127

if OVERFLOW bit is ‘1’

(PC) + 2 + 2n  PC

Operation:

(f)  f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0100

nnnn

0111

bbba

ffff

Description:

If the OVERFLOW bit is ‘1’, then the

program will branch.

Description:

Bit ‘b’ in data memory location ‘f’ is

inverted.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

2-cycle instruction.

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Words:

Cycles:

1

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Q Cycle Activity:

Q1

No

operation

No

operation

No

operation

No

operation

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

If No Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

BTG

PORTC, 4, 0

Before Instruction:

PORTC

After Instruction:

PORTC

=

0111 0101 [75h]

0110 0101 [65h]

Example:

HERE

BOV Jump

Before Instruction

=

PC

=

address (HERE)

After Instruction

If OVERFLOW =

PC

If OVERFLOW =

PC

1;

=

address (Jump)

0;

=

address (HERE + 2)

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PIC18(L)F1XK22

BZ

Branch if Zero

CALL

Subroutine Call

Syntax:

BZ

n

Syntax:

CALL k {,s}

Operands:

Operation:

-128  n  127

Operands:

0  k  1048575

s [0,1]

if ZERO bit is ‘1’

(PC) + 2 + 2n  PC

Operation:

(PC) + 4  TOS,

k  PC<20:1>,

if s = 1

Status Affected:

Encoding:

None

1110

0000

nnnn

(W)  WS,

(Status)  STATUSS,

(BSR)  BSRS

Description:

If the ZERO bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

2-cycle instruction.

Status Affected:

None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

110s

k kkk

kkkk

7

0

8

k

kkk kkkk

19

Description:

Subroutine call of entire 2-Mbyte

memory range. First, return address

(PC + 4) is pushed onto the return

stack. If ‘s’ = 1, the W, Status and BSR

registers are also pushed into their

respective shadow registers, WS,

STATUSS and BSRS. If ‘s’ = 0, no

update occurs (default). Then, the

20-bit value ‘k’ is loaded into PC<20:1>.

CALLis a 2-cycle instruction.

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

No

Words:

Cycles:

2

operation

If No Jump:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read literal

‘n’

Process

Data

No

operation

Q2

Q3

Q4

Decode

Read literal PUSH PC to Read literal

‘k’<7:0>,

stack

‘k’<19:8>,

Write to PC

Example:

HERE

BZ Jump

No

operation

No

operation

No

operation

No

operation

Before Instruction

PC

=

address (HERE)

After Instruction

If ZERO

PC

If ZERO

PC

=

1;

Example:

HERE

CALL THERE, 1

address (Jump)

0;

Before Instruction

PC

After Instruction

address (HERE + 2)

=

address (HERE)

PC

=

address (THERE)

TOS

WS

=

address (HERE + 4)

W

BSR

Status

BSRS

STATUSS=

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CLRF

Clear f

CLRWDT

Clear Watchdog Timer

Syntax:

CLRF f {,a}

Syntax:

CLRWDT

None

Operands:

0  f  255

a [0,1]

Operands:

Operation:

000h  WDT,

000h  WDT postscaler,

1  TO,

Operation:

000h  f

1  Z

1  PD

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

TO, PD

0110

101a

ffff

0000

0100

Description:

Clears the contents of the specified

register.

Description:

CLRWDTinstruction resets the

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Watchdog Timer. It also resets the post-

scaler of the WDT. Status bits, TO and

PD, are set.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

Process

Data

No

operation

Words:

Cycles:

1

Example:

CLRWDT

Q Cycle Activity:

Q1

Before Instruction

Q2

Q3

Q4

WDT Counter

After Instruction

WDT Counter

WDT Postscaler

TO

=

?

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

=

00h

0

1

Example:

CLRF

FLAG_REG, 1

PD

1

Before Instruction

FLAG_REG

After Instruction

FLAG_REG

=

5Ah

00h

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PIC18(L)F1XK22

CPFSEQ

Compare f with W, skip if f = W

COMF

Complement f

Syntax:

CPFSEQ f {,a}

Syntax:

COMF f {,d {,a}}

Operands:

0  f  255

a  [0,1]

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(f) – (W),

skip if (f) = (W)

(unsigned comparison)

Operation:

(f)  dest

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

None

0001

11da

ffff

0110

001a

ffff

Description:

The contents of register ‘f’ are

Description:

Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If ‘f’ = W, then the fetched instruction is

discarded and a NOPis executed

instead, making this a 2-cycle

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

instruction.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

1(2)

Decode

Read

register ‘f’

Process

Data

Write to

destination

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Example:

COMF

REG, 0, 0

Q2

Q3

Q4

Before Instruction

Decode

Read

register ‘f’

Process

Data

No

operation

REG

=

13h

After Instruction

If skip:

REG

W

=

13h

ECh

Q1

No

Q2

No

Q3

No

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

No

Q2

No

Q3

No

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

Example:

HERE

CPFSEQ REG, 0

NEQUAL

EQUAL

:

Before Instruction

PC Address

=

HERE

W

REG

=

?

After Instruction

If REG

PC

=

W;

Address (EQUAL)

If REG

PC



=

W;

Address (NEQUAL)

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CPFSGT

Compare f with W, skip if f > W

CPFSLT

Compare f with W, skip if f < W

Syntax:

CPFSGT f {,a}

Syntax:

CPFSLT f {,a}

Operands:

0  f  255

a  [0,1]

Operands:

0  f  255

a  [0,1]

Operation:

(f) –W),

skip if (f) > (W)

(unsigned comparison)

Operation:

(f) –W),

skip if (f) < (W)

(unsigned comparison)

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0110

010a

ffff

000a

ffff

Description:

Compares the contents of data memory

location ‘f’ to the contents of the W by

performing an unsigned subtraction.

If the contents of ‘f’ are greater than the

^{contents of WREG}, then the fetched

instruction is discarded and a NOPis

executed instead, making this a

Description:

Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If the contents of ‘f’ are less than the

contents of W, then the fetched

instruction is discarded and a NOPis

executed instead, making this a

2-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Words:

Cycles:

1

1(2)

Note: Three cycles if skip and

followed by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Words:

Cycles:

1

Decode

Read

register ‘f’

Process

Data

No

operation

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

If skip:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

No

operation

No

operation

No

operation

No

operation

Q2

Q3

Q4

No

operation

Decode

Read

register ‘f’

Process

Data

If skip and followed by 2-word instruction:

If skip:

Q1

Q2

Q3

Q4

Q1

No

Q2

No

Q3

No

Q4

No

operation

No

operation

No

operation

No

operation

No

If skip and followed by 2-word instruction:

operation

Q1

No

operation

No

Q2

No

operation

No

Q3

No

operation

No

Q4

No

operation

No

Example:

HERE

NLESS

LESS

CPFSLT REG, 1

:

operation

Before Instruction

PC

W

=

Address (HERE)

Example:

HERE

NGREATER

GREATER

CPFSGT REG, 0

:

?

After Instruction

If REG

PC

If REG

PC

<

=



W;

Before Instruction

Address (LESS)

W;

Address (NLESS)

PC

W

=

Address (HERE)

?

=

After Instruction

If REG

PC



=

W;

Address (GREATER)

If REG

PC



=

W;

Address (NGREATER)

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PIC18(L)F1XK22

DAW

Decimal Adjust W Register

DECF

Decrement f

Syntax:

DAW

None

Syntax:

DECF f {,d {,a}}

Operands:

Operation:

Operands:

0  f  255

d  [0,1]

a  [0,1]

If [W<3:0> > 9] or [DC = 1] then

(W<3:0>) + 6  W<3:0>;

else

Operation:

(f) – 1  dest

(W<3:0>)  W<3:0>;

Status Affected:

Encoding:

C, DC, N, OV, Z

0000

01da

ffff

If [W<7:4> + DC > 9] or [C = 1] then

(W<7:4>) + 6 + DC  W<7:4>;

else

Description:

Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

(W<7:4>) + DC  W<7:4>

Status Affected:

Encoding:

C

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

0000

0111

Description:

DAW adjusts the 8-bit value in W, result-

ing from the earlier addition of two vari-

ables (each in packed BCD format) and

produces a correct packed BCD result.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read

register W

Process

Data

Write

W

Q Cycle Activity:

Q1

Example1:

Q2

Q3

Q4

DAW

Decode

Read

register ‘f’

Process

Data

Write to

destination

Before Instruction

W

=

A5h

C

DC

=

0

Example:

DECF

CNT,

1, 0

After Instruction

Before Instruction

CNT

Z

After Instruction

=

01h

0

W

C

DC

=

05h

1

0

=

Example 2:

CNT

Z

=

00h

1

Before Instruction

W

=

CEh

C

DC

=

0

After Instruction

W

=

34h

C

DC

=

1

0

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PIC18(L)F1XK22

DECFSZ

Decrement f, skip if 0

DCFSNZ

Decrement f, skip if not 0

Syntax:

DECFSZ f {,d {,a}}

Syntax:

DCFSNZ f {,d {,a}}

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(f) – 1  dest,

Operation:

(f) – 1  dest,

skip if result = 0

skip if result  0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0100

The contents of register ‘f’ are

0010

11da

ffff

11da

ffff

Description:

The contents of register ‘f’ are

Description:

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOPis executed instead, making

it a 2-cycle instruction.

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOPis executed

instead, making it a 2-cycle

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

Process

Data

Write to

destination

register ‘f’

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

Example:

HERE

DECFSZ

GOTO

CNT, 1, 1

LOOP

Example:

HERE

ZERO

NZERO

DCFSNZ TEMP, 1, 0

:

CONTINUE

Before Instruction

PC

After Instruction

Before Instruction

TEMP

After Instruction

=

Address (HERE)

=

?

CNT

=

CNT - 1

0;

If CNT

=



=

TEMP

If TEMP

PC

If TEMP

PC

=



=

TEMP – 1,

0;

PC

Address (CONTINUE)

0;

If CNT

PC

Address (ZERO)

0;

Address (HERE + 2)

Address (NZERO)

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PIC18(L)F1XK22

GOTO

Unconditional Branch

INCF

Increment f

Syntax:

GOTO

k

Syntax:

INCF f {,d {,a}}

Operands:

Operation:

Status Affected:

0  k  1048575

k  PC<20:1>

None

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(f) + 1  dest

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

Status Affected:

Encoding:

C, DC, N, OV, Z

1110

1111

kkk

k kkk

kkkk

7

0

8

k

0010

10da

ffff

19

Description:

GOTOallows an unconditional branch

anywhere within entire 2-Mbyte memory

range. The 20-bit value ‘k’ is loaded into

PC<20:1>. GOTOis always a 2-cycle

instruction.

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘k’<7:0>,

No

operation

Read literal

‘k’<19:8>,

Write to PC

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

1

Q Cycle Activity:

Q1

Example:

GOTO THERE

Q2

Q3

Q4

After Instruction

Decode

Read

register ‘f’

Process

Data

Write to

destination

PC

=

Address (THERE)

Example:

INCF

CNT, 1, 0

Before Instruction

CNT

Z

=

FFh

0

=

C

?

DC

?

After Instruction

CNT

Z

=

00h

1

=

C

1

DC

1

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INFSNZ

Increment f, skip if not 0

INCFSZ

Increment f, skip if 0

Syntax:

INFSNZ f {,d {,a}}

Syntax:

INCFSZ f {,d {,a}}

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(f) + 1  dest,

skip if result  0

Operation:

(f) + 1  dest,

skip if result = 0

Status Affected:

Encoding:

None

0100

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

Status Affected:

Encoding:

None

10da

ffff

0011

11da

ffff

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOPis executed instead, making

it a 2-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

instruction, which is already fetched, is

discarded and a NOPis executed

instead, making it a 2-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

register ‘f’

Process

Data

Write to

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

Example:

HERE

NZERO

ZERO

INCFSZ

:

CNT, 1, 0

Example:

HERE

ZERO

NZERO

INFSNZ REG, 1, 0

Before Instruction

PC

After Instruction

Before Instruction

PC

After Instruction

=

Address (HERE)

=

Address (HERE)

REG

If REG

PC

If REG

PC

=

REG + 1

0;

Address (NZERO)

0;

Address (ZERO)

CNT

If CNT

PC

If CNT

PC

=

CNT + 1



=



=

0;

Address (ZERO)

0;

Address (NZERO)

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PIC18(L)F1XK22

IORLW

Inclusive OR literal with W

IORWF

Inclusive OR W with f

Syntax:

IORLW

k

Syntax:

IORWF f {,d {,a}}

Operands:

Operation:

Status Affected:

Encoding:

Description:

0  k  255

(W) .OR. k  W

N, Z

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(W) .OR. (f)  dest

0000

1001

kkkk

Status Affected:

Encoding:

N, Z

The contents of W are ORed with the 8-

bit literal ‘k’. The result is placed in W.

0001

00da

ffff

Description:

Inclusive OR W with register ‘f’. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is placed back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

Process

Data

Write to W

literal ‘k’

Example:

IORLW

35h

Before Instruction

W

=

9Ah

BFh

After Instruction

W

=

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

IORWF RESULT, 0, 1

Before Instruction

RESULT =

13h

91h

W

=

After Instruction

RESULT =

13h

93h

W

=

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PIC18(L)F1XK22

LFSR

Load FSR

MOVF

Move f

Syntax:

LFSR f, k

Syntax:

MOVF f {,d {,a}}

Operands:

0  f  2

0  k  4095

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

k  FSRf

Operation:

f  dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

0101

1110

1111

1110

0000

00ff

k kkk

11

kkkk

00da

ffff

7

Description:

The 12-bit literal ‘k’ is loaded into the

File Select Register pointed to by ‘f’.

Description:

The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘k’ MSB

Process

Data

Write

literal ‘k’

MSB to

FSRfH

Decode

Read literal

‘k’ LSB

Process

Data

Write literal

‘k’ to FSRfL

Example:

LFSR 2, 3ABh

After Instruction

Words:

Cycles:

1

FSR2H

FSR2L

=

03h

ABh

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write W

Example:

MOVF

REG, 0, 0

Before Instruction

REG

W

=

22h

FFh

After Instruction

REG

W

=

22h

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PIC18(L)F1XK22

MOVFF

Move f to f

MOVLB

Move literal to low nibble in BSR

Syntax:

MOVFF f ,f

Syntax:

MOVLB k

s

d

Operands:

0  f  4095

Operands:

Operation:

Status Affected:

Encoding:

Description:

0  k  255

k  BSR

None

s

0  f  4095

d

Operation:

(f )  f

s

d

Status Affected:

None

0000

0001

0000

kkkk

Encoding:

1st word (source)

2nd word (destin.)

The 8-bit literal ‘k’ is loaded into the

Bank Select Register (BSR). The value

of BSR<7:4> always remains ‘0’,

1100

1111

ffff

ffff_s

ffff_d

Description:

The contents of source register ‘f ’ are

regardless of the value of k :k .

s

7 4

moved to destination register ‘f ’.

d

Words:

Cycles:

1

Location of source ‘f ’ can be anywhere

s

in the 4096-byte data space (000h to

FFFh) and location of destination ‘f ’

can also be anywhere from 000h to

FFFh.

Either source or destination can be W

(a useful special situation).

d

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write literal

‘k’ to BSR

MOVFFis particularly useful for

transferring a data memory location to a

peripheral register (such as the transmit

buffer or an I/O port).

The MOVFFinstruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Example:

MOVLB

5

Before Instruction

BSR Register =

After Instruction

BSR Register =

02h

05h

Words:

Cycles:

2

2 (3)

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

(src)

Process

Data

No

operation

Decode

No

operation

No

operation

Write

register ‘f’

(dest)

No dummy

read

Example:

MOVFF

REG1, REG2

Before Instruction

REG1

REG2

=

33h

11h

After Instruction

REG1

REG2

=

33h

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PIC18(L)F1XK22

MOVLW

Move literal to W

MOVWF

Move W to f

Syntax:

MOVLW

k

Syntax:

MOVWF f {,a}

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

0  k  255

k  W

None

Operands:

0  f  255

a  [0,1]

Operation:

(W)  f

Status Affected:

Encoding:

None

0110

Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank.

0000

1110

kkkk

111a

ffff

The 8-bit literal ‘k’ is loaded into W.

Description:

1

Cycles:

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

MOVLW

5Ah

After Instruction

W

=

5Ah

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

Example:

MOVWF

REG, 0

Before Instruction

W

REG

=

4Fh

FFh

After Instruction

W

REG

=

4Fh

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PIC18(L)F1XK22

MULLW

Multiply literal with W

MULWF

Multiply W with f

Syntax:

MULLW

k

Syntax:

MULWF f {,a}

Operands:

Operation:

Status Affected:

Encoding:

Description:

0  k  255

Operands:

0  f  255

a  [0,1]

(W) x k  PRODH:PRODL

Operation:

(W) x (f)  PRODH:PRODL

None

Status Affected:

Encoding:

None

0000

1101

kkkk

0000

001a

ffff

An unsigned multiplication is carried

out between the contents of W and the

8-bit literal ‘k’. The 16-bit result is

placed in the PRODH:PRODL register

pair. PRODH contains the high byte.

W is unchanged.

None of the Status flags are affected.

Note that neither overflow nor carry is

possible in this operation. A zero result

is possible but not detected.

Description:

An unsigned multiplication is carried

out between the contents of W and the

register file location ‘f’. The 16-bit

result is stored in the PRODH:PRODL

register pair. PRODH contains the

high byte. Both W and ‘f’ are

unchanged.

None of the Status flags are affected.

Note that neither overflow nor carry is

possible in this operation. A zero

result is possible but not detected.

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write

registers

PRODH:

PRODL

f 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Example:

MULLW

0C4h

Before Instruction

Words:

Cycles:

1

W

PRODH

PRODL

=

E2h

?

Q Cycle Activity:

Q1

After Instruction

W

Q2

Q3

Q4

=

E2h

ADh

08h

Decode

Read

register ‘f’

Process

Data

Write

PRODH

PRODL

registers

PRODH:

PRODL

Example:

MULWF

REG, 1

Before Instruction

W

=

C4h

REG

PRODH

PRODL

=

B5h

?

After Instruction

W

=

C4h

REG

PRODH

PRODL

=

B5h

8Ah

94h

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PIC18(L)F1XK22

NEGF

Negate f

NOP

No Operation

Syntax:

NEGF f {,a}

Syntax:

NOP

Operands:

0  f  255

a  [0,1]

Operands:

Operation:

None

No operation

Operation:

( f ) + 1  f

Status Affected:

Encoding:

None

0000

1111

Status Affected:

Encoding:

N, OV, C, DC, Z

0000

xxxx

0000

xxxx

0000

xxxx

0110

110a

ffff

Description:

Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Description:

Words:

No operation.

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

No

Q4

Decode

No

operation

No

operation

Example:

None.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

Example:

NEGF

REG, 1

Before Instruction

REG

After Instruction

REG

=

0011 1010 [3Ah]

1100 0110 [C6h]

=

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PIC18(L)F1XK22

POP

Pop Top of Return Stack

PUSH

Push Top of Return Stack

Syntax:

POP

Syntax:

PUSH

Operands:

Operation:

Status Affected:

Encoding:

Description:

None

Operands:

Operation:

Status Affected:

Encoding:

Description:

None

(TOS)  bit bucket

(PC + 2)  TOS

None

0000

0110

0000

0101

The TOS value is pulled off the return

stack and is discarded. The TOS value

then becomes the previous value that

was pushed onto the return stack.

This instruction is provided to enable

the user to properly manage the return

stack to incorporate a software stack.

The PC + 2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implementing a

software stack by modifying TOS and

then pushing it onto the return stack.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

PUSH

No

Decode

No

operation

POP TOS

value

No

operation

PC + 2 onto

return stack

operation

Example:

POP

Example:

PUSH

GOTO

NEW

Before Instruction

TOS

Stack (1 level down)

After Instruction

TOS

PC

=

345Ah

0124h

=

0031A2h

014332h

After Instruction

PC

TOS

=

0126h

345Ah

TOS

PC

=

014332h

NEW

Stack (1 level down)

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PIC18(L)F1XK22

RCALL

Relative Call

RESET

Reset

Syntax:

RCALL

n

Syntax:

RESET

None

Operands:

Operation:

-1024  n  1023

Operands:

Operation:

(PC) + 2  TOS,

(PC) + 2 + 2n  PC

Reset all registers and flags that are

affected by a MCLR Reset.

Status Affected:

Encoding:

None

Status Affected:

Encoding:

All

0000

1101

1nnn

nnnn

0000

1111

Description:

Subroutine call with a jump up to 1K

from the current location. First, return

address (PC + 2) is pushed onto the

stack. Then, add the 2’s complement

number ‘2n’ to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

2-cycle instruction.

Description:

This instruction provides a way to

execute a MCLR Reset by software.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Start

No

Reset

operation

Words:

Cycles:

1

2

Example:

RESET

Q Cycle Activity:

Q1

After Instruction

Registers =

Q2

Q3

Q4

Reset Value

Flags*

=

Decode

Read literal

‘n’

Process

Data

Write to PC

PUSH PCto

stack

No

operation

Example:

HERE

RCALL Jump

Before Instruction

PC

After Instruction

PC

TOS =

=

Address (HERE)

=

Address (Jump)

Address (HERE + 2)

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PIC18(L)F1XK22

RETFIE

Return from Interrupt

RETLW

Return literal to W

Syntax:

RETFIE {s}

Syntax:

RETLW k

Operands:

Operation:

s  [0,1]

Operands:

Operation:

0  k  255

(TOS)  PC,

k  W,

1  GIE/GIEH or PEIE/GIEL,

if s = 1

(TOS)  PC,

PCLATU, PCLATH are unchanged

(WS)  W,

(STATUSS)  Status,

(BSRS)  BSR,

Status Affected:

Encoding:

None

0000

1100

kkkk

PCLATU, PCLATH are unchanged.

Description:

W is loaded with the 8-bit literal ‘k’. The

program counter is loaded from the top

of the stack (the return address). The

high address latch (PCLATH) remains

unchanged.

Status Affected:

Encoding:

GIE/GIEH, PEIE/GIEL

0000

0001

000s

Description:

Return from interrupt. Stack is popped

and Top-of-Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low priority

global interrupt enable bit. If ‘s’ = 1, the

contents of the shadow registers, WS,

STATUSS and BSRS, are loaded into

their corresponding registers, W,

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

POP PC

from stack,

Write to W

Status and BSR. If ‘s’ = 0, no update of

these registers occurs (default).

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Example:

Q2

Q3

Q4

CALL TABLE ; W contains table

; offset value

Decode

No

operation

No

operation

POP PC

from stack

; W now has

; table value

Set GIEH or

GIEL

:

No

operation

No

operation

No

operation

No

operation

TABLE

ADDWF PCL ; W = offset

RETLW k0

RETLW k1

; Begin table

;

Example:

RETFIE

1

:

After Interrupt

PC

W

=

TOS

WS

RETLW kn

; End of table

BSR

Status

GIE/GIEH, PEIE/GIEL

BSRS

STATUSS

1

Before Instruction

W

=

07h

After Instruction

W

=

value of kn

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PIC18(L)F1XK22

RETURN

Return from Subroutine

RLCF

Rotate Left f through Carry

Syntax:

RETURN {s}

Syntax:

RLCF f {,d {,a}}

Operands:

Operation:

s  [0,1]

Operands:

0  f  255

d  [0,1]

a  [0,1]

(TOS)  PC,

if s = 1

(WS)  W,

Operation:

(f<n>)  dest<n + 1>,

(f<7>)  C,

(C)  dest<0>

(STATUSS)  Status,

(BSRS)  BSR,

PCLATU, PCLATH are unchanged

Status Affected:

Encoding:

C, N, Z

Status Affected:

Encoding:

None

0011

01da

ffff

0000

0001

001s

Description:

The contents of register ‘f’ are rotated

one bit to the left through the CARRY

flag. If ‘d’ is ‘0’, the result is placed in

W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used to

select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

Description:

Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers, WS, STATUSS and BSRS,

are loaded into their corresponding

registers, W, Status and BSR. If

‘s’ = 0, no update of these registers

occurs (default).

Words:

Cycles:

1

2

f 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

Process

Data

POP PC

from stack

register f

C

No

Words:

Cycles:

1

operation

Q Cycle Activity:

Q1

Example:

RETURN

Q2

Q3

Q4

After Instruction:

PC = TOS

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

RLCF

REG, 0, 0

Before Instruction

REG

C

=

1110 0110

0

After Instruction

REG

=

1110 0110

W

C

=

1100 1100

1

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PIC18(L)F1XK22

RLNCF

Rotate Left f (No Carry)

RRCF

Rotate Right f through Carry

Syntax:

RLNCF f {,d {,a}}

Syntax:

RRCF f {,d {,a}}

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(f<n>)  dest<n + 1>,

(f<7>)  dest<0>

Operation:

(f<n>)  dest<n – 1>,

(f<0>)  C,

(C)  dest<7>

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

C, N, Z

0100

01da

ffff

0011

00da

ffff

Description:

The contents of register ‘f’ are rotated

one bit to the left. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Description:

The contents of register ‘f’ are rotated

one bit to the right through the CARRY

flag. If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed back in

register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

register f

C

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register ‘f’

Process

Data

Write to

destination

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

RLNCF

REG, 1, 0

Before Instruction

REG

After Instruction

Example:

RRCF

REG, 0, 0

=

1010 1011

0101 0111

Before Instruction

REG

=

REG

C

=

1110 0110

0

After Instruction

REG

=

1110 0110

W

C

=

0111 0011

0

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PIC18(L)F1XK22

RRNCF

Rotate Right f (No Carry)

SETF

Set f

Syntax:

RRNCF f {,d {,a}}

Syntax:

SETF f {,a}

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operands:

0  f  255

a [0,1]

Operation:

FFh  f

Operation:

(f<n>)  dest<n – 1>,

(f<0>)  dest<7>

Status Affected:

Encoding:

None

0110

100a

ffff

Status Affected:

Encoding:

N, Z

Description:

The contents of the specified register

are set to FFh.

0100

00da

ffff

Description:

The contents of register ‘f’ are rotated

one bit to the right. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If ‘a’

is ‘1’, then the bank will be selected as

per the BSR value (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

register f

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

Words:

Cycles:

1

Example:

SETF

REG, 1

Q Cycle Activity:

Q1

Before Instruction

REG

After Instruction

REG

=

5Ah

FFh

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example 1:

RRNCF

REG, 1, 0

Before Instruction

REG

After Instruction

REG

=

1101 0111

1110 1011

RRNCF REG, 0, 0

=

Example 2:

Before Instruction

W

REG

=

?

1101 0111

After Instruction

W

REG

=

1110 1011

1101 0111

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PIC18(L)F1XK22

SLEEP

Enter Sleep mode

SUBFWB

Subtract f from W with borrow

Syntax:

SLEEP

None

Syntax:

SUBFWB f {,d {,a}}

Operands:

Operation:

Operands:

0 f 255

d  [0,1]

a  [0,1]

00h  WDT,

0  WDT postscaler,

1  TO,

Operation:

(W) – (f) – (C) dest

0  PD

Status Affected:

Encoding:

N, OV, C, DC, Z

Status Affected:

Encoding:

TO, PD

0101

01da

ffff

0000

0011

Description:

Subtract register ‘f’ and CARRY flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored in

register ‘f’ (default).

Description:

The Power-down Status bit (PD) is

cleared. The Time-out Status bit (TO)

is set. Watchdog Timer and its posts-

caler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

Process

Data

Go to

Sleep

Example:

SLEEP

Words:

Cycles:

1

Before Instruction

TO

PD

=

?

Q Cycle Activity:

Q1

Q2

Q3

Q4

After Instruction

Decode

Read

register ‘f’

Process

Data

Write to

destination

TO

PD

=

1†

0

Example 1:

SUBFWB

REG, 1, 0

†

If WDT causes wake-up, this bit is cleared.

Before Instruction

REG

W

C

=

3

2

1

After Instruction

REG

W

C

=

FF

2

=

0

Z

0

1

N

; result is negative

Example 2:

Before Instruction

SUBFWB

REG, 0, 0

REG

W

=

2

5

1

C

After Instruction

REG

W

C

=

2

3

1

0

=

Z

N

0

; result is positive

Example 3:

SUBFWB

REG, 1, 0

Before Instruction

REG

W

=

1

2

0

C

After Instruction

REG

W

C

=

0

2

1

0

=

Z

; result is zero

N

DS40001365F-page 300

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

SUBLW

Subtract W from literal

SUBWF

Subtract W from f

Syntax:

SUBLW

k

Syntax:

SUBWF f {,d {,a}}

Operands:

Operation:

Status Affected:

Encoding:

Description

0 k 255

Operands:

0 f 255

d  [0,1]

a  [0,1]

k – (W) W

N, OV, C, DC, Z

Operation:

(f) – (W) dest

0000

1000

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

0101 11da

W is subtracted from the 8-bit

literal ‘k’. The result is placed in W.

ffff

Description:

Subtract W from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Decode

Read

literal ‘k’

Process

Data

Write to W

Example 1:

SUBLW 02h

Before Instruction

W

C

=

01h

?

After Instruction

W

C

Z

=

01h

=

1

0

; result is positive

N

Words:

Cycles:

1

Example 2:

SUBLW 02h

Before Instruction

Q Cycle Activity:

Q1

W

C

=

02h

?

Q2

Q3

Q4

After Instruction

Decode

Read

register ‘f’

Process

Data

Write to

destination

W

C

Z

=

00h

=

1

0

; result is zero

N

Example 1:

SUBWF

REG, 1, 0

Before Instruction

Example 3:

SUBLW 02h

REG

W

C

=

3

2

?

Before Instruction

=

W

C

=

03h

?

After Instruction

REG

W

C

=

1

2

1

0

W

C

Z

=

FFh ; (2’s complement)

=

0

1

; result is negative

; result is positive

Z

N

Example 2:

SUBWF

REG, 0, 0

Before Instruction

REG

W

=

2

?

C

After Instruction

REG

W

C

=

2

0

1

0

=

; result is zero

Z

N

Example 3:

Before Instruction

SUBWF

REG, 1, 0

REG

W

=

1

2

?

C

After Instruction

REG

W

C

=

FFh ;(2’s complement)

2

0

1

=

; result is negative

Z

N

 2009-2016 Microchip Technology Inc.

DS40001365F-page 301

PIC18(L)F1XK22

SUBWFB

Subtract W from f with Borrow

SWAPF

Swap f

SUBWFB f {,d {,a}}

Syntax:

SWAPF f {,d {,a}}

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(f) – (W) – (C) dest

Operation:

(f<3:0>)  dest<7:4>,

(f<7:4>)  dest<3:0>

Status Affected:

Encoding:

N, OV, C, DC, Z

0101

10da

ffff

Status Affected:

Encoding:

None

Description:

Subtract W and the CARRY flag

0011

10da

ffff

(borrow) from register ‘f’ (2’s comple-

ment method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Description:

The upper and lower nibbles of register

‘f’ are exchanged. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example 1:

SUBWFB REG, 1, 0

Before Instruction

REG

W

=

19h

0Dh

1

(0001 1001)

(0000 1101)

Example:

SWAPF

REG, 1, 0

C

Before Instruction

After Instruction

REG

=

53h

35h

REG

=

0Ch

0Dh

1

(0000 1011)

(0000 1101)

After Instruction

W

=

REG

=

C

Z

0

N

0

; result is positive

Example 2:

SUBWFB REG, 0, 0

Before Instruction

REG

W

=

1Bh

1Ah

0

(0001 1011)

(0001 1010)

C

After Instruction

REG

W

C

=

1Bh

00h

1

(0001 1011)

=

Z

1

; result is zero

N

0

Example 3:

Before Instruction

SUBWFB REG, 1, 0

REG

=

03h

0Eh

1

(0000 0011)

(0000 1101)

W

C

After Instruction

REG

=

F5h

(1111 0100)

; [2’s comp]

W

=

0Eh

0

1

(0000 1101)

C

Z

N

; result is negative

DS40001365F-page 302

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TBLRD

Table Read

TBLRD

Table Read (Continued)

Syntax:

TBLRD ( *; *+; *-; +*)

None

Example1:

TBLRD *+ ;

Operands:

Operation:

Before Instruction

TABLAT

TBLPTR

MEMORY (00A356h)

=

55h

00A356h

34h

if TBLRD *,

(Prog Mem (TBLPTR))  TABLAT;

TBLPTR – No Change;

if TBLRD *+,

(Prog Mem (TBLPTR))  TABLAT;

(TBLPTR) + 1  TBLPTR;

if TBLRD *-,

(Prog Mem (TBLPTR))  TABLAT;

(TBLPTR) – 1  TBLPTR;

if TBLRD +*,

(TBLPTR) + 1  TBLPTR;

(Prog Mem (TBLPTR))  TABLAT;

After Instruction

TABLAT

TBLPTR

=

34h

00A357h

Example2:

TBLRD +* ;

Before Instruction

TABLAT

TBLPTR

MEMORY (01A357h)

MEMORY (01A358h)

After Instruction

=

AAh

01A357h

12h

34h

TABLAT

TBLPTR

=

34h

01A358h

Status Affected: None

Encoding:

0000

10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description:

This instruction is used to read the contents

of Program Memory (P.M.). To address the

program memory, a pointer called Table

Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range.

TBLPTR[0] = 0: LeastSignificantByte

of Program Memory

Word

TBLPTR[0] = 1: Most Significant Byte

of Program Memory

Word

The TBLRDinstruction can modify the value

of TBLPTR as follows:

•

no change

post-increment

post-decrement

pre-increment

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

No

No operation

No

No operation

operation (Read Program operation (Write TABLAT)

Memory)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 303

PIC18(L)F1XK22

TBLWT

Table Write

TBLWT

Table Write (Continued)

Syntax:

TBLWT ( *; *+; *-; +*)

None

Example1:

TBLWT *+;

Operands:

Operation:

Before Instruction

if TBLWT*,

TABLAT

TBLPTR

HOLDING REGISTER

(00A356h)

=

55h

00A356h

(TABLAT)  Holding Register;

TBLPTR – No Change;

if TBLWT*+,

(TABLAT)  Holding Register;

(TBLPTR) + 1  TBLPTR;

if TBLWT*-,

(TABLAT)  Holding Register;

(TBLPTR) – 1  TBLPTR;

if TBLWT+*,

(TBLPTR) + 1  TBLPTR;

(TABLAT)  Holding Register;

=

FFh

After Instructions (table write completion)

TABLAT

TBLPTR

HOLDING REGISTER

(00A356h)

=

55h

00A357h

=

55h

Example 2:

TBLWT +*;

Before Instruction

TABLAT

TBLPTR

HOLDING REGISTER

(01389Ah)

HOLDING REGISTER

(01389Bh)

=

34h

01389Ah

Status Affected: None

=

FFh

Encoding:

0000

11nn

nn=0 *

=1 *+

=2 *-

=3 +*

=

FFh

After Instruction (table write completion)

TABLAT

TBLPTR

HOLDING REGISTER

(01389Ah)

HOLDING REGISTER

(01389Bh)

=

34h

01389Bh

Description:

This instruction uses the 3 LSBs of

TBLPTR to determine which of the

eight holding registers the TABLAT is writ-

ten to. The holding registers are used to

program the contents of Program

Memory (P.M.). (Refer to Section 4.0

“Flash Program Memory” for additional

details on programming Flash memory.)

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory.

TBLPTR has a 2-MByte address range.

The LSb of the TBLPTR selects which

byte of the program memory location to

access.

=

FFh

34h

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

•

no change

post-increment

post-decrement

pre-increment

Words:

1

2

Cycles:

Q Cycle Activity:

Q1

Q2

No

Q3

No

Q4

No

Decode

operation operation operation

No

No No No

operation operation operation operation

(Read

TABLAT)

(Write to

Holding

Register )

DS40001365F-page 304

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PIC18(L)F1XK22

TSTFSZ

Test f, skip if 0

XORLW

Exclusive OR literal with W

Syntax:

TSTFSZ f {,a}

Syntax:

XORLW k

Operands:

0  f  255

a  [0,1]

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 k 255

(W) .XOR. k W

N, Z

Operation:

skip if f = 0

Status Affected:

Encoding:

None

0000

1010

kkkk

0110

011a

ffff

The contents of W are XORed with

the 8-bit literal ‘k’. The result is placed

in W.

Description:

If ‘f’ = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOPis executed,

making this a 2-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

XORLW

0AFh

Before Instruction

W

=

B5h

1Ah

Words:

Cycles:

1

After Instruction

1(2)

W

=

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

No

operation

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

Example:

HERE

NZERO

ZERO

TSTFSZ CNT, 1

:

Before Instruction

PC

=

Address (HERE)

After Instruction

If CNT

PC

If CNT

PC

=



=

00h,

Address (ZERO)

00h,

Address (NZERO)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 305

PIC18(L)F1XK22

XORWF

Exclusive OR W with f

Syntax:

XORWF f {,d {,a}}

Operands:

0  f  255

d  [0,1]

a  [0,1]

Operation:

(W) .XOR. (f) dest

Status Affected:

Encoding:

N, Z

0001

10da

ffff

Description:

Exclusive OR the contents of W with

register ‘f’. If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in the register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

XORWF

REG, 1, 0

Before Instruction

REG

W

=

AFh

B5h

After Instruction

REG

W

=

1Ah

B5h

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PIC18(L)F1XK22

A summary of the instructions in the extended

instruction set is provided in Table 24-3. Detailed

descriptions are provided in Section 24.2.2

“Extended Instruction Set”. The opcode field

descriptions in Table 24-1 (page 266) apply to both the

standard and extended PIC18 instruction sets.

24.2 Extended Instruction Set

In addition to the standard 75 instructions of the PIC18

instruction set, PIC18(L)F1XK22 devices also provide

an optional extension to the core CPU functionality.

The added features include eight additional

instructions that augment indirect and indexed

addressing operations and the implementation of

Indexed Literal Offset Addressing mode for many of the

standard PIC18 instructions.

Note:

The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applications

written in C; the user may likely never use

these instructions directly in assembler.

The syntax for these commands is

provided as a reference for users who

may be reviewing code that has been

generated by a compiler.

The additional features of the extended instruction set

are disabled by default. To enable them, users must set

the XINST Configuration bit.

The instructions in the extended set can all be

classified as literal operations, which either manipulate

the File Select Registers, or use them for indexed

addressing. Two of the instructions, ADDFSR and

SUBFSR, each have an additional special instantiation

for using FSR2. These versions (ADDULNK and

SUBULNK) allow for automatic return after execution.

24.2.1

EXTENDED INSTRUCTION SYNTAX

Most of the extended instructions use indexed

arguments, using one of the File Select Registers and

some offset to specify a source or destination register.

When an argument for an instruction serves as part of

indexed addressing, it is enclosed in square brackets

(“[ ]”). This is done to indicate that the argument is used

as an index or offset. MPASM™ Assembler will flag an

error if it determines that an index or offset value is not

bracketed.

The extended instructions are specifically implemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things, they allow users working in high-level

languages to perform certain operations on data

structures more efficiently. These include:

When the extended instruction set is enabled, brackets

are also used to indicate index arguments in byte-

oriented and bit-oriented instructions. This is in addition

to other changes in their syntax. For more details, see

Section 24.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”.

• Dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

• Function pointer invocation

• Software Stack Pointer manipulation

• Manipulation of variables located in a software

stack

Note:

In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text and going forward, optional

arguments are denoted by braces (“{ }”).

TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

16-Bit Instruction Word

MSb LSb

Mnemonic,

Operands

Status

Affected

Description

Cycles

ADDFSR

ADDULNK

CALLW

f, k

k

Add literal to FSR

Add literal to FSR2 and return

Call subroutine using WREG

1

2

1110 1000 ffkk kkkk

1110 1000 11kk kkkk

0000 0000 0001 0100

1110 1011 0zzz zzzz

1111 ffff ffff ffff

1110 1011 1zzz zzzz

1111 xxxx xzzz zzzz

1110 1010 kkkk kkkk

None

MOVSF

z_s, f_dMove z_s(source) to 1st word

f_d(destination) 2nd word

z_s, z_dMove z_s(source) to 1st word

MOVSS

PUSHL

2

1

None

z_d(destination)

Store literal at FSR2,

decrement FSR2

2nd word

k

SUBFSR

SUBULNK

f, k

k

Subtract literal from FSR

Subtract literal from FSR2 and

return

1

2

1110 1001 ffkk kkkk

1110 1001 11kk kkkk

None

 2009-2016 Microchip Technology Inc.

DS40001365F-page 307

PIC18(L)F1XK22

24.2.2

EXTENDED INSTRUCTION SET

ADDFSR

Add Literal to FSR

ADDULNK

Add Literal to FSR2 and Return

Syntax:

ADDFSR f, k

Syntax:

ADDULNK k

Operands:

0  k  63

f  [ 0, 1, 2 ]

Operands:

Operation:

0  k  63

FSR2 + k  FSR2,

(TOS) PC

None

Operation:

FSR(f) + k  FSR(f)

Status Affected:

Encoding:

None

Status Affected:

Encoding:

1110

1000

ffkk

kkkk

1110

1000

11kk

kkkk

Description:

The 6-bit literal ‘k’ is added to the

contents of the FSR specified by ‘f’.

Description:

The 6-bit literal ‘k’ is added to the

contents of FSR2. A RETURNis then

executed by loading the PC with the

TOS.

Words:

1

Cycles:

The instruction takes two cycles to

execute; a NOPis performed during

the second cycle.

This may be thought of as a special

case of the ADDFSRinstruction,

where f = 3 (binary ‘11’); it operates

only on FSR2.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to

FSR

ADDFSR 2, 23h

Example:

Words:

Cycles:

1

2

Before Instruction

FSR2

After Instruction

FSR2

=

03FFh

0422h

Q Cycle Activity:

Q1

=

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to

FSR

No

Operation

ADDULNK 23h

Example:

Before Instruction

FSR2

PC

=

03FFh

0100h

After Instruction

FSR2

PC

=

0422h

(TOS)

Note:

All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

DS40001365F-page 308

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PIC18(L)F1XK22

CALLW

Subroutine Call Using WREG

MOVSF

Move Indexed to f

Syntax:

CALLW

None

Syntax:

MOVSF [z ], f

s

d

Operands:

Operation:

Operands:

0  z  127

s

0  f  4095

d

(PC + 2)  TOS,

(W)  PCL,

Operation:

((FSR2) + z )  f

s

d

(PCLATH)  PCH,

(PCLATU)  PCU

Status Affected:

None

Encoding:

1st word (source)

2nd word (destin.)

Status Affected:

Encoding:

None

1110

1111

1011

ffff

0zzz

ffff

zzzz

ffff

s

0000

0001

0100

d

Description

First, the return address (PC + 2) is

pushed onto the return stack. Next, the

contents of W are written to PCL; the

existing value is discarded. Then, the

contents of PCLATH and PCLATU are

latched into PCH and PCU,

respectively. The second cycle is

executed as a NOPinstruction while the

new next instruction is fetched.

Description:

The contents of the source register are

moved to destination register ‘f ’. The

d

actual address of the source register is

determined by adding the 7-bit literal

offset ‘z ’ in the first word to the value of

s

FSR2. The address of the destination

register is specified by the 12-bit literal

‘f ’ in the second word. Both addresses

d

can be anywhere in the 4096-byte data

space (000h to FFFh).

The MOVSFinstruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h.

Unlike CALL, there is no option to

update W, Status or BSR.

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Words:

Cycles:

2

Decode

Read

WREG

PUSH PC to

stack

No

operation

No

operation

No

operation

No

operation

No

operation

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Determine

Read

source addr source addr source reg

Example:

HERE

CALLW

Decode

No

operation

No

operation

Write

register ‘f’

(dest)

Before Instruction

PC

=

address (HERE)

PCLATH =

PCLATU =

10h

00h

06h

No dummy

read

W

=

After Instruction

PC

=

001006h

Example:

MOVSF

[05h], REG2

TOS

=

address (HERE + 2)

PCLATH =

PCLATU =

W

10h

00h

06h

Before Instruction

FSR2

=

80h

33h

=

Contents

of 85h

REG2

=

11h

After Instruction

FSR2

=

80h

Contents

of 85h

REG2

=

33h

 2009-2016 Microchip Technology Inc.

DS40001365F-page 309

PIC18(L)F1XK22

MOVSS

Move Indexed to Indexed

PUSHL

Store Literal at FSR2, Decrement FSR2

Syntax:

MOVSS [z ], [z ]

Syntax:

PUSHL k

s

d

Operands:

0  z  127

s

Operands:

Operation:

0k  255

0  z  127

d

k  (FSR2),

FSR2 – 1  FSR2

Operation:

((FSR2) + z )  ((FSR2) + z )

s d

Status Affected:

None

Status Affected: None

Encoding:

1st word (source)

2nd word (dest.)

Encoding:

1110

1010

kkkk

1110

1111

1011

xxxx

1zzz

xzzz

zzzz

s

d

Description:

The 8-bit literal ‘k’ is written to the data

memory address specified by FSR2. FSR2

is decremented by 1 after the operation.

This instruction allows users to push values

onto a software stack.

Description

The contents of the source register are

moved to the destination register. The

addresses of the source and destination

registers are determined by adding the

7-bit literal offsets ‘z ’ or ‘z ’,

Words:

Cycles:

1

s

d

respectively, to the value of FSR2. Both

registers can be located anywhere in

the 4096-byte data memory space

(000h to FFFh).

Q Cycle Activity:

Q1

Q2

Q3

Q4

The MOVSSinstruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Decode

Read ‘k’

Process

data

Write to

destination

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h. If the

resultant destination address points to

an indirect addressing register, the

instruction will execute as a NOP.

Example:

PUSHL 08h

Before Instruction

FSR2H:FSR2L

Memory (01ECh)

=

01ECh

00h

Words:

2

After Instruction

FSR2H:FSR2L

Memory (01ECh)

=

01EBh

08h

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Determine

Read

source addr source addr source reg

Decode

Determine

dest addr

Determine

dest addr

Write

to dest reg

Example:

MOVSS [05h], [06h]

Before Instruction

FSR2

=

80h

33h

11h

Contents

of 85h

Contents

of 86h

After Instruction

FSR2

=

80h

33h

Contents

of 85h

Contents

of 86h

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PIC18(L)F1XK22

SUBFSR

Subtract Literal from FSR

SUBULNK

Subtract Literal from FSR2 and Return

Syntax:

SUBFSR f, k

0  k  63

Syntax:

SUBULNK k

Operands:

Operation:

0  k  63

f  [ 0, 1, 2 ]

FSR(f) – k  FSRf

None

FSR2 – k  FSR2

(TOS) PC

Operation:

Status Affected:

Encoding:

Status Affected: None

1110

1001

ffkk

kkkk

Encoding:

1110

1001

11kk

kkkk

Description:

The 6-bit literal ‘k’ is subtracted from

the contents of the FSR specified by

‘f’.

Description:

The 6-bit literal ‘k’ is subtracted from the

contents of the FSR2. A RETURNis then

executed by loading the PC with the TOS.

The instruction takes two cycles to

execute; a NOPis performed during the

second cycle.

This may be thought of as a special case of

the SUBFSRinstruction, where f = 3 (binary

‘11’); it operates only on FSR2.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Words:

1

2

Cycles:

Q Cycle Activity:

Q1

Example:

SUBFSR 2, 23h

03FFh

Q2

Q3

Q4

Before Instruction

FSR2

After Instruction

FSR2

Decode

Read

register ‘f’

Process

Data

Write to

destination

=

No

Operation

No

Operation

No

Operation

No

Operation

=

03DCh

Example:

SUBULNK 23h

Before Instruction

FSR2

PC

=

03FFh

0100h

After Instruction

FSR2

PC

=

03DCh

(TOS)

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PIC18(L)F1XK22

24.2.3

BYTE-ORIENTED AND

BIT-ORIENTED INSTRUCTIONS IN

INDEXED LITERAL OFFSET MODE

24.2.3.1

Extended Instruction Syntax with

Standard PIC18 Commands

When the extended instruction set is enabled, the file

register argument, ‘f’, in the standard byte-oriented and

bit-oriented commands is replaced with the literal offset

value, ‘k’. As already noted, this occurs only when ‘f’ is

less than or equal to 5Fh. When an offset value is used,

it must be indicated by square brackets (“[ ]”). As with

the extended instructions, the use of brackets indicates

to the compiler that the value is to be interpreted as an

index or an offset. Omitting the brackets, or using a

value greater than 5Fh within brackets, will generate an

error in the MPASM™ assembler.

Note: Enabling the PIC18 instruction set

extension may cause legacy applications

to behave erratically or fail entirely.

In addition to eight new commands in the extended set,

enabling the extended instruction set also enables

Indexed Literal Offset Addressing mode (Section 3.5.1

“Indexed Addressing with Literal Offset”). This has

a significant impact on the way that many commands of

the standard PIC18 instruction set are interpreted.

When the extended set is disabled, addresses

embedded in opcodes are treated as literal memory

locations: either as a location in the Access Bank (‘a’ =

0), or in a GPR bank designated by the BSR (‘a’ = 1).

When the extended instruction set is enabled and ‘a’ =

0, however, a file register argument of 5Fh or less is

interpreted as an offset from the pointer value in FSR2

and not as a literal address. For practical purposes, this

means that all instructions that use the Access RAM bit

as an argument – that is, all byte-oriented and bit-

oriented instructions, or almost half of the core PIC18

instructions – may behave differently when the

extended instruction set is enabled.

If the index argument is properly bracketed for Indexed

Literal Offset Addressing, the Access RAM argument is

never specified; it will automatically be assumed to be

‘0’. This is in contrast to standard operation (extended

instruction set disabled) when ‘a’ is set on the basis of

the target address. Declaring the Access RAM bit in

this mode will also generate an error in the MPASM

assembler.

The destination argument, ‘d’, functions as before.

In the latest versions of the MPASM assembler,

language support for the extended instruction set must

be explicitly invoked. This is done with either the

command line option, /y, or the PE directive in the

source listing.

When the content of FSR2 is 00h, the boundaries of the

Access RAM are essentially remapped to their original

values. This may be useful in creating backward

compatible code. If this technique is used, it may be

necessary to save the value of FSR2 and restore it

when moving back and forth between C and assembly

routines in order to preserve the Stack Pointer. Users

must also keep in mind the syntax requirements of the

extended instruction set (see Section 24.2.3.1

“Extended Instruction Syntax with Standard PIC18

Commands”).

24.2.4

CONSIDERATIONS WHEN

ENABLING THE EXTENDED

INSTRUCTION SET

It is important to note that the extensions to the

instruction set may not be beneficial to all users. In

particular, users who are not writing code that uses a

software stack may not benefit from using the

extensions to the instruction set.

Although the Indexed Literal Offset Addressing mode

can be very useful for dynamic stack and pointer

manipulation, it can also be very annoying if a simple

arithmetic operation is carried out on the wrong

register. Users who are accustomed to the PIC18

programming must keep in mind that, when the

extended instruction set is enabled, register addresses

of 5Fh or less are used for Indexed Literal Offset

Addressing.

Additionally, the Indexed Literal Offset Addressing

mode may create issues with legacy applications

written to the PIC18 assembler. This is because

instructions in the legacy code may attempt to address

registers in the Access Bank below 5Fh. Since these

addresses are interpreted as literal offsets to FSR2

when the instruction set extension is enabled, the

application may read or write to the wrong data

addresses.

Representative examples of typical byte-oriented and

bit-oriented instructions in the Indexed Literal Offset

Addressing mode are provided on the following page to

show how execution is affected. The operand

conditions shown in the examples are applicable to all

instructions of these types.

When porting an application to the PIC18(L)F1XK22, it

is very important to consider the type of code. A large,

re-entrant application that is written in ‘C’ and would

benefit from efficient compilation will do well when

using the instruction set extensions. Legacy

applications that heavily use the Access Bank will most

likely not benefit from using the extended instruction

set.

DS40001365F-page 312

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PIC18(L)F1XK22

ADD W to Indexed

(Indexed Literal Offset mode)

Bit Set Indexed

(Indexed Literal Offset mode)

ADDWF

BSF

Syntax:

ADDWF

[k] {,d}

Syntax:

BSF [k], b

Operands:

0  k  95

d  [0,1]

Operands:

0  f  95

0  b  7

Operation:

(W) + ((FSR2) + k)  dest

Operation:

1  ((FSR2) + k)

Status Affected:

Encoding:

N, OV, C, DC, Z

Status Affected:

Encoding:

None

1000

0010

01d0

kkkk

bbb0

kkkk

Description:

The contents of W are added to the

contents of the register indicated by

FSR2, offset by the value ‘k’.

If ‘d’ is ‘0’, the result is stored in W. If ‘d’

is ‘1’, the result is stored back in

register ‘f’ (default).

Description:

Bit ‘b’ of the register indicated by FSR2,

offset by the value ‘k’, is set.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Q Cycle Activity:

Q1

Q2

Q3

Q4

Example:

BSF

[FLAG_OFST], 7

Decode

Read ‘k’

Process

Data

Write to

destination

Before Instruction

FLAG_OFST

FSR2

Contents

of 0A0Ah

=

0Ah

0A00h

Example:

ADDWF

[OFST], 0

=

55h

D5h

Before Instruction

After Instruction

W

OFST

FSR2

=

17h

2Ch

0A00h

Contents

of 0A0Ah

=

Contents

of 0A2Ch

=

20h

After Instruction

W

=

37h

20h

Set Indexed

(Indexed Literal Offset mode)

Contents

of 0A2Ch

SETF

Syntax:

SETF [k]

Operands:

Operation:

Status Affected:

Encoding:

Description:

0  k  95

FFh  ((FSR2) + k)

None

0110

1000

kkkk

The contents of the register indicated by

FSR2, offset by ‘k’, are set to FFh.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read ‘k’

Process

Data

Write

register

Example:

SETF

[OFST]

2Ch

Before Instruction

OFST

=

FSR2

0A00h

Contents

of 0A2Ch

=

00h

After Instruction

Contents

of 0A2Ch

=

FFh

 2009-2016 Microchip Technology Inc.

DS40001365F-page 313

PIC18(L)F1XK22

24.2.5

SPECIAL CONSIDERATIONS WITH

MICROCHIP MPLAB^®IDE TOOLS

The latest versions of Microchip’s software tools have

been designed to fully support the extended instruction

set of the PIC18(L)F1XK22 family of devices. This

includes the MPLAB^®C18 C compiler, MPASM

assembly

language

and

MPLAB

Integrated

Development Environment (IDE).

When selecting target device for software

a

development, MPLAB IDE will automatically set default

Configuration bits for that device. The default setting for

the XINST Configuration bit is ‘0’, disabling the

extended instruction set and Indexed Literal Offset

Addressing mode. For proper execution of applications

developed to take advantage of the extended

instruction set, XINST must be set during

programming.

To develop software for the extended instruction set,

the user must enable support for the instructions and

the Indexed Addressing mode in their language tool(s).

Depending on the environment being used, this may be

done in several ways:

• A menu option, or dialog box within the

environment, that allows the user to configure the

language tool and its settings for the project

• A command line option

• A directive in the source code

These options vary between different compilers,

assemblers and development environments. Users are

encouraged to review the documentation accompanying

their development systems for the appropriate

information.

DS40001365F-page 314

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PIC18(L)F1XK22

25.1 MPLAB X Integrated Development

Environment Software

25.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers (MCU) and dsPIC^®digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

hardware development tool that runs on Windows^®,

Linux and Mac OS^®X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

• Integrated Development Environment

- MPLAB^®X IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

• Simulators

- MPLAB X SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

Feature-Rich Editor:

- PICkit™ 3

• Color syntax highlighting

• Device Programmers

- MPLAB PM3 Device Programmer

• Smart code completion makes suggestions and

provides hints as you type

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Automatic code formatting based on user-defined

rules

• Third-party development tools

• Live parsing

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker

 2009-2016 Microchip Technology Inc.

DS40001365F-page 315

PIC18(L)F1XK22

25.2 MPLAB XC Compilers

25.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16, and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other

relocatable object files and archives to create an

executable file. MPLAB XC Compiler uses the

assembler to produce its object file. Notable features of

the assembler include:

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

25.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

25.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multipurpose

source files

• Directives that allow complete control over the

assembly process

DS40001365F-page 316

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PIC18(L)F1XK22

25.6 MPLAB X SIM Software Simulator

25.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB X SIM Software Simulator allows code

development in

a

PC-hosted environment by

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

simulating the PIC MCUs and dsPIC DSCs on an

instruction level. On any given instruction, the data

areas can be examined or modified and stimuli can be

applied from a comprehensive stimulus controller.

Registers can be logged to files for further run-time

analysis. The trace buffer and logic analyzer display

extend the power of the simulator to record and track

program execution, actions on I/O, most peripherals

and internal registers.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The

software simulator offers the flexibility to develop and

debug code outside of the hardware laboratory

environment, making it an excellent, economical

software development tool.

25.9 PICkit 3 In-Circuit Debugger/

Programmer

The MPLAB PICkit

3

allows debugging and

programming of PIC and dsPIC Flash microcontrollers

at a most affordable price point using the powerful

graphical user interface of the MPLAB IDE. The

MPLAB PICkit 3 is connected to the design engineer’s

PC using a full-speed USB interface and can be

connected to the target via a Microchip debug (RJ-11)

connector (compatible with MPLAB ICD 3 and MPLAB

REAL ICE). The connector uses two device I/O pins

and the Reset line to implement in-circuit debugging

and In-Circuit Serial Programming™ (ICSP™).

25.7 MPLAB REAL ICE In-Circuit

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

25.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a

modular, detachable socket assembly to support

various package types. The ICSP cable assembly is

included as a standard item. In Stand-Alone mode, the

MPLAB PM3 Device Programmer can read, verify and

program PIC devices without a PC connection. It can

also set code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.

The emulator is field upgradable through future firmware

downloads in MPLAB X IDE. MPLAB REAL ICE offers

significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 317

PIC18(L)F1XK22

25.11 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

25.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide

application firmware and source code for examination

and modification.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

• Demonstration Boards from companies, such as

MikroElektronika, Digilent^®and Olimex

• Embedded Ethernet Solutions from companies,

such as EZ Web Lynx, WIZnet and IPLogika^®

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has

a

line of evaluation kits and

demonstration software for analog filter design,

®

KEELOQ security ICs, CAN, IrDA^®, PowerSmart

battery management, SEEVAL^®evaluation system,

Sigma-Delta ADC, flow rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS40001365F-page 318

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PIC18(L)F1XK22

26.0 ELECTRICAL SPECIFICATIONS

(†)

26.1 Absolute Maximum Ratings

Ambient temperature under bias...................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on pins with respect to VSS

on VDD pin

PIC18F1XK22 ........................................................................................................... -0.3V to +6.5V

PIC18LF1XK22 ......................................................................................................... -0.3V to +4.0V

on MCLR pin ........................................................................................................................... -0.3V to +9.0V

on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)

Maximum current⁽¹⁾

on VSS pin

-40°C  TA  +85°C, Industrial ............................................................................................. 250 mA

-40°C  TA  +125°C, Extended ............................................................................................. 85 mA

on VDD pin

-40°C  TA  +85°C,Industrial .............................................................................................. 250 mA

-40°C  TA  +125°C, Extended ............................................................................................. 85 mA

sunk by all ports................................................................................................................................... 250 mA

sourced by all ports ............................................................................................................................. 250 mA

Maximum output current

sunk by any I/O pin.............................................................................................................................. 50 mA

sourced by any I/O pin ....................................................................................................................... 50 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA

Total power dissipation⁽²⁾...............................................................................................................................800 mW

Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be

limited by the device package power dissipation characterizations, see Table 26-8 to calculate device

specifications.

2: Power dissipation is calculated as follows:

PDIS = VDD x {IDD – ΣIOH} + Σ{VDD – VOH) x IOH} + Σ(VOL x IOI).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 319

PIC18(L)F1XK22

26.2 Standard Operating Conditions

The standard operating conditions for any device are defined as:

Operating Voltage:

Operating Temperature:

VDDMIN VDD VDDMAX

TA_MIN TA TA_MAX

VDD — Operating Supply Voltage⁽¹⁾

PIC18LF1XK22

VDDMIN (Fosc  16 MHz).......................................................................................................... +1.8V

VDDMIN (Fosc  20 MHz).......................................................................................................... +2.0V

VDDMIN (Fosc  64 MHz).......................................................................................................... +3.0V

VDDMAX .................................................................................................................................... +3.6V

PIC18F1XK22

VDDMIN (Fosc  20 MHz).......................................................................................................... +2.3V

VDDMIN (Fosc  64 MHz).......................................................................................................... +3.0V

VDDMAX .................................................................................................................................... +5.5V

TA — Operating Ambient Temperature Range

Industrial Temperature

TA_MIN ...................................................................................................................................... -40°C

TA_MAX .................................................................................................................................... +85°C

Extended Temperature

TA_MIN ...................................................................................................................................... -40°C

TA_MAX .................................................................................................................................. +125°C

Note 1: See Parameter D001, DC Characteristics: Supply Voltage.

DS40001365F-page 320

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 26-1:

PIC18F1XK22 VOLTAGE FREQUENCY GRAPH, -40°C TA +85°C

5.5

3.6

3.0

2.3

0

10

20

40

48

64

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 26-13 for each Oscillator mode’s supported frequencies.

FIGURE 26-2:

PIC18F1XK22 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C

5.5

3.6

3.0

2.3

0

10

20

40

48

64

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 26-13 for each Oscillator mode’s supported frequencies.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 321

PIC18(L)F1XK22

FIGURE 26-3:

PIC18LF1XK22 VOLTAGE FREQUENCY GRAPH, -40°C TA +85°C

3.6

3.0

2.0

1.8

0

10

20

40

48

16

64

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 26-13 for each Oscillator mode’s supported frequencies.

FIGURE 26-4:

PIC18LF1XK22 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C

3.6

3.0

2.0

1.8

16

0

10

20

40

48

64

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 26-13 for each Oscillator mode’s supported frequencies.

DS40001365F-page 322

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 26-5:

HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

± 5%

± 3%

85

60

25

± 2%

0

-20

± 5%

-40

1.8

2.0

2.5

3.5

4.0

VDD (V)

4.5

5.0

5.5

3.0

 2009-2016 Microchip Technology Inc.

DS40001365F-page 323

PIC18(L)F1XK22

26.3 DC Characteristics

TABLE 26-1: SUPPLY VOLTAGE

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

PIC18F1XK22

Param.

No.

Sym.

Characteristic

Supply Voltage

Min. Typ.† Max. Units

Conditions

D001

VDD

PIC18LF1XK22

1.8

2.0

3.0

—

3.6

V

FOSC  16 MHz

FOSC 20 MHz

FOSC  64 MHz  85°C

FOSC  48 MHz  125°C

D001

PIC18F1XK22

2.3

3.0

—

5.5

V

FOSC  20 MHz

FOSC  64 MHz  85°C

FOSC  48 MHz  125°C

(1)

D002*

VDR

RAM Data Retention Voltage

PIC18LF1XK22

1.5

1.7

—

V

Device in Sleep mode

PIC18F1XK22

VPOR*

Power-on Reset Release Voltage

1.6

0.8

—

V

VPORR* Power-on Reset Rearm Voltage

—

V

D004*

SVDD

VDD Rise Rate to ensure internal

0.05

V/ms

Power-on Reset signal

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

DS40001365F-page 324

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 26-6:

POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR

POR REARM

VSS

(3)

(2)

TPOR

TVLOW

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 325

PIC18(L)F1XK22

TABLE 26-2: RC RUN SUPPLY CURRENT

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

PIC18F1XK22

Param.

Standard Operating Conditions (unless otherwise stated)

Device Characteristics

Typ.

Max. Units

Conditions

No.

(1, 2, 4, 5)

D008

6

7

9

A

mA

-40°C

+25°C

Supply Current (IDD)

10

14

17

15

16

25

28

45

48

50

55

50

55

60

75

55

60

65

80

0.5

VDD = 1.8V

8

+85°C

(4)

FOSC = 31 kHz

11

12

13

17

22

23

25

28

25

27

30

32

30

33

37

40

0.4

+125°C

-40°C

(RC_RUN mode,

LFINTOSC source)

D008A

D008

+25°C

VDD = 3.0V

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

-40°C

D008A

D008B

(4)

FOSC = 31 kHz

+25°C

(RC_RUN mode,

LFINTOSC source)

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

-40°C to +125°C

D009

VDD = 1.8V

VDD = 3.0V

FOSC = 1 MHz

(RC_RUN mode,

HFINTOSC source)

D009A

0.6

0.8

mA

-40°C to +125°C

D009

0.45

0.60

0.80

1.9

0.55

0.82

1.0

mA

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

VDD = 1.8V

FOSC = 1 MHz

(RC_RUN mode,

HFINTOSC source)

D009A

D009B

D010

2.5

FOSC = 16 MHz

(RC_RUN mode,

HF-INTOSC source)

D010A

4.4

-40°C to +125°C

VDD = 3.0V

3.5

mA

D010

D010A

D010B

*

3.5

4.6

4.7

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

2.4

3.5

3.7

mA

FOSC = 16 MHz

(RC_RUN mode,

HF-INTOSC source)

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.

5: When a single temperature range is provided for a parameter, the specification applies to both industrial and extended

temperature devices.

DS40001365F-page 326

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-3: RC IDLE SUPPLY CURRENT

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

PIC18F1XK22

Param.

Standard Operating Conditions (unless otherwise stated)

Device Characteristics

Typ.

Max. Units

Conditions

No.

(1, 2, 4, 5)

D011

2

5

6

A

mA

-40°C

+25°C

Supply Current (IDD)

VDD = 1.8V

3

9

+85°C

(4)

FOSC = 31 kHz

8

11

8

+125°C

-40°C

(RC_IDLE mode,

LFINTOSC source)

D011A

D011

4

10

13

15

28

35

41

50

35

40

46

65

43

48

51

71

0.45

+25°C

VDD = 3.0V

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

5

+85°C

8

+125°C

-40°C

20

21

23

24

23

25

28

30

28

30

32

33

0.30

+25°C

+85°C

+125°C

-40°C

D011A

D011B

(4)

FOSC = 31 kHz

+25°C

(RC_IDLE mode,

LFINTOSC source)

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

-40°C to +125°C

D012

VDD = 1.8V

VDD = 3.0V

FOSC = 1 MHz

(RC_IDLE mode,

HF-INTOSC source)

D012A

0.60

-40°C to +125°C

0.45

mA

D012

0.45

0.62

0.78

1.20

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

VDD = 1.8V

0.32

0.47

0.63

0.89

mA

FOSC = 1 MHz

(RC_IDLE mode,

HF-INTOSC source)

D012A

D012B

D013

FOSC = 16 MHz

(RC_IDLE mode,

HF-INTOSC source)

D013A

2.00

-40°C to +125°C

VDD = 3.0V

1.45

mA

D013

D013A

D013B

*

1.50

2.00

2.20

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

1.10

1.45

1.53

mA

FOSC = 16 MHz

(RC_IDLE mode,

HF-INTOSC source)

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.

5: When a single temperature range is provided for a parameter, the specification applies to both industrial and extended

temperature devices.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 327

PIC18(L)F1XK22

TABLE 26-4: PRIMARY RUN SUPPLY CURRENT

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

PIC18F1XK22

Param.

Standard Operating Conditions (unless otherwise stated)

Device Characteristics

Typ. Max. Units

Conditions

No.

(1, 2, 4, 5)

Supply Current (IDD)

D014

0.20 0.32

0.27 0.39

mA

-40°C to +125°C

VDD = 1.8V

VDD = 3.0V

FOSC = 1 MHz

(PRI_RUN,

EC Med Osc)

D014A

D014

.20

.27

.30

1.7

.32

.39

.42

2.6

mA

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

VDD = 1.8V

FOSC = 1 MHz

(PRI_RUN,

EC Med Osc)

D014A

D014B

D015

FOSC = 16 MHz

(PRI_RUN,

EC High Osc)

D015A

3.0

4.2

mA

-40°C to +125°C

VDD = 3.0V

D015

2.4

3.0

3.3

3.2

4.2

4.4

mA

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

FOSC = 16 MHz

(PRI_RUN,

EC High Osc)

D015A

D015B

D016

FOSC = 64 MHz

(PRI_RUN,

EC High Osc)

11.5

11.9

14.0

14.4

mA

-40°C to +125°C

VDD = 3.0V

D016

mA

-40°C to +125°C

VDD = 2.3V

VDD = 5.0V

VDD = 1.8V

VDD = 3.0V

FOSC = 64 MHz

(PRI_RUN,

EC High Osc)

D016A

12.1 14.6

D017

2.1

3.1

2.9

4.0

FOSC = 4 MHz

16 MHz Internal

(PRI_RUN HS+PLL)

D017A

D017

2.1

3.1

3.3

2.9

4.0

4.5

mA

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

FOSC = 4 MHz

16 MHz Internal

(PRI_RUN HS+PLL)

D017A

D017B

D018

FOSC = 16 MHz

64 MHz Internal

10

15

mA

-40°C to +125°C

VDD = 3.0V

(PRI_RUN HS+PLL)

D018

12.4 15.4

12.6 15.6

mA

-40°C to +125°C

VDD = 3.0V

VDD = 5.0V

FOSC = 16 MHz

64 MHz Internal

(PRI_RUN HS+PLL)

D018A

*

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact

on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be

extended by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.

5: When a single temperature range is provided for a parameter, the specification applies to both industrial and extended

temperature devices.

DS40001365F-page 328

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-5: PRIMARY IDLE SUPPLY CURRENT

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

PIC18F1XK22

Param.

Standard Operating Conditions (unless otherwise stated)

Device Characteristics

Typ. Max. Units

Conditions

No.

(1, 2, 4, 5)

D019

105

180

-40°C to +125°C

VDD = 1.8V

VDD = 3.0V

Supply Current (IDD)

70

A

FOSC = 1 MHz

(PRI_IDLE mode,

EC Med Osc)

D019A

140

D019

120

180

230

1.8

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

VDD = 1.8V

80

140

151

1.0

A

mA

FOSC = 1 MHz

(PRI_IDLE mode,

EC Med Osc)

D019A

D019B

D020

FOSC = 16 MHz

(PRI_IDLEmode,

EC High Osc)

D020A

2.0

-40°C to +125°C

VDD = 3.0V

1.2

mA

D020

1.8

2.0

2.1

-40°C to +125°C

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

1.0

1.2

1.4

mA

FOSC = 16 MHz

(PRI_IDLEmode,

EC High Osc)

D020A

D020B

D021

FOSC = 64 MHz

(PRI_IDLEmode,

EC High Osc)

7.0

-40°C to +125°C

VDD = 3.0V

5.0

mA

D021

6.2

6.3

-40°C to +125°C

VDD = 3.0V

VDD = 5.0V

5.2

5.3

mA

FOSC = 64 MHz

(PRI_IDLEmode,

EC High Osc)

D021A

*

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact

on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be

extended by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.

5: When a single temperature range is provided for a parameter, the specification applies to both industrial and extended

temperature devices.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 329

PIC18(L)F1XK22

TABLE 26-6: SECONDARY RUN SUPPLY CURRENT

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

PIC18F1XK22

Param.

Standard Operating Conditions (unless otherwise stated)

Device Characteristics

Typ. Max. Units

Conditions

No.

(1, 2, 4)

D022

6

9

A

-40°C

+25°C

+85°C

+125°C

-40°C

Supply Current (IDD)

6

10

14

17

15

16

25

28

65

67

69

75

70

72

74

77

75

77

79

83

VDD = 1.8V

7

(3)

FOSC = 32 kHz

11

12

26

22

23

25

28

25

27

30

32

30

32

34

35

(SEC_RUN mode,

Timer1 as clock)

D022A

D022

D022A

D022B

*

+25°C

+85°C

+125°C

-40°C

VDD = 3.0V

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

+25°C

+85°C

+125°C

-40°C

(3)

FOSC = 32 kHz

+25°C

+85°C

+125°C

-40°C

(SEC_RUN mode,

Timer1 as clock)

+25°C

+85°C

+125°C

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact

on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be

extended by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.

DS40001365F-page 330

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-7: SECONDARY IDLE SUPPLY CURRENT

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

PIC18F1XK22

Param.

Standard Operating Conditions (unless otherwise stated)

Device Characteristics

Typ. Max. Units

Conditions

No.

(1, 2, 4)

D023

2

5

A

-40°C

+25°C

+85°C

+125°C

-40°C

Supply Current (IDD)

2

5

VDD = 1.8V

3

9

(3)

FOSC = 32 kHz

8

11

8

(SEC_IDLE mode,

Timer1 as clock)

D023A

D023

D023A

D023B

*

4

5

10

20

23

40

41

44

47

45

47

49

52

50

54

59

62

+25°C

+85°C

+125°C

-40°C

VDD = 3.0V

VDD = 2.3V

VDD = 3.0V

VDD = 5.0V

9

20

21

23

24

23

25

28

30

28

30

32

33

+25°C

+85°C

+125°C

-40°C

(3)

FOSC = 32 kHz

+25°C

+85°C

+125°C

-40°C

(SEC_IDLE mode,

Timer1 as clock)

+25°C

+85°C

+125°C

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact

on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be

extended by the formula IR = VDD/2REXT (mA) with REXT in k

4: FVR and BOR are disabled.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 331

PIC18(L)F1XK22

TABLE 26-8: POWER-DOWN CURRENT

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

Standard Operating Conditions (unless otherwise stated)

PIC18F1XK22

Conditions

Note

Param.

No.

Max.

+85°C +125°C

Max.

Device Characteristics

Min.

Typ.†

Units

VDD

(2)

Power-down Base Current (IPD)

D027

—

0.034

0.071

17

1.0

2.0

40

9.0

10

55

65

80

A

1.8

3.0

2.3

3.0

5.0

WDT, BOR, FVR, T1OSC

disabled, all Peripherals Inactive

D027

WDT, BOR, FVR and T1OSC

disabled, all Peripherals Inactive

18

43

20

45

Power-down Module Current

(1)

D028

—

.46

.74

18

21

22

12

14

40

50

70

12

30

64

.65

0.90

19

20

22

1.3

3.0

44

10

11

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

3.0

5.0

1.8

3.0

2.3

3.0

5.0

LPWDT Current

(1)

60

70

85

28

30

80

85

135

23

80

120

11

LPWDT Current

46

48

(3)

D029

20

FVR Current

22

(3)

65

FVR Current

70

120

17

(1, 3)

D030

BOR Current

(1, 3)

55

BOR Current

100

1.5

4.0

45

(1)

D031

T1OSC Current

12

60

70

80

(1)

T1OSC Current

50

55

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.

4: A/D oscillator source is FRC.

DS40001365F-page 332

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-8: POWER-DOWN CURRENT (CONTINUED)

Standard Operating Conditions (unless otherwise stated)

PIC18LF1XK22

Standard Operating Conditions (unless otherwise stated)

PIC18F1XK22

Conditions

Note

Param.

No.

Max.

+85°C +125°C

Max.

Device Characteristics

Min.

Typ.†

Units

VDD

Power-down Module Current

(1, 4)

D032

—

.7

.8

1.0

3.0

42

9.0

10

A

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

1.8

3.0

2.3

3.0

5.0

A/D Current

progress

, no conversion in

(1, 4)

D032

19

20

22

8

60

A/D Current

progress

44

65

46

80

D033

30

32

Comparator Current, low power

C1 and C2 enabled

11

23

31

33

44

65

77

84

90

13

22

33

35

48

32

35

55

65

Comparator Current, low power

C1 and C2 enabled

65

75

95

D033A

110

130

137

140

150

18

160

165

155

165

180

33

Comparator Current, high power

C1 and C2 enabled

Comparator Current, high power

C1 and C2 enabled

D034

FVR Current

30

40

55

85

FVR Current

80

95

90

120

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.

4: A/D oscillator source is FRC.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 333

PIC18(L)F1XK22

TABLE 26-9: I/O PORTS

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Param.

No.

Sym.

Characteristic

Min.

Typ.†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O ports:

D036

with TTL buffer

VSS

—

0.8

V

4.5V  VDD  5.5V

D036A

D036B

D037

0.15 VDD

0.2 VDD

0.3 VDD

0.8 VDD

0.2 VDD

0.3 VDD

0.2 VDD

0.3 VDD

1.8V  VDD  4.5V

2.0V  VDD  5.5V

1.8V  VDD  5.5V

with Schmitt Trigger buffer

2

D037A

D037B

D038

with I C levels

with SMBus levels

MCLR

2.7V  VDD  5.5V

D039

OSC1

HS, HSPLL modes

(1)

D039A

D039B

D039C

OSC1

EC, RC modes

OSC1

XT, LP modes

T1CKI

VIH

Input High Voltage

I/O ports:

D040

with TTL buffer

2.0

—

VDD

V

4.5V  VDD 5.5V

1.8V  VDD  4.5V

D040A

0.25 VDD +

0.8

D041

with Schmitt Trigger buffer

0.8 VDD

0.7 VDD

2.1

—

VDD

V

1.8V  VDD  5.5V

2.7V  VDD  5.5V

2

D041A

D037A

D042

with I C levels

with SMBus levels

MCLR

VDD

0.8 VDD

0.9 VDD

0.7 VDD

0.8 VDD

0.9 VDD

1.6

VDD

D042A

D043

MCLR

0.3 VDD

VDD

1.8V  VDD  2.4V

HS, HSPLL modes

EC mode

OSC1

D043A

D043B

D043C

D043E

OSC1

VDD

(1)

OSC1

VDD

RC mode

OSC1

VDD

XT, LP modes

T1CKI

1.6

VDD

(2)

IIL

Input Leakage Current

D060

D061

I/O ports

—

± 5

± 100

nA

VSS  VPIN  VDD, Pin at

high-impedance, -40°C to 85°C

VSS  VPIN  VDD, 85°C to 125°C

—

± 5

± 1000

± 200

nA

(3)

MCLR

± 50

VSS  VPIN  VDD

IPUR

PORTB Weak Pull-up Current

D070*

*

50

250

400

A

VDD = 5.0V, VPIN = VSS

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: Including OSC2 in CLKOUT mode.

DS40001365F-page 334

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-9: I/O PORTS (CONTINUED)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Param.

No.

Sym.

Characteristic

Min.

Typ.†

Max.

Units

Conditions

(4)

VOL

Output Low Voltage

D080

I/O ports

VSS+0.6

IOL = 8 mA, VDD = 5V

IOL = 6 mA, VDD = 3.3V

IOL = 3 mA, VDD = VDDMIN

—

V

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: Including OSC2 in CLKOUT mode.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 335

PIC18(L)F1XK22

TABLE 26-9: I/O PORTS (CONTINUED)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Param.

No.

Sym.

Characteristic

Min.

Typ.†

Max.

Units

Conditions

(4)

VOH

Output High Voltage

D090

I/O ports

VDD-0.7

IOH = 3.5 mA, VDD = 5V

IOH = 3 mA, VDD = 3.3V

IOH = 2 mA, VDD = VDDMIN

—

V

Capacitive Loading Specs on Output Pins

D101*

COSC2 OSC2 pin

—

15

50

pF

In XT, HS and LP modes when

external clock is used to drive

OSC1

D101A* CIO

All I/O pins

—

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: Including OSC2 in CLKOUT mode.

DS40001365F-page 336

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-10: MEMORY PROGRAMMING REQUIREMENTS

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

No.

Characteristic

Min.

Typ.†

Max.

Units

Conditions

Internal Program Memory

Programming Specifications

(1)

D110

D113

VPP

Voltage on MCLR/VPP/RA3 pin

8

—

9

V

(Note 3, Note 4)

IDDP

Supply Current during Programming

—

10

mA

(2)

Data EEPROM Memory

D120

D121

D122

D123

ED

Byte Endurance

100K

VDDMIN

—

3

—

VDDMAX

4

E/W -40C to +85C

VDRW

TDEW

VDD for Read/Write

Erase/Write Cycle Time

V

Using EECON to read/write

ms

TRETD Characteristic Retention

—

40

—

Year Provided no other

specifications are violated

D124

D130

TREF

Number of Total Erase/Write Cycles

before Refresh

1M

10M

—

E/W -40°C to +85°C

(2)

Program Flash Memory

EP

Cell Endurance

10k

E/W Temperature during program-

ming: 10°C  TA  40°C

D131

VPR

VDD for Read

VDDMIN

8.0

—

VDDMAX

9.0

V

Temperature during program-

ming: 10°C  TA  40°C

D131A

Voltage on MCLR/VPP during

Erase/Program

V

D131B VBE

D132 VPEW

VDD for Bulk Erase

2.7

—

VDDMAX

Temperature during program-

ming: 10°C  TA  40°C

VDD for Write or Row Erase

2.2

VDDMIN

—

VDDMAX

PIC18LF1XK22

PIC18F1XK22

Temperature during program-

ming: 10°C  TA  40°C

D132A IPPPGM Current on MCLR/VPP during

Erase/Write

—

1.0

—

mA

D132B IDDPGM Current on VDD during Erase/Write

Temperature during program-

ming: 10°C  TA  40°C

5.0

2.0

—

mA

ms

D133

D134

TPEW

Erase/Write cycle time

2.8

Temperature during program-

ming: 10°C  TA  40°C

TRETD Characteristic Retention

40

—

Year Provided no other

specifications are violated

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions.

2: Refer to Section 5.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance.

3: Required only if single-supply programming is disabled.

4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed

between the ICD 2 and target system when programming or debugging with the ICD 2.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 337

PIC18(L)F1XK22

TABLE 26-11: THERMAL CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Typ.

Units

Conditions

20-pin PDIP package

No.

TH01

^JA

Thermal Resistance Junction to Ambient

62.2

75.0

89.3

43.0

27.5

23.1

31.1

5.3

C/W

C

20-pin SOIC package

20-pin SSOP package

20-pin QFN 4x4mm package

20-pin PDIP package

TH02

^JC

Thermal Resistance Junction to Case

20-pin SOIC package

20-pin SSOP package

20-pin QFN 4x4mm package

TH03

TH04

TH05

TH06

TH07

TJMAX

PD

Maximum Junction Temperature

Power Dissipation

150

—

W

PD = PINTERNAL + PI/O

(1)

PINTERNAL Internal Power Dissipation

—

W

PINTERNAL = IDD x VDD

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

(2)

PDER

—

W

PDER = PDMAX (TJ - TA)/JA

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature.

3: TJ = Junction Temperature.

DS40001365F-page 338

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

26.4

Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O PORT

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 26-7:

LOAD CONDITIONS

Load Condition

CL

VSS

Legend: CL = 50 pF for all pins, 15 pF for

OSC2 output

 2009-2016 Microchip Technology Inc.

DS40001365F-page 339

PIC18(L)F1XK22

26.5 AC Characteristics: PIC18(L)F1XK22-I/E

FIGURE 26-8:

CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC1/CLKIN

OS02

OS04

OS03

OSC2/CLKOUT

(LP,XT,HS Modes)

OSC2/CLKOUT

(CLKOUT Mode)

DS40001365F-page 340

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-12: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

Symbol

Characteristic

Min.

Max.

Units

Conditions

No.

1A

FOSC

External CLKIN

DC

48

MHz EC, ECIO Oscillator mode,

(Extended Range Devices)

Frequency⁽¹⁾

DC

64

MHz EC, ECIO Oscillator mode,

(Industrial Range Devices)

Oscillator Frequency⁽¹⁾

DC

0.1

4

MHz RC Oscillator mode

MHz XT Oscillator mode

MHz HS Oscillator mode

25

16

4

MHz HS + PLL Oscillator mode,

(Industrial Range Devices)

4

12

MHz HS + PLL Oscillator mode,

(Extended Range Devices)

5

33

—

kHz LP Oscillator mode

1

TOSC

External CLKIN Period⁽¹⁾

Oscillator Period⁽¹⁾

20.8

ns

EC, ECIO, Oscillator mode

(Extended Range Devices)

15.6

—

ns

EC, ECIO, Oscillator mode,

(Industrial Range Devices)

250

—

ns

RC Oscillator mode

XT Oscillator mode

10,000

40

62.5

250

ns

HS Oscillator mode

HS + PLL Oscillator mode,

(Industrial range devices)

HS + PLL Oscillator mode,

(Extended Range Devices)

83.3

250

ns

30

62.5

30

200

—

s

ns

s

ns

LP Oscillator mode

TCY = 4/FOSC

2

3

TCY

Instruction Cycle Time⁽¹⁾

TOSL,

TOSH

External Clock in (OSC1)

High or Low Time

—

XT Oscillator mode

LP Oscillator mode

HS Oscillator mode

XT Oscillator mode

LP Oscillator mode

HS Oscillator mode

2.5

10

—

4

TOSR,

TOSF

External Clock in (OSC1)

Rise or Fall Time

—

20

50

7.5

—

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations

except PLL. All specified values are based on characterization data for that particular oscillator type under

standard operating conditions with the device executing code. Exceeding these specified limits may result

in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested

to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock

input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 341

PIC18(L)F1XK22

TABLE 26-13: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Freq.

Tolerance

Sym.

Characteristic

Min. Typ.† Max. Units

Conditions

OS08

HFOSC

Internal Calibrated HFINTOSC

Frequency

2%

3%

—

16.0

—

MHz 0°C  TA  60°C

MHz 60°C  TA  +85°C

(2)

5%

0

—

16.0

—

8

MHz

kHz

OS09

LFOSC Internal LFINTOSC Frequency

31.25

OS10* TIOSC ST HFINTOSC

Wake-up from Sleep Start-up Time

—

5

s

VDD = 2.0V, -40°C to +85°C

—

8

VDD = 3.0V, -40°C to +85°C

VDD = 5.0V, -40°C to +85°C

—

8

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

3: By design.

TABLE 26-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 5.5V)

Param.

Sym.

Characteristic

Min.

Typ.†

Max.

Units

Conditions

No.

F10

FOSC Oscillator Frequency Range

4

—

5

MHz VDD = 1.8-3.0V

16

MHz VDD = 3.0-5.0V,

-40°C to +85°C

4

—

12

MHz

VDD = 3.0-5.0V,

125°C

F11

FSYS On-Chip VCO System Frequency

16

—

20

64

MHz VDD = 1.8-3.0V

MHz VDD = 3.0-5.0V,

-40°C to +85°C

16

—

48

MHz VDD = 3.0-5.0V,

125°C

F12

t_rc

PLL Start-up Time (Lock Time)

—

2

ms

%

F13*

^CLKCLKOUT Stability (Jitter)

-0.25

+0.25

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS40001365F-page 342

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 26-9:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Execute

Q3

Q2

FOSC

OS12

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS18

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

TABLE 26-15: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ.† Max. Units

Conditions

OS11

OS12

OS13

TOSH2CKL Fosc to CLKOUT ⁽¹⁾

TOSH2CKH Fosc to CLKOUT ⁽¹⁾

TCKL2IOV CLKOUT to Port out valid⁽¹⁾

—

70

72

20

ns VDD = 3.3-5.0V

ns

—

OS14

OS15

OS16

TIOV2CKH Port input valid before CLKOUT⁽¹⁾

TOSC + 200 ns

—

50

—

70*

—

ns

TOSH2IOV Fosc (Q1 cycle) to Port out valid

—

ns VDD = 3.3-5.0V

TOSH2IOI Fosc (Q2 cycle) to Port input invalid

50

(I/O in hold time)

OS17

OS18

OS19

TIOV2OSH Port input valid to Fosc(Q2 cycle)

20

—

ns

(I/O in setup time)

TIOR

TIOF

Port output rise time⁽²⁾

—

40

15

72

32

ns

VDD = 1.8V

VDD = 3.3-5.0V

Port output fall time⁽²⁾

—

28

15

55

30

VDD = 1.8V

VDD = 3.3-5.0V

OS20* TINP

OS21* TRBP

INT pin input high or low time

25

—

ns

PORTB interrupt-on-change new input

level time

*

†

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

2: Includes OSC2 in CLKOUT mode.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 343

PIC18(L)F1XK22

FIGURE 26-10:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Start-Up Time

(1)

Internal Reset

Watchdog Timer

(1)

Reset

31/

31A

34

I/O pins

Note 1: Asserted low.

FIGURE 26-11:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR and VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

TBORREJ

37

Reset

(1)

33

(due to BOR)

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if PWRTE = 0.

DS40001365F-page 344

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-16: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Min. Typ.† Max. Units

Conditions

No.

30

TMCL

MCLR Pulse Width (low)

2

5

—

s VDD = 3.3-5V, -40°C to +85°C

s VDD = 3.3-5V

31

TWDT

Standard Watchdog Timer Time-out

Period (1:16 Prescaler)

10

17

27

30

ms VDD = 3.3V-5V, -40°C to +85°C

ms VDD = 3.3V-5V

31A

TWDTLP Low-Power Watchdog Timer

Time-out Period (No Prescaler)

10

18

27

33

ms VDD = 3.3V-5V, -40°C to +85°C

ms VDD = 3.3V-5V

32

TOST

Oscillator Start-up Timer Period^(1,2)

—

1024

65

—

TOSC (Note 3)

33*

TPWRT Power-up Timer Period,

40

140

ms

PWRTE = 0

34*

35

TIOZ

I/O high-impedance from MCLR

Low or Watchdog Timer Reset

—

2.73

s

VBOR

Brown-out Reset Voltage

1.75

2.05

2.35

1.9

2.2

2.5

2.05

2.35

2.65

V

BORV = 1.9V⁽⁵⁾

BORV = 2.2V⁽⁵⁾

BORV = 2.7V

2.65 2.85 3.05

BORV = 2.85V

36*

37*

VHYST

Brown-out Reset Hysteresis

0

25

3

50

35

mV -40°C to +85°C

s

TBORDC Brown-out Reset DC Response

Time

VDD  VBOR

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at “min” values with an

external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is

“DC” (no clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

5: PIC18LF1XK22 devices only.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 345

PIC18(L)F1XK22

FIGURE 26-12:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

TABLE 26-17: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

TT0H

Characteristic

Min.

Typ.†

Max.

Units

Conditions

No.

40*

T0CKI High-Pulse Width No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

41*

42*

TT0L

TT0P

T0CKI Low-Pulse Width No Prescaler

With Prescaler

T0CKI Period

Greater of:

20 or TCY + 40

N

N = prescale value

(2, 4, ..., 256)

45*

46*

47*

TT1H

TT1L

TT1P

T1CKI

High Time

Synchronous, No Prescaler

Synchronous, with Prescaler

Asynchronous

0.5 TCY + 20

—

ns

15

30

T1CKI

Low Time

Synchronous, No Prescaler

Synchronous, with Prescaler

Asynchronous

0.5 TCY + 20

15

30

T1CKI

Input

Period

Synchronous

Greater of:

30 or TCY + 40

N

N = prescale value

(1, 2, 4, 8)

Asynchronous

60

—

ns

48

FT1

Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OS-

CEN)

32.4

32.76

8

33.1

kHz

49*

TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC

—

7 TOSC

—

Timers in Sync

mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS40001365F-page 346

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 26-13:

CAPTURE/COMPARE/PWM TIMINGS (CCP)

CCPx

(Capture mode)

CC01

CC02

CC03

Note: Refer to Figure 26-7 for load conditions.

TABLE 26-18: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Min.

Typ.† Max. Units

Conditions

No.

CC01* TccL CCPx Input Low Time

CC02* TccH CCPx Input High Time

CC03* TccP CCPx Input Period

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

—

ns

20

0.5TCY + 20

20

3TCY + 40

N

N = prescale value (1, 4 or 16)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

TABLE 26-19: PIC18(L)F1XK22 A/D CONVERTER (ADC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature: Tested at 25°C

Param.

No.

Sym.

Characteristic

Resolution

Min. Typ.†

Max. Units

Conditions

AD01

AD02

AD03

NR

—

10

±2

bit

EIL

EDL

Integral Error

LSb VREF = 3.0V

Differential Error

±1.5

LSb No missing codes

VREF = 3.0V

AD04

AD05

AD06

EOFF Offset Error

—

±3

LSb VREF = 3.0V

EGN Gain Error

VREF Change in Reference Voltage =

1.8

VDD

V

1.8 VREF+ VDD + 0.3V

(2), (3)

VREF+ - VREF-

VSS - 0.3V VREF- VREF+ - 1.8V

AD07

AD08

VAIN Full-Scale Range

VSS

—

VREF

10

V

ZAIN Recommended Impedance of

Analog Voltage Source

Can go higher if external 0.01 F capacitor is

present on input pin.

k

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.

3: FVR voltage selected must be 2.048V or 4.096V.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 347

PIC18(L)F1XK22

FIGURE 26-14:

A/D CONVERSION TIMING

BSF ADCON0, GO

(Note 2)

131

130

Q4

132

A/D CLK

. . .

.. .

9

8

7

2

1

0

A/D DATA

ADRES

NEW_DATA

TCY

OLD_DATA

ADIF

GO

DONE

SAMPLING STOPPED

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEPinstruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

TABLE 26-20: A/D CONVERSION REQUIREMENTS

Param.

Symbol

Characteristic

Min.

Max.

Units

Conditions

No.

130*

TAD

A/D Clock Period

0.7

25.0⁽¹⁾

s

TOSC based, VREF  3.0V,

-40°C to +85°C

0.7

4.0⁽¹⁾

s

TOSC based, VREF  3.0V,

-40°C to +125°C

1.0

12

4.0

12

s

A/D RC mode

131

TCNV

Conversion Time

TAD

(not including acquisition time)⁽²⁾

132*

135

136

TACQ

TSWC

TDIS

Acquisition Time⁽³⁾

1.4

—

5.0

s

VDD 3.0V, RS = 50

(4)

—

Switching Time from Convert - Sample

Discharge Time

2

s

* These parameters are characterized but not tested.

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES register may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the ‘new’ input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.

4: On the following cycle of the device clock.

DS40001365F-page 348

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-21: COMPARATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristics

Min.

Typ.

Max.

Units

Comments

CM01

VIOFF

Input Offset Voltage

—

10

50

mV

VREF = VDD/2,

High-Power mode

—

12

80

mV

VREF = VDD/2,

Low-Power mode

CM02

CM04

VICM

Input Common-mode Voltage

Response Time

VSS

—

200

300

—

VDD

400

600

10

V

TRESP

ns

s

High-Power mode

Low-Power mode

—

CM05

TMC2OV Comparator Mode Change to

Output Valid*

—

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS

to VDD.

TABLE 26-22: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristics

Step Size

Min.

Typ.

Max.

Units

Comments

DAC01*

DAC02*

DAC03*

DAC04*

*

CLSB

—

VDD/32

—

 1/2

—

V

LSb



CACC

CR

Absolute Accuracy

Unit Resistor Value (R)

Settling Time⁽¹⁾

5k

CST

—

10

s

These parameters are characterized but not tested.

Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.

TABLE 26-23: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS

VR Voltage Reference Specifications

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristics

Min.

Typ.

Max.

Units

Comments

D003

VADFVR

Fixed Voltage Reference Voltage for

ADC, Initial Accuracy

-8

—

6

%

1.024V, VDD  2.5V⁽¹⁾

2.048V, VDD  2.5V

4.096V, VDD  4.75V

D003A

D004*

VCDAFVR Fixed Voltage Reference Voltage for

Comparator and DAC, Initial Accuracy

-11

—

7

%

1.024V, VDD  2.5V

2.048V, VDD  2.5V

4.096V, VDD  4.75V

SVDD

VDD Rise Rate to ensure internal

0.05

—

V/ms

See Section 22.3 “Power-on

Reset (POR)” for details.

Power-on Reset signal

*

These parameters are characterized but not tested.

Note 1: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater.

When selecting the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware

that the voltage must be 1.8V or greater.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 349

PIC18(L)F1XK22

FIGURE 26-15:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK

DT

US121

US122

US120

Refer to Figure 26-7 for load conditions.

Note:

TABLE 26-24: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Symbol

Characteristic

Min.

Max.

Units Conditions

US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

—

80

100

45

ns

US121 TCKRF

Clock out rise time and fall time

(Master mode)

50

US122 TDTRF

Data-out rise time and fall time

45

50

FIGURE 26-16:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK

DT

US125

US126

Note: Refer to Figure 26-7 for load conditions.

TABLE 26-25: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Symbol

Characteristic

Min.

Max.

Units

Conditions

US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK  (DT hold time)

10

15

—

ns

US126 TCKL2DTL Data-hold after CK  (DT hold time)

DS40001365F-page 350

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 26-17:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

SP70

SCK

(CKP = 0)

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

LSb In

SP74

SP73

Note: Refer to Figure 26-7 for load conditions.

FIGURE 26-18:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81

SCK

(CKP = 0)

SP71

SP73

SP72

SP79

SCK

(CKP = 1)

SP80

SP78

LSb

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

SP74

Note: Refer to Figure 26-7 for load conditions.

LSb In

 2009-2016 Microchip Technology Inc.

DS40001365F-page 351

PIC18(L)F1XK22

FIGURE 26-19:

SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK

(CKP = 0)

SP83

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

MSb

SDO

SDI

bit 6 - - - - - -1

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

SP73

LSb In

Note: Refer to Figure 26-7 for load conditions.

FIGURE 26-20:

SPI SLAVE MODE TIMING (CKE = 1)

SP82

SP70

SS

SP83

SCK

(CKP = 0)

SP72

SP71

SCK

(CKP = 1)

SP80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note: Refer to Figure 26-7 for load conditions.

DS40001365F-page 352

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-26: SPI MODE REQUIREMENTS

Param.

Symbol

Characteristic

Min.

Typ.† Max. Units Conditions

No.

SP70* TSSL2SCH, SS to SCK or SCK input

TCY

—

ns

TSSL2SCL

SP71* TSCH

SP72* TSCL

SCK input high time (Slave mode)

SCK input low time (Slave mode)

TCY + 20

100

—

ns

SP73* TDIV2SCH, Setup time of SDI data input to SCK edge

TDIV2SCL

SP74* TSCH2DIL, Hold time of SDI data input to SCK edge

TSCL2DIL

100

—

ns

SP75* TDOR

SDO data output rise time

3.0-5.5V

1.8-5.5V

—

10

—

Tcy

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns

SP76* TDOF

SDO data output fall time

SP77* TSSH2DOZ SS to SDO output high-impedance

SP78* TSCR

SCK output rise time

(Master mode)

3.0-5.5V

1.8-5.5V

SP79* TSCF

SCK output fall time (Master mode)

SP80* TSCH2DOV, SDO data output valid after

TSCL2DOV SCK edge

3.0-5.5V

1.8-5.5V

SP81* TDOV2SCH, SDO data output setup to SCK edge

TDOV2SCL

SP82* TSSL2DOV SDO data output valid after SS edge

—

50

—

ns

SP83* TSCH2SSH, SS after SCK edge

1.5TCY + 40

TSCL2SSH

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 26-21:

I²C BUS START/STOP BITS TIMING

SCL

SP93

SP91

SP90

SP92

SDA

Stop

Condition

Start

Condition

Note: Refer to Figure 26-7 for load conditions.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 353

PIC18(L)F1XK22

TABLE 26-27: I²C BUS START/STOP BITS REQUIREMENTS

Param.

Symbol

Characteristic

Min. Typ. Max. Units

Conditions

No.

SP90* TSU:STA Start condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns Only relevant for Repeated

Start condition

SP91* THD:STA Start condition

Hold time

4000

600

ns After this period, the first

clock pulse is generated

SP92* TSU:STO Stop condition

Setup time

4700

600

ns

SP93 THD:STO Stop condition

Hold time

4000

600

ns

*

These parameters are characterized but not tested.

FIGURE 26-22:

I²C BUS DATA TIMING

SP100

SP102

SP103

SP101

SCL

SP90

SP91

SP106

SP107

SP92

SDA

In

SP110

SP109

SDA

Out

Note: Refer to Figure 26-7 for load conditions.

DS40001365F-page 354

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

TABLE 26-28: I²C BUS DATA REQUIREMENTS

Param.

Symbol

Characteristic

Min.

Max. Units

Conditions

No.

SP100* THIGH

Clock high time

100 kHz mode

4.0

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

Device must operate at a

minimum of 10 MHz

SSP Module

1.5TCY

4.7

—

SP101* TLOW

Clock low time

100 kHz mode

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

Device must operate at a

minimum of 10 MHz

SSP Module

1.5TCY

—

SP102* TR

SP103* TF

SDA and SCL rise 100 kHz mode

1000

300

ns

time

400 kHz mode

20 +

CB is specified to be from

10-400 pF

0.1CB

SDA and SCL fall

time

100 kHz mode

400 kHz mode

—

250

ns

20 +

0.1CB

CB is specified to be from

10-400 pF

SP90* TSU:STA Start condition

setup time

100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

0

—

s

ns

s

ns

s

ns

s

Only relevant for

Repeated Start condition

SP91* THD:STA Start condition hold 100 kHz mode

—

After this period the first

clock pulse is generated

time

400 kHz mode

—

SP106* THD:DAT Data input hold

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

0

0.9

—

SP107* TSU:DAT Data input setup

time

250

100

4.7

0.6

—

(Note 2)

—

SP92* TSU:STO Stop condition

setup time

—

SP109* TAA

Output valid from

clock

3500

—

(Note 1)

—

SP110* TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmis-

sion can start

—

SP

CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification), before the SCL line is released.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 355

PIC18(L)F1XK22

27.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”

represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each

temperature range.

DS40001365F-page 356

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 27-1:

PIC18LF1XK22 TYPICAL BASE IPD

5

4.5

4

125°C

3.5

3

2.5

2

1.5

1

85°C

25°C

-40°C

0.5

0

1.8

2

2.2

2.4

VDD (V)

2.6

2.8

3

FIGURE 27-2:

PIC18LF1XK22 TYPICAL IPD FOR WATCHDOG TIMER

6.0

5.4

4.8

4.2

3.6

3.0

2.4

125°C

1.8

1.2

0.6

85°C

Typ. 25°C

0.0

1.8

2

2.2

2.4

2.6

2.8

3

VDD (V)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 357

PIC18(L)F1XK22

FIGURE 27-3:

PIC18LF1XK22 TYPICAL IPD FOR BROWN-OUT RESET

16

14

12

10

8

125°C

85°C

Typ. 25°C

6

4

2

0

2

2.1

2.2

2.3

2.4

2.5

VDD (V)

2.6

2.7

2.8

2.9

3

FIGURE 27-4:

PIC18LF1XK22 TYPICAL IPD FOR DIGITAL-TO-ANALOG CONVERTER (CVREF)

40

35

30

25

20

15

10

5

125°C

85°C

25°C

0

1.8

2

2.2

2.4

2.6

2.8

3

VDD (V)

DS40001365F-page 358

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 27-5:

PIC18LF1XK22 ICOMP – TYPICAL IPD FOR COMPARATOR IN LOW-POWER

MODE

25.0

20.0

15.0

10.0

125°C

85°C

25°C

-40°C

5.0

1.8

2

2.2

2.4

2.6

2.8

3

VDD (V)

FIGURE 27-6:

PIC18LF1XK22 ICOMP – TYPICAL IPD FOR COMPARATOR IN HIGH-POWER

MODE

125

100

75

125°C

85°C

25°C

50

-40°C

25

0

1.8

2

2.2

2.4

VDD (V)

2.6

2.8

3

 2009-2016 Microchip Technology Inc.

DS40001365F-page 359

PIC18(L)F1XK22

FIGURE 27-7:

PIC18LF1XK22 TYPICAL RC_RUN 31 kHz IDD

30

25

20

15

10

5

125°C

85°C

25°C

-40°C

0

1.8

2

2.2

2.4

2.6

2.8

3

VDD (V)

FIGURE 27-8:

PIC18LF1XK22 TYPICAL RC_RUN IDD

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

16 MHz

1 MHz

0.0

1.8

2

2.2

2.4

VDD (V)

2.6

2.8

3

DS40001365F-page 360

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 27-9:

PIC18LF1XK22 TYPICAL PRI_RUN IDD (EC)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

16 MHz

1 MHz

0.0

1.8

2

2.2

2.4

VDD (V)

2.6

2.8

3

FIGURE 27-10:

PIC18LF1XK22 TYPICAL PRI_RUN IDD (HS + PLL)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

16 MHz

(4 MHz Input)

1.0

0.5

0.0

1.8

2

2.2

2.4

2.6

2.8

3

VDD (V)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 361

PIC18(L)F1XK22

FIGURE 27-11:

MEMLOW TYPICAL BASE IPD

50

45

40

35

30

25

20

15

10

5

125°C

85°C

25°C

-40°C

0

2.3

2.8

3.3

3.8

4.3

4.8

VDD (V)

FIGURE 27-12:

MEMLOW TYPICAL IPD FOR WATCHDOG TIMER

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

125°C

85°C

Typ. 25°C

0.0

2.3

2.8

3.3

3.8

4.3

4.8

VDD (V)

DS40001365F-page 362

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 27-13:

MEMLOW TYPICAL IPD FOR BROWN-OUT RESET

80

70

60

50

40

30

20

10

125°C

85°C

Typ. 25°C

0

3

3.2

3.4

3.6

3.8

4

4.2

4.4

4.6

4.8

5

VDD (V)

FIGURE 27-14:

MEMLOW TYPICAL IPD FOR DIGITAL-TO-ANALOG CONVERTER (CVREF)

80

70

60

50

40

30

20

10

125°C

85°C

25°C

0

2.3

2.8

3.3

3.8

4.3

4.8

VDD (V)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 363

PIC18(L)F1XK22

FIGURE 27-15:

MEMLOW ICOMP – TYPICAL IPD FOR COMPARATOR IN LOW-POWER MODE

60.0

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

125°C

85°C

25°C

-40°C

10.0

2.3

2.8

3.3

3.8

VDD (V)

4.3

4.8

FIGURE 27-16:

MEMLOW ICOMP – TYPICAL IPD FOR COMPARATOR IN HIGH-POWER MODE

150

125

100

75

125°C

85°C

25°C

-40°C

50

25

0

2.3

2.8

3.3

3.8

4.3

4.8

VDD (V)

DS40001365F-page 364

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 27-17:

MEMLOW TYPICAL RC_RUN 31 kHz IDD

50

45

40

35

30

25

20

15

10

5

125°C

85°C

25°C

-40°C

0

2.3

2.8

3.3

3.8

VDD (V)

4.3

4.8

FIGURE 27-18:

MEMLOW TYPICAL RC_RUN IDD

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

16 MHz

1 MHz

0.0

2.3

2.8

3.3

3.8

4.3

4.8

VDD (V)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 365

PIC18(L)F1XK22

FIGURE 27-19:

MEMLOW TYPICAL PRI_RUN IDD (EC)

14

64 MHz

12

10

8

6

4

16 MHz

1 MHz

2

0

2.3

2.8

3.3

3.8

4.3

4.8

VDD (V)

FIGURE 27-20:

MEMLOW TYPICAL PRI_RUN IDD (HS + PLL)

16

14

12

10

8

64 MHz

(16 MHz Input)

6

4

16 MHz

(4 MHz Input)

2

0

2.3

2.8

3.3

3.8

4.3

4.8

VDD (V)

DS40001365F-page 366

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 27-21:

PIC18(L)F1XK22 TTL BUFFER TYPICAL VIH

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

0.3

Min.

-40°C

25°C

85°C

125°C

0.1

1.8

2.3

2.8

3.3

3.8

4.3

4.8

5.3

VDD (V)

FIGURE 27-22:

PIC18(L)F1XK22 SCHMITT TRIGGER BUFFER TYPICAL VIH

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

Min.

-40°C

125°C

1.8

2.3

2.8

3.3

3.8

VDD (V)

4.3

4.8

5.3

 2009-2016 Microchip Technology Inc.

DS40001365F-page 367

PIC18(L)F1XK22

FIGURE 27-23:

PIC18(L)F1XK22 TTL BUFFER TYPICAL VIL

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

0.3

0.1

25°C

85°C

-40°C

125°C

Max.

1.8

2.3

2.8

3.3

3.8

VDD (V)

4.3

4.8

5.3

FIGURE 27-24:

PIC18(L)F1XK22 SCHMITT BUFFER TYPICAL VIL

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

-40°C

125°C

Max.

0.2

1.8

2.3

2.8

3.3

3.8

4.3

4.8

5.3

VDD (V)

DS40001365F-page 368

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 27-25:

MEMLOW TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz ± 15%)

33.3

32.3

31.3

30.3

29.3

25°C

-40°C

85°C

125°C

28.3

2

2.5

3

3.5

4

4.5

5

5.5

VDD (V)

FIGURE 27-26:

MEMLOW TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz ± 15%)

32.5

32.0

31.5

31.0

30.5

30.0

29.5

2.5V

3.0V

5.5V

29.0

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 369

PIC18(L)F1XK22

FIGURE 27-27:

PIC18LF1XK22 TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz ±

15%)

33.3

32.3

31.3

30.3

29.3

28.3

27.3

26.3

25.3

25°C

-40°C

85°C

125°C

2

2.4

2.8

3.2

3.6

VDD (V)

FIGURE 27-28:

PIC18LF1XK22 TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz ±

15%)

33.0

32.0

31.0

30.0

29.0

28.0

27.0

2.5V

3V

3.6V

26.0

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

DS40001365F-page 370

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

FIGURE 27-29:

MEMLOW TYPICAL VOH vs. IOH

6

5

4

3

2

1

5.5V

4.0V

3.0V

2.0V

0

5

10

15

20

25

30

35

IOH (mA)

FIGURE 27-30:

MEMLOW TYPICAL VOL vs. IOL

2.5

2.0

1.5

1.0

0.5

1.8V

3.0

4.0V

5.5V

0.0

0

5

10

15

20

25

30

IOL (mA)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 371

PIC18(L)F1XK22

28.0 PACKAGING INFORMATION

28.1 Package Marking Information

20-Lead PDIP (300 mil)

Example

PIC18F13K22

-E/P

XXXXXXXXXXXXXXXXX

e

3

0910017

YYWWNNN

20-Lead SSOP (5.30 mm)

Example

PIC18F13K22

e

3

-I/SS

0910017

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS40001365F-page 372

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

Package Marking Information (Continued)

Example

20-Lead SOIC (7.50 mm)

PIC18F14K22

e

3

-E/SO

0910017

20-Lead QFN (4x4x0.9 mm)

Example

PIC18

PIN 1

F14K22

e

3

E/ML

910017

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2009-2016 Microchip Technology Inc.

DS40001365F-page 373

PIC18(L)F1XK22

28.2 Package Details

The following sections give the technical details of the packages.

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DS40001365F-page 374

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

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ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢜꢎ1

 2009-2016 Microchip Technology Inc.

DS40001365F-page 375

PIC18(L)F1XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001365F-page 376

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2016 Microchip Technology Inc.

DS40001365F-page 377

PIC18(L)F1XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS40001365F-page 378

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2016 Microchip Technology Inc.

DS40001365F-page 379

PIC18(L)F1XK22

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DS40001365F-page 380

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

ꢛꢗꢋꢄꢜ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ

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 2009-2016 Microchip Technology Inc.

DS40001365F-page 381

PIC18(L)F1XK22

APPENDIX A: REVISION HISTORY

Revision A (February 2009)

Original data sheet for PIC18(L)F1XK22 devices.

Revision B (04/2009)

Revised data sheet title; Revised Peripheral Features

section; Revised Table 3-1, Table 3-2; Revised

Example 15-1; Revised Table 21-4.

Revision C (10/2009)

Updated Table 1-1; Updated the “Electrical

Specifications” section (Figures 25-1 to 25-4; sub-

sections 25.1, 25.2, 25.3, 25.4, 25.5, 25.6, 25.7, 25.8,

Added Param No. OS09 to Table 25-2; Added Param

No. D003A and Note 1 to Table 25-12); Added graphs

to the “DC and AC Characteristics Graphs and Charts”

section; Other minor corrections.

Revision D (05/2010)

Revised Section 1.3 (deleted #2); Revised Figure 1-1;

Added Table 2-4; Removed register EEADRH from

Tables 3-1 and 3-2; Revised Section 5 (Data EEPROM

Memory); Updated Example 5-2 and Table 5-1;

Revised Section 13.4.4 (Enhanced PWM Auto-Shut-

down Mode); Added Note 4 below Register 13-2;

Revised Figure 16-1; Revised Equation 20-1;

Removed sub-section 20.1.3 (Output Clamped to VSS);

Updated Figure 20-1; Revised Tables 21-4 and Table

22-1; Updated Register 22-5, Figure 25-5, Table 25-2,

Table 25-8, Table 25-10 and Table 25-12; Updated the

Electrical Specification section; Other minor

corrections.

Revision E (10/2011)

Updated data sheet to new format; Updated the Pin

Diagrams; Updated the Electrical Specifications

section; Updated the Packaging Information section;

Updated Table B-1; Updated the Product Identification

System section; Other minor corrections.

Revision F (04/2016)

Updated Analog Features section on page 1; Updated

Tables 1-2, 3-2, 8-5, 8-6, 16-2 and 22-4; Added Note 3

to Tables 3-2, 8-1 and 8-2; Added Note 1 to Tables 9-1,

10-2, 12-1 and 17-2, and Register 8-4; Updated

Figures 3-7, 9-1 and 9-2; Updated Registers 13-2,

16-2, 19-1; Updated Section 1.1.2, 7.9 and 8.1;

Replaced chapter 20.0 (Voltage References) with

chapter 20.0 (Fixed Voltage Reference) and 21.0

(Digital-to-Analog Converter (DAC) Module); Updated

Chapter 26.0 (Electrical Specifications); Other minor

corrections.

DS40001365F-page 382

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

APPENDIX B: DEVICE

DIFFERENCES

The differences between the devices listed in this data

sheet are shown in Table .

TABLE B-1:

DEVICE DIFFERENCES

PIC18F13K22

Features

PIC18F14K22

PIC18LF13K22

PIC18LF14K22

8192

4096

256

2.3

16384

8192

512

8192

4096

256

1.8

16384

8192

512

Program Memory (Bytes)

Program Memory (Instructions)

Data Memory SRAM (bytes)

Data Memory EEPROM (bytes)

VDD Min^(V)

256

2.3

1.8

VDD Max^(V)

5.5

3.6

Packages

20-pin PDIP

20-pin SOIC

20-pin SSOP

20-Pin QFN

20-pin PDIP

20-pin SOIC

20-pin SSOP

20-Pin QFN

20-pin PDIP

20-pin SOIC

20-pin SSOP

20-Pin QFN

20-pin PDIP

20-pin SOIC

20-pin SSOP

20-Pin QFN

 2009-2016 Microchip Technology Inc.

DS40001365F-page 383

PIC18(L)F1XK22

THE MICROCHIP WEBSITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This website is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the website contains the following information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers

should

contact

their

distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the website

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip website at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

DS40001365F-page 384

 2009-2016 Microchip Technology Inc.

PIC18(L)F1XK22

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(2)

X

/XX

XXX

PART NO.

Device

[X]

-

Examples:

Temperature

Range

Package

Pattern

Tape and Reel

Option

a)

b)

PIC18F14K22-E/P 301 = Extended temp.,

PDIP package, QTP pattern #301.

PIC18LF14K22-E/SO = Extended temp., SOIC

package.

c)

d)

PIC18LF14K22-E/ML = Extended temp., QFN

package.

Device:

PIC18F13K22, PIC18LF13K22

PIC18F14K22, PIC18LF14K22

PIC18F13K22T-I/SS = Industrial temp., SSOP

package, Tape and Reel.

Tape and Reel

Option:

Blank = standard packaging (tube or tray)

T = Tape and Reel^{(1), (2)}

Temperature

Range:

E

I

=

-40C to +125C (Extended)

-40C to +85C

(Industrial)

Package:

ML

P

SO

SS

=

QFN

=

PDIP

SOIC

SSOP

Note 1:

2:

Tape and Reel option is available for ML,

MV, PT, SO and SS packages with industrial

Temperature Range only.

Tape and Reel identifier only appears in

catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package.

Pattern:

QTP, SQTP, Code or Special Requirements

(blank otherwise)

 2009-2016 Microchip Technology Inc.

DS40001365F-page 385

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

32

OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,

Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0464-4

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

DS40001365F-page 386

 2009-2016 Microchip Technology Inc.

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

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Tel: 49-2129-3766400

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

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Tel: 86-10-8569-7000

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Germany - Karlsruhe

Tel: 49-721-625370

India - Pune

Tel: 91-20-3019-1500

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Austin, TX

Tel: 512-257-3370

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Dongguan

Tel: 86-769-8702-9880

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

Cleveland

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Poland - Warsaw

Tel: 48-22-3325737

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Sweden - Stockholm

Tel: 46-8-5090-4654

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Novi, MI

UK - Wokingham

Tel: 44-118-921-5800

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Tel: 248-848-4000

Fax: 44-118-921-5820

Houston, TX

Tel: 281-894-5983

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

New York, NY

Tel: 631-435-6000

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

San Jose, CA

Tel: 408-735-9110

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-673-0699

Fax: 905-673-6509

07/14/15

 2009-2016 Microchip Technology Inc.

DS40001365F-page 387


型号：	PIC18F13K22T-I/SS
厂家：	MICROCHIP
描述：	16-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PDSO20, 5.30 MM, LEAD FREE, PLASTIC, SSOP-20 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟微控制器光电二极管外围集成电路
文件：	总387页 (文件大小：3442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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