PIC18F16Q41 [MICROCHIP]
PIC18FXXQ41 Family Programming Specification;型号: | PIC18F16Q41 |
厂家: | MICROCHIP |
描述: | PIC18FXXQ41 Family Programming Specification 外围集成电路 |
文件: | 总40页 (文件大小:554K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC18FXXQ41
PIC18FXXQ41 Family Programming Specification
Introduction
This programming specification describes a SPI-based programming method for the PIC18FXXQ41 family of
microcontrollers. Programming Algorithms describes the programming commands, programming algorithms and
electrical specifications used in that particular programming method. APPENDIX B contains individual part numbers,
device identification values, pinout and packaging information, and Configuration Bytes.
Important:ꢀ
•
•
This is a SPI-compliant programming method with 8-bit commands.
The low-voltage entry code is now 32 clocks and MSb first, unlike earlier PIC18 devices, which had
33 clocks and LSb first.
DS40002143B-page 1
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Table of Contents
Introduction.....................................................................................................................................................1
1. Overview................................................................................................................................................. 4
1.1. Programming Data Flow...............................................................................................................4
1.2. Pin Utilization................................................................................................................................4
1.3. Hardware Requirements.............................................................................................................. 4
1.4. Write and/or Erase Section.......................................................................................................... 5
2. Memory Map........................................................................................................................................... 6
2.1. User ID Location...........................................................................................................................7
2.2. Device/Revision ID.......................................................................................................................7
2.3. Device Configuration Information (DCI)....................................................................................... 7
2.4. Configuration Bytes......................................................................................................................7
2.5. Device ID .....................................................................................................................................9
2.6. Revision ID ................................................................................................................................10
3. Programming Algorithms.......................................................................................................................11
3.1. Program/Verify Mode..................................................................................................................11
3.2. Programming Algorithms............................................................................................................18
3.3. Code Protection..........................................................................................................................23
3.4. Hex File Usage...........................................................................................................................23
3.5. CRC Checksum Computation.................................................................................................... 24
4. Electrical Specifications........................................................................................................................ 25
5. APPENDIX A: Revision History.............................................................................................................27
6. APPENDIX B.........................................................................................................................................28
6.1. CONFIG1 .................................................................................................................................. 29
6.2. CONFIG2 .................................................................................................................................. 30
6.3. CONFIG3................................................................................................................................... 31
6.4. CONFIG4................................................................................................................................... 32
6.5. CONFIG5................................................................................................................................... 33
6.6. CONFIG6................................................................................................................................... 34
6.7. CONFIG7................................................................................................................................... 35
6.8. CONFIG8................................................................................................................................... 36
6.9. CONFIG9................................................................................................................................... 37
The Microchip Website.................................................................................................................................38
Product Change Notification Service............................................................................................................38
Customer Support........................................................................................................................................ 38
Microchip Devices Code Protection Feature................................................................................................38
Legal Notice................................................................................................................................................. 38
Trademarks.................................................................................................................................................. 39
DS40002143B-page 2
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Quality Management System....................................................................................................................... 39
Worldwide Sales and Service.......................................................................................................................40
DS40002143B-page 3
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Overview
1.
Overview
1.1
Programming Data Flow
Nonvolatile Memory (NVM) programming data can be supplied by either the high-voltage In-Circuit Serial
™
™
Programming (ICSP ) interface or the low-voltage In-Circuit Serial Programming (ICSP) interface. Data can be
programmed into the Program Flash Memory (PFM), Data EEPROM Memory, dedicated “User ID” locations and the
Configuration Bytes.
1.2
Pin Utilization
Five pins are needed for ICSP programming. The pins are listed in the table below. For pin locations and packaging
information, refer to the table in 6. APPENDIX B.
Table 1-1.ꢀPIN DESCRIPTIONS DURING PROGRAMMING
Pin Name
During Programming
Function
Pin Type
Pin Description
ISCPCLK
ICSPCLK
I
Clock Input - Schmitt
Trigger Input
ISCPDAT
ICSPDAT
I/O
Data Input/Output - Schmitt
Trigger Input
MCLR/VPP
VDD
Program/Verify mode
I(1)
P
Program Mode Select
Power Supply
Ground
VDD
VSS
VSS
P
Legend: I = Input, O = Output, P = Power
Note:ꢀ
1. The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to the MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
1.3
Hardware Requirements
1.3.1
High-Voltage ICSP Programming
In High-Voltage ICSP mode, the device requires two programmable power supplies: one for VDD and one for the
MCLR/VPP pin.
1.3.2
Low-Voltage ICSP Programming
In Low-Voltage ICSP mode, the device can be programmed using a single VDD source in the device operating range.
The MCLR/VPP pin does not have to be brought to programming voltage, but can instead be left at the normal
operating voltage.
1.3.2.1 Single-Supply ICSP Programming
The device’s LVP Configuration bit enables single-supply (low-voltage) ICSP programming. The LVP bit defaults to a
‘1’ (enabled). The LVP bit may only be programmed to ‘0’ by entering the High-Voltage ICSP mode, where the
MCLR/VPP pin is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode is
available and can be used to program the device.
DS40002143B-page 4
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Overview
Important:ꢀ
•
The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying
VIHH to the MCLR/VPP pin.
•
While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit. Also, the
MCLR pin can no longer be used as a general purpose input.
1.4
Write and/or Erase Section
Erasing or writing is selected according to the command used to begin operation (see Table 3-1). The terminologies
used in this document, related to erasing/writing to the program memory, are defined in the table below.
Table 1-2.ꢀPROGRAMMING TERMS
Term
Programmed Cell
Erased Cell
Erase
Definition
A memory cell at logic ‘0’
A memory cell at logic ‘1’
Change memory cell from a ‘0’ to a ‘1’
Change memory cell from a ‘1’ to a ‘0’
Generic erase and/or write
Write
Program
1.4.1
1.4.2
Erasing Memory
Memory is erased by 128-word pages or in bulk, where ‘bulk’ includes many subsets of the total memory space. The
duration of the data memory erase is determined by the size of data memory. All Bulk ICSP Erase commands have
minimum VDD requirements, which are higher than the Page Erase and Write requirements.
Page erasing pertains to PFM and User ID memory only. Configuration and data memory should be erased by the
Bulk Erase command. For self-write operations, each byte write to data memory includes an automatic erase cycle
for the location about to be programmed.
Writing Memory
Memory is written one word at a time. The duration of the write is determined internally.
Note:ꢀ The size of the word is 16 bits for the Program Flash Memory and is 8 bits for the EEPROM, but the same 24-
bit payload is used for both memory regions.
DS40002143B-page 5
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Memory Map
2.
Memory Map
This section provides details about how the program memory and EEPROM is organized for this device.
Figure 2-1.ꢀProgram and Data EEPROM Memory Map
Rev. 40-000101E
4/20/2017
Device
Address
PIC18Fx4Q41
PIC18Fx5Q41
PIC18Fx6Q41
00 0000h
to
00 3FFFh
00 4000h
to
Program Flash Memory
(8KW)(1)
Program Flash
Memory
(16 KW)(1)
Program Flash
Memory
(32 KW)(1)
00 7FFFh
00 8000h
to
00 FFFFh
Not
Present(2)
01 0000h
to
Not
Present(2)
01 FFFFh
Not
Present(2)
02 0000h
to
1F FFFFh
20 0000h
to
20 003Fh
20 0040h
to
User IDs (32 Words)(3)
Reserved
2B FFFFh
2C 0000h
to
2C 00FFh
2C 0100h
to
Device Information Area (DIA)(3)(5)
Reserved
2F FFFFh
30 0000h
to
30 0009h
30 000Ah
to
Configuration Bytes (3)
Reserved
37 FFFFh
38 0000h
to
38 03FFh
38 0400h
to
Data EEPROM (1024 Bytes)
Reserved
3B FFFFh
3C 0000h
to
Device Configuration Information(3)(4)(5)
Reserved
3C 0009h
3C 000Ah
to
3F FFFBh
3F FFFCh
to
3F FFFDh
3F FFFEh
to
Revision ID (1 Word)(3)(4)(5)
Device ID (1 Word)(3)(4)(5)
3F FFFFh
Storage Area Flash is implemented as the last 128
Note 1:
Words of User Flash, if enabled.
The addresses do not roll over. The region is read as ‘0’.
Not code-protected.
2:
3:
4:
5:
Hard-coded in silicon.
This region cannot be written by the user and it’s not affected by a Bulk Erase.
DS40002143B-page 6
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Memory Map
2.1
2.2
2.3
User ID Location
A user may store identification information (User ID) in 32 designated locations. The User ID locations are mapped to
20 0000h-20 003Fh. Each location is 16 bits in length. Code protection has no effect on these memory locations.
Each location may be read with code protection enabled or disabled.
Device/Revision ID
The 16-bit Device ID Word is located at 3F FFFEh and the 16-bit Revision ID is located at 3F FFFCh. These
locations are read-only and cannot be erased or modified. See DEVICE ID and REVISION ID registers for more
details.
Device Configuration Information (DCI)
The Device Configuration Information (DCI) is a dedicated region in the memory that holds information about the
device which is useful for programming and bootloader applications. The data stored in this region is read-only and
cannot be modified/erased. Refer to the table below for complete DCI table addresses and description.
Table 2-1.ꢀDEVICE CONFIGURATION INFORMATION
Value
Address Name
Description
Units
PIC18F04/14Q41
PIC18F05/15Q41
PIC18F06/16Q41
3C 0000h ERSIZ Erase Page Size
128
Words
Words
Number of write
3C 0002h WLSIZ
0
latches per row
Number of user
3C 0004h URSIZ
128
256
512
Pages
erasable pages
Data EEPROM
3C 0006h EESIZ
1024
Bytes
Pins
memory size
3C 0008h PCNT Pin Count
14(1)/20
14(1)/20
14(1)/20
Note:ꢀ
1. Pin Count value of 14 is used for 16-pin parts as well.
2.4
Configuration Bytes
The devices have ten Configuration Bytes, starting at address, 30 0000h. Configuration bits enable or disable specific
features, placing these controls outside the normal software process, and they establish configured values prior to
the execution of any software.
In terms of programming, these important Configuration bits should be considered:
1. LVP: Low-Voltage Programming Enable bit
– 1 = ON: Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration
bit is ignored.
– 0 = OFF: High voltage on MCLR/VPP must be used for programming.
It is important to note that the LVP bit cannot be written (to ‘0’) while operating from the LVP programming
interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming
from LVP mode, or accidentally eliminating LVP mode from the Configuration state. For more information, refer
to the Low-Voltage Programming (LVP) Mode section.
2. MCLRE: Master Clear (MCLR) Enable bit
– If LVP = 1: RA3 pin function is MCLR
DS40002143B-page 7
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Memory Map
– If LVP = 0
• 1 =RA3 pin is MCLR
• 0 =RA3 pin function is a port-defined function
3. CP: User NVM Program Memory Code Protection bit
– 1 = OFF: User NVM code protection is disabled
– 0 = ON: User NVM code protection is enabled
For more information on code protection, see Code Protection.
DS40002143B-page 8
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Memory Map
2.5
Device ID
Name:ꢀ
DEVICEID
Address:ꢀ 3F FFFEh
Device ID Register
Bit
15
14
13
12
11
10
9
8
DEV[15:8]
DEV[7:0]
Access
Reset
R
q
R
q
R
q
R
q
R
q
R
q
R
q
R
q
Bit
7
6
5
4
3
2
1
0
Access
Reset
R
q
R
q
R
q
R
q
R
q
R
q
R
q
R
q
Bits 15:0 – DEV[15:0]ꢀDevice ID
Device
Device ID
7540h
7500h
7580h
7520h
74E0h
7560h
PIC18F04Q41
PIC18F05Q41
PIC18F06Q41
PIC18F14Q41
PIC18F15Q41
PIC18F16Q41
DS40002143B-page 9
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Memory Map
2.6
Revision ID
Name:ꢀ
REVISIONID
Address:ꢀ 3F FFFCh
Revision ID Register
Bit
15
14
13
12
11
10
9
8
1010[3:0]
MJRREV[5:2]
Access
Reset
R
1
R
0
R
1
R
0
RO
q
RO
q
RO
q
RO
q
Bit
7
6
5
4
3
2
1
0
MJRREV[1:0]
MNRREV[5:0]
Access
Reset
RO
q
RO
q
RO
q
RO
q
RO
q
RO
q
RO
q
RO
q
Bits 15:12 – 1010[3:0]ꢀ Read as 'b1010
These bits are fixed with value 'b1010for all devices in this family.
Bits 11:6 – MJRREV[5:0]ꢀMajor Revision ID
These bits are used to identify a major revision. (A0, B0, C0, etc.).
Revision A = 'b00 0000
Bits 5:0 – MNRREV[5:0]ꢀMinor Revision ID
These bits are used to identify a minor revision.
Revision A0 = 'b00 0000
DS40002143B-page 10
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
3.
Programming Algorithms
3.1
Program/Verify Mode
In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in
serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data
words are transmitted MSb first. Data changes on the rising edge of the ICSPCLK and is latched on the falling edge.
In Program/Verify mode, both the ICSPDAT and ICSPCLK pins are Schmitt Trigger inputs. The sequence that enters
the device into Program/Verify mode places all other logic into the Reset state, all I/Os are automatically configured
as high-impedance inputs and the Program Counter (PC) is cleared.
3.1.1
High-Voltage Program/Verify Mode Entry and Exit
There are two different modes of entering Program/Verify mode via high voltage:
•
•
VPP-First Entry mode
VDD-First Entry mode
3.1.1.1 VPP-First Entry Mode
To enter Program/Verify mode via the VPP-First Entry mode, the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low.
2. Raise the voltage on MCLR from 0V to VIHH
.
3. Raise the voltage on VDD from 0V to the desired operating voltage.
The VPP-First Entry mode prevents the device from executing code prior to entering Program/Verify mode. For
example, when the Configuration Byte has already been programmed to have MCLR disabled (MCLRE = 0), the
Power-up Timer disabled (PWRTE = 0) and the internal oscillator selected, the device will execute code immediately.
VPP-First Entry mode is strongly recommended as it prevents user code from executing. See the timing diagram in
Figure 3-1.
Figure 3-1.ꢀPROGRAMMING ENTRY AND EXIT MODES – VPP-First and Last
PROGRAMMING MODE ENTRY – ENTRY
VPP-First
PROGRAMMING MODE ENTRY – EXIT
VPP-Last
TENTS
TENTH
TEXIT
VDD
VIHH
VPP
VIL
ICSPDAT
ICSPCLK
3.1.1.2 VDD- First Entry Mode
To enter Program/Verify mode via the VDD-First Entry mode, the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low.
DS40002143B-page 11
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
2. Raise the voltage on VDD from 0V to the desired operating voltage.
3. Raise the voltage on MCLR from VDD or below to VIHH
.
The VDD-First Entry mode is useful for programming the device when VDD is already applied, for it is not necessary to
disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 3-2.
Figure 3-2.ꢀPROGRAMMING ENTRY AND EXIT MODES – VDD-First and Last
PROGRAMMING MODE ENTRY – ENTRY
VDD-First
PROGRAMMING MODE ENTRY – EXIT
VDD-Last
TENTS
TENTH
TEXIT
VDD
VPP
VIHH
VIL
ICSPDAT
ICSPCLK
3.1.1.3 Program/Verify Mode Exit
To exit Program/Verify mode, lower MCLR from VIHH to VIL. VPP-First Entry mode should use VPP-Last Exit mode (see
Figure 3-1). VDD-First Entry mode should use VDD-Last Exit mode (see Figure 3-2).
3.1.2
Low-Voltage Programming (LVP) Mode
The Low-Voltage Programming mode allows the devices to be programmed using VDD only, without high voltage.
When the LVP bit in the Configuration Byte register is set to ‘1’, the Low-Voltage ICSP Programming entry is enabled.
To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify mode requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on ICSPDAT, clocked by ICSPCLK. The LSb of the pattern is a “don’t
care X”. The Program/Verify mode entry pattern detect hardware verifies only the first 31 bits of the sequence
and the last clock is required before the pattern detect goes active.
The key sequence is a specific 32-bit pattern, ‘32’h4d434850’ (more easily remembered as MCHP in ASCII). The
device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit of the Most Significant
Byte must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/
Verify mode is to be maintained. For Low-Voltage Programming timing, see Figure 3-3 and Figure 3-4.
DS40002143B-page 12
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-3.ꢀLVP Entry (Powering Up)
VDD
MCLR
TENTS
TENTH
32 Clocks
TENTH
TCKH
TCKL
ICSPCLK
ICSPDAT
TDH
TDS
MSb of Pattern
31
LSb of Pattern
30
29
1
Figure 3-4.ꢀLVP Entry (Powered)
VDD
MCLR
TENTH
TENTH
32 Clocks
TCKH
TCKL
ICSPCLK
TDH
TDS
MSb of Pattern
LSb of Pattern
31
30
29
1
ICSPDAT
Exiting Program/Verify mode is done by raising MCLR from below VIL to VIH level (or higher, up to VDD).
Important:ꢀ
To enter LVP mode, the MSb of the Most Significant nibble must be shifted in first. This differs from
entering the key sequence on some other device families.
3.1.3
Program/Verify Commands
Once a device has entered ICSP Program/Verify mode (using either high-voltage or LVP entry), the programming
host device may issue six commands to the microcontroller, each eight bits in length. The commands are
summarized in Table 3-1. The commands are used to erase or program the device based on the location of the
Program Counter (PC).
Some of the 8-bit commands also have an associated data payload (such as Load PC Address and Read Data from
NVM).
If the host device issues an 8-bit command byte that has an associated data payload, the host device is responsible
for sending an additional 24 clock pulses (for example, three 8-bit bytes) in order to send or receive the payload data
associated with the command.
The payload field size is used so as to be compatible with many 8-bit SPI-based systems. Within each 24-bit payload
field, the first bit transmitted is always a Start bit, followed by a variable number of Pad bits, followed by the useful
data payload bits and ending with one Stop bit. The useful data payload bits are always transmitted, Most Significant
bit (MSb) first.
DS40002143B-page 13
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
When the programming device issues a command that involves a host to microcontroller payload (for example, Load
PC Address), the Start, Stop and Pad bits should all be driven by the programmer to ‘0’. When the programming host
device issues a command that involves microcontroller to host payload data (for example, Read Data from NVM), the
Start, Stop and Pad bits should be treated as “don't care” bits and the values should be ignored by the host.
When the programming host device issues an 8-bit command byte to the microcontroller, the host should wait a
specified minimum amount of delay (which is command-specific) prior to sending any additional clock pulses
(associated with either a 24-bit data payload field or the next command byte).
(1)
™
Table 3-1.ꢀ ICSP COMMAND SET SUMMARY
Command Name
Command Value
Payload
Expected
Delay after
Command
Data/Note
Binary (MSb …
LSb)
Hex
1000 0000
Load PC Address
Bulk Erase
80
Yes
Yes
TDLY
Payload Value =
PC
0001 1000
18
TERAB
The payload
carries the
information of the
regions that need
to be bulk
erased.
1111 0000
1111 11J0
Page Erase
Program Memory
F0
No
TERAS
The page
addressed by the
MSbs of the PC
is erased; LSbs
are ignored
Read Data from
NVM
FC/FE
Yes
TDLY
Data output ‘0’ if
code-protect is
enabled: J = 0:
PC is unchanged
J = 1: PC = PC +
n(2) after reading
1111 1000
11J0 0000
Increment
Address
F8
No
TDLY
PC = PC + n(2)
Program Data
C0/E0
Yes
TPROG
Payload value =
Data Word J = 0:
PC is unchanged
J = 1: PC = PC +
n after writing
Important:ꢀ
1. All clock pulses for both the 8-bit commands and the 24-bit payload fields are generated by the host
programming device. The microcontroller does not drive the ICSPCLK line. The ICSPDAT signal is
a bidirectional data line. For all commands and payload fields, except the Read Data from NVM
payload, the host programming device continuously drives the ICSPDAT line. Both the host
programmer device and the microcontroller should latch received ICSPDAT values on the falling
edge of the ICSPCLK line. When the microcontroller receives ICSPDAT line values from the host
programmer, the ICSPDAT values must be valid a minimum of TDS before the falling edges of
ICSPCLK and should remain valid for a minimum of TDH after the falling edge of ICSPDAT. See
Figure 3-5.
2. PC is incremented by n = 1 for data memory, Configuration Bytes and n = 2 for all other regions.
DS40002143B-page 14
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-5.ꢀClock and Data Timing
TCKH
TCKL
ICSPCLK
TDS TDH
ICSPDAT
as
Input
TCO
ICSPDAT
as
Output
TLZD
ICSPDAT
from Input
to Output
THZD
ICSPDAT
from Output
to Input
3.1.3.1 Program Data
The Program Data command is used to program one NVM word (for example, one 16-bit instruction word for program
memory/User ID memory or one 8-bit data for a Data EEPROM Memory address). The payload data is written into
program or EEPROM memory immediately after the Programming Data command is issued (see Programming
Algorithms). Depending on the value of bit 5 of the command, the PC may or may not be incremented (see Table
3-1).
Figure 3-6.ꢀPROGRAM DATA (Program Memory and User IDs)
7
6
5
4
3
2
1
0
23
22
17
16
1
0
TPINT
TDLY
ICSPCLK
ICSPDAT
1
1
J
0
0
0
0
0
0
0
0
MSb
LSb
0
Start Bit
Stop Bit
8-Bit Command
24-Bit Payload Field
Figure 3-7.ꢀPROGRAM DATA (DATA EEPROM and Configuration Bytes)
7
6
5
4
3
2
1
0
23
22
9
8
1
0
TPDFM
TDLY
ICSPCLK
ICSPDAT
1
1
J
0
0
0
0
0
0
0
0
MSb
LSb
0
Start Bit
Stop Bit
8-Bit Command
24-Bit Payload Field
DS40002143B-page 15
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
3.1.3.2 Read Data from NVM
The Read Data from the NVM command will transmit data bits out of the current PC address. The ICSPDAT pin will
go into Output mode on the first falling edge of the ICSP data payload clock and it will revert to Input mode (high-
impedance) after the 24th falling edge of the ICSP data payload clock. The Start and Stop bits are only one-half of a
bit time wide; therefore, they should be ignored by the host programmer device, since the latched value may be
indeterminate. Additionally, the host programmer device should only consider the MSb to LSb payload bits as valid
and should ignore the values of the Pad bits. If the memory region is code-protected (CP or DP), the data will be read
as zeros (see Figure 3-8 and Figure 3-9). Depending on the value of bit 1 of the command, the PC may or may not
be incremented (see Table 3-1). The Read Data from the NVM command can be used to read data for Program Flash
Memory (see Figure 3-8) or the Data EEPROM Memory (see Figure 3-9).
Figure 3-8.ꢀREAD DATA FROM NVM (PFM and User IDs)
7
6
5
4
3
2
1
0
23
22
17
16
1
0
TDLY
TDLY
ICSPCLK
High-Z
ICSPDAT (from
programmer)
1
1
1
1
1
1
J
0
High-Z
0
0
0
0
MSb Data LSb
ICSPDAT
(from device)
Stop
Start
Input
Output
Input
Figure 3-9.ꢀREAD DATA FROM NVM (DATA EEPROM and Configuration Bytes)
7
6
5
4
3
2
1
0
23
22
9
8
1
0
TDLY
TDLY
ICSPCLK
High-Z
ICSPDAT (from
Programmer)
1
1
1
1
1
1
J
0
High-Z
0
0
0
0
MSb Data LSb
ICSPDAT
(from device)
Start
Stop
Input
Output
Input
3.1.3.3 Increment Address
The address is incremented when this command is received. Depending on the current value of the Program
Counter, the increment varies. If the PC points to PFM, then the PC is incremented by 2; if the PC points to the data
EEPROM or Configuration Space, then it is incremented by 1. It is not possible to decrement the address. To reset
the Program Counter, the user must use the Load PC Address command.
DS40002143B-page 16
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-10.ꢀINCREMENT ADDRESS
Next Command
7
6
5
4
3
2
1
0
7
6
5
TDLY
ICSPCLK
ICSPDAT
1
1
1
1
1
0
0
0
x
x
x
Address
Address + 1
3.1.3.4 Load PC Address
The PC value is set using the supplied data. The address indicates the memory location (PFM or Data EEPROM
Memory or Configuration memory) to be accessed (see Figure 3-11).
Figure 3-11.ꢀLOAD PC ADDRESS
7
6
5
4
3
2
1
0
23
22
1
0
TDLY
TDLY
ICSPCLK
ICSPDAT
MSb
LSb
1
0
0
0
0
0
0
0
0
Address
0
Start
Stop
3.1.3.5 Bulk Erase
The Bulk Erase command is used to completely erase different memory regions. The area selection is a bit field in
the payload.
By setting the following bits of the payload, the corresponding memory regions can be bulk erased. Setting multiple
bits is valid.
1. Bit 1: Data EEPROM
2. Bit 2: Flash memory
3. Bit 3: User ID memory
4. Bit 4: Configuration memory
Important:ꢀ If the device is code-protected and a Bulk Erase command for the configuration memory is
issued, all other regions are also bulk erased.
After receiving the Bulk Erase command, the erase will complete after the time interval TERAB. See Figure 3-12 for
Bulk Erase command structure.
DS40002143B-page 17
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-12.ꢀBULK ERASE MEMORY
TERAB
3.1.3.6 Page Erase Program Memory
The Page Erase Program Memory command will erase an individual page based on the current address of the
Program Counter. If the program memory is code-protected, the Page Erase Memory command will be ignored. The
Bulk Erase command must be used to erase code-protected memory.
The Flash memory page defined by the current PC will be erased. The user must wait TERAS for erasing to be
complete (see Figure 3-13). Page Erase may be used for program memory and User ID regions only. Configuration
and data regions must be erased with the Bulk Erase method.
Figure 3-13.ꢀPAGE ERASE MEMORY
Next Command
7
6
5
4
3
2
1
0
7
6
5
TERAS
ICSPCLK
ICSPDAT
1
1
1
1
0
0
0
0
x
x
x
3.2
Programming Algorithms
The Program Flash Memory and User ID are programmed one word at a time. The EEPROM memory and
Configuration regions are programmed one byte at a time.
DS40002143B-page 18
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-14.ꢀDEVICE PROGRAM/VERIFY FLOWCHART
START
Enter Programming
Mode
Bulk Erase Device
Write Program Memory(1)
Verify Program Memory
Write Data
EEPROM
Verify Data
EEPROM
Write User IDs
Verify User IDs
Write Configuration
Bytes
Exit Programming
Mode
Done
Note:ꢀ
1. See Figure 3-15.
2. See Figure 3-17.
DS40002143B-page 19
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-15.ꢀPROGRAM MEMORY FLOWCHART
Start
Bulk Erase Program
Memory(1)
Load PC Address
(00 0000h)
One-Word Program Cycle(2)
(Program Data)
Read from NVM
Command
Data
No
Report Programming
Failure
Correct?
No
Yes
Increment PC Address
All Locations
Yes
Done
Done?
Note:ꢀ
1. This step is optional if the device has already been erased or has not been previously programmed.
2. If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 3-18.
DS40002143B-page 20
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-16.ꢀONE-WORD PROGRAM CYCLE
Program Cycle
(For programming Data, EEPROM, User ID and Configuration Bytes)
Load PC with Address
Program Data Command
Wait TPINT
DS40002143B-page 21
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-17.ꢀUSER ID AND CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load PC Address
(select Bulk Erase
regions)
Bulk Erase
Program Memory(1)
Load PC Address
(First Address of User ID
Space)
One-Word Program
Cycle(2)
(User ID)
Read from NVM
Command
Data
No
Report Programming
Failure
Correct?
No
Yes
Increment PC
Address
Load PC Address
Address =
Yes
(First Address of
Configuration Space)
Last address of
User ID space?
One-Word Program
Cycle(2)
(Config. Byte)
Read from NVM
Command
Data
Correct?
Report Programming
Failure
No
No
Yes
Increment PC
Address
Address =
Last address of
Configuration
Space?
Yes
Done
Note:ꢀ
1. This step is optional if the device has already been erased or has not been previously programmed.
2. See Figure 3-16.
DS40002143B-page 22
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Figure 3-18.ꢀBULK ERASE FLOWCHART
Start
Bulk Erase Command with
payload containing area
selections for bulk erase
Wait TERAB for Operation
to complete
Done
3.3
Code Protection
Code protection is controlled using the CP bit. When code protection is enabled, all program memory and Data
EEPROM locations read as ‘0’. Further programming is disabled for the program memory and Data EEPROM until a
Bulk Erase operation is performed on the configuration memory region. Program memory and Data EEPROM can
still be programmed and read during program execution.
The User ID locations and Configuration Bytes can be programmed and read out regardless of the code protection
settings.
The only way to disable code protection is to use the Bulk Erase Program Memory command with bit 4 of the payload
set to ‘1’. This will clear the disable code protection and also erase all the memory locations.
3.4
Hex File Usage
3.4.1
Embedding Configuration Information in the HEX File
To allow portability of code, a programmer is required to read the Configuration Byte locations from the Hex file. If
Configuration Byte information is not present in the Hex file, then a simple warning message should be issued.
Similarly, when saving a Hex file, all Configuration Byte information should be included. An option to not include the
Configuration Byte information may be provided. When embedding Configuration Byte information in the Hex file, it
should start at address 30 0000h.
Important:ꢀ
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
3.4.2
Embedding Data EEPROM Information in the HEX File
To allow portability of code, a programmer is required to read the data EEPROM information from the Hex file. If data
EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a Hex file,
all data EEPROM information must be included. An option to not include the data EEPROM information may be
provided. When embedding data EEPROM information in the Hex file, it should start at address 38 0000h.
DS40002143B-page 23
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Programming Algorithms
Important:ꢀ
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
3.5
CRC Checksum Computation
Unlike older PIC® devices, the Microchip toolchain runs a 32-bit CRC calculation on the entire hex file to calculate its
checksum. The checksum uses the standard CRC-32 algorithm with the polynomial 0x4C11DB7
32
26
23
22
16
12
11
10
8
7
5
4
2
ꢀ
+ ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + ꢀ + 1 .
DS40002143B-page 24
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Electrical Specifications
4.
Electrical Specifications
Refer to the device-specific data sheet for absolute maximum ratings.
Table 4-1.ꢀAC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions Production tested
AC/DC CHARACTERISTICS
at +25°C
Sym.
Characteristics
Min. Typ. Max. Units Conditions/Comments
Programming Supply Voltages and Currents
VDD Supply Voltage (VDDMIN, VDDMAX
)
1.80
VDDMIN
VBORMAX
—
—
—
—
—
—
5.50
VDDMAX
VDDMAX
1.0
V
V
(Note 1)
(Note 2)
VPEW Read/Write and Page Erase Operations
VBE Bulk Erase Operations
V
IDDI Current on VDD, Idle
mA
mA
IDDP Current on VDD, Programming
—
10
VPP
IPP
Current on MCLR/VPP
—
—
—
600
9.0
µA
V
High Voltage on MCLR/VPP for Program/Verify Mode
Entry
7.9
VIHH
MCLR Rise Time (VIL to VIHH) for Program/Verify
—
—
1.0
µs
T
VHHR Mode Entry
I/O Pins
VIH
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) Input High Level
(ICSPCLK, ICSPDAT, MCLR/VPP) Input Low Level
0.8 VDD
VSS
—
—
—
VDD
0.2 VDD
—
V
V
V
V
VOH ICSPDAT Output High Level
VOL ICSPDAT Output Low Level
VDD-0.7
—
IOH = 3 mA, VDD = 3.0V
IOL = 6 mA, VDD = 3.0V
— VSS + 0.6
Programming Mode Entry and Exit
Programing Mode Entry Setup Time: ICSPCLK,
ICSPDAT Setup Time before VDD or MCLR↑
100
—
—
—
ns
TENTS
Programing Mode Entry Hold Time: ICSPCLK,
ICSPDAT Hold Time before VDD or MCLR↑
1
—
ms
TENTH
Serial Program/Verify
TCKL Clock Low Pulse Width
100
100
100
100
—
—
—
—
—
—
—
—
—
80
ns
ns
ns
ns
ns
TCKH Clock High Pulse Width
TDS Data in Setup Time before Clock↓
TDH Data in Hold Time after Clock↓
Clock↑ to Data Out Valid (during a Read Data
command)
0
TCO
Clock↓ to Data Low-Impedance (during a Read Data
from NVM command)
0
—
—
—
80
80
—
ns
ns
µs
TLZD
Clock↓ to Data High-Impedance (during a Read Data
from NVM command)
0
THZD
Data Input not Driven to Next Clock Input (delay
1.0
TDLY required between command/data or command/
command)
TERAB Bulk Erase Cycle Time
TERAS Page Erase Cycle Time
—
—
—
—
—
—
11
11
11
ms Program, Config and ID
ms
Internally Timed DFM (EEPROM) Programming
ms EEPROM Memory and
Configuration Bytes
T
PDFM Operation Time
TPINT Internally Timed Programming Operation Time
—
—
75
µs Program Memory and
Configuration Bytes
DS40002143B-page 25
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
Electrical Specifications
...........continued
AC/DC CHARACTERISTICS
Characteristics
Standard Operating Conditions Production tested
at +25°C
Sym.
Min. Typ. Max. Units Conditions/Comments
TEXIT Time Delay when Exiting Program/Verify Mode
1
—
—
µs
Note:ꢀ
1. Bulk erased devices default to Brown-out Reset enabled with BORV = 11(low trip point). VDDMIN is the VBOR
threshold (with BORV = 1) when performing Low-Voltage Programming on a bulk erased device to ensure that
the device is not held in Brown-out Reset.
2. The hardware requires VDD to be above the BOR threshold, at the ~1.9V nominal setting, in order to perform
Bulk Erase operations. This threshold does not depend on the BORV Configuration bit settings. Refer to the
microcontroller device data sheet specifications for min./typ./max. limits of the VBOR level.
DS40002143B-page 26
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX A: Revision History
5.
APPENDIX A: Revision History
Doc Rev.
Date
Comments
B
A
10/2019
09/2019
Updated Table 4-1 - TPINT from 50 µs to 75 µs.
Initial document release.
DS40002143B-page 27
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.
APPENDIX B
This section provides information about the Device IDs and Pinout Descriptions
Table 6-1.ꢀProgramming Pin Locations By Package Type
VDD
PIN
VSS
MCLR
PORT
ICSPCLK
ICSPDAT
Package
Code
Device
Package
PIN
PIN
PIN
PORT
PIN
PORT
14-Pin
SOIC
D3X
D4X
D5X
G6X
G5X
G3X
REB
1
1
14
4
RA3
RA3
RA3
RA3
RA3
RA3
RA3
12
RA1
13
13
12
19
19
19
16
RA0
PIC18F04Q41
PIC18F05Q41
PIC18F06Q41
14-Pin
TSSOP
14
13
20
20
20
17
4
3
4
4
4
1
12
11
18
18
18
15
RA1
RA1
RA1
RA1
RA1
RA1
RA0
RA0
RA0
RA0
RA0
RA0
16-Pin
VQFN
16
1
20-Pin
PDIP
20-Pin
SOIC
1
PIC18F14Q41
PIC18F15Q41
PIC18F16Q41
20-Pin
SSOP
1
20-Pin
VQFN
18
Note:ꢀ
The most current package drawings are located in the Microchip Packaging Specification, DS00000049 (http://
www.microchip.com/packaging). The drawing numbers listed above do not include the current revision designator,
which is added at the end of the number.
DS40002143B-page 28
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.1
CONFIG1
Name:ꢀ
CONFIG1
Address:ꢀ 30 0000h
Configuration Byte 1
Bit
7
6
5
4
3
2
1
0
RSTOSC[2:0]
FEXTOSC[2:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bits 6:4 – RSTOSC[2:0]ꢀPower-up Default Value for COSC
This value is the Reset default value for COSC and selects the oscillator first used by user software. Refer to COSC
operation.
Value
111
Description
EXTOSC operating per FEXTOSC bits
110
HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1. Resets COSC/NOSC to b'110'.
101
100
011
010
001
000
LFINTOSC
SOSC
Reserved
EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
Reserved
HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1. Resets COSC/NOSC to b'110'.
Bits 2:0 – FEXTOSC[2:0]ꢀExternal Oscillator Mode Selection
Value
111
110
101
100
011
010
001
000
Description
ECH (external clock) above 8 MHz
ECM (external clock) for 500 kHz to 8 MHz
ECL (external clock) below 500 kHz
Oscillator not enabled
Reserved (do not use)
HS (crystal oscillator) above 4 MHz
XT (crystal oscillator) above 500 kHz, below 4 MHz
LP (crystal oscillator) optimized for 32.768 kHz
DS40002143B-page 29
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.2
CONFIG2
Name:ꢀ
CONFIG2
Address:ꢀ 30 0001h
Configuration Byte 2
Bit
7
FCMENS
R/W
6
FCMENP
R/W
5
FCMEN
R/W
1
4
3
CSWEN
R/W
1
2
1
PR1WAY
R/W
0
CLKOUTEN
Access
Reset
R/W
1
1
1
1
Bit 7 – FCMENSꢀFail-Safe Clock Monitor Enable - Secondary XTAL Enable
Value
Description
1
0
Fail-Safe Clock Monitor enabled; timer will flag FSCMS bit and OSFIF interrupt on SOSC failure.
Fail-Safe Clock Monitor disabled
Bit 6 – FCMENPꢀFail-Safe Clock Monitor Enable - Primary XTAL Enable
Value
Description
1
0
Fail-Safe Clock Monitor enabled; timer will flag FSCMP bit and OSFIF interrupt on EXTOSC failure.
Fail-Safe Clock Monitor disabled
Bit 5 – FCMENꢀFail-Safe Clock Monitor Enable
Value
Description
1
0
Fail-Safe Clock Monitor enabled
Fail-Safe Clock Monitor disabled
Bit 3 – CSWENꢀClock Switch Enable
Value
Description
1
0
Writing to NOSC and NDIV is allowed
The NOSC and NDIV bits cannot be changed by user software
Bit 1 – PR1WAYꢀPRLOCKED One-Way Set Enable
Value
Description
1
PRLOCKED bit can be cleared and set only once; Priority registers remain locked after one clear/set
cycle
0
PRLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
Bit 0 – CLKOUTENꢀClock Out Enable
If FEXTOSC = HS, XT, LP, then this bit is ignored.
Otherwise:
Value
Description
1
0
CLKOUT function is disabled; I/O function on OSC2
CLKOUT function is enabled; FOSC/4 clock appears at OSC2
DS40002143B-page 30
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.3
CONFIG3
Name:ꢀ
CONFIG3
Address:ꢀ 30 0002h
Configuration Byte 3
Bit
7
6
5
LPBOREN
R/W
4
IVT1WAY
R/W
3
MVECEN
R/W
2
1
0
MCLRE
R/W
1
BOREN[1:0]
PWRTS[1:0]
Access
Reset
R/W
0
R/W
1
R/W
1
R/W
1
1
1
1
Bits 7:6 – BOREN[1:0]ꢀBrown-out Reset Enable
When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit
Value
11
Description
Brown-out Reset enabled, SBOREN bit is ignored
10
01
00
Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored
Brown-out Reset enabled according to SBOREN
Brown-out Reset disabled
Bit 5 – LPBORENꢀLow-Power BOR Enable
Value
Description
1
0
Low-Power Brown-out Reset is disabled
Low-Power Brown-out Reset is enabled
Bit 4 – IVT1WAYꢀIVTLOCK One-Way Set Enable
Value
Description
1
0
IVTLOCK bit can be cleared and set only once; IVT registers remain locked after one clear/set cycle
IVTLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
Bit 3 – MVECENꢀMultivector Enable
Value
Description
1
0
Multivector is enabled; vector table used for interrupts
Legacy interrupt behavior
Bits 2:1 – PWRTS[1:0]ꢀPower-up Timer Selection
Value
11
10
01
00
Description
PWRT is disabled
PWRT is set at 64 ms
PWRT is set at 16 ms
PWRT is set at 1 ms
Bit 0 – MCLREꢀMaster Clear (MCLR) Enable
Value
x
1
0
Condition
If LVP = 1
If LVP = 0
If LVP = 0
Description
RA3 pin function is MCLR
MCLR pin is MCLR
MCLR pin function is port defined function
DS40002143B-page 31
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.4
CONFIG4
Name:ꢀ
CONFIG4
Address:ꢀ 30 0003h
Configuration Byte 4
Bit
7
XINST
R/W
1
6
5
4
STVREN
R/W
3
PPS1WAY
R/W
2
1
0
LVP
R/W
1
ZCD
R/W
1
BORV[1:0]
Access
Reset
R/W
1
R/W
1
1
1
Bit 7 – XINSTꢀExtended Instruction Set Enable
Value
Description
1
0
Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode)
Extended Instruction Set and Indexed Addressing mode enabled
Bit 5 – LVPꢀLow-Voltage Programming Enable
The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule
is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating
LVP mode from the Configuration state.
Value
Description
1
Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is
ignored.
0
HV on MCLR/VPP must be used for programming
Bit 4 – STVRENꢀStack Overflow/Underflow Reset Enable
Value
Description
1
0
Stack Overflow or Underflow will cause a Reset
Stack Overflow or Underflow will not cause a Reset
Bit 3 – PPS1WAYꢀPPSLOCKED One-Way Set Enable
Value
Description
1
The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK
is set, all future changes to PPS registers are prevented
0
The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required)
Bit 2 – ZCDꢀZCD Disable
Value
Description
1
0
ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
ZCD always enabled, PMDx[ZCDMD] bit is ignored
Bits 1:0 – BORV[1:0]ꢀ Brown-out Reset Voltage Selection(1)
Value
11
10
01
00
Description
Brown-out Reset Voltage (VBOR) set to 1.90 V
Brown-out Reset Voltage (VBOR) set to 2.45 V
Brown-out Reset Voltage (VBOR) set to 2.7 V
Brown-out Reset Voltage (VBOR) set to 2.85 V
Note:ꢀ
1. The higher voltage setting is recommended for operation at or above 16 MHz.
DS40002143B-page 32
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.5
CONFIG5
Name:ꢀ
CONFIG5
Address:ꢀ 30 0004h
Configuration Byte 5
Bit
7
6
5
4
3
2
1
0
WDTE[1:0]
WDTCPS[4:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bits 6:5 – WDTE[1:0]ꢀWDT Operating Mode
Value
11
Description
WDT enabled regardless of Sleep; SEN bit in WDTCON0 is ignored
10
01
00
WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit in WDTCON0 is ignored
WDT enabled/disabled by SEN bit in WDTCON0
WDT disabled, SEN bit in WDTCON0 is ignored
Bits 4:0 – WDTCPS[4:0]ꢀWDT Period Select
WDTCON0[WDTPS] at POR
Typical Time Out
(FIN = 31 kHz)
WDTCPS
Software Control of WDTPS?
Value
Divider Ratio
1:65536 216
2s
1 ms
256s
128s
64s
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
11111
01011
25
11110 to 10011 11110 to 10011
1:32
1:8388608 223
1:4194304 222
1:2097152 221
1:1048576 220
1:524288 219
1:262144 218
1:131072 217
1:65536 216
1:32768 215
1:16384 214
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
32s
16s
8s
4s
2s
1s
512 ms
256 ms
128 ms
64 ms
32 ms
16 ms
8 ms
4 ms
2 ms
1 ms
1:8192
1:4096
1:2048
1:1024
1:512
1:256
1:128
1:64
213
212
211
210
29
28
27
26
1:32
25
DS40002143B-page 33
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.6
CONFIG6
Name:ꢀ
CONFIG6
Address:ꢀ 30 0005h
Configuration Byte 6
Bit
7
6
5
4
3
2
1
0
WDTCCS[2:0]
WDTCWS[2:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bits 5:3 – WDTCCS[2:0]ꢀWDT Input Clock Selector
Value
x
111
110 to
011
Condition
WDTE = 00
WDTE ≠ 00
WDTE ≠ 00
Description
These bits have no effect
Software Control
Reserved
010
001
000
WDTE ≠ 00
WDTE ≠ 00
WDTE ≠ 00
WDT reference clock is the SOSC
WDT reference clock is the 31.25 kHz MFINTOSC
WDT reference clock is the 31.0 kHz LFINTOSC
Bits 2:0 – WDTCWS[2:0]ꢀWDT Window Select
WDTCON1[WINDOW] at POR
Software control of
WINDOW
Keyed access
required?
WDTCWS
Window delay
Percent of time
Window opening
Percent of time
Value
111
110
101
100
011
010
001
000
111
110
101
100
011
010
001
000
n/a
n/a
25
100
100
75
Yes
No
37.5
50
62.5
50
No
Yes
62.5
75
37.5
25
87.5
12.5
DS40002143B-page 34
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.7
CONFIG7
Name:ꢀ
CONFIG7
Address:ꢀ 30 0006h
Configuration Byte 7
Bit
7
6
5
DEBUG
R/W
1
4
SAFEN
R/W
1
3
BBEN
R/W
1
2
1
0
BBSIZE[2:0]
Access
Reset
R/W
1
R/W
1
R/W
1
Bit 5 – DEBUGꢀDebugger Enable
Value
Description
1
0
Background debugger disabled
Background debugger enabled
Bit 4 – SAFENꢀ Storage Area Flash (SAF) Enable(1)
Value
Description
1
0
SAF is disabled
SAF is enabled
Bit 3 – BBENꢀ Boot Block Enable(1)
Value
Description
1
0
Boot Block is disabled
Boot Block is enabled
Bits 2:0 – BBSIZE[2:0]ꢀ Boot Block Size Selection(2)
Table 6-2.ꢀBoot Block Size
Boot Block Size (words)
End Address of
Boot Block
BBEN
BBSIZE
PIC18Fx4Q41
PIC18Fx5Q41
PIC18Fx6Q41
1
0
0
0
0
0
0
0
0
xxx
111
110
101
100
011
010
001
000
–
–
00 03FFh
00 07FFh
00 0FFFh
00 1FFFh
00 3FFFh
00 7FFFh
00 FFFFh
00 FFFFh
512
1024
2048
4096
–
8192
–
–
–
16384
Note:ꢀ
™
1. Once protection is enabled through ICSP or a self-write, it can only be reset through a Bulk Erase.
2. BBSIZE[2:0] bits can only be changed when BBEN = 1. Once BBEN = 0, BBSIZE[2:0] can only be changed
through a Bulk Erase.
DS40002143B-page 35
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.8
CONFIG8
Name:ꢀ
CONFIG8
Address:ꢀ 30 0007h
Configuration Byte 8
Bit
7
WRTAPP
R/W
6
5
4
3
WRTSAF
R/W
2
WRTD
R/W
1
1
WRTC
R/W
1
0
WRTB
R/W
1
Access
Reset
1
1
Bit 7 – WRTAPPꢀ Application Block Write Protection(1)
Value
Description
1
0
Application Block is NOT write-protected
Application Block is write-protected
Bit 3 – WRTSAFꢀ Storage Area Flash (SAF) Write Protection(1,2)
Value
Description
1
0
SAF is NOT write-protected
SAF is write-protected
Bit 2 – WRTDꢀ Data EEPROM Write Protection(1)
Value
Description
1
0
Data EEPROM is NOT write-protected
Data EEPROM is write-protected
Bit 1 – WRTCꢀ Configuration Register Write Protection(1)
Value
Description
1
0
Configuration registers are NOT write-protected
Configuration registers are write-protected
Bit 0 – WRTBꢀ Boot Block Write Protection(1,3)
Value
Description
1
0
Boot Block is NOT write-protected
Boot Block is write-protected
Note:ꢀ
™
1. Once protection is enabled through ICSP or a self-write, it can only be reset through a Bulk Erase.
2. Applicable only if SAFEN = 0.
3. Applicable only if BBEN = 0.
DS40002143B-page 36
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
APPENDIX B
6.9
CONFIG9
Name:ꢀ
CONFIG9
Address:ꢀ 30 0008h
Configuration Byte 9
Bit
7
6
5
4
3
2
1
0
CP
R/W
1
Access
Reset
Bit 0 – CPꢀ User Program Flash Memory and Data EEPROM Code Protection
Value
Description
1
0
User Program Flash Memory and Data EEPROM code protection are disabled
User Program Flash Memory and Data EEPROM code protection are enabled
DS40002143B-page 37
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
The Microchip Website
Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files
and information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
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Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these
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specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
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•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
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may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with
DS40002143B-page 38
Programming Specification
© 2019 Microchip Technology Inc.
PIC18FXXQ41
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER
EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,
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©
2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-5163-1
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For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.
DS40002143B-page 39
Programming Specification
© 2019 Microchip Technology Inc.
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DS40002143B-page 40
Programming Specification
© 2019 Microchip Technology Inc.
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