PIC18F2320-E/SO [MICROCHIP]
8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PDSO28, 0.300 INCH, PLASTIC, MS-013, SO-28;
| 型号： | PIC18F2320-E/SO |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PDSO28, 0.300 INCH, PLASTIC, MS-013, SO-28 闪存 微控制器 |
| 文件： | 总388页 (文件大小：6899K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F2220/2320/4220/4320
Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
2003 Microchip Technology Inc.
DS39599C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS39599C-page ii
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
28/40/44-Pin High-Performance, Enhanced Flash MCUs
with 10-bit A/D and nanoWatt Technology
Low-Power Features:
Peripheral Highlights:
• Power Managed modes:
• High current sink/source 25 mA/25 mA
• Three external interrupts
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Power Consumption modes:
- PRI_RUN: 150 µA, 1 MHz, 2V
- PRI_IDLE: 37 µA, 1 MHz, 2V
- SEC_RUN: 14 µA, 32 kHz, 2V
- SEC_IDLE: 5.8 µA, 32 kHz, 2V
- RC_RUN: 110 µA, 1 MHz, 2V
- RC_IDLE: 52 µA, 1 MHz, 2V
- Sleep: 0.1 µA, 1 MHz, 2V
• Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution is 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution is 100 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
• Enhanced Capture/Compare/PWM (ECCP) module:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead-time
- Auto-Shutdown and Auto-Restart
• Compatible 10-bit, up to 13-channel
Analog-to-Digital Converter module (A/D) with
programmable acquisition time
• Timer1 Oscillator: 1.1 µA, 32 kHz, 2V
• Watchdog Timer: 2.1 µA
• Two-Speed Oscillator Start-up
• Dual analog comparators
• Addressable USART module:
- RS-232 operation using internal oscillator
block (no external crystal required)
Oscillators:
• Four Crystal modes:
- LP, XT, HS: up to 25 MHz
Special Microcontroller Features:
- HSPLL: 4-10 MHz (16-40 MHz internal)
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Internal oscillator block:
- 8 user selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
- 125 kHz-8 MHz calibrated to 1%
- Two modes select one or two I/O pins
- OSCTUNE – Allows user to shift frequency
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor
• 100,000 erase/write cycle Enhanced Flash program
memory typical
• 1,000,000 erase/write cycle Data EEPROM memory
typical
• Flash/Data EEPROM Retention: > 40 years
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
- 2% stability over VDD and Temperature
• Single-supply 5V In-Circuit Serial Programming™
(ICSP™) via two pins
- Allows for safe shutdown if peripheral clock stops
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
Program Memory
Data Memory
MSSP
CCP/
10-bit
A/D (ch)
Timers
8/16-bit
Device
I/O
ECCP
USART
Flash # Single Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
Master
SPI™
2
(PWM)
I C™
PIC18F2220
PIC18F2320
PIC18F4220
PIC18F4320
4096
8192
4096
8192
2048
4096
2048
4096
512
512
512
512
256
256
256
256
25
25
36
36
10
10
13
13
2/0
2/0
1/1
1/1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2/3
2/3
2/3
2/3
2003 Microchip Technology Inc.
DS39599C-page 1
PIC18F2220/2320/4220/4320
Pin Diagrams
PDIP
MCLR/VPP/RE3
RA0/AN0
1
2
3
4
RB7/KBI3/PGD
RB6/KBI2/PGC
40
39
38
37
36
35
34
33
32
31
30
29
28
RA1/AN1
RA2/AN2/VREF-/CVREF
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2*
RB2/AN8/INT2
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
5
6
7
8
RA5/AN4/SS/LVDIN/C2OUT
RE0/AN5/RD
RB1/AN10/INT1
RB0/AN12/INT0
VDD
RE1/AN6/WR
RE2/AN7/CS
9
10
11
12
13
14
15
16
17
18
19
20
VSS
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
27
26
25
24
23
22
21
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
SPDIP, SOIC
28
27
26
1
2
3
4
5
6
7
8
9
RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2*
RB2/AN8/INT2
RB1/AN10/INT1
RB0/AN12/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
VSS
25
24
23
22
21
20
19
18
17
16
15
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
RC3/SCK/SCL
10
11
12
13
14
RC4/SDI/SDA
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 40-pin PIC16C7X devices.
DS39599C-page 2
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Pin Diagrams (Cont.’d)
TQFP
NC
33
32
31
30
29
28
27
26
25
24
23
RC7/RX/DT
1
2
3
4
5
6
7
8
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
PIC18F4220
PIC18F4320
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT
VDD
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2*
9
10
11
* RB3 is the alternate pin for the CCP2 pin multiplexing.
QFN
RC7/RX/DT
1
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VSS
VDD
33
RD4/PSP4
2
32
31
30
29
28
27
26
RD5/PSP5/P1B
3
RD6/PSP6/P1C
4
PIC18F4220
PIC18F4320
RD7/PSP7/P1D
5
VSS
VDD
VDD
NC
6
7
8
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
9
10
11
25
24
23
* RB3 is the alternate pin for the CCP2 pin multiplexing.
2003 Microchip Technology Inc.
DS39599C-page 3
PIC18F2220/2320/4220/4320
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 19
3.0 Power Managed Modes ............................................................................................................................................................. 29
4.0 Reset.......................................................................................................................................................................................... 43
5.0 Memory Organization................................................................................................................................................................. 53
6.0 Flash Program Memory.............................................................................................................................................................. 71
7.0 Data EEPROM Memory ............................................................................................................................................................. 81
8.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 85
9.0 Interrupts .................................................................................................................................................................................... 87
10.0 I/O Ports ................................................................................................................................................................................... 101
11.0 Timer0 Module ......................................................................................................................................................................... 117
12.0 Timer1 Module ......................................................................................................................................................................... 121
13.0 Timer2 Module ......................................................................................................................................................................... 127
14.0 Timer3 Module ......................................................................................................................................................................... 129
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 133
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 141
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 155
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 195
19.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 211
20.0 Comparator Module.................................................................................................................................................................. 221
21.0 Comparator Voltage Reference Module................................................................................................................................... 227
22.0 Low-Voltage Detect.................................................................................................................................................................. 231
23.0 Special Features of the CPU.................................................................................................................................................... 237
24.0 Instruction Set Summary.......................................................................................................................................................... 255
25.0 Development Support............................................................................................................................................................... 299
26.0 Electrical Characteristics.......................................................................................................................................................... 305
27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 343
28.0 Packaging Information.............................................................................................................................................................. 361
Appendix A: Revision History............................................................................................................................................................. 369
Appendix B: Device Differences......................................................................................................................................................... 369
Appendix C: Conversion Considerations ........................................................................................................................................... 370
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 370
Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 371
Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 371
Index .................................................................................................................................................................................................. 373
On-Line Support................................................................................................................................................................................. 383
Systems Information and Upgrade Hot Line ...................................................................................................................................... 383
Reader Response .............................................................................................................................................................................. 384
PIC18F2220/2320/4220/4320 Product Identification System ............................................................................................................ 385
DS39599C-page 4
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
2003 Microchip Technology Inc.
DS39599C-page 5
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 6
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
• PIC18F2220
• PIC18F2320
• PIC18F4220
• PIC18F4320
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
low-speed operation or a safe application shutdown.
This family offers the advantages of all PIC18 micro-
controllers – namely, high computational performance
at an economical price with the addition of high-
endurance Enhanced Flash program memory. On top
of these features, the PIC18F2220/2320/4220/4320
family introduces design enhancements that make
these microcontrollers a logical choice for many
high-performance, power sensitive applications.
• Two-Speed Start-up: This option allows the internal
oscillator to serve as the clock source from Power-on
Reset, or wake-up from Sleep mode, until the primary
clock source is available. This allows for code execu-
tion during what would otherwise be the clock start-up
interval and can even allow an application to perform
routine background activities and return to Sleep
without returning to full power operation.
1.1
New Core Features
1.1.1
nanoWatt TECHNOLOGY
All of the devices in the PIC18F2220/2320/4220/4320
family incorporate a range of features that can signifi-
cantly reduce power consumption during operation.
Key items include:
1.2
Other Special Features
• Memory Endurance: The Enhanced Flash cells for
both program memory and data EEPROM are rated
to last for many thousands of erase/write cycles – up
to 100,000 for program memory and 1,000,000 for
EEPROM. Data retention without refresh is
conservatively estimated to be greater than 40 years.
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled, but the peripherals are
still active. In these states, power consumption can
be reduced even further, to as little as 4% of normal
operation requirements.
• Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top of pro-
gram memory, it becomes possible to create an
application that can update itself in the field.
• On-the-fly Mode Switching: The power managed
modes are invoked by user code during operation,
allowing the user to incorporate power saving ideas
into their application’s software design.
• Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers. Other
features include Auto-Shutdown for disabling PWM
outputs on interrupt or other select conditions and
Auto-Restart to reactivate outputs once the
condition has cleared.
• Lower Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer have been reduced by up to 80%, with typical
values of 1.8 and 2.2 µA, respectively.
• Addressable USART: This serial communication
module is capable of standard RS-232 operation
using the internal oscillator block, removing the
need for an external crystal (and its accompanying
power requirement) in applications that talk to the
outside world.
1.1.2
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2220/2320/4220/4320
family offer nine different oscillator options, allowing
users a wide range of choices in developing application
hardware. These include:
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a chan-
nel to be selected and a conversion to be initiated
without waiting for a sampling period and thus,
reduce code overhead.
• Four Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input with the
second pin reassigned as general I/O).
• Extended Watchdog Timer (WDT): This enhanced
version incorporates a 16-bit prescaler, allowing a
time-out range from 4 ms to over 2 minutes, that is
stable across operating voltage and temperature.
• Two External RC Oscillator modes with the same
pin options as the External Clock modes.
• An internal oscillator block, which provides a 31 kHz
INTRC clock and an 8 MHz clock with 6 program
selectable divider ratios (4 MHz to 125 kHz) for a
total of 8 clock frequencies.
2003 Microchip Technology Inc.
DS39599C-page 7
PIC18F2220/2320/4220/4320
3. I/O ports (3 bidirectional ports and 1 input only
port on PIC18F2X20 devices, 5 bidirectional
ports on PIC18F4X20 devices)
1.3
Details on Individual Family
Members
Devices in the PIC18F2220/2320/4220/4320 family are
available in 28-pin (PIC18F2X20) and 40/44-pin
(PIC18F4X20) packages. Block diagrams for the two
groups are shown in Figure 1-1 and Figure 1-2.
4. CCP and Enhanced CCP implementation
(PIC18F2X20 devices have 2 standard CCP
modules, PIC18F4X20 devices have one
standard CCP module and one ECCP module)
The devices are differentiated from each other in five
ways:
5. Parallel Slave Port (present only on
PIC18F4X20 devices)
1. Flash program memory (4 Kbytes for
PIC18FX220 devices, 8 Kbytes for PIC18FX320)
All other features for devices in this family are identical.
These are summarized in Table 1-1.
2. A/D channels (10 for PIC18F2X20 devices, 13 for
PIC18F4X20 devices)
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F2220
PIC18F2320
PIC18F4220
PIC18F4320
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Data EEPROM Memory (Bytes)
Interrupt Sources
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
4096
8192
4096
512
256
19
4096
2048
512
256
20
8192
4096
512
256
20
2048
512
256
19
I/O Ports
Ports A, B, C (E)
Ports A, B, C (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers
4
2
0
4
2
0
4
1
1
4
1
1
Capture/Compare/PWM Modules
Enhanced Capture/
Compare/PWM Modules
Serial Communications
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
Parallel Communications (PSP)
10-bit Analog-to-Digital Module
Resets (and Delays)
No
No
Yes
Yes
10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
POR, BOR, POR, BOR, POR, BOR, POR, BOR,
RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Programmable Low-Voltage
Detect
Yes
Yes
Yes
Yes
Programmable Brown-out Reset
Instruction Set
Yes
Yes
Yes
Yes
75 Instructions
75 Instructions
75 Instructions
75 Instructions
Packages
28-pin SPDIP
28-pin SOIC
28-pin SPDIP
28-pin SOIC
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
DS39599C-page 8
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 1-1:
PIC18F2220/2320 BLOCK DIAGRAM
Data Bus<8>
PORTA
Data Latch
Table Pointer <2>
inc/dec logic
21
8
8
8
8
RA0/AN0
RA1/AN1
Data RAM
(512 Bytes)
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
OSC2/CLKO/RA6(3)
OSC1/CLKI/RA7(3)
21
21
Address Latch
20
PCLATU PCLATH
PCU PCH PCL
12(2)
Address Latch
Program Memory
(4 Kbytes)
Address<12>
Program Counter
4
BSR
12
FSR0
4
PORTB
Data Latch
Bank0, F
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2(1)
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
FSR1
FSR2
31 Level Stack
12
16
inc/dec
logic
Decode
Table Latch
8
ROM Latch
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
Instruction
Register
8
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
PRODH PRODL
8 x 8 Multiply
3
8
WREG
8
BIT OP
8
OSC1(3)
OSC2(3)
T1OSI
Power-up
Timer
Internal
Oscillator
Block
8
Oscillator
Start-up Timer
8
INT RC
Oscillator
ALU<8>
Power-on
Reset
PORTE
T1OSO
8
Watchdog
Timer
Precision
Voltage
Reference
RE3(2)
Brown-out
Reset
Low-Voltage
Programming
MCLR(2)
VDD, VSS
Fail-Safe
Clock Monitor
In-Circuit
Debugger
Timer3
(16-bit)
Timer0
(8- or 16-bit)
Timer2
(8-bit)
Timer1
(16-bit)
10-bit A/D
Converter
Master
Synchronous
Serial Port
Addressable
USART
Data EEPROM
(256 Bytes)
CCP1
CCP2
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCPMX2 configuration bit.
2: RE3 is available only when the MCLR Resets are disabled.
3: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
2003 Microchip Technology Inc.
DS39599C-page 9
PIC18F2220/2320/4220/4320
FIGURE 1-2:
PIC18F4220/4320 BLOCK DIAGRAM
Data Bus<8>
PORTA
Data Latch
Data RAM
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Table Pointer <2>
inc/dec logic
21
8
8
8
8
(512 Bytes)
21
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
OSC2/CLKO/RA6(3)
OSC1/CLKI/RA7(3)
21
Address Latch
20
PCLATU PCLATH
12(2)
Address Latch
Program Memory
(8 Kbytes)
Address<12>
PCU PCH PCL
Program Counter
4
BSR
12
FSR0
4
PORTB
Data Latch
Bank0, F
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2(1)
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
FSR1
FSR2
31 Level Stack
12
16
inc/dec
logic
Decode
Table Latch
8
ROM Latch
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
Instruction
Register
8
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
PRODH PRODL
8 x 8 Multiply
3
PORTD
8
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
BIT OP
8
WREG
8
OSC1(3)
OSC2(3)
T1OSI
Internal
Oscillator
Block
Power-up
Timer
8
Oscillator
Start-up Timer
8
INT RC
Oscillator
ALU<8>
Power-on
Reset
T1OSO
8
Watchdog
Timer
PORTE
Precision
Voltage
Reference
RE0/AN5/RD
Brown-out
Reset
Low-Voltage
Programming
RE1/AN6/WR
RE2/AN7/CS
RE3(2)
(2)
MCLR
Fail-Safe
Clock Monitor
In-Circuit
Debugger
VDD, VSS
Timer1
(16-bit)
Timer2
(8-bit)
Timer3
(16-bit)
10-bit A/D
Converter
Timer0
(8- or 16-bit)
Master
Synchronous
Serial Port
Addressable
USART
Data EEPROM
(256 Bytes)
Enhanced
CCP
CCP2
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCP2MX configuration bit.
2: RE3 is available only when the MCLR Resets are disabled.
3: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
DS39599C-page 10
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 1-2:
PIC18F2220/2320 PINOUT I/O DESCRIPTIONS
Pin Number
PDIP SOIC
Pin Buffer
Type Type
Pin Name
Description
MCLR/VPP/RE3
MCLR
1
1
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low Reset
to the device.
I
ST
ST
VPP
RE3
P
I
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
9
9
Oscillator crystal or external clock input.
I
I
ST
CMOS
TTL
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)
General purpose I/O pin.
CLKI
RA7
I/O
OSC2/CLKO/RA6
OSC2
10
10
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
CLKO
RA6
I/O
TTL
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
2
3
4
2
3
4
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-/CVREF
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
CVREF
I
I
O
Analog
Analog
Analog
Analog input 2.
A/D Reference Voltage (Low) input.
Comparator Reference Voltage output.
RA3/AN3/VREF+
RA3
5
6
7
5
6
7
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
AN3
VREF+
RA4/T0CKI/C1OUT
RA4
I/O ST/OD
I
O
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
T0CKI
C1OUT
ST
—
RA5/AN4/SS/LVDIN/C2OUT
RA5
AN4
SS
LVDIN
C2OUT
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low-Voltage Detect input.
Comparator 2 output.
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
OD = Open-drain (no diode to VDD)
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
2: Alternate assignment for CCP2 when CCP2MX is cleared.
2003 Microchip Technology Inc.
DS39599C-page 11
PIC18F2220/2320/4220/4320
TABLE 1-2:
PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
PDIP SOIC
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0
RB0
21
22
23
24
25
26
27
28
21
22
23
24
25
26
27
28
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 12.
External interrupt 0.
AN12
INT0
RB1/AN10/INT1
RB1
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 10.
External interrupt 1.
AN10
INT1
RB2/AN8/INT2
RB2
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
AN8
INT2
RB3/AN9/CCP2
RB3
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture2 input, Compare2 output, PWM2 output.
AN9
CCP2(1)
RB4/AN11/KBI0
RB4
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
AN11
KBI0
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
KBI1
PGM
Interrupt-on-change pin.
Low-voltage ICSP programming enable pin.
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
OD = Open-drain (no diode to VDD)
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
2: Alternate assignment for CCP2 when CCP2MX is cleared.
DS39599C-page 12
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 1-2:
PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PDIP SOIC
Pin Buffer
Type Type
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
11
12
13
14
15
11
12
13
14
15
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
T1OSI
CCP2(2)
RC2/CCP1/P1A
RC2
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP1
P1A
Capture1 input/Compare1 output/PWM1 output.
Enhanced CCP1 output.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
SDI
SDA
RC5/SDO
RC5
16
17
16
17
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX
CK
USART asynchronous transmit.
USART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
18
18
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
USART asynchronous receive.
USART synchronous data (see related TX/CK).
RE3
VSS
VDD
—
—
—
P
—
—
—
See MCLR/VPP/RE3 pin.
8, 19 8, 19
20 20
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
CMOS = CMOS compatible input or output
P
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
OD = Open-drain (no diode to VDD)
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
2: Alternate assignment for CCP2 when CCP2MX is cleared.
2003 Microchip Technology Inc.
DS39599C-page 13
PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Description
Type Type
PDIP TQFP QFN
MCLR/VPP/RE3
MCLR
1
18
30
18
32
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
ST
VPP
RE3
P
I
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
13
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I
I
ST
CLKI
CMOS
RA7
I/O
TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
14
31
33
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
CLKO
RA6
I/O
TTL
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
2
3
4
19
20
21
19
20
21
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-/CVREF
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
CVREF
I
I
O
Analog
Analog
Analog
Analog input 2.
A/D reference voltage (Low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
5
6
7
22
23
24
22
23
24
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
AN3
VREF+
RA4/T0CKI/C1OUT
RA4
I/O ST/OD
I
O
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
T0CKI
C1OUT
ST
—
RA5/AN4/SS/LVDIN/
C2OUT
RA5
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
Low-Voltage Detect input.
Comparator 2 output.
AN4
SS
LVDIN
C2OUT
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
OD = Open-drain (no diode to VDD)
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
2: Alternate assignment for CCP2 when CCP2MX is cleared.
DS39599C-page 14
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP TQFP QFN
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0
RB0
33
34
35
36
37
38
39
40
8
9
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 12.
External interrupt 0.
AN12
INT0
RB1/AN10/INT1
RB1
9
10
11
12
14
15
16
17
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 10.
External interrupt 1.
AN10
INT1
RB2/AN8/INT2
RB2
10
11
14
15
16
17
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
AN8
INT2
RB3/AN9/CCP2
RB3
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture2 input, Compare2 output, PWM2 output.
AN9
CCP2(1)
RB4/AN11/KBI0
RB4
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
AN11
KBI0
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
KBI1
PGM
Interrupt-on-change pin.
Low-voltage ICSP programming enable pin.
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
OD = Open-drain (no diode to VDD)
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
2: Alternate assignment for CCP2 when CCP2MX is cleared.
2003 Microchip Technology Inc.
DS39599C-page 15
PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Description
Type Type
PDIP TQFP QFN
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
15
16
17
18
23
32
35
36
37
42
34
35
36
37
42
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
T1OSI
CCP2(2)
RC2/CCP1/P1A
RC2
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP1
P1A
Capture1 input/Compare1 output/PWM1 output.
Enhanced CCP1 output.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
SDI
SDA
RC5/SDO
RC5
24
25
43
44
43
44
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX
CK
USART asynchronous transmit.
USART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
26
1
1
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
USART asynchronous receive.
USART synchronous data (see related TX/CK).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
OD = Open-drain (no diode to VDD)
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
2: Alternate assignment for CCP2 when CCP2MX is cleared.
DS39599C-page 16
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP TQFP QFN
PORTD is a bidirectional I/O port or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.
RD0/PSP0
RD0
19
20
21
22
27
28
38
39
40
41
2
38
39
40
41
2
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP0
RD1/PSP1
RD1
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP1
RD2/PSP2
RD2
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP2
RD3/PSP3
RD3
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP3
RD4/PSP4
RD4
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP4
RD5/PSP5/P1B
RD5
3
3
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
PSP5
P1B
RD6/PSP6/P1C
RD6
29
30
4
5
4
5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
PSP6
P1C
RD7/PSP7/P1D
RD7
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
PSP7
P1D
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
OD = Open-drain (no diode to VDD)
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
2: Alternate assignment for CCP2 when CCP2MX is cleared.
2003 Microchip Technology Inc.
DS39599C-page 17
PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Description
Type Type
PDIP TQFP QFN
PORTE is a bidirectional I/O port.
RE0/AN5/RD
RE0
8
9
25
26
27
18
25
26
27
18
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 5.
Read control for Parallel Slave Port
(see also WR and CS pins).
AN5
RD
RE1/AN6/WR
RE1
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 6.
Write control for Parallel Slave Port
(see CS and RD pins).
AN6
WR
RE2/AN7/CS
RE2
10
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 7.
Chip select control for Parallel Slave Port
(see related RD and WR).
AN7
CS
RE3
VSS
1
—
P
—
—
See MCLR/VPP/RE3 pin.
12, 6, 29 6, 30,
31 31
Ground reference for logic and I/O pins.
VDD
NC
11, 32 7, 28 7, 8,
28, 29
P
—
Positive supply for logic and I/O pins.
—
—
13
NC
NC No connect.
CMOS = CMOS compatible input or output
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
OD = Open-drain (no diode to VDD)
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
2: Alternate assignment for CCP2 when CCP2MX is cleared.
DS39599C-page 18
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Oscillator Types
(1)
C1
OSC1
The PIC18F2X20 and PIC18F4X20 devices can be
operated in ten different oscillator modes. The user can
program the configuration bits, FOSC3:FOSC0, in
Configuration Register 1H to select one of these ten
modes:
To
Internal
Logic
XTAL
(3)
RF
Sleep
(2)
RS
1. LP
Low-Power Crystal
(1)
PIC18FXXXX
C2
2. XT
Crystal/Resonator
OSC2
3. HS
High-Speed Crystal/Resonator
Note 1: See Table 2-1 and Table 2-2 for initial values
of C1 and C2.
4. HSPLL
High-Speed Crystal/Resonator
with PLL enabled
2: A series resistor (RS) may be required for AT
strip cut crystals.
5. RC
External Resistor/Capacitor with
FOSC/4 output on RA6
3: RF varies with the oscillator mode chosen.
6. RCIO
7. INTIO1
8. INTIO2
External Resistor/Capacitor with
I/O on RA6
Internal Oscillator with FOSC/4
output on RA6 and I/O on RA7
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Internal Oscillator with I/O on RA6
and RA7
Typical Capacitor Values Used:
9. EC
External Clock with FOSC/4 output
External Clock with I/O on RA6
Mode
Freq
OSC1
OSC2
10. ECIO
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
2.2
Crystal Oscillator/Ceramic
Resonators
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
The oscillator design requires the use of a parallel cut
crystal.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
Note:
Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
See the notes on page 20 for additional information.
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
2003 Microchip Technology Inc.
DS39599C-page 19
PIC18F2220/2320/4220/4320
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Typical Capacitor Values
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Crystal
Freq
Tested:
Osc Type
C1
C2
LP
XT
HS
32 kHz
200 kHz
1 MHz
4 MHz
4 MHz
8 MHz
20 MHz
33 pF
15 pF
33 pF
27 pF
27 pF
22 pF
15 pF
33 pF
15 pF
33 pF
27 pF
27 pF
22 pF
15 pF
OSC1
Clock from
Ext. System
PIC18FXXXX
(HS Mode)
OSC2
Open
2.3
HSPLL
Capacitor values are for design guidance only.
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.
See the notes following this table for additional
information.
The PLL is enabled only when the oscillator configura-
tion bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.
Crystals Used:
32 kHz
200 kHz
1 MHz
4 MHz
8 MHz
20 MHz
FIGURE 2-3:
PLL BLOCK DIAGRAM
HS Osc Enable
PLL Enable
(from Configuration Register 1H)
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
OSC2
OSC1
Phase
Comparator
HS Mode
Crystal
Osc
FIN
FOUT
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
Loop
Filter
appropriate
values
of
external
components.
÷4
VCO
4: RS may be required to avoid overdriving
SYSCLK
crystals with low drive level specification.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
DS39599C-page 20
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
2.4
External Clock Input
2.5
RC Oscillator
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal manufacturing variation. Furthermore, the dif-
ference in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 2-6 shows how the
R/C combination is connected.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
OSC1/CLKI
Clock from
Ext. System
PIC18FXXXX
OSC2/CLKO
FOSC/4
FIGURE 2-6:
RC OSCILLATOR MODE
VDD
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
REXT
Internal
OSC1
Clock
CEXT
VSS
PIC18FXXXX
FIGURE 2-5:
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
OSC2/CLKO
FOSC/4
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
OSC1/CLKI
PIC18FXXXX
I/O (OSC2)
Clock from
Ext. System
The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
RA6
FIGURE 2-7:
RCIO OSCILLATOR MODE
VDD
REXT
Internal
OSC1
Clock
CEXT
PIC18FXXXX
VSS
I/O (OSC2)
RA6
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
2003 Microchip Technology Inc.
DS39599C-page 21
PIC18F2220/2320/4220/4320
2.6.2
INTRC OUTPUT FREQUENCY
2.6
Internal Oscillator Block
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
This changes the frequency of the INTRC source from
its nominal 31.25 kHz. Peripherals and features that
depend on the INTRC source will be affected by this
shift in frequency.
The PIC18F2X20/4X20 devices include an internal
oscillator block which generates two different clock sig-
nals. Either can be used as the system’s clock source.
This can eliminate the need for external oscillator
circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the system clock. It
also drives a postscaler which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.
Once set during factory calibration, the INTRC
frequency will remain within ±1% as temperature and
VDD change across their full specified operating
ranges.
2.6.3
OSCTUNE REGISTER
The other clock source is the internal RC oscillator
(INTRC) which provides a 31 kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source or when any of the
following are enabled:
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user's application.
This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
• Power-up Timer
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new fre-
quency within 8 clock cycles (approximately
8 * 32 µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred. Oper-
ation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 26).
2.6.1
INTIO MODES
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
DS39599C-page 22
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 2-1:
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
R/W-0
TUN5
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
bit 7
bit 0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: Frequency Tuning bits
011111= Maximum frequency (+12.5%, approximately)
•
•
•
•
000001
000000= Center frequency. Oscillator module is running at the calibrated frequency.
111111
•
•
•
•
100000= Minimum frequency (-12.5%, approximately)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
DS39599C-page 23
PIC18F2220/2320/4220/4320
2.7.1
OSCILLATOR CONTROL REGISTER
2.7
Clock Sources and Oscillator
Switching
The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power managed modes.
Like previous PIC18 devices, the PIC18F2X20 and
PIC18F4X20 devices include a feature that allows the
system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
PIC18F2X20/4X20 devices offer two alternate clock
sources. When enabled, these give additional options
for switching to the various power managed operating
modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating
in power managed modes. The available clock sources
are the primary clock (defined in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The clock selection
has no effect until a SLEEPinstruction is executed and
the device enters a power managed mode of operation.
The SCS bits are cleared on all forms of Reset.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source, the INTOSC source (8 MHz) or one of
the six frequencies derived from the INTOSC
postscaler (125 kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output.
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined on POR by the contents
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed out and the primary clock is providing the system
clock in primary clock modes. The IOFS bit indicates
when the internal oscillator block has stabilized and is
providing the system clock in RC Clock modes. The
T1RUN bit (T1CON<6>) indicates when the Timer1
oscillator is providing the system clock in secondary
clock modes. If none of these bits are set, the INTRC is
providing the system clock, or the internal oscillator
block has just started and is not yet stable.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.
PIC18F2X20/4X20 devices offer only the Timer1
oscillator as a secondary oscillator. This oscillator, in all
power managed modes, is often the time base for
functions such as a real-time clock.
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T1CKI and RC1/T1OSI pins.
Like the LP mode oscillator circuit, loading capacitors
are also connected from each pin to ground.
The IDLEN bit controls the selective shutdown of the
controller’s CPU in power managed modes. The use of
these bits is discussed in more detail in Section 3.0
“Power Managed Modes”.
The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator block is available as a power managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to set the
SCS0 bit will be ignored.
The clock sources for the PIC18F2X20/4X20 devices
are shown in Figure 2-8. See Section 12.0 “Timer1
Module” for further details of the Timer1 oscillator. See
Section 23.1 “Configuration Bits” for Configuration
register details.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEPinstruction or a very
long delay may occur while the Timer1
oscillator starts.
DS39599C-page 24
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 2-8:
PIC18F2X20/4X20 CLOCK DIAGRAM
Clock
Control
PIC18F2X20/4X20
CONFIG1H<3:0>
HSPLL
OSCCON<1:0>
Peripherals
Primary Oscillator
OSC2
4 x PLL
Sleep
LP, XT, HS, RC, EC
OSC1
Secondary Oscillator
T1OSC
T1OSO
Clock Source Option
for Other Modules
T1OSCEN
Enable
Oscillator
T1OSI
OSCCON<6:4>
Internal Oscillator
CPU
8 MHz
OSCCON<6:4>
111
110
101
4 MHz
2 MHz
Internal
Oscillator
Block
IDLEN
1 MHz
100
011
010
001
000
500 kHz
250 kHz
125 kHz
31 kHz
8 MHz
(INTOSC)
INTRC
Source
WDT, FSCM
2003 Microchip Technology Inc.
DS39599C-page 25
PIC18F2220/2320/4220/4320
REGISTER 2-2:
OSCCON REGISTER
R/W-0
IDLEN
R/W-0
IRCF2
R/W-0
IRCF1
R/W-0
IRCF0
R(1)
R-0
R/W-0
SCS1
R/W-0
SCS0
OSTS
IOFS
bit 7
bit 0
bit 7
IDLEN: Idle Enable bit
1= Idle mode enabled; CPU core is not clocked in power managed modes
0= Run mode enabled; CPU core is clocked in power managed modes
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111= 8 MHz (8 MHz source drives clock directly)
110= 4 MHz
101= 2 MHz
100= 1 MHz
011= 500 kHz
010= 250 kHz
001= 125 kHz
000= 31 kHz (INTRC source drives clock directly)
bit 3
bit 2
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Oscillator start-up time-out timer has expired; primary oscillator is running
0= Oscillator start-up time-out timer is running; primary oscillator is not ready
IOFS: INTOSC Frequency Stable bit
1= INTOSC frequency is stable
0= INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select bits
1x= Internal oscillator block (RC modes)
01= Timer1 oscillator (Secondary modes)(2)
00= Primary oscillator (Sleep and PRI_IDLE modes)
Note 1: Depends on state of IESO bit in Configuration Register 1H.
2: SCS0 may not be set while T1OSCEN (T1CON<3>) is clear.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 26
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
2.7.2
OSCILLATOR TRANSITIONS
The PIC18F2X20/4X20 devices contain circuitry to pre-
vent clocking “glitches” when switching between clock
sources. A short pause in the system clock occurs dur-
ing the clock switch. The length of this pause is
between 8 and 9 clock periods of the new clock source.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a real-
time clock. Other features may be operating that do not
require a system clock source (i.e., SSP slave, PSP,
INTn pins, A/D conversions and others).
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.
2.8
Effects of Power Managed Modes
on the Various Clock Sources
2.9
Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.1 “Power-on Reset (POR)”
through Section 4.5 “Brown-out Reset (BOR)”.
When the device executes a SLEEP instruction, the
system is switched to one of the power managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power Managed Modes” for details.
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
The first timer is the Power-up Timer (PWRT) which
provides a fixed delay on power-up (parameter 33,
Table 26-10), if enabled, in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the crys-
tal oscillator is stable (LP, XT and HS modes). The OST
does this by counting 1024 oscillator cycles before
allowing the oscillator to clock the device.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and pro-
viding the system clock. The Timer1 oscillator may also
run in all power managed modes if required to clock
Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power managed mode (see Section 23.2 “Watchdog
Timer (WDT)” through Section 23.4 “Fail-Safe Clock
Monitor”). The INTOSC output at 8 MHz may be used
directly to clock the system or may be divided down
first. The INTOSC output is disabled if the system clock
is provided directly from the INTRC output.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of 5 to 10 µs, following POR, while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only delay that occurs when any of the EC,
RC or INTIO modes are used as the primary clock
source.
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode
OSC1 Pin
OSC2 Pin
RC, INTIO1
Floating, external resistor
should pull high
At logic low (clock/4 output)
RCIO, INTIO2
Floating, external resistor
should pull high
Configured as PORTA, bit 6
ECIO
Floating, pulled by external clock
Floating, pulled by external clock
Configured as PORTA, bit 6
At logic low (clock/4 output)
EC
LP, XT, and HS
Feedback inverter disabled at
quiescent voltage level
Feedback inverter disabled at
quiescent voltage level
Note:
See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
2003 Microchip Technology Inc.
DS39599C-page 27
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 28
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
For PIC18F2X20/4X20 devices, the power managed
3.0
POWER MANAGED MODES
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when trig-
gered by an interrupt, a Reset, or a WDT time-out
(PRI_RUN mode is the normal full power execution
mode; the CPU and peripherals are clocked by the pri-
mary oscillator source). In addition, power managed
Run modes may also exit to Sleep mode or their
corresponding Idle mode.
The PIC18F2X20 and PIC18F4X20 devices offer a total
of six operating modes for more efficient power
management (see Table 3-1). These operating modes
provide a variety of options for selective power
conservation in applications where resources may be
limited (i.e., battery-powered devices).
There are three categories of power managed modes:
• Sleep mode
• Idle modes
• Run modes
3.1
Selecting Power Managed Modes
Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking while the
SC1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PICmicro® devices (where all system clocks are
stopped) are both offered in the PIC18F2X20/4X20
devices (SEC_RUN and Sleep modes, respectively).
However, additional power managed modes are avail-
able that allow the user greater flexibility in determining
what portions of the device are operating. The power
managed modes are event driven; that is, some
specific event must occur for the device to enter or
(more particularly) exit these operating modes.
3.1.1
CLOCK SOURCES
The clock source is selected by setting the SCS bits of
the OSCCON register. Three clock sources are avail-
able for use in power managed Idle modes: the primary
clock (as configured in Configuration Register 1H), the
secondary clock (Timer1 oscillator) and the internal
oscillator block. The secondary and internal oscillator
block sources are available for the power managed
modes (PRI_RUN mode is the normal full power exe-
cution mode; the CPU and peripherals are clocked by
the primary oscillator source).
TABLE 3-1:
Mode
POWER MANAGED MODES
OSCCON Bits
Module Clocking
Available Clock and Oscillator Source
IDLEN SCS1:SCS0
CPU
Peripherals
<7>
<1:0>
None – All clocks are disabled
Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(1)
This is the normal full power execution mode.
Sleep
0
0
00
00
Off
Off
.
PRI_RUN
Clocked
Clocked
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
0
0
1
1
1
01
1x
00
01
1x
Clocked
Clocked
Off
Clocked
Clocked
Clocked
Clocked
Clocked
Secondary – Timer1 Oscillator
Internal Oscillator Block(1)
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – Timer1 Oscillator
Internal Oscillator Block(1)
Off
Off
Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
2003 Microchip Technology Inc.
DS39599C-page 29
PIC18F2220/2320/4220/4320
3.1.2
ENTERING POWER MANAGED
MODES
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
In general, entry, exit and switching between power
managed clock sources requires clock source
switching. In each case, the sequence of events is the
same.
Any change in the power managed mode begins with
loading the OSCCON register and executing a SLEEP
instruction. The SCS1:SCS0 bits select one of three
power managed clock sources; the primary clock (as
defined in Configuration Register 1H), the secondary
clock (the Timer1 oscillator) and the internal oscillator
block (used in RC modes). Modifying the SCS bits will
have no effect until a SLEEP instruction is executed.
Entry to the power managed mode is triggered by the
execution of a SLEEPinstruction.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode; executing a SLEEP instruction is
simply a trigger to place the controller into
a power managed mode selected by the
OSCCON register, one of which is Sleep
mode.
3.1.3
MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the
SLEEPinstruction is determined by the settings of the
IDLEN and SCS bits at the time the instruction is exe-
cuted. If another SLEEP instruction is executed, the
device will enter the power managed mode specified by
these same bits at that time. If the bits have changed,
the device will enter the new power managed mode
specified by the new bit settings.
Figure 3-5 shows how the system is clocked while
switching from the primary clock to the Timer1 oscilla-
tor. When the SLEEPinstruction is executed, clocks to
the device are stopped at the beginning of the next
instruction cycle. Eight clock cycles from the new clock
source are counted to synchronize with the new clock
source. After eight clock pulses from the new clock
source are counted, clocks from the new clock source
resume clocking the system. The actual length of the
pause is between eight and nine clock periods from the
new clock source. This ensures that the new clock
source is stable and that its pulse width will not be less
than the shortest pulse width of the two clock sources.
3.1.4
COMPARISONS BETWEEN RUN
AND IDLE MODES
Clock source selection for the Run modes is identical to
the corresponding Idle modes. When a SLEEPinstruc-
tion is executed, the SCS bits in the OSCCON register
are used to switch to a different clock source. As a
result, if there is a change of clock source at the time a
SLEEPinstruction is executed, a clock switch will occur.
Three bits indicate the current clock source: OSTS and
IOFS in the OSCCON register and T1RUN in the
T1CON register. Only one of these bits will be set while
in a power managed mode other than PRI_RUN. When
the OSTS bit is set, the primary clock is providing the
system clock. When the IOFS bit is set, the INTOSC
output is providing a stable 8 MHz clock source and is
providing the system clock. When the T1RUN bit is set,
the Timer1 oscillator is providing the system clock. If
none of these bits are set, then either the INTRC clock
source is clocking the system or the INTOSC source is
not yet stable.
In Idle modes, the CPU is not clocked and is not run-
ning. In Run modes, the CPU is clocked and executing
code. This difference modifies the operation of the
WDT when it times out. In Idle modes, a WDT time-out
results in a wake from power managed modes. In Run
modes, a WDT time-out results in a WDT Reset (see
Table 3-2).
During a wake-up from an Idle mode, the CPU starts
executing code by entering the corresponding Run
mode until the primary clock becomes ready. When the
primary clock becomes ready, the clock source is auto-
matically switched to the primary clock. The IDLEN and
SCS bits are unchanged during and after the wake-up.
If the internal oscillator block is configured as the pri-
mary clock source in Configuration Register 1H, then
both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering a power managed RC mode
(same frequency) would clear the OSTS bit.
Figure 3-2 shows how the system is clocked during the
clock source switch. The example assumes the device
was in SEC_IDLE or SEC_RUN mode when a wake is
triggered (the primary clock was configured in HSPLL
mode).
DS39599C-page 30
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 3-2:
COMPARISON BETWEEN POWER MANAGED MODES
Power
Managed
Mode
Clock during wake-up
(while primary becomes
ready)
WDT time-out
causes a ...
Peripherals are
clocked by ...
CPU is clocked by ...
Sleep
Not clocked (not running) Wake-up
Not clocked
None or INTOSC multiplexer if
Two-Speed Start-up or
Fail-Safe Clock Monitor are
enabled.
Any Idle mode Not clocked (not running) Wake-up
Primary, Secondary or Unchanged from Idle mode
INTOSC multiplexer
(CPU operates as in
corresponding Run mode).
Any Run mode Secondary or INTOSC
multiplexer
Reset
Secondary or INTOSC Unchanged from Run mode.
multiplexer
There is one exception to how the IDLEN bit functions.
When all the low-power OSCCON bits are cleared
(IDLEN:SCS1:SCS0 = 000), the device enters Sleep
mode upon the execution of the SLEEPinstruction. This
is both the Reset state of the OSCCON register and the
setting that selects Sleep mode. This maintains com-
patibility with other PICmicro devices that do not offer
power managed modes.
3.2
Sleep Mode
The power managed Sleep mode in the PIC18F2X20/
4X20 devices is identical to that offered in all other
PICmicro controllers. It is entered by clearing the
IDLEN and SCS1:SCS0 bits (this is the Reset state)
and executing the SLEEPinstruction. This shuts down
the primary oscillator and the OSTS bit is cleared (see
Figure 3-1).
If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a
‘1’ when a SLEEP instruction is executed, the
peripherals will be clocked from the clock source
selected using the SCS1:SCS0 bits; however, the CPU
will not be clocked. Since the CPU is not executing
instructions, the only exits from any of the Idle modes
are by interrupt, WDT time-out or a Reset.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the system will not be clocked
until the primary clock source becomes ready (see
Figure 3-2), or it will be clocked from the internal
oscillator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabled (see Section 23.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock is providing the
system clocks. The IDLEN and SCS bits are not
affected by the wake-up.
When a wake-up event occurs, CPU execution is
delayed approximately 10 µs while it becomes ready to
execute code. When the CPU begins executing code,
it is clocked by the same clock source as was selected
in the power managed mode (i.e., when waking from
RC_IDLE mode, the internal oscillator block will clock
the CPU and peripherals until the primary clock source
becomes ready – this is essentially RC_RUN mode).
This continues until the primary clock source becomes
ready. When the primary clock becomes ready, the
OSTS bit is set and the system clock source is
switched to the primary clock (see Figure 3-4). The
IDLEN and SCS bits are not affected by the wake-up.
3.3
Idle Modes
The IDLEN bit allows the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Clearing IDLEN allows the CPU to be clocked.
Setting IDLEN disables clocks to the CPU, effectively
stopping program execution (see Register 2-2). The
peripherals continue to be clocked regardless of the
setting of the IDLEN bit.
While in any Idle mode or the Sleep mode, a WDT time-out
will result in a WDT wake-up to full power operation.
2003 Microchip Technology Inc.
DS39599C-page 31
PIC18F2220/2320/4220/4320
FIGURE 3-1:
TIMING TRANSITION FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-2:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
PC + 8
Wake-up Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
OSTS bit Set
DS39599C-page 32
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
When a wake-up event occurs, the CPU is clocked
from the primary clock source. A delay of approxi-
3.3.1
PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation, with its
more accurate primary clock source, since the clock
source does not have to “warm up” or transition from
another oscillator.
mately 10 µs is required between the wake-up event
and when code execution starts. This is required to
allow the CPU to become ready to execute instructions.
After the wake-up, the OSTS bit remains set. The
IDLEN and SCS bits are not affected by the wake-up
(see Figure 3-4).
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEPinstruc-
tion. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
FIGURE 3-3:
TRANSITION TIMING TO PRI_IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-4:
TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Q1
Q3
Q4
Q2
OSC1
CPU Start-up Delay
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
Wake-up Event
2003 Microchip Technology Inc.
DS39599C-page 33
PIC18F2220/2320/4220/4320
When a wake-up event occurs, the peripherals continue
to be clocked from the Timer1 oscillator. After a 10 µs
delay following the wake-up event, the CPU begins exe-
cuting code, being clocked by the Timer1 oscillator. The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready, a clock switch back to the primary clock
occurs (see Figure 3-6). When the clock switch is com-
plete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
3.3.2
SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the IDLEN
bit, modifying to SCS1:SCS0 = 01 and executing a
SLEEPinstruction. When the clock source is switched
to the Timer1 oscillator (see Figure 3-5), the primary
oscillator is shut down, the OSTS bit is cleared and the
T1RUN bit is set.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when try-
ing to set the SCS0 bit (OSCCON<0>),
the write to SCS0 will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started; in such sit-
uations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 3-5:
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
Q1 Q2 Q3 Q4 Q1
1
2
3
4
5
6
7
8
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-6:
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
T1OSI
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
1
2
3
4
5
6
7
8
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake-up from Interrupt Event
DS39599C-page 34
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
was executed and the INTOSC source was already
stable, the IOFS bit will remain set. If the IRCF bits are
all clear, the INTOSC output is not enabled and the
IOFS bit will remain clear; there will be no indication of
the current clock source.
3.3.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
When a wake-up event occurs, the peripherals con-
tinue to be clocked from the INTOSC multiplexer. After
a 10 µs delay following the wake-up event, the CPU
begins executing code, being clocked by the INTOSC
multiplexer. The microcontroller operates in RC_RUN
mode until the primary clock becomes ready. When the
primary clock becomes ready, a clock switch back to
the primary clock occurs (see Figure 3-8). When the
clock switch is complete, the IOFS bit is cleared, the
OSTS bit is set and the primary clock is providing the
system clock. The IDLEN and SCS bits are not affected
by the wake-up. The INTRC source will continue to run
if either the WDT or the Fail-Safe Clock Monitor is
enabled.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEPinstruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were previ-
ously at a non-zero value before the SLEEPinstruction
FIGURE 3-7:
TIMING TRANSITION TO RC_IDLE MODE
Q1 Q2 Q3 Q4 Q1
1
2
3
4
5
6
7
8
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-8:
TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q4
Q1
Q2
INTOSC
Multiplexer
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
1
2
3
4
5
6
7
8
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake-up from Interrupt Event
2003 Microchip Technology Inc.
DS39599C-page 35
PIC18F2220/2320/4220/4320
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instruction. The system clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
3.4
Run Modes
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating modes may not afford the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when try-
ing to set the SCS0 bit, the write to
SCS0 will not occur. If the Timer1 oscilla-
tor is enabled, but not yet running, system
clocks will be delayed until the oscillator
has started; in such situations, initial oscil-
lator operation is far from stable and
unpredictable operation may result.
Wake-up from a power managed Run mode can be
triggered by an interrupt, or any Reset, to return to full
power operation. As the CPU is executing code in Run
modes, several additional exits from Run modes are
possible. They include exit to Sleep mode, exit to a cor-
responding Idle mode, and exit by executing a RESET
instruction. While the device is in any of the power
managed Run modes, a WDT time-out will result in a
WDT Reset.
When a wake-up event occurs, the peripherals and
CPU continue to be clocked from the Timer1 oscillator
while the primary clock is started. When the primary
clock becomes ready, a clock switch back to the primary
clock occurs (see Figure 3-6). When the clock switch is
complete, the T1RUN bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
3.4.1
PRI_RUN MODE
The PRI_RUN mode is the normal full power execution
mode. If the SLEEPinstruction is never executed, the
microcontroller operates in this mode (a SLEEPinstruc-
tion is executed to enter all other power managed
modes). All other power managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
Firmware can force an exit from SEC_RUN mode. By
clearing the T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full power operation is trig-
gered. The Timer1 oscillator will continue to run and
provide the system clock even though the T1OSCEN bit
is cleared. The primary clock is started. When the pri-
mary clock becomes ready, a clock switch back to the
primary clock occurs (see Figure 3-6). When the clock
switch is complete, the Timer1 oscillator is disabled, the
T1RUN bit is cleared, the OSTS bit is set and the pri-
mary clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
FIGURE 3-9:
TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
4
5
6
7
8
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 2
DS39599C-page 36
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
3.4.3
RC_RUN MODE
Note:
Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode pro-
vides the best power conservation of all the Run modes
while still executing code. It works well for user applica-
tions which are not highly timing sensitive or do not
require high-speed clocks at all times.
If the IRCF bits are all clear, the INTOSC output is not
enabled and the IOFS bit will remain clear; there will be
no indication of the current clock source. The INTRC
source is providing the system clocks.
If the primary clock source is the internal oscillator
block (either of the INTIO1 or INTIO2 oscillators), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to, and exit
from, RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.
If the IRCF bits are changed from all clear (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable. Clocks to
the system continue while the INTOSC source
stabilizes in approximately 1 ms.
If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed and the
INTOSC source was already stable, the IOFS bit will
remain set.
This mode is entered by clearing the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.
When a wake-up event occurs, the system continues to
be clocked from the INTOSC multiplexer while the pri-
mary clock is started. When the primary clock becomes
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is cleared, the OSTS bit is set and the primary
clock is providing the system clock. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
The IRCF bits may be modified at any time to immedi-
ately change the system clock speed. Executing a
SLEEPinstruction is not required to select a new clock
frequency from the INTOSC multiplexer.
FIGURE 3-10:
TIMING TRANSITION TO RC_RUN MODE
Q4 Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
4
5
6
7
8
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
2003 Microchip Technology Inc.
DS39599C-page 37
PIC18F2220/2320/4220/4320
3.4.4
EXIT TO IDLE MODE
3.5
Wake-up From Power Managed
Modes
An exit from a power managed Run mode to its corre-
sponding Idle mode is executed by setting the IDLEN
bit and executing a SLEEP instruction. The CPU is
halted at the beginning of the instruction following the
SLEEPinstruction. There are no changes to any of the
clock source status bits (OSTS, IOFS or T1RUN).
While the CPU is halted, the peripherals continue to be
clocked from the previously selected clock source.
An exit from any of the power managed modes is trig-
gered by an interrupt, a Reset, or a WDT time-out. This
section discusses the triggers that cause exits from
power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Section 3.2 “Sleep Mode” through
Section 3.4 “Run Modes”).
3.4.5
EXIT TO SLEEP MODE
Note:
If application code is timing sensitive, it
should wait for the OSTS bit to become set
before continuing. Use the interval during
the low-power exit sequence (before
OSTS is set) to perform timing insensitive
“housekeeping” tasks.
An exit from a power managed Run mode to Sleep
mode is executed by clearing the IDLEN and
SCS1:SCS0 bits and executing a SLEEP instruction.
The code is no different than the method used to invoke
Sleep mode from the normal operating (full power)
mode.
Device behavior during Low-Power mode exits is
summarized in Table 3-3.
The primary clock and internal oscillator block are dis-
abled. The INTRC will continue to operate if the WDT
is enabled. The Timer1 oscillator will continue to run, if
enabled, in the T1CON register. All clock source status
bits are cleared (OSTS, IOFS and T1RUN).
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit a power managed mode and resume full
power operation. To enable this functionality, an inter-
rupt source must be enabled by setting its enable bit in
one of the INTCON or PIE registers. The exit sequence
is initiated when the corresponding interrupt flag bit is
set. On all exits from Lower Power mode by interrupt,
code execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
DS39599C-page 38
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 3-3:
ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR
ANY IDLE MODE (BY CLOCK SOURCES)
Power
Activity During Wake-up from
Power Managed Mode
ClockReady
Status Bit
(OSCCON)
Clock in Power Primary System
Managed
Mode Exit
Delay
Managed Mode
Clock
Exit by Interrupt
CPU and peripherals
Exit by Reset
Not clocked or
LP, XT, HS
HSPLL
EC, RC, INTRC(1)
INTOSC(2)
LP, XT, HS
HSPLL
OSTS
Primary System
Clock
(PRI_IDLE mode)
clocked by primary clock Two-Speed Start-up
5-10 µs(5)
and executing
instructions.
(if enabled)(3)
.
—
IOFS
OST
CPU and peripherals
clocked by selected
power managed mode
clock and executing
instructions until primary
clock source becomes
ready.
OSTS
OST + 2 ms
T1OSC or
INTRC(1)
EC, RC, INTRC(1) 5-10 µs(5)
—
INTOSC(2)
LP, XT, HS
HSPLL
1 ms(4)
IOFS
OST
OSTS
OST + 2 ms
INTOSC(2)
EC, RC, INTRC(1) 5-10 µs(5)
—
INTOSC(2)
LP, XT, HS
HSPLL
EC, RC, INTRC(1) 5-10 µs(5)
INTOSC(2) 1 ms(4)
None
OST
IOFS
Not clocked or
OSTS
Two-Speed Start-up (if
enabled) until primary
clock source becomes
OST + 2 ms
Sleep mode
—
ready(3)
.
IOFS
Note 1: In this instance, refers specifically to the INTRC clock source.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: Two-Speed Start-up is covered in greater detail in Section 23.3 “Two-Speed Start-up”.
4: Execution continues during the INTOSC stabilization period.
5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
2003 Microchip Technology Inc.
DS39599C-page 39
PIC18F2220/2320/4220/4320
3.5.2
EXIT BY RESET
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock (defined in
Configuration Register 1H) becomes ready. At that
time, the OSTS bit is set and the device begins
executing code.
Certain exits from power managed modes do not
invoke the OST at all. These are:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 23.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 23.4 “Fail-Safe Clock
Monitor”) are enabled in Configuration Register 1H,
the device may begin execution as soon as the Reset
source has cleared. Execution is clocked by the
INTOSC multiplexer driven by the internal oscillator
block. Since the OSCCON register is cleared following
all Resets, the INTRC clock source is selected. A higher
speed clock may be selected by modifying the IRCF bits
in the OSCCON register. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready, or a power managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these cases, the primary clock source either does
not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes).
However, a fixed delay (approximately 10 µs) following
the wake-up event is required when leaving Sleep and
Idle modes. This delay is required for the CPU to pre-
pare for execution. Instruction execution resumes on
the first clock cycle following this delay.
3.6
INTOSC Frequency Drift
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways.
3.5.3
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power managed mode the device is in when
the time-out occurs.
It is possible to adjust the INTOSC frequency by modi-
fying the value in the OSCTUNE register. This has the
side effect that the INTRC clock source frequency is
also affected. However, the features that use the
INTRC source often do not require an exact frequency.
These features include the Fail-Safe Clock Monitor, the
Watchdog Timer and the RC_RUN/RC_IDLE modes
when the INTRC clock source is selected.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in a wake-up from
the power managed mode (see Section 3.2 “Sleep
Mode” through Section 3.4 “Run Modes”).
If the device is executing code (all Run modes), the
time-out will result in a WDT Reset (see Section 23.2
“Watchdog Timer (WDT)”).
The WDT timer and postscaler are cleared by execut-
ing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
system clock source.
Being able to adjust the INTOSC requires knowing
when an adjustment is required, in which direction it
should be made and in some cases, how large a
change is needed. Three examples are shown but
other techniques may be used.
DS39599C-page 40
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
3.6.1
EXAMPLE – USART
3.6.3
EXAMPLE – CCP IN CAPTURE
MODE
An adjustment may be indicated when the USART
begins to generate framing errors or receives data
with errors while in Asynchronous mode. Framing
errors indicate that the system clock frequency is too
high – try decrementing the value in the OSCTUNE
register to reduce the system clock frequency. Errors in
data may suggest that the system clock speed is too
low – increment OSCTUNE.
A CCP module can use free running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power fre-
quency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
3.6.2
EXAMPLE – TIMERS
This technique compares system clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast – decrement OSCTUNE. If the measured time
is much less than the calculated time, the internal
oscillator block is running too slow – increment
OSCTUNE.
Both timers are cleared but the timer clocked by the ref-
erence generates interrupts. When an interrupt occurs,
the internally clocked timer is read and both timers are
cleared. If the internally clocked timer value is greater
than expected, then the internal oscillator block is
running too fast – decrement OSCTUNE.
2003 Microchip Technology Inc.
DS39599C-page 41
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 42
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-
4.0
RESET
The PIC18F2X20/4X20 devices differentiate between
various kinds of Reset:
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-2. These bits
are used in software to determine the nature of the
Reset. See Table 4-3 for a full description of the Reset
states of all registers.
a) Power-on Reset (POR)
b) MCLR Reset while executing instructions
c) MCLR Reset when not executing instructions
d) Watchdog Timer (WDT) Reset (during
execution)
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
The enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
g) Stack Full Reset
h) Stack Underflow Reset
The MCLR pin is not driven low by any internal Resets,
including the WDT.
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
The MCLR input provided by the MCLR pin can be dis-
abled with the MCLRE bit in Configuration Register 3H
(CONFIG3H<7>). See Section 23.1 “Configuration
Bits” for more information.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
BOREN
VDD
Brown-out
Reset
S
OST/PWRT
OST
10-bit Ripple Counter
1024 Cycles
Chip_Reset
R
Q
OSC1
32 µs
INTRC(1)
65.5 ms
PWRT
11-bit Ripple Counter
Enable PWRT
(2)
Enable OST
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-1 for time-out situations.
2003 Microchip Technology Inc.
DS39599C-page 43
PIC18F2220/2320/4220/4320
4.1
Power-on Reset (POR)
4.3
Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR cir-
cuitry, just tie the MCLR pin through a resistor (1k to
10 kΩ) to VDD. This will eliminate external RC compo-
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified
(parameter D004). For a slow rise time, see Figure 4-2.
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power managed modes.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
4.4
PLL Lock Time-out
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A portion of the
Power-up Timer is used to provide a fixed time-out that
is sufficient for the PLL to lock to the main oscillator fre-
quency. This PLL lock time-out (TPLL) is typically 2 ms
and follows the oscillator start-up time-out.
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
VDD
D
4.5
Brown-out Reset (BOR)
R
A configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below VBOR (parameter D005) for
greater than TBOR (parameter #35), the brown-out situ-
ation will reset the chip. A Reset may not occur if VDD
falls below VBOR for less than TBOR. The chip will
remain in Brown-out Reset until VDD rises above VBOR.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay TPWRT (parameter
#33). If VDD drops below VBOR while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above VBOR, the Power-up Timer will execute
the additional time delay. Enabling BOR Reset does
not automatically enable the PWRT.
R1
MCLR
PIC18FXXXX
C
Note 1: External Power-on Reset circuit is
required only if the VDD power-up slope is
too slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that the voltage drop across R does not
violate the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the
event of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
4.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, after the POR pulse has cleared, PWRT time-out
is invoked (if enabled). Then, the OST is activated. The
total time-out will vary based on oscillator configuration
and the status of the PWRT. For example, in RC mode
with the PWRT disabled, there will be no time-out at all.
Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and
Figure 4-7 depict time-out sequences on power-up.
4.2
Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC18F2X20/4X20
devices is an 11-bit counter, which uses the INTRC
source as the clock input. This yields a count of
2048 x 32 µs = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.
The PWRT is enabled by clearing configuration bit,
PWRTEN.
Table 4-2 shows the Reset conditions for some Special
Function Registers, while Table 4-3 shows the Reset
conditions for all the registers.
DS39599C-page 44
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 4-1:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out
Exit from
Configuration
Power Managed Mode
PWRTEN = 0
PWRTEN = 1
HSPLL
66 ms(1) + 1024 TOSC + 2 ms(2)
66 ms(1) + 1024 TOSC
66 ms(1)
1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
HS, XT, LP
EC, ECIO
1024 TOSC
1024 TOSC
—
—
—
—
—
—
RC, RCIO
66 ms(1)
66 ms(1)
INTIO1, INTIO2
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the 4x PLL to lock.
REGISTER 4-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-1
POR
R/W-1
BOR
bit 7
bit 0
Note:
Refer to Section 5.14 “RCON Register” for bit definitions.
TABLE 4-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
RESETInstruction
Brown-out
0000h
0000h
0000h
0--1 1100
0--0 uuuu
0--1 11u-
1
0
1
1
u
1
1
u
1
0
u
u
0
u
0
0
u
u
0
u
u
MCLR during power managed
Run modes
0000h
0000h
0000h
0--u 1uuu
0--u 10uu
0--u 0uuu
u
u
u
1
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
MCLR during power managed
Idle modes and Sleep mode
WDT Time-out during full power
or power managed Run mode
MCLR during full power
execution
u
1
u
u
u
1
Stack Full Reset (STVREN = 1)
0000h
0--u uuuu
u
u
u
u
u
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
PC + 2
PC + 2
u--u uuuu
u--u 00uu
u--u u0uu
u
u
u
u
0
u
u
0
0
u
u
u
u
u
u
u
u
u
1
u
u
WDT Time-out during power
managed Idle or Sleep modes
Interrupt exit from power
managed modes
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
2003 Microchip Technology Inc.
DS39599C-page 45
PIC18F2220/2320/4220/4320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
TOSU
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0 2220 2320 4220 4320
POSTDEC0 2220 2320 4220 4320
N/A
N/A
N/A
N/A
N/A
N/A
PREINC0
PLUSW0
FSR0H
FSR0L
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
WREG
INDF1
POSTINC1 2220 2320 4220 4320
POSTDEC1 2220 2320 4220 4320
N/A
N/A
N/A
N/A
N/A
N/A
PREINC1
PLUSW1
2220 2320 4220 4320
2220 2320 4220 4320
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
DS39599C-page 46
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
FSR1H
FSR1L
BSR
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
---- xxxx
xxxx xxxx
---- 0000
N/A
---- uuuu
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
INDF2
POSTINC2 2220 2320 4220 4320
POSTDEC2 2220 2320 4220 4320
N/A
N/A
N/A
N/A
N/A
N/A
PREINC2
PLUSW2
FSR2H
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0000 q000
--00 0101
---- ---0
0--1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0000 q000
--00 0101
---- ---0
0--q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu qquu
--uu uuuu
---- ---u
u--u qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1 2220 2320 4220 4320
SSPCON2 2220 2320 4220 4320
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
2003 Microchip Technology Inc.
DS39599C-page 47
PIC18F2220/2320/4220/4320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
xxxx xxxx
xxxx xxxx
--00 0000
--00 0000
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
000- 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0000 0000
0000 0000
xx-0 x000
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
0-00 0000
uuuu uuuu
uuuu uuuu
0000 0000
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 0000
0000 0000
000- 0000
0000 0111
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0000 0000
0000 0000
uu-0 u000
0000 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-0 u000
0000 0000
CCP1CON
CCPR2H
CCPR2L
CCP2CON 2220 2320 4220 4320
PWM1CON 2220 2320 4220 4320
ECCPAS
CVRCON
CMCON
TMR3H
TMR3L
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON1
EECON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
DS39599C-page 48
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
IPR2
PIR2
PIE2
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
11-1 1111
00-0 0000
00-0 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
--00 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111(5)
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx(5)
---- xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000(5)
11-1 1111
00-0 0000
00-0 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
--00 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
---- xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu0u 0000(5)
uu-u uuuu
uu-u uuuu(1)
uu-u uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu(1)
-uuu uuuu(1)
uuuu uuuu
-uuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
IPR1
PIR1
PIE1
OSCTUNE 2220 2320 4220 4320
TRISE
TRISD
TRISC
TRISB
TRISA(5)
LATE
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
LATD
LATC
LATB
LATA(5)
PORTE
PORTD
PORTC
PORTB
PORTA(5)
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
2003 Microchip Technology Inc.
DS39599C-page 49
PIC18F2220/2320/4220/4320
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
DS39599C-page 50
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
0V
1V
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
TOST
TPLL
PLL Time-out
Internal Reset
Note:
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
2003 Microchip Technology Inc.
DS39599C-page 51
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 52
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
There are three memory types in Enhanced MCU
devices. These memory types are:
• Program Memory
• Data RAM
• Data EEPROM
The PIC18F2220 and PIC18F4220 each have
4 Kbytes of Flash memory and can store up to 2,048
single-word instructions.
Data and program memory use separate busses which
allow for concurrent access of these types.
Additional detailed information for Flash program mem-
ory and data EEPROM is provided in Section 6.0
“Flash Program Memory” and Section 7.0 “Data
EEPROM Memory”, respectively.
The PIC18F2320 and PIC18F4320 each have
8 Kbytes of Flash memory and can store up to 4,096
single-word instructions.
The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
The Program Memory Maps for PIC18F2220/4220 and
PIC18F2320/4320 devices are shown in Figure 5-1
and Figure 5-2, respectively.
FIGURE 5-1:
PROGRAM MEMORY MAP
AND STACK FOR
FIGURE 5-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F2220/4220
PIC18F2320/4320
PC<20:0>
PC<20:0>
21
21
CALL,RCALL,RETURN
RETFIE,RETLW
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 1
•
•
•
•
•
•
Stack Level 31
Stack Level 31
0000h
0000h
Reset Vector
Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
0008h
0018h
On-Chip
Program Memory
On-Chip
Program Memory
0FFFh
1000h
1FFFh
2000h
Read ‘0’
Read ‘0’
1FFFFFh
200000h
1FFFFFh
200000h
2003 Microchip Technology Inc.
DS39599C-page 53
PIC18F2220/2320/4220/4320
5.2.2
RETURN STACK POINTER
(STKPTR)
5.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALLor RCALLinstruction is executed or an interrupt is
Acknowledged. The PC value is pulled off the stack on
a RETURN, RETLWor a RETFIEinstruction. PCLATU
and PCLATH are not affected by any of the RETURNor
CALLinstructions.
The STKPTR register (Register 5-1) contains the stack
pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the stack pointer can be 0 through 31. The stack
pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. At Reset, the stack pointer value will be zero.
The user may read and write the stack pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all Resets. There is no RAM associated
with stack pointer 00000b. This is only a Reset value.
During a CALLtype instruction, causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC (already pointing to the
instruction following the CALL). During a RETURNtype
instruction, causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR are
transferred to the PC and then the stack pointer is
decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a description of
the device configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the stack
pointer will be set to zero.
The stack space is not part of either program or data
space. The stack pointer is readable and writable and
the address on the top of the stack is readable and writ-
able through the top-of-stack Special File Registers.
Data can also be pushed to, or popped from, the stack
using the top-of-stack SFRs. Status bits indicate if the
stack is full, has overflowed or underflowed.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push,
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.
5.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register (Figure 5-3). This allows users to
implement a software stack if necessary. After a CALL,
RCALLor interrupt, the software can read the pushed
value by reading the TOSU, TOSH and TOSL registers.
These values can be placed on a user defined software
stack. At return time, the software can replace the
TOSU, TOSH and TOSL and do a return.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
TOSU
00h
TOSH
1Ah
TOSL
34h
00010
00011
001A34h 00010
000D58h 00001
00000
Top-of-Stack
DS39599C-page 54
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 5-1:
STKPTR REGISTER
R/C-0 R/C-0
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL STKUNF
bit 7
bit 0
bit 7(1)
bit 6(1)
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented
‘0’ = Bit is cleared
C = Clearable only bit
x = Bit is unknown
- n = Value at POR
5.2.3
PUSH AND POP INSTRUCTIONS
5.2.4
STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place data or a return address
on the stack.
These Resets are enabled by programming the
STVREN bit in Configuration Register 4L. When the
STVREN bit is cleared, a full or underflow condition will
set the appropriate STKFUL or STKUNF bit but not
cause a device Reset. When the STVREN bit is set, a
full or underflow condition will set the appropriate
STKFUL or STKUNF bit and then cause a device
Reset. The STKFUL or STKUNF bits are cleared by the
user software or a POR Reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POPinstruction. The POPinstruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
2003 Microchip Technology Inc.
DS39599C-page 55
PIC18F2220/2320/4220/4320
5.3
Fast Register Stack
5.4
PCL, PCLATH and PCLATU
A “fast return” option is available for interrupts. A Fast
Register Stack is provided for the Status, WREG and
BSR registers and are only one in depth. The stack is
not readable or writable and is loaded with the current
value of the corresponding register when the processor
vectors for an interrupt. The values in the registers are
then loaded back into the working registers if the
RETFIE, FASTinstruction is used to return from the
interrupt.
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
contains the PC<15:8> bits and is not directly readable
or writable. Updates to the PCH register may be per-
formed through the PCLATH register. The upper byte is
called PCU. This register contains the PC<20:16> bits
and is not directly readable or writable. Updates to the
PCU register may be performed through the PCLATU
register.
All interrupt sources will push values into the stack reg-
isters. If both low and high priority interrupts are
enabled, the stack registers cannot be used reliably to
return from low priority interrupts. If a high priority inter-
rupt occurs while servicing a low priority interrupt, the
stack register values stored by the low priority interrupt
will be overwritten. Users must save the key registers
in software during a low priority interrupt.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by any operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 5.8.1
“Computed GOTO”).
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instructions in the program memory.
If no interrupts are used, the Fast Register Stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the Status,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FASTinstruction is then executed to restore
these registers from the Fast Register Stack.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
•
•
SUB1
•
•
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
DS39599C-page 56
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.5
Clocking Scheme/Instruction
Cycle
5.6
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 5-2).
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the Pro-
gram Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 5-4.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-4:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC+2
PC
PC+4
OSC2/CLKO
(RC mode)
Execute INST (PC-2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+2)
Fetch INST (PC+4)
EXAMPLE 5-2:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
Execute 2
Fetch 3
3. BRA
4. BSF
SUB_1
PORTA, BIT3 (Forced NOP)
Execute 3
Fetch 4
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
2003 Microchip Technology Inc.
DS39599C-page 57
PIC18F2220/2320/4220/4320
The CALLand GOTOinstructions have the absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-5 shows how the
instruction ‘GOTO 000006h’ is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction repre-
sents the number of single-word instructions that the
PC will be offset by. Section 24.0 “Instruction Set
Summary” provides further details of the instruction
set.
5.7
Instructions in Program Memory
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 5-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 5.4 “PCL,
PCLATH and PCLATU”).
FIGURE 5-5:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that results in a skip opera-
tion. A program example that demonstrates this con-
cept is shown in Example 5-3. Refer to Section 24.0
“Instruction Set Summary” for further details of the
instruction set.
5.7.1
TWO-WORD INSTRUCTIONS
PIC18F2X20/4X20 devices have four two-word instruc-
tions: MOVFF, CALL, GOTOand LFSR. The second
word of these instructions has the 4 MSBs set to ‘1’s
and is decoded as a NOPinstruction. The lower 12 bits
of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the
EXAMPLE 5-3:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
REG1
; is RAM location 0?
; No, skip this word
; Execute this word as a NOP
; continue code
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
MOVFF
REG1, REG2
ADDWF
REG3
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
TSTFSZ
MOVFF
REG1
; is RAM location 0?
; Yes, execute this word
; 2nd word of instruction
; continue code
REG1, REG2
REG3
ADDWF
DS39599C-page 58
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.8
Look-up Tables
5.9
Data Memory Organization
Look-up tables are implemented two ways:
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 5-6
shows the data memory organization for the
PIC18F2X20/4X20 devices.
• Computed GOTO
• Table Reads
5.8.1
COMPUTED GOTO
The data memory map is divided into as many as 16
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits of the BSR are
not implemented.
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 5-4.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(FFFh) and extend towards F80h. Any remaining space
beyond the SFRs in the bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ‘0’s.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSB = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi-
rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the data memory map without banking. See
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” for indirect addressing details.
EXAMPLE 5-4:
COMPUTED GOTO USING
AN OFFSET VALUE
MOVFW
CALL
OFFSET
TABLE
ORG
0xnn00
TABLE ADDWF
PCL
RETLW
RETLW
RETLW
•
•
•
0xnn
0xnn
0xnn
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFFinstruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 5.10
“Access Bank” provides a detailed description of the
Access RAM.
5.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per pro-
gram word by using table reads and writes. The table
pointer (TBLPTR) specifies the byte address and the
table latch (TABLAT) contains the data that is read
from, or written to program memory. Data is transferred
to/from program memory, one byte at a time.
5.9.1
GENERAL PURPOSE
REGISTER FILE
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
The Table Read/Table Write operation is discussed
further in Section 6.1 “Table Reads and Table
Writes”.
Data RAM is available for use as GPR registers by all
instructions. The second half of Bank 15 (F80h to
FFFh) contains SFRs. All other banks of data memory
contain GPRs, starting with Bank 0.
2003 Microchip Technology Inc.
DS39599C-page 59
PIC18F2220/2320/4220/4320
FIGURE 5-6:
BSR<3:0>
= 0000
DATA MEMORY MAP FOR PIC18F2X20/4X20 DEVICES
Data Memory Map
000h
00h
Access RAM
GPR
07Fh
080h
0FFh
100h
Bank 0
Bank 1
FFh
00h
= 0001
GPR
1FFh
200h
FFh
Access Bank
00h
Access RAM Low
7Fh
80h
= 0010
= 1110
Access RAM High
(SFRs)
Bank 2
to
Bank 14
Unused
Read ‘00h’
FFh
When a = 0:
The BSR is ignored and the
Access Bank is used.
The first 128 bytes are
general purpose RAM
(from Bank 0).
EFFh
F00h
F7Fh
F80h
FFFh
00h
FFh
Unused
SFR
= 1111
The second 128 bytes are
Special Function Registers
(from Bank 15).
Bank 15
When a = 1:
The BSR specifies the bank
used by the instruction.
DS39599C-page 60
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
5.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2X20/4X20 DEVICES
Address
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
Name
TOSU
Address
Name
INDF2(2)
Address
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
Name
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
—
Address
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
Name
IPR1
PIR1
PIE1
—
FDFh
TOSH
FDEh POSTINC2(2)
FDDh POSTDEC2(2)
FDCh PREINC2(2)
FDBh PLUSW2(2)
TOSL
STKPTR
PCLATU
PCLATH
PCL
OSCTUNE
—
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
FSR2H
FSR2L
—
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0(2)
STATUS
TMR0H
TMR0L
FB8h
—
—
FB7h PWM1CON(1)
FB6h ECCPAS(1)
—
TRISE(1)
TRISD(1)
TRISC
TRISB
TRISA
—
T0CON
—
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CVRCON
CMCON
TMR3H
TMR3L
T3CON
—
OSCCON
LVDCON
WDTCON
RCON
—
TMR1H
TMR1L
SPBRG
RCREG
TXREG
TXSTA
RCSTA
—
—
FEEh POSTINC0(2)
FEDh POSTDEC0(2)
FECh PREINC0(2)
FEBh PLUSW0(2)
—
T1CON
TMR2
LATE(1)
LATD(1)
LATC
LATB
LATA
—
PR2
FEAh
FE9h
FE8h
FE7h
FE6h POSTINC1(2)
FE5h POSTDEC1(2)
FE4h PREINC1(2)
FE3h PLUSW1(2)
FSR0H
FSR0L
WREG
INDF1(2)
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
EEADR
EEDATA
EECON2
EECON1
—
—
—
—
—
PORTE
PORTD(1)
PORTC
PORTB
PORTA
—
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
PIR2
PIE2
Legend: — = Unimplemented registers, read as ‘0’.
Note 1: This register is not available on PIC18F2X20 devices.
2: This is not a physical register.
2003 Microchip Technology Inc.
DS39599C-page 61
PIC18F2220/2320/4220/4320
TABLE 5-2:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320)
Value on
POR, BOR
Details on
page:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
n/a
46, 54
46, 54
46, 54
46, 55
46, 56
46, 56
46, 56
46, 74
46, 74
46, 74
46, 74
46, 85
46, 85
46, 89
46, 90
46, 91
46, 66
46, 66
46, 66
46, 66
46, 66
46, 66
46, 66
46
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
bit 21(3)
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH PEIE/GIEL
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
RBPU
INTEDG0
INT1IP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTINC0
n/a
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
n/a
PREINC0
PLUSW0
FSR0H
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
n/a
n/a
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- 0000
xxxx xxxx
xxxx xxxx
n/a
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
46, 66
46, 66
46, 66
46, 66
46, 66
47, 66
47, 66
47, 65
47, 66
47, 66
47, 66
47, 66
47, 66
47, 66
47, 66
47, 68
47, 119
47, 119
47, 117
POSTINC1
n/a
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
n/a
PREINC1
PLUSW1
FSR1H
FSR1L
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
n/a
n/a
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- 0000
xxxx xxxx
---- 0000
n/a
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTINC2
n/a
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
n/a
PREINC2
PLUSW2
FSR2H
FSR2L
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
n/a
n/a
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
TMR0H
TMR0L
T0CON
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
‘0’ in all other oscillator modes.
2:
3:
4:
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
5:
6:
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is
read-only.
DS39599C-page 62
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
Value on
POR, BOR
Details on
page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
LVDCON
WDTCON
IDLEN
—
IRCF2
—
IRCF1
IRVST
—
IRCF0
LVDEN
—
OSTS
LVDL3
—
IOFS
LVDL2
—
SCS1
LVDL1
—
SCS0
LVDL0
0000 q000
--00 0101
--- ---0
26, 47
47, 233
47, 246
—
—
SWDTEN
RCON
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 11q0 45, 69, 98
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
47, 125
47, 125
47, 121
47, 127
47, 127
47, 127
RD16
T1RUN
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON
Timer2 Register
PR2
Timer2 Period Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
SSP Receive Buffer/Transmit Register
T2CON
SSPBUF
—
T2CKPS0 -000 0000
xxxx xxxx
47, 156,
164
SSPADD
SSPSTAT
SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode.
0000 0000
47, 164
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000
47, 156,
165
SSPCON1
SSPOV
SSPEN
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
0000 0000
47, 157,
166
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
ACKSTAT
ACKDT
ACKEN
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 0000
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
47, 167
48, 220
48, 220
48, 211
48, 212
48, 213
48, 134
48, 134
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
P1M1(5)
P1M0(5)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
48, 133,
141
CCPR2H
CCPR2L
CCP2CON
PWM1CON(5)
ECCPAS(5)
CVRCON
CMCON
TMR3H
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
000- 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
48, 134
48, 134
48, 133
48, 149
48, 150
48, 227
48, 221
48, 131
48, 131
48, 129
48, 198
—
—
DC2B1
PDC5
DC2B0
PDC4
CCP2M3
PDC3
CCP2M2
PDC2
CCP2M1
PDC1
CCP2M0
PDC0
PRSEN
PDC6
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
PSSAC1
CVR3
PSSAC0
CVR2
PSSBD1
CVR1
PSSBD0
CVR0
CVREN
C2OUT
CVROE
C1OUT
CVRR
C2INV
—
C1INV
CIS
CM2
CM1
CM0
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3L
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
SPBRG
USART Baud Rate Generator
USART Receive Register
RCREG
48, 204,
203
TXREG
USART Transmit Register
0000 0000
48, 202,
203
TXSTA
RCSTA
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 -010
0000 000x
48, 196
48, 197
ADDEN
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
‘0’ in all other oscillator modes.
2:
3:
4:
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
5:
6:
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is
read-only.
2003 Microchip Technology Inc.
DS39599C-page 63
PIC18F2220/2320/4220/4320
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
Value on
POR, BOR
Details on
page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EEADR
EEDATA
EECON2
EECON1
IPR2
EEPROM Address Register
EEPROM Data Register
0000 0000
0000 0000
48, 81
48, 84
EEPROM Control Register 2 (not a physical register)
0000 0000 48, 72, 81
xx-0 x000 48, 73, 82
EEPGD
OSCFIP
OSCFIF
OSCFIE
PSPIP(5)
PSPIF(5)
PSPIE(5)
—
CFGS
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
—
—
—
FREE
EEIP
WRERR
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
WREN
LVDIP
WR
RD
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TUN0
11-1 1111
00-0 0000
00-0 0000
1111 1111
0000 0000
0000 0000
--00 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
49, 97
49, 93
PIR2
—
EEIF
LVDIF
PIE2
—
EEIE
LVDIE
49, 95
IPR1
RCIP
RCIF
RCIE
TUN5
IBOV
TXIP
CCP1IP
CCP1IF
CCP1IE
TUN2
49, 96
PIR1
TXIF
49, 92
PIE1
TXIE
49, 94
OSCTUNE
TRISE(5)
TRISD(5)
TRISC
TRISB
TRISA
LATE(5)
LATD(5)
LATC
TUN4
PSPMODE
23, 49
IBF
OBF
Data Direction bits for PORTE(5)
49, 112
49, 110
49, 108
49, 106
49, 103
49, 113
49, 110
49, 108
49, 106
49, 103
49, 113
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
TRISA7(2)
TRISA6(1) Data Direction Control Register for PORTA
—
—
—
—
—
Read/Write PORTE Data Latch
Read/Write PORTD Data Latch
Read/Write PORTC Data Latch
Read/Write PORTB Data Latch
LATB
LATA
LATA<7>(2) LATA<6>(1) Read/Write PORTA Data Latch
RE3(6)
PORTE
—
—
—
—
Read PORTE pins,
Write PORTE Data Latch(5)
PORTD
PORTC
PORTB
PORTA
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch(4)
RA7(2) RA6(1)
Read PORTA pins, Write PORTA Data Latch
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
49, 110
49, 108
49, 106
49, 103
Legend:
Note 1:
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
‘0’ in all other oscillator modes.
2:
3:
4:
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
5:
6:
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is
read-only.
DS39599C-page 64
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.10
Access Bank
5.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into as many as sixteen banks. When using
direct addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect (see Figure 5-7).
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
A
MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
• Faster evaluation/control of SFRs (no banking)
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
The Access Bank is comprised of the last 128 bytes in
Bank 15 (SFRs) and the first 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 5-6
indicates the Access RAM areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted as the ‘a’ bit (for
access bit).
A MOVFFinstruction ignores the BSR since the 12-bit
addresses are embedded into the instruction word.
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-
ing which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so these registers can
be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 5-7:
DIRECT ADDRESSING
Direct Addressing
(3)
From Opcode
BSR<7:4>
BSR<3:0>
7
0
0
0
0
0
(2)
(3)
Bank Select
Location Select
00h
000h
01h
100h
0Eh
E00h
0Fh
F00h
Data
Memory(1)
0FFh
Bank 0
1FFh
Bank 1
EFFh
FFFh
Bank 14
Bank 15
Note 1: For register file map detail, see Table 5-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
2003 Microchip Technology Inc.
DS39599C-page 65
PIC18F2220/2320/4220/4320
If INDF0, INDF1 or INDF2 are read indirectly via an
5.12 Indirect Addressing, INDF and
FSR Registers
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
status bits are not affected.
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 5-8
shows how the fetched instruction is modified prior to
being executed.
5.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation using one of these five registers
determines how the FSR will be modified during
indirect addressing.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address which is shown in
Figure 5-9.
When data access is performed using one of the five
INDFn locations, the address selected will configure
the FSRn register to:
• Do nothing to FSRn after an indirect access (no
change) – INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) – POSTDECn
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer); this is indirect addressing.
• Auto-increment FSRn after an indirect access
(post-increment) – POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) – PREINCn
Example 5-5 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
INDIRECT ADDRESSING
LFSR FSR0,0x100 ;
NEXT
CLRF POSTINC0
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
Auto-incrementing or auto-decrementing an FSR
affects all 12 bits. That is, when FSRnL overflows from
an increment, FSRnH will be incremented
automatically.
BTFSS FSR0H, 1
GOTO NEXT
CONTINUE
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its use for table operations
in data memory.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required:
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed. The
WREG offset range is -128 to +127.
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is set)
while an indirect write will be equivalent to a NOP
(status bits are not affected).
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If an indirect addressing write is performed when the
target address is an FSRnH or FSRnL register, the
data is written to the FSR register but no pre- or
post-increment/decrement is performed.
DS39599C-page 66
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 5-8:
INDIRECT ADDRESSING OPERATION
0h
RAM
Instruction
Executed
Opcode
Address
12
FFFh
File Address = access of an indirect addressing register
BSR<3:0>
12
12
Instruction
Fetched
4
8
Opcode
File
FSR
FIGURE 5-9:
INDIRECT ADDRESSING
Indirect Addressing
FSRnH:FSRnL
3
0
7
0
0
11
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 5-1.
2003 Microchip Technology Inc.
DS39599C-page 67
PIC18F2220/2320/4220/4320
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the Status register
5.13 Status Register
The Status register, shown in Register 5-2, contains the
arithmetic status of the ALU. The Status register can be
the operand for any instruction as with any other regis-
ter. If the Status register is the destination for an instruc-
tion that affects the Z, DC, C, OV or N bits, then the
write to these five bits is disabled. These bits are set or
cleared according to the device logic. Therefore, the
result of an instruction with the Status register as
destination may be different than intended.
as 000u u1uu(where u= unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the Status register, because these instructions do
not affect the Z, C, DC, OV or N bits in the Status reg-
ister. For other instructions not affecting any status bits,
see Table 24-2.
Note:
The C and DC bits operate as a borrow
and digit borrow bit respectively, in
subtraction.
REGISTER 5-2:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
N
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions.
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions.
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 68
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.14 RCON Register
Note 1: If the BOREN configuration bit is set
(Brown-out Reset enabled), the BOR bit
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
is ‘1’ on a Power-on Reset. After a Brown-
out Reset has occurred, the BOR bit will
be cleared and must be set by firmware to
indicate the occurrence of the next
Brown-out Reset.
2: It is recommended that the POR bit be set
after
a Power-on Reset has been
detected so that subsequent Power-on
Resets may be detected.
REGISTER 5-3:
RCON REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESETinstruction was executed causing a device Reset (must be set in software after
a Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Cleared by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 69
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 70
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The program memory space is 16 bits wide while the
6.0
FLASH PROGRAM MEMORY
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
Table read operations retrieve data from program
memory and place it into TABLAT in the data RAM
space. Figure 6-1 shows the operation of a table read
with program memory and data RAM.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.
Table write operations store data from TABLAT in the
data memory space into holding registers in program
memory. The procedure to write the contents of the
holding registers into program memory is detailed in
Section 6.5 “Writing to Flash Program Memory”.
Figure 6-2 shows the operation of a table write with
program memory and data RAM.
While writing or erasing program memory, instruction
fetches cease until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into program
memory, program instructions will need to be word
aligned (TBLPTRL<0> = 0).
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1
Table Reads and Table Writes
The EEPROM on-chip timer controls the write and
erase times. The write and erase voltages are gener-
ated by an on-chip charge pump rated to operate over
the voltage range of the device for byte or word
operations.
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
2003 Microchip Technology Inc.
DS39599C-page 71
PIC18F2220/2320/4220/4320
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled – the WR bit cannot be set while the WREN bit
is clear. This process helps to prevent accidental writes
to memory due to errant (unexpected) code execution.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
Firmware should keep the WREN bit clear at all times
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
6.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
The WRERR bit is set when a write operation is inter-
rupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It will be
necessary to reload the data and address registers
(EEDATA and EEADR) as these registers have cleared
as a result of the Reset.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.3 “Reading the
Flash Program Memory” regarding table reads.
The FREE bit controls program memory erase opera-
tions. When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.
DS39599C-page 72
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 6-1:
EECON1 REGISTER
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access program Flash memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1= Access configuration registers
0= Access program Flash or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation – TBLPTR<5:0> are ignored)
0= Perform write only
bit 3
WRERR: EEPROM Error Flag bit
1= A write operation was prematurely terminated (any Reset during self-timed programming)
0= The write operation completed normally
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: Write Enable bit
1= Allows erase or write cycles
0= Inhibits erase or write cycles
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write
cycle. (The operation is self-timed and the bit is cleared by hardware once write is
complete. The WR bit can only be set (not cleared) in software.)
0= Write cycle completed
bit 0
RD: Read Control bit
1= Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0= Read completed
Legend:
R = Readable bit
S = Settable only
U = Unimplemented bit, read as ‘0’ W = Writable bit
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR ‘1’ = Bit is set
2003 Microchip Technology Inc.
DS39599C-page 73
PIC18F2220/2320/4220/4320
6.2.2
TABLAT – TABLE LATCH REGISTER
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program or
configuration memory into TABLAT.
6.2.3
TBLPTR – TABLE POINTER
REGISTER
When a TBLWTis executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the TBLPTR (TBLPTR<21:3>) will deter-
mine which program memory block of 8 bytes is written
to (TBLPTR<2:0> are ignored). For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low order
21 bits allow the device to address up to 2 Mbytes of
program memory space. Setting the 22nd bit allows
access to the device ID, the user ID and the
configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR<21:6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
The table pointer, TBLPTR, is used by the TBLRDand
TBLWTinstructions. These instructions can update the
TBLPTR in one of four ways based on the table opera-
tion. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low order
21 bits.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
ERASE – TBLPTR<21:6>
LONG WRITE – TBLPTR<21:3>
READ or WRITE – TBLPTR<21:0>
DS39599C-page 74
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
6.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table
reads from program memory are performed one byte at
a time.
shows the interface between the internal program
memory and the TABLAT.
TBLPTR points to a byte address in program space.
Executing a TBLRDinstruction places the byte pointed
to into TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
Odd (High) Byte
Even (Low) Byte
TBLPTR
TBLPTR
LSB = 0
LSB = 1
Instruction Register
(IR)
TABLAT
Read Register
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVFW
; read into TABLAT and increment TBLPTR
; get data
TABLAT
MOVWF
WORD_EVEN
TBLRD*+
MOVFW
; read into TABLAT and increment TBLPTR
; get data
TABLAT
MOVWF
WORD_ODD
2003 Microchip Technology Inc.
DS39599C-page 75
PIC18F2220/2320/4220/4320
6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block size is 32 words or 64 bytes
under firmware control. Only through the use of an
external programmer, or through ICSP control, can
larger blocks of program memory be bulk erased. Word
erase in Flash memory is not supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer with address of row being
erased.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased;
TBLPTR<5:0> are ignored.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program
memory;
• clear the CFGS bit to access program
memory;
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash pro-
gram memory. The CFGS bit must be clear to access
program Flash and data EEPROM memory. The
WREN bit must be set to enable write operations. The
FREE bit is set to select an erase operation. The WR
bit is set as part of the required instruction sequence
(as shown in Example 6-2) and starts the actual erase
operation. It is not necessary to load the TABLAT
register with any data as it is ignored.
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
For protection, the write initiate sequence using
EECON2 must be used.
8. Execute a NOP.
9. Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1,EEPGD
EECON1,WREN
EECON1,FREE
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON2,WR
; point to Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write 55H
Required
Sequence
; write AAH
; start erase (CPU stall)
NOP
BSF
INTCON,GIE
; re-enable interrupts
DS39599C-page 76
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Since the Table Latch (TABLAT) is only a single byte,
6.5
Writing to Flash Program Memory
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The programming block size is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding reg-
isters needed to program the Flash memory. There are
8 holding registers used by the table writes for
programming.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx2
TBLPTR = xxxxx7
Holding Register
TBLPTR = xxxxx1
Holding Register
Holding Register
Holding Register
Program Memory
8. Disable interrupts.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer with address being erased.
13. Execute a NOP.
14. Re-enable interrupts.
4. Do the row erase procedure (see Section 6.4.1
“Flash Program Memory Erase Sequence”).
15. Repeat steps 6-14 seven times, to write 64
bytes.
5. Load Table Pointer with address of first byte
being written.
16. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
6. Write the first 8 bytes into the holding registers
with auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program
memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable byte writes.
2003 Microchip Technology Inc.
DS39599C-page 77
PIC18F2220/2320/4220/4320
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
D'64
; number of bytes in erase block
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; point to buffer
; Load TBLPTR with the base
; address of the memory block
; 6 LSB = 0
READ_BLOCK
TBLRD*+
MOVFW
; read into TABLAT, and inc
; get data
TABLAT
MOVWF
DECFSZ COUNTER
POSTINC0
; store data and increment FSR0
; done?
GOTO
READ_BLOCK
; repeat
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
; update buffer word and increment FSR0
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1,CFGS
EECON1,EEPGD
EECON1,WREN
EECON1,FREE
INTCON,GIE
55h
; load TBLPTR with the base
; address of the memory block
; 6 LSB = 0
; point to PROG/EEPROM memory
; point to Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
; Required sequence
; write 55H
EECON2
AAh
EECON2
EECON1,WR
; write AAH
; start erase (CPU stall)
NOP
BSF
INTCON,GIE
; re-enable interrupts
WRITE_BUFFER_BACK
MOVLW
8
; number of write buffer groups of 8 bytes
; point to buffer
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
COUNTER_HI
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
PROGRAM_LOOP
MOVLW
MOVWF
8
; number of bytes in holding register
COUNTER
WRITE_WORD_TO_HREGS
MOVFW
MOVWF
TBLWT+*
POSTINC0
TABLAT
; get low byte of buffer data and increment FSR0
; present data to table latch
; short write
; to internal TBLWT holding register, increment
TBLPTR
DECFSZ COUNTER
GOTO WRITE_WORD_TO_HREGS
; loop until buffers are full
DS39599C-page 78
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BCF
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
; disable interrupts
; required sequence
; write 55H
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write AAH
; start program (CPU stall)
NOP
BSF
INTCON,GIE
; re-enable interrupts
; loop until done
DECFSZ COUNTER_HI
GOTO
BCF
PROGRAM_LOOP
EECON1,WREN
; disable write to memory
6.5.2
WRITE VERIFY
6.6
Flash Program Operation During
Code Protection
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
See Section 23.0 “Special Features of the CPU”
(Section 23.5 “Program Verification and Code Pro-
tection”) for details on code protection of Flash
program memory.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset, during normal operation. In
these situations, users can check the WRERR bit and
rewrite the location.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Value on
Value on:
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
--00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
TABLAT
INTCON
EECON2
EECON1
IPR2
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
RD
EEPROM Control Register 2 (not a physical register)
—
—
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR WREN
WR
xx-0 x000 uu-0 u000
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP
TMR3IF
TMR3IE
CCP2IP 11-1 1111 ---1 1111
CCP2IF 00-0 0000 ---0 0000
CCP2IE 00-0 0000 ---0 0000
PIR2
PIE2
Legend:
x= unknown, u= unchanged, r = reserved, -= unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
2003 Microchip Technology Inc.
DS39599C-page 79
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 80
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Control bit CFGS determines if the access will be to the
configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
7.0
DATA EEPROM MEMORY
The data EEPROM is readable and writable during nor-
mal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled; the WR bit cannot be set while the WREN bit
is clear. This mechanism helps to prevent accidental
writes to memory due to errant (unexpected) code
execution.
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
• EECON1
• EECON2
• EEDATA
• EEADR
Firmware should keep the WREN bit clear at all times
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 00h to FFh.
The WRERR bit is set when a write operation is inter-
rupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It is nec-
essary to reload the data and address registers
(EEDATA and EEADR), as these registers have
cleared as a result of the Reset.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write time
will vary with voltage and temperature, as well as from
chip to chip. Please refer to parameter D122 (Table 26-1
in Section 26.0 “Electrical Characteristics”) for exact
limits.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
7.1
EEADR
The address register can address 256 bytes of data
EEPROM.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
7.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit EEPGD determines if the access will be to
program or data EEPROM memory. When clear, oper-
ations will access the data EEPROM memory. When
set, program memory is accessed.
2003 Microchip Technology Inc.
DS39599C-page 81
PIC18F2220/2320/4220/4320
REGISTER 7-1:
EECON1 REGISTER
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access program Flash memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1= Access configuration or calibration registers
0= Access program Flash or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command (cleared
by completion of erase operation)
0= Perform write only
bit 3
WRERR: EEPROM Error Flag bit
1= A write operation was prematurely terminated
(MCLR or WDT Reset during self-timed erase or program operation)
0= The write operation completed normally
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: Erase/Write Enable bit
1= Allows erase/write cycles
0= Inhibits erase/write cycles
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle is completed
bit 0
RD: Read Control bit
1= Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0= Read completed
Legend:
R = Readable bit
S = Settable only U = Unimplemented bit, read as ‘0’ W = Writable bit
- n = Value at POR ‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
DS39599C-page 82
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation or until it is written to
by the user (during a write operation).
set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit. EEIF must be cleared by software.
7.5
Write Verify
7.4
Writing to the Data EEPROM
Memory
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write AAh to EECON2,
then set WR bit) for each byte. It is strongly recom-
mended that interrupts be disabled during this
code segment.
7.6
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times except when updating the
EEPROM. The WREN bit is not cleared by hardware.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
EXAMPLE 7-1:
DATA EEPROM READ
MOVLW
MOVWF
BCF
BSF
MOVF
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, RD
EEDATA, W
;
; Data Memory Address to read
; Point to DATA memory
; EEPROM Read
; W = EEDATA
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
MOVWF
DATA_EE_ADDR
EEADR
;
; Data Memory Address to write
MOVLW
MOVWF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
;
; Data Memory Value to write
; Point to DATA memory
; Enable writes
; Disable Interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Enable Interrupts
Required
Sequence
BSF
SLEEP
BCF
; Wait for interrupt to signal write complete
; Disable writes
EECON1, WREN
2003 Microchip Technology Inc.
DS39599C-page 83
PIC18F2220/2320/4220/4320
7.7
Operation During Code-Protect
7.8
Using the Data EEPROM
Data EEPROM memory has its own code-protect bits in
configuration words. External read and write opera-
tions are disabled if either of these mechanisms are
enabled.
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124 or D124A. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
The microcontroller itself can both read and write to the
internal Data EEPROM regardless of the state of the
code-protect configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF
EEADR
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
LOOP
BSF
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR, F
; Increment address
BRA
Loop
; Not zero, do it again
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
TABLE 7-1:
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
EEADR
EEDATA
GIE/GIEH PEIE/GIEL TMR0IE
EEPROM Address Register
EEPROM Data Register
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register)
—
—
EECON1
IPR2
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR WREN
WR
RD
xx-0 x000 uu-0 u000
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP CCP2IP 11-1 1111 ---1 1111
TMR3IF CCP2IF 00-0 0000 ---0 0000
TMR3IE CCP2IE 00-0 0000 ---0 0000
PIR2
PIE2
Legend:
x= unknown, u= unchanged, r= reserved, -= unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
DS39599C-page 84
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Making the 8 x 8 multiplier execute in a single-cycle
gives the following advantages:
8.0
8.1
8 X 8 HARDWARE MULTIPLIER
• Higher computational throughput
Introduction
• Reduces code size requirements for multiply
algorithms
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F2X20/4X20 devices. By making the multiply
a hardware operation, it completes in a single instruc-
tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the Status register.
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Program
Time
Cycles
(Max)
Multiply Method
Memory
(Words)
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.8 µs
25.4 µs
4.0 µs
27.6 µs
400 ns
36.4 µs
2.4 µs
69 µs
1 µs
91 µs
6 µs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 µs
11.2 µs
102.6 µs
16.0 µs
242 µs
28 µs
254 µs
40 µs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8.2
Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
MOVF
ARG1, W
ARG2
;
MULWF
; ARG1 * ARG2 ->
;
PRODH:PRODL
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
ARG1, W
ARG2
MULWF
; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC
SUBWF
ARG2, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
2003 Microchip Technology Inc.
DS39599C-page 85
PIC18F2220/2320/4220/4320
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 216) +
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H ² 28) +
(ARG1L • ARG2L) +
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, W
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39599C-page 86
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
9.0
INTERRUPTS
compatible with PICmicro® mid-range devices. In Com-
patibility mode, the interrupt priority bits for each source
have no effect. INTCON<6> is the PEIE bit which
enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
The PIC18F2320/4320 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will
interrupt any low priority interrupts that may be in
progress.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
In general, each interrupt source has three bits to
control its operation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
(most interrupt sources have priority bits)
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all inter-
rupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will vec-
tor immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual inter-
rupts can be disabled through their corresponding
enable bits.
2003 Microchip Technology Inc.
DS39599C-page 87
PIC18F2220/2320/4220/4320
FIGURE 9-1:
INTERRUPT LOGIC
Wake-up if in
Power Managed Mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
PSPIF
PSPIE
PSPIP
GIEH/GIE
ADIF
ADIE
ADIP
IPE
IPEN
RCIF
RCIE
RCIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
PSPIF
PSPIE
PSPIP
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
ADIF
ADIE
ADIP
RBIF
RBIE
RBIP
RCIF
RCIE
RCIP
GIEL\PEIE
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39599C-page 88
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 9-1:
INTCON REGISTER
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
GIE/GIEH PEIE/GIEL
bit 7
TMR0IE
INT0IE
TMR0IF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all high priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 89
PIC18F2220/2320/4220/4320
REGISTER 9-2:
INTCON2 REGISTER
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
U-0
—
R/W-1
U-0
—
R/W-1
RBIP
INTEDG0 INTEDG1 INTEDG2
TMR0IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 3
bit 2
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
DS39599C-page 90
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 9-3:
INTCON3 REGISTER
R/W-1
R/W-1
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
2003 Microchip Technology Inc.
DS39599C-page 91
PIC18F2220/2320/4220/4320
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag registers (PIR1, PIR2).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 0
bit 7
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit clear.
bit 6
bit 5
bit 4
bit 3
bit 2
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The USART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 92
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
R/W-0
CMIF
U-0
—
R/W-0
EEIF
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
R/W-0
TMR3IF
CCP2IF
bit 0
bit 7
bit 6
OSCFIF: Oscillator Fail Interrupt Flag bit
1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= System clock operating
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1= The write operation is complete (must be cleared in software)
0= The write operation is not complete, or has not been started
bit 3
bit 2
bit 1
bit 0
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
LVDIF: Low-Voltage Detect Interrupt Flag bit
1= A low-voltage condition occurred (must be cleared in software)
0= The device voltage is above the Low-Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
CCP2IF: CCPx Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 93
PIC18F2220/2320/4220/4320
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Enable registers (PIE1, PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 9-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
CCP1IE
TMR2IE
bit 7
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit clear.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 94
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 9-7:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
CMIE
U-0
—
R/W-0
EEIE
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
R/W-0
TMR3IE
CCP2IE
bit 0
bit 7
bit 6
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit
1= Enabled
0= Disabled
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1= Enabled
0= Disabled
bit 3
bit 2
bit 1
bit 0
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
CCP2IE: CCP2 Interrupt Enable bit
1= Enabled
0= Disabled
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 95
PIC18F2220/2320/4220/4320
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Priority registers (IPR1, IPR2). Using the priority
bits requires that the Interrupt Priority Enable (IPEN) bit
be set.
REGISTER 9-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
bit 7
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
R/W-1
R/W-1
TMR1IP
bit 0
CCP1IP
TMR2IP
bit 7
PSPIP(1): Parallel Slave Port Read/Write Interrupt Priority bit
1= High priority
0= Low priority
Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit set.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: USART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: USART Transmit Interrupt Priority bit
1= High priority
0= Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 96
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 9-9:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
OSCFIP
bit 7
R/W-1
CMIP
U-0
—
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
R/W-1
TMR3IP
CCP2IP
bit 0
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
LVDIP: Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 97
PIC18F2220/2320/4220/4320
9.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from power man-
aged mode. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-10: RCON REGISTER
R/W-0
IPEN
bit 7
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESETinstruction was executed causing a device Reset (must be set in software after
a Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-Down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Cleared by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 98
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
9.6
INTn Pin Interrupts
9.8
PORTB Interrupt-on-Change
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising if the
corresponding INTEDGx bit is set in the INTCON2 reg-
ister, or falling if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared in software in the Interrupt Ser-
vice Routine before re-enabling the interrupt. All exter-
nal interrupts (INT0, INT1 and INT2) can wake-up the
processor from the power managed modes if bit INTxE
was set prior to going into power managed modes. If
the global interrupt enable bit GIE is set, the processor
will branch to the interrupt vector following wake-up.
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on the
stack. Additionally, the WREG, Status and BSR registers
are saved on the fast return stack. If a fast return from
interrupt is not used (See Section 5.3 “Fast Register
Stack”), the user may need to save the WREG, Status
and BSR registers on entry to the Interrupt Service Rou-
tine. Depending on the user’s application, other registers
may also need to be saved. Example 9-1 saves and
restores the WREG, Status and BSR registers during an
Interrupt Service Routine.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the Interrupt Priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
9.7
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow
(FFh → 00h) in the TMR0 register will set flag bit
TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h)
in the TMR0H:TMR0L registers will set flag bit TMR0IF.
The interrupt can be enabled/disabled by setting/clear-
ing enable bit, TMR0IE (INTCON<5>). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
Section 11.0 “Timer0 Module” for further details on
the Timer0 module.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
2003 Microchip Technology Inc.
DS39599C-page 99
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 100
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
10.1 PORTA, TRISA and LATA
Registers
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate func-
tion from the peripheral features on the device. In gen-
eral, when a peripheral is enabled, that pin may not be
used as a general purpose I/O pin.
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Each port has three registers for its operation. These
registers are:
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
• LAT register (Data Latch)
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in Configuration Register 1H (see
Section 23.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in Figure 10-1.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the com-
parator voltage reference output. The operation of pins,
RA3:RA0 and RA5, as A/D converter inputs is selected
by clearing/setting the control bits in the ADCON1 reg-
ister (A/D Control Register 1). Pins RA0 through RA5
may also be used as comparator inputs or outputs by
setting the appropriate bits in the CMCON register.
RD LAT
Data
Bus
D
Q
WR LAT
I/O pin(1)
or
Port
CK
Data Latch
D
Q
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input
and an open-drain output. All other PORTA pins have
TTL input levels and full CMOS output drivers.
The TRISA register controls the direction of the RA pins
even when they are being used as analog inputs. The
user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Q
D
EN
RD Port
EXAMPLE 10-1:
INITIALIZING PORTA
Note 1: I/O pins have diode protection to VDD and VSS.
CLRF
PORTA
LATA
0x07
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
2003 Microchip Technology Inc.
DS39599C-page 101
PIC18F2220/2320/4220/4320
FIGURE 10-2:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 10-4:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
RD LATA
RD LATA
Data
Bus
Data
Bus
D
Q
D
Q
WR LATA
or
PORTA
VDD
WR LATA
or
PORTA
Q
I/O pin(1)
Q
Data Latch
CK
CK
P
N
Data Latch
I/O pin(1)
N
D
Q
Q
VSS
D
Q
WR TRISA
RD TRISA
Schmitt
Trigger
Input
WR TRISA
CK
VSS
Q
CK
Analog
Input
Mode
TRIS Latch
TRIS Latch
Buffer
RD TRISA
TTL
Input
Buffer
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
SS Input (RA5 only)
TMR0 Clock Input
Note 1: I/O pins have protection diodes to VDD and VSS.
To A/D Converter and LVD Modules
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 10-5:
BLOCK DIAGRAM OF
RA7 PIN
FIGURE 10-3:
BLOCK DIAGRAM OF
RA6 PIN
RA6 Enable
RA7 Enable
To Oscillator
Data
Bus
Data
Bus
RD LATA
RD LATA
D
D
Q
Q
Q
Q
VDD
P
VDD
P
WR LATA
WR LATA
or
or
PORTA
PORTA
CK
CK
Data Latch
Data Latch
I/O pin(1)
I/O pin(1)
N
N
D
Q
D
Q
WR
WR
TRISA
TRISA
VSS
VSS
CK
CK
Q
Q
TRIS Latch
TRIS Latch
RD
RD
TRISA
TTL
Input
Buffer
TTL
Input
Buffer
TRISA
ECIO or
RCIO
RA7
Enable
Enable
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
2003 Microchip Technology Inc.
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39599C-page 102
PIC18F2220/2320/4220/4320
TABLE 10-1: PORTA FUNCTIONS
Name
Bit#
Buffer
Function
Input/output or analog input.
RA0/AN0
RA1/AN1
bit 0
bit 1
bit 2
bit 3
bit 4
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Input/output, analog input, VREF- or Comparator VREF output.
Input/output, analog input or VREF+.
RA4/T0CKI/C1OUT
Input/output, external clock input for Timer0 or Comparator 1
output. Output is open-drain type.
RA5/AN4/SS/LVDIN/C2OUT
bit 5
TTL
Input/output, analog input, Slave Select input for Synchronous
Serial Port, Low-Voltage Detect input or Comparator 2 output.
OSC2/CLKO/RA6
OSC1/CLKI/RA7
bit 6
bit 7
TTL
TTL
OSC2, clock output or I/O pin.
OSC1, clock input or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xx0x 0000 uu0u 0000
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
(1)
(1)
LATA
LATA7
LATA6
LATA Data Latch Register
(1)
(1)
TRISA
TRISA7
—
TRISA6
—
PORTA Data Direction Register
ADCON1
CMCON
CVRCON
VCFG1
C2INV
CVRR
VCFG0
C1INV
—
PCFG3
CIS
PCFG2
CM2
PCFG1
CM1
PCFG0 --00 0000 --00 0000
C2OUT
CVREN
C1OUT
CVROE
CM0
0000 0111 0000 0111
000- 0000 000- 0000
CVR3
CVR2
CVR1
CVR0
Legend: x= unknown, u= unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
2003 Microchip Technology Inc.
DS39599C-page 103
PIC18F2220/2320/4220/4320
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
EXAMPLE 10-2:
INITIALIZING PORTB
CLRF
PORTB
LATB
0x0F
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
RB3 can be configured by the configuration bit,
CCP2MX, as the alternate peripheral pin for the CCP2
module (CCP2MX = 0).
CLRF
FIGURE 10-6:
BLOCK DIAGRAM OF
RB7:RB5 PINS
MOVLW
MOVWF
; Set RB<4:0> as
ADCON1 ; digital I/O pins
; (required if config bit
VDD
RBPU(2)
Data Bus
Weak
Pull-up
; PBADEN is set)
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
P
MOVLW
MOVWF
0xCF
Data Latch
D
Q
WR LATB
or PORTB
I/O pin(1)
TRISB
CK
TRIS Latch
D
Q
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
WR TRISB
TTL
Input
Buffer
CK
ST
Buffer
RD TRISB
RD LATB
Note:
On a Power-on Reset, RB4:RB0 are con-
figured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
Latch
Q
Q
D
RD PORTB
Set RBIF
EN
Q1
By programming the configuration bit,
PBADEN (CONFIG3H<1>), RB4:RB0 will
alternatively be configured as digital inputs
on POR.
D
RD PORTB
Q3
From other
RB7:RB5 and
RB4 pins
EN
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
RB7:RB5 in Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
DS39599C-page 104
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 10-7:
BLOCK DIAGRAM OF
RB2:RB0 PINS
FIGURE 10-8:
BLOCK DIAGRAM OF
RB4 PIN
VDD
VDD
RBPU(2)
Analog Input Mode
RBPU(2)
Data Bus
Weak
Pull-up
Weak
Pull-up
P
P
Data Latch
D
Q
Data Bus
D
Q
I/O pin(1)
WR LATB
or PORTB
I/O pin(1)
WR LATB
or PORTB
CK
TRIS Latch
CK
Data Latch
D
Q
D
Q
WR TRISB
TTL
Input
Buffer
CK
WR TRISB
CK
TRIS Latch
TTL
Input
Buffer
RD TRISB
RD LATB
RD TRISB
RD LATB
Latch
Q
Q
D
RD PORTB
Set RBIF
Q
D
EN
Q1
EN
RD PORTB
D
Schmitt Trigger
Buffer
RD PORTB
Q3
INTx
From RB7:RB5
EN
To A/D Converter
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2<7>).
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
FIGURE 10-9:
BLOCK DIAGRAM OF RB3/CCP2 PIN
VDD
Port/CCP2 Select
CCP2 Data Out
RBPU
Weak
P
Analog Input Mode
Pull-up
0
1
RD LATC
VDD
P
Data Bus
D
Q
WR LATB
or PORTB
CK
Data Latch
RB3 pin(1)
TTL Input
Buffer
D
Q
N
WR TRISB
RD TRISC
CK
TRIS Latch
VSS
Q
D
EN
Schmitt
Trigger
RD PORTB
CCP2 Input
Analog Input Mode
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
2003 Microchip Technology Inc.
DS39599C-page 105
PIC18F2220/2320/4220/4320
TABLE 10-3: PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/AN12/INT0
bit 0
TTL(1)/ST(2) Input/output pin, analog input or external interrupt input 0.
Internal software programmable weak pull-up.
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2
bit 1
bit 2
bit 3
TTL(1)/ST(2) Input/output pin, analog input or external interrupt input 1.
Internal software programmable weak pull-up.
TTL(1)/ST(2) Input/output pin, analog input or external interrupt input 2.
Internal software programmable weak pull-up.
TTL(1)/ST(3) Input/output pin or analog input. Capture2 input/Compare2 output/
PWM output when CCP2MX configuration bit is set(4)
Internal software programmable weak pull-up.
.
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
bit 4
bit 5
bit 6
bit 7
TTL
Input/output pin (with interrupt-on-change) or analog input.
Internal software programmable weak pull-up.
TTL/ST(5) Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Low-voltage ICSP enable pin.
TTL/ST(5) Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming clock.
TTL/ST(5) Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a TTL input when configured as digital I/O.
2: This buffer is a Schmitt Trigger input when configured as the external interrupt.
3: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
4: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
5: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxq qqqq
xxxx xxxx
1111 1111
0000 000x
1111 -1-1
uuuu uuuu
uuuu uuuu
1111 1111
0000 000u
1111 -1-1
11-0 0-00
--00 0000
LATB Data Latch Register
TRISB
PORTB Data Direction Register
GIE/GIEH PEIE/GIEL TMR0IE
INTCON
INTCON2
INTCON3
ADCON1
Legend:
INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
RBIP
RBPU
INT2IP
—
INTEDG0 INTEDG1 INTEDG2
TMR0IP
—
—
INT1IP
—
—
INT2IE
VCFG0
INT1IE
INT2IF
INT1IF 11-0 0-00
VCFG1
PCFG3 PCFG2 PCFG1 PCFG0 --00 0000
x= unknown, u= unchanged, q= value depends on condition. Shaded cells are not used by PORTB.
DS39599C-page 106
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
10.3 PORTC, TRISC and LATC
Registers
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
CLRF
LATC
; Alternate method
; to clear output
; data latches
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input buff-
ers. RC1 is normally configured by configuration bit,
CCP2MX (CONFIG3H<0>), as the default peripheral
pin of the CCP2 module (default/erased state,
CCP2MX = 1).
MOVLW
MOVWF
0xCF
; Value used to
;initializedata
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
TRISC
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
FIGURE 10-10:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(2)
VDD
Peripheral Data Out
RD LATC
0
Data Bus
D
Q
Q
P
WR LATC or
WR PORTC
1
CK
I/O pin(1)
Data Latch
D
Q
WR TRISC
RD TRISC
N
Q
CK
TRIS Latch
Schmitt
Trigger
VSS
Peripheral Output
Enable(3)
Q
D
EN
RD PORTC
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port data (output) and peripheral output.
3: Peripheral Output Enable is only active if Peripheral Select is active.
2003 Microchip Technology Inc.
DS39599C-page 107
PIC18F2220/2320/4220/4320
TABLE 10-5: PORTC FUNCTIONS
Name
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
bit 0
bit 1
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
Input/output port pin, Timer1 oscillator input or Capture2 input/
Compare2 output/PWM output when CCP2MX configuration bit is
disabled.
RC2/CCP1/P1A(1)
RC3/SCK/SCL
bit 2
bit 3
ST
ST
Input/output port pin, Capture1 input/Compare1 output/PWM1 output
or enhanced PWM output A(1)
.
RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA
RC5/SDO
bit 4
bit 5
bit 6
ST
ST
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK
Input/output port pin, Addressable USART Asynchronous Transmit or
Addressable USART Synchronous Clock.
RC7/RX/DT
bit 7
ST
Input/output port pin, Addressable USART Asynchronous Receive or
Addressable USART Synchronous Data.
Legend: ST = Schmitt Trigger input
Note 1: Enhanced PWM output is available only on PIC18F4X20 devices.
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
LATC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
LATC Data Latch Register
PORTC Data Direction Register
TRISC
Legend: x= unknown, u= unchanged
DS39599C-page 108
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
10.4 PORTD, TRISD and LATD
Registers
buffers are TTL. See Section 10.6 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
Note:
PORTD is only available on PIC18F4X20
devices.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note:
When the enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
The Data Latch register (LATD) is also memory mapped.
Read-modify-write operations on the LATD register read
and write the latched output value for PORTD.
CLRF
LATD
All pins on PORTD are implemented with Schmitt Trig-
ger input buffers. Each pin is individually configurable
as an input or output.
MOVLW
MOVWF
0xCF
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
TRISD
:
Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
FIGURE 10-11:
BLOCK DIAGRAM OF RD7:RD5 PINS
PORTD/CCP1 Select
CCP Data Out
PSPMODE
RD LATD
Data Bus
WR LATD
0
1
D
Q
Q
VDD
P
or
PORTD
CK
Data Latch
D
Q
I/O pin(1)
WR TRISD
PSP Read
RD TRISD
Q
CK
0
1
N
TRIS Latch
VSS
TTL Buffer
1
0
Q
D
EN
RD PORTD
PSP Write
Schmitt Trigger
Input Buffer
0
1
Note 1: I/O pins have diode protection to VDD and VSS.
2003 Microchip Technology Inc.
DS39599C-page 109
PIC18F2220/2320/4220/4320
FIGURE 10-12:
BLOCK DIAGRAM OF RD4:RD0 PINS
PORTD/CCP1 Select
PSPMODE
RD LATD
Data Bus
VDD
P
D
Q
Q
WR LATD
or
PORTD
CK
Data Latch
D
Q
I/O pin(1)
WR TRISD
PSP Read
RD TRISD
Q
CK
0
1
N
TRIS Latch
VSS
TTL Buffer
1
0
Q
D
EN
RD PORTD
PSP Write
Schmitt Trigger
Input Buffer
0
1
Note 1: I/O pins have diode protection to VDD and VSS.
TABLE 10-7: PORTD FUNCTIONS
Name
Bit# Buffer Type
Function
RD0/PSP0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
ST/TTL(1) Input/output port pin or Parallel Slave Port bit 0.
ST/TTL(1) Input/output port pin or Parallel Slave Port bit 1.
ST/TTL(1) Input/output port pin or Parallel Slave Port bit 2.
ST/TTL(1) Input/output port pin or Parallel Slave Port bit 3.
ST/TTL(1) Input/output port pin or Parallel Slave Port bit 4.
ST/TTL(1) Input/output port pin, Parallel Slave Port bit 5 or enhanced PWM output P1B.
ST/TTL(1) Input/output port pin, Parallel Slave Port bit 6 or enhanced PWM output P1C.
ST/TTL(1) Input/output port pin, Parallel Slave Port bit 7 or enhanced PWM output P1D.
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
PORTD
LATD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
xxxx xxxx
1111 1111
0000 -111
uuuu uuuu
uuuu uuuu
1111 1111
0000 -111
0000 0000
LATD Data Latch Register
TRISD
PORTD Data Direction Register
TRISE
IBF
OBF
IBOV
PSPMODE
DC1B0
—
PORTE Data Direction bits
CCP1CON
Legend:
P1M1
P1M0
DC1B1
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
DS39599C-page 110
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
10.5.1
PORTE IN 28-PIN DEVICES
10.5 PORTE, TRISE and LATE
Registers
For PIC18F2X20 devices, PORTE is only available
when Master Clear functionality is disabled
(CONFIG3H<7> = 0). In these cases, PORTE is a
single bit, input only port comprised of RE3 only. The
pin operates as previously described.
Depending on the particular PIC18F2X20/4X20 device
selected, PORTE is implemented in two different ways.
For PIC18F4X20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/
AN7/CS) are individually configurable as inputs or out-
puts. These pins have Schmitt Trigger input buffers.
When selected as an analog input, these pins will read
as ‘0’s.
FIGURE 10-13:
BLOCK DIAGRAM OF
RE2:RE0 PINS
RD LATE
Data
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISE
bit (= 0) will make the corresponding PORTE pin an
output (i.e., put the contents of the output latch on the
selected pin).
Bus
D
Q
WR LATE
or
PORTE
I/O pin(1)
CK
Data Latch
TRISE controls the direction of the RE pins even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
D
Q
WR TRISE
RD TRISE
Schmitt
Trigger
Input
CK
TRIS Latch
Note:
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
Buffer
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
Q
D
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
EN
RD PORTE
To Analog Converter
Note 1: I/O pins have diode protection to VDD and VSS.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE con-
figuration bit in Configuration Register 3H
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
FIGURE 10-14:
BLOCK DIAGRAM OF
MCLR/VPP/RE3 PIN
MCLRE
Data Bus
MCLR/VPP/
RE3
Note:
On a Power-on Reset, RE3 is enabled as
digital input only if Master Clear
functionality is disabled.
RD TRISE
RD LATE
a
Schmitt
Trigger
EXAMPLE 10-5:
CLRF
INITIALIZING PORTE
Latch
D
PORTE
LATE
0x0A
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
Q
EN
CLRF
RD PORTE
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
High-Voltage Detect
HV
0x03
; Value used to
; initialize data
; direction
Internal MCLR
Filter
MOVWF
TRISC
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
Low-Level
MCLR Detect
2003 Microchip Technology Inc.
DS39599C-page 111
PIC18F2220/2320/4220/4320
REGISTER 10-1: TRISE REGISTER
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
TRISE2
TRISE1
TRISE0
bit 7
bit 0
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in
software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General Purpose I/O mode
bit 3
bit 2
Unimplemented: Read as ‘0’
TRISE2: RE2 Direction Control bit
1= Input
0= Output
bit 1
bit 0
TRISE1: RE1 Direction Control bit
1= Input
0= Output
TRISE0: RE0 Direction Control bit
1= Input
0= Output
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 112
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 10-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
MCLR/VPP/RE3
bit 0
ST/TTL(1)
Input/output port pin, analog input or read control input in Parallel Slave
Port mode.
For RD (PSP Control mode):
1= PSP is Idle
0= Read operation. Reads PORTD register (if chip selected).
bit 1
bit 2
bit 3
ST/TTL(1)
ST/TTL(1)
ST
Input/output port pin, analog input or write control input in Parallel
Slave Port mode.
For WR (PSP Control mode):
1= PSP is Idle
0= Write operation. Writes PORTD register (if chip selected).
Input/output port pin, analog input or chip select control input in Parallel
Slave Port mode.
For CS (PSP Control mode):
1= PSP is Idle
0= External device is selected
Input only port pin or programming voltage input (if MCLR is disabled);
Master Clear input or programming voltage input (if MCLR is enabled).
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
(1)
PORTE
LATE
—
—
—
—
—
—
—
—
RE3
—
RE2
RE1
RE0
---- q000 ---- q000
---- -xxx ---- -uuu
0000 -111 0000 -111
LATE Data Latch Register
PORTE Data Direction bits
TRISE
IBF
—
OBF
—
IBOV
VCFG1
PSPMODE
VCFG0
—
ADCON1
Legend:
PCFG3
PCFG2
PCFG1
PCFG0 --00 0000 --00 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0).
2003 Microchip Technology Inc.
DS39599C-page 113
PIC18F2220/2320/4220/4320
The timing for the control signals in Write and Read
modes is shown in Figure 10-16 and Figure 10-17,
respectively.
10.6 Parallel Slave Port
Note:
The Parallel Slave Port is only available on
PIC18F4X20 devices.
FIGURE 10-15:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is con-
trolled by the 4 upper bits of the TRISE register
(Register 10-1). Setting control bit, PSPMODE
(TRISE<4>), enables PSP operation, as long as the
Enhanced CCP module is not operating in dual output
or quad output PWM mode. In Slave mode, the port is
asynchronously readable and writable by the external
world.
One bit of PORTD
Data Bus
D
Q
RDx pin
WR LATD
or
WR PORTD
CK
Data Latch
TTL
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit, PSPMODE, enables the PORTE I/O
pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For
this functionality, the corresponding data direction bits
of the TRISE register (TRISE<2:0>) must be config-
ured as inputs (set). The A/D port configuration bits
PFCG3:PFCG0 (ADCON1<3:0>) must also be set to
‘1010’.
Q
D
RD PORTD
RD LATD
EN
Set Interrupt Flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
PORTE Pins
Read
RD
CS
WR
TTL
Chip Select
TTL
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
Write
TTL
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit is
set. User applications should wait for PSPIF to be set
before servicing the PSP; when this happens, the IBF and
OBF bits can be polled and the appropriate action taken.
Note:
I/O pins have diode protection to VDD and VSS.
DS39599C-page 114
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 10-16:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-17:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
Port Data Latch when written; Port pins when read
LATD Data Latch bits
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---- 0000 ---- 0000
---- -xxx ---- -uuu
0000 -111 0000 -111
0000 000x 0000 000u
TRISD
PORTE
LATE
PORTD Data Direction bits
—
—
—
—
—
—
—
—
RE3
—
RE2
RE1
RE0
LATE Data Latch bits
PORTE Data Direction bits
TMR0IF INT0IF RBIF
TRISE
INTCON
IBF
OBF
IBOV
TMR0IF
PSPMODE
INT0IE
—
GIE/
GIEH
PEIE/
GIEL
RBIE
PIR1
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF
TMR1IF 0000 0000 0000 0000
PIE1
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
IPR1
RCIP
TXIP
ADCON1
Legend:
VCFG1
VCFG0
PCFG3 PCFG2
PCFG1
PCFG0
--00 0000 --00 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
2003 Microchip Technology Inc.
DS39599C-page 115
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 116
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
11.0 TIMER0 MODULE
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit
timer/counter
The T0CON register (Register 11-1) is a readable and
writable register that controls all the aspects of Timer0,
• Readable and writable
including the prescale selection.
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
bit 0
T08BIT
bit 7
bit 6
bit 5
bit 4
bit 3
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 prescale value
110= 1:128 prescale value
101= 1:64 prescale value
100= 1:32 prescale value
011= 1:16 prescale value
010= 1:8 prescale value
001= 1:4 prescale value
000= 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 117
PIC18F2220/2320/4220/4320
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
8
FOSC/4
0
1
RA4/T0CKI/C1OUT
pin
0
Sync with
Internal
Clocks
TMR0
Programmable
Prescaler
1
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
RA4/T0CKI/C1OUT
pin
FOSC/4
0
1
0
1
Sync with
Internal
Clocks
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
TMR0L
Programmable
Prescaler
8
(2 TCY delay)
T0SE
3
Read TMR0L
Write TMR0L
T0PS2, T0PS1, T0PS0
T0CS
PSA
8
8
TMR0H
8
Data Bus<7:0>
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
DS39599C-page 118
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
11.2.1
SWITCHING PRESCALER
ASSIGNMENT
11.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
11.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module Interrupt Service
Routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from Sleep
mode, since the timer requires clock cycles, even when
T0CS is set.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the
rising edge.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.4 16-Bit Mode Timer Reads and
Writes
11.2 Prescaler
TMR0H is not the high byte of the timer/counter in
16-bit mode but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0, without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
TMR0H
INTCON
T0CON
TRISA
Timer0 Module Low Byte Register
Timer0 Module High Byte Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 000x 0000 000u
1111 1111 1111 1111
1111 1111 1111 1111
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
PSA
TMR0IF INT0IF
T0PS2 T0PS1
RBIF
TMR0ON
T08BIT
T0CS
T0SE
T0PS0
(1)
(1)
RA7
RA6
PORTA Data Direction Register
Legend:
x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H.
2003 Microchip Technology Inc.
DS39599C-page 119
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 120
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Register 12-1 details the Timer1 Control register. This
register controls the operating mode of the Timer1
module and contains the Timer1 Oscillator Enable bit
(T1OSCEN). Timer1 can be enabled or disabled by
setting or clearing control bit, TMR1ON (T1CON<0>).
12.0 TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter (two 8-bit registers: TMR1H
and TMR1L)
The Timer1 oscillator can be used as a secondary clock
source in power managed modes. When the T1RUN bit
is set, the Timer1 oscillator is providing the system clock.
If the Fail-Safe Clock Monitor is enabled and the Timer1
oscillator fails while providing the system clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
• Status of system clock operation
Figure 12-1 is a simplified block diagram of the Timer1
module.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
bit 6
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of TImer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
T1RUN: Timer1 System Clock Status bit
1= System clock is derived from Timer1 oscillator
0= System clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 prescale value
10= 1:4 prescale value
01= 1:2 prescale value
00= 1:1 prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1(External Clock):
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0(Internal Clock):
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 121
PIC18F2220/2320/4220/4320
When TMR1CS = 0, Timer1 increments every instruc-
12.1 Timer1 Operation
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. The TRISC1:TRISC0 values are
ignored and the pins read as ‘0’.
The operating mode is determined by the Clock Select
bit, TMR1CS (T1CON<1>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
Synchronized
TMR1
CLR
0
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
1
T1CKI/T1OSO
T1OSI
Synchronize
det
T1OSCEN
Enable
Prescaler
1, 2, 4, 8
(1)
FOSC/4
Internal
Clock
Oscillator
0
2
Peripheral Clocks
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
0
TMR1IF
Overflow
Interrupt
Synchronized
Clock Input
TMR1
8
CLR
Timer 1
High Byte
TMR1L
Flag bit
1
TMR1ON
on/off
T1SYNC
T1OSC
T1CKI/T1OSO
1
Synchronize
Prescaler
1, 2, 4, 8
T1OSCEN
det
FOSC/4
Internal
Clock
Enable
0
(1)
T1OSI
Oscillator
2
Peripheral Clocks
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39599C-page 122
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
12.2 Timer1 Oscillator
12.3 Timer1 Oscillator Layout
Considerations
A crystal oscillator circuit is built-in between pins,
T1OSI (input) and T1OSO (amplifier output). It is
enabled by setting control bit, T1OSCEN (T1CON<3>).
The oscillator is a low-power oscillator rated for 32 kHz
crystals. It will continue to run during all power man-
aged modes. The circuit for a typical LP oscillator is
shown in Figure 12-3. Table 12-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator circuit draws very little power
during operation. Due to the low power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in output compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 12-3:
EXTERNAL COMPONENTS
FOR THE TIMER1 LP
OSCILLATOR
C1
33 pF
PIC18FXXXX
T1OSI
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED GUARD
RING
XTAL
32.768 kHz
VDD
VSS
T1OSO
C2
33 pF
OSC1
OSC2
Note:
See the Notes with Table 12-1 for additional
information about capacitor selection.
RC0
RC1
TABLE 12-1: CAPACITOR SELECTION FOR
THETIMEROSCILLATOR(2,3,4)
Osc Type
Freq
C1
C2
27 pF(1)
27 pF(1)
RC2
LP
32 kHz
Note: Not drawn to scale.
Note 1: Microchip suggests this value as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Capacitor values are for design guidance
only.
2003 Microchip Technology Inc.
DS39599C-page 123
PIC18F2220/2320/4220/4320
A write to the high byte of Timer1 must also take place
12.4 Timer1 Interrupt
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing Timer1 interrupt enable bit, TMR1IE
(PIE1<0>).
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 High Byte Buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
12.5 Resetting Timer1 Using a CCP
Trigger Output
12.7 Using Timer1 as a Real-Time
Clock
If the CCP module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion if the A/D module is enabled (see
Section 15.4.4 “Special Event Trigger” for more
information).
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.2 “Timer1 Oscillator”
above), gives users the option to include RTC function-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1 reg-
ister pair to overflow, triggers the interrupt and calls the
routine, which increments the seconds counter by one;
additional counters for minutes and hours are
incremented as the previous counter overflow.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSbit of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
12.6 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is valid
due to a rollover between reads.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the rou-
tine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
DS39599C-page 124
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
0x80
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1OSC
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
TMR1H,7
PIR1,TMR1IF
secs,F
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
.59
; 60 seconds elapsed?
CPFSGT secs
RETURN
; No, done
CLRF
INCF
MOVLW
secs
mins,F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
CPFSGT mins
RETURN
; No, done
CLRF
INCF
MOVLW
mins
hours,F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
CPFSGT hours
RETURN
; No, done
MOVLW
MOVWF
RETURN
.01
hours
; Reset hours to 1
; Done
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
(1)
(1)
PIE1
TXIE
TXIP
IPR1
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 125
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 126
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
13.1 Timer2 Operation
13.0 TIMER2 MODULE
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)).
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
• SSP module optional use of TMR2 output to
generate clock shift
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 has a control register shown in Register 13-1.
TMR2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 Control regis-
ter. The prescaler and postscaler selection of Timer2
are controlled by this register.
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 postscale
0001= 1:2 postscale
•
•
•
1111= 1:16 postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 127
PIC18F2220/2320/4220/4320
13.2 Timer2 Interrupt
13.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate the shift clock.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
bit TMR2IF
(1)
Output
Prescaler
Reset
EQ
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
1:1 to 1:16
2
Comparator
PR2
T2CKPS1:T2CKPS0
4
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF
CCP1IE TMR2IE
CCP1IP TMR2IP
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
0000 0000 0000 0000
(1)
(1)
PIE1
TXIE
TXIP
IPR1
TMR2
T2CON
PR2
Timer2 Module Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
IDLEN IRCF2
1111 1111 1111 1111
0000 qq00 0000 qq00
OSCCON
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
DS39599C-page 128
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Figure 14-1 is a simplified block diagram of the Timer3
module.
14.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
• 16-bit timer/counter (two 8-bit registers: TMR3H
and TMR3L)
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN) which can be a clock source for
Timer3.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x= Timer3 is the clock source for compare/capture CCP modules
01= Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00= Timer1 is the clock source for compare/capture CCP modules
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 prescale value
10= 1:4 prescale value
01= 1:2 prescale value
00= 1:1 prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first
falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 129
PIC18F2220/2320/4220/4320
When TMR3CS = 0, Timer3 increments every instruc-
14.1 Timer3 Operation
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator if enabled.
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC1:TRISC0 value
is ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
CCP Special Event Trigger
T3CCPx
TMR3IF
Overflow
Interrupt
Synchronized
Clock Input
0
Flag bit
CLR
TMR3L
TMR3H
T1OSC
1
TMR3ON
On/Off
T3SYNC
T1OSO/
T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
T1OSI
Oscillator
2
Peripheral Clocks
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Event Trigger
T3CCPx
Synchronized
Clock Input
8
TMR3
Set TMR3IF Flag bit
on Overflow
0
CLR
Timer3
High Byte
TMR3L
1
To Timer1 Clock Input
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
Peripheral Clocks
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39599C-page 130
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
14.2 Timer1 Oscillator
14.4 Resetting Timer3 Using a CCP
Trigger Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low-
power oscillator rated for 32 kHz crystals. See
Section 12.2 “Timer1 Oscillator” for further details.
If the CCP module is configured in Compare mode
to generate “special event trigger”
a
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3. See Section 15.4.4 “Special Event Trigger”
for more information.
14.3 Timer3 Interrupt
Note:
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
OSCIF
OSCIE
OSCIP
CMIF
CMIE
CMIP
—
—
—
EEIF
EEIE
EEIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
TMR3IE
TMR3IP
CCP2IF 00-0 0000 00-0 0000
CCP2IE 00-0 0000 00-0 0000
CCP2IP 11-1 1111 11-1 1111
xxxx xxxx uuuu uuuu
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
RD16
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
2003 Microchip Technology Inc.
DS39599C-page 131
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 132
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Note:
In 28-pin devices, both CCP1 and CCP2
function as standard CCP modules. In
40-pin devices, CCP1 is implemented as
an Enhanced CCP module, offering addi-
tional capabilities in PWM mode. Capture
and Compare modes are identical in all
modules regardless of the device.
The standard CCP (Capture/Compare/PWM) module
contains a 16-bit register that can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register. Table 15-1 shows
the timer resources required for each of the CCP
module modes.
Please see Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Mod-
ule” for a discussion of the enhanced
PWM capabilities of the CCP1 module.
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module is described with respect to
CCP1 except where noted. Table 15-2 shows the
interaction of the CCP modules.
REGISTER 15-1: CCPxCON: CCP MODULE CONTROL REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6 Reserved: Read as ‘0’.
See Section 16.0 “Enhanced Capture/Compare/PWM (ECCP) Module”.
bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, initialize CCP pin Low; on compare match, force CCP pin High
(CCPxIF bit is set)
1001= Compare mode, initialize CCP pin High; on compare match, force CCP pin Low
(CCPxIF bit is set)
1010= Compare mode, generate software interrupt on compare match (CCPxIF bit is set, CCP
pin operates as a port pin for input and output)
1011= Compare mode, trigger special event (CCP2IF bit is set)
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 133
PIC18F2220/2320/4220/4320
15.1 CCP1 Module
15.2 CCP2 Module
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Capture/Compare/PWM Register 2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
CCP2 functions identically to CCP1 except for the
enhanced PWM modes offered by CCP2
TABLE 15-1: CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TABLE 15-2: INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Capture
TMR1 or TMR3 time base. Time base can be different for each CCP.
Compare The compare could be configured for the special event trigger which clears either TMR1
or TMR3 depending upon which time base is used.
Compare
Compare The compare(s) could be configured for the special event trigger which clears TMR1 or
TMR3 depending upon which time base is used.
PWM
PWM
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
None.
Capture
Compare None.
DS39599C-page 134
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
15.3.3
SOFTWARE INTERRUPT
15.3 Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RC2/CCP1/P1A. An event is defined as
one of the following:
• every falling edge
• every rising edge
15.3.4
CCP PRESCALER
• every 4th rising edge
• every 16th rising edge
There are four prescaler settings specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the recom-
mended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
15.3.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1/P1A pin should be
configured as an input by setting the TRISC<2> bit.
Note:
If the RC2/CCP1/P1A is configured as an
output, a write to the port can cause a
capture condition.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
CCP1CON, F
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
MOVLW
NEW_CAPT_PS
CCP1CON
15.3.2
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with each CCP module is
selected in the T3CON register.
MOVWF
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
CCPR1L
TMR1L
Set Flag bit CCP1IF
T3CCP2
TMR3
Enable
Prescaler
÷ 1, 4, 16
CCP1 pin
CCPR1H
TMR1
and
Edge Detect
T3CCP2
Enable
TMR1H
CCP1CON<3:0>
Q’s
Set Flag bit CCP2IF
T3CCP1
TMR3H
TMR3L
CCPR2L
TMR1L
T3CCP2
TMR3
Enable
Prescaler
÷ 1, 4, 16
CCP2 pin
CCPR2H
TMR1
and
Edge Detect
Enable
T3CCP2
T3CCP1
TMR1H
CCP2CON<3:0>
Q’s
2003 Microchip Technology Inc.
DS39599C-page 135
PIC18F2220/2320/4220/4320
15.4.2
TIMER1/TIMER3 MODE SELECTION
15.4 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the
TMR1 register pair value, or the TMR3 register pair
value. When a match occurs, the RC2/CCP1/P1A
(RC1/T1OSI/CCP2) pin:
15.4.3
SOFTWARE INTERRUPT MODE
• Is driven High
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
• Is driven Low
• Toggles output (High to Low or Low to High)
• Remains unchanged (interrupt only)
15.4.4
SPECIAL EVENT TRIGGER
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit, CCP1IF (CCP2IF), is set.
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
15.4.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
The special trigger output of CCP2 resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
special event trigger will start an A/D conversion if the
A/D module is enabled.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1/P1A compare output latch
to the default low level. This is not the
PORTC I/O data latch.
Note:
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3 but not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
Match
RC2/CCP1/P1A
pin
TRISC<2>
Output Enable
1
0
CCP1CON<3:0>
Mode Select
T3CCP2
TMR1H TMR1L
TMR3H TMR3L
Special Event Trigger
Set Flag bit CCP2IF
T3CCP1
T3CCP2
0
1
Q
S
R
Output
Logic
Comparator
Match
RC1/T1OSI/CCP2
pin
TRISC<1>
Output Enable
CCPR2H CCPR2L
CCP2CON<3:0>
Mode Select
DS39599C-page 136
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
(1)
PIE1
TXIE
TXIP
IPR1
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 (MSB)
CCP1CON
CCPR2L
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 2 (LSB)
CCPR2H Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
PIR2
—
—
DC2B1
—
DC2B0
EEIF
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
OSCFIF
OSCFIE
OSCFIP
CMIF
CMIE
CMIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF 00-0 0000 00-0 0000
TMR3IE CCP2IE 00-0 0000 00-0 0000
TMR3IP CCP2IP 11-1 1111 11-1 1111
PIE2
—
EEIE
EEIP
IPR2
—
TMR3L
TMR3H
T3CON
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: These bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 137
PIC18F2220/2320/4220/4320
15.5.1
PWM PERIOD
15.5 PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
EQUATION 15-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
• TMR2 is cleared
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.5.3
“Setup for PWM Operation”.
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
15.5.2
PWM DUTY CYCLE
CCPR1H (Slave)
Comparator
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation.
Q
R
S
RC2/CCP1/P1A
(Note 1)
TMR2
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
EQUATION 15-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Note: 8-bit timer is concatenated with 2-bit internal Q clock or
2 bits of the prescaler to create 10-bit time base.
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
A PWM output (Figure 15-4) has a time base (period)
and a time that the output is high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-4:
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS39599C-page 138
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
15.5.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and the CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
EQUATION 15-3:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
FOSC
FPWM
log
5. Configure the CCP1 module for PWM operation.
bits
PWM Resolution (max) =
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
(1)
PIE1
TXIE
TXIP
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 Module Register
0000 0000 0000 0000
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
CCPR1L
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 (MSB)
CCP1CON
CCPR2L
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 2 (LSB)
CCPR2H Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
OSCCON
—
—
DC2B1
IRCF1
DC2B0
IRCF0
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
IDLEN
IRCF2
OSTS
IOFS
SCS1
SCS0
0000 qq00 0000 qq00
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 139
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 140
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The ECCP module differs from the CCP with the addi-
tion of an enhanced PWM mode which allows for 2 or
4 output channels, user-selectable polarity, dead band
control and automatic shutdown and restart. These
features are discussed in detail in Section 16.4
16.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
Note:
The ECCP (Enhanced Capture/ Compare/
“Enhanced PWM Mode”.
PWM) module is only available on
PIC18F4X20 devices.
The control register for CCP1 is shown in Register 16-1.
It differs from the CCP1CON register of PIC18F2X20
devices in that the two Most Significant bits are
implemented to control enhanced PWM functionality.
In 40 and 44-pin devices, the CCP1 module is
implemented as standard CCP module with
a
enhanced PWM capabilities. Operation of the Capture,
Compare and standard single output PWM modes is
described in Section 15.0 “Capture/Compare/PWM
(CCP) Modules”. Discussion in that section relating to
PWM frequency and duty cycle also apply to the
enhanced PWM mode.
REGISTER 16-1: CCP1CON REGISTER FOR ENHANCED CCP OPERATION (PIC18F4X20 ONLY)
R/W-0
P1M1
R/W-0
P1M0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7
bit 7-6
P1M1:P1M0: PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10(Capture, Compare, or disabled):
xx=P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11(PWM modes):
00=Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01=Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output; P1A, P1B modulated with dead band control; P1C, P1D assigned as port pins
11=Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DC1B1:DC1B0: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: ECCP1 Mode Select bits
0000= Capture/Compare/PWM off (resets ECCP module)
0001= Unused (reserved)
0010= Compare mode, toggle output on match (ECCP1IF bit is set)
0011= Unused (reserved)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (ECCP1IF bit is set)
1001= Compare mode, clear output on match (ECCP1IF bit is set)
1010= Compare mode, generate software interrupt on match (ECCP1IF bit is set, ECCP1 pin
operates as a port pin for input and output)
1011= Compare mode, trigger special event (ECCP1IF bit is set, ECCP resets TMR1or TMR2
and starts an A/D conversion if the A/D module is enabled)
1100= PWM mode, P1A, P1C active-high, P1B, P1D active-high
1101= PWM mode, P1A, P1C active-high, P1B, P1D active-low
1110= PWM mode, P1A, P1C active-low, P1B, P1D active-high
1111= PWM mode, P1A, P1C active-low, P1B, P1D active-low
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 141
PIC18F2220/2320/4220/4320
In addition to the expanded functions of the CCP1CON
16.2 Capture and Compare Modes
register, the ECCP module has two additional registers
associated with enhanced PWM operation and
Auto-Shutdown features:
The Capture and Compare modes of the ECCP module
are identical in operation to that of CCP1, as discussed
in Section 15.3 “Capture Mode” and Section 15.4
“Compare Mode”. No changes are required when
moving between these modules on PIC18F2X20 and
PIC18F4X20 devices.
• PWM1CON
• ECCPAS
All other registers associated with the ECCP module
are identical to those used for the CCP1 module in
PIC18F2X20 devices, including register and individual
bit names. Likewise, the timer assignments and inter-
actions between the two CCP modules are identical,
regardless of whether CCP1 is a standard or enhanced
module.
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 15.4
“Compare Mode”.
Note:
When setting up single output PWM opera-
tions, users are free to use either of the pro-
cesses described in Section 15.5.3 “Setup
for PWM Operation” or Section 16.4.7
“Setup for PWM Operation”. The latter is
more generic but will work for either single
or multi output PWM.
16.1 ECCP Outputs
The Enhanced CCP module may have up to four outputs
depending on the selected operating mode. These out-
puts, designated P1A through P1D, are multiplexed with
I/O pins on PORTC and PORTD. The pin assignments
are summarized in Table 16-1.
To configure I/O pins as PWM outputs, the proper PWM
mode must be selected by setting the P1Mn and
CCP1Mn bits (CCP1CON<7:6> and <3:0>, respec-
tively). The appropriate TRISC and TRISD direction
bits for the port pins must also be set as outputs.
TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
CCP1CON
ECCP Mode
RC2
RD5
RD6
RD7
Configuration
Compatible CCP
00xx11xx
10xx11xx
x1xx11xx
CCP1
P1A
RD5/PSP5
P1B
RD6/PSP6
RD6/PSP6
P1C
RD7/PSP7
RD6/PSP6
P1D
Dual PWM
Quad PWM
P1A
P1B
Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1: TRIS register values must be configured appropriately.
2: With ECCP in Dual or Quad PWM mode, the PSP input/output control of PORTD is overridden by P1B,
P1C and P1D.
DS39599C-page 142
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
waveforms do not exactly match the standard PWM
waveforms but are instead offset by one full instruction
cycle (4 TOSC).
16.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is an upwardly compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the P1M1:P1M0 and
CCP1M3:CCP1M0 bits of the CCP1CON register
(CCP1CON<7:6> and CCP1CON<3:0>, respectively).
As before, the user must manually configure the
appropriate TRISD bits for output.
16.4.1
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• Single Output
• Half-Bridge Output
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to pre-
vent glitches on any of the outputs. The exception is the
PWM Delay register, ECCP1DEL, which is loaded at
either the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets instead of
starting immediately. This means that enhanced PWM
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the Standard PWM mode
discussed in Section 15.5 “PWM Mode”. The Half-
Bridge and Full-Bridge Output modes are covered in
detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
FIGURE 16-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
P1M1<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
CCPR1L
CCP1/P1A
RC2/CCP1/P1A
TRISD<4>
TRISD<5>
TRISD<6>
TRISD<7>
CCPR1H (Slave)
Comparator
P1B
RD5/PSP5/P1B
RD6/PSP6/P1C
Output
Controller
R
S
Q
P1C
(Note 1)
TMR2
P1D
RD7/PSP7/P1D
Comparator
PR2
Clear Timer,
set CCP1 pin and
latch D.C.
PWM1CON
Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base.
2003 Microchip Technology Inc.
DS39599C-page 143
PIC18F2220/2320/4220/4320
FIGURE 16-2:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
(Single Output)
00
10
(1)
(1)
Delay
Delay
P1A Modulated
P1B Modulated
(Half-Bridge)
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
FIGURE 16-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
(1)
(1)
Delay
Delay
(Half-Bridge)
P1B Inactive
(Full-Bridge,
Forward)
01
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead band delay is programmed using the PWM1CON register (see Section 16.4.4 “Programmable Dead Band Delay”).
DS39599C-page 144
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
16.4.2
HALF-BRIDGE MODE
FIGURE 16-4:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the RC2/CCP1/P1A pin, while the com-
plementary PWM output signal is output on the RD5/
PSP5/P1B pin (Figure 16-4). This mode can be used
for half-bridge applications, as shown in Figure 16-5, or
for full-bridge applications where four power switches
are being modulated with two PWM signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
td
td
P1B
In Half-Bridge Output mode, the programmable dead
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.4
“Programmable Dead Band Delay” for more details
of the dead band delay operations.
(1)
(1)
(1)
td = Dead Band Delay
Note 1: At this time, the TMR2 register is equal to the PR2
register.
2: Output signals are shown as active-high.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F4220/4320
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F4220/4320
FET
Driver
FET
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
2003 Microchip Technology Inc.
DS39599C-page 145
PIC18F2220/2320/4220/4320
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2> and PORTD<5:7> data latches. The
TRISC<2> and TRISD<5:7> bits must be cleared to
make the P1A, P1B, P1C and P1D pins output.
16.4.3
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as out-
puts; however, only two outputs are active at a time. In
the Forward mode, pin RC2/CCP1/P1A is continuously
active and pin RD7/PSP7/P1D is modulated. In the
Reverse mode, RD6/PSP6/P1C pin is continuously
active and RD5/PSP5/P1B pin is modulated. These are
illustrated in Figure 16-6.
FIGURE 16-6:
FULL-BRIDGE PWM OUTPUT
FORWARD MODE
Period
(2)
P1A
Duty Cycle
(2)
(2)
P1B
P1C
(2)
P1D
(1)
(1)
REVERSE MODE
Period
Duty Cycle
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
DS39599C-page 146
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 16-7:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F4220/4320
QC
QA
FET
Driver
FET
Driver
P1A
Load
P1B
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
Figure 16-9 shows an example where the PWM direc-
tion changes from forward to reverse at a near 100%
duty cycle. At time t1, the outputs P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices QC and QD
(see Figure 16-7) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
16.4.3.1
Direction Change in Full-Bridge
Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows users to control the forward/
reverse direction. When the application firmware
changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the mod-
ulated outputs (P1B and P1D) are placed in their inactive
state, while the unmodulated outputs (P1A and P1C) are
switched to drive in the opposite direction. This occurs in
a time interval of 4 TOSC * (Timer2 Prescale Value)
before the next PWM period begins. The Timer2
prescaler will be either 1, 4 or 16, depending on the
value of the T2CKPS bit (T2CON<1:0>). During the
interval from the switch of the unmodulated outputs to
the beginning of the next period, the modulated outputs
(P1B and P1D) remain inactive. This relationship is
shown in Figure 16-8.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for
changing directions.
a PWM period before
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any dead band delay. In gen-
eral, since only one output is modulated at all times,
dead band delay is not required. However, there is a
situation where a dead band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
2003 Microchip Technology Inc.
DS39599C-page 147
PIC18F2220/2320/4220/4320
FIGURE 16-8:
PWM DIRECTION CHANGE
(1)
Period
Period
SIGNAL
P1A (Active High)
P1B (Active High)
DC
P1C (Active High)
P1D (Active High)
(Note 2)
DC
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of
4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are
inactive at this time.
FIGURE 16-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE(1)
Forward Period
Reverse Period
t1
P1A
P1B
DC
P1C
P1D
DC
(2)
t
on
External Switch C
External Switch D
(3)
t
off
(2,3)
Potential
Shoot-Through
Current
t = t – t
off
on
Note 1: All signals are shown as active-high.
2: t is the turn-on delay of power switch QC and its driver.
on
3: t is the turn-off delay of power switch QD and its driver.
off
DS39599C-page 148
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
A shutdown event can be caused by either of the two
comparator modules or the INT0 pin (or any combina-
tion of these three sources). The comparators may be
used to monitor a voltage input proportional to a current
being monitored in the bridge circuit. If the voltage
exceeds a threshold, the comparator switches state
and triggers a shutdown. Alternatively, a digital signal
on the INT0 pin can also trigger a shutdown. The auto-
shutdown feature can be disabled by not selecting any
auto-shutdown sources. The auto-shutdown sources to
be used are selected using the ECCPAS2:ECCPAS0
bits (ECCPAS<6:4>).
16.4.4
PROGRAMMABLE DEAD BAND
DELAY
In half-bridge applications, where all power switches
are modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shoot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
When a shutdown occurs, the output pins are asyn-
chronously placed in their shutdown states, specified
by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits
(ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/
P1D) may be set to drive high, drive low or be tri-stated
(not driving). The ECCPASE bit (ECCPAS<7>) is also
set to hold the enhanced PWM outputs in their
shutdown states.
In the Half-Bridge Output mode, a digitally program-
mable dead band delay is available to avoid shoot-
through current from destroying the bridge power
switches. The delay occurs at the signal transition from
the non-active state to the active state. See Figure 16-4
for illustration. The lower seven bits of the PWM1CON
register (Register 16-2) set the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
16.4.5
ENHANCED PWM
AUTO-SHUTDOWN
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
When the ECCP is programmed for any of the
enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
REGISTER 16-2: PWM1CON: PWM CONFIGURATION REGISTER
R/W-0
R/W-0
PDC6
R/W-0
PDC5
R/W-0
PDC4
R/W-0
PDC3
R/W-0
PDC2
R/W-0
PDC1
R/W-0
PDC0
PRSEN
bit 7
bit 0
bit 7
PRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
goes away; the PWM restarts automatically
0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0
PDC<6:0>: PWM Delay Count bits
Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should
transition active and the actual time it transitions active.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 149
PIC18F2220/2320/4220/4320
REGISTER 16-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
bit 7
bit 0
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
0= ECCP outputs are operating
1= A shutdown event has occurred; ECCP outputs are in shutdown state
bit 6-4
ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits
000= Auto-shutdown is disabled
001= Comparator 1 output
010= Comparator 2 output
011= Either Comparator 1 or 2
100= INT0
101= INT0 or Comparator 1
110= INT0 or Comparator 2
111= INT0 or Comparator 1 or Comparator 2
bit 3-2
bit 1-0
PSSAC<1:0>: Pin A and C Shutdown State Control bits
00= Drive Pins A and C to ‘0’
01= Drive Pins A and C to ‘1’
1x= Pins A and C tri-state
PSSBD<1:0>: Pin B and D Shutdown State Control bits
00= Drive Pins B and D to ‘0’
01= Drive Pins B and D to ‘1’
1x= Pins B and D tri-state
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 150
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
16.4.5.1
Auto-Shutdown and Automatic
Restart
16.4.6
START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller is released from Reset, all of
the I/O pins are in the high-impedance state. The exter-
nal circuits must keep the power switch devices in the
off state until the microcontroller drives the I/O pins with
the proper signal levels or activates the PWM output(s).
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
PWM1CON register (PWM1CON<7>).
In Shutdown mode with PRSEN = 1(Figure 16-10), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown condi-
tion clears, the ECCPASE bit is cleared. If PRSEN = 0
(Figure 16-11), once a shutdown condition occurs, the
ECCPASE bit will remain set until it is cleared by firm-
ware. Once ECCPASE is cleared, the enhanced PWM
will resume at the beginning of the next PWM period.
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output polar-
ities must be selected before the PWM pins are config-
ured as outputs. Changing the polarity configuration
while the PWM pins are configured as outputs is not
recommended since it may result in damage to the
application circuits.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Independent of the PRSEN bit setting, if the auto-
shutdown source is one of the comparators, the shut-
down condition is a level. The ECCPASE bit cannot be
cleared as long as the cause of the shutdown persists.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the application
circuit. The ECCP module must be enabled in the proper
output mode and complete a full PWM cycle before con-
figuring the PWM pins as outputs. The completion of a
full PWM cycle is indicated by the TMR2IF bit being set
as the second PWM period begins.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
FIGURE 16-10:
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period
PWM Period
PWM Period
PWM Activity
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Shutdown Event
ECCPASE bit
FIGURE 16-11:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period
PWM Period
PWM Period
PWM Activity
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Shutdown Event
ECCPASE bit
ECCPASE
Cleared by Firmware
2003 Microchip Technology Inc.
DS39599C-page 151
PIC18F2220/2320/4220/4320
16.4.7
SETUP FOR PWM OPERATION
16.4.8
OPERATION IN POWER MANAGED
MODES
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from INTOSC
and the postscaler may not be stable immediately.
1. Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISC and TRISD bits.
2. Set the PWM period by loading the PR2 register.
3. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change.
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
In all other power managed modes, the selected power
managed mode clock will clock Timer2. Other power
managed mode clocks will most likely be different than
the primary clock frequency.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
4. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
16.4.8.1
OPERATION WITH FAIL-SAFE
CLOCK MONITOR
5. For Half-Bridge Output mode, set the dead band
delay by loading PWM1CON<6:0> with the
appropriate value.
If the Fail-Safe Clock Monitor is enabled
(CONFIG1H<6> is programmed), a clock failure will
force the device into the RC_RUN Power Managed
mode and the OSCFIF bit (PIR2<7>) will be set. The
ECCP will then be clocked from the internal oscillator
clock source which may have a different clock
frequency than the primary clock. By loading the
IRCF2:IRCF0 bits on Resets, the user can obtain a
frequency higher than the default INTRC clock source
in the event of a clock failure.
6. If auto-shutdown operation is required, load the
ECCPAS register:
• Select the auto-shutdown sources using the
ECCPAS<2:0> bits.
• Select the shutdown states of the PWM
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCPAS<7>).
See the previous section for additional details.
• Configure the comparators using the CMCON
register.
16.4.9
EFFECTS OF A RESET
• Configure the comparator inputs as analog
inputs.
Both Power-on and subsequent Resets will force all
ports to Input mode and the CCP registers to their
Reset states.
7. If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
8. Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
9. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRISC
and TRISD bits.
• Clear the ECCPASE bit (ECCPAS<7>).
DS39599C-page 152
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 16-2: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 000x 0000 000u
0--1 11qq 0--q qquu
IPEN
PSPIF
PSPIE
PSPIP
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
0000 0000 0000 0000
PIE1
IPR1
TMR2
Timer2 Module Register
Timer2 Module Period Register
PR2
1111 1111 1111 1111
T2CON
TRISC
TRISD
CCPR1H
CCPR1L
CCP1CON
ECCPAS
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PORTC Data Direction Register
1111 1111 1111 1111
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PORTD Data Direction Register
Enhanced Capture/Compare/PWM Register 1 High Byte
Enhanced Capture/Compare/PWM Register 1 Low Byte
P1M1
P1M0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
PWM1CON PRSEN
PDC6
IRCF2
PDC5
IRCF1
PDC4
IRCF0
PDC3
OSTS
PDC2
IOFS
PDC1
SCS1
PDC0 0000 0000 0000 0000
SCS0 0000 q000 0000 q000
OSCCON
IDLEN
Legend:
x= unknown, u= unchanged, -= unimplemented, read as ‘0’.
Shaded cells are not used by the ECCP module in enhanced PWM mode.
2003 Microchip Technology Inc.
DS39599C-page 153
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 154
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.3 SPI Mode
17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
17.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/LVDIN/C2OUT
Register 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
Read
Write
• Master mode
• Multi-Master mode
• Slave mode
SSPBUF reg
SSPSR reg
17.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
RC4/SDI/SDA
RC5/SDO
Shift
Clock
bit 0
Control
Enable
SS
Additional details are provided under the individual
sections.
RA5/AN4/SS/
LVDIN/C2OUT
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
(
)
2
Edge
Select
TOSC
Prescaler
4, 16, 64
RC3/SCK/
SCL
Data to TX/RX in SSPSR
TRIS bit
2003 Microchip Technology Inc.
DS39599C-page 155
PIC18F2220/2320/4220/4320
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
17.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Edge Select bit
When CKP = 0:
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
When CKP = 1:
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D/A: Data/Address bit
Used in I2C mode only.
P: Stop bit
Used in I2C mode only.
S: Start bit
Used in I2C mode only.
R/W: Read/Write bit information
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 156
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be
cleared in software).
0= No overflow
Note:
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When the MSSP is enabled in SPI mode, these pins must be properly configured
as input or output.
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 157
PIC18F2220/2320/4220/4320
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision Detect bit,
WCOL (SSPCON1<7>), will be set. User software
must clear the WCOL bit so that it can be determined if
the following write(s) to the SSPBUF register
completed successfully.
17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
Full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a Transmit/Receive Shift regis-
ter (SSPSR) and a Buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPBUF register. Then the Buffer Full Detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 17-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP
BTFSS
BRA
SSPSTAT, BF
LOOP
;Has data been received(transmit complete)?
;No
MOVF
SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS39599C-page 158
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.3.3
ENABLING SPI I/O
17.3.4
TYPICAL CONNECTION
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
Register 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDI must have TRISC<4> bit set
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISC<5> bit set
• Master sends dummy data – Slave sends data
Any serial port function that is not desired may be over-
ridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
2003 Microchip Technology Inc.
DS39599C-page 159
PIC18F2220/2320/4220/4320
Figure 17-3, Figure 17-5 and Figure 17-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
17.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• (Timer2 output)/2
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The maximum data rate is approximately 3.0 Mbps,
limited by timing requirements (see Table 26-14
through Table 26-17).
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication as shown in
FIGURE 17-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
DS39599C-page 160
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
is tri-stated, even if in the middle of a transmitted byte.
External pull-up/pull-down resistors may be desirable,
depending on the application.
17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> = 0100),
the SPI module will reset when the SS pin is
set high.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in power managed modes, the slave can trans-
mit/receive data. When a byte is received, the device
will wake-up from power managed modes.
When the SPI module resets, SSPSR is cleared. This
can be done by either driving the SS pin to a high level
or clearing the SSPEN bit.
17.3.7
SLAVE SELECT CONTROL
The SS pin allows a master controller to select one of
several slave controllers for communications in sys-
tems with more than one slave. The SPI must be in
Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The SS pin is configured for
input by setting TRISA<5>. When the SS pin is low,
transmission and reception are enabled and the SDO
pin is driven. When the SS pin goes high, the SDO pin
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 17-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 7
bit 7
bit 0
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
2003 Microchip Technology Inc.
DS39599C-page 161
PIC18F2220/2320/4220/4320
FIGURE 17-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 3
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 17-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 3
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
DS39599C-page 162
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.3.8
MASTER IN POWER MANAGED
MODES
17.3.8.1
Slave in Power Managed Modes
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in any power managed mode and
data to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if MSSP interrupts are
enabled, will wake the device from a power managed
mode.
In Master mode, module clocks may be operating at a
different speed than when in full power mode, or in the
case of the Sleep Power Managed mode, all clocks are
halted.
In most power managed modes, a clock is provided to
the peripherals and is derived from the primary clock
source, the secondary clock (Timer1 oscillator at 32.768
kHz) or the internal oscillator block (one of eight frequen-
cies between 31 kHz and 8 MHz). See Section 2.7
“Clock Sources and Oscillator Switching” for
additional information.
17.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
If MSSP interrupts are enabled, they can wake the con-
troller from a power managed mode when the master
completes sending data. If an exit from a power
managed mode is not desired, MSSP interrupts should
be disabled.
TABLE 17-1: SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will pause until
the device wakes from the power managed mode. After
the device returns to full power mode, the module will
resume transmitting and receiving data.
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
There is also an SMP bit which controls when the data
is sampled.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
PIE1
PSPIE
(1)
IPR1
PSPIP
TRISC
SSPBUF
SSPCON1
TRISA
SSPSTAT
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
PORTA Data Direction Register
D/A
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0 0000 0000 0000 0000
(1)
(1)
TRISA7
SMP
TRISA6
CKE
--11 1111 --11 1111
P
S
R/W
UA
BF
0000 0000 0000 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 163
PIC18F2220/2320/4220/4320
2
17.4.1
REGISTERS
17.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on Start and Stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
Two pins are used for data transfer:
• Serial Clock (SCL) – RC3/SCK/SCL
• Serial Data (SDA) – RC4/SDI/SDA
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
The user must configure these pins as inputs using the
TRISC<4:3> bits.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
Internal
Data Bus
Read
Write
SSPADD register holds the slave device address
when the SSP is configured in I2C Slave mode. When
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate
Generator reload value.
SSPBUF reg
Shift
Clock
RC3/SCK/
SCL
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPSR reg
RC4/SDI/
SDA
MSb
LSb
Addr Match
Match Detect
SSPADD reg
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit Detect
DS39599C-page 164
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
bit 5
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled
0 = Slew rate control enabled
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Note:
This bit is cleared on Reset when SSPEN is cleared or a Start bit has been detected.
S: Start bit
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
Note:
This bit is cleared on Reset when SSPEN is cleared or a Stop bit has been detected.
R/W: Read/Write bit Information (I2C mode only)
In Slave mode:
1= Read
0= Write
Note:
This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
Note:
OR’ing this bit with the SSPCON2 bits, SEN, RSEN, PEN, RCEN or ACKEN will
indicate if the MSSP is in Idle mode.
bit 1
bit 0
UA: Update Address (10-bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
In Receive mode:
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 165
PIC18F2220/2320/4220/4320
REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for
a transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPBUF register is still holding the previous byte (must be
cleared in software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDA and SCL pins must be configured as input pins.
CKP: SCK Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (Slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Note:
Bit combinations not specifically listed here are either reserved, or implemented in
SPI mode only.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 166
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1= Not Acknowledge
0= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
RCEN: Receive Enable bit (Master mode only)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (Master mode only)
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
bit 1
bit 0
RSEN: Repeated Start Condition Enabled bit (Master mode only)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enabled/Stretch Enabled bit
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0= Clock stretching is disabled
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 167
PIC18F2220/2320/4220/4320
17.4.2
OPERATION
17.4.3.1
Addressing
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I2C oper-
ation. Four mode selection bits (SSPCON1<3:0>) allow
one of the following I2C modes to be selected:
• I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is com-
pared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
• I2C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode,
slave is Idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for
10-bit address is as follows, with steps 7 through 9 for
the slave-transmitter:
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits.
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
7. Receive Repeated Start condition.
• The overflow bit, SSPOV (SSPCON1<6>), was
set before the transfer was received.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
In this case, the SSPSR register value is not loaded
into the SSPBUF but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared by software.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
DS39599C-page 168
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.3.2
Reception
17.4.3.3
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit, CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPSTAT<0>), is
set or bit, SSPOV (SSPCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit,
CKP (SSPCON1<4>). See Section 17.4.4 “Clock
Stretching” for more detail.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
2003 Microchip Technology Inc.
DS39599C-page 169
PIC18F2220/2320/4220/4320
2
FIGURE 17-8:
I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
DS39599C-page 170
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
2
FIGURE 17-9:
I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
2003 Microchip Technology Inc.
DS39599C-page 171
PIC18F2220/2320/4220/4320
FIGURE 17-10:
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
DS39599C-page 172
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
2
FIGURE 17-11:
I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
2003 Microchip Technology Inc.
DS39599C-page 173
PIC18F2220/2320/4220/4320
17.4.4
CLOCK STRETCHING
17.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
17.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF bit
is set, the CKP bit in the SSPCON1 register is automat-
ically cleared, forcing the SCL output to be held low.
The CKP being cleared to ‘0’ will assert the SCL line
low. The CKP bit must be set in the user’s ISR before
reception is allowed to continue. By holding the SCL
line low, the user has time to service the ISR and read
the contents of the SSPBUF before the master device
can initiate another receive sequence. This will prevent
buffer overruns from occurring (see Figure 17-13).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
17.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 17-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
17.4.4.2
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but the CKP bit is not cleared. During this time, if the
UA bit is set after the ninth clock, clock stretching is
initiated. The UA bit is set after receiving the upper
byte of the 10-bit address and following the receive of
the second byte of the 10-bit address with the R/W bit
cleared to ‘0’. The release of the clock line occurs
upon updating SSPADD. Clock stretching will occur on
each data receive sequence as described in 7-bit
mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
DS39599C-page 174
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
17.4.4.5
Clock Synchronization and
the CKP bit (SEN = 1)
The SEN bit is also used to synchronize writes to the
CKP bit. If a user clears the CKP bit, the SCL output is
forced to ‘0’. When the SEN bit is set to ‘1’, setting the
CKP bit will not assert the SCL output low until the
SCL output is already sampled low. If the user
attempts to drive SCL low, the CKP bit will not assert
the SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
Note:
If the SEN bit is ‘0’, clearing the CKP bit
will result in immediately driving the SCL
output to ‘0’ regardless of the current
state.
FIGURE 17-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX-1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON1
2003 Microchip Technology Inc.
DS39599C-page 175
PIC18F2220/2320/4220/4320
2
FIGURE 17-13:
I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
DS39599C-page 176
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 17-14:
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
2003 Microchip Technology Inc.
DS39599C-page 177
PIC18F2220/2320/4220/4320
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
17.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit (GCEN) is enabled
(SSPCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPSR and the address is com-
pared against the SSPADD. It is also compared to the
general call address and fixed in hardware.
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to general call address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
General Call Address
ACK
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
‘0’
‘1’
DS39599C-page 178
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condi-
tion is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set or the
bus is Idle, with both the S and P bits clear.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start Condition
• Stop Condition
Once Master mode is enabled, the user has six
options.
• Data Transfer Byte Transmitted/Received
• Acknowledge Transmit
• Repeated Start
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
2
FIGURE 17-16:
MSSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
2003 Microchip Technology Inc.
DS39599C-page 179
PIC18F2220/2320/4220/4320
I2C Master Mode Operation
A typical transmit sequence would go as follows:
17.4.6.1
1. The user generates a Start condition by setting
the Start enable bit, SEN (SSPCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate” for more detail.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
DS39599C-page 180
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.7
BAUD RATE
17.4.7.1
Baud Rate Generation in Power
Managed Modes
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
When the device is operating in a power managed
mode, the clock source to the Baud Rate Generator
may change frequency or stop, depending on the
power managed mode and clock source selected.
In most power modes, the Baud Rate Generator
continues to be clocked but may be clocked from the
primary clock (selected in a configuration word), the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the internal oscillator block (one of eight frequencies
between 31 kHz and 8 MHz). If the Sleep mode is
selected, all clocks are stopped and the Baud Rate
Generator will not be clocked.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Reload
Control
BRG Down Counter
CLKO
FOSC/4
TABLE 17-3: I2C CLOCK RATE W/BRG
SSPADD VALUE
(See Register 17-4,
Mode 1000)
(2)
FSCL
FOSC
FCY
FCY*2
(2 Rollovers of BRG)
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Bh
27h
02h
09h
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
4 MHz
100kHz
1 MHz(1)
4 MHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2: Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low
time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”).
2003 Microchip Technology Inc.
DS39599C-page 181
PIC18F2220/2320/4220/4320
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-18).
17.4.7.2
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 17-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
DS39599C-page 182
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.8
I2C MASTER MODE START
CONDITION TIMING
17.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
To initiate a Start condition, the user sets the Start
Condition Enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<6:0>
and starts its count. If SCL and SDA are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the Start condition and
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Generator is reloaded with the con-
tents of SSPADD<6:0> and resumes its count. When
the Baud Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
Note:
If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
FIGURE 17-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
At completion of Start bit,
Write to SEN bit occurs here
SDA = 1,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG
TBRG
Write to SSPBUF occurs here
2nd bit
1st bit
SDA
TBRG
SCL
TBRG
S
2003 Microchip Technology Inc.
DS39599C-page 183
PIC18F2220/2320/4220/4320
I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
17.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Genera-
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
notbesetuntiltheBaudRateGeneratorhastimedout.
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 17-20:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
SDA = 1,
SCL = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPBUF occurs here
TBRG
Falling edge of ninth clock,
end of Xmit
SCL
TBRG
Sr = Repeated Start
DS39599C-page 184
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.10 I2C MASTER MODE
TRANSMISSION
17.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full Flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
#106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification
parameter #107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit, during the ninth bit time, if an
address match occurred or if data was received prop-
erly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared; if not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
17.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate
Generator is suspended from counting, holding SCL
low. The MSSP is now in Idle state, awaiting the next
command. When the buffer is read by the CPU, the BF
flag bit is automatically cleared. The user can then
send an Acknowledge bit at the end of reception by
setting the Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>).
17.4.11.1 BF Status Flag
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
17.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
2003 Microchip Technology Inc.
DS39599C-page 185
PIC18F2220/2320/4220/4320
2
FIGURE 17-21:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS39599C-page 186
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
2
FIGURE 17-22:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
2003 Microchip Technology Inc.
DS39599C-page 187
PIC18F2220/2320/4220/4320
17.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
ACKNOWLEDGE SEQUENCE TIMING
17.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A TBRG later, the PEN bit is cleared and the SSPIF
bit is set (Figure 17-24).
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG) and
the SCL pin is deasserted (pulled high). When the SCL
pin is sampled high (clock arbitration), the Baud Rate
Generator counts for TBRG. The SCL pin is then pulled
low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.13.1 WCOL Status Flag
17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2,
ACKEN automatically cleared
TBRG
ACKEN = 1, ACKDT = 0
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in software
Set SSPIF at the end
Set SSPIF at the end
of receive
Cleared in
software
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 17-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
DS39599C-page 188
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.14 POWER MANAGED MODE
OPERATION
17.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in any power managed mode, the I2C module
can receive addresses or data and when an address
match or complete byte transfer occurs, wake the
processor from Sleep (if the MSSP interrupt is
enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I2C port to its Idle state (Figure 17-25).
17.4.15 EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16 MULTI-MASTER MODE
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set or the
bus is idle with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the con-
dition is aborted, the SDA and SCL lines are deasserted,
and the respective control bits in the SSPCON2 register
are cleared. When the user services the bus collision
Interrupt Service Routine and if the I2C bus is free, the
user can resume communication by asserting a Start
condition.
In multi-master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• Data Transfer
• A Start Condition
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
• A Repeated Start Condition
• An Acknowledge Condition
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register or
the bus is Idle and the S and P bits are cleared.
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set Bus Collision
Interrupt Flag (BCLIF)
BCLIF
2003 Microchip Technology Inc.
DS39599C-page 189
PIC18F2220/2320/4220/4320
If the SDA pin is sampled low during this count, the
17.4.17.1 Bus Collision During a Start
Condition
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0 and during this time, if the SCL pins
are sampled as ‘0’, a bus collision does not occur. At
the end of the BRG count, the SCLpin is asserted low.
During a Start condition, a bus collision occurs if:
a) SDA or SCL is sampled low at the beginning of
the Start condition (Figure 17-26).
b) SCL is sampled low before SDA is asserted low
(Figure 17-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low or the SCL pin is already
low, then all of the following occur:
• The Start condition is aborted
• The BCLIF flag is set
•
The MSSP module is reset to its Idle state
(Figure 17-26)
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 17-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
DS39599C-page 190
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPIF
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF
‘0’
S
SSPIF
SDA = 0, SCL = 1,
set SSPIF
Interrupts cleared
in software
2003 Microchip Technology Inc.
DS39599C-page 191
PIC18F2220/2320/4220/4320
If SDA is low, a bus collision has occurred (i.e., another
17.4.17.2 Bus Collision During a Repeated
Start Condition
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high to low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(see Figure 17-30).
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 17-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 17-30:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
BCLIF
RSEN
set BCLIF. Release SDA and SCL.
Interrupt cleared
in software
‘0’
S
SSPIF
DS39599C-page 192
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is sam-
pled low before SDA is allowed to float high, a bus col-
lision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
17.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
2003 Microchip Technology Inc.
DS39599C-page 193
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 194
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
18.1 Asynchronous Operation in Power
Managed Modes
18.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART may operate in Asynchronous mode while
the peripheral clocks are being provided by the internal
oscillator block. This mode makes it possible to remove
the crystal or resonator that is commonly connected as
the primary clock on the OSC1 and OSC2 pins.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules available in the PIC18F2X20/4X20 family
of microcontrollers. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
The factory calibrates the internal oscillator block out-
put (INTOSC) for 8 MHz. However, this frequency may
drift as VDD or temperature changes and this directly
affects the asynchronous baud rate. Two methods may
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE regis-
ter to adjust the INTOSC output back to 8 MHz. Adjust-
ing the value in the OSCTUNE register allows for fine
resolution changes to the system clock source (see
Section 3.6 “INTOSC Frequency Drift” for more
information).
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The other method adjusts the value in the Baud Rate
Generator since there may be not be fine enough res-
olution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
The RC6/TX/CK and RC7/RX/DT pins must be config-
ured as shown for use with the Universal Synchronous
Asynchronous Receiver Transmitter:
• SPEN (RCSTA<7>) bit must be set (= 1)
• TRISC<7> bit must be set (= 1)
• TRISC<6> bit must be cleared (= 0)
Register 18-1 shows the Transmit Status and Control
register (TXSTA) and Register 18-2 shows the Receive
Status and Control register (RCSTA).
2003 Microchip Technology Inc.
DS39599C-page 195
PIC18F2220/2320/4220/4320
REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as ‘0’
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 196
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enable address detection, enable interrupt and load the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 197
PIC18F2220/2320/4220/4320
It may be advantageous to use the high baud rate
18.2 USART Baud Rate Generator (BRG)
(BRGH = 1), even for slower baud clocks, because the
FOSC/(16 (X + 1)) equation can reduce the baud rate
error in some cases.
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free-running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA<2>) also con-
trols the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different USART modes which only
apply in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
18.2.1
POWER MANAGED MODE
OPERATION
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
The system clock is used to generate the desired baud
rate; however, when a power managed mode is
entered, the clock source may be operating at a differ-
ent frequency than in PRI_RUN mode. In Sleep mode,
no clocks are present and in PRI_IDLE, the primary
clock source continues to provide clocks to the baud
rate generator; however, in other power managed
modes, the clock frequency will probably change. This
may require the value in SPBRG to be adjusted.
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
• FOSC = 16 MHz
• Desired Baud Rate = 9600
• BRGH = 0
• SYNC = 0
18.2.2
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 18-1:
CALCULATING BAUD RATE ERROR
Desired Baud Rate
= FOSC/(64 (X + 1))
Solving for X:
X
X
X
= ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
TABLE 18-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
Baud Rate = FOSC/(16 (X + 1))
N/A
0(Asynchronous)
1(Synchronous)
Baud Rate = FOSC/(64 (X + 1))
Baud Rate = FOSC/(4 (X + 1))
Legend: X = value in SPBRG (0 to 255)
TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA
RCSTA
SPBRG
CSRC
SPEN
TX9
RX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010
0000 -010
0000 -00x
0000 0000
SREN CREN ADDEN FERR OERR RX9D 0000 -00x
0000 0000
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
DS39599C-page 198
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0, LOW SPEED)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 16.000 MHz
FOSC = 10.000 MHz
BAUD
RATE Actual
Actual
Rate
(K)
Actual
Rate
(K)
Actual
Rate
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
%
Error
(K)
Rate
(K)
0.3
1.2
—
—
—
—
—
—
255
64
32
15
10
7
—
1.22
2.40
9.47
19.53
39.06
62.50
78.13
104.17
—
—
1.73
0.16
-1.36
1.73
1.73
8.51
1.73
8.51
—
—
255
129
32
15
7
0.98
1.20
2.40
9.62
19.23
35.71
62.50
83.33
—
225.52
0.16
0.16
0.16
0.16
-6.99
8.51
8.51
—
255
207
103
25
12
6
0.61
1.20
2.40
9.77
19.53
39.06
52.08
78.13
—
103.45
0.16
0.16
1.73
1.73
1.73
-9.58
1.73
—
255
129
64
15
7
2.4
2.44
1.73
0.16
-1.36
1.73
-1.36
1.73
-6.99
8.51
-16.67
4.17
0.00
9.6
9.62
19.2
38.4
57.6
76.8
96.0
115.2
18.94
39.06
56.82
78.13
89.29
125.00
3
4
3
2
3
2
1
6
2
—
1
—
1
4
—
125.00
250.00
—
8.51
0.00
—
78.13
—
-32.18
—
250.0 208.33
300.0 312.50
625.0 625.00
2
—
—
0
—
—
—
1
312.50
—
4.17
—
0
—
—
—
—
0
—
—
—
—
—
FOSC = 8.000000 MHz
FOSC = 7.159090 MHz
FOSC = 5.068800 MHz
FOSC = 4.000000 MHz
BAUD
RATE Actual
Actual
Rate
(K)
Actual
Rate
(K)
Actual
Rate
(K)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
%
Error
(K)
Rate
(K)
0.3
1.2
0.49
1.20
62.76
0.16
0.16
0.16
-6.99
8.51
8.51
—
255
103
51
12
6
0.44
1.20
45.65
0.23
-0.83
-2.90
-2.90
-2.90
-2.90
—
255
92
46
11
5
0.31
1.20
2.40
9.90
19.80
39.60
—
3.13
0.00
0.00
3.13
3.13
3.13
—
255
65
32
7
0.30
1.20
2.40
8.93
20.83
31.25
62.50
—
0.16
0.16
0.16
-6.99
8.51
-18.62
8.51
—
207
51
25
6
2.4
2.40
2.38
9.6
9.62
9.32
19.2
38.4
57.6
—
17.86
41.67
62.50
—
18.64
37.29
55.93
—
3
2
2
2
1
1
1
1
—
0
0
—
0
—
0
79.20
—
3.13
—
—
—
115.2
125.00
8.51
111.86
-2.90
—
—
—
FOSC = 3.579545 MHz
FOSC = 2.000000 MHz
FOSC = 1.000000 MHz
FOSC = 0.032768 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
Actual
Rate
(K)
Actual
Rate
(K)
Actual
Rate
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
%
%
%
%
Error
Error
Error
Error
(decimal)
(decimal)
(decimal)
(decimal)
0.3
1.2
0.30
1.19
2.43
9.32
18.64
—
0.23
-0.83
1.32
-2.90
-2.90
—
185
46
22
5
0.30
1.20
2.40
10.42
15.63
31.25
—
0.16
0.16
0.16
8.51
-18.62
-18.62
—
103
25
12
2
0.30
1.20
2.23
7.81
15.63
—
0.16
0.16
-6.99
-18.62
-18.62
—
51
12
6
0.26
—
-14.67
—
1
—
—
—
—
—
—
2.4
—
—
9.6
1
—
—
19.2
38.4
57.6
2
1
0
—
—
—
0
0
—
—
—
—
55.93
-2.90
—
—
—
—
—
2003 Microchip Technology Inc.
DS39599C-page 199
PIC18F2220/2320/4220/4320
TABLE 18-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1, HIGH SPEED)
FOSC = 40.000 MHz
SPBRG
FOSC = 20.000 MHz
SPBRG
FOSC = 16.000 MHz
SPBRG
FOSC = 10.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG
value
Actual
%
Actual
%
Actual
%
%
value
value
value
Rate (K) Error
Rate (K) Error
Rate (K) Error
Error
(decimal)
(decimal)
(decimal)
(decimal)
2.4
9.6
—
—
1.73
0.16
0.16
0.94
-1.36
0.16
-1.36
0.00
4.17
0.00
0.00
-16.67
0.00
—
255
129
64
42
32
25
21
9
4.88
9.62
103.45
0.16
0.16
-1.36
-1.36
1.73
0.16
-1.36
0.00
4.17
-16.67
0.00
—
255
129
64
32
21
15
12
10
4
3.91
9.62
62.76
0.16
0.16
0.16
2.12
0.16
4.17
-3.55
0.00
11.11
0.00
—
255
103
51
25
16
12
9
2.44
9.63
1.73
0.16
-1.36
1.73
-1.36
1.73
-6.99
8.51
255
64
32
15
10
7
9.77
19.2
19.23
38.46
58.14
75.76
96.15
113.64
250.00
312.50
500.00
625.00
833.33
19.23
37.88
56.82
78.13
96.15
113.64
250.00
312.50
416.67
625.00
—
19.23
38.46
58.82
76.92
100.00
111.11
250.00
333.33
500.00
—
18.94
39.06
56.82
78.13
89.29
125.00
38.4
57.6
76.8
96.0
6
115.2
250.0
300.0
500.0
625.0
1000.0
8
4
3
208.33 -16.67
2
7
3
2
312.50
—
4.17
—
1
4
2
1
—
0
3
1
—
0
625.00
—
0.00
—
2
—
0
1000.00
—
0.00
—
—
—
1250.0 1250.00
1
1250.00
0.00
—
—
—
FOSC = 8.000000 MHz
SPBRG
FOSC = 7.159090 MHz
SPBRG
FOSC = 5.068800 MHz
SPBRG
FOSC = 4.000 MHz
SPBRG
BAUD
RATE
(K)
Actual
%
Actual
%
Actual
%
Actual
%
value
value
value
value
Rate (K) Error
Rate (K) Error
Rate (K) Error
Rate (K) Error
(decimal)
(decimal)
(decimal)
(decimal)
0.3
1.2
—
—
—
255
207
51
25
12
8
—
—
—
255
185
46
22
11
7
—
1.24
2.40
9.60
18.64
39.60
52.80
79.20
—
—
3.13
0.00
0.00
-2.94
3.13
-8.33
3.13
—
—
255
131
32
16
7
0.98
1.20
2.40
9.62
19.23
35.71
62.50
83.33
—
225.52
0.16
0.16
0.16
0.16
-6.99
8.51
8.51
—
255
207
103
25
12
6
1.95
62.76
0.16
0.16
0.16
0.16
-3.55
-6.99
4.17
8.51
0.00
—
1.75
45.65
0.23
2.4
2.40
2.41
9.6
9.62
9.52
-0.83
1.32
19.2
38.4
57.6
76.8
96.0
115.2
250.0
300.0
500.0
19.23
38.46
55.56
71.43
100.00
125.00
250.00
—
19.45
37.29
55.93
74.57
89.49
111.86
223.72
—
-2.90
-2.90
-2.90
-6.78
-2.90
-10.51
—
5
3
6
5
3
2
4
4
—
2
—
1
3
3
105.60
—
-8.33
—
125.00
250.00
—
8.51
0.00
—
1
1
—
0
0
—
0
—
0
316.80
—
5.60
—
—
—
500.00
0.00
447.44
-10.51
—
—
—
FOSC = 3.579545 MHz
SPBRG
FOSC = 2.000000 MHz
SPBRG
FOSC = 1.000000 MHz
SPBRG
FOSC = 0.032768 MHz
SPBRG
BAUD
RATE
(K)
Actual
%
Actual
%
Actual
%
Actual
%
value
value
value
value
Rate (K) Error
Rate (K) Error
Rate (K) Error
Rate (K) Error
(decimal)
(decimal)
(decimal)
(decimal)
0.3
1.2
0.87
1.20
191.30
0.23
255
185
92
22
11
5
0.49
1.20
2.40
9.62
17.86
41.67
62.50
—
62.76
0.16
0.16
0.16
-6.99
8.51
8.51
—
255
103
51
12
6
0.30
1.20
2.40
8.93
20.83
31.25
62.50
—
0.16
0.16
0.16
-6.99
8.51
-18.62
8.51
—
207
51
25
6
0.29
1.02
2.05
—
-2.48
-14.67
-14.67
—
6
1
2.4
2.41
0.23
0
9.6
9.73
1.32
—
—
—
—
—
—
—
19.2
38.4
57.6
76.8
115.2
250.0
18.64
37.29
55.93
74.57
111.86
223.72
-2.90
-2.90
-2.90
-2.90
-2.90
-10.51
2
—
—
2
1
—
—
3
1
0
—
—
2
—
0
—
—
—
—
—
1
125.00
—
8.51
—
—
—
—
—
0
—
—
—
—
—
DS39599C-page 200
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 18-5: BAUD RATES FOR SYNCHRONOUS MODE (SYNC = 1)
FOSC = 40.000 MHz
SPBRG
FOSC = 20.000 MHz
SPBRG
FOSC = 16.000 MHz
SPBRG
FOSC = 10.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG
value
Actual
%
Actual
%
Actual
%
%
value
value
value
Rate (K) Error
Rate (K) Error
Rate (K) Error
Error
(decimal)
(decimal)
(decimal)
(decimal)
9.6
—
—
—
—
—
—
—
255
129
86
64
51
19
16
9
15.63
19.23
62.76
0.16
0.16
0.64
0.16
-0.79
0.00
2.56
0.00
6.67
0.00
6.67
255
207
103
68
51
41
15
12
7
9.77
19.23
38.46
58.14
75.76
96.15
250.00
312.50
500.00
625.00
1.73
0.16
0.16
0.94
-1.36
0.16
0.00
4.17
0.00
0.00
255
129
64
42
32
25
9
19.2
—
—
19.53
1.73
0.16
-0.22
0.16
0.16
0.00
-1.96
0.00
0.00
0.00
0.00
38.4
39.06
57.47
76.92
96.15
250.00
303.03
500.00
625.00
1.73
-0.22
0.16
0.16
0.00
1.01
0.00
0.00
0.00
0.00
255
173
129
103
39
32
19
15
9
38.46
38.46
57.6
57.47
57.97
76.8
76.92
76.92
96.0
96.15
95.24
250.0
300.0
500.0
625.0
250.00
294.12
500.00
625.00
1000.00
1250.00
250.00
307.69
500.00
666.67
1000.00
1333.33
7
4
7
5
3
1000.0 1000.00
1250.0 1250.00
4
3
833.33 -16.67
1250.00 0.00
2
7
3
2
1
FOSC = 8.000000 MHz
SPBRG
FOSC = 7.159090 MHz
SPBRG
FOSC = 5.068800 MHz
SPBRG
FOSC = 4.000 MHz
SPBRG
BAUD
RATE
(K)
Actual
%
Actual
%
Actual
%
Actual
%
value
value
value
value
Rate (K) Error
Rate (K) Error
Rate (K) Error
Rate (K) Error
(decimal)
(decimal)
(decimal)
(decimal)
2.4
9.6
7.81
9.62
225.52
0.16
0.16
0.16
-0.79
0.16
-0.79
0.00
-4.76
0.00
6.67
0.00
—
255
207
103
51
34
25
20
7
6.99
9.62
191.30
0.23
255
185
92
46
30
22
18
6
4.95
9.60
106.25
0.00
0.00
0.00
0.00
-2.94
1.54
1.38
5.60
-15.52
1.38
—
255
131
65
32
21
16
12
4
3.91
9.62
62.76
0.16
0.16
0.16
2.12
0.16
4.17
0.00
11.11
0.00
—
255
103
51
25
16
12
9
19.2
38.4
57.6
76.8
96.0
250.0
300.0
500.0
625.0
19.23
38.46
57.14
76.92
95.24
250.00
285.71
500.00
666.67
19.24
0.23
19.20
38.40
57.60
74.54
97.48
253.44
316.80
422.40
633.60
—
19.23
38.46
58.82
76.92
100.00
250.00
333.33
500.00
—
38.08
-0.83
0.23
57.73
77.82
1.32
94.20
-1.88
2.27
255.68
298.30
447.44
596.59
894.89
1789.77
3
6
-0.57
-10.51
-4.55
-10.51
43.18
5
3
2
3
3
2
1
2
2
1
—
0
1000.0 1000.00
1
1
—
0
1000.00
—
0.00
—
1250.0
—
—
0
1267.20
1.38
—
FOSC = 3.579545 MHz
SPBRG
FOSC = 2.000000 MHz
SPBRG
FOSC = 1.000000 MHz
SPBRG
FOSC = 0.032768 MHz
SPBRG
BAUD
RATE
(K)
Actual
%
Actual
%
Actual
%
Actual
%
value
value
value
value
Rate (K) Error
Rate (K) Error
Rate (K) Error
Rate (K) Error
(decimal)
(decimal)
(decimal)
(decimal)
0.3
1.2
—
—
—
—
255
92
46
22
15
11
8
—
—
—
255
207
51
25
12
8
0.98
1.20
225.52
0.16
0.16
0.16
0.16
-6.99
8.51
8.51
—
255
207
103
25
12
6
0.30
1.17
2.73
8.19
—
1.14
-2.48
13.78
-14.67
—
26
6
—
—
1.95
62.76
0.16
0.16
0.16
0.16
-3.55
-6.99
4.17
0.00
0.00
2.4
3.50
45.65
0.23
2.40
2.40
2
9.6
9.62
9.62
9.62
0
19.2
38.4
57.6
76.8
96.0
250.0
500.0
19.04
38.91
55.93
74.57
99.43
223.72
447.44
-0.83
1.32
19.23
38.46
55.56
71.43
100.00
250.00
500.00
19,.23
35.71
62.50
83.33
—
—
—
—
—
—
—
—
—
—
-2.90
-2.90
3.57
3
—
—
6
2
—
—
4
—
0
—
—
-10.51
-10.51
3
1
250.00
—
0.00
—
—
—
1
0
—
—
—
2003 Microchip Technology Inc.
DS39599C-page 201
PIC18F2220/2320/4220/4320
18.3.1
USART ASYNCHRONOUS
TRANSMITTER
18.3 USART Asynchronous Mode
In this mode, the USART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip dedicated 8-bit Baud Rate Gener-
ator can be used to derive standard baud rate frequen-
cies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent but use the same
data format and baud rate. The Baud Rate Generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not sup-
ported by the hardware but can be implemented in soft-
ware (and stored as the ninth data bit). Asynchronous
mode functions in all power managed modes except
Sleep mode when call clock sources are stopped.
When in PRI_IDLE mode, no changes to the Baud
Rate Generator values are required; however, other
power managed mode clocks may operate at another
frequency than the primary clock. Therefore, the Baud
Rate generator values may need adjusting.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit, TXIF (PIR1<4>), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. Flag bit TXIF is not cleared immediately upon
loading the Transmit Buffer register, TXREG. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following
a load of TXREG will return invalid results. While flag bit
TXIF indicated the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. Status bit TRMT is a read-only bit
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, therefore, the user must poll
this bit in order to determine whether the TSR register
is empty.
Asynchronous mode is selected by clearing bit, SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
FIGURE 18-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
8
TXIE
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
SPBRG
TRMT
SPEN
TX9
TX9D
Baud Rate Generator
DS39599C-page 202
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 18-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
TXIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
IPR1
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
TXREG USART Transmit Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
—
BRGH TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 203
PIC18F2220/2320/4220/4320
18.3.2
USART ASYNCHRONOUS
RECEIVER
18.3.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 18-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter, operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC. This mode would
typically be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with address
detect enable:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
To set up an Asynchronous Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.2 “USART Baud
Rate Generator (BRG)”).
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
9. Read RCREG to determine if the device is being
addressed.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-4:
USART RECEIVE BLOCK DIAGRAM
CREN
FERR
OERR
x64 Baud Rate CLK
÷ 64
or
÷ 16
RSR Register
MSb
Stop
LSb
SPBRG
0
7
1
Start
(8)
• • •
Baud Rate Generator
RX9
Pin Buffer
and Control
Data
Recovery
RC7/RX/DT
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
DS39599C-page 204
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
To set up an Asynchronous Transmission:
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.2 “USART Baud
Rate Generator (BRG)”).
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set Transmit bit,
TX9. Can be used as address/data bit.
FIGURE 18-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit 0 bit 1
bit 7/8
bit 7/8 Stop
bit
bit 7/8 Stop
bit
Stop
bit
bit 0
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun) bit to be set.
TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
PSPIE(1) ADIE
PSPIP(1) ADIP
ADIF
RCIF
RCIE
RCIP
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register
0000 0000 0000 0000
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH TRMT
SPBRG
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 205
PIC18F2220/2320/4220/4320
(PIE1<4>). Flag bit TXIF will be set regardless of the
18.4 USART Synchronous Master
Mode
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA<1>),
shows the status of the TSR register. TRMT is a read-
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty. The
TSR is not mapped in data memory so it is not available
to the user.
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit, SYNC (TXSTA<4>). In
addition, enable bit, SPEN (RCSTA<7>), is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit, CSRC (TXSTA<7>).
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.2 “USART Baud Rate
Generator (BRG)”).
18.4.1
USART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and inter-
rupt bit, TXIF (PIR1<4>), is set. The interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2Q3 Q4 Q1 Q2Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
RC6/TX/CK
pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRG = 0; continuous transmission of two 8-bit words.
DS39599C-page 206
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 18-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
TXREG USART Transmit Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
—
BRGH
TRMT
TX9D
Legend: x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 207
PIC18F2220/2320/4220/4320
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
18.4.2
USART SYNCHRONOUS MASTER
RECEPTION
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit, SREN
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
To set up a Synchronous Master Reception:
9. Read the 8-bit received data by reading the
RCREG register.
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.2 “USART Baud Rate
Generator (BRG)”).
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Legend: x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
DS39599C-page 208
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
To set up a Synchronous Slave Transmission:
18.5 USART Synchronous Slave Mode
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in any power managed mode. Slave
mode is entered by clearing bit, CSRC (TXSTA<7>).
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
18.5.1
USART SYNCHRONOUS SLAVE
TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
7. Start transmission by loading data to the TXREG
register.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
TXREG USART Transmit Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Legend: x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 209
PIC18F2220/2320/4220/4320
To set up a Synchronous Slave Reception:
18.5.2
USART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep or any
Idle mode and bit SREN, which is a “don't care” in
Slave mode.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting bit CREN prior to enter-
ing Sleep or any Idle mode, then a word may be
received while in this power managed mode. Once the
word is received, the RSR register will transfer the data
to the RCREG register and if enable bit RCIE bit is set,
the interrupt generated will wake the chip from the
power managed mode. If the global interrupt is
enabled, the program will branch to the interrupt vector.
5. Flag bit RCIF will be set when reception is
complete. An interrupt will be generated if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE
GIEL
RBIE TMR0IF INT0IF
RBIF 0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9 TXEN
SPBRG Baud Rate Generator Register
SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Legend: x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
DS39599C-page 210
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The module has five registers:
19.0 10-BIT ANALOG-TO-DIGITAL
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has 10
inputs for the PIC18F2X20 devices and 13 for the
PIC18F4X20 devices. This module allows conversion
of an analog input signal to a corresponding 10-bit
digital number.
The ADCON0 register, shown in Register 19-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 19-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 19-3, configures the A/D clock
source, programmed acquisition time and justification.
A new feature for the A/D converter is the addition of
programmable acquisition time. This feature allows the
user to select a new channel for conversion and setting
the GO/DONE bit immediately. When the GO/DONE bit is
set, the selected channel is sampled for the programmed
acquisition time before a conversion is actually started.
This removes the firmware overhead that may have been
required to allow for an acquisition (sampling) period (see
Register 19-3 and Section 19.3 “Selecting and
Configuring Automatic Acquisition Time”).
REGISTER 19-1: ADCON0 REGISTER
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)(1,2)
0110= Channel 6 (AN6)(1,2)
0111= Channel 7 (AN7)(1,2)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12)
1101= Unimplemented(2)
1110= Unimplemented(2)
1111= Unimplemented(2)
Note 1: These channels are not implemented on the PIC18F2X20 (28-pin) devices.
2: Performing a conversion on unimplemented channels returns full-scale results.
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 211
PIC18F2220/2320/4220/4320
REGISTER 19-2: ADCON1 REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-q(1) R/W-q(1) R/W-q(1) R/W-q(1)
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 0
bit 7
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit, VREFL Source
1= VREF- (AN2)
0= AVSS
bit 4
VCFG0: Voltage Reference Configuration bit, VREFH Source
1= VREF+ (AN3)
0= AVDD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG3:
PCFG0
0000(1)
0001
0010
0011
0100
0101
0110
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBAD bit in
Configuration Register 3H. When PBAD = 1, PCFG<3:0> = 0000; when PBAD = 0,
PCFG<3:0> = 0111.
2: AN5 through AN7 are available only in PIC18F4X20 devices.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 212
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 19-3: ADCON2 REGISTER
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS1:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is
added before the A/D clock starts. This allows the SLEEPinstruction to be executed
before starting a conversion.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 213
PIC18F2220/2320/4220/4320
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 19-1.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter which generates the result via successive
approximation.
FIGURE 19-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1100
AN12(2)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
0011
(Input Voltage)
10-bit
Converter
A/D
AN3/VREF+
0010
AN2/VREF-
0001
VCFG1:VCFG0
AN1
0000
AVDD
AN0
X0
X1
1X
0X
VREFH
VREFL
Reference
Voltage
AVSS
Note 1: Channels AN5 through AN7 are not available on PIC18F2X20 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39599C-page 214
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The value in the ADRESH/ADRESL registers is not
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
• Set ADIE bit
• Set GIE bit
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 19.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF if required.
The following steps should be followed to do an A/D
conversion:
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
FIGURE 19-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
VAIN
ILEAKAGE
± 500 nA
CHOLD = 120 pF
VT = 0.6 V
5 pF
VSS
Legend: CPIN
= input capacitance
= threshold voltage
6V
VT
5V
VDD 4V
3V
ILEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
= sampling switch
2V
SS
CHOLD
RSS
= sample/hold capacitance (from DAC)
= sampling switch resistance
5
6
7
8 9 10 11
Sampling Switch (kΩ)
2003 Microchip Technology Inc.
DS39599C-page 215
PIC18F2220/2320/4220/4320
19.1 A/D Acquisition Requirements
19.2 A/D VREF+ and VREF- References
For the A/D converter to meet its specified accuracy, the
Charge Holding Capacitor (CHOLD) must be allowed to
fully charge to the input channel voltage level. The ana-
log input model is shown in Figure 19-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD). The source imped-
ance affects the offset voltage at the analog input (due to
pin leakage current). The maximum recommended
impedance for analog sources is 2.5 kΩ. After the
analog input channel is selected (changed), the channel
must be sampled for at least the minimum acquisition
time before starting a conversion.
If external voltage references are used instead of the
internal AVDD and AVSS sources, the source imped-
ance of the VREF+ and VREF- voltage sources must be
considered. During acquisition, currents supplied by
these sources are insignificant. However, during con-
version, the A/D module sinks and sources current
through the reference sources.
In order to maintain the A/D accuracy, the voltage ref-
erence source impedances should be kept low to
reduce voltage changes. These voltage changes occur
as reference currents flow through the reference
source impedance. The maximum recommended
impedance of the VREF+ and VREF- external
reference voltage sources is 75Ω.
Note:
When the conversion is started, the holding
capacitor is disconnected from the input pin.
Note:
When using external references, the
source impedance of the external voltage
references must be less than 75Ω in order
to achieve the specified ADC resolution. A
higher reference source impedance will
increase the ADC offset and gain errors.
Resistive voltage dividers will not provide a
low enough source impedance. To ensure
the best possible ADC performance, exter-
nal VREF inputs should be buffered with an
op amp or other low-impedance circuit.
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 19-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is based
on the following application system assumptions:
CHOLD
RS
Conversion Error
VDD
Temperature
VHOLD
=
=
≤
=
=
=
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
EQUATION 19-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 19-2: MINIMUM A/D HOLDING CAPACITOR
VHOLD
or
=
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))
)
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EXAMPLE 19-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
5 µs
(Temp – 25°C)(0.05 µs/°C)
(50°C – 25°C)(0.05 µs/°C)
1.25 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC
–
-(CHOLD)(RIC + RSS + RS) ln(1/2047) µs
-(120 pF) (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) µs
9.61 µs
TACQ
=
5 µs + 1.25 µs + 9.61 µs
12.86 µs
DS39599C-page 216
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
19.3 Selecting and Configuring
Automatic Acquisition Time
19.4 Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
• 2 TOSC
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (approximately 2 µs, see parameter #130
for more information).
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module contin-
ues to sample the input for the selected acquisition
time, then automatically begins a conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
Table 19-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS2:ADCS0
PIC18FXX20
PIC18LFXX20(4)
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(3)
000
100
001
101
010
110
x11
1.25 MHz
2.50 MHz
5.00 MHz
10.0 MHz
20.0 MHz
40.0 MHz
1.00 MHz(1)
666 kHz
1.33 MHz
2.66 MHz
5.33 MHz
10.65 MHz
21.33 MHz
1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 4 µs.
2: The RC source has a typical TAD time of 6 µs.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
4: Low-power devices only.
2003 Microchip Technology Inc.
DS39599C-page 217
PIC18F2220/2320/4220/4320
19.5 Operation in Power Managed
Modes
19.6 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power managed mode.
If the A/D is expected to operate while the device is in
a power managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power managed mode clock that
will be used. After the power managed mode is entered
(either of the power managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power managed Idle mode during the
conversion.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
If the power managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
3: The PBADEN bit in the Configuration
register configures PORTB pins to reset
as analog or digital pins by controlling
how the PCFG0 bits in ADCON1 are
reset.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
DS39599C-page 218
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
19.7 A/D Conversions
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sleep mode before the
conversion begins.
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are set to ‘010’ and selecting a 4 TAD acquisition
time before the conversion starts.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 19-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD
TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6
b7
b6
b4
b1
b0
b2
b9
b8
b5
b3
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL are loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 19-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
7
8
9
10
b1
11
b0
1
2
3
4
1
2
3
4
5
6
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Conversion starts
(Holding capacitor is disconnected)
Set GO bit
(Holding capacitor continues
acquiring input)
Next Q4: ADRESH:ADRESL are loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
2003 Microchip Technology Inc.
DS39599C-page 219
PIC18F2220/2320/4220/4320
desired location). The appropriate analog input chan-
19.8 Use of the CCP2 Trigger
nel must be selected and the minimum acquisition
period is either timed by the user or an appropriate
TACQ time, selected before the “special event trigger”,
sets the GO/DONE bit (starts a conversion).
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automati-
cally repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
TABLE 19-2: SUMMARY OF A/D REGISTERS
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PSPIF
PSPIE
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
SSPIF CCP1IF
SSPIE CCP1IE
SSPIP CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
CCP2IF 00-0 0000 00-0 0000
CCP2IE 00-0 0000 00-0 0000
CCP2IP 11-1 1111 11-1 1111
xxxx xxxx uuuu uuuu
PSPIP
OSCFIF
OSCFIE
OSCFIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
—
—
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
ADCON0
ADCON1
ADCON2
PORTA
TRISA
—
—
—
—
CHS3
VCFG1
ACQT2
RA5
CHS3
VCFG0
ACQT1
RA4
CHS1
CHS0 GO/DONE ADON
--00 0000 --00 0000
PCFG0 --00 qqqq --00 qqqq
ADCS0 0-00 0000 0-00 0000
PCFG3 PCFG2
ACQT0 ADCS2
PCFG1
ADCS1
RA1
ADFM
—
(4)
(4)
RA7
RA6
RA3
RA2
RA0
--0x 0000 --0u 0000
--11 1111 --11 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- xxxx ---- uuuu
0000 -111 0000 -111
---- -xxx ---- -uuu
(4)
(4)
TRISA7
TRISA6
PORTB
TRISB
Read PORTB pins, Write LATB Latch
PORTB Data Direction Register
PORTB Output Data Latch
LATB
(2)
(4)
PORTE
—
IBF
—
—
OBE
—
—
IBOV
—
—
PSPMODE
—
RE3
—
Read PORTE pins, Write LATE
PORTE Data Direction
(3)
TRISE
(3)
LATE
PORTE Output Data Latch
Legend:
x= unknown, u= unchanged, - = unimplemented, read as ‘0’, q= value depends on condition.
Shaded cells are not used for A/D conversion.
Note 1: RE3 port bit is available only as an input pin when MCLRE bit in configuration register is ‘0’.
2: This register is not implemented on PIC18F2X20 devices.
3: These bits are not implemented on PIC18F2X20 devices.
4: These pins may be configured as port pins depending on the oscillator mode selected.
DS39599C-page 220
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
20.1 Comparator Configuration
20.0 COMPARATOR MODULE
There are eight modes of operation for the comparators.
The CM bits (CMCON<2:0>) are used to select these
modes. Figure 20-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator mode
is changed, the comparator output level may not be valid
for the specified mode change delay shown in the
Electrical Specifications (see Section 26.0 “Electrical
Characteristics”).
The comparator module contains two analog compara-
tors. The inputs and outputs for the comparators are
multiplexed with the RA0 through RA5 pins. The on-
chip voltage reference (Section 21.0 “Comparator
Voltage Reference Module”) can also be an input to
the comparators.
The CMCON register, shown as Register 20-1,
controls the comparator module’s input and output
multiplexers.
A
block diagram of the various
comparator configurations is shown in Figure 20-1.
Note:
Comparator interrupts should be disabled
during Comparator mode change.
Otherwise, a false interrupt may occur.
a
REGISTER 20-1: CMCON REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-1
CM2
R/W-1
CM1
R/W-1
CM0
C2OUT
C1OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RA3/AN3
C2 VIN- connects to RA2/AN2
0= C1 VIN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 20-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
2003 Microchip Technology Inc.
DS39599C-page 221
PIC18F2220/2320/4220/4320
FIGURE 20-1:
COMPARATOR I/O OPERATING MODES
Comparators RESET
Comparators Off (POR Default Value)
CM<2:0> = 000
CM<2:0> = 111
D
D
VIN-
VIN-
RA0/AN0
RA0/AN0
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
D
D
RA3/AN3/
VREF+
RA3/AN3/
VREF+
D
D
D
VIN-
VIN-
RA1/AN1
RA2/AN2/
RA1/AN1
VIN+
VIN+
D
RA2/AN2/
VREF-/CVREF
VREF-/CVREF
Two Independent Comparators with Outputs
CM<2:0> = 011
Two Independent Comparators
CM<2:0> = 010
A
VIN-
A
VIN-
RA0/AN0
RA0/AN0
C1OUT
C2OUT
C1
VIN+
A
C1OUT
C2OUT
C1
C2
VIN+
RA3/AN3/
VREF+
A
RA3/AN3/
VREF+
(1)
RA4/T0CKI/C1OUT
A
A
VIN-
RA1/AN1
RA2/AN2/
A
VIN-
RA1/AN1
RA2/AN2/
VIN+
C2
VIN+
A
VREF-/CVREF
VREF-/CVREF
(1)
RA5/AN4/SS/LVDIN/C2OUT
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
CM<2:0> = 100
CM<2:0> = 101
A
A
A
VIN-
VIN-
RA0/AN0
RA0/AN0
C1OUT
C2OUT
C1OUT
C1
C2
C1
C2
VIN+
VIN+
A
RA3/AN3/
VREF+
RA3/AN3/
VREF+
(1)
RA4/T0CKI/C1OUT
A
D
VIN-
RA1/AN1
RA2/AN2/
A
D
VIN-
VIN+
VIN+
RA1/AN1
C2OUT
VREF-/CVREF
RA2/AN2/
VREF-/CVREF
(1)
RA5/AN4/SS/LVDIN/C2OUT
Four Inputs Multiplexed to Two Comparators
One Independent Comparator with Output
CM<2:0> = 110
CM<2:0> = 001
A
A
A
VIN-
RA0/AN0
RA0/AN0
CIS = 0
CIS = 1
VIN-
A
C1OUT
C1
C2
VIN+
RA3/AN3/
VREF+
C1OUT
C1
C2
RA3/AN3/
VREF+
VIN+
A
A
(1)
RA4/T0CKI/C1OUT
RA1/AN1
RA2/AN2/
VIN-
CIS = 0
CIS = 1
C2OUT
VIN+
D
D
VIN-
RA1/AN1
RA2/AN2/
VREF-/CVREF
CVROE = 0
CVROE = 1
Off (Read as ‘0’)
VIN+
CVREF
From VREF Module
VREF-/CVREF
(2)
A = Analog Input, port reads zeros always, overrides TRISA bit
D = Digital Input.
.
CIS (CMCON<3>) is the Comparator Input Switch; CVROE (CVRCON<6>) is the Voltage Reference Output Switch.
Note 1: RA4 must be configured as an output pin in TRISA<4> when used to output C1OUT. RA5 ignores TRISA<5> when
used as an output for C2OUT.
2: Mode 110 is exception. Comparator input pins obey TRISA bits.
DS39599C-page 222
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
20.3.2
INTERNAL REFERENCE SIGNAL
20.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference for the compara-
tors. Section 21.0 “Comparator Voltage Reference
Module” contains a detailed description of the compar-
ator voltage reference module that provides this signal.
The internal reference signal is used when comparators
are in mode, CM2:CM0 = 110 (Figure 20-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
A single comparator is shown in Figure 20-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 20-2 represent
the uncertainty due to input offsets and response time.
Depending on the setting of the CVROE bit
(CVRCON<6>), the voltage reference may also be
available on pin RA2.
20.3 Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingly (Figure 20-2).
20.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Table 26-2 in
Section 26.0 “Electrical Characteristics”).
FIGURE 20-2:
SINGLE COMPARATOR
VIN+
VIN-
+
Output
–
20.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA4 and RA5
I/O pins. When enabled, multiplexers in the output path
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 20-3 shows the
comparator output block diagram.
VIN-
VIN+
Output
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5>).
20.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
Note 1: When reading the Port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
2003 Microchip Technology Inc.
DS39599C-page 223
PIC18F2220/2320/4220/4320
FIGURE 20-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
-
CxINV
To RA4 or
RA5 Pin
Bus
Data
Q
D
Read CMCON
EN
Q
Set
CMIF
bit
D
From
other
Comparator
EN
CL
Read CMCON
Reset
20.6 Comparator Interrupts
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit is cleared by firmware. Since it is also possible
to write a ‘1’ to this register, a simulated interrupt may
be initiated.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DS39599C-page 224
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
20.7 Comparator Operation in Power
20.9 Analog Input Connection
Considerations
Managed Modes
When a comparator is active and the device is placed
in a power managed mode, the comparator remains
active and the interrupt is functional if enabled. This
interrupt will wake-up the device from a power
managed mode when enabled. Each operational com-
parator will consume additional current, as shown in
the comparator specifications. To minimize power
consumption while in a power managed mode, turn off
the comparators (CM<2:0> = 111) before entering the
power managed modes. If the device wakes up from a
power managed mode, the contents of the CMCON
register are not affected.
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Therefore, the analog input must be between
VSS and VDD. If the input voltage exceeds this range by
more than 0.6V, one of the diodes is forward biased
and a latch-up condition may occur. A maximum source
impedance of 10 kΩ is recommended for the analog
sources.
20.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the Com-
parator Reset mode (CM<2:0> = 111). This ensures
that all potential inputs are analog inputs. Device cur-
rent is minimized when digital inputs are present at
Reset time. The comparators will be powered down
during the Reset interval.
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
2003 Microchip Technology Inc.
DS39599C-page 225
PIC18F2220/2320/4220/4320
TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
all other
Resets
Value on
POR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON C2OUT C1OUT C2INV C1INV
CVRCON CVREN CVROE CVRR
CIS
CM2
CM1
CM0
0000 0111 0000 0111
—
CVR3
CVR2
CVR1
CVR0 000- 0000 000- 0000
RBIF 0000 0000 0000 0000
INTCON
GIE/
PEIE/ TMR0IE INT0IE
GIEL
RBIE TMR0IF INT0IF
GIEH
PIR2
—
—
CMIF
CMIE
CMIP
RA6(1)
—
—
—
—
—
BCLIF
BCLIE
BCLIP
RA3
LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000
LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000
LVDIP TMR3IP CCP2IP -1-- 1111 -1-- 1111
PIE2
IPR2
—
RA7(1)
—
—
PORTA
LATA
TRISA
RA5
RA4
RA2
RA1
RA0
xx0x 0000 xx0x 0000
xxxx xxxx xxxx xxxx
1111 1111 1111 1111
—
LATA Data Output Register
PORTA Data Direction Register
—
—
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’.
Shaded cells are unused by the comparator module.
Note 1: These pins are enabled based on oscillator configuration (see Configuration Register 1H).
DS39599C-page 226
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
21.1 Configuring the Comparator
Voltage Reference
21.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference can output 16 distinct
voltage levels for each range. The equations used to cal-
culate the output of the comparator voltage reference
are as follows:
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable voltage refer-
ence. The resistor ladder is segmented to provide two
ranges of CVREF values and has a power-down func-
tion to conserve power when the reference is not being
used. The CVRCON register controls the operation of
the reference as shown in Register 21-1. The block
diagram is given in Figure 21-1.
EQUATION 21-1:
If CVRR = 1:
CVREF = (CVR<3:0>) •
VDD
24
The comparator reference supply voltage comes from
VDD and VSS.
If CVRR = 0:
CVREF = (CVR<3:0> + 8) •
VDD
32
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 26-2 in Section 26.0 “Electrical
Characteristics”).
REGISTER 21-1:
CVRCON REGISTER
R/W-0
R/W-0
R/W-0
CVRR
U-0
—
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVROE
bit 7
bit 0
bit 7
bit 6
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit
1= CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF(1) pin
0= CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin
Note 1: CVROE overrides the TRISA<2> bit setting.
bit 5
CVRR: Comparator VREF Range Selection bit
1= 0.00 VDD to 0.75 VDD, with VDD/24 step size
0= 0.25 VDD to 0.75 VDD, with VDD/32 step size
bit 4
Unimplemented: Read as ‘0’
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection 0 ≤ VR3:VR0 ≤ 15 bits
When CVRR = 1:
VDD
CVREF = (CVR<3:0>) •
24
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (CVR<3:0> + 8) •
VDD
32
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 227
PIC18F2220/2320/4220/4320
FIGURE 21-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
16 Stages
CVREN
R
R
R
R
8R
CVRR
RA2/AN2/VREF-/CVREF
8R
CVROE
CVR3
(From CVRCON<3:0>)
CVR0
CVREF
16-1 Analog Mux
21.2 Voltage Reference Accuracy/Error
21.4 Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 21-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from VDD; therefore, the CVREF output changes with
fluctuations in VDD. The tested absolute accuracy of
the voltage reference can be found in Section 26.0
“Electrical Characteristics”.
A device Reset disables the voltage reference by clear-
ing the CVRCON register. This also disconnects the
reference from the RA2 pin, selects the high-voltage
range and selects the lowest voltage tap from the
resistor divider.
21.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be output using the RA2 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto the RA2 pin, with an input signal present, will
increase current consumption.
21.3 Operation in Power Managed
Modes
The contents of the CVRCON register are not affected
by entry to or exit from power managed modes. To min-
imize current consumption in power managed modes,
the voltage reference module should be disabled; how-
ever, this can cause an interrupt from the comparators
so the comparator interrupt should also be disabled
while the CVRCON register is being modified.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, an external buffer must be used on the
voltage reference output for external connections to
VREF. Figure 21-2 shows an example buffering
technique.
DS39599C-page 228
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 21-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
R
RA2
CVREF
Module
+
–
CVREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration bits (CVRCON<3:0> and CVRCON<5>).
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Value on
all other
Resets
Value on
POR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVRCON CVREN CVROE CVRR
—
CVR3
CIS
CVR2
CM2
RA2
CVR1
CM1
RA1
CVR0 000- 0000 000- 0000
CMCON
TRISA
C2OUT C1OUT C2INV C1INV
RA7(1) RA6(1)
RA5 RA4
CM0
RA0
0000 0111 0000 0111
1111 1111 1111 1111
RA3
Legend: x= unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
Note 1: These pins are enabled based on oscillator configuration (see Configuration Register 1H).
2003 Microchip Technology Inc.
DS39599C-page 229
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 230
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference, TB – TA, is the total
time for shutdown.
22.0 LOW-VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do “housekeeping tasks” before the device
voltage exits the valid operating range. This can be
done using the Low-Voltage Detect (LVD) module.
The block diagram for the LVD module is shown in
Figure 22-2. A comparator uses an internally gener-
ated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to that interrupt source.
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage ref-
erence module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 22-2). The trip point is selected by programming
the LVDL3:LVDL0 bits (LVDCON<3:0>).
The Low-Voltage Detect circuitry is completely under
software control. This allows the circuitry to be turned
off by the software which minimizes the current
consumption for the device.
Figure 22-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
FIGURE 22-1:
TYPICAL LOW-VOLTAGE DETECT APPLICATION
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TB
TA
Time
2003 Microchip Technology Inc.
DS39599C-page 231
PIC18F2220/2320/4220/4320
FIGURE 22-2:
LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD
LVDIN
LVD Control
Register
LVDIF
Internally Generated
LVDEN
Reference Voltage
1.2V
The LVD module has an additional feature that allows
the user to supply the sense voltage to the module
from an external source. This mode is enabled when
bits LVDL3:LVDL0 are set to ‘1111’. In this state, the
comparator input is multiplexed from the external input
pin, LVDIN (Figure 22-3). This gives users flexibility
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
FIGURE 22-3:
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVD Control
Register
LVDIN
LVDEN
Externally Generated
Trip Point
LVD
VxEN
BODEN
EN
BGAP
DS39599C-page 232
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
22.1 Control Register
The Low-Voltage Detect Control register controls the
operation of the Low-Voltage Detect circuitry.
REGISTER 22-1: LVDCON REGISTER
U-0
—
U-0
—
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5
bit 4
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0= Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
LVDEN: Low-Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.50V-4.78V
1101= 4.20V-4.46V
1100= 4.00V-4.26V
1011= 3.80V-4.04V
1010= 3.60V-3.84V
1001= 3.50V-3.72V
1000= 3.30V-3.52V
0111= 3.00V-3.20V
0110= 2.80V-2.98V
0101= 2.70V-2.86V
0100= 2.50V-2.66V
0011= 2.40V-2.55V
0010= 2.20V-2.34V
0001= 2.00V-2.12V
0000= Reserved
Note:
LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
DS39599C-page 233
PIC18F2220/2320/4220/4320
The following steps are needed to set up the LVD
module:
22.2 Operation
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be
constantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods where the voltage is checked. After doing
the check, the LVD module may be disabled.
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register) which selects the desired
LVD trip point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 22-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 22-4:
LOW-VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIVRST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
TIVRST
Internally Generated
Reference Stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS39599C-page 234
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
22.2.1
REFERENCE VOLTAGE SET POINT
22.3 Operation During Sleep
The internal reference voltage of the LVD module may
be used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low-voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low-voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 22-4.
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
22.4 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
22.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
2003 Microchip Technology Inc.
DS39599C-page 235
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 236
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The inclusion of an internal RC oscillator also provides
23.0 SPECIAL FEATURES OF THE
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up while the primary clock source
completes its start-up delays.
CPU
PIC18F2X20/4X20 devices include several features
intended to maximize system reliability and minimize
cost through elimination of external components.
These are:
• Oscillator Selection
• Resets:
All of these features are enabled and configured by
setting the appropriate configuration register bits.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
23.1 Configuration Bits
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh)
which can only be accessed using table reads and
table writes.
• ID Locations
• In-Circuit Serial Programming
Programming the configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
configuration register. In normal operation mode, a
TBLWTinstruction with the TBLPTR pointing to the con-
figuration register sets up the address and the data for
the configuration register write. Setting the WR bit
starts a long write to the configuration register. The con-
figuration registers are written a byte at a time. To write
or erase a configuration cell, a TBLWTinstruction can
write a ‘1’ or a ‘0’ into the cell. For additional details on
Flash programming, refer to Section 6.5 “Writing to
Flash Program Memory”.
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2X20/4X20
devices have a Watchdog Timer which is either perma-
nently enabled via the configuration bits or software
controlled (if configured as disabled).
TABLE 23-1: CONFIGURATION BITS AND DEVICE IDS
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
IESO
—
FSCM
—
—
—
—
—
FOSC3
FOSC2
FOSC1
BOR
FOSC0
PWRT
WDT
CCP2MX
STVR
CP0
11-- 1111
---- 1111
---1 1111
1--- --11
1--- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
BORV1
BORV0
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0
300005h CONFIG3H MCLRE
300006h CONFIG4L DEBUG
—
—
—
—
—
—
—
LVP
PBAD
—
—
—
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
—
CPD
—
—
—
—
CP3
—
CP2
—
CP1
—
CPB
—
—
—
—
—
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
30000Bh CONFIG6H WRTD
WRTB
—
WRTC
—
—
30000Ch CONFIG7L
30000Dh CONFIG7H
—
—
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
EBTRB
DEV1
DEV9
—
—
(1)
(1)
3FFFFEh DEVID1
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(1)
3FFFFFh DEVID2
0000 0101
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 23-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
2003 Microchip Technology Inc.
DS39599C-page 237
PIC18F2220/2320/4220/4320
REGISTER 23-1: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTEADDRESS300001h)
R/P-1
IESO
R/P-1
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
FSCM
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7
bit 6
IESO: Internal External Switch Over bit
1= Internal External Switch Over mode enabled
0= Internal External Switch Over mode disabled
FSCM: Fail-Safe Clock Monitor enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 FOSC<3:0>: Oscillator Selection bits
11xx= External RC oscillator, CLKO function on RA6
1001= Internal oscillator block, CLKO function on RA6 and port function on RA7
1000= Internal oscillator block, port function on RA6 and port function on RA7
0111= External RC oscillator, port function on RA6
0110= HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
0101= EC oscillator, port function on RA6
0100= EC oscillator, CLKO function on RA6
0010= HS oscillator
0001= XT oscillator
0000= LP oscillator
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
DS39599C-page 238
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 23-2: CONFIG2L:CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS300002h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
BOR
R/P-1
BORV1
BORV0
PWRT
bit 7
bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits
11= VBOR set to 2.0V
10= VBOR set to 2.7V
01= VBOR set to 4.2V
00= VBOR set to 4.5V
bit 1
bit 0
BOR: Brown-out Reset enable bit(1)
1= Brown-out Reset enabled
0= Brown-out Reset disabled
PWRT: Power-up Timer enable bit(1)
1= PWRT disabled
0= PWRT enabled
Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to
be independently controlled.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDT
WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7
bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDPS<3:0>: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
bit 0
WDT: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
2003 Microchip Technology Inc.
DS39599C-page 239
PIC18F2220/2320/4220/4320
REGISTER 23-4: CONFIG3H:CONFIGURATIONREGISTER3HIGH(BYTEADDRESS300005h)
R/P-1
MCLRE
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
PBAD
R/P-1
CCP2MX
bit 0
bit 7
MCLRE: MCLR Pin Enable bit
1= MCLR pin enabled; RE3 input pin disabled
0= RE3 input pin enabled; MCLR disabled
bit 6-2 Unimplemented: Read as ‘0’
bit 1
PBAD: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0>
pin configuration.)
1= PORTB<4:0> pins are configured as analog input channels on Reset
0= PORTB<4:0> pins are configured as digital I/O on Reset
bit 0
CCP2MX: CCP2 Mux bit
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RB3
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 23-5: CONFIG4L:CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS300006h)
R/P-1
DEBUG
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
LVP
U-0
—
R/P-1
STVR
bit 0
bit 7
DEBUG: Background Debugger Enable bit
1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6-3 Unimplemented: Read as ‘0’
bit 2
LVP: Low-Voltage ICSP Enable bit
1= Low-voltage ICSP enabled
0= Low-voltage ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVR: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause Reset
0= Stack full/underflow will not cause Reset
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39599C-page 240
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 23-6: CONFIG5L:CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS300008h)
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
CP3(1)
R/C-1
CP2(1)
R/C-1
CP1
R/C-1
CP0
bit 7
bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3
bit 2
bit 1
bit 0
CP3: Code Protection bit(1)
1= Block 3 (001800-001FFFh) not code-protected
0= Block 3 (001800-001FFFh) code-protected
CP2: Code Protection bit(1)
1= Block 2 (001000-0017FFh) not code-protected
0= Block 2 (001000-0017FFh) code-protected
CP1: Code Protection bit
1= Block 1 (000800-000FFFh) not code-protected
0= Block 1 (000800-000FFFh) code-protected
CP0: Code Protection bit
1= Block 0 (000200-0007FFh) not code-protected
0= Block 0 (000200-0007FFh) code-protected
Note 1: Unimplemented in PIC18FX220 devices; maintain this bit set.
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 23-7: CONFIG5H:CONFIGURATIONREGISTER5HIGH(BYTEADDRESS300009h)
R/C-1
CPD
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
bit 6
CPD: Data EEPROM Code Protection bit
1= Data EEPROM not code-protected
0= Data EEPROM code-protected
CPB: Boot Block Code Protection bit
1= Boot block (000000-0001FFh) not code-protected
0= Boot block (000000-0001FFh) code-protected
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
2003 Microchip Technology Inc.
DS39599C-page 241
PIC18F2220/2320/4220/4320
REGISTER 23-8: CONFIG6L:CONFIGURATIONREGISTER6LOW(BYTE ADDRESS30000Ah)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
WRT3(1) WRT2(1)
R/P-1
R/P-1
R/P-1
WRT1
WRT0
bit 7
bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3
bit 2
bit 1
bit 0
WRT3: Write Protection bit(1)
1= Block 3 (001800-001FFFh) not write-protected
0= Block 3 (001800-001FFFh) write-protected
WRT2: Write Protection bit(1)
1= Block 2 (001000-0017FFh) not write-protected
0= Block 2 (001000-0017FFh) write-protected
WRT1: Write Protection bit
1= Block 1 (000800-000FFFh) not write-protected
0= Block 1 (000800-000FFFh) write-protected
WRT0: Write Protection bit
1= Block 0 (000200-0007FFh) not write-protected
0= Block 0 (000200-0007FFh) write-protected
Note 1: Unimplemented in PIC18FX220 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 23-9: CONFIG6H:CONFIGURATION REGISTER6 HIGH(BYTEADDRESS30000Bh)
R/P-1
R/P-1
R-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
WRTD
WRTB
WRTC
bit 7
bit 0
bit 7
bit 6
bit 5
WRTD: Data EEPROM Write Protection bit
1= Data EEPROM not write-protected
0= Data EEPROM write-protected
WRTB: Boot Block Write Protection bit
1= Boot block (000000-0001FFh) not write-protected
0= Boot block (000000-0001FFh) write-protected
WRTC: Configuration Register Write Protection bit
1= Configuration registers (300000-3000FFh) not write-protected
0= Configuration registers (300000-3000FFh) write-protected
Note:
This bit is read-only in normal execution mode; it can be written only in Program
mode.
bit 4-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39599C-page 242
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 23-10: CONFIG7L:CONFIGURATIONREGISTER7LOW(BYTEADDRESS30000Ch)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
EBTR3(1) EBTR2(1)
R/P-1
R/P-1
R/P-1
EBTR1
EBTR0
bit 7
bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3
bit 2
bit 1
bit 0
EBTR3: Table Read Protection bit(1)
1= Block 3 (001800-001FFFh) not protected from table reads executed in other blocks
0= Block 3 (001800-001FFFh) protected from table reads executed in other blocks
EBTR2: Table Read Protection bit(1)
1= Block 2 (001000-0017FFh) not protected from table reads executed in other blocks
0= Block 2 (001000-0017FFh) protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
1= Block 1 (000800-000FFFh) not protected from table reads executed in other blocks
0= Block 1 (000800-000FFFh) protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
1= Block 0 (000200-0007FFh) not protected from table reads executed in other blocks
0= Block 0 (000200-0007FFh) protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18FX220 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 23-11: CONFIG7H:CONFIGURATION REGISTER7 HIGH(BYTEADDRESS30000Dh)
U-0
—
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
EBTRB
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1= Boot block (000000-0001FFh) not protected from table reads executed in other blocks
0= Boot block (000000-0001FFh) protected from table reads executed in other blocks
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
2003 Microchip Technology Inc.
DS39599C-page 243
PIC18F2220/2320/4220/4320
REGISTER 23-12: DEVICE ID REGISTER 1 FOR PIC18F2220/2320/4220/4320 DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5 DEV2:DEV0: Device ID bits
000= PIC18F4220
001= PIC18F4320
100= PIC18F2220
101= PIC18F2320
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Read-only bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 23-13: DEVICE ID REGISTER 2 FOR PIC18F2220/2320/4220/4320 DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the
part number.
0000 0101= PIC18F2220/2320/4220/4320 devices
Note:
These values for DEV10:DEV3 may be shared with other devices. The specific
device is always identified by using the entire DEV10:DEV0 bit sequence.
Legend:
R = Read-only bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39599C-page 244
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
23.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F2X20/4X20 devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
2: Changing the setting of the IRCF bits
(OSCCON<6:4> clears the WDT and
postscaler counts.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: execute a SLEEP or CLRWDT instruction, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
3: When a CLRWDTinstruction is executed,
the postscaler count will be cleared.
23.2.1
CONTROL REGISTER
Register 23-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit, but only if the configuration bit has
disabled the WDT.
Adjustments to the internal oscillator clock period using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
FIGURE 23-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
WDTEN
INTRC Control
WDT Counter
÷125
Wake-up
from Sleep
INTRC Source
Change on IRCF bits
CLRWDT
WDT
Reset
Reset
Programmable Postscaler
1:1 to 1:32,768
All Device Resets
WDT
4
WDTPS<3:0>
Sleep
2003 Microchip Technology Inc.
DS39599C-page 245
PIC18F2220/2320/4220/4320
REGISTER 23-14: WDTCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN
bit 0
bit 7
bit 7-1 Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is off
Note 1: This bit has no effect if the configuration bit, WDTEN (CONFIG2H<0>), is enabled.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG2H
RCON
—
IPEN
—
—
—
—
—
—
—
WDTPS3 WDTPS2 WDTPS2 WDTPS0
WDTEN
BOR
RI
—
TO
—
PD
—
POR
—
WDTCON
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
DS39599C-page 246
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
23.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscil-
lator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
In all other power managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
Two-Speed Start-up is available only if the primary oscil-
lator mode is LP, XT, HS or HSPLL (Crystal-based
modes). Other sources do not require a OST start-up
delay; for these, Two-Speed Start-up is disabled.
23.3.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power managed modes, including serial
SLEEP instructions (refer to Section 3.1.3 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings and issue
SLEEPcommands before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execution
while the primary oscillator starts and the OST is run-
ning. Once the OST times out, the device automatically
switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits IFRC2:IFRC0 immediately after
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
FIGURE 23-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2
INTOSC
Multiplexer
OSC1
(1)
TOST
(1)
TPLL
PLL Clock
Output
1
2
3
4
5
6
7
8
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 6
Wake from Interrupt Event
2003 Microchip Technology Inc.
DS39599C-page 247
PIC18F2220/2320/4220/4320
Since the postscaler frequency from the internal oscil-
23.4 Fail-Safe Clock Monitor
lator block may not be sufficiently stable, it may be
desirable to select another clock configuration and
enter an alternate power managed mode (see
Section 23.3.1 “Special Considerations for Using
Two-Speed Start-up” and Section 3.1.3 “Multiple
Sleep Commands” for more details). This can be
done to attempt a partial recovery or execute a
controlled shutdown.
The Fail-Safe Clock Monitor (FSCM) allows the micro-
controller to continue operation, in the event of an
external oscillator failure, by automatically switching
the system clock to the internal oscillator block. The
FSCM function is enabled by setting the Fail-Safe
Clock Monitor Enable bit, FCMEN (CONFIG1H<6>).
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide
an instant backup clock in the event of a clock failure.
Clock monitoring (shown in Figure 23-3) is accom-
plished by creating a sample clock signal, which is the
INTRC output divided by 64. This allows ample time
between FSCM sample clocks for a peripheral clock
edge to occur. The peripheral system clock and the
sample clock are presented as inputs to the Clock Mon-
itor latch (CM). The CM is set on the falling edge of the
system clock source but cleared on the rising edge of
the sample clock.
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits IFRC2:IFRC0
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting IFRC2:IFRC0 prior to entering Sleep mode.
Adjustments to the internal oscillator block using the
OSCTUNE register also affect the period of the FSCM
by the same factor. This can usually be neglected, as
the clock frequency being monitored is generally much
higher than the sample clock frequency.
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
FIGURE 23-3:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
S
Q
23.4.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a sep-
arate divider and counter, disabling the WDT has no
effect on the operation of the INTRC oscillator when the
FSCM is enabled.
INTRC
Source
C
Q
÷ 64
(32 µs)
488 Hz
(2.048 ms)
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, fail-safe clock events
also reset the WDT and postscaler, allowing it to start
timing from when execution speed was changed and
decreasing the likelihood of an erroneous time-out.
Clock
Failure
Detected
Clock failure is tested on the falling edge of the sample
clock. If a sample clock falling edge occurs while CM is
still set, a clock failure has been detected (Figure 23-4).
This causes the following:
• The FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>)
• The system clock source is switched to the
internal oscillator block (OSCCON is not updated
to show the current clock source – this is the
fail-safe condition)
• The WDT is reset
DS39599C-page 248
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The primary clock source may never become ready dur-
ing start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain in
its Reset state until a power managed mode is entered.
23.4.2
EXITING FAIL-SAFE OPERATION
The fail-safe condition is terminated by either a device
Reset or by entering a power managed mode. On Reset,
the controller starts the primary clock source specified in
Configuration Register 1H (with any required start-up
delays that are required for the oscillator mode, such as
OST or PLL timer). The INTOSC multiplexer provides the
system clock until the primary clock source becomes
ready (similar to a Two-speed Start-up). The clock system
source is then switched to the primary clock (indicated by
the OSTS bit in the OSCCON register becoming set). The
Fail-Safe Clock Monitor then resumes monitoring the
peripheral clock.
Entering a power managed mode by loading the
OSCCON register and executing a SLEEP instruction
will clear the fail-safe condition. When the fail-safe
condition is cleared, the clock monitor will resume
monitoring the peripheral clock.
FIGURE 23-4:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
2003 Microchip Technology Inc.
DS39599C-page 249
PIC18F2220/2320/4220/4320
23.4.3
FSCM INTERRUPTS IN POWER
MANAGED MODES
23.4.4
POR OR WAKE FROM SLEEP
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or Low-Power Sleep mode. When the primary
system clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
As previously mentioned, entering a power managed
mode clears the fail-safe condition. By entering a
power managed mode, the clock multiplexer selects
the clock source selected by the OSCCON register.
Fail-safe monitoring of the power managed clock
source resumes in the power managed mode.
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat dif-
ferent. Since the oscillator may require a start-up time
considerably longer than the FCSM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the system clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source.
If an oscillator failure occurs during power managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, the device will not exit the
power managed mode on oscillator failure. Instead, the
device will continue to operate as before but clocked by
the INTOSC multiplexer. While in Idle mode, subse-
quent interrupts will cause the CPU to begin executing
instructions while being clocked by the INTOSC multi-
plexer. The device will not transition to a different clock
source until the fail-safe condition is cleared.
Note:
The same logic that prevents false oscilla-
tor failure interrupts on POR or wake from
Sleep will also prevent the detection of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a tim-
ing routine to determine if the oscillator is
taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
As noted in Section 23.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alter-
nate power managed mode while waiting for the pri-
mary system clock to become stable. When the new
powered managed mode is selected, the primary clock
is disabled.
DS39599C-page 250
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Each of the five blocks has three code protection bits
associated with them. They are:
23.5 Program Verification and
Code Protection
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro® devices.
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code protec-
tion bit associated with each block. The actual locations
of the bits are summarized in Table 23-3.
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into four blocks on binary
boundaries.
FIGURE 23-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2X20/4X20
MEMORY SIZE/DEVICE
Block Code Protection
4 Kbytes
(PIC18F2220/4220)
8 Kbytes
(PIC18F2320/4320)
Address
Range
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000000h
0001FFh
Boot Block
Boot Block
Block 0
000200h
Block 0
Block 1
0007FFh
000800h
Block 1
Block 2
Block 3
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
000FFFh
001000h
Unimplemented
Read ‘0’s
0017FFh
001800h
Unimplemented
Read ‘0’s
001FFFh
002000h
Unimplemented
Unimplemented
Read ‘0’s
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
300009h
CONFIG5L
CONFIG5H
—
CPD
—
—
CPB
—
—
—
—
—
—
—
—
—
CP3
—
CP2
—
CP1
—
CP0
—
30000Ah CONFIG6L
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
30000Bh CONFIG6H WRTD
WRTB
—
WRTC
—
30000Ch CONFIG7L
30000Dh CONFIG7H
—
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
EBTRB
—
Legend: Shaded cells are unimplemented.
2003 Microchip Technology Inc.
DS39599C-page 251
PIC18F2220/2320/4220/4320
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 23-6 through 23-8
illustrate table write and table read protection.
23.5.1
PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The configuration registers may be read and
written with the table read and table write instructions.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 23-6:
TABLE WRITE (WRTn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0001FFh
000200h
TBLPTR = 0002FFh
PC = 0007FEh
WRT0, EBTR0 = 01
TBLWT *
TBLWT *
0007FFh
000800h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
000FFFh
001000h
PC = 0017FEh
0017FFh
001800h
001FFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
DS39599C-page 252
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 23-7:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Program Memory Configuration Bit Settings
Register Values
000000h
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
0001FFh
000200h
TBLPTR = 0002FFh
0007FFh
000800h
TBLRD *
PC = 000FFEh
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
000FFFh
001000h
0017FFh
001800h
WRT3, EBTR3 = 11
001FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 23-8:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
0001FFh
000200h
TBLPTR = 0002FFh
PC = 0007FEh
TBLRD *
0007FFh
000800h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
000FFFh
001000h
0017FFh
001800h
001FFFh
Results: Table reads permitted within Blockn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
2003 Microchip Technology Inc.
DS39599C-page 253
PIC18F2220/2320/4220/4320
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, VSS,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
23.5.2
DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM
regardless of the protection bit settings.
23.9 Low-Voltage ICSP Programming
The LVP bit in Configuration Register 4L
(CONFIG4L<2>) enables Low-Voltage ICSP Program-
ming (LVP). When LVP is enabled, the microcontroller
can be programmed without requiring high voltage
being applied to the MCLR/VPP pin, but the RB5/PGM
pin is then dedicated to controlling Program mode entry
and is not available as a general purpose I/O pin.
23.5.3
CONFIGURATION REGISTER
PROTECTION
The configuration registers can be write-protected. The
WRTC bit controls protection of the configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
LVP is enabled in erased devices.
While programming using LVP, VDD is applied to the
MCLR/VPP pin as in normal execution mode. To enter
Programming mode, VDD is applied to the PGM pin.
23.6 ID Locations
Eight memory locations (200000h-200007h) are desig-
nated as ID locations, where the user can store check-
sum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRDand TBLWTinstructions,
or during program/verify. The ID locations can be read
when the device is code-protected.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: When Low-Voltage Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
23.7
In-Circuit Serial Programming
3: When LVP is enabled, externally pull the
PGM pin to VSS to allow normal program
execution.
PIC18F2X20/4X20 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed (see Table 23-5).
If Low-Voltage ICSP Programming mode will not be
used, the LVP bit can be cleared and RB5/PGM
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP pin). Once LVP has been disabled, only the stan-
dard high-voltage programming is available and must
be used to program the device.
23.8 In-Circuit Debugger
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a block erase is required. If a block erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with VDD of 4.5V to 5.5V.
When the DEBUG bit in configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB®
IDE. When the microcontroller has this feature
enabled, some resources are not available for general
use. Table 23-4 shows which resources are required by
the background debugger.
TABLE 23-5: ICSP/ICD CONNECTIONS
Signal
Pin
Notes
TABLE 23-4: DEBUGGER RESOURCES
PGD
PGC
MCLR
VDD
RB7
RB6
MCLR
VDD
I/O pins:
RB6, RB7
May require isolation from
application circuits
Stack:
2 levels
Program Memory:
Data Memory:
512 bytes
10 bytes
VSS
VSS
PGM
RB5
Pull RB5 low if LVP is enabled
DS39599C-page 254
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The control instructions may use some of the following
operands:
24.0 INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PICmicro instruction sets, while maintain-
ing an easy migration from these PICmicro instruction
sets.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
Most instructions are a single program memory word
(16 bits) but there are three instructions that require two
program memory locations.
• No operand required
(specified by ‘—’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the oper-
ation of the instruction.
All instructions are a single word except for three dou-
ble word instructions. These three instructions were
made double word instructions so that all the required
information is available in these 32 bits. In the second
word, the 4 MSbs are ‘1’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 24-2 lists
byte-oriented, bit-oriented, literal and control opera-
tions. Table 24-1 shows the opcode field descriptions.
The double word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
Two-word branch instructions (if true) would take 3 µs.
2. The destination of the result
(specified by ‘d’)
3. The accessed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
Figure 24-1 shows the general formats that the
instructions can have.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
All examples use the format ‘nnh’ to represent a hexa-
decimal number, where ‘h’ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 24-2,
lists the instructions recognized by the Microchip
Assembler (MPASMTM). Section 24.2 “Instruction
Set” provides a description of each instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register
(specified by ‘b’)
24.1 READ-MODIFY-WRITE OPERATIONS
3. The accessed memory
(specified by ‘a’)
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction or
the destination designator ‘d’. A read operation is per-
formed on a register even if the instruction writes to that
register.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
For example, a “BCF PORTB,1” instruction will read
PORTB, clear bit 1 of the data, then write the result
back to PORTB. The read operation would have the
unintended result that any condition that sets the RBIF
flag would be cleared. The R-M-W operation may also
copy the level of an input pin to its corresponding output
latch.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
2003 Microchip Technology Inc.
DS39599C-page 255
PIC18F2220/2320/4220/4320
TABLE 24-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
BSR
d
Bit address within an 8-bit file register (0 to 7).
Bank Select Register. Used to select the current RAM bank.
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination either the WREG register or the specified register file location.
8-bit register file address (0x00 to 0xFF).
fs
12-bit register file address (0x000 to 0xFFF). This is the source address.
12-bit register file address (0x000 to 0xFFF). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
fd
k
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No Change to register (such as TBLPTR with table reads and writes).
Post-Increment register (such as TBLPTR with table reads and writes).
Post-Decrement register (such as TBLPTR with table reads and writes).
Pre-Increment register (such as TBLPTR with table reads and writes).
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct address for
Call/Branch and Return instructions.
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged.
WREG
x
Working register (accumulator).
Don't care (‘0’ or ‘1’) .
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
TABLAT
TOS
21-bit Table Pointer (points to a Program Memory location).
8-bit Table Latch.
Top-of-Stack.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Global Interrupt Enable bit.
Watchdog Timer.
PCH
PCLATH
PCLATU
GIE
WDT
TO
Time-out bit.
PD
Power-down bit.
C, DC, Z, OV, N
ALU status bits Carry, Digit Carry, Zero, Overflow, Negative.
Optional.
[
]
)
(
Contents.
→
< >
∈
Assigned to.
Register bit field.
In the set of.
italics
User defined term (font is courier).
DS39599C-page 256
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 24-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10
OPCODE
Example Instruction
9
8
7
0
d
a
f (FILE #)
ADDWF MYREG, W, B
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 0x7F
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
2003 Microchip Technology Inc.
DS39599C-page 257
PIC18F2220/2320/4220/4320
TABLE 24-2: PIC18FXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
1
1
1
1
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
f, a
f, a
f, a
Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None
Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None
Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
f, d, a Decrement f
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1
1, 2, 3, 4
1, 2
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
fs, fd Move fs (source) to 1st word
fd (destination) 2nd word
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N 1, 2
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
1, 2
RRNCF
SETF
f, a
Set f
SUBFWB f, d, a Subtract f from WREG with
borrow
0101 01da ffff ffff C, DC, Z, OV, N 1, 2
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N
0101 10da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
f, a Test f, skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da ffff ffff None
4
1, 2
1 (2 or 3) 0110 011a ffff ffff None
1
0001 10da ffff ffff Z, N
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39599C-page 258
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 24-2: PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
Call subroutine 1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C, DC
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS) 1
Relative Call
1
1
1
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
2
1
2
Software device Reset
Return from interrupt enable
s
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
2003 Microchip Technology Inc.
DS39599C-page 259
PIC18F2220/2320/4220/4320
TABLE 24-2: PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSRx 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with
WREG
1
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
1
1
2
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2 (5)
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39599C-page 260
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
24.2 Instruction Set
ADDLW
ADD literal to W
ADDWF
ADD W to f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ADDWF
f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is
placed in W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’,
the BSR is used.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
literal ‘k’
Process
Data
Write to W
Q Cycle Activity:
Q1
ADDLW
0x15
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
=
0x10
After Instruction
W
=
0x25
ADDWF
REG, W
Example:
Before Instruction
W
REG
=
=
0x17
0xC2
After Instruction
W
REG
=
=
0xD9
0xC2
2003 Microchip Technology Inc.
DS39599C-page 261
PIC18F2220/2320/4220/4320
ADDWFC
ADD W and Carry bit to f
ANDLW
AND literal with W
Syntax:
[ label ] ADDWFC
f [,d [,a]]
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
The contents of W are ANDed with
the 8-bit literal ‘k’. The result is
placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data
memory location ‘f’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed in data memory loca-
tion ‘f’. If ‘a’ is ‘0’, the Access Bank
will be selected. If ‘a’ is ‘1’, the BSR
will not be overridden.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
ANDLW
0x5F
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
W
=
0xA3
0x03
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
ADDWFC
REG, W
Example:
Before Instruction
Carry bit =
1
REG
W
=
=
0x02
0x4D
After Instruction
Carry bit =
0
0x02
REG
=
W
=
0x50
DS39599C-page 262
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
ANDWF
AND W with f
BC
Branch if Carry
[ label ] BC
Syntax:
[ label ] ANDWF
f [,d [,a]]
Syntax:
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if carry bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is ‘1’, the BSR will
not be overridden (default).
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
ANDWF
REG, W
Example:
Before Instruction
If No Jump:
Q1
W
REG
=
=
0x17
0xC2
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
After Instruction
W
REG
=
=
0x02
0xC2
HERE
BC JUMP
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
=
=
=
=
1;
PC
address (JUMP)
If Carry
PC
0;
address (HERE+2)
2003 Microchip Technology Inc.
DS39599C-page 263
PIC18F2220/2320/4220/4320
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
[ label ] BCF f,b[,a]
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if negative bit is ’1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
Q1
Q2
Q3
Q4
register ‘f’
Decode
Read literal
‘n’
Process
Data
Write to PC
BCF
FLAG_REG,
7
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction
FLAG_REG = 0xC7
If No Jump:
Q1
After Instruction
Q2
Q3
Q4
FLAG_REG = 0x47
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
=
=
=
=
1;
PC
address (Jump)
If Negative
PC
0;
address (HERE+2)
DS39599C-page 264
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 ≤ n ≤ 127
if carry bit is ’0’
n
Syntax:
[ label ] BNN
-128 ≤ n ≤ 127
n
Operands:
Operation:
Operands:
Operation:
if negative bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the
program will branch.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BNC Jump
HERE
BNN Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
=
=
=
=
0;
If Negative
=
=
=
=
0;
PC
address (Jump)
PC
address (Jump)
If Carry
PC
1;
If Negative
PC
1;
address (HERE+2)
address (HERE+2)
2003 Microchip Technology Inc.
DS39599C-page 265
PIC18F2220/2320/4220/4320
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
-128 ≤ n ≤ 127
n
Syntax:
[ label ] BNZ
-128 ≤ n ≤ 127
if zero bit is ’0’
n
Operands:
Operation:
Operands:
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
Description:
If the Zero bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BNOV Jump
HERE
BNZ Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
=
=
=
=
0;
If Zero
=
=
=
=
0;
PC
address (Jump)
PC
address (Jump)
If Overflow
PC
1;
If Zero
PC
1;
address (HERE+2)
address (HERE+2)
DS39599C-page 266
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
[ label ] BSF f,b[,a]
Operands:
Operation:
Status Affected:
Encoding:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Description:
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG
=
=
0x0A
0x8A
Before Instruction
After Instruction
FLAG_REG
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
2003 Microchip Technology Inc.
DS39599C-page 267
PIC18F2220/2320/4220/4320
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
None
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution is discarded
and a NOPis executed instead, mak-
ing this a two-cycle instruction. If ‘a’
is ‘0’, the Access Bank will be
instruction execution is discarded
and a NOPis executed instead, mak-
ing this a two-cycle instruction. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected
as per the BSR value (default).
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Process Data
No
Decode
Read
Process Data
No
register ‘f’
operation
register ‘f’
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1
Example:
Example:
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
=
=
=
=
0;
If FLAG<1>
=
=
=
=
0;
PC
address (TRUE)
1;
PC
address (FALSE)
1;
If FLAG<1>
PC
If FLAG<1>
PC
address (FALSE)
address (TRUE)
DS39599C-page 268
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
-128 ≤ n ≤ 127
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
if overflow bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
Q1
Q2
Q3
Q4
register ‘f’
Decode
Read literal
‘n’
Process
Data
Write to PC
BTG
PORTC,
4
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction:
PORTC
=
0111 0101 [0x75]
If No Jump:
Q1
After Instruction:
Q2
Q3
Q4
PORTC
=
0110 0101 [0x65]
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BOV JUMP
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
=
=
=
=
1;
PC
address (JUMP)
If Overflow
PC
0;
address (HERE+2)
2003 Microchip Technology Inc.
DS39599C-page 269
PIC18F2220/2320/4220/4320
BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
[ label ] CALL k [,s]
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2 Mbyte
memory range. First, return
Words:
Cycles:
1
address (PC+ 4) is pushed onto the
return stack. If ‘s’ = 1, the W, Status
and BSR registers are also pushed
into their respective shadow regis-
ters, WS, STATUSS and BSRS. If
‘s’ = 0, no update occurs (default).
Then, the 20-bit value ‘k’ is loaded
into PC<20:1>. CALLis a two-cycle
instruction.
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
operation
No
operation
No
operation
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
HERE
BZ Jump
Example:
‘k’<7:0>,
stack
‘k’<19:8>,
Write to PC
Before Instruction
PC
=
address (HERE)
No
No
No
No
operation
operation
operation
operation
After Instruction
If Zero
=
=
=
=
1;
PC
address (Jump)
HERE
CALL THERE,FAST
Example:
If Zero
PC
0;
address (HERE+2)
Before Instruction
PC
=
address (HERE)
After Instruction
PC
=
=
=
=
address (THERE)
TOS
WS
address (HERE + 4)
W
BSR
STATUS
BSRS
STATUSS=
DS39599C-page 270
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRF f [,a]
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
None
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
CLRWDT
Example:
CLRF
FLAG_REG
Example:
Before Instruction
WDT Counter
=
?
Before Instruction
FLAG_REG
=
=
0x5A
0x00
After Instruction
WDT Counter
WDT Postscaler
TO
=
=
=
=
0x00
After Instruction
FLAG_REG
0
1
1
PD
2003 Microchip Technology Inc.
DS39599C-page 271
PIC18F2220/2320/4220/4320
COMF
Complement f
CPFSEQ
Compare f with W, skip if f = W
Syntax:
[ label ] COMF f [,d [,a]]
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
Operation:
(f) → dest
skip if (f) = (W)
(unsigned comparison)
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If ‘f’ = W, then the fetched instruc-
tion is discarded and a NOPis
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
Write to
1(2)
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
REG, W
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x13
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
=
0x13
W
=
0xEC
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
HERE
W
REG
=
=
?
?
After Instruction
If REG
PC
=
=
W;
Address (EQUAL)
If REG
PC
≠
=
W;
Address (NEQUAL)
DS39599C-page 272
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
CPFSGT
Compare f with W, skip if f > W
CPFSLT
Compare f with W, skip if f < W
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (W),
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data
memory location 'f' to the contents
of the W by performing an
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
unsigned subtraction.
If the contents of ‘f’ are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOPis executed instead, making
this a two-cycle instruction. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
If the contents of ‘f’ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ’a’
is ‘1’, the BSR will not be
overridden (default).
Words:
Cycles:
1
1(2)
Words:
Cycles:
1
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
No
No
No
No
Q1
Q2
Q3
Q4
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
HERE
CPFSGT REG
Example:
NGREATER
GREATER
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
Before Instruction
After Instruction
PC
W
=
=
Address (HERE)
?
If REG
PC
If REG
PC
<
=
≥
=
W;
Address (LESS)
W;
Address (NLESS)
After Instruction
If REG
PC
>
=
W;
Address (GREATER)
If REG
PC
≤
=
W;
Address (NGREATER)
2003 Microchip Technology Inc.
DS39599C-page 273
PIC18F2220/2320/4220/4320
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
[ label ] DAW
Syntax:
[ label ] DECF f [,d [,a]]
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> >9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
(W<3:0>) → W<3:0>;
Operation:
(f) – 1 → dest
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> >9] or [C = 1] then
(W<7:4>) + 6 → W<7:4>;
else
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
(W<7:4>) → W<7:4>;
Status Affected:
Encoding:
C, DC
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in
W, resulting from the earlier addi-
tion of two variables (each in
packed BCD format) and produces
a correct packed BCD result. The
carry bit may be set by DAWregard-
less of its setting prior to the DAW
execution.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
Cycles:
1
1
DECF
CNT,
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
CNT
Z
=
=
0x01
0
Decode
Read
register W
Process
Data
Write
W
After Instruction
CNT
Z
=
=
0x00
1
DAW
Example1:
Before Instruction
W
=
0xA5
C
DC
=
=
0
0
After Instruction
W
=
0x05
C
DC
=
=
1
0
Example 2:
Before Instruction
W
=
0xCE
C
DC
=
=
0
0
After Instruction
W
=
0x34
C
DC
=
=
1
0
DS39599C-page 274
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
DECFSZ
Decrement f, skip if 0
DCFSNZ
Decrement f, skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[ label ] DCFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next instruc-
tion which is already fetched is dis-
carded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT
LOOP
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
Example:
Example:
CONTINUE
Before Instruction
Before Instruction
TEMP
PC
=
Address (HERE)
=
?
After Instruction
After Instruction
CNT
=
=
=
≠
=
CNT - 1
0;
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP - 1,
0;
If CNT
PC
Address (CONTINUE)
0;
Address (ZERO)
0;
If CNT
PC
Address (HERE+2)
Address (NZERO)
2003 Microchip Technology Inc.
DS39599C-page 275
PIC18F2220/2320/4220/4320
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Syntax:
[ label ] INCF f [,d [,a]]
Operands:
Operation:
Status Affected:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional
branch anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
Read
register ‘f’
Process
Data
Write to
destination
GOTO THERE
Example:
INCF
CNT,
Example:
After Instruction
Before Instruction
PC
=
Address (THERE)
CNT
=
0xFF
Z
=
=
=
0
?
?
C
DC
After Instruction
CNT
=
=
=
=
0x00
Z
1
1
1
C
DC
DS39599C-page 276
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
INCFSZ
Increment f, skip if 0
INFSNZ
Increment f, skip if not 0
Syntax:
[ label ] INCFSZ f [,d [,a]]
Syntax:
[ label ] INFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
instruction which is already fetched
is discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT
HERE
ZERO
NZERO
INFSNZ REG
Example:
Example:
Before Instruction
Before Instruction
PC
=
Address (HERE)
PC
=
Address (HERE)
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT + 1
REG
If REG
PC
If REG
PC
=
≠
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
0;
Address (ZERO)
0;
Address (NZERO)
2003 Microchip Technology Inc.
DS39599C-page 277
PIC18F2220/2320/4220/4320
IORLW
Inclusive OR literal with W
IORWF
Inclusive OR W with f
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORWF f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .OR. k → W
N, Z
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
Description:
The contents of W are OR’ed with
the eight-bit literal ‘k’. The result is
placed in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If
‘d’ is ‘0’, the result is placed in W. If
‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
IORLW
0x35
Example:
Before Instruction
Q Cycle Activity:
Q1
W
=
0x9A
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
0xBF
IORWF RESULT, W
Example:
Before Instruction
RESULT =
0x13
0x91
W
=
After Instruction
RESULT =
0x13
0x93
W
=
DS39599C-page 278
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ] LFSR f,k
Syntax:
[ label ] MOVF f [,d [,a]]
Operands:
0 ≤ f ≤ 2
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ k ≤ 4095
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into
the file select register pointed to
by ‘f’.
Description:
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed back in register ‘f’
(default). Location ‘f’ can be any-
where in the 256-byte bank. If ‘a’ is
‘0’, the Access Bank will be
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
LFSR 2, 0x3AB
Example:
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write W
FSR2H
FSR2L
=
=
0x03
0xAB
MOVF
REG, W
Example:
Before Instruction
REG
W
=
=
0x22
0xFF
After Instruction
REG
W
=
=
0x22
0x22
2003 Microchip Technology Inc.
DS39599C-page 279
PIC18F2220/2320/4220/4320
MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[ label ] MOVFF fs,fd
Syntax:
[ label ] MOVLB k
0 ≤ k ≤ 255
k → BSR
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Operation:
(fs) → fd
None
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
Description:
The 8-bit literal ‘k’ is loaded into
the Bank Select Register (BSR).
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
1
1
Description:
The contents of source register ‘fs’
are moved to destination register
‘fd’. Location of source ‘fs’ can be
anywhere in the 4096-byte data
space (000h to FFFh) and location
of destination ‘fd’ can also be
anywhere from 000h to FFFh.
Either source or destination can be
W (a useful special situation).
MOVFFis particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write
literal ‘k’ to
BSR
MOVLB
5
Example:
Before Instruction
BSR register
=
=
0x02
0x05
After Instruction
BSR register
The MOVFFinstruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
The MOVFFinstruction should not
be used to modify interrupt settings
while any interrupt is enabled (see
Page 87).
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
MOVFF
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x33
0x11
After Instruction
REG1
REG2
=
=
0x33,
0x33
DS39599C-page 280
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
MOVLW
Move literal to W
MOVWF
Move W to f
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → W
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
None
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
Description:
The eight-bit literal ‘k’ is loaded into
W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
MOVLW
0x5A
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x5A
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
MOVWF
REG
Example:
Before Instruction
W
REG
=
=
0x4F
0xFF
After Instruction
W
REG
=
=
0x4F
0x4F
2003 Microchip Technology Inc.
DS39599C-page 281
PIC18F2220/2320/4220/4320
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
[ label ] MULLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
Description:
An unsigned multiplication is
carried out between the contents
of W and the 8-bit literal ‘k’. The
16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected.
Description:
An unsigned multiplication is
carried out between the contents
of W and the register file location
‘f’. The 16-bit result is stored in
the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If
‘a’= 1, then the bank will be
selected as per the BSR value
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
MULLW
0xC4
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
W
PRODH
PRODL
=
=
=
0xE2
registers
PRODH:
PRODL
?
?
After Instruction
W
=
0xE2
0xAD
0x08
MULWF
REG
Example:
PRODH
PRODL
=
=
Before Instruction
W
=
0xC4
REG
PRODH
PRODL
=
=
=
0xB5
?
?
After Instruction
W
=
0xC4
REG
PRODH
PRODL
=
=
=
0xB5
0x8A
0x94
DS39599C-page 282
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
NEGF
Negate f
NOP
No Operation
Syntax:
[ label ] NEGF f [,a]
Syntax:
[ label ] NOP
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
No operation
None
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Words:
No operation.
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in
the data memory location ‘f’. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value.
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
NEGF
REG, 1
Example:
Before Instruction
REG
=
0011 1010 [0x3A]
1100 0110 [0xC6]
After Instruction
REG
=
2003 Microchip Technology Inc.
DS39599C-page 283
PIC18F2220/2320/4220/4320
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ] POP
None
Syntax:
[ label ] PUSH
None
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(TOS) → bit bucket
None
(PC+2) → TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
Description:
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the previ-
ous value that was pushed onto the
return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Description:
The PC+2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows to implement
a software stack by modifying TOS,
and then push it onto the return
stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
PUSH PC+2
onto return
stack
No
operation
No
operation
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
PUSH
Example:
POP
GOTO
Example:
Before Instruction
NEW
TOS
PC
=
=
0x00345A
0x000124
Before Instruction
TOS
=
=
0x0031A2
0x014332
After Instruction
Stack (1 level down)
PC
=
=
=
0x000126
0x000126
0x00345A
TOS
After Instruction
Stack (1 level down)
TOS
PC
=
=
0x014332
NEW
DS39599C-page 284
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 ≤ n ≤ 1023
(PC) + 2 → TOS,
n
Syntax:
[ label ] RESET
Operands:
Operation:
Operands:
Operation:
None
Reset all registers and flags that
are affected by a MCLR Reset.
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ‘2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n. This
instruction is a two-cycle
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
instruction.
Words:
Cycles:
1
2
RESET
Example:
After Instruction
Registers =
Reset Value
Reset Value
Q Cycle Activity:
Q1
Flags*
=
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
HERE
RCALL
Jump
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
PC
=
Address (Jump)
Address (HERE+2)
TOS =
2003 Microchip Technology Inc.
DS39599C-page 285
PIC18F2220/2320/4220/4320
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ] RETFIE [s]
s ∈ [0,1]
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
pop PC from
stack, Write
to W
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
2
Example:
CALL TABLE ; W contains table
; offset value
Q Cycle Activity:
Q1
Q2
Q3
Q4
; W now has
; table value
Decode
No
operation
No
operation
pop PC from
stack
:
TABLE
ADDWF PCL ; W = offset
Set GIEH or
GIEL
RETLW k0
RETLW k1
:
; Begin table
;
No
operation
No
operation
No
operation
No
operation
:
RETLW kn
; End of table
RETFIE
1
Example:
After Interrupt
Before Instruction
PC
W
=
=
=
=
=
TOS
WS
W
=
0x07
BSR
STATUS
GIE/GIEH, PEIE/GIEL
BSRS
STATUSS
1
After Instruction
W
=
value of kn
DS39599C-page 286
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ] RETURN [s]
s ∈ [0,1]
Syntax:
[ label ] RLCF f [,d [,a]]
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
Operation:
(f<n>) → dest<n+1>,
(f<7>) → C,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
(C) → dest<0>
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of the
shadow registers WS, STATUSS
and BSRS are loaded into their cor-
responding registers, W, Status
and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
Words:
Cycles:
1
2
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
No
operation
Process
Data
pop PC from
stack
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
Read
register ‘f’
Process
Data
Write to
destination
RLCF
REG, W
Example:
RETURN
Example:
Before Instruction
REG
C
=
=
1110 0110
0
After Interrupt
PC = TOS
After Instruction
REG
=
1110 0110
W
C
=
=
1100 1100
1
2003 Microchip Technology Inc.
DS39599C-page 287
PIC18F2220/2320/4220/4320
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f [,d [,a]]
Syntax:
[ label ] RRCF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n+1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n-1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are
rotated one bit to the left. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry Flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
RLNCF
REG
Example:
Before Instruction
RRCF
REG, W
Example:
REG
=
1010 1011
0101 0111
After Instruction
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
1110 0110
W
C
=
=
0111 0011
0
DS39599C-page 288
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ] RRNCF f [,d [,a]]
Syntax:
[ label ] SETF f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n-1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified regis-
ter are set to FFh. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed back in reg-
ister ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
SETF
REG
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
=
0x5A
0xFF
Q2
Q3
Q4
After Instruction
REG
Decode
Read
register ‘f’
Process
Data
Write to
destination
RRNCF
REG, 1, 0
Example 1:
Before Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, W
After Instruction
REG
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
2003 Microchip Technology Inc.
DS39599C-page 289
PIC18F2220/2320/4220/4320
SLEEP
Enter SLEEP mode
SUBFWB
Subtract f from W with borrow
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBFWB f [,d [,a]]
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored in register ‘d’ (default). If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Description:
The power-down status bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SLEEP
Example:
Before Instruction
SUBFWB REG
Example 1:
TO
PD
=
?
=
?
Before Instruction
After Instruction
REG
W
C
=
=
=
0x03
0x02
0x01
TO
PD
=
=
1 †
0
After Instruction
† If WDT causes wake-up, this bit is cleared.
REG
=
0xFF
0x02
W
=
C
Z
N
=
=
=
0x00
0x00
0x01 ; result is negative
SUBFWB
REG, 0, 0
Example 2:
Before Instruction
REG
=
2
W
C
=
=
5
1
After Instruction
REG
W
=
=
2
3
C
Z
N
=
=
=
1
0
0
; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
=
1
W
C
=
=
2
0
After Instruction
REG
W
=
=
0
2
C
Z
N
=
=
=
1
1
0
; result is zero
DS39599C-page 290
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
SUBLW
Subtract W from literal
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
[ label ] SUBWF f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed in
W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is
‘1’, the result is stored back in
register ‘f’ (default). If = ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
SUBLW 0x02
Example 1:
Words:
Cycles:
1
1
Before Instruction
W
C
=
=
1
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
=
1
C
=
=
=
1
0
0
; result is positive
Z
SUBWF REG
Example 1:
N
SUBLW 0x02
Example 2:
Before Instruction
REG
W
C
=
=
=
3
2
?
Before Instruction
W
C
=
=
2
?
After Instruction
After Instruction
REG
W
=
=
1
2
W
=
0
C
Z
N
=
=
=
1
0
0
; result is positive
C
Z
N
=
=
=
1
1
0
; result is zero
SUBWF REG, W
Example 2:
SUBLW 0x02
Example 3:
Before Instruction
Before Instruction
REG
=
2
2
?
W
C
=
=
3
?
W
C
=
=
After Instruction
After Instruction
W
=
FF ; (2’s complement)
REG
=
2
0
C
Z
N
=
=
=
0
0
1
; result is negative
W
=
C
Z
N
=
=
=
1
1
0
; result is zero
SUBWF REG
Example 3:
Before Instruction
REG
=
0x01
W
C
=
=
0x02
?
After Instruction
REG
W
=
=
0xFFh ;(2’s complement)
0x02
C
Z
N
=
=
=
0x00 ; result is negative
0x00
0x01
2003 Microchip Technology Inc.
DS39599C-page 291
PIC18F2220/2320/4220/4320
SUBWFB
Syntax:
Subtract W from f with Borrow
SUBWFB REG, 1, 0
Example 1:
Before Instruction
[ label ] SUBWFB f [,d [,a]]
REG
W
C
=
=
=
0x19
0x0D
0x01
(0001 1001)
(0000 1101)
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
After Instruction
REG
W
C
Z
N
=
=
=
=
=
0x0C
0x0D
(0000 1011)
(0000 1101)
Operation:
(f) – (W) – (C) → dest
Status Affected: N, OV, C, DC, Z
0x01
0x00
0x00
Encoding:
0101
10da
ffff
ffff
; result is positive
Description:
Subtract W and the carry flag (bor-
row) from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
SUBWFB REG, 0, 0
Example 2:
Before Instruction
REG
W
C
=
=
=
0x1B
0x1A
0x00
(0001 1011)
(0001 1010)
After Instruction
REG
W
C
Z
N
=
=
=
=
=
0x1B
0x00
(0001 1011)
0x01
0x01
0x00
; result is zero
Words:
Cycles:
1
1
SUBWFB REG, 1, 0
Example 3:
Before Instruction
Q Cycle Activity:
Q1
REG
W
C
=
=
=
0x03
0x0E
0x01
(0000 0011)
(0000 1101)
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
REG
=
0xF5
0x0E
(1111 0100)
; [2’s comp]
(0000 1101)
W
=
C
Z
N
=
=
=
0x00
0x00
0x01
; result is negative
DS39599C-page 292
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
SWAPF
Swap f
Syntax:
[ label ] SWAPF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
None
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of reg-
ister ‘f’ are exchanged. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’,
the result is placed in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SWAPF
REG
Example:
Before Instruction
REG
=
0x53
0x35
After Instruction
REG
=
2003 Microchip Technology Inc.
DS39599C-page 293
PIC18F2220/2320/4220/4320
TBLRD
Table Read
TBLRD
Table Read (cont’d)
TBLRD *+ ;
Syntax:
[ label ] TBLRD ( *; *+; *-; +*)
Example1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) +1 → TBLPTR;
if TBLRD *-,
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
TBLRD +* ;
Example2:
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) -1 → TBLPTR;
if TBLRD +*,
(TBLPTR) +1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT;
Before Instruction
TABLAT
TBLPTR
=
=
=
=
0xAA
0x01A357
0x12
MEMORY(0x01A357)
MEMORY(0x01A358)
0x34
After Instruction
Status Affected:None
TABLAT
TBLPTR
=
=
0x34
0x01A358
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
Description:
This instruction is used to read the
contents of Program Memory (P.M.). To
address the program memory, a pointer
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 Mbyte address range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRDinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No operation
No
No operation
operation (Read Program operation (Write TABLAT)
Memory)
DS39599C-page 294
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TBLWT
Table Write
TBLWT Table Write (Continued)
Syntax:
[ label ]
TBLWT ( *; *+; *-; +*)
Words: 1
Cycles: 2
Q Cycle Activity:
Q1
Operands:
Operation:
None
if TBLWT*,
(TABLAT) → Holding Register;
TBLPTR - No Change;
if TBLWT*+,
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
(TABLAT) → Holding Register;
(TBLPTR) +1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) -1 → TBLPTR;
if TBLWT+*,
No
operation
No
operation
(Read
No
operation
No
operation
(Write to
Holding
Register )
TABLAT)
(TBLPTR) +1 → TBLPTR;
(TABLAT) → Holding Register;
Example1:
TBLWT *+;
Status Affected: None
Before Instruction
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
TABLAT
TBLPTR
HOLDING REGISTER
(0x00A356)
=
=
0x55
0x00A356
=
0xFF
After Instructions (table write completion)
TABLAT
=
0x55
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the 8
holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program
Memory (P.M.). (Refer to Section 6.0
“Flash Program Memory” for
additional details on programming
Flash memory.)
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 MBtye address
range. The LSb of the TBLPTR selects
which byte of the program memory
location to access.
TBLPTR
=
0x00A357
HOLDING REGISTER
(0x00A356)
=
0x55
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389A
=
=
0xFF
0xFF
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389B
=
=
0xFF
0x34
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
2003 Microchip Technology Inc.
DS39599C-page 295
PIC18F2220/2320/4220/4320
TSTFSZ
Test f, skip if 0
XORLW
Exclusive OR literal with W
Syntax:
[ label ] TSTFSZ f [,a]
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
None
Status Affected:
Encoding:
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
Description:
The contents of W are XOR’ed
with the 8-bit literal ‘k’. The result
is placed in W.
Description:
If ‘f’ = 0, the next instruction,
fetched during the current instruc-
tion execution is discarded and a
NOPis executed, making this a two-
cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1(2)
Example:
XORLW 0xAF
= 0xB5
Note: 3 cycles if skip and followed
by a 2-word instruction.
Before Instruction
W
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x1A
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ CNT
:
Example:
:
Before Instruction
PC = Address (HERE)
After Instruction
If CNT
=
=
≠
=
0x00,
PC
Address (ZERO)
0x00,
If CNT
PC
Address (NZERO)
DS39599C-page 296
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W
with register ‘f’. If ‘d’ is ‘0’, the result
is stored in W. If ‘d’ is ‘1’, the result
is stored back in the register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
XORWF
REG
Example:
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
2003 Microchip Technology Inc.
DS39599C-page 297
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 298
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
25.1 MPLAB Integrated Development
Environment Software
25.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• An interface to debugging tools
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
• Customizable data windows with direct edit of
contents
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
• High-level source code debugging
• Mouse over variable inspection
• Extensive on-line help
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
- MPLAB ICD 2
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
• Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
• Debug using:
- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
25.2 MPASM Assembler
®
- KEELOQ
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
- PICDEM MSC
- microID®
- CAN
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol ref-
erence, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
- PowerSmart®
- Analog
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
2003 Microchip Technology Inc.
DS39599C-page299
PIC18F2220/2320/4220/4320
25.3 MPLAB C17 and MPLAB C18
C Compilers
25.6 MPLAB ASM30 Assembler, Linker
and Librarian
The MPLAB C17 and MPLAB C18 Code Development
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Systems are complete ANSI
C
compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
25.4 MPLINK Object Linker/
MPLIB Object Librarian
• Rich directive set
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
• Flexible macro language
• MPLAB IDE compatibility
25.7 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execu-
tion can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.5 MPLAB C30 C Compiler
25.8 MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command-
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabili-
ties and afford fine control of the compiler code
generator.
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping and math functions (trigonometric, exponential
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
DS39599C-page 300
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
25.9 MPLAB ICE 2000
High-Performance Universal
In-Circuit Emulator
25.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM
)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB Inte-
grated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
25.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
25.10 MPLAB ICE 4000
High-Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
25.13 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
2003 Microchip Technology Inc.
DS39599C-page301
PIC18F2220/2320/4220/4320
25.14 PICDEM 1 PICmicro
Demonstration Board
25.17 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device program-
mer or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional appli-
cation components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
25.18 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320 fam-
ily of microcontrollers. PICDEM 4 is intended to show-
case the many features of these low pin count parts,
including LIN and Motor Control using ECCP. Special
provisions are made for low-power operation with the
supercapacitor circuit and jumpers allow on-board
hardware to be disabled to eliminate current draw in
this mode. Included on the demo board are provisions
for Crystal, RC or Canned Oscillator modes, a five volt
regulator for use with a nine volt wall adapter or battery,
DB-9 RS-232 interface, ICD connector for program-
ming via ICSP and development with MPLAB ICD 2,
2x16 liquid crystal display, PCB footprints for H-Bridge
motor driver, LIN transceiver and EEPROM. Also
included are: header for expansion, eight LEDs, four
potentiometers, three push buttons and a prototyping
area. Included with the kit is a PIC16F627A and a
PIC18F1320. Tutorial firmware is included along with
the User’s Guide.
25.15 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
25.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development pro-
grammer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
25.16 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary hardware and software is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
DS39599C-page 302
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
25.20 PICDEM 18R PIC18C601/801
Demonstration Board
25.23 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
25.24 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
25.21 PICDEM LIN PIC16C43X
Demonstration Board
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
on-board LIN transceivers.
A PIC16F874 Flash
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN bus communication.
• microID development and rfLabTM development
software
25.22 PICkitTM 1 Flash Starter Kit
• SEEVAL® designer kit for memory evaluation and
endurance calculations
A complete “development system in a box”, the PICkit
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the user's guide (on
CD ROM), PICkit 1 tutorial software and code for vari-
ous applications. Also included are MPLAB® IDE (Inte-
grated Development Environment) software, software
and hardware “Tips 'n Tricks for 8-pin Flash PIC®
Microcontrollers” Handbook and a USB Interface
Cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
• PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.
2003 Microchip Technology Inc.
DS39599C-page303
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 304
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to VSS............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2003 Microchip Technology Inc.
DS39599C-page 305
PIC18F2220/2320/4220/4320
FIGURE 26-1:
PIC18F2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F2X20/4X20
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 26-2:
PIC18F2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F2X20/4X20
4.2V
3.5V
3.0V
2.5V
2.0V
25 MHz
Frequency
DS39599C-page 306
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-3:
PIC18LF2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18LF2X20/4X20
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
2003 Microchip Technology Inc.
DS39599C-page 307
PIC18F2220/2320/4220/4320
26.1 DC Characteristics: Supply Voltage
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Symbol
Characteristic
Supply Voltage
Min
Typ
Max Units
Conditions
VDD
D001
PIC18LF2X20/4X20 2.0
PIC18F2X20/4X20 4.2
—
—
—
5.5
5.5
—
V
V
V
HS, XT, RC and LP Osc mode
D002
D003
VDR
RAM Data Retention
Voltage
1.5
(1)
VPOR
VDD Start Voltage
to ensure internal
—
—
—
0.7
—
V
See section on Power-on Reset for details
Power-on Reset signal
D004
SVDD
VBOR
VDD Rise Rate
0.05
V/ms See section on Power-on Reset for details
to ensure internal
Power-on Reset signal
Brown-out Reset Voltage
PIC18LF2X20/4X20 Industrial Low Voltage
D005
BORV1:BORV0 = 11
BORV1:BORV0 = 10
BORV1:BORV0 = 01
BORV1:BORV0 = 00
NA
—
NA
V
V
V
V
Reserved
2.50
3.88
4.18
2.72 2.94
4.22 4.56
4.54 4.90
D005
PIC18F2X20/4X20 Industrial
BORV1:BORV0 = 1x
NA
—
NA
V
V
V
Not in operating voltage range of device
Not in operating voltage range of device
BORV1:BORV0 = 01
BORV1:BORV0 = 00
3.88
4.18
4.22 4.56
4.54 4.90
D005E
PIC18F2X20/4X20 Extended
BORV1:BORV0 = 1x
NA
—
NA
V
V
V
BORV1:BORV0 = 01
BORV1:BORV0 = 00
3.71
4.00
4.22 4.73
4.54 5.08
Legend:
Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
DS39599C-page 308
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(1)
Power-down Current (IPD)
PIC18LF2X20/4X20 0.1
0.5
0.5
1.7
0.5
0.5
1.7
2.0
2.0
6.5
50
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V,
(Sleep mode)
0.1
0.2
PIC18LF2X20/4X20 0.1
VDD = 3.0V,
(Sleep mode)
0.1
+25°C
+85°C
-40°C
0.3
All devices 0.1
0.1
0.4
+25°C
+85°C
+125°C
VDD = 5.0V,
(Sleep mode)
Extended devices 11.2
(2,3)
Supply Current (IDD)
PIC18LF2X20/4X20
11
13
14
34
28
25
77
62
53
50
25
25
25
40
40
40
80
80
80
80
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
PIC18LF2X20/4X20
All devices
FOSC = 31 kHz
(RC_RUN mode,
+25°C
+85°C
-40°C
internal oscillator source)
+25°C
+85°C
+125°C
VDD = 5.0V
Extended devices
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 309
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF2X20/4X20 100
220
220
220
330
330
330
550
550
550
650
600
600
600
900
900
900
1.8
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
-40°C
110
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
120
PIC18LF2X20/4X20 180
FOSC = 1 MHz
(RC_RUN mode,
180
170
internal oscillator source)
All devices 340
330
VDD = 5.0V
310
Extended devices 410
PIC18LF2X20/4X20 350
360
VDD = 2.0V
VDD = 3.0V
370
PIC18LF2X20/4X20 580
FOSC = 4 MHz
(RC_RUN mode,
580
560
internal oscillator source)
All devices 1.1
1.1
1.0
1.8
+25°C
+85°C
+125°C
VDD = 5.0V
1.8
Extended devices 1.2
1.8
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599C-page 310
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF2X20/4X20 4.7
8
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
4.6
8
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
VDD = 2.0V
VDD = 3.0V
5.1
11
PIC18LF2X20/4X20 6.9
11
FOSC = 31 kHz
(RC_IDLE mode,
6.3
6.8
11
15
internal oscillator source)
All devices
12
10
10
25
49
52
56
73
77
77
16
16
VDD = 5.0V
22
Extended devices
75
PIC18LF2X20/4X20
150
150
150
180
180
180
300
300
300
435
VDD = 2.0V
VDD = 3.0V
PIC18LF2X20/4X20
FOSC = 1 MHz
(RC_IDLE mode,
internal oscillator source)
All devices 130
130
130
VDD = 5.0V
Extended devices 350
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 311
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF2X20/4X20 140
275
275
275
375
375
375
800
800
800
800
250
250
250
350
350
350
1.0
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
-40°C
140
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
150
PIC18LF2X20/4X20 220
FOSC = 4 MHz
(RC_IDLE mode,
220
210
internal oscillator source)
All devices 390
400
VDD = 5.0V
380
Extended devices 410
PIC18LF2X20/4X20 150
150
VDD = 2.0V
VDD = 3.0V
160
PIC18LF2X20/4X20 340
FOSC = 1 MHZ
(PRI_RUN,
300
280
All devices 0.72
0.63
EC oscillator)
1.0
+25°C
+85°C
+125°C
VDD = 5.0V
0.57
1.0
Extended devices 0.53
1.0
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599C-page 312
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF2X20/4X20 440
600
600
600
1.0
1.0
1.0
2.0
2.0
2.0
2.0
9.0
µA
µA
-40°C
450
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
460
µA
PIC18LF2X20/4X20 0.80
mA
mA
mA
mA
mA
mA
mA
mA
FOSC = 4 MHz
(PRI_RUN,
0.78
+25°C
+85°C
-40°C
0.77
All devices 1.6
1.5
EC oscillator)
+25°C
+85°C
+125°C
+125°C
VDD = 5.0V
1.5
Extended devices 1.5
Extended devices 6.3
FOSC = 25 MHZ
(PRI_RUN,
EC oscillator)
VDD = 4.2V
VDD = 5.0V
7.9
10.0
mA
+125°C
All devices 9.5
12
12
12
15
15
15
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
9.7
VDD = 4.2V
VDD = 5.0V
FOSC = 40 MHZ
(PRI_RUN,
EC oscillator)
9.9
All devices 11.9
12.1
12.3
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 313
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF2X20/4X20
37
37
38
58
59
60
50
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
-40°C
50
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
60
PIC18LF2X20/4X20
80
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
80
+25°C
+85°C
-40°C
100
180
180
180
300
180
180
180
280
280
280
525
525
525
800
3.0
All devices 110
110
+25°C
+85°C
+125°C
-40°C
VDD = 5.0V
110
Extended devices 125
PIC18LF2X20/4X20 140
140
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
140
PIC18LF2X20/4X20 220
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
230
+25°C
+85°C
-40°C
230
All devices 410
420
+25°C
+85°C
+125°C
+125°C
VDD = 5.0V
430
Extended devices 450
Extended devices 2.2
FOSC = 25 MHZ
(PRI_IDLE,
EC oscillator)
VDD = 4.2V
VDD = 5.0V
2.7
3.5
mA
+125°C
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599C-page 314
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
All devices 3.1
4.1
4.1
4.1
5.1
5.1
5.1
15
15
18
30
30
35
80
80
85
9
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
3.2
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 4.2 V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
3.3
All devices 4.4
4.6
4.6
PIC18LF2X20/4X20
9
10
13
22
21
20
50
50
45
(4)
PIC18LF2X20/4X20
All devices
FOSC = 32 kHz
(SEC_RUN mode,
Timer1 as clock)
PIC18LF2X20/4X20 5.1
5.8
9
7.9
11
12
12
14
20
20
25
(4)
PIC18LF2X20/4X20 7.9
FOSC = 32 kHz
8.9
(SEC_IDLE mode,
Timer1 as clock)
10.5
All devices
13
16
18
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 315
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
Module Differential Currents (∆IWDT, ∆IBOR, ∆ILVD, ∆IOSCB, ∆IAD)
D022
(∆IWDT)
Watchdog Timer 1.5
3.8
3.8
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
+25°C
2.2
VDD = 2.0V
VDD = 3.0V
2.7
4.0
+85°C
2.3
4.6
-40°C
2.7
4.6
+25°C
3.1
4.8
+85°C
3.0
10.0
10.0
10.0
13.0
35.0
45.0
50.0
25.0
35.0
45.0
50.0
-40°C
3.3
3.9
+25°C
VDD = 5.0V
+85°C
Extended devices only 4.0
+125°C
-40°C to +85°C
-40°C to +85°C
D022A
Brown-out Reset
17
47
48
14
18
21
24
VDD = 3.0V
VDD = 5.0V
(∆IBOR)
Extended devices only
µA -40°C to +125°C
D022B
Low-Voltage Detect
µA
µA
µA
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 2.0V
VDD = 3.0V
(∆ILVD)
VDD = 5.0V
Extended devices only
µA -40°C to +125°C
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599C-page 316
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
D025
Timer1 Oscillator 2.1
2.2
2.2
2.2
3.8
3.8
3.8
6.0
6.0
7.0
2.0
2.0
2.0
8.0
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
(4)
(4)
(4)
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
32 kHz on Timer1
32 kHz on Timer1
32 kHz on Timer1
(∆IOSCB)
1.8
+25°C
+85°C
2.1
2.2
-40°C
2.6
+25°C
2.9
+85°C
3.0
-40°C
3.2
+25°C
3.4
+85°C
D026
(∆IAD)
A/D Converter 1.0
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 5.0V
1.0
1.0
A/D on, not converting
Extended devices only 1.0
µA -40°C to +125°C
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2003 Microchip Technology Inc.
DS39599C-page 317
PIC18F2220/2320/4220/4320
26.3 DC Characteristics: PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
VIH
IIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
VSS
—
0.15 VDD
0.8
V
V
VDD < 4.5V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
0.2 VDD
0.3 VDD
V
V
D032
MCLR
VSS
VSS
0.2 VDD
0.2 VDD
V
V
D032A
OSC1 and T1OSI
LP, XT, HS, HSPLL
modes(1)
EC mode(1)
D033
OSC1
VSS
0.2 VDD
V
Input High Voltage
I/O ports:
D040
D040A
D041
with TTL buffer
0.25 VDD + 0.8V
2.0
VDD
VDD
V
V
VDD < 4.5V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
0.8 VDD
0.7 VDD
VDD
VDD
V
V
D042
MCLR
0.8 VDD
1.6
VDD
VDD
V
V
D042A
OSC1 and T1OSI
LP, XT, HS, HSPLL
modes(1)
EC mode(1)
D043
D060
OSC1
0.8 VDD
—
VDD
0.2
V
Input Leakage Current(2,3)
I/O ports
µA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
D063
MCLR, RA4
—
—
1.0
1.0
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070
IPURB
50
400
µA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
DS39599C-page 318
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.3 DC Characteristics: PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
VOH
VOD
Output Low Voltage
I/O ports
D080
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D080A
D083
OSC2/CLKO
(RC mode)
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
D083A
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
Output High Voltage(3)
D090
I/O ports
VDD – 0.7
VDD – 0.7
VDD – 0.7
VDD – 0.7
—
—
—
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D090A
D092
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
OSC2/CLKO
(RC mode)
—
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D092A
D150
—
Open-Drain High Voltage
8.5
RA4 pin
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin
15
pF In XT, HS and LP modes
when external clock is
used to drive OSC1
—
D101
D102
CIO
CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC Timing
Specifications
pF In I2C mode
SCL, SDA
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
2003 Microchip Technology Inc.
DS39599C-page 319
PIC18F2220/2320/4220/4320
TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
DC Characteristics
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Internal Program Memory
Programming Specifications
D110
D112
D113
VPP
IPP
Voltage on MCLR/VPP pin
Current into MCLR/VPP pin
9.00
—
—
—
—
13.25
300
V
(Note 2)
µA
mA
IDDP
Supply Current during
Programming
—
1.0
Data EEPROM Memory
D120
ED
Byte Endurance
100K
10K
1M
100K
—
—
E/W -40°C to +85°C
E/W -40°C to +125°C
D121 VDRW VDD for Read/Write
VMIN
—
5.5
V
Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time
D123 TRETD Characteristic Retention
—
4
—
—
ms
40
—
Year Provided no other
specifications are violated
D124
TREF
Number of Total Erase/Write
Cycles before Refresh(1)
1M
100K
10M
1M
—
—
E/W -40°C to +85°C
E/W -40°C to +125°C
Program Flash Memory
D130
D131
D132
EP
Cell Endurance
10K
1K
100K
10K
—
—
E/W -40°C to +85°C
E/W -40°C to +125°C
VPR
VDD for Read
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
VIE
VDD for Block Erase
4.5
4.5
—
—
5.5
5.5
V
V
Using ICSP port
Using ICSP port
D132A VIW
VDD for Externally Timed Erase
or Write
D132B VPEW VDD for Self-timed Write
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D133
TIE
ICSP Block Erase Cycle Time
—
1
4
—
—
ms VDD > 4.5V
ms VDD > 4.5V
D133A TIW
ICSP Erase or Write Cycle Time
(externally timed)
—
D133A TIW
Self-timed Write Cycle Time
—
2
—
—
ms
D134 TRETD Characteristic Retention
40
—
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
2: Required only if Low-Voltage Programming is disabled.
DS39599C-page 320
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
D300
VIOFF
—
0
± 5.0
—
± 10
VDD – 1.5
—
mV
V
D301
D302
VICM
Input Common Mode Voltage*
Common Mode Rejection Ratio*
Response Time(1)*
CMRR
TRESP
55
—
—
dB
300
300A
150
400
600
ns
ns
PIC18FXX20
PIC18LFXX20
301
TMC2OV Comparator Mode Change to
Output Valid*
—
—
10
µs
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 26-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.
Param
No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
—
VDD/32
LSb
D311
VRAA
Absolute Accuracy
—
—
—
—
1/2
1/2
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
D312
310
VRUR
TSET
Unit Resistor Value (R)*
Settling Time(1)*
—
—
2k
—
—
Ω
10
µs
*
These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from ‘0000’ to ‘1111’.
2003 Microchip Technology Inc.
DS39599C-page 321
PIC18F2220/2320/4220/4320
FIGURE 26-4:
LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 26-4: LOW-VOLTAGE DETECT CHARACTERISTICS
PIC18LF2220/2320/4220/4320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2220/2320/4220/4320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Symbol
No.
Characteristic
Min
Typ†
Max
Units
Conditions
D420
LVD Voltage on VDD Transition High to Low
PIC18LF2X20/4X20 LVDL<3:0> = 0000
LVDL<3:0> = 0001
Industrial
N/A
N/A
N/A
N/A
N/A
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Reserved
Reserved
N/A
LVDL<3:0> = 0010
2.15
2.26
2.45
2.55
2.77
2.87
3.07
3.36
3.57
3.67
3.87
4.07
4.28
4.60
2.37
2.58
2.68
2.91
3.01
3.22
3.53
3.75
3.85
4.07
4.28
4.49
4.82
LVDL<3:0> = 0011
2.33
LVDL<3:0> = 0100
2.43
LVDL<3:0> = 0101
2.63
LVDL<3:0> = 0110
2.73
LVDL<3:0> = 0111
2.91
LVDL<3:0> = 1000
3.20
LVDL<3:0> = 1001
3.39
LVDL<3:0> = 1010
3.49
LVDL<3:0> = 1011
3.68
LVDL<3:0> = 1100
3.87
LVDL<3:0> = 1101
4.06
LVDL<3:0> = 1110
4.37
D420
LVD Voltage on VDD Transition High to Low
PIC18F2X20/4X20 LVDL<3:0> = 1011
LVDL<3:0> = 1100
Industrial
3.68
3.87
4.07
4.28
4.60
4.07
4.28
4.49
4.82
V
V
V
V
3.87
LVDL<3:0> = 1101
4.06
LVDL<3:0> = 1110
4.37
D420E
Legend:
LVD Voltage on VDD Transition High to Low
PIC18F2X20/4X20 LVDL<3:0> = 1011
LVDL<3:0> = 1100
Extended
3.48
3.87
4.07
4.28
4.60
4.25
4.48
4.70
5.05
V
V
V
V
3.66
LVDL<3:0> = 1101
3.85
LVDL<3:0> = 1110
4.14
Shading of rows is to assist in readability of the table.
†
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
DS39599C-page 322
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.4 AC (Timing) Characteristics
26.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (High-impedance)
Low
Valid
High-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
2003 Microchip Technology Inc.
DS39599C-page 323
PIC18F2220/2320/4220/4320
26.4.2
TIMING CONDITIONS
Note:
Because of space limitations, the generic
terms “PIC18FXX20” and “PIC18LFXX20”
are used throughout this section to refer
to the PIC18F2220/2320/4220/4320 and
PIC18LF2220/2320/4220/4320 families of
devices specifically and only those
devices.
The temperature and voltages specified in Table 26-5
apply to all timing specifications unless otherwise
noted. Figure 26-5 specifies the load conditions for the
timing specifications.
TABLE 26-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 26.1 and
Section 26.3.
LF parts operate up to industrial temperatures only.
FIGURE 26-5:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
DS39599C-page 324
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-6:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
CLKO
3
4
3
2
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
DC
DC
DC
0.1
4
40
25
4
MHz EC, ECIO (industrial)
MHz EC, ECIO (extended)
MHz RC osc
Oscillator Frequency(1)
1
MHz XT osc
25
10
6.25
33
—
—
—
—
MHz HS osc
4
MHz HS + PLL osc (industrial)
MHz HS + PLL osc (extended)
4
5
kHz
ns
LP Osc mode
EC, ECIO (industrial)
EC, ECIO (extended)
RC osc
1
TOSC
External CLKI Period(1)
Oscillator Period(1)
25
40
250
1
ns
ns
µs
XT osc
40
100
250
250
ns
ns
HS osc
HS + PLL osc (industrial)
160
30
250
—
ns
HS + PLL osc (extended)
LP osc
µs
2
3
TCY
Instruction Cycle Time(1)
100
160
—
—
ns
ns
TCY = 4/FOSC (industrial)
TCY = 4/FOSC (extended)
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
30
2.5
10
—
—
—
ns
µs
ns
ns
ns
ns
XT osc
LP osc
HS osc
XT osc
LP osc
HS osc
—
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
20
50
7.5
—
—
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2003 Microchip Technology Inc.
DS39599C-page 325
PIC18F2220/2320/4220/4320
TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
F10
FOSC Oscillator Frequency Range
4
—
—
—
—
10
40
2
MHz HS mode only
F11
F12
F13
FSYS On-Chip VCO System Frequency
16
—
-2
MHz HS mode only
tPLL
PLL Start-up Time (Lock Time)
ms
%
∆CLK CLKO Stability (Jitter)
+2
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 26-8: INTERNAL RC ACCURACY: PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial, Extended)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Min
Typ
Max
Units
Conditions
(1)
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz
F14
PIC18LF2220/2320/4220/4320
PIC18F2220/2320/4220/4320
-2
-5
+/-1
—
2
5
%
%
%
%
%
%
+25°C
VDD = 2.7-3.3V
F15
F16
F17
F18
F19
-10°C to +85°C VDD = 2.7-3.3V
-40°C to +85°C VDD = 2.7-3.3V
-10
-2
—
10
2
+/-1
—
+25°C
VDD = 4.5-5.5V
-5
5
-10°C to +85°C VDD = 4.5-5.5V
-40°C to +85°C VDD = 4.5-5.5V
-10
—
10
(2)
INTRC Accuracy @ Freq = 31 kHz
PIC18LF2220/2320/4220/4320 26.562
PIC18F2220/2320/4220/4320 26.562
F20
—
—
35.938
35.938
kHz -40°C to +85°C VDD = 2.7-3.3V
kHz -40°C to +85°C VDD = 4.5-5.5V
F21
Legend:
Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTRC frequency after calibration.
3: Change of INTRC frequency as VDD changes.
DS39599C-page 326
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-7:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
12
19
18
14
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 26-5 for load conditions.
Note:
TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TOSH2CKL OSC1 ↑ to CLKO ↓
TOSH2CKH OSC1 ↑ to CLKO ↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns
ns
ns
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
11
12
13
14
15
16
17
18
18A
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
TCKL2IOV CLKO ↓ to Port Out Valid
0.5 TCY + 20 ns
TIOV2CKH Port In Valid before CLKO ↑
TCKH2IOI Port In Hold after CLKO ↑
0.25 TCY + 25
—
—
ns
ns
ns
ns
ns
0
TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid
TOSH2IOI OSC1↑ (Q2 cycle) to Port PIC18FXX20
—
150
—
100
200
Input Invalid
(I/O in hold time)
PIC18LFXX20
—
19
TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time)
0
—
10
—
10
—
—
25
60
25
60
ns
ns
ns
ns
ns
20
TIOR
Port Output Rise Time
Port Output Fall Time
PIC18FXX20
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
—
—
—
—
20A
21
TIOF
21A
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
2003 Microchip Technology Inc.
DS39599C-page 327
PIC18F2220/2320/4220/4320
FIGURE 26-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 26-5 for load conditions.
FIGURE 26-9:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
TOST
MCLR Pulse Width (low)
2
3.48
—
4.00
—
—
4.71
µs
ms
—
31
32
33
34
Watchdog Timer Time-out Period (no postscaler)
Oscillation Start-up Timer Period
Power-up Timer Period
1024 TOSC
57.0
1024 TOSC
77.2
TOSC = OSC1 period
TPWRT
65.5
2
ms
µs
TIOZ
I/O High-Impedance from MCLR Low or
Watchdog Timer Reset
—
—
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
µs
µs
VDD ≤ BVDD (see D005)
VDD ≤ VLVD
TIVRST
Time for Internal Reference Voltage to become
stable
20
50
37
TLVD
Low-Voltage Detect Pulse Width
200
—
—
µs
DS39599C-page 328
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
TT0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or TCY + 40
N
ns N = prescale
value
(1, 2, 4,..., 256)
45
46
TT1H
TT1L
T1CKI
High Time
Synchronous, no prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Synchronous,
with prescaler
PIC18FXX20
10
PIC18LFXX20
25
Asynchronous PIC18FXX20
PIC18LFXX20
30
50
T1CKI
Low Time
Synchronous, no prescaler
0.5 TCY + 5
Synchronous,
with prescaler
PIC18FXX20
10
25
30
50
PIC18LFXX20
Asynchronous PIC18FXX20
PIC18LFXX20
47
48
TT1P
FT1
T1CKI
Input
Period
Synchronous
Greater of:
20 ns or TCY + 40
N
ns N = prescale
value
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T1CKI Oscillator Input Frequency Range
TCKE2TMRI Delay from External T1CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
2003 Microchip Technology Inc.
DS39599C-page 329
PIC18F2220/2320/4220/4320
FIGURE 26-11:
CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Refer to Figure 26-5 for load conditions.
Note:
TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
50
TCCL
CCPx Input Low
Time
No prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
With
PIC18FXX20
10
prescaler
PIC18LFXX20
20
51
TCCH
CCPx Input High No prescaler
Time
0.5 TCY + 20
With
PIC18FXX20
10
20
prescaler
PIC18LFXX20
52
53
TCCP
TCCR
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1,4 or 16)
CCPx Output Fall Time
CCPx Output Fall Time
PIC18FXX20
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
—
—
—
—
25
45
25
45
ns
ns
ns
ns
54
TCCF
DS39599C-page 330
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-12:
PARALLEL SLAVE PORT TIMING (PIC18F4X20)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X20)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TDTV2WRH Data in valid before WR ↑ or CS ↑
20
—
ns
(setup time)
63
TWRH2DTI WR ↑ or CS ↑ to data–in invalid PIC18FXX20
20
35
—
10
—
—
—
ns
ns
ns
ns
(hold time)
PIC18LFXX20
64
65
66
TRDL2DTV RD ↓ and CS ↓ to data–out valid
TRDH2DTI RD ↑ or CS ↓ to data–out invalid
80
30
TIBFINH
Inhibit of the IBF flag bit being cleared from
3 TCY
WR ↑ or CS ↑
2003 Microchip Technology Inc.
DS39599C-page 331
PIC18F2220/2320/4220/4320
FIGURE 26-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time PIC18FXX20
PIC18LFXX20
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TDOF
TSCR
SDO Data Output Fall Time
SCK Output Rise Time
(Master mode)
PIC18FXX20
PIC18LFXX20
79
80
TSCF
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after PIC18FXX20
TSCL2DOV SCK Edge
PIC18LFXX20
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
DS39599C-page 332
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-14:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
75, 76
MSb In
74
LSb In
bit 6 - - - -1
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
TSCH
Characteristic
Min
Max Units Conditions
71
SCK Input High Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time PIC18FXX20
PIC18LFXX20
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TDOF
TSCR
SDO Data Output Fall Time
—
—
SCK Output Rise Time
(Master mode)
PIC18FXX20
PIC18LFXX20
79
80
TSCF
SCK Output Fall Time (Master mode)
—
—
TSCH2DOV, SDO Data Output Valid after PIC18FXX20
TSCL2DOV SCK Edge
PIC18LFXX20
81
TDOV2SCH, SDO Data Output Setup to SCK Edge
TDOV2SCL
TCY
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
2003 Microchip Technology Inc.
DS39599C-page 333
PIC18F2220/2320/4220/4320
FIGURE 26-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
80
78
MSb
LSb
SDO
SDI
bit 6 - - - - - -1
77
75, 76
LSb In
MSb In
74
bit 6 - - - -1
73
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCK Input High Time (Slave mode)
SCK Input Low Time (Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LFXX20
76
77
78
TDOF
SDO Data Output Fall Time
—
10
—
TSSH2DOZ SS ↑ to SDO Output High-Impedance
TSCR
SCK Output Rise Time (Master mode) PIC18FXX20
PIC18LFXX20
79
80
TSCF
SCK Output Fall Time (Master mode)
—
—
TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX20
TSCL2DOV
PIC18LFXX20
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
DS39599C-page 334
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-16:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
bit 6 - - - -1
LSb In
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
TSCL
TB2B
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCK Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LFXX20
76
77
78
TDOF
SDO Data Output Fall Time
—
TSSH2DOZ SS↑ to SDO Output High-Impedance
10
TSCR
SCK Output Rise Time
(Master mode)
PIC18FXX20
—
PIC18LFXX20
—
79
80
TSCF
SCK Output Fall Time (Master mode)
—
TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20
TSCL2DOV Edge
—
PIC18LFXX20
—
82
83
TSSL2DOV SDO Data Output Valid after SS ↓ PIC18FXX20
—
—
Edge
PIC18LFXX20
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
2003 Microchip Technology Inc.
DS39599C-page 335
PIC18F2220/2320/4220/4320
FIGURE 26-17:
I2C BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-18: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start condition
Hold time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop condition
Setup time
4700
600
THD:STO Stop condition
Hold time
4000
600
FIGURE 26-18:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 26-5 for load conditions.
DS39599C-page 336
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-19: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock High Time
4.0
—
µs
PIC18FXX20 must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
µs
PIC18FXX20 must operate at a
minimum of 10 MHz
SSP module
1.5 TCY
4.7
—
—
101
TLOW
Clock Low Time
100 kHz mode
µs
µs
PIC18FXX20 must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC18FXX20 must operate at a
minimum of 10 MHz
SSP module
1.5 TCY
—
1000
300
300
300
—
102
103
90
TR
TF
SDA and SCL Rise
Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
ns
ns
ns
ns
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
pF
20 + 0.1 CB
CB is specified to be from 10 to 400 pF
CB is specified to be from 10 to 400 pF
SDA and SCL Fall
Time
—
20 + 0.1 CB
TSU:STA Start Condition Setup 100 kHz mode
4.7
0.6
4.0
0.6
0
Only relevant for Repeated
Start condition
Time
400 kHz mode
—
91
THD:STA Start Condition Hold 100 kHz mode
—
After this period, the first clock pulse is
generated
Time
400 kHz mode
—
106
107
92
THD:DAT Data Input Hold Time 100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data Input Setup
Time
100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop Condition Setup 100 kHz mode
—
Time
400 kHz mode
—
109
110
D102
TAA
TBUF
CB
Output Valid from
Clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
Bus Free Time
4.7
1.3
—
—
Time the bus must be free before a
new transmission can start
—
Bus Capacitive Loading
400
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2
2
2: A fast mode I C bus device can be used in a standard mode I C bus system but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I C bus specification), before the SCL line
is released.
2003 Microchip Technology Inc.
DS39599C-page 337
PIC18F2220/2320/4220/4320
FIGURE 26-19:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-20: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start condition 100 kHz mode
Setup time 400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start condition
1 MHz mode(1) 2(TOSC)(BRG + 1)
91
92
93
THD:STA Start condition 100 kHz mode
Hold time 400 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the first
clock pulse is generated
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
TSU:STO Stop condition 100 kHz mode
Setup time 400 kHz mode
2(TOSC)(BRG + 1)
ns
ns
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
THD:STO Stop condition 100 kHz mode
Hold time 400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 26-20:
MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 26-5 for load conditions.
DS39599C-page 338
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-21: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
101
102
103
90
THIGH
Clock High Time
Clock Low Time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
—
TLOW
TR
—
—
—
SDA and SCL
Rise Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
1000
300
300
300
300
100
—
ns CB is specified to be from
10 to 400 pF
20 + 0.1 CB
ns
—
ns
TF
SDA and SCL
Fall Time
—
20 + 0.1 CB
—
ns CB is specified to be from
10 to 400 pF
ns
ns
TSU:STA Start Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
ms Only relevant for
Repeated Start condition
—
ms
—
ms
91
THD:STA Start Condition
Hold Time
—
ms After this period, the first
clock pulse is generated
—
ms
—
ms
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
—
ns
0
0.9
—
ms
TBD
250
100
TBD
ns
TSU:DAT Data Input
Setup Time
—
ns (Note 2)
—
ns
—
ns
TSU:STO Stop Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
—
ms
—
ms
109
110
D102
TAA
TBUF
CB
Output Valid from
Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
—
3500
1000
—
ns
ns
—
ns
Bus Free Time
4.7
1.3
TBD
—
—
ms Time the bus must be free
before a new transmission
—
ms
can start
ms
—
Bus Capacitive Loading
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
2003 Microchip Technology Inc.
DS39599C-page 339
PIC18F2220/2320/4220/4320
FIGURE 26-21:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 26-5 for load conditions.
122
TABLE 26-22: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18FXX20
—
—
—
—
—
—
40
100
20
ns
ns
ns
ns
ns
ns
PIC18LFXX20
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time PIC18FXX20
(Master mode)
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
50
Data Out Rise Time and Fall Time
20
50
FIGURE 26-22:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-23: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time)
TCKL2DTL Data Hold after CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
DS39599C-page 340
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F2220/2320/4220/4320 (INDUSTRIAL)
PIC18F2220/2320/4220/4320 (EXTENDED)
PIC18LF2220/2320/4220/4320 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Resolution
Min
Typ
Max
Units
Conditions
A01
NR
—
—
—
—
—
—
—
—
—
—
10
bit ∆VREF ≥ 3.0V
A03
A04
A06
A07
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
<±1
<±1
<±1
<±1
LSb ∆VREF ≥ 3.0V
LSb ∆VREF ≥ 3.0V
LSb ∆VREF ≥ 3.0V
LSb ∆VREF ≥ 3.0V
EDL
EOFF
EGN
Gain Error
A10
A20
—
Monotonicity
guaranteed(2)
—
∆VREF Reference Voltage Range
3
—
AVDD – AVSS
V
For 10-bit resolution
(VREFH – VREFL)
A21
A22
A25
A28
A29
A30
VREFH Reference Voltage High
VREFL Reference Voltage Low
AVSS + 3.0V
AVSS – 0.3V
VREFL
—
—
—
—
—
—
AVDD + 0.3V
AVDD – 3.0V
VREFH
V
V
For 10-bit resolution
For 10-bit resolution
VAIN
Analog Input Voltage
Analog Supply Voltage
Analog Supply Voltage
V
AVDD
AVSS
ZAIN
VDD – 0.3
VSS – 0.3
—
VDD + 0.3
VSS + 0.3
2.5(4)
V
Tie to VDD
Tie to VSS
V
Recommended Impedance of
Analog Voltage Source
kΩ
A40
A50
IAD
A/D Current
from VDD
PIC18FXX20
—
—
—
—
180(5)
90(5)
µA Average current during
conversion(1)
PIC18LFXX20
µA
IREF
VREF Input Current (3)
—
—
—
—
±5(5)
µA During VAIN acquisition.
µA During A/D conversion
cycle.
±150(5)
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
4: Assume quiet environment. If adjacent pins have high-frequency signals (analog or digital), ZAIN may need
to be reduced to as low as 1 kΩ to fight crosstalk effects.
5: For guidance only.
2003 Microchip Technology Inc.
DS39599C-page 341
PIC18F2220/2320/4220/4320
FIGURE 26-23:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction to be
executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
PIC18FXX20
1.6
3.0
2.0
3.0
11
20(2)
20(2)
6.0
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC mode
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
9.0
µs A/D RC mode
131
TCNV
Conversion Time
12
TAD
(not including acquisition time)(1)
Note 1: ADRES register may be read on the following TCY cycle.
2: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
DS39599C-page 342
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
27.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean – 3σ)
respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 27-1:
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
0.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.4
0.3
0.2
0.1
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 27-2:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +85°C
0.7
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.6
0.5
0.4
0.3
0.2
0.1
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
2003 Microchip Technology Inc.
DS39599C-page 343
PIC18F2220/2320/4220/4320
FIGURE 27-3:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
0.7
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.6
0.5
0.4
0.3
0.2
0.1
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 27-4:
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
2.0
Typical:
statistical mean @ 25°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
1.0
1.5
2.0
2.5
(MHz)
3.0
3.5
4.0
F
OSC
DS39599C-page 344
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-5:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
2.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
2.0
1.5
1.0
0.5
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 27-6:
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
16
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
14
12
10
8
5.5V
5.0V
4.5V
4.0V
6
3.5V
4
3.0V
2
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
F
(MHz)
OSC
2003 Microchip Technology Inc.
DS39599C-page 345
PIC18F2220/2320/4220/4320
FIGURE 27-7:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
16
Typical:
statistical mean @ 25°C
14
12
10
8
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
5.0V
4.0V
4.5V
3.5V
6
4
3.0V
2
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 27-8:
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
0.035
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
0.030
0.025
0.020
0.015
0.010
0.005
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
DS39599C-page 346
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-9:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +85°C
0.045
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 27-10:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
0.100
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.090
0.080
0.070
0.060
0.050
0.040
0.030
0.020
0.010
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
2003 Microchip Technology Inc.
DS39599C-page 347
PIC18F2220/2320/4220/4320
FIGURE 27-11:
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
600
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
500
400
300
200
100
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
1.0
1.5
2.0
2.5
(MHz)
3.0
3.5
4.0
F
OSC
FIGURE 27-12:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
600
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
500
400
300
200
100
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS39599C-page 348
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-13:
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
6.0
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
4
8
12
16
20
24
28
32
36
40
F
(MHz)
OSC
FIGURE 27-14:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
2003 Microchip Technology Inc.
DS39599C-page 349
PIC18F2220/2320/4220/4320
FIGURE 27-15:
TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_RUN MODE,
ALL PERIPHERALS DISABLED
3000
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
8 MHz
2500
2000
1500
1000
500
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
4 MHz
2 MHz
1 MHz
125 kHz
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-16:
MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_RUN,
ALL PERIPHERALS DISABLED
3500
8 MHz
3000
2500
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
2000
1500
1000
500
0
4 MHz
2 MHz
1 MHz
125 kHz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39599C-page 350
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-17:
TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_RUN,
ALL PERIPHERALS DISABLED
100
Max (+125°C)
Max (+85°C)
Typ (+25°C)
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-18:
TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_IDLE MODE,
ALL PERIPHERALS DISABLED
800
750
700
650
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
8 MHz
4 MHz
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
600
550
500
450
400
350
300
250
200
150
100
2 MHz
1 MHz
125 kHz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2003 Microchip Technology Inc.
DS39599C-page 351
PIC18F2220/2320/4220/4320
FIGURE 27-19:
MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_IDLE,
ALL PERIPHERALS DISABLED
800
750
700
650
600
550
500
450
400
350
300
250
200
150
8 MHz
4 MHz
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
2 MHz
1 MHz
125 kHz
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-20:
TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_IDLE,
ALL PERIPHERALS DISABLED
100
Max (+125°C)
Max (+85°C)
Typ (+25°C)
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39599C-page 352
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-21:
IPD SEC_RUN MODE, -10°C TO +70°C 32.768 kHz XTAL 2 X 22 pF,
ALL PERIPHERALS DISABLED
80
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
70
60
50
40
30
20
10
0
Max (+70°C)
Typ (+25°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-22:
IPD SEC_IDLE, -10°C TO +70°C 32.768 kHz 2 X 22 pF,
ALL PERIPHERALS DISABLED
20
18
16
14
12
10
8
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Max (+70°C)
Typ (+25°C)
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2003 Microchip Technology Inc.
DS39599C-page 353
PIC18F2220/2320/4220/4320
FIGURE 27-23:
TOTAL IPD, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED
100
Max (+125°C)
Max (+85°C)
10
1
0.1
0.01
Typ (+25°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.001
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-24:
VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V
3.0
2.5
2.0
1.5
1.0
0.5
Max (+125°C)
Typ (+25°C)
Min (+125°C)
0.0
0
5
10
15
20
25
IOH (-mA)
DS39599C-page 354
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-25:
VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max (+125°C)
Typ (+25°C)
Min (+125°C)
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 27-26:
VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V
3.0
Max (+125°C)
2.5
2.0
1.5
1.0
0.5
Max (+85°C)
Typ (+25°C)
Min (+125°C)
0.0
0
5
10
15
20
25
IOL (-mA)
2003 Microchip Technology Inc.
DS39599C-page 355
PIC18F2220/2320/4220/4320
FIGURE 27-27:
VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Max (+125°C)
Max (+85°C)
Typ (+25°C)
Min (+125°C)
0.0
0
5
10
15
20
25
IOL (-mA)
FIGURE 27-28:
∆ IPD TIMER1 OSCILLATOR, -10°C TO +70°C SLEEP MODE,
TMR1 COUNTER DISABLED
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max (-10°C to +70°C)
Typ (+25°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39599C-page 356
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-29:
∆IPD FSCM vs. VDD OVER TEMPERATURE PRI_IDLE, EC OSCILLATOR AT 32 kHz,
-40°C TO +125°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max (-40°C)
Typ (+25°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
FIGURE 27-30:
∆IPD WDT, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED
14
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
12
10
8
Max (+125°C)
6
Max (+85°C)
Typ (+25°C)
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
2003 Microchip Technology Inc.
DS39599C-page 357
PIC18F2220/2320/4220/4320
FIGURE 27-31:
∆IPD LVD vs. VDD SLEEP MODE, LVD = 2.00V-2.12V
50
45
40
35
30
25
20
15
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Max (+125°C)
Max (+85°C)
Typ (+25°C)
Low-Voltage Detection Range
5
0
Normal Operating Range
3.5 4.0
2.0
2.5
3.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-32:
∆IPD BOR vs. VDD, -40°C TO +125°C SLEEP MODE,
BOR ENABLED AT 2.00V-2.16V
40
35
30
25
20
15
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Max (+125°C)
Typ (+25°C)
Device may be in Reset
5
0
Device is Operating
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD (V)
DS39599C-page 358
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-33:
∆IPD A/D, -40°C TO +125°C SLEEP MODE, A/D ENABLED (NOT CONVERTING)
10
Max (+125°C)
1
Max (+85°C)
0.1
0.01
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Typ (+25°C)
0.001
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-34:
AVERAGE FOSC vs. VDD FOR VARIOUS R'S EXTERNAL RC MODE,
C = 20 pF, TEMPERATURE = +25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Operation above 4 MHz is not recomended
5.1K
10K
33K
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
2003 Microchip Technology Inc.
DS39599C-page 359
PIC18F2220/2320/4220/4320
FIGURE 27-35:
AVERAGE FOSC vs. VDD FOR VARIOUS R'S EXTERNAL RC MODE,
C = 100 pF, TEMPERATURE = +25°C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5.1K
10K
33K
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
FIGURE 27-36:
AVERAGE FOSC vs. VDD FOR VARIOUS R'S EXTERNAL RC MODE,
C = 300 pF, TEMPERATURE = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
5.1K
10K
33K
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
DS39599C-page 360
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
28.0 PACKAGING INFORMATION
28.1 Package Marking Information
28-Lead SPDIP
Example
PIC18F2220-I/SP
0310017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC18F2320-E/SO
0310017
YYWWNNN
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC18F4220-I/P
0310017
Legend: XX...X Customer specific information*
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2003 Microchip Technology Inc.
DS39599C-page 361
PIC18F2220/2320/4220/4320
Package Marking Information (Continued)
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F4320
-I/PT
0310017
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F4220
-I/ML
0310017
DS39599C-page 362
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
28.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
2003 Microchip Technology Inc.
DS39599C-page 363
PIC18F2220/2320/4220/4320
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS39599C-page 364
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
1
α
n
E
A2
A
L
c
B1
B
β
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
eB
α
β
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
5
10
15
5
10
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
2003 Microchip Technology Inc.
DS39599C-page 365
PIC18F2220/2320/4220/4320
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
φ
β
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
DS39599C-page 366
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
EXPOSED
METAL
PAD
E
p
D
D2
2
1
B
n
PIN 1
INDEX ON
EXPOSED PAD
OPTIONAL PIN 1
INDEX ON
TOP MARKING
E2
L
(PROFILE MAY VARY)
TOP VIEW
BOTTOM VIEW
DETAIL: CONTACT VARIANTS
A
A1
(A3)
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Contacts
44
1
2
1
Pitch
.026 BSC
.035
.001
.010 REF
0.65 BSC
Overall Height
Standoff
A
A1
(A3)
E
.031
.039
0.80
0.90
1.00
.000
.002
0
0.02
0.05
2
Base Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
0.25 REF
.309
.246
.309
.246
.008
.014
.315
.268
.315
.268
.013
.016
.321
.274
.321
.274
.013
.019
7.85
6.25
7.85
6.25
0.20
0.35
8.00
6.80
8.00
6.80
0.33
0.40
8.15
6.95
8.15
6.95
0.35
0.48
E2
D
D2
B
L
*Controlling Parameter
Notes:
1. BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
2. REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
3. Contact profiles may vary.
4. JEDEC equivalent: M0-220
Drawing No. C04-103
2003 Microchip Technology Inc.
DS39599C-page 367
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 368
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (June 2002)
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for PIC18F2X20/4X20 devices.
Revision B (October 2002)
This revision includes major changes to Section 2.0
“Oscillator Configurations” and Section 3.0 “Power
Managed Modes”, updates to the Electrical Specifica-
tions in Section 26.0 “Electrical Characteristics”
and minor corrections to the data sheet text.
Revision C (October 2003)
This revision includes updates to the Electrical Specifi-
cations in Section 26.0 “Electrical Characteristics”
and to the DC Characteristics Graphs and Charts in
Section 27.0 “DC and AC Characteristics Graphs
and Tables” and minor corrections to the data sheet
text.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F2220
PIC18F2320
PIC18F4220
PIC18F4320
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
4096
8192
4096
19
4096
2048
20
8192
4096
20
2048
19
I/O Ports
Ports A, B, C, (E)
2
Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Capture/Compare/PWM Modules
2
1
1
Enhanced Capture/Compare/
PWM Modules
0
0
1
1
Parallel Communications (PSP)
10-bit Analog-to-Digital Module
No
No
Yes
Yes
10 input channels 10 input channels 13 input channels 13 input channels
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
28-pin SPDIP
28-pin SOIC
28-pin SPDIP
28-pin SOIC
Packages
2003 Microchip Technology Inc.
DS39599C-page 369
PIC18F2220/2320/4220/4320
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This appendix discusses the considerations for con-
verting from previous versions of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
DS39599C-page 370
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
APPENDIX E: MIGRATION FROM
APPENDIX F: MIGRATION FROM
HIGH-END TO
MID-RANGE TO
ENHANCED DEVICES
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442.” The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration.” This Application Note is
available as Literature Number DS00726.
This Application Note is available as Literature Number
DS00716.
2003 Microchip Technology Inc.
DS39599C-page 371
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 372
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
INDEX
Compare Mode Operation ....................................... 136
External Power-on Reset Circuit
A
A/D ................................................................................... 211
A/D Converter Interrupt, Configuring ....................... 215
Acquisition Requirements ........................................ 216
ADCON0 Register .................................................... 211
ADCON1 Register .................................................... 211
ADCON2 Register .................................................... 211
ADRESH Register ............................................ 211, 214
ADRESL Register .................................................... 211
Analog Port Pins, Configuring .................................. 218
Associated Registers ............................................... 220
Automatic Acquisition Time ...................................... 217
Calculating the Minimum Required
Acquisition Time ............................................... 216
Configuring the Module ............................................ 215
Conversion Clock (TAD) ........................................... 217
Conversion Status (GO/DONE Bit) .......................... 214
Conversions ............................................................. 219
Converter Characteristics ........................................ 341
Operation in Power Managed Modes ...................... 218
Special Event Trigger (CCP) ............................ 136, 220
Use of the CCP2 Trigger .......................................... 220
VREF+ and VREF- References .................................. 216
Absolute Maximum Ratings ............................................. 305
AC (Timing) Characteristics ............................................. 323
Load Conditions for Device
Timing Specifications ....................................... 324
Parameter Symbology ............................................. 323
Temperature and Voltage Specifications ................. 324
Timing Conditions .................................................... 324
Access Bank ...................................................................... 65
ACKSTAT Status Flag ..................................................... 185
ADCON0 Register ............................................................ 211
GO/DONE Bit ........................................................... 214
ADCON1 Register ............................................................ 211
ADCON2 Register ............................................................ 211
ADDLW ............................................................................ 261
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See USART.
(Slow VDD Power-up) ........................................ 44
Fail-Safe Clock Monitor ........................................... 248
Generic I/O Port Operation ...................................... 101
Interrupt Logic ............................................................ 88
Low-Voltage Detect (LVD) ....................................... 232
Low-Voltage Detect (LVD) with External Input ........ 232
MCLR/VPP/RE3 Pin ................................................. 111
2
MSSP (I C Master Mode) ........................................ 179
2
MSSP (I C Mode) .................................................... 164
MSSP (SPI Mode) ................................................... 155
On-Chip Reset Circuit ................................................ 43
PIC18F2220/2320 ....................................................... 9
PIC18F4220/4320 ..................................................... 10
PLL ............................................................................ 20
PORTC (Peripheral Output Override) ...................... 107
PORTD and PORTE (Parallel Slave Port) ............... 114
PWM (Enhanced) .................................................... 143
PWM (Standard) ...................................................... 138
RA3:RA0 and RA5 Pins ........................................... 102
RA4/T0CKI Pin ........................................................ 102
RA6 Pin ................................................................... 102
RA7 Pin ................................................................... 102
RB2:RB0 Pins .......................................................... 105
RB3/CCP2 Pin ......................................................... 105
RB4 Pin ................................................................... 105
RB7:RB5 Pins .......................................................... 104
RD4:RD0 Pins ......................................................... 110
RD7:RD5 Pins ......................................................... 109
RE2:RE0 Pins .......................................................... 111
Reads from Flash Program Memory .......................... 75
System Clock ............................................................. 25
Table Read Operation ............................................... 71
Table Write Operation ................................................ 72
Table Writes to Flash Program Memory .................... 77
Timer0 in 16-bit Mode .............................................. 118
Timer0 in 8-bit Mode ................................................ 118
Timer1 ..................................................................... 122
Timer1 (16-bit Read/Write Mode) ............................ 122
Timer2 ..................................................................... 128
Timer3 ..................................................................... 130
Timer3 (16-bit Read/Write Mode) ............................ 130
USART Receive ....................................................... 204
USART Transmit ...................................................... 202
Watchdog Timer ...................................................... 245
BN .................................................................................... 264
BNC ................................................................................. 265
BNN ................................................................................. 265
BNOV ............................................................................... 266
BNZ .................................................................................. 266
BOR. See Brown-out Reset.
ADDWF ............................................................................ 261
ADDWFC ......................................................................... 262
ADRESH Register ............................................................ 211
ADRESL Register .................................................... 211, 214
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 262
ANDWF ............................................................................ 263
Assembler
MPASM Assembler .................................................. 299
B
Bank Select Register (BSR) ............................................... 65
Baud Rate Generator ....................................................... 181
BC .................................................................................... 263
BCF .................................................................................. 264
BF Status Flag ................................................................. 185
Block Diagrams
BOV ................................................................................. 269
BRA ................................................................................. 267
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..............................................44, 237
BSF .................................................................................. 267
BTFSC ............................................................................. 268
BTFSS ............................................................................. 268
BTG ................................................................................. 269
BZ .................................................................................... 270
A/D ........................................................................... 214
Analog Input Model .................................................. 215
Baud Rate Generator ............................................... 181
Capture Mode Operation ......................................... 135
Comparator I/O Operating Modes ............................ 222
Comparator Output .................................................. 224
Comparator Voltage Reference ............................... 228
2003 Microchip Technology Inc.
DS39599C-page 373
PIC18F2220/2320/4220/4320
Comparator ...................................................................... 221
C
Analog Input Connection Considerations ................ 225
Associated Registers ............................................... 226
Configuration ........................................................... 221
Effects of a Reset .................................................... 225
Interrupts .................................................................. 224
Operation ................................................................. 223
Operation in Power Managed Modes ...................... 225
Outputs .................................................................... 223
Reference ................................................................ 223
Response Time ........................................................ 223
Comparator Specifications ............................................... 321
Comparator Voltage Reference ....................................... 227
Accuracy and Error .................................................. 228
Associated Registers ............................................... 229
Configuring .............................................................. 227
Connection Considerations ...................................... 228
Effects of a Reset .................................................... 228
Operation in Power Managed Modes ...................... 228
Compare (CCP Module) .................................................. 136
Associated Registers ............................................... 137
CCP Pin Configuration ............................................. 136
CCPR1 Register ...................................................... 136
Software Interrupt .................................................... 136
Special Event Trigger .......................................136, 220
Timer1/Timer3 Mode Selection ................................ 136
Compare (ECCP Mode) ................................................... 142
Computed GOTO ............................................................... 59
Configuration Bits ............................................................ 237
Configuration Register Protection .................................... 254
Context Saving During Interrupts ....................................... 99
Control Registers
C Compilers
MPLAB C17 .............................................................300
MPLAB C18 .............................................................300
MPLAB C30 .............................................................300
CALL ................................................................................270
Capture (CCP Module) .....................................................135
Associated Registers ...............................................137
CCP Pin Configuration .............................................135
CCPR1H:CCPR1L Registers ...................................135
Software Interrupt .....................................................135
Timer1/Timer3 Mode Selection ................................135
Capture (ECCP Module) ..................................................142
Capture/Compare/PWM (CCP) ........................................133
Capture Mode. See Capture.
CCP1 ........................................................................134
CCPR1H Register ............................................134
CCPR1L Register ............................................134
CCP2 ........................................................................134
CCPR2H Register ............................................134
CCPR2L Register ............................................134
Compare Mode. See Compare.
Interaction of Two CCP Modules .............................134
PWM Mode. See PWM.
Timer Resources ......................................................134
Clock Sources ....................................................................24
Selection Using OSCCON Register ...........................24
Clocking Scheme/Instruction Cycle ....................................57
CLRF ................................................................................271
CLRWDT ..........................................................................271
Code Examples
16 x 16 Signed Multiply Routine .................................86
16 x 16 Unsigned Multiply Routine .............................86
8 x 8 Signed Multiply Routine .....................................85
8 x 8 Unsigned Multiply Routine .................................85
Changing Between Capture Prescalers ...................135
Computed GOTO Using an Offset Value ...................59
Data EEPROM Read .................................................83
Data EEPROM Refresh Routine ................................84
Data EEPROM Write ..................................................83
Erasing a Flash Program Memory Row .....................76
Fast Register Stack ....................................................56
How to Clear RAM (Bank 1) Using
EECON1 and EECON2 ............................................. 72
Conversion Considerations .............................................. 370
CPFSEQ .......................................................................... 272
CPFSGT .......................................................................... 273
CPFSLT ........................................................................... 273
Crystal Oscillator/Ceramic Resonator ................................ 19
D
Data EEPROM Code Protection ...................................... 254
Data EEPROM Memory ..................................................... 81
Associated Registers ................................................. 84
EEADR Register ........................................................ 81
EECON1 and EECON2 Registers ............................. 81
Operation During Code-Protect ................................. 84
Protection Against Spurious Write ............................. 83
Reading ..................................................................... 83
Using .......................................................................... 84
Write Verify ................................................................ 83
Writing ........................................................................ 83
Data Memory ..................................................................... 59
General Purpose Registers ....................................... 59
Map for PIC18F2X20/4X20 ........................................ 60
Special Function Registers ........................................ 61
DAW ................................................................................ 274
DC and AC Characteristics
Graphs and Tables .................................................. 343
DC Characteristics ........................................................... 318
Power-Down and Supply Current ............................ 309
Supply Voltage ......................................................... 308
DCFSNZ .......................................................................... 275
DECF ............................................................................... 274
DECFSZ .......................................................................... 275
Indirect Addressing ............................................66
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service ..................................125
Initializing PORTA ....................................................101
Initializing PORTB ....................................................104
Initializing PORTC ....................................................107
Initializing PORTD ....................................................109
Initializing PORTE ....................................................111
Loading the SSPBUF (SSPSR) Register .................158
Reading a Flash Program Memory Word ...................75
Saving Status, WREG and BSR Registers
in RAM ...............................................................99
Writing to Flash Program Memory ....................... 78–79
Code Protection ....................................................... 237, 251
COMF ...............................................................................272
DS39599C-page 374
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Demonstration Boards
G
PICDEM 1 ................................................................ 302
PICDEM 17 .............................................................. 302
PICDEM 18R PIC18C601/801 ................................. 303
PICDEM 2 Plus ........................................................ 302
PICDEM 3 PIC16C92X ............................................ 302
PICDEM 4 ................................................................ 302
PICDEM LIN PIC16C43X ........................................ 303
PICDEM USB PIC16C7X5 ....................................... 303
PICDEM.net Internet/Ethernet ................................. 302
Development Support ...................................................... 299
Device Differences ........................................................... 369
Device Overview .................................................................. 7
Features (table) ............................................................ 8
New Core Features ...................................................... 7
Other Special Features ................................................ 7
Direct Addressing ............................................................... 67
GOTO .............................................................................. 276
H
Hardware Multiplier ............................................................ 85
Introduction ................................................................ 85
Operation ................................................................... 85
Performance Comparison .......................................... 85
HSPLL ............................................................................... 20
I
I/O Ports ........................................................................... 101
2
I C Mode
ACK Pulse ........................................................168, 169
Acknowledge Sequence Timing .............................. 188
Baud Rate Generator .............................................. 181
Bus Collision During a Repeated
Start Condition ................................................. 192
Bus Collision During a Start Condition ..................... 190
Bus Collision During a Stop Condition ..................... 193
Clock Arbitration ...................................................... 182
Clock Stretching ....................................................... 174
Effect of a Reset ...................................................... 189
General Call Address Support ................................. 178
Master Mode ............................................................ 179
Master Mode (Reception, 7-bit Address) ................. 187
Master Mode Operation ........................................... 180
Master Mode Reception ........................................... 185
Master Mode Repeated Start
E
ECCP ............................................................................... 141
Auto-Shutdown ........................................................ 149
and Automatic Restart ..................................... 151
Capture and Compare Modes .................................. 142
Outputs .................................................................... 142
Standard PWM Mode ............................................... 142
Start-up Considerations ........................................... 151
Effects of Power Managed Modes on
Various Clock Sources ............................................... 27
Electrical Characteristics .................................................. 305
Enhanced Capture/Compare/PWM (ECCP) .................... 141
Capture Mode. See Capture (ECCP Module).
Condition Timing .............................................. 184
Master Mode Start Condition Timing ....................... 183
Master Mode Transmission ..................................... 185
Multi-Master Communication, Bus Collision
PWM Mode. See PWM (ECCP Module).
Enhanced CCP Auto-Shutdown ....................................... 149
Enhanced PWM Mode. See PWM (ECCP Module).
Equations
16 x 16 Signed Multiplication Algorithm ..................... 86
16 x 16 Unsigned Multiplication Algorithm ................. 86
A/D Acquisition Time ................................................ 216
A/D Minimum Holding Capacitor .............................. 216
Errata ................................................................................... 5
Evaluation and Programming Tools ................................. 303
External Clock Input ........................................................... 21
and Bus Arbitration .......................................... 189
Multi-Master Mode ................................................... 189
Operation ................................................................. 168
Operation in Power Managed Mode ........................ 189
Read/Write Bit Information (R/W Bit) ................168, 169
Registers ................................................................. 164
Serial Clock (RC3/SCK/SCL) ................................... 169
Slave Mode .............................................................. 168
Addressing ....................................................... 168
Reception ........................................................ 169
Transmission ................................................... 169
Stop Condition Timing ............................................. 188
ID Locations ..............................................................237, 254
INCF ................................................................................ 276
INCFSZ ............................................................................ 277
In-Circuit Debugger .......................................................... 254
In-Circuit Serial Programming (ICSP) .......................237, 254
Indirect Addressing
INDF and FSR Registers ........................................... 66
Operation ................................................................... 66
Indirect Addressing Operation ........................................... 67
Indirect File Operand ......................................................... 59
INFSNZ ............................................................................ 277
Initialization Conditions for all Registers .......................46–49
Instruction Cycle ................................................................ 57
Instruction Flow/Pipelining ................................................. 57
Instruction Format ............................................................ 257
F
Fail-Safe Clock Monitor ............................................ 237, 248
Interrupts in Power Managed Modes ....................... 250
POR or Wake-up from Sleep ................................... 250
WDT During Oscillator Failure ................................. 248
Fast Register Stack ............................................................ 56
Firmware Instructions ....................................................... 255
Flash Program Memory ...................................................... 71
Associated Registers ................................................. 79
Control Registers ....................................................... 72
Erase Sequence ........................................................ 76
Erasing ....................................................................... 76
Operation During Code-Protect ................................. 79
Reading ...................................................................... 75
TABLAT Register ....................................................... 74
Table Pointer .............................................................. 74
Boundaries Based on Operation ........................ 74
Table Pointer Boundaries .......................................... 74
Table Reads and Table Writes .................................. 71
Unexpected Termination of Write Operation .............. 79
Write Verify ................................................................ 79
Writing to .................................................................... 77
FSCM. See Fail-Safe Clock Monitor.
2003 Microchip Technology Inc.
DS39599C-page 375
PIC18F2220/2320/4220/4320
Instruction Set ..................................................................255
ADDLW ....................................................................261
ADDWF ....................................................................261
ADDWFC .................................................................262
ANDLW ....................................................................262
ANDWF ....................................................................263
BC ............................................................................263
BCF ..........................................................................264
BN ............................................................................264
BNC ..........................................................................265
BNN ..........................................................................265
BNOV .......................................................................266
BNZ ..........................................................................266
BOV ..........................................................................269
BRA ..........................................................................267
BSF ..........................................................................267
BTFSC .....................................................................268
BTFSS ......................................................................268
BTG ..........................................................................269
BZ .............................................................................270
CALL ........................................................................270
CLRF ........................................................................271
CLRWDT ..................................................................271
COMF .......................................................................272
CPFSEQ ..................................................................272
CPFSGT ...................................................................273
CPFSLT ...................................................................273
DAW .........................................................................274
DCFSNZ ...................................................................275
DECF .......................................................................274
DECFSZ ...................................................................275
GOTO .......................................................................276
INCF .........................................................................276
INCFSZ ....................................................................277
INFSNZ ....................................................................277
IORLW .....................................................................278
IORWF .....................................................................278
LFSR ........................................................................279
MOVF .......................................................................279
MOVFF .....................................................................280
MOVLB .....................................................................280
MOVLW ....................................................................281
MOVWF ...................................................................281
MULLW ....................................................................282
MULWF ....................................................................282
NEGF .......................................................................283
NOP .........................................................................283
POP ..........................................................................284
PUSH .......................................................................284
RCALL ......................................................................285
Reset ........................................................................285
RETFIE ....................................................................286
RETLW .....................................................................286
RETURN ..................................................................287
RLCF ........................................................................287
RLNCF .....................................................................288
RRCF .......................................................................288
RRNCF .....................................................................289
SETF ........................................................................289
SLEEP ......................................................................290
SUBFWB ..................................................................290
SUBLW .................................................................... 291
SUBWF .................................................................... 291
SUBWFB ................................................................. 292
SWAPF .................................................................... 293
TBLRD ..................................................................... 294
TBLWT ..................................................................... 295
TSTFSZ ................................................................... 296
XORLW .................................................................... 296
XORWF ................................................................... 297
Summary Table ....................................................... 258
INTCON Register
RBIF Bit ................................................................... 104
INTCON Registers ............................................................. 89
2
Inter-Integrated Circuit. See I C.
Internal Oscillator Block ..................................................... 22
Adjustment ................................................................. 22
INTIO Modes ............................................................. 22
INTRC Output Frequency .......................................... 22
OSCTUNE Register ................................................... 22
Internal RC Oscillator
Use with WDT .......................................................... 245
Interrupt Sources ............................................................. 237
A/D Conversion Complete ....................................... 215
Capture Complete (CCP) ......................................... 135
Compare Complete (CCP) ....................................... 136
Interrupt-on-Change (RB7:RB4) .............................. 104
INTn Pin ..................................................................... 99
PORTB, Interrupt-on-Change .................................... 99
TMR0 ......................................................................... 99
TMR1 Overflow ........................................................ 121
TMR2 to PR2 Match ................................................ 128
TMR2 to PR2 Match (PWM) .............................127, 138
TMR3 Overflow .................................................129, 131
USART Receive/Transmit Complete ....................... 195
Interrupts ............................................................................ 87
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ..................................... 135
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit) .......................................... 135
CCP1IF Flag (CCP1IF Bit) ....................................... 136
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ..... 104
INTOSC Frequency Drift .................................................... 40
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 278
IORWF ............................................................................. 278
IPR Registers ..................................................................... 96
L
LFSR ................................................................................ 279
Look-up Tables .................................................................. 59
Low-Voltage Detect ......................................................... 231
Characteristics ......................................................... 322
Effects of a Reset .................................................... 235
Operation ................................................................. 234
Current Consumption ....................................... 235
Reference Voltage Set Point ........................... 235
Operation During Sleep ........................................... 235
Low-Voltage ICSP Programming ..................................... 254
LVD. See Low-Voltage Detect.
DS39599C-page 376
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Oscillator Start-up Timer (OST) ............................27, 44, 237
Oscillator Switching ........................................................... 24
Oscillator Transitions ......................................................... 27
Oscillator, Timer1 ......................................................121, 131
Oscillator, Timer3 ............................................................. 129
M
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ......................................................... 53
Data Memory ............................................................. 59
Program Memory ....................................................... 53
Memory Programming Requirements .............................. 320
Migration from Baseline to Enhanced Devices ................ 370
Migration from High-End to Enhanced Devices ............... 371
Migration from Mid-Range to Enhanced Devices ............. 371
MOVF ............................................................................... 279
MOVFF ............................................................................. 280
MOVLB ............................................................................. 280
MOVLW ............................................................................ 281
MOVWF ........................................................................... 281
MPLAB ASM30 Assembler, Linker, Librarian .................. 300
MPLAB ICD 2 In-Circuit Debugger ................................... 301
MPLAB ICE 2000 High Performance
Universal In-Circuit Emulator ................................... 301
MPLAB ICE 4000 High Performance
Universal In-Circuit Emulator ................................... 301
MPLAB Integrated Development
Environment Software .............................................. 299
MPLINK Object Linker/MPLIB Object Librarian ............... 300
MSSP ............................................................................... 155
Control Registers (General) ..................................... 155
Enabling SPI I/O ...................................................... 159
P
Packaging Information ..................................................... 361
Marking .............................................................361, 362
Parallel Slave Port (PSP) ..........................................109, 114
Associated Registers ............................................... 115
CS (Chip Select) ...............................................113, 114
PORTD .................................................................... 114
RD (Read Input) ................................................113, 114
RE0/AN5/RD Pin ..................................................... 113
RE1/AN6/WR Pin ..................................................... 113
RE2/AN7/CS Pin ...................................................... 113
Select (PSPMODE Bit) .....................................109, 114
WR (Write Input) ...............................................113, 114
PICkit 1 Flash Starter Kit ................................................. 303
PICSTART Plus Development Programmer .................... 301
PIE Registers ..................................................................... 94
Pin Functions
MCLR/VPP/RE3 ....................................................11, 14
OSC1/CLKI/RA7 ...................................................11, 14
OSC2/CLKO/RA6 .................................................11, 14
RA0/AN0 ...............................................................11, 14
RA1/AN1 ...............................................................11, 14
RA2/AN2/VREF-/CVREF .........................................11, 14
RA3/AN3/VREF+ ...................................................11, 14
RA4/T0CKI/C1OUT ..............................................11, 14
RA5/AN4/SS/LVDIN/C2OUT ................................11, 14
RB0/AN12/INT0 ....................................................12, 15
RB1/AN10/INT1 ....................................................12, 15
RB2/AN8/INT2 ......................................................12, 15
RB3/AN9/CCP2 ....................................................12, 15
RB4/AN11/KBI0 ....................................................12, 15
RB5/KBI1/PGM .....................................................12, 15
RB6/KBI2/PGC .....................................................12, 15
RB7/KBI3/PGD .......................................................... 12
RB7/PGD ................................................................... 15
RC0/T1OSO/T1CKI ..............................................13, 16
RC1/T1OSI/CCP2 .................................................13, 16
RC2/CCP1/P1A ....................................................13, 16
RC3/SCK/SCL ......................................................13, 16
RC4/SDI/SDA .......................................................13, 16
RC5/SDO ..............................................................13, 16
RC6/TX/CK ...........................................................13, 16
RC7/RX/DT ...........................................................13, 16
RD0/PSP0 ................................................................. 17
RD1/PSP1 ................................................................. 17
RD2/PSP2 ................................................................. 17
RD3/PSP3 ................................................................. 17
RD4/PSP4 ................................................................. 17
RD5/PSP5/P1B ......................................................... 17
RD6/PSP6/P1C ......................................................... 17
RD7/PSP7/P1D ......................................................... 17
RE0/AN5/RD .............................................................. 18
RE1/AN6/WR ............................................................. 18
RE2/AN7/CS .............................................................. 18
RE3 ............................................................................ 18
VDD .......................................................................13, 18
VSS .......................................................................13, 18
2
I C Master Mode ...................................................... 179
2
I C Mode
2
I C Slave Mode ........................................................ 168
Operation ................................................................. 158
Overview .................................................................. 155
Slave Select Control ................................................ 161
SPI Master Mode ..................................................... 160
SPI Master/Slave Connection .................................. 159
SPI Mode ................................................................. 155
SPI Slave Mode ....................................................... 161
Typical Connection .................................................. 159
MULLW ............................................................................ 282
MULWF ............................................................................ 282
N
NEGF ............................................................................... 283
NOP ................................................................................. 283
O
Opcode Field Descriptions ............................................... 256
OPTION_REG Register
PSA Bit ..................................................................... 119
T0CS Bit ................................................................... 119
T0PS2:T0PS0 Bits ................................................... 119
T0SE Bit ................................................................... 119
Oscillator Configuration ...................................................... 19
EC .............................................................................. 19
ECIO .......................................................................... 19
HS .............................................................................. 19
HSPLL ........................................................................ 19
Internal Oscillator Block ............................................. 22
INTIO1 ....................................................................... 19
INTIO2 ....................................................................... 19
LP ............................................................................... 19
RC .............................................................................. 19
RCIO .......................................................................... 19
XT .............................................................................. 19
Oscillator Selection .......................................................... 237
2003 Microchip Technology Inc.
DS39599C-page 377
PIC18F2220/2320/4220/4320
Pinout I/O Descriptions
Program Memory
PIC18F2220/2320 ......................................................11
PIC18F4220/4320 ......................................................14
PIR Registers .....................................................................92
PLL Lock Time-out .............................................................44
Pointer, FSRn .....................................................................66
POP ..................................................................................284
POR. See Power-on Reset.
Instructions ................................................................ 58
Two-Word .......................................................... 58
Interrupt Vector .......................................................... 53
Map and Stack for PIC18F2220/4220 ....................... 53
Map and Stack for PIC18F2320/4320 ....................... 53
Reset Vector .............................................................. 53
Program Memory Code Protection .................................. 252
Program Verification ........................................................ 251
Program Verification and Code Protection
Associated Registers ............................................... 251
Programming, Device Instructions ................................... 255
PSP. See Parallel Slave Port.
Pulse Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
PUSH ............................................................................... 284
PUSH and POP Instructions .............................................. 55
PWM (CCP Module) ........................................................ 138
Associated Registers ............................................... 139
CCPR1H:CCPR1L Registers ................................... 138
Duty Cycle ............................................................... 138
Example Frequencies/Resolutions .......................... 139
Period ...................................................................... 138
Setup for PWM Operation ........................................ 139
TMR2 to PR2 Match .........................................127, 138
PWM (ECCP Module) ...................................................... 143
Associated Registers ............................................... 153
Direction Change in Full-Bridge Output Mode ......... 147
Effects of a Reset .................................................... 152
Full-Bridge Application Example .............................. 147
Full-Bridge Mode ..................................................... 146
Half-Bridge Mode ..................................................... 145
Half-Bridge Output Mode Applications Example ...... 145
Operation in Power Managed Modes ...................... 152
Operation with Fail-Safe Clock Monitor ................... 152
Output Configurations .............................................. 143
Output Relationships (Active-High State) ................ 144
Output Relationships (Active-Low State) ................. 144
Programmable Dead Band Delay ............................ 149
Setup for Operation ................................................. 152
Shoot-Through Current ............................................ 149
Start-up Considerations ........................................... 151
PORTA
Associated Registers ...............................................103
LATA Register ..........................................................101
PORTA Register ......................................................101
TRISA Register ........................................................101
PORTB
Associated Registers ...............................................106
LATB Register ..........................................................104
PORTB Register ......................................................104
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........104
TRISB Register ........................................................104
PORTC
Associated Registers ...............................................108
LATC Register ..........................................................107
PORTC Register ......................................................107
TRISC Register ........................................................107
PORTD
Associated Registers ...............................................110
LATD Register ..........................................................109
Parallel Slave Port (PSP) Function ..........................109
PORTD Register ......................................................109
TRISD Register ........................................................109
PORTE
Analog Port Pins ......................................................113
Associated Registers ...............................................113
LATE Register ..........................................................111
PORTE Register ......................................................111
PSP Mode Select (PSPMODE Bit) ..........................109
RE0/AN5/RD Pin ......................................................113
RE1/AN6/WR Pin .....................................................113
RE2/AN7/CS Pin ......................................................113
TRISE Register ........................................................111
Postscaler, WDT
Assignment (PSA Bit) ...............................................119
Rate Select (T0PS2:T0PS0 Bits) .............................119
Power Managed Modes .....................................................29
Entering ......................................................................30
Idle Modes ..................................................................31
Run Modes .................................................................36
Selecting ....................................................................29
Sleep Mode ................................................................31
Summary (table) .........................................................29
Wake-up from .............................................................38
Power-on Reset (POR) .............................................. 44, 237
Power-up Delays ................................................................27
Power-up Timer (PWRT) ...................................... 27, 44, 237
Prescaler, Capture ...........................................................135
Prescaler, Timer0 .............................................................119
Assignment (PSA Bit) ...............................................119
Rate Select (T0PS2:T0PS0 Bits) .............................119
Prescaler, Timer2 .............................................................139
PRO MATE II Universal Device Programmer ...................301
Product Identification System ...........................................385
Program Counter
Q
Q Clock ............................................................................ 139
R
RAM. See Data Memory.
RC Oscillator ...................................................................... 21
RCIO Oscillator Mode ................................................ 21
RCALL ............................................................................. 285
RCON Register
Bit Status During Initialization .................................... 45
Bits and Positions ...................................................... 45
RCSTA Register
SPEN Bit .................................................................. 195
Register File ....................................................................... 59
Registers
ADCON0 (A/D Control 0) ......................................... 211
ADCON1 (A/D Control 1) ......................................... 212
ADCON2 (A/D Control 2) ......................................... 213
CCP1CON (Enhanced CCP
Operation Control 1) ........................................ 141
CCPxCON (Capture/Compare/PWM Control) ......... 133
CMCON (Comparator Control) ................................ 221
CONFIG1H (Configuration 1 High) .......................... 238
PCL Register ..............................................................56
PCLATH Register .......................................................56
PCLATU Register .......................................................56
DS39599C-page 378
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
CONFIG2H (Configuration 2 High) .......................... 239
S
CONFIG2L (Configuration 2 Low) ............................ 239
CONFIG3H (Configuration 3 High) .......................... 240
CONFIG4L (Configuration 4 Low) ............................ 240
CONFIG5H (Configuration 5 High) .......................... 241
CONFIG5L (Configuration 5 Low) ............................ 241
CONFIG6H (Configuration 6 High) .......................... 242
CONFIG6L (Configuration 6 Low) ............................ 242
CONFIG7H (Configuration 7 High) .......................... 243
CONFIG7L (Configuration 7 Low) ............................ 243
CVRCON (Comparator Voltage
SCI. See USART.
SCK ................................................................................. 155
SDI ................................................................................... 155
SDO ................................................................................. 155
Serial Clock (SCK) Pin ..................................................... 155
Serial Communication Interface. See USART.
Serial Data In (SDI) Pin ................................................... 155
Serial Data Out (SDO) Pin ............................................... 155
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 289
Shoot-Through Current .................................................... 149
Slave Select (SS) Pin ...................................................... 155
SLEEP ............................................................................. 290
Sleep
Reference Control) ........................................... 227
Device ID Register 1 ................................................ 244
Device ID Register 2 ................................................ 244
ECCPAS (Enhanced CCP
Auto-Shutdown Control) ................................... 150
EECON1 (Data EEPROM Control 1) ................... 73, 82
INTCON (Interrupt Control) ........................................ 89
INTCON2 (Interrupt Control 2) ................................... 90
INTCON3 (Interrupt Control 3) ................................... 91
IPR1 (Peripheral Interrupt Priority 1) .......................... 96
IPR2 (Peripheral Interrupt Priority 2) .......................... 97
LVDCON (LVD Control) ........................................... 233
OSCCON (Oscillator Control) .................................... 26
OSCTUNE (Oscillator Tuning) ................................... 23
PIE1 (Peripheral Interrupt Enable 1) .......................... 94
PIE2 (Peripheral Interrupt Enable 2) .......................... 95
PIR1 (Peripheral Interrupt Request
OSC1 and OSC2 Pin States ...................................... 27
Software Simulator (MPLAB SIM) ................................... 300
Software Simulator (MPLAB SIM30) ............................... 300
Special Event Trigger. See Compare
(CCP Module)
Special Features of the CPU ........................................... 237
Special Function Registers ................................................ 61
Map ............................................................................ 61
SPI Mode
Associated Registers ............................................... 163
Bus Mode Compatibility ........................................... 163
Effects of a Reset .................................................... 163
Master in Power Managed Modes ........................... 163
Master Mode ............................................................ 160
Master/Slave Connection ......................................... 159
Registers ................................................................. 156
Serial Clock .............................................................. 155
Serial Data In ........................................................... 155
Serial Data Out ........................................................ 155
Slave in Power Managed Modes ............................. 163
Slave Mode .............................................................. 161
Slave Select ............................................................. 155
SPI Clock ................................................................. 160
SS .................................................................................... 155
SSP
(Flag) 1) ............................................................. 92
PIR2 (Peripheral Interrupt Request
(Flag) 2) ............................................................. 93
PWM1CON (Enhanced PWM Configuration) ........... 149
RCON (Reset Control) ......................................... 69, 98
RCSTA (Receive Status and Control) ...................... 197
2
SSPCON1 (MSSP Control 1, I C Mode) ................. 166
SSPCON1 (MSSP Control 1, SPI Mode) ................. 157
2
SSPCON2 (MSSP Control 2, I C Mode) ................. 167
2
SSPSTAT (MSSP Status, I C Mode) ....................... 165
SSPSTAT (MSSP Status, SPI Mode) ...................... 156
Status ......................................................................... 68
STKPTR (Stack Pointer) ............................................ 55
Summary .............................................................. 62–64
T0CON (Timer0 Control) .......................................... 117
T1CON (Timer 1 Control) ......................................... 121
T2CON (Timer 2 Control) ......................................... 127
T3CON (Timer3 Control) .......................................... 129
TRISE ...................................................................... 112
TXSTA (Transmit Status and Control) ..................... 196
WDTCON (Watchdog Timer Control) ....................... 246
Reset .......................................................................... 43, 285
Resets .............................................................................. 237
RETFIE ............................................................................ 286
RETLW ............................................................................. 286
RETURN .......................................................................... 287
Return Address Stack ........................................................ 54
Return Stack Pointer (STKPTR) ........................................ 54
Revision History ............................................................... 369
RLCF ................................................................................ 287
RLNCF ............................................................................. 288
RRCF ............................................................................... 288
RRNCF ............................................................................. 289
2
2
I C Mode. See I C.
SSPBUF Register .................................................... 160
SSPSR Register ...................................................... 160
TMR2 Output for Clock Shift .............................127, 128
SSPOV Status Flag ......................................................... 185
SSPSTAT Register
R/W Bit .............................................................168, 169
Stack Full/Underflow Resets .............................................. 55
SUBFWB ......................................................................... 290
SUBLW ............................................................................ 291
SUBWF ............................................................................ 291
SUBWFB ......................................................................... 292
SWAPF ............................................................................ 293
T
TABLAT Register ............................................................... 74
Table Pointer Operations (table) ........................................ 74
Table Reads/Table Writes ................................................. 59
TBLPTR Register ............................................................... 74
TBLRD ............................................................................. 294
TBLWT ............................................................................. 295
Time-out in Various Situations (table) ................................ 45
Time-out Sequence ........................................................... 44
2003 Microchip Technology Inc.
DS39599C-page 379
PIC18F2220/2320/4220/4320
Timer0 ..............................................................................117
16-bit Mode Timer Reads and Writes ......................119
Associated Registers ...............................................119
Clock Source Edge Select (T0SE Bit) ......................119
Clock Source Select (T0CS Bit) ...............................119
Interrupt ....................................................................119
Operation .................................................................119
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment ..............................119
Timer1 ..............................................................................121
16-bit Read/Write Mode ...........................................124
Associated Registers ...............................................125
Interrupt ....................................................................124
Operation .................................................................122
Oscillator .......................................................... 121, 123
Oscillator Layout Considerations .............................123
Overflow Interrupt .....................................................121
Resetting, Using a Special Event
Trigger Output (CCP) .......................................124
Special Event Trigger (CCP) ....................................136
TMR1H Register ......................................................121
TMR1L Register .......................................................121
Use as a Real-Time Clock .......................................124
Timer2 ..............................................................................127
Associated Registers ...............................................128
Operation .................................................................127
Postscaler. See Postscaler, Timer2.
Capture/Compare/PWM (CCP) ............................... 330
CLKO and I/O .......................................................... 327
Clock Synchronization ............................................. 175
Clock, Instruction Cycle ............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 332
Example SPI Master Mode (CKE = 1) ..................... 333
Example SPI Slave Mode (CKE = 0) ....................... 334
Example SPI Slave Mode (CKE = 1) ....................... 335
External Clock (All Modes except PLL) ................... 325
Fail-Safe Clock Monitor (FSCM) .............................. 249
First Start Bit ............................................................ 183
Full-Bridge PWM Output .......................................... 146
Half-Bridge PWM Output ......................................... 145
2
I C Bus Data ............................................................ 336
2
I C Bus Start/Stop Bits ............................................ 336
2
I C Master Mode (Transmission,
7 or 10-bit Address) ......................................... 186
I C Slave Mode (Transmission, 10-bit Address) ...... 173
I C Slave Mode (Transmission, 7-bit Address) ........ 171
I C Slave Mode with SEN = 0
2
2
2
(Reception, 10-bit Address) ............................. 172
I C Slave Mode with SEN = 0
2
(Reception, 7-bit Address) ............................... 170
I C Slave Mode with SEN = 1
2
(Reception, 10-bit Address) ............................. 177
I C Slave Mode with SEN = 1
2
(Reception, 7-bit Address) ............................... 176
Low-Voltage Detect ................................................. 234
Low-Voltage Detect Characteristics ......................... 322
PR2 Register .................................................... 127, 138
Prescaler. See Prescaler, Timer2.
2
SSP Clock Shift ................................................ 127, 128
TMR2 Register .........................................................127
TMR2 to PR2 Match Interrupt .................. 127, 128, 138
Timer3 ..............................................................................129
Associated Registers ...............................................131
Operation .................................................................130
Oscillator .......................................................... 129, 131
Overflow Interrupt ............................................. 129, 131
Resetting, Using a Special Event
Trigger Output (CCP) .......................................131
TMR3H Register ......................................................129
TMR3L Register .......................................................129
Timing Diagrams
Master SSP I C Bus Data ........................................ 338
2
Master SSP I C Bus Start/Stop Bits ........................ 338
Parallel Slave Port (PIC18F4X20) ........................... 331
Parallel Slave Port (PSP) Read ............................... 115
Parallel Slave Port (PSP) Write ............................... 115
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 151
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 151
PWM Direction Change ........................................... 148
PWM Direction Change at Near
100% Duty Cycle ............................................. 148
PWM Output ............................................................ 138
Repeat Start Condition ............................................ 184
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 328
Slave Mode General Call Address
Sequence (7 or 10-bit Address Mode) ............. 178
Slave Synchronization ............................................. 161
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 51
SPI Mode (Master Mode) ......................................... 160
SPI Mode (Slave Mode with CKE = 0) ..................... 162
SPI Mode (Slave Mode with CKE = 1) ..................... 162
Stop Condition Receive or Transmit Mode .............. 188
Synchronous Transmission ..................................... 206
Synchronous Transmission (Through TXEN) .......... 207
Time-out Sequence on POR w/
A/D Conversion ........................................................342
Acknowledge Sequence ...........................................188
Asynchronous Reception .........................................205
Asynchronous Transmission ....................................203
Asynchronous Transmission (Back to Back) ............203
Baud Rate Generator with Clock Arbitration ............182
BRG Reset Due to SDA Arbitration
During Start Condition ......................................191
Brown-out Reset (BOR) ...........................................328
Bus Collision During a Repeated
Start Condition (Case 1) ..................................192
Bus Collision During a Repeated
Start Condition (Case 2) ..................................192
Bus Collision During a Stop Condition
(Case 1) ...........................................................193
Bus Collision During a Stop Condition
(Case 2) ...........................................................193
Bus Collision During Start Condition
PLL Enabled (MCLR Tied to VDD) ..................... 51
Time-out Sequence on Power-up
(SCL = 0) ..........................................................191
Bus Collision During Start Condition
(MCLR Not Tied to VDD): Case 1 ....................... 50
Time-out Sequence on Power-up
(SDA Only) .......................................................190
Bus Collision for Transmit and
(MCLR Not Tied to VDD): Case 2 ....................... 50
Time-out Sequence on Power-up
Acknowledge ....................................................189
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 50
DS39599C-page 380
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Timer0 and Timer1 External Clock .......................... 329
U
Transition for Entry to SEC_IDLE Mode .................... 34
Transition for Entry to SEC_RUN Mode .................... 36
Transition for Entry to Sleep Mode ............................ 32
Transition for Two-Speed Start-up
USART ............................................................................. 195
Asynchronous Mode ................................................ 202
Associated Registers, Receive ........................ 205
Associated Registers, Transmit ....................... 203
Receiver .......................................................... 204
Transmitter ...................................................... 202
Baud Rate Generator (BRG) ................................... 198
Associated Registers ....................................... 198
Baud Rate Formula ......................................... 198
Baud Rates, Asynchronous Mode
(INTOSC to HSPLL) ......................................... 247
Transition for Wake from PRI_IDLE Mode ................. 33
Transition for Wake from RC_RUN Mode
(RC_RUN to PRI_RUN) ..................................... 35
Transition for Wake from SEC_RUN Mode
(HSPLL) ............................................................. 34
Transition for Wake from Sleep (HSPLL) ................... 32
Transition to PRI_IDLE Mode .................................... 33
Transition to RC_IDLE Mode ..................................... 35
Transition to RC_RUN Mode ..................................... 37
USART Synchronous Receive
(BRGH = 0, Low Speed) .......................... 199
Baud Rates, Asynchronous Mode
(BRGH = 1, High Speed) ......................... 200
Baud Rates, Synchronous Mode
(SYNC = 1) .............................................. 201
High Baud Rate Select (BRGH Bit) ................. 198
Operation in Power Managed Mode ................ 198
Sampling .......................................................... 198
Serial Port Enable (SPEN Bit) ................................. 195
Setting Up 9-bit Mode with Address Detect ............. 204
Synchronous Master Mode ...................................... 206
Associated Registers, Reception ..................... 208
Associated Registers, Transmit ....................... 207
Reception ........................................................ 208
Transmission ................................................... 206
Synchronous Slave Mode ........................................ 209
Associated Registers, Receive ........................ 210
Associated Registers, Transmit ....................... 209
Reception ........................................................ 210
Transmission ................................................... 209
(Master/Slave) .................................................. 340
USART Synchronous Reception
(Master Mode, SREN) ...................................... 208
USART SynchronousTransmission
(Master/Slave) .................................................. 340
Timing Diagrams and Specifications ................................ 325
A/D Conversion Requirements ................................ 342
Capture/Compare/PWM Requirements ................... 330
CLKO and I/O Requirements ................................... 327
DC Characteristics - Internal RC Accuracy .............. 326
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 332
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 333
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 334
Example SPI Slave Mode Requirements
V
(CKE = 1) ......................................................... 335
External Clock Requirements .................................. 325
Voltage Reference Specifications .................................... 321
2
W
I C Bus Data Requirements (Slave Mode) .............. 337
2
Master SSP I C Bus Data Requirements ................ 339
Watchdog Timer (WDT) ............................................237, 245
Associated Registers ............................................... 246
Control Register ....................................................... 245
During Oscillator Failure .......................................... 248
Programming Considerations .................................. 245
WCOL .............................................................................. 183
WCOL Status Flag ............................................183, 185, 188
WWW, On-Line Support ...................................................... 5
2
Master SSP I C Bus Start/Stop Bits
Requirements ................................................... 338
Parallel Slave Port Requirements (PIC18F4X20) .... 331
PLL Clock ................................................................. 326
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer
and Brown-out Reset Requirements ................ 328
Timer0 and Timer1 External Clock
X
Requirements ................................................... 329
USART Synchronous Receive
XORLW ............................................................................ 296
XORWF ........................................................................... 297
Requirements ................................................... 340
USART Synchronous Transmission
Requirements ................................................... 340
Top-of-Stack Access .......................................................... 54
TRISE Register
PSPMODE Bit .......................................................... 109
TSTFSZ ............................................................................ 296
Two-Speed Start-up ................................................. 237, 247
Two-Word Instructions
Example Cases .......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 198
2003 Microchip Technology Inc.
DS39599C-page 381
PIC18F2220/2320/4220/4320
NOTES:
DS39599C-page 382
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
ON-LINE SUPPORT
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
Microchip provides on-line support on the Microchip
World Wide Web site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits. The Hot Line
Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2003 Microchip Technology Inc.
DS39599C-page 383
PIC18F2220/2320/4220/4320
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC18F2220/2320/4220/4320
DS39599C
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39599C-page 384
2003 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
PIC18F2220/2320/4220/4320 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
−
Examples:
Temperature Package
Range
Pattern
a) PIC18LF4320-I/P 301 = Industrial temp.,
PDIP package, Extended VDD limits,
QTP pattern #301.
b) PIC18LF2220-I/SO = Industrial temp.,
SOIC package, Extended VDD limits.
c) PIC18F4220-I/P = Industrial temp., PDIP
package, normal VDD limits.
(1)
Device
PIC18F2220/2320/4220/4320
PIC18F2220/2320/4220/4320T
VDD range 4.2V to 5.5V
,
(1,2)
;
(1)
PIC18LF2220/2320/4220/4320
PIC18LF2220/2320/4220/4320T
VDD range 2.0V to 5.5V
,
(1,2)
;
Temperature
Range
I
=
-40°C to +85°C (Industrial)
Note 1:
2:
F
= Standard Voltage Range
LF = Wide Voltage Range
T
= in tape and reel – SOIC
and TQFP packages only.
Package
PT
SO
SP
P
=
=
=
=
=
TQFP (Thin Quad Flatpack)
SOIC
Skinny Plastic DIP
PDIP
QFN
ML
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2003 Microchip Technology Inc.
DS39599C-page 385
WORLDWIDE SALES AND SERVICE
Korea
AMERICAS
ASIA/PACIFIC
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
China - Beijing
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
Atlanta
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Boston
China - Chengdu
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
Fax: 86-28-86766599
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Dallas
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
China - Shunde
Fax: 248-538-2260
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
Kokomo
France
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Phoenix
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966
Fax: 480-792-4338
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
San Jose
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Fax: 408-436-7955
India
Toronto
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Fax: 905-673-6509
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
07/28/03
DS39599C-page 386
2003 Microchip Technology Inc.
相关型号：
PIC18F2320-I/ML
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2320-I/P
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2320-I/PT
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2320-I/SO
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2320-I/SOG
8-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PDSO28, 0.300 INCH, PLASTIC, MS-013, SO-28
MICROCHIP
PIC18F2320-I/SP
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2320-I/SPREL
8-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28
MICROCHIP
PIC18F2320T
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2320T-E/SO
8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PDSO28, 0.300 INCH, PLASTIC, MS-013, SO-28
MICROCHIP
PIC18F2320T-E/SOG
8-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PDSO28, 0.300 INCH, PLASTIC, MS-013, SO-28
MICROCHIP
PIC18F2320T-I/ML
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2320T-I/P
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
MICROCHIP
©2020 ICPDF网 联系我们和版权申明