PIC18F2553T-I/SP [MICROCHIP]
FLASH, 48 MHz, MICROCONTROLLER, PDIP28, DIP-28;型号: | PIC18F2553T-I/SP |
厂家: | MICROCHIP |
描述: | FLASH, 48 MHz, MICROCONTROLLER, PDIP28, DIP-28 光电二极管 |
文件: | 总46页 (文件大小:829K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC18F2458/2553/4458/4553
Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash, USB Microcontrollers
with 12-Bit A/D and nanoWatt Technology
© 2009 Microchip Technology Inc.
DS39887C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
32
PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39887C-page 2
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
28/40/44-Pin High-Performance, Enhanced Flash, USB
Microcontrollers with 12-Bit A/D and nanoWatt Technology
Universal Serial Bus Features:
Flexible Oscillator Structure:
• USB V2.0 Compliant
• Four Crystal modes, Including High-Precision PLL
for USB
• Two External Clock modes, up to 48 MHz
• Internal Oscillator Block:
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control, Interrupt, Isochronous and Bulk
Transfers
• Supports up to 32 Endpoints (16 bidirectional)
• 1-Kbyte Dual Access RAM for USB
• On-Chip USB Transceiver with On-Chip Voltage
Regulator
• Interface for Off-Chip USB Transceiver
• Streaming Parallel Port (SPP) for USB Streaming
Transfers (40/44-pin devices only)
- 8 user-selectable frequencies, from 31 kHz
to 8 MHz
- User-tunable to compensate for frequency drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Dual Oscillator Options allow Microcontroller and
USB module to Run at Different Clock Speeds
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Power-Managed Modes:
• Run: CPU On, Peripherals On
• Idle: CPU Off, Peripherals On
Peripheral Highlights:
• High-Current Sink/Source: 25 mA/25 mA
• Three External Interrupts
• Four Timer modules (Timer0 to Timer3)
• Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 5.2 ns (TCY/16)
- Compare is 16-bit, max. resolution 83.3 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bits
• Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
• Sleep: CPU Off, Peripherals Off
• Idle mode Currents Down to 5.8 μA Typical
• Sleep mode Currents Down to 0.1 μA Typical
• Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V
• Watchdog Timer: 2.1 μA Typical
• Two-Speed Oscillator Start-up
Special Microcontroller Features:
• C Compiler Optimized Architecture with Optional
- Selectable polarity
Extended Instruction Set
- Programmable dead time
- Auto-shutdown and auto-restart
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Enhanced USART module:
- LIN bus support
• Flash/Data EEPROM Retention: > 40 Years
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I2C™
Master and Slave modes
• 12-Bit, up to 13-Channel Analog-to-Digital Converter
module (A/D) with Programmable Acquisition Time
• Dual Analog Comparators with Input Multiplexing
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
• Programmable Code Protection
• Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Optional Dedicated ICD/ICSP Port (44-pin TQFP
package only)
Note:
This document is supplemented by
the “PIC18F2455/2550/4455/4550 Data
Sheet” (DS39632). See Section 1.0
“Device Overview”.
• Wide Operating Voltage Range (2.0V to 5.5V)
Program Memory
Data Memory
MSSP
12-Bit CCP/ECCP
Timers
8/16-Bit
Device
I/O
SPP
Flash # Single-Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
Master
A/D (ch)
(PWM)
SPI
2
I C™
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
24K
32K
24K
32K
12288
16384
12288
16384
24
35
10
13
2/0
1/1
No
2048
256
Y
Y
1
2
1/3
Yes
© 2009 Microchip Technology Inc.
DS39887C-page 3
PIC18F2458/2553/4458/4553
Pin Diagrams
28-Pin SPDIP, SOIC
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP/RE3
RA0/AN0
2
RA1/AN1
3
4
5
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
VSS
6
7
8
9
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1
VSS
10
11
12
13
14
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
VUSB
40-Pin PDIP
MCLR/VPP/RE3
RA0/AN0
40
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
1
2
3
4
5
6
7
8
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VDD
9
VSS
10
11
12
13
14
15
16
17
18
19
20
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1/P1A
VUSB
RD0/SPP0
RD1/SPP1
RD2/SPP2
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
DS39887C-page 4
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
Pin Diagrams (Continued)
44-Pin TQFP
(2)
NC/ICRST(2)/ICVPP
33
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
VSS
1
2
3
4
5
6
7
8
9
10
11
32
31
30
29
28
27
26
25
24
23
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
PIC18F4458
PIC18F4553
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
44-Pin QFN
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VSS
VDD
RC7/RX/DT/SDO
RD4/SPP4
1
2
3
4
5
6
7
8
9
10
11
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
PIC18F4458
PIC18F4553
VDD
VSS
VDD
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
Note 1:
2:
RB3 is the alternate pin for CCP2 multiplexing.
Special ICPORT features are available only in 44-pin TQFP packages. See Section 25.9 “Special ICPORT Features” in
the “PIC18F2455/2550/4455/4550 Data Sheet”’.
© 2009 Microchip Technology Inc.
DS39887C-page 5
PIC18F2458/2553/4458/4553
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 21
3.0 Special Features of the CPU...................................................................................................................................................... 31
4.0 Electrical Characteristics ............................................................................................................................................................ 33
5.0 Packaging Information................................................................................................................................................................ 37
Appendix A: Revision History............................................................................................................................................................... 39
Appendix B: Device Differences........................................................................................................................................................... 39
Appendix C: Migration From Mid-Range to Enhanced Devices........................................................................................................... 40
Appendix D: Migration From High-End to Enhanced Devices ............................................................................................................. 40
Index .................................................................................................................................................................................................... 41
The Microchip Web Site....................................................................................................................................................................... 43
Customer Change Notification Service ................................................................................................................................................ 43
Customer Support................................................................................................................................................................................ 43
Reader Response ................................................................................................................................................................................ 44
Product Identification System............................................................................................................................................................... 45
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
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DS39887C-page 6
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
1.2
Details on Individual Family
Members
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
The PIC18F2458/2553/4458/4553 devices are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
• PIC18F2458
• PIC18F2553
• PIC18F4458
• PIC18F4553
The devices are differentiated from each other in the
following ways:
Note:
This data sheet documents only the
devices’ features and specifications that are
in addition to the features and specifica-
tions of the PIC18F2455/2550/4455/4550
devices. For information on the features
1. Flash program memory (24 Kbytes for
PIC18FX458
devices,
32 Kbytes
for
PIC18FX553).
2. A/D channels (10 for 28-pin devices, 13 for
40-pin and 44-pin devices).
and
the PIC18F2458/2553/4458/4553
PIC18F2455/2550/4455/4550
specifications
shared
by
and
3. I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40-pin and 44-pin devices).
devices,
see the “PIC18F2455/2550/4455/4550
Data Sheet” (DS39632).
4. CCP and Enhanced CCP implementation
(28-pin devices have two standard CCP
modules, 40-pin and 44-pin devices have one
standard CCP module and one ECCP module).
The PIC18F4553 family of devices offers the advan-
tages of all PIC18 microcontrollers – namely, high
computational performance at an economical price –
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F4553 family introduces design enhancements
that make these microcontrollers a logical choice for
many high-performance, power sensitive applications.
5. Streaming Parallel Port (present only on
40/44-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
1.1
Special Features
Members of the PIC18F4553 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2458),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2458), function over an extended VDD range
of 2.0V to 5.5V.
• 12-Bit A/D Converter: The PIC18F4553 family
implements a 12-bit A/D Converter. The A/D
Converter incorporates programmable acquisi-
tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting
for a sampling period and thus, reducing code
overhead.
© 2009 Microchip Technology Inc.
DS39887C-page 7
PIC18F2458/2553/4458/4553
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
Operating Frequency
DC – 48 MHz
24576
DC – 48 MHz
32768
DC – 48 MHz
24576
DC – 48 MHz
32768
Program Memory (Bytes)
Program Memory
(Instructions)
12288
16384
12288
16384
Data Memory (Bytes)
2048
256
2048
256
2048
256
2048
256
Data EEPROM Memory
(Bytes)
Interrupt Sources
I/O Ports
19
19
20
20
Ports A, B, C, (E)
Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers
4
2
4
2
4
1
4
1
Capture/Compare/PWM
Modules
Enhanced Capture/
0
0
1
1
Compare/PWM Modules
Serial Communications
MSSP,
MSSP,
MSSP,
MSSP,
Enhanced USART Enhanced USART Enhanced USART Enhanced USART
Universal Serial Bus (USB)
Module
1
1
1
1
Streaming Parallel Port (SPP)
No
No
Yes
Yes
12-Bit Analog-to-Digital
Converter Module
10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Comparators
2
2
2
2
Resets (and Delays)
POR, BOR, WDT,
POR, BOR, WDT,
POR, BOR, WDT,
POR, BOR, WDT,
RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,
Stack Full, Stack
Underflow, MCLR
(optional),
Stack Full, Stack
Underflow, MCLR
(optional),
Stack Full, Stack
Underflow, MCLR
(optional),
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
Programmable High/
Low-Voltage Detect
Yes
Yes
Yes
Yes
Programmable Brown-out
Reset
Yes
Yes
Yes
Yes
Instruction Set
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
Packages
28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
Corresponding Devices with
10-Bit A/D
PIC18F2455
PIC18F2550
PIC18F4455
PIC18F4550
DS39887C-page 8
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
FIGURE 1-1:
PIC18F2458/2553 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
PORTA
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
21
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Data Memory
(2 Kbytes)
PCLATU PCLATH
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(24/32 Kbytes)
12
Data Latch
PORTB
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
8
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
8 x 8 Multiply
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(3)/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
3
8
OSC1(2)
OSC2(2)
T1OSI
Power-up
Timer
Internal
Oscillator
Block
BITOP
8
W
8
8
Oscillator
Start-up Timer
RC6/TX/CK
RC7/RX/DT/SDO
INTRC
Oscillator
8
8
Power-on
Reset
8 MHz
Oscillator
ALU<8>
8
Watchdog
Timer
T1OSO
Brown-out
Reset
MCLR(1)
VDD,VSS
Single-Supply
Programming
In-Circuit
Fail-Safe
Clock Monitor
Debugger
PORTE
Band Gap
Reference
USB Voltage
Regulator
VUSB
MCLR/VPP/RE3(1)
BOR
HLVD
Data
EEPROM
Timer0
Timer1
MSSP
Timer2
Timer3
ADC
12-Bit
EUSART
USB
Comparator
CCP1
CCP2
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: RB3 is the alternate pin for CCP2 multiplexing.
© 2009 Microchip Technology Inc.
DS39887C-page 9
PIC18F2458/2553/4458/4553
FIGURE 1-2:
PIC18F4458/4553(40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
21
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6
Data Memory
(2 Kbytes)
PCLATU PCLATH
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
31 Level Stack
STKPTR
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(4)/VPO
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
4
BSR
12
4
Address Latch
Access
Bank
FSR0
FSR1
FSR2
Program Memory
(24/32 Kbytes)
12
Data Latch
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
8
Table Latch
PORTC
Address
Decode
ROM Latch
IR
Instruction Bus <16>
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
8
RC6/TX/CK
RC7/RX/DT/SDO
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
8 x 8 Multiply
PORTD
3
VDD, VSS
8
Internal
Power-up
Timer
RD0/SPP0:RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
Oscillator
Block
OSC1(2)
OSC2(2)
T1OSI
BITOP
8
W
8
8
Oscillator
Start-up Timer
INTRC
Oscillator
RD7/SPP7/P1D
8
8
Power-on
Reset
8 MHz
Oscillator
T1OSO
ALU<8>
8
Watchdog
Timer
ICPGC(3)
ICPGD(3)
ICPORTS(3)
ICRST(3)
MCLR(1)
Single-Supply
Programming
Brown-out
Reset
PORTE
In-Circuit
Debugger
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
MCLR/VPP/RE3(1)
Fail-Safe
Clock Monitor
Band Gap
Reference
USB Voltage
Regulator
VUSB
BOR
HLVD
Data
EEPROM
Timer0
Timer1
MSSP
Timer2
Timer3
ADC
12-Bit
EUSART
Comparator
ECCP1
CCP2
USB
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
3: These pins are only available on 44-pin TQFP packages under certain conditions.
4: RB3 is the alternate pin for CCP2 multiplexing.
DS39887C-page 10
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-2:
PIC18F2458/2553 PINOUT I/O DESCRIPTIONS
Pin
Number
Pin Buffer
Type Type
Pin Name
Description
SPDIP,
SOIC
MCLR/VPP/RE3
MCLR
1
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
ST
VPP
RE3
P
I
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
9
Oscillator crystal or external clock input.
I
I
Analog
Analog
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
CLKI
OSC2/CLKO/RA6
OSC2
10
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
CLKO
RA6
I/O
TTL
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2009 Microchip Technology Inc.
DS39887C-page 11
PIC18F2458/2553/4458/4553
TABLE 1-2:
PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number
Pin Buffer
Type Type
Pin Name
Description
SPDIP,
SOIC
PORTA is a bidirectional I/O port.
2
RA0/AN0
RA0
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
3
4
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-/CVREF
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
CVREF
I
I
O
Analog
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
5
6
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI/C1OUT/RCV
RA4
I/O
ST
ST
—
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
T0CKI
C1OUT
RCV
I
O
I
TTL
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
7
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
AN4
SS
HLVDIN
C2OUT
RA6
—
—
—
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
DS39887C-page 12
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-2:
PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number
Pin Buffer
Type Type
Pin Name
Description
SPDIP,
SOIC
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/FLT0/
21
SDI/SDA
RB0
I/O
I
I
I
I
TTL
Analog
ST
ST
ST
Digital I/O.
AN12
INT0
FLT0
SDI
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.
SDA
I/O
ST
I2C™ data I/O.
RB1/AN10/INT1/SCK/
22
SCL
RB1
AN10
INT1
SCK
SCL
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
23
24
RB2
AN8
INT2
VMO
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
O
—
RB3/AN9/CCP2/VPO
RB3
I/O
I
I/O
O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
AN9
CCP2(1)
VPO
—
RB4/AN11/KBI0
RB4
25
26
27
28
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
AN11
KBI0
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
KBI1
PGM
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2009 Microchip Technology Inc.
DS39887C-page 13
PIC18F2458/2553/4458/4553
TABLE 1-2:
PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number
Pin Buffer
Type Type
Pin Name
Description
SPDIP,
SOIC
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
11
12
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2/UOE
RC1
I/O
I
I/O
—
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
T1OSI
CCP2(2)
UOE
—
RC2/CCP1
RC2
13
15
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture 1 input/Compare 1 output/PWM1 output.
RC4/D-/VM
RC4
D-
VM
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
16
17
18
RC5
D+
VP
I
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
I/O
O
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
SDO
RE3
—
—
—
See MCLR/VPP/RE3 pin.
VUSB
14
Internal USB transceiver power supply.
When the internal USB regulator is enabled, VUSB is the
regulator output.
O
P
—
—
When the internal USB regulator is disabled, VUSB is the
power input for the USB transceiver.
VSS
VDD
8, 19
20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
CMOS = CMOS compatible input or output
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
DS39887C-page 14
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
1
18
18
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
ST
VPP
RE3
P
I
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
13
14
32
33
30
31
Oscillator crystal or external clock input.
I
I
Analog
Analog
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
CLKI
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
O
O
—
—
CLKO
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc.
DS39887C-page 15
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Description
Type Type
PDIP QFN TQFP
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
2
3
4
19
20
21
19
20
21
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-/
CVREF
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
CVREF
I
I
O
Analog
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
5
6
22
23
22
23
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI/C1OUT/
RCV
RA4
I/O
ST
ST
—
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
T0CKI
C1OUT
RCV
I
O
I
TTL
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
7
24
—
24
—
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
AN4
SS
HLVDIN
C2OUT
RA6
—
—
—
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39887C-page 16
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTB is a bidirectional I/O port. PORTB can be soft-
ware programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
33
34
9
8
I/O
I
I
I
I
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 12.
AN12
INT0
FLT0
SDI
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.
SDA
I/O
ST
I2C™ data I/O.
RB1/AN10/INT1/SCK/
10
9
SCL
RB1
AN10
INT1
SCK
SCL
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
35
36
11
12
14
10
11
14
RB2
AN8
INT2
VMO
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
O
—
RB3/AN9/CCP2/VPO
RB3
I/O
I
I/O
O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
AN9
CCP2(1)
VPO
—
RB4/AN11/KBI0/CSSPP 37
RB4
AN11
KBI0
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.
CSSPP
O
—
RB5/KBI1/PGM
RB5
38
39
40
15
16
17
15
16
17
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
KBI1
PGM
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc.
DS39887C-page 17
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Description
Type Type
PDIP QFN TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
15
16
34
35
32
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2/
UOE
RC1
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
T1OSI
CCP2(2)
UOE
—
RC2/CCP1/P1A
RC2
17
23
24
25
26
36
42
43
44
1
36
42
43
44
1
I/O
I/O
O
ST
ST
TTL
Digital I/O.
CCP1
P1A
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 PWM output, channel A.
RC4/D-/VM
RC4
D-
VM
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
I
I/O
I
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX
CK
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
SDO
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39887C-page 18
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). PORTD can be software
programmed for internal weak pull-ups on all inputs.
These pins have TTL input buffers when the SPP
module is enabled.
RD0/SPP0
RD0
19
20
21
22
27
28
38
39
40
41
2
38
39
40
41
2
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
SPP0
RD1/SPP1
RD1
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
SPP1
RD2/SPP2
RD2
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
SPP2
RD3/SPP3
RD3
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
SPP3
RD4/SPP4
RD4
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
SPP4
RD5/SPP5/P1B
RD5
3
3
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel B.
SPP5
P1B
RD6/SPP6/P1C
RD6
29
30
4
5
4
5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel C.
SPP6
P1C
RD7/SPP7/P1D
RD7
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel D.
SPP7
P1D
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc.
DS39887C-page 19
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Description
Type Type
PDIP QFN TQFP
PORTE is a bidirectional I/O port.
RE0/AN5/CK1SPP
RE0
8
9
25
26
27
—
25
26
27
—
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 5.
SPP clock 1 output.
AN5
CK1SPP
RE1/AN6/CK2SPP
RE1
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
SPP clock 2 output.
AN6
CK2SPP
RE2/AN7/OESPP
RE2
10
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
SPP output enable output.
AN7
OESPP
RE3
VSS
—
—
P
—
—
See MCLR/VPP/RE3 pin.
12, 6, 30, 6, 29
31 31
Ground reference for logic and I/O pins.
VDD
11, 32 7, 8, 7, 28
28, 29
P
—
Positive supply for logic and I/O pins.
VUSB
18
37
37
Internal USB transceiver power supply.
When the internal USB regulator is enabled, VUSB is
the regulator output.
O
P
—
—
When the internal USB regulator is disabled, VUSB
is the power input for the USB transceiver.
NC/ICCK/ICPGC(3)
ICCK
ICPGC
NC/ICDT/ICPGD(3)
—
—
—
—
—
—
—
—
—
13
12
13
33
34
—
No Connect or dedicated ICD/ICSP™ port clock.
In-Circuit Debugger clock.
I/O
I/O
ST
ST
ICSP programming clock.
No Connect or dedicated ICD/ICSP port clock.
In-Circuit Debugger data.
ICDT
ICPGD
I/O
I/O
ST
ST
ICSP programming data.
(3)
NC/ICRST/ICVPP
No Connect or dedicated ICD/ICSP port Reset.
Master Clear (Reset) input.
ICRST
ICVPP
NC/ICPORTS(3)
I
P
—
—
Programming voltage input.
P
—
No Connect or 28-pin device emulation.
Enable 28-pin device emulation when connected
to VSS.
ICPORTS
NC
—
—
No Connect.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39887C-page 20
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
The ADCON0 register, shown in Register 2-1, controls
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
The Analog-to-Digital (A/D) Converter module has
10 inputs for the 28-pin devices and 13 for the 40-pin
and 44-pin devices. This module allows conversion of an
analog input signal to a corresponding 12-bit digital
number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
REGISTER 2-1:
ADCON0: A/D CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-2
Unimplemented: Read as ‘0’
CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)(1,2)
0110= Channel 6 (AN6)(1,2)
0111= Channel 7 (AN7)(1,2)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12
1101= Unimplemented(2)
1110= Unimplemented(2)
1111= Unimplemented(2)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D Converter module is enabled
0= A/D Converter module is disabled
Note 1: These channels are not implemented on 28-pin devices.
2: Performing a conversion on unimplemented channels will return a floating input measurement.
© 2009 Microchip Technology Inc.
DS39887C-page 21
PIC18F2458/2553/4458/4553
REGISTER 2-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W(1)
R/W(1)
R/W(1)
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= VSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= VDD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3:
PCFG0
0000(1)
0001
0010
0011
0100
0101
0110
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Note 1: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40-pin and 44-pin devices.
DS39887C-page 22
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
REGISTER 2-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
bit 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
© 2009 Microchip Technology Inc.
DS39887C-page 23
PIC18F2458/2553/4458/4553
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and the A/D Interrupt Flag bit, ADIF, is set. The
block diagram of the A/D module is shown in Figure 2-1.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
Converter, which generates the result via successive
approximation.
FIGURE 2-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
0011
(Input Voltage)
12-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
0000
VDD
AN0
X0
VREF+
VREF-
X1
1X
0X
Reference
Voltage
VSS
Note 1: Channels AN5 through AN7 are not available on 28-pin devices.
DS39887C-page 24
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets,
and is not affected by any other Reset.
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 2-2:
A/D TRANSFER FUNCTION
The following steps should be followed to perform an A/D
conversion:
FFFh
FFEh
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
003h
002h
001h
000h
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
Analog Input Voltage
FIGURE 2-3:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
5 pF
CHOLD = 25 pF
VSS
VAIN
ILEAKAGE
±100 nA
VT = 0.6V
Legend: CPIN
= Input Capacitance
= Threshold Voltage
6V
5V
4V
3V
2V
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
VDD
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
RSS
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
1
2
3
4
Sampling Switch (kΩ)
© 2009 Microchip Technology Inc.
DS39887C-page 25
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To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
2.1
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
Example 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 4 kΩ
85°C (system max.)
the minimum acquisition time before starting
conversion.
a
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 2-1:
ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 2-2:
A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
-(CHOLD)(RIC + RSS + RS) ln(1/4096)
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 µs
(Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ
=
0.2 µs + 1.56 μs + 1.2 µs
2.96 µs
DS39887C-page 26
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
2.2
Selecting and Configuring
Acquisition Time
2.3
Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provides a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisi-
tion time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
Manual
acquisition
is
selected
when
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (see parameter 130 for more
information).
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
Table 2-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 2-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Assumes TAD Min. = 0.8 μs
A/D Clock Source (TAD)
Operation
ADCS2:ADCS0
Maximum FOSC
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(1)
000
100
001
101
010
110
x11
2.50 MHz
5.00 MHz
10.00 MHz
20.00 MHz
40.00 MHz
48.00 MHz
1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 2.5 μs.
2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.
© 2009 Microchip Technology Inc.
DS39887C-page 27
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2.4
Operation in Power-Managed
Modes
2.5
Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After
entering the mode, an A/D acquisition or conversion
may be started. Once started, the device should
continue to be clocked by the same clock source until
the conversion has been completed.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a dig-
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by control-
ling how the PCFG3:PCFG0 bits in
ADCON1 are reset.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN bit
(OSCCON<7>) must have already been cleared prior
to starting the conversion.
DS39887C-page 28
© 2009 Microchip Technology Inc.
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After the A/D conversion is completed or aborted, a
2 TCY wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
2.6
A/D Conversions
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’, and selecting a
4 TAD acquisition time before the conversion starts.
2.7
Discharge
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
FIGURE 2-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
b6
b3
b2
b1
b0
b11 b10
b9
Conversion starts
b8
b7
b5
b4
Discharge
(typically 200 ns)
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 2-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
6
7
8
9
10
b4 b3
11
b2
12
b1 b0
13 TAD1
1
2
3
4
1
2
3
4
5
b9
b8
b5
b10
b7
b6
b11
Automatic
Acquisition
Time
Discharge
(typically
200 ns)
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
© 2009 Microchip Technology Inc.
DS39887C-page 29
PIC18F2458/2553/4458/4553
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate TACQ
time selected before the Special Event Trigger sets the
GO/DONE bit (starts a conversion).
2.8
Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion, and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automatically
repeat the A/D acquisition period with minimal software
overhead (firmware must move ADRESH:ADRESL to
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 2-2:
Name
REGISTERS ASSOCIATED WITH A/D OPERATION
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
RBIE
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
RBIF
SPPIF(1)
SPPIE(1)
SPPIP(1)
OSCFIF
OSCFIE
OSCFIP
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
IPR1
PIR2
PIE2
RCIP
USBIF
USBIE
USBIP
IPR2
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0
ADCON1
ADCON2
PORTA
TRISA
—
—
—
—
CHS3
VCFG1
ACQT2
RA5
CHS2
VCFG0
ACQT1
RA4
CHS1
PCFG3
ACQT0
RA3
CHS0 GO/DONE ADON
21
22
PCFG2
ADCS2
RA2
PCFG1
ADCS1
RA1
PCFG0
ADCS0
RA0
ADFM
—
—
RA6(2)
23
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
—
TRISA6(2) PORTA Data Direction Control Register
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
LATB
PORTE(1)
TRISE(1)
LATE(1)
RDPU
—
—
—
—
—
—
—
—
—
—
RE3(3)
RE2(1)
RE1(1)
RE0(1)
—
TRISE2
TRISE1
TRISE0
—
—
PORTE Data Latch Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’.
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: For these Reset values, see the “PIC18F2455/2550/4455/4550 Data Sheet”.
DS39887C-page 30
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
3.1
Device ID Registers
3.0
SPECIAL FEATURES OF THE
CPU
The Device ID registers are “read-only” registers.
They identify the device type and revision to device
programmers, and can be read by firmware using
table reads.
Note:
For additional details on the Con-
figuration
bits,
refer
to
the
“PIC18F2455/2550/4455/4550 Data Sheet”,
Section 25.1 “Configuration Bits”. Device
ID information presented in this section is for
PIC18F2458/2553/4458/4553 only.
PIC18F2458/2553/4458/4553 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Device ID Registers
TABLE 3-1:
DEVICE IDs
Default/
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unprogrammed
Value
(1)
3FFFFEh DEVID1
3FFFFFh DEVID2
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(1)
DEV10
xxxx xxxx
Legend:
x= unknown, u= unchanged
Note 1: See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.
© 2009 Microchip Technology Inc.
DS39887C-page 31
PIC18F2458/2553/4458/4553
REGISTER 3-1:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2458/2553/4458/4553 DEVICES
R
DEV2
bit 7
R
R
R
R
R
R
R
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
bit 4-0
DEV2:DEV0: Device ID bits
See Register 3-2 for a complete listing.
REV3:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2458/2553/4458/4553 DEVICES
R
DEV10
bit 7
R
R
R
R
R
R
R
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-0
DEV10:DEV3: Device ID bits
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
Device
(DEVID1<7:5>)
0010 1010
0010 1010
0010 1010
0010 1010
011
010
001
000
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
DS39887C-page 32
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
4.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RE3 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2009 Microchip Technology Inc.
DS39887C-page 33
PIC18F2458/2553/4458/4553
FIGURE 4-1:
PIC18F2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F2458/2553/4458/4553
4.2V
3.5V
3.0V
2.5V
2.0V
48 MHz
Frequency
FIGURE 4-2:
PIC18LF2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18LF2458/2553/4458/4553
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
48 MHz
4 MHz
Frequency
For 2.0V ≤ VDD < 4.2V: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
For 4.2V ≤ VDD: FMAX = 48 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39887C-page 34
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 4-1:
A/D CONVERTER CHARACTERISTICS: PIC18F2458/2553/4458/4553 (INDUSTRIAL)
PIC18LF2458/2553/4458/4553 (INDUSTRIAL)
Param
Sym
No.
Characteristic
Min
Typ
Max
Units
Conditions
A01
A03
NR
EIL
Resolution
—
—
—
—
—
—
—
—
—
—
12
±2.0
bit
ΔVREF ≥ 3.0V
Integral Linearity Error
±1
LSB VDD = 3.0V ΔVREF ≥ 3.0V
LSB VDD = 5.0V
—
±2.0
A04
A06
A07
EDL
Differential Linearity Error
±1
+1.5/-1.0
+1.5/-1.0
±5
LSB VDD = 3.0V ΔVREF ≥ 3.0V
LSB VDD = 5.0V
—
EOFF Offset Error
±1
LSB VDD = 3.0V ΔVREF ≥ 3.0V
LSB VDD = 5.0V
—
±3
EGN
Gain Error
±1
±1.25
±2.00
LSB VDD = 3.0V ΔVREF ≥ 3.0V
LSB VDD = 5.0V
—
Guaranteed
—
(1)
A10
A20
—
Monotonicity
—
V
VSS ≤ VAIN ≤ VREF
ΔVREF Reference Voltage Range
3
VDD – VSS
For 12-bit resolution
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VREFL Reference Voltage Low
VSS + 3.0V
VSS – 0.3V
VREFL
—
—
—
—
VDD + 0.3V
VDD – 3.0V
VREFH
V
V
For 12-bit resolution
For 12-bit resolution
VAIN
ZAIN
Analog Input Voltage
V
Recommended
—
2.5
kΩ
Impedance of Analog
Voltage Source
(2)
A50
IREF
VREF Input Current
—
—
—
—
5
150
μA
μA
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
© 2009 Microchip Technology Inc.
DS39887C-page 35
PIC18F2458/2553/4458/4553
FIGURE 4-3:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
A/D CLK(1)
132
. . .
. . .
11
10
9
3
2
1
0
A/D DATA
NEW_DATA
TCY
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2:
A/D CONVERSION REQUIREMENTS
Characteristic
Param
No.
Symbol
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
PIC18FXXXX
0.8
1.4
12.5(1)
25.0(1)
μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX
μs VDD = 3.0V;
TOSC based, VREF full range
PIC18FXXXX
—
—
13
1
3
μs A/D RC mode
μs VDD = 3.0V; A/D RC mode
TAD
PIC18LFXXXX
131
TCNV
Conversion Time
14
(not including acquisition time)(2)
Acquisition Time(3)
132
135
137
TACQ
TSWC
TDIS
1.4
—
—
(Note 4)
—
μs
Switching Time from Convert → Sample
Discharge Time
0.2
μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
DS39887C-page 36
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
5.0
PACKAGING INFORMATION
For packaging information, see the “PIC18F2455/
2550/4455/4550 Data Sheet” (DS39632).
© 2009 Microchip Technology Inc.
DS39887C-page 37
PIC18F2458/2553/4458/4553
NOTES:
DS39887C-page 38
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (May 2007)
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for the PIC18F2458/2553/4458/
4553 devices.
Revision B (June 2007)
Changes to Figure 4-2: PIC18LF2458/2553/4458/4553
Voltage-Frequency Graph (Industrial).
Revision C (October 2009)
Removed “Preliminary” marking.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
24576
32768
16384
19
24576
12288
20
32768
16384
20
12288
19
I/O Ports
Ports A, B, C, (E)
Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Capture/Compare/PWM Modules
2
0
2
0
1
1
1
1
Enhanced Capture/Compare/
PWM Modules
Parallel Communications (SPP)
12-Bit Analog-to-Digital Module
Packages
No
No
Yes
Yes
10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
© 2009 Microchip Technology Inc.
DS39887C-page 39
PIC18F2458/2553/4458/4553
APPENDIX C: MIGRATION FROM
MID-RANGE TO
APPENDIX D: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”.
This Application Note is available as Literature Number
DS00726.
This Application Note is available as Literature Number
DS00716.
DS39887C-page 40
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
INDEX
A
M
A/D ..................................................................................... 21
A/D Converter Interrupt, Configuring ......................... 25
Acquisition Requirements .......................................... 26
ADCON0 Register ...................................................... 21
ADCON1 Register ...................................................... 21
ADCON2 Register ...................................................... 21
ADRESH Register ................................................ 21, 24
ADRESL Register ...................................................... 21
Analog Port Pins, Configuring .................................... 28
Associated Registers ................................................. 30
Calculating the Minimum Required Acquisition Time . 26
Configuring the Module .............................................. 25
Conversion Clock (TAD) ............................................. 27
Conversion Status (GO/DONE Bit) ............................ 24
Conversions ............................................................... 29
Converter Characteristics .......................................... 35
Discharge ................................................................... 29
Operation in Power-Managed Modes ........................ 28
Selecting and Configuring Acquisition Time .............. 27
Special Event Trigger (CCP) ...................................... 30
Use of the CCP2 Trigger ............................................ 30
Absolute Maximum Ratings ............................................... 33
ADCON0 Register .............................................................. 21
GO/DONE Bit ............................................................. 24
ADCON1 Register .............................................................. 21
ADCON2 Register .............................................................. 21
ADRESH Register .............................................................. 21
ADRESL Register ........................................................ 21, 24
Analog-to-Digital Converter. See A/D.
Microchip Internet Web Site ............................................... 43
Migration from High-End to Enhanced Devices ................. 40
Migration from Mid-Range to Enhanced Devices .............. 40
P
Packaging Information ....................................................... 37
Pin Functions
MCLR/VPP/RE3 ......................................................... 11
MCLR/VPP/RE3 ......................................................... 15
NC/ICCK/ICPGC ....................................................... 20
NC/ICDT/ICPGD ........................................................ 20
NC/ICPORTS ............................................................ 20
NC/ICRST/ICVPP ....................................................... 20
OSC1/CLKI .......................................................... 11, 15
OSC2/CLKO/RA6 ................................................ 11, 15
RA0/AN0 .............................................................. 12, 16
RA1/AN1 .............................................................. 12, 16
RA2/AN2/VREF-/CVREF ....................................... 12, 16
RA3/AN3/VREF+ .................................................. 12, 16
RA4/T0CKI/C1OUT/RCV ..................................... 12, 16
RA5/AN4/SS/HLVDIN/C2OUT ............................ 12, 16
RB0/AN12/INT0/FLT0/SDI/SDA .......................... 13, 17
RB1/AN10/INT1/SCK/SCL .................................. 13, 17
RB2/AN8/INT2/VMO ............................................ 13, 17
RB3/AN9/CCP2/VPO .......................................... 13, 17
RB4/AN11/KBI0 ......................................................... 13
RB4/AN11/KBI0/CSSPP ............................................ 17
RB5/KBI1/PGM .................................................... 13, 17
RB6/KBI2/PGC .................................................... 13, 17
RB7/KBI3/PGD .................................................... 13, 17
RC0/T1OSO/T13CKI ........................................... 14, 18
RC1/T1OSI/CCP2/UOE ....................................... 14, 18
RC2/CCP1 ................................................................. 14
RC2/CCP1/P1A ......................................................... 18
RC4/D-/VM .......................................................... 14, 18
RC5/D+/VP .......................................................... 14, 18
RC6/TX/CK .......................................................... 14, 18
RC7/RX/DT/SDO ................................................. 14, 18
RD0/SPP0 ................................................................. 19
RD1/SPP1 ................................................................. 19
RD2/SPP2 ................................................................. 19
RD3/SPP3 ................................................................. 19
RD4/SPP4 ................................................................. 19
RD5/SPP5/P1B ......................................................... 19
RD6/SPP6/P1C ......................................................... 19
RD7/SPP7/P1D ......................................................... 19
RE0/AN5/CK1SPP .................................................... 20
RE1/AN6/CK2SPP .................................................... 20
RE2/AN7/OESPP ...................................................... 20
VDD ...................................................................... 14, 20
VSS ...................................................................... 14, 20
VUSB .................................................................... 14, 20
Pinout I/O Descriptions
B
Block Diagrams
A/D ............................................................................. 24
Analog Input Model .................................................... 25
PIC18F2458/2553 ........................................................ 9
PIC18F4458/4553 ...................................................... 10
C
Compare (CCP Module)
Special Event Trigger ................................................. 30
Customer Change Notification Service .............................. 43
Customer Notification Service ............................................ 43
Customer Support .............................................................. 43
D
Device Differences ............................................................. 39
Device ID Registers ........................................................... 31
Device Overview .................................................................. 7
Other Special Features ................................................ 7
E
Electrical Characteristics .................................................... 33
Equations
A/D Acquisition Time .................................................. 26
A/D Minimum Charging Time ..................................... 26
Errata ................................................................................... 6
PIC18F2458/2553 ..................................................... 11
PIC18F4458/4553 ..................................................... 15
Power-Managed Modes
and A/D Operation ..................................................... 28
I
Internet Address ................................................................. 43
Interrupt Sources
R
Reader Response .............................................................. 44
Registers
A/D Conversion Complete ......................................... 25
ADCON0 (A/D Control 0) ........................................... 21
© 2009 Microchip Technology Inc.
DS39887C-page 41
PIC18F2458/2553/4458/4553
ADCON1 (A/D Control 1) ...........................................22
ADCON2 (A/D Control 2) ...........................................23
DEVID1 (Device ID 1) ................................................32
DEVID2 (Device ID 2) ................................................32
Revision History .................................................................39
S
Special Features of the CPU ..............................................31
T
Timing Diagrams
A/D Conversion ..........................................................36
Timing Diagrams and Specifications
A/D Conversion Requirements ..................................36
W
WWW Address ...................................................................43
WWW, On-Line Support .......................................................6
DS39887C-page 42
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
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• Local Sales Office
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• Technical Support
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• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
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Microchip’s customer notification service helps keep
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To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2009 Microchip Technology Inc.
DS39887C-page 43
PIC18F2458/2553/4458/4553
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PIC18F2458/2553/4458/4553
Device:
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DS39887C-page 44
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18LF4553-I/P 301 = Industrial temp., PDIP
package, Extended VDD limits, QTP pattern
#301.
b)
c)
PIC18LF2458-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
Device
PIC18F2458/2553(1), PIC18F4458/4553(1)
,
PIC18F4458-I/P = Industrial temp., PDIP
package, normal VDD limits.
PIC18F2458/2553T(2), PIC18F4458/4553T(2)
VDD range 4.2V to 5.5V
;
PIC18LF2458/2553(1), PIC18LF4458/4553(1)
PIC18LF2458/2553T(2), PIC18LF4458/4553T(2)
VDD range 2.0V to 5.5V
,
;
Temperature Range
Package
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
PT
SO
SP
P
=
=
=
=
=
TQFP (Thin Quad Flatpack)
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Wide Voltage Range
In tape and reel TQFP
packages only.
SOIC
Skinny PDIP
PDIP
ML
QFN
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2009 Microchip Technology Inc.
DS39887C-page 45
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Cleveland
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS39887C-page 46
© 2009 Microchip Technology Inc.
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