PIC18F258-I/SOSQTP [MICROCHIP]
28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module; 40分之28引脚高性能,增强型闪存微控制器与CAN模块型号: | PIC18F258-I/SOSQTP |
厂家: | MICROCHIP |
描述: | 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module |
文件: | 总402页 (文件大小:7079K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC18FXX8
Data Sheet
28/40-Pin High-Performance,
Enhanced Flash Microcontrollers
with CAN Module
© 2006 Microchip Technology Inc.
DS41159E
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS41159E-page ii
© 2006 Microchip Technology Inc.
PIC18FXX8
28/40-Pin High-Performance, Enhanced Flash
Microcontrollers with CAN
High-Performance RISC CPU:
Advanced Analog Features:
• 10-bit, up to 8-channel Analog-to-Digital Converter
module (A/D) with:
• Linear program memory addressing up to
2 Mbytes
- Conversion available during Sleep
- Up to 8 channels available
• Linear data memory addressing to 4 Kbytes
• Up to 10 MIPS operation
• Analog Comparator module:
• DC – 40 MHz clock input
- Programmable input and output multiplexing
• Comparator Voltage Reference module
• Programmable Low-Voltage Detection (LVD) module:
- Supports interrupt-on-Low-Voltage Detection
• Programmable Brown-out Reset (BOR)
• 4 MHz-10 MHz oscillator/clock input with
PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
CAN bus Module Features:
Peripheral Features:
• Complies with ISO CAN Conformance Test
• Message bit rates up to 1 Mbps
• Conforms to CAN 2.0B Active Spec with:
- 29-bit Identifier Fields
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
- 8-byte message length
• Timer1 module: 16-bit timer/counter
- 3 Transmit Message Buffers with prioritization
- 2 Receive Message Buffers
• Timer2 module: 8-bit timer/counter with 8-bit
period register (time base for PWM)
• Timer3 module: 16-bit timer/counter
- 6 full, 29-bit Acceptance Filters
- Prioritization of Acceptance Filters
• Secondary oscillator clock option – Timer1/Timer3
• Capture/Compare/PWM (CCP) modules;
CCP pins can be configured as:
- Multiple Receive Buffers for High Priority
Messages to prevent loss due to overflow
- Capture input: 16-bit, max resolution 6.25 ns
- Compare: 16-bit, max resolution 100 ns (TCY)
- Advanced Error Management Features
Special Microcontroller Features:
- PWM output: PWM resolution is 1 to 10-bit
Max. PWM freq. @:8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Enhanced CCP module which has all the features
of the standard CCP module, but also has the
following features for advanced motor control:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator
• Programmable code protection
- 1, 2 or 4 PWM outputs
• Power-saving Sleep mode
- Selectable PWM polarity
- Programmable PWM dead time
• Selectable oscillator options, including:
- 4x Phase Lock Loop (PLL) of primary oscillator
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
• Master Synchronous Serial Port (MSSP) with two
modes of operation:
- 3-wire SPI™ (Supports all 4 SPI modes)
- I2C™ Master and Slave mode
Flash Technology:
• Addressable USART module:
• Low-power, high-speed Enhanced Flash technology
• Fully static design
- Supports interrupt-on-address bit
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges
© 2006 Microchip Technology Inc.
DS41159E-page 1
PIC18FXX8
Program Memory
Device
Data Memory
MSSP
10-bit
A/D
(ch)
CCP/
ECCP
(PWM)
Timers
8/16-bit
I/O
USART
Flash # Single-Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
Master
SPI™
2
I C™
PIC18F248 16K
PIC18F258 32K
PIC18F448 16K
PIC18F458 32K
8192
16384
8192
768
1536
768
256
256
256
256
22
22
33
33
5
5
8
8
—
—
2
1/0
1/0
1/1
1/1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1/3
1/3
1/3
1/3
16384
1536
2
Pin Diagrams
PDIP
MCLR/VPP
1
40
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RA0/AN0/CVREF
2
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RA1/AN1
RA2/AN2/VREF-
3
4
RA3/AN3/VREF+
RB3/CANRX
5
RA4/T0CKI
RB2/CANTX/INT2
RB1/INT1
RB0/INT0
VDD
6
RA5/AN4/SS/LVDIN
RE0/AN5/RD
RE1/AN6/WR/C1OUT
RE2/AN7/CS/C2OUT
VDD
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4/ECCP1/P1A
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
PLCC
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/AN5/RD
RE1/AN6/WR/C1OUT
7
39
RB3/CANRX
RB2/CANTX/INT2
RB1/INT1
RB0/INT0
VDD
8
38
37
36
35
34
33
32
31
30
29
9
10
11
12
13
14
15
16
17
RE2/AN7/CS/C2OUT
PIC18F448
PIC18F458
VDD
VSS
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4/ECCP1/P1A
RC7/RX/DT
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CK1
NC
DS41159E-page 2
© 2006 Microchip Technology Inc.
PIC18FXX8
Pin Diagrams (Continued)
TQFP
RC7/RX/DT
RD4/PSP4/ECCP1/P1A
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
PIC18F448
PIC18F458
VDD
RB0/INT0
RB1/INT1
RE2/AN7/CS/C2OUT
RE1/AN6/WR/C1OUT
RE0//AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
9
10
11
RB2/CANTX/INT2
RB3/CANRX
SPDIP, SOIC
MCLR/VPP
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
1
2
3
4
5
6
28
27
26
25
24
23
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3/CANRX
RB2/CANTX/INT2
RA5/AN4/SS/LVDIN
VSS
22
21
RB1/INT1
RB0/INT0
7
8
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
20
19
18
17
16
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
9
10
11
12
13
14
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
15
RC4/SDI/SDA
© 2006 Microchip Technology Inc.
DS41159E-page 3
PIC18FXX8
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 17
3.0 Reset.......................................................................................................................................................................................... 25
4.0 Memory Organization................................................................................................................................................................. 37
5.0 Data EEPROM Memory ............................................................................................................................................................ 59
6.0 Flash Program Memory.............................................................................................................................................................. 65
7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 75
8.0 Interrupts .................................................................................................................................................................................... 77
9.0 I/O Ports ..................................................................................................................................................................................... 93
10.0 Parallel Slave Port.................................................................................................................................................................... 107
11.0 Timer0 Module ......................................................................................................................................................................... 109
12.0 Timer1 Module ......................................................................................................................................................................... 113
13.0 Timer2 Module ......................................................................................................................................................................... 117
14.0 Timer3 Module ......................................................................................................................................................................... 119
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 123
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 131
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 143
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 183
19.0 CAN Module ............................................................................................................................................................................. 199
20.0 Compatible 10-Bit Analog-to-Digital Converter (A/D) Module .................................................................................................. 241
21.0 Comparator Module.................................................................................................................................................................. 249
22.0 Comparator Voltage Reference Module................................................................................................................................... 255
23.0 Low-Voltage Detect.................................................................................................................................................................. 259
24.0 Special Features of the CPU.................................................................................................................................................... 265
25.0 Instruction Set Summary.......................................................................................................................................................... 281
26.0 Development Support............................................................................................................................................................... 323
27.0 Electrical Characteristics.......................................................................................................................................................... 329
28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 361
29.0 Packaging Information.............................................................................................................................................................. 377
Appendix A: Data Sheet Revision History.......................................................................................................................................... 385
Appendix B: Device Differences......................................................................................................................................................... 385
Appendix C: Device Migrations.......................................................................................................................................................... 386
Appendix D: Migrating From Other PICmicro® Devices..................................................................................................................... 386
Index .................................................................................................................................................................................................. 387
On-Line Support................................................................................................................................................................................. 397
Systems Information and Upgrade Hot Line ...................................................................................................................................... 397
Reader Response .............................................................................................................................................................................. 398
PIC18FXX8 Product Identification System......................................................................................................................................... 399
DS41159E-page 4
© 2006 Microchip Technology Inc.
PIC18FXX8
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2006 Microchip Technology Inc.
DS41159E-page 5
PIC18FXX8
NOTES:
DS41159E-page 6
© 2006 Microchip Technology Inc.
PIC18FXX8
2. PIC18F2X8 devices implement 5 A/D channels,
as opposed to 8 for PIC18F4X8 devices.
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
3. PIC18F2X8 devices implement 3 I/O ports,
while PIC18F4X8 devices implement 5.
• PIC18F248
• PIC18F258
• PIC18F448
• PIC18F458
4. Only PIC18F4X8 devices implement the
Enhanced CCP module, analog comparators
and the Parallel Slave Port.
All other features for devices in the PIC18FXX8 family,
including the serial communications modules, are
identical. These are summarized in Table 1-1.
These devices are available in 28-pin, 40-pin and
44-pin packages. They are differentiated from each
other in four ways:
Block diagrams of the PIC18F2X8 and PIC18F4X8
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.
1. PIC18FX58 devices have twice the Flash
program memory and data RAM of PIC18FX48
devices (32 Kbytes and 1536 bytes vs.
16 Kbytes and 768 bytes, respectively).
TABLE 1-1:
PIC18FXX8 DEVICE FEATURES
Features
PIC18F248
PIC18F258
PIC18F448
PIC18F458
Operating Frequency
DC – 40 MHz
16K
DC – 40 MHz
32K
DC – 40 MHz
16K
DC – 40 MHz
32K
Internal
Program
Memory
Bytes
# of Single-Word
Instructions
8192
16384
8192
16384
Data Memory (Bytes)
Data EEPROM Memory (Bytes)
Interrupt Sources
768
1536
768
256
21
1536
256
21
256
256
17
17
I/O Ports
Ports A, B, C
Ports A, B, C
Ports A, B, C, D, E Ports A, B, C, D, E
Timers
4
1
4
1
4
1
1
4
1
1
Capture/Compare/PWM Modules
Enhanced Capture/Compare/
PWM Modules
—
—
Serial Communications
MSSP, CAN,
MSSP, CAN,
MSSP, CAN,
MSSP, CAN,
Addressable USART Addressable USART Addressable USART Addressable USART
Parallel Communications (PSP)
10-bit Analog-to-Digital Converter
Analog Comparators
No
5 input channels
No
No
5 input channels
No
Yes
8 input channels
2
Yes
8 input channels
2
Analog Comparators VREF Output
Resets (and Delays)
N/A
N/A
Yes
Yes
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Programmable Low-Voltage Detect
Programmable Brown-out Reset
CAN Module
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
In-Circuit Serial Programming™
(ICSP™)
Instruction Set
Packages
75 Instructions
75 Instructions
75 Instructions
75 Instructions
28-pin SPDIP
28-pin SOIC
28-pin SPDIP
28-pin SOIC
40-pin PDIP
44-pin PLCC
44-pin TQFP
40-pin PDIP
44-pin PLCC
44-pin TQFP
© 2006 Microchip Technology Inc.
DS41159E-page 7
PIC18FXX8
FIGURE 1-1:
PIC18F248/258 BLOCK DIAGRAM
Data Bus<8>
PORTA
PORTB
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Table Pointer<21>
inc/dec logic
Data Latch
21
8
8
Data RAM
up to 1536 bytes
21
RA5/AN4/SS/LVDIN
OSC2/CLKO/RA6
Address Latch
21
PCLATH
PCLATU
PCU
12
RB0/INT0
RB1/INT1
RB2/CANTX/INT2
RB3/CANRX
RB4
RB5/PGM
RB6/PGC
RB7/PGD
Address<12>
PCH PCL
Program Counter
4
12
FSR0
4
BSR
Bank0, F
Address Latch
FSR1
FSR2
Program Memory
up to 32 Kbytes
31 Level Stack
12
Data Latch
inc/dec
logic
Decode
PORTC
Table Latch
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
8
16
ROM Latch
IR
RC6/TX/CK
RC7/RX/DT
8
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
8
3
OSC2/CLKO/RA6
OSC1/CLKI
W
8
BITOP
8
8
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
8
T1OSI
T1OSO
ALU<8>
8
Power-on
Reset
4X PLL
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
Precision
Band Gap
Reference
Band Gap
MCLR
VDD, VSS
PBOR
PLVD
10-bit
ADC
Timer0
Timer1
Timer2
Timer3
Synchronous
Serial Port
Data EEPROM
CCP1
USART
CAN Module
DS41159E-page 8
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 1-2:
PIC18F448/458 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Table Pointer<21>
21
Data Latch
8
8
Data RAM
up to 1536 Kbytes
inc/dec logic
21
RA5/AN4/SS/LVDIN
OSC2/CLKO/RA6
Address Latch
21
PCLATU PCLATH
PORTB
12
RB0/INT0
RB1/INT1
RB2/CANTX/INT2
RB3/CANRX
RB4
RB5/PGM
RB6/PGC
RB7/PGD
Address<12>
PCH PCL
Program Counter
PCU
12
4
4
Bank0, F
BSR
Address Latch
FSR0
FSR1
FSR2
Program Memory
up to 32 Kbytes
31 Level Stack
12
Data Latch
inc/dec
logic
Decode
PORTC
Table Latch
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
16
ROM Latch
IR
8
PORTD
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
RD2/PSP2/C2IN+
RD3/PSP3/C2IN-
RD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
8
3
OSC2/CLKO/RA6
OSC1/CLKI
W
8
BITOP
8
RD6/PSP6/P1C
RD7/PSP7/P1D
8
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
PORTE
8
RE0/AN5/RD
RE1/AN6/WR//C1OUT
RE2/AN7/CS/C2OUT
T1OSI
T1OSO
ALU<8>
Power-on
Reset
4X
8
PLL
Watchdog
Timer
Brown-out
Reset
Test Mode
Select
Precision
Band Gap
Reference
Band Gap
MCLR
VDD, VSS
PBOR
PLVD
10-bit
ADC
Parallel
Slave Port
Timer0
Timer1
CCP1
Timer2
Timer3
Synchronous
Serial Port
Enhanced
CCP
Data EEPROM
USART
Comparators
CAN Module
© 2006 Microchip Technology Inc.
DS41159E-page 9
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS
Pin Number
PIC18F248/258 PIC18F448/458
SPDIP, SOIC PDIP TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
MCLR/VPP
MCLR
1
1
18
2
Master Clear (input) or
programming voltage (output).
Master Clear (Reset) input.
This pin is an active low Reset
to the device.
I
ST
VPP
NC
P
—
—
Programming voltage input.
—
9
—
12, 13, 1, 17,
33, 34 28, 40
—
These pins should be left
unconnected.
OSC1/CLKI
OSC1
13
30
14
Oscillator crystal or external clock
input.
I
I
CMOS/ST
CMOS
Oscillator crystal input or
external clock source input. ST
buffer when configured in RC
mode; otherwise, CMOS.
External clock source input.
Always associated with pin
function OSC1 (see OSC1/
CLKI, OSC2/CLKO pins).
CLKI
OSC2/CLKO/RA6
OSC2
10
14
31
15
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or
resonator in Crystal Oscillator
mode.
O
O
—
—
CLKO
In RC mode, OSC2 pin outputs
CLKO, which has 1/4 the
frequency of OSC1 and
denotes the instruction cycle
rate.
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DS41159E-page 10
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18F248/258
PIC18F448/458
Description
SPDIP, SOIC PDIP TQFP PLCC
PORTA is a bidirectional I/O port.
RA0/AN0/CVREF
RA0
2
2
19
3
I/O
I
O
TTL
Analog
Analog
Digital I/O.
AN0
CVREF
Analog input 0.
Comparator voltage reference
output.
RA1/AN1
RA1
3
4
3
4
20
21
4
5
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage
(Low) input.
RA3/AN3/VREF+
RA3
5
6
7
5
6
7
22
23
24
6
7
8
I/O
I
I
TTL
Analog
Analog
Digital I/O.
AN3
VREF+
Analog input 3.
A/D reference voltage
(High) input.
RA4/T0CKI
RA4
I/O
I
TTL/OD
ST
Digital I/O – open-drain when
configured as output.
Timer0 external clock input.
T0CKI
RA5/AN4/SS/LVDIN
RA5
AN4
SS
I/O
TTL
Analog
ST
Digital I/O.
Analog input 4.
SPI™ slave select input.
Low-Voltage Detect input.
I
I
I
LVDIN
Analog
RA6
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
© 2006 Microchip Technology Inc.
DS41159E-page 11
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18F248/258 PIC18F448/458
SPDIP, SOIC PDIP TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTB is a bidirectional I/O port.
PORTB can be software
programmed for internal weak
pull-ups on all inputs.
RB0/INT0
RB0
21
22
23
33
34
35
8
9
36
37
38
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/CANTX/INT2
RB2
10
I/O
O
I
TTL
TTL
ST
Digital I/O.
Transmit signal for CAN bus.
External interrupt 2.
CANTX
INT2
RB3/CANRX
RB3
24
36
11
39
I/O
I
TTL
TTL
Digital I/O.
Receive signal for CAN bus.
CANRX
RB4
25
26
37
38
14
15
41
42
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
RB5/PGM
RB5
I/O
I
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP™
programming enable.
PGM
RB6/PGC
RB6
27
28
39
40
16
17
43
44
I/O
I
TTL
ST
Digital I/O. In-Circuit
Debugger pin.
Interrupt-on-change pin.
ICSP programming clock.
PGC
RB7/PGD
RB7
I/O
I/O
TTL
ST
Digital I/O. In-Circuit
Debugger pin.
Interrupt-on-change pin.
ICSP programming data.
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DS41159E-page 12
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18F248/258
PIC18F448/458
Description
SPDIP, SOIC PDIP TQFP PLCC
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
11
15
32
16
I/O
O
I
ST
—
ST
Digital I/O.
T1OSO
T1CKI
Timer1 oscillator output.
Timer1/Timer3 external clock
input.
RC1/T1OSI
RC1
12
13
14
16
17
18
35
36
37
18
19
20
I/O
I
ST
CMOS
Digital I/O.
Timer1 oscillator input.
T1OSI
RC2/CCP1
RC2
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1
output/PWM1 output.
CCP1
RC3/SCK/SCL
RC3
I/O
I/O
ST
ST
Digital I/O.
SCK
Synchronous serial clock
input/output for SPI™ mode.
Synchronous serial clock
input/output for I2C™ mode.
SCL
I/O
ST
RC4/SDI/SDA
RC4
15
23
42
25
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
SDI
SDA
RC5/SDO
RC5
16
17
24
25
43
44
26
27
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX/CK
RC6
I/O
O
ST
—
Digital I/O.
USART asynchronous
transmit.
TX
CK
I/O
ST
USART synchronous clock
(see RX/DT).
RC7/RX/DT
RC7
18
26
1
29
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
USART asynchronous receive.
USART synchronous data
(see TX/CK).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
© 2006 Microchip Technology Inc.
DS41159E-page 13
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PIC18F248/258 PIC18F448/458
SPDIP, SOIC PDIP TQFP PLCC
Pin
Type
Buffer
Type
Pin Name
Description
PORTD is a bidirectional I/O port.
These pins have TTL input buffers
when external memory is enabled.
RD0/PSP0/C1IN+
RD0
—
—
—
—
—
19
20
21
22
27
38
39
40
41
2
21
22
23
24
30
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 1 input.
PSP0
C1IN+
RD1/PSP1/C1IN-
RD1
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 1 input.
PSP1
C1IN-
RD2/PSP2/C2IN+
RD2
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 2 input.
PSP2
C2IN+
RD3/PSP3/C2IN-
RD3
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 2 input.
PSP3
C2IN-
RD4/PSP4/ECCP1/
P1A
RD4
I/O
I/O
I/O
O
ST
TTL
ST
—
Digital I/O.
PSP4
ECCP1
P1A
Parallel Slave Port data.
ECCP1 capture/compare.
ECCP1 PWM output A.
RD5/PSP5/P1B
RD5
—
—
—
28
29
30
3
4
5
31
32
33
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output B.
PSP5
P1B
RD6/PSP6/P1C
RD6
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output C.
PSP6
P1C
RD7/PSP7/P1D
RD7
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output D.
PSP7
P1D
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DS41159E-page 14
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 1-2:
PIC18FXX8 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
PIC18F248/258
PIC18F448/458
Description
SPDIP, SOIC PDIP TQFP PLCC
PORTE is a bidirectional I/O port.
RE0/AN5/RD
RE0
—
—
8
9
25
26
9
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 5.
Read control for Parallel Slave
Port (see WR and CS pins).
AN5
RD
RE1/AN6/WR/C1OUT
10
RE1
AN6
WR
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 6.
Write control for Parallel Slave
Port (see CS and RD pins).
Comparator 1 output.
C1OUT
O
Analog
RE2/AN7/CS/C2OUT
—
10
27
11
RE2
AN7
CS
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 7.
Chip select control for Parallel
Slave Port (see RD and WR
pins).
C2OUT
VSS
O
Analog
—
Comparator 2 output.
19, 8
20
12, 31 6, 29 13, 34
11, 32 7, 28 12, 35
—
Ground reference for logic and
I/O pins.
VDD
—
—
Positive supply for logic and I/O
pins.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
© 2006 Microchip Technology Inc.
DS41159E-page 15
PIC18FXX8
NOTES:
DS41159E-page 16
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP OSC
CONFIGURATION)
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Oscillator Types
(1)
C1
OSC1
The PIC18FXX8 can be operated in one of eight oscil-
lator modes, programmable by three configuration bits
(FOSC2, FOSC1 and FOSC0).
To
Internal
Logic
(3)
XTAL
RF
1. LP
2. XT
3. HS
4. HS4
Low-Power Crystal
Crystal/Resonator
Sleep
(2)
RS
High-Speed Crystal/Resonator
(1)
PIC18FXX8
C2
OSC2
High-Speed Crystal/Resonator with
PLL enabled
Note 1: See Table 2-1 and Table 2-2 for recommended
5. RC
External Resistor/Capacitor
values of C1 and C2.
6. RCIO
External Resistor/Capacitor with I/O
pin enabled
2: A series resistor (RS) may be required for AT
strip cut crystals.
7. EC
External Clock
3: RF varies with the crystal chosen.
8. ECIO
External Clock with I/O pin enabled
2.2
Crystal Oscillator/Ceramic
Resonators
TABLE 2-1:
CERAMIC RESONATORS
Ranges Tested:
In XT, LP, HS or HS4 (PLL) Oscillator modes, a crystal
or ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections. An external clock source may also
be connected to the OSC1 pin, as shown in Figure 2-3
and Figure 2-4.
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS
8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
The PIC18FXX8 oscillator design requires the use of a
parallel cut crystal.
These values are for design guidance only.
See notes following Table 2-2.
Note:
Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
Resonators Used:
455 kHz Panasonic EFO-A455K04B
0.3%
2.0 MHz
4.0 MHz
8.0 MHz
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
0.5%
0.5%
0.5%
0.5%
16.0 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
© 2006 Microchip Technology Inc.
DS41159E-page 17
PIC18FXX8
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
2.3
RC Oscillator
For timing insensitive applications, the “RC” and “RCIO”
device options offer additional cost savings. The RC
oscillator frequency is a function of the supply voltage,
the resistor (REXT) and capacitor (CEXT) values and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the differ-
ence in lead frame capacitance between package types
will also affect the oscillation frequency, especially for
low CEXT values. The user also needs to take into
account variation due to tolerance of external R and C
components used. Figure 2-2 shows how the RC
combination is connected.
Crystal Cap. Range Cap.Range
Osc Type
Freq
C1
C2
LP
32.0 kHz
200 kHz
200 kHz
1.0 MHz
4.0 MHz
4.0 MHz
8.0 MHz
20.0 MHz
25.0 MHz
33 pF
15 pF
33 pF
15 pF
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15-33 pF
15-33 pF
15-33 pF
15-33 pF
15-33 pF
15-33 pF
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
These values are for design guidance only.
See notes on this page.
Crystals Used
Note:
If the oscillator frequency divided by 4
signal is not required in the application, it
is recommended to use RCIO mode to
save current.
32.0 kHz Epson C-001R32.768K-A
20 PPM
200 kHz
1.0 MHz
4.0 MHz
STD XTL 200.000KHz
ECS ECS-10-13-1
ECS ECS-40-20-1
20 PPM
50 PPM
50 PPM
30 PPM
30 PPM
FIGURE 2-2:
RC OSCILLATOR MODE
8.0 MHz EPSON CA-301 8.000M-C
20.0 MHz EPSON CA-301 20.000M-C
VDD
PIC18FXX8
Internal
OSC1
REXT
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
Clock
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
CEXT
VSS
OSC2/CLKO
FOSC/4
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
appropriate
values
of
external
components.
4: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
The RCIO Oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
DS41159E-page 18
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION (ECIO
CONFIGURATION)
2.4
External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from Sleep mode.
PIC18FXX8
OSC1
Clock from
Ext. System
I/O (OSC2)
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
2.5
HS4 (PLL)
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
FIGURE 2-3:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
PIC18FXX8
OSC1
Clock from
Ext. System
The PLL can only be enabled when the oscillator
configuration bits are programmed for HS mode. If they
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
OSC2
FOSC/4
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. Figure 2-4 shows the pin
connections for the ECIO Oscillator mode.
The PLL is one of the modes of the FOSC2:FOSC0
configuration bits. The oscillator mode is specified
during device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out referred to as TPLL.
FIGURE 2-5:
PLL BLOCK DIAGRAM
FOSC2:FOSC0 = 110
Phase
Comparator
OSC2
FIN
Loop
Filter
VCO
Crystal
FOUT
Osc
SYSCLK
Divide by 4
OSC1
© 2006 Microchip Technology Inc.
DS41159E-page 19
PIC18FXX8
2.6.1
SYSTEM CLOCK SWITCH BIT
2.6
Oscillator Switching Feature
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON register), controls the clock switching. When
the SCS bit is ‘0’, the system clock source comes from
the main oscillator selected by the FOSC2:FOSC0
configuration bits. When the SCS bit is set, the system
clock source comes from the Timer1 oscillator. The SCS
bit is cleared on all forms of Reset.
The PIC18FXX8 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
For the PIC18FXX8 devices, this alternate clock source
is the Timer1 oscillator. If a low-frequency crystal
(32 kHz, for example) has been attached to the Timer1
oscillator pins and the Timer1 oscillator has been
enabled, the device can switch to a Low-Power Execu-
tion mode. Figure 2-6 shows a block diagram of the
system clock sources. The clock switching feature is
enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration register,
CONFIG1H, to a ‘0’. Clock switching is disabled in an
erased device. See Section 12.2 “Timer1 Oscillator”
for further details of the Timer1 oscillator and
Section 24.1 “Configuration Bits” for Configuration
register details.
Note:
The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON). If the Timer1 oscillator is not
enabled, any write to the SCS bit will be
ignored (SCS bit forced cleared) and the
main oscillator continues to be the system
clock source.
FIGURE 2-6:
DEVICE CLOCK SOURCES
PIC18FXX8
Main Oscillator
OSC2
TOSC/4
4 x PLL
Sleep
TOSC
TT1P
TSCLK
OSC1
Timer 1 Oscillator
T1OSO
T1OSCEN
Enable
Oscillator
Clock
Source
T1OSI
Clock Source Option
for Other Modules
Note:
I/O pins have diode protection to VDD and VSS.
REGISTER 2-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R/W-1
SCS
—
bit 7
bit 0
bit 7-1 Unimplemented: Read as ‘0’
bit 0
SCS: System Clock Switch bit
When OSCSEN configuration bit = 0and T1OSCEN bit is set:
1= Switch to Timer1 oscillator/clock pin
0= Use primary oscillator/clock input pin
When OSCSEN is clear or T1OSCEN is clear:
Bit is forced clear.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 20
© 2006 Microchip Technology Inc.
PIC18FXX8
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
2.6.2
OSCILLATOR TRANSITIONS
The PIC18FXX8 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
If the main oscillator is configured for an external
crystal (HS, XT, LP), the transition will take place after
an oscillator start-up time (TOST) has occurred. A timing
diagram indicating the transition from the Timer1
oscillator to the main oscillator for HS, XT and LP
modes is shown in Figure 2-8.
Figure 2-7 shows a timing diagram indicating the tran-
sition from the main oscillator to the Timer1 oscillator.
The Timer1 oscillator is assumed to be running all the
time. After the SCS bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator,
operation resumes. No additional delays are required
after the synchronization cycles.
FIGURE 2-7:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q4
Q1 Q2 Q3
Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4 Q1
TT1P
2
1
3
4
5
6
7
8
T1OSI
OSC1
Tscs
TOSC
Internal
System
Clock
TDLY
SCS
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3
Q4
Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3
TT1P
T1OSI
OSC1
1
2
3
4
5
6
7
8
TOST
TSCS
OSC2
TOSC
Internal System
Clock
SCS
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note 1: TOST = 1024 TOSC (drawing not to scale).
© 2006 Microchip Technology Inc.
DS41159E-page 21
PIC18FXX8
If the main oscillator is configured for HS4 (PLL) mode,
an oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram indicating the transition
from the Timer1 oscillator to the main oscillator for HS4
mode is shown in Figure 2-9.
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram indicat-
ing the transition from the Timer1 oscillator to the main
oscillator for RC, RCIO, EC and ECIO modes is shown
in Figure 2-10.
FIGURE 2-9:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4
Q1
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
8
7
Internal System
Clock
SCS
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note 1: TOST = 1024 TOSC (drawing not to scale).
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
TT1P
T1OSI
OSC1
TOSC
1
2
3
4
5
6
7
8
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program
Counter
PC
PC + 2
PC + 4
Note 1: RC Oscillator mode assumed.
DS41159E-page 22
© 2006 Microchip Technology Inc.
PIC18FXX8
Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
2.7
Effects of Sleep Mode on the
On-Chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of TPWRT (parameter
#D033) on power-up only (POR and BOR). The second
timer is the Oscillator Start-up Timer (OST), intended to
keep the chip in Reset until the crystal oscillator is
stable.
With the PLL enabled (HS4 Oscillator mode), the time-
out sequence following a Power-on Reset is different
from other oscillator modes. The time-out sequence is
as follows: the PWRT time-out is invoked after a POR
time delay has expired, then the Oscillator Start-up
Timer (OST) is invoked. However, this is still not a
sufficient amount of time to allow the PLL to lock at high
frequencies. The PWRT timer is used to provide an
additional fixed 2 ms (nominal) to allow the PLL ample
time to lock to the incoming clock frequency.
2.8
Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC Mode
OSC2 Pin
RC
Floating, external resistor should pull high At logic low
RCIO
Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO
Floating
Floating
Configured as PORTA, bit 6
At logic low
EC
LP, XT and HS
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.
© 2006 Microchip Technology Inc.
DS41159E-page 23
PIC18FXX8
NOTES:
DS41159E-page 24
© 2006 Microchip Technology Inc.
PIC18FXX8
state on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESETinstruction.
3.0
RESET
The PIC18FXX8 differentiates between various kinds
of RESET:
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR are set or cleared differently in different
Reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset during normal
operation
e) Programmable Brown-out Reset (PBOR)
f) RESETInstruction
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
g) Stack Full Reset
h) Stack Underflow Reset
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset”
A WDT Reset does not drive MCLR pin low.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
External Reset
Stack
Pointer
MCLR
Sleep
WDT
Time-out
Reset
WDT
Module
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
BOREN
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
10-bit Ripple Counter
Q
R
OSC1
PWRT
On-chip
(1)
RC OSC
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
© 2006 Microchip Technology Inc.
DS41159E-page 25
PIC18FXX8
3.1
Power-on Reset (POR)
3.3
Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected. To take advantage of the POR
circuitry, connect the MCLR pin directly (or through a
resistor) to VDD. This eliminates external RC compo-
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified (refer to
parameter D004). For a slow rise time, see Figure 3-2.
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit (PWRTEN in CONFIG2L
register) is provided to enable/disable the PWRT.
When the device starts normal operation (exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating condi-
tions are met. Brown-out Reset may be used to meet
the voltage start-up condition.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.4
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This additional
delay ensures that the crystal oscillator or resonator
has started and stabilized.
3.2
MCLR
PIC18FXX8 devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
The OST time-out is invoked only for XT, LP, HS and
HS4 modes and only on Power-on Reset or wake-up
from Sleep.
It should be noted that a WDT Reset does not drive
MCLR pin low.
3.5
PLL Lock Time-out
The behavior of the ESD protection on the MCLR pin
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both Resets and current draws outside of
device specification during the Reset event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an RC
network, as shown in Figure 3-2, is suggested.
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 2 ms and follows the oscillator
start-up time-out (OST).
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
3.6
Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set), the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation resets the
chip. A Reset may not occur if VDD falls below param-
eter D005 for less than parameter #35. The chip will
remain in Brown-out Reset until VDD rises above BVDD.
The Power-up Timer will then be invoked and will keep
the chip in Reset an additional time delay (parameter
#33). If VDD drops below BVDD while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above BVDD, the Power-up Timer will
execute the additional time delay.
VDD
D
R
R1
MCLR
PIC18FXXX
C
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current flow-
ing into MCLR from external capacitor C, in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
DS41159E-page 26
© 2006 Microchip Technology Inc.
PIC18FXX8
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18FXX8 device
operating in parallel.
3.7
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired, then OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all registers.
TABLE 3-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Wake-up from
Oscillator
Configuration
Brown-out(2)
Sleep or
PWRTEN = 0
PWRTEN = 1
Oscillator Switch
HS with PLL enabled(1) 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms
HS, XT, LP
EC
72 ms + 1024 TOSC
72 ms
1024 TOSC
72 ms + 1024 TOSC
72 ms
1024 TOSC
—
—
—
—
External RC
72 ms
72 ms
Note 1: 2 ms = Nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal Power-up Timer delay.
REGISTER 3-1:
TABLE 3-2:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-1
BOR
bit 7
bit 0
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h
0000h
0--1 110q
0--0 011q
1
u
1
u
1
u
0
u
0
u
u
u
u
u
MCLR Reset during normal
operation
Software Reset during normal
operation
0000h
0000h
0000h
0--0 011q
0--0 011q
0--0 011q
0
u
u
u
u
u
u
u
u
u
1
1
u
1
1
u
u
1
u
1
u
Stack Full Reset during normal
operation
Stack Underflow Reset during
normal operation
MCLR Reset during Sleep
WDT Reset
0000h
0000h
0--0 011q
0--0 011q
0--1 101q
0--1 110q
0--1 101q
u
u
u
1
u
1
0
0
1
1
0
1
0
1
0
u
u
u
u
u
u
u
u
0
u
u
u
u
u
u
u
u
u
u
u
WDT Wake-up
PC + 2
Brown-out Reset
0000h
PC + 2(1)
Interrupt wake-up from Sleep
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (000008h or 000018h).
© 2006 Microchip Technology Inc.
DS41159E-page 27
PIC18FXX8
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
DS41159E-page 28
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note: TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
© 2006 Microchip Technology Inc.
DS41159E-page 29
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Reset
WDT Reset
RESETInstruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
TOSU
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
111- -1-1
11-0 0-00
N/A
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
111- -1-1
11-0 0-00
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuu- -u-u(1)
uu-u u-uu(1)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
DS41159E-page 30
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction
Stack Resets
FSR1H
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
---- xxxx
xxxx xxxx
---- 0000
N/A
---- uuuu
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
---- ---0
--00 0101
---- ---0
0--1 110q
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 00-0
---- uuuu
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
---- ---0
--00 0101
---- ---0
0--0 011q
uuuu uuuu
uuuu uuuu
u-uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 00-0
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
--uu uuuu
---- ---u
0--1 101q
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
© 2006 Microchip Technology Inc.
DS41159E-page 31
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
RESETInstruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
ADCON1
CCPR1H
CCPR1L
CCP1CON
ECCPR1H
ECCPR1L
ECCP1CON
ECCP1DEL
ECCPAS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
SPBRG
RCREG
TXREG
TXSTA
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
00-- 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx-0 x000
1111 1111
0000 0000
0000 0000
-1-1 1111
-0-0 0000
-0-0 0000
1111 1111
0000 0000
0000 0000
00-- 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 -010
0000 000u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-0 u000
1111 1111
0000 0000
0000 0000
-1-1 1111
-0-0 0000
-0-0 0000
1111 1111
0000 0000
0000 0000
uu-- uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-0 u000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-u uuuu
-u-u uuuu(1)
-u-u uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
DS41159E-page 32
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction
Stack Resets
TRISE
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111(5)
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx(5)
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000(5)
0000 0000
0000 0000
0000 0000
--00 ----
-0-- -000
0000 0000
0000 0000
xxxx xxx-
xxx- xxx-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
---- -000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u0u 0000(5)
0000 0000
0000 0000
0000 0000
--00 ----
-0-- -000
0000 0000
0000 0000
uuuu uuu-
uuu- uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu ----
-u-- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuu-
uuu- uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TRISD
TRISC
TRISB
TRISA(5)
LATE
LATD
LATC
LATB
LATA(5)
PORTE
PORTD
PORTC
PORTB
PORTA(5)
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
BRGCON3
BRGCON2
BRGCON1
CANCON
CANSTAT(6)
RXB0D7
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
© 2006 Microchip Technology Inc.
DS41159E-page 33
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
RESETInstruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
RXB1D7
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
000- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
000- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
RXB1D6
RXB1D5
RXB1D4
RXB1D3
RXB1D2
RXB1D1
RXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
TXB0D7
TXB0D6
TXB0D5
TXB0D4
TXB0D3
TXB0D2
TXB0D1
TXB0D0
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
DS41159E-page 34
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction
Stack Resets
TXB0SIDH
TXB0CON
TXB1D7
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
xxxx xxxx
-000 0-00
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
-000 0-00
xxxx xxxx
xxxx xxxx
uuuu uuuu
-000 0-00
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
-000 0-00
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
-uuu u-uu
uuuu uuuu
uuuu uuuu
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D0
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
TXB2D7
TXB2D6
TXB2D5
TXB2D4
TXB2D3
TXB2D2
TXB2D1
TXB2D0
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
RXM1EIDL
RXM1EIDH
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
© 2006 Microchip Technology Inc.
DS41159E-page 35
PIC18FXX8
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Reset
WDT Reset
RESETInstruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
RXM1SIDL
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
RXM0SIDH
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
RXF3SIDL
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
RXF1EIDL
RXF1EIDH
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
PIC18F2X8 PIC18F4X8
xxx- --xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- --xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
uuu- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuu- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Values for CANSTAT also apply to its other instances (CANSTATRO1 through CANSTATRO4).
DS41159E-page 36
© 2006 Microchip Technology Inc.
PIC18FXX8
Figure 4-1 shows the diagram for program memory
map and stack for the PIC18F248 and PIC18F448.
Figure 4-2 shows the diagram for the program memory
map and stack for the PIC18F258 and PIC18F458.
4.0
MEMORY ORGANIZATION
There are three memory blocks in Enhanced MCU
devices. These memory blocks are:
• Enhanced Flash Program Memory
• Data Memory
• EEPROM Data Memory
4.1.1
INTERNAL PROGRAM MEMORY
OPERATION
The PIC18F258 and the PIC18F458 have 32 Kbytes of
internal Enhanced Flash program memory. This means
that the PIC18F258 and the PIC18F458 can store up to
16K of single-word instructions. The PIC18F248 and
PIC18F448 have 16 Kbytes of Enhanced Flash
program memory. This translates into 8192 single-word
instructions, which can be stored in the program
memory. Accessing a location between the physically
implemented memory and the 2-Mbyte address will
cause a read of all ‘0’s (a NOPinstruction).
Data and program memory use separate busses,
which allows concurrent access of these blocks.
Additional detailed information on data EEPROM and
Flash program memory is provided in Section 5.0
“Data EEPROM Memory” and Section 6.0 “Flash
Program Memory”, respectively.
4.1
Program Memory Organization
The PIC18F258/458 devices have a 21-bit program
counter that is capable of addressing a 2-Mbyte
program memory space.
The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F258/458
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F248/448
PC<20:0>
PC<20:0>
21
21
CALL,RCALL,RETURN
RETFIE,RETLW
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 1
•
•
•
•
•
•
Stack Level 31
Stack Level 31
0000h
Reset Vector
0000h
Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
On-Chip
Program Memory
3FFFh
4000h
On-Chip
Program Memory
7FFFh
8000h
Read ‘0’
Read ‘0’
1FFFFFh
200000h
1FFFFFh
200000h
© 2006 Microchip Technology Inc.
DS41159E-page 37
PIC18FXX8
4.2.2
RETURN STACK POINTER
(STKPTR)
4.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
PUSH, CALL or RCALL instruction is executed, or an
interrupt is Acknowledged. The PC value is pulled off
the stack on a RETURN, RETLWor a RETFIEinstruc-
tion. PCLATU and PCLATH are not affected by any of
the RETURNinstructions.
The STKPTR register contains the Stack Pointer value,
the STKFUL (Stack Full) status bit and the STKUNF
(Stack Underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the Stack Pointer can be
0 through 31. The Stack Pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At Reset, the Stack
Pointer value will be ‘0’. The user may read and write
the Stack Pointer value. This feature can be used by a
Real-Time Operating System for return stack
maintenance.
The stack operates as a 31-word by 21-bit stack
memory and a 5-bit Stack Pointer register, with the
Stack Pointer initialized to 00000b after all Resets.
There is no RAM associated with Stack Pointer
00000b. This is only a Reset value. During a CALLtype
instruction, causing a push onto the stack, the Stack
Pointer is first incremented and the RAM location
pointed to by the Stack Pointer is written with the con-
tents of the PC. During a RETURN type instruction,
causing a pop from the stack, the contents of the RAM
location indicated by the STKPTR are transferred to the
PC and then the Stack Pointer is decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 21.0 “Comparator Module” for a description
of the device configuration bits. If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to ‘0’.
The stack space is not part of either program or data
space. The Stack Pointer is readable and writable and
the data on the top of the stack is readable and writable
through SFR registers. Status bits indicate if the stack
pointer is at or beyond the 31 levels provided.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
The 32nd push will overwrite the 31st push (and so on),
while STKPTR remains at 31.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL allow
access to the contents of the stack location indicated by
the STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at ‘0’. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken.
The user should disable the global interrupt enable bits
during this time to prevent inadvertent stack
operations.
DS41159E-page 38
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 4-1:
STKPTR: STACK POINTER REGISTER
R/C-0
STKFUL
bit 7
R/C-0
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKUNF
bit 0
bit 7
bit 6
bit 5
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note:
Bit 7 and bit 6 need to be cleared following a stack underflow or a stack overflow.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared C = Clearable bit
FIGURE 4-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
00010
TOSU
00h
TOSH
1Ah
TOSL
34h
00011
001A34h 00010
000D58h 00001
000000h 00000(1)
Top-of-Stack
Note 1: No RAM associated with this address; always maintained ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 39
PIC18FXX8
4.2.3
PUSH AND POP INSTRUCTIONS
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the Stack Pointer and load the
current PC value onto the stack. TOSU, TOSH and
TOSL can then be modified to place a return address
on the stack.
CALL SUB1, FAST
•
•
SUB1
•
•
•
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
The POPinstruction discards the current TOS by decre-
menting the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
4.4
PCL, PCLATH and PCLATU
4.2.4
STACK FULL/UNDERFLOW RESETS
These Resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
Reset. When the STVREN bit is enabled, a full or
underflow condition will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR.
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
4.3
Fast Register Stack
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSb of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instructions in the program memory.
A “fast return” option is available for interrupts and
calls. A fast register stack is provided for the Status,
WREG and BSR registers and is only one layer in
depth. The stack is not readable or writable and is
loaded with the current value of the corresponding
register when the processor vectors for an interrupt.
The values in the fast register stack are then loaded
back into the working registers if the FAST RETURN
instruction is used to return from the interrupt.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
The contents of PCLATH and PCLATU will be
transferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1
“Computed GOTO”).
If high priority interrupts are not disabled during low
priority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
DS41159E-page 40
© 2006 Microchip Technology Inc.
PIC18FXX8
4.5
Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
Program Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.
FIGURE 4-4:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Internal
Phase
Clock
Q2
Q3
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC Mode)
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
4.6
Instruction Flow/Pipelining
4.7
Instructions in Program Memory
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
two cycles are required to complete the instruction
(Example 4-2).
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 4-3 shows an
example of how instruction words are stored in the
program memory. To maintain alignment with instruc-
tion boundaries, the PC increments in steps of 2 and
the LSB will always read ‘0’ (see Section 4.4 “PCL,
PCLATH and PCLATU”).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
The CALL and GOTO instructions have an absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Example 4-3 shows how the
instruction “GOTO 000006h” is encoded in the program
memory. Program branch instructions that encode a
relative address offset operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions by which the PC will
be offset. Section 25.0 “Instruction Set Summary”
provides further details of the instruction set.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
© 2006 Microchip Technology Inc.
DS41159E-page 41
PIC18FXX8
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1
Execute SUB_1
Note:
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is
“flushed” from the pipeline while the new instruction is being fetched and then executed.
EXAMPLE 4-3:
INSTRUCTIONS IN PROGRAM MEMORY
Instruction
Opcode
Memory
Address
—
000007h
000008h
000009h
00000Ah
00000Bh
00000Ch
00000Dh
00000Eh
00000Fh
000010h
000011h
000012h
MOVLW 055h
0E55h
55h
0Eh
GOTO 000006h
0EF03h, 0F000h
03h
0EFh
00h
0F0h
23h
MOVFF 123h, 456h
0C123h, 0F456h
0C1h
56h
0F4h
—
DS41159E-page 42
© 2006 Microchip Technology Inc.
PIC18FXX8
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18FXX8 devices have 4 two-word instructions:
MOVFF, CALL, GOTOand LFSR. The 4 Most Signifi-
cant bits of the second word are set to ‘1’s and indicate
a special NOP instruction. The lower 12 bits of the
second word contain the data to be used by the
instruction. If the first word of the instruction is executed,
the data in the second word is accessed. If the second
word of the instruction is executed by itself (first word
was skipped), it will execute as a NOP. This action is
necessary when the two-word instruction is preceded by
a conditional instruction that changes the PC. A program
example that demonstrates this concept is shown in
Example 4-4. Refer to Section 25.0 “Instruction Set
Summary” for further details of the instruction set.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
Note 1: The LSb of PCL is fixed to a value of ‘0’.
Hence, computed GOTOto an odd address
is not possible.
2: The ADDWF PCL instruction does not
update PCLATH/PCLATU. A read opera-
tion on PCL must be performed to update
PCLATH and PCLATU.
4.8
Look-up Tables
4.8.2
TABLE READS/TABLE WRITES
Look-up tables are implemented two ways. These are:
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
• Computed GOTO
• Table Reads
Look-up table data may be stored as 2 bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) specifies the byte address and
the Table Latch (TABLAT) contains the data that is read
from, or written to, program memory. Data is
transferred to/from program memory, one byte at a
time.
4.8.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
A description of the table read/table write operation is
shown in Section 6.1 “Table Reads and Table Writes”.
EXAMPLE 4-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110
REG1
; is RAM location 0?
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
0010 0100 0000 0000 ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110
REG1
; is RAM location 0?
REG1, REG2 ; Yes
; 2nd operand becomes NOP
REG3 ; continue code
0010 0100 0000 0000 ADDWF
© 2006 Microchip Technology Inc.
DS41159E-page 43
PIC18FXX8
4.9.1
GENERAL PURPOSE
REGISTER FILE
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
shows the data memory organization for the
PIC18FXX8 devices.
The register file can be accessed either directly or
indirectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12 “Indirect
Addressing, INDF and FSR Registers”.
The data memory map is divided into as many as
16 banks that contain 256 bytes each. The lower 4 bits
of the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (F00h to FFFh) contains SFRs.
All other banks of data memory contain GPR registers,
starting with Bank 0.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(FFFh) and grow downwards. GPRs start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ‘0’s.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 4-1.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of
the File Select Register (FSR). Each FSR holds a
12-bit address value that can be used to access any
location in the data memory map without banking.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFFinstruction. The
MOVFF instruction is a two-word/two-cycle instruction,
that moves a value from one register to another.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s. See Table 4-1 for addresses for the SFRs.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10
“Access Bank” provides a detailed description of the
Access RAM.
DS41159E-page 44
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 4-5:
BSR<3:0>
= 0000
DATA MEMORY MAP FOR PIC18F248/448
Data Memory Map
000h
05Fh
00h
Access RAM
GPR
Bank 0
060h
0FFh
100h
FFh
00h
= 0001
= 0010
GPR
GPR
Bank 1
Bank 2
1FFh
200h
FFh
00h
FFh
300h
Access Bank
00h
Access Bank Low
(GPR)
5Fh
60h
= 0011
= 1110
Access Bank High
Bank 3
to
Bank 14
Unused
Read ‘00h’
(SFR)
FFh
When a = 0,
the BSR is ignored and
the Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The next 160 bytes are
Special Function
Registers (from Bank 15).
When a = 1,
EFFh
F00h
F5Fh
F60h
FFFh
the BSR is used to specify
the RAM location that the
instruction uses.
00h
FFh
Unused
SFR
= 1111
Bank 15
© 2006 Microchip Technology Inc.
DS41159E-page 45
PIC18FXX8
FIGURE 4-6:
BSR<3:0>
= 0000
DATA MEMORY MAP FOR PIC18F258/458
Data Memory Map
000h
05Fh
060h
0FFh
00h
Access RAM
GPR
Bank 0
FFh
00h
100h
= 0001
= 0010
GPR
GPR
Bank 1
Bank 2
Bank 3
1FFh
200h
FFh
00h
2FFh
300h
FFh
00h
= 0011
= 0100
= 0101
GPR
FFh
3FFh
400h
Access Bank
Bank 4
Bank 5
GPR
GPR
4FFh
500h
00h
Access Bank low
(GPR)
00h
FFh
5Fh
60h
5FFh
600h
Access Bank high
(SFR)
FFh
= 0110
= 1110
When a = 0,
Bank 6
to
Bank 14
Unused
Read ‘00h’
the BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
EFFh
F00h
F5Fh
F60h
FFFh
The next 160 bytes are
SpecialFunctionRegisters
(from Bank 15).
00h
FFh
SFR
SFR
= 1111
Bank 15
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
DS41159E-page 46
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER MAP
Name
Address
Name
Address
Name
Address
Name
FFFh TOSU
FDFh INDF2(2)
FBFh CCPR1H
F9Fh IPR1
FFEh TOSH
FDEh POSTINC2(2)
FDDh POSTDEC2(2)
FDCh PREINC2(2)
FDBh PLUSW2(2)
FDAh FSR2H
FBEh CCPR1L
F9Eh PIR1
F9Dh PIE1
F9Ch
FFDh TOSL
FBDh CCP1CON
FBCh ECCPR1H(5)
FBBh ECCPR1L(5)
FBAh ECCP1CON(5)
FFCh STKPTR
FFBh PCLATU
FFAh PCLATH
FF9h PCL
—
—
—
—
—
—
F9Bh
F9Ah
FD9h FSR2L
FB9h
—
F99h
FF8h TBLPTRU
FF7h TBLPTRH
FF6h TBLPTRL
FF5h TABLAT
FF4h PRODH
FF3h PRODL
FD8h STATUS
FD7h TMR0H
FB8h
—
F98h
FB7h ECCP1DEL(5)
FB6h ECCPAS(5)
FB5h CVRCON(5)
FB4h CMCON(5)
FB3h TMR3H
F97h
FD6h TMR0L
F96h TRISE(5)
F95h TRISD(5)
F94h TRISC
F93h TRISB
F92h TRISA
FD5h T0CON
FD4h
—
FD3h OSCCON
FD2h LVDCON
FD1h WDTCON
FD0h RCON
FF2h INTCON
FF1h INTCON2
FF0h INTCON3
FEFh INDF0(2)
FEEh POSTINC0(2)
FEDh POSTDEC0(2)
FECh PREINC0(2)
FEBh PLUSW0(2)
FEAh FSR0H
FB2h TMR3L
FB1h T3CON
F91h
F90h
F8Fh
F8Eh
—
—
—
—
FB0h
—
FCFh TMR1H
FCEh TMR1L
FCDh T1CON
FCCh TMR2
FAFh SPBRG
FAEh RCREG
FADh TXREG
FACh TXSTA
FABh RCSTA
F8Dh LATE(5)
F8Ch LATD(5)
F8Bh LATC
F8Ah LATB
F89h LATA
FCBh PR2
FCAh T2CON
FC9h SSPBUF
FC8h SSPADD
FC7h SSPSTAT
FC6h SSPCON1
FC5h SSPCON2
FC4h ADRESH
FC3h ADRESL
FC2h ADCON0
FC1h ADCON1
FAAh
—
FE9h FSR0L
FA9h EEADR
FA8h EEDATA
FA7h EECON2
FA6h EECON1
FA5h IPR3
FA4h PIR3
FA3h PIE3
FA2h IPR2
FA1h PIR2
FA0h PIE2
FE8h WREG
F88h
F87h
F86h
F85h
—
—
—
—
FE7h INDF1(2)
FE6h POSTINC1(2)
FE5h POSTDEC1(2)
FE4h PREINC1(2)
FE3h PLUSW1(2)
FE2h FSR1H
F84h PORTE(5)
F83h PORTD(5)
F82h PORTC
F81h PORTB
F80h PORTA
FE1h FSR1L
FE0h BSR
FC0h
—
Note 1: Unimplemented registers are read as ‘0’.
2: This is not a physical register.
3: Contents of register are dependent on WIN2:WIN0 bits in the CANCON register.
4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the CANSTAT register due to the Microchip header file requirement.
5: These registers are not implemented on the PIC18F248 and PIC18F258.
© 2006 Microchip Technology Inc.
DS41159E-page 47
PIC18FXX8
TABLE 4-1:
SPECIAL FUNCTION REGISTER MAP (CONTINUED)
Address
Name
Address
Name
Address
Name
Address
Name
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
—
—
—
—
—
—
—
—
—
F5Fh
—
F3Fh
—
F1Fh RXM1EIDL
F1Eh RXM1EIDH
F1Dh RXM1SIDL
F1Ch RXM1SIDH
F1Bh RXM0EIDL
F1Ah RXM0EIDH
F19h RXM0SIDL
F18h RXM0SIDH
F17h RXF5EIDL
F16h RXF5EIDH
F15h RXF5SIDL
F14h RXF5SIDH
F13h RXF4EIDL
F12h RXF4EIDH
F11h RXF4SIDL
F10h RXF4SIDH
F0Fh RXF3EIDL
F0Eh RXF3EIDH
F0Dh RXF3SIDL
F0Ch RXF3SIDH
F0Bh RXF2EIDL
F0Ah RXF2EIDH
F09h RXF2SIDL
F08h RXF2SIDH
F07h RXF1EIDL
F06h RXF1EIDH
F05h RXF1SIDL
F04h RXF1SIDH
F03h RXF0EIDL
F02h RXF0EIDH
F01h RXF0SIDL
F00h RXF0SIDH
F5Eh CANSTATRO1(4)
F5Dh RXB1D7
F5Ch RXB1D6
F5Bh RXB1D5
F5Ah RXB1D4
F59h RXB1D3
F58h RXB1D2
F57h RXB1D1
F56h RXB1D0
F55h RXB1DLC
F54h RXB1EIDL
F53h RXB1EIDH
F52h RXB1SIDL
F51h RXB1SIDH
F50h RXB1CON
F3Eh CANSTATRO3(4)
F3Dh TXB1D7
F3Ch TXB1D6
F3Bh TXB1D5
F3Ah TXB1D4
F39h TXB1D3
F38h TXB1D2
F37h TXB1D1
F36h TXB1D0
F35h TXB1DLC
F34h TXB1EIDL
F33h TXB1EIDH
F32h TXB1SIDL
F31h TXB1SIDH
F30h TXB1CON
F76h TXERRCNT
F75h RXERRCNT
F74h COMSTAT
F73h CIOCON
F72h BRGCON3
F71h BRGCON2
F70h BRGCON1
F6Fh CANCON
F4Fh
—
F2Fh
—
F6Eh CANSTAT
F6Dh RXB0D7(3)
F6Ch RXB0D6(3)
F6Bh RXB0D5(3)
F6Ah RXB0D4(3)
F69h RXB0D3(3)
F68h RXB0D2(3)
F67h RXB0D1(3)
F66h RXB0D0(3)
F65h RXB0DLC(3)
F64h RXB0EIDL(3)
F63h RXB0EIDH(3)
F62h RXB0SIDL(3)
F61h RXB0SIDH(3)
F60h RXB0CON(3)
F4Eh CANSTATRO2(4)
F4Dh TXB0D7
F4Ch TXB0D6
F4Bh TXB0D5
F4Ah TXB0D4
F49h TXB0D3
F48h TXB0D2
F47h TXB0D1
F46h TXB0D0
F45h TXB0DLC
F44h TXB0EIDL
F43h TXB0EIDH
F42h TXB0SIDL
F41h TXB0SIDH
F40h TXB0CON
F2Eh CANSTATRO4(4)
F2Dh TXB2D7
F2Ch TXB2D6
F2Bh TXB2D5
F2Ah TXB2D4
F29h TXB2D3
F28h TXB2D2
F27h TXB2D1
F26h TXB2D0
F25h TXB2DLC
F24h TXB2EIDL
F23h TXB2EIDH
F22h TXB2SIDL
F21h TXB2SIDH
F20h TXB2CON
Note:
Shaded registers are available in Bank 15, while the rest are in Access Bank low.
Note 1: Unimplemented registers are read as ‘0’.
2: This is not a physical register.
3: Contents of register are dependent on WIN2:WIN0 bits in the CANCON register.
4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the CANSTAT register due to the Microchip header file requirement.
5: These registers are not implemented on the PIC18F248 and PIC18F258.
DS41159E-page 48
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 4-2:
REGISTER FILE SUMMARY
Value on Details on
Bit 0
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
POR, BOR
Page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
111- -1-1
11-0 0-00
N/A
30, 38
30, 38
30, 38
30, 39
30, 40
30, 40
30, 40
30, 68
30, 68
30, 68
30, 68
30, 75
30, 75
30, 79
30, 80
30, 81
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
31, 55
31, 55
31, 54
31, 55
31, 55
31, 55
31, 55
31, 55
31, 55
31, 55
31, 57
31, 111
31, 111
31, 109
31, 20
31, 261
31, 272
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
bit 21(2)
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
—
—
bit 21(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
INTCON
INTCON2
INTCON3
INDF0
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
—
INT0IE
—
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
INT2IP
INT2IE
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
N/A
N/A
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- xxxx
xxxx xxxx
---- 0000
N/A
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
---- ---0
--00 0101
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
TMR0H
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
TMR0L
T0CON
TMR0ON
T08BIT
—
T0CS
—
T0SE
—
PSA
—
T0PS2
—
T0PS1
—
T0PS0
SCS
OSCCON
LVDCON
WDTCON
—
—
—
—
IRVST
—
LVDEN
—
LVDL3
—
LVDL2
—
LVDL1
—
LVDL0
—
SWDTEN ---- ---0
BOR 0--1 110q 31, 58, 91
RCON
IPEN
—
—
RI
TO
PD
POR
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
© 2006 Microchip Technology Inc.
DS41159E-page 49
PIC18FXX8
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
Value on Details on
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
Page:
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx
xxxx xxxx
31, 116
31, 116
31, 113
31, 118
31, 118
31, 117
31, 146
31, 152
RD16
—
T1CKPS1
TOUTPS2
T1CKPS0
TOUTPS1
T1OSCEN
TOUTPS0
T1SYNC
TMR2ON
TMR1CS
TMR1ON 0-00 0000
0000 0000
Timer2 Register
PR2
Timer2 Period Register
TOUTPS3
1111 1111
T2CON
SSPBUF
SSPADD
SSPSTAT
—
T2CKPS1 T2CKPS0 -000 0000
SSP Receive Buffer/Transmit Register
SSP Address Register in I2C™ Slave mode. SSP Baud Rate Reload Register in I2C Master mode.
xxxx xxxx
0000 0000
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 31, 144,
153
SSPCON1
SSPOV
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
0000 0000 31, 145,
145
SSPCON2
ADRESH
ADRESL
ACKSTAT
ACKEN
0000 0000
xxxx xxxx
xxxx xxxx
0000 00-0
00-- 0000
xxxx xxxx
xxxx xxxx
31, 155
31, 243
31, 243
31, 241
32, 242
32, 124
32, 124
32, 123
32, 133
32, 133
32, 131
32, 140
32, 142
32, 255
32, 249
32, 121
32, 121
A/D Result Register High Byte
A/D Result Register Low Byte
ADCON0
ADCON1
CCPR1H
ADCS1
ADFM
ADCS0
ADCS2
CHS2
—
CHS1
—
CHS0
GO/DONE
PCFG2
—
ADON
PCFG3
PCFG1
PCFG0
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
CCPR1L
CCP1CON
ECCPR1H(1)
ECCPR1L(1)
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000
xxxx xxxx
Enhanced Capture/Compare/PWM Register 1 High Byte
Enhanced Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
ECCP1CON(1) EPWM1M1 EPWM1M0
EDC1B1
EPDC5
ECCPAS1
CVRR
EDC1B0
EPDC4
ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000
ECCP1DEL(1)
ECCPAS(1)
CVRCON(1)
CMCON(1)
TMR3H
EPDC7
ECCPASE
CVREN
EPDC6
ECCPAS2
CVROE
C1OUT
EPDC3
PSSAC1
CVR3
EPDC2
PSSAC0
CVR2
EPDC1
PSSBD1
CVR1
EPDC0
0000 0000
ECCPAS0
CVRSS
C1INV
PSSBD0 0000 0000
CVR0
CM0
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
C2OUT
C2INV
CIS
CM2
CM1
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3L
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR3
RD16
T3ECCP1
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON 0000 0000
0000 0000
32, 119
32, 185
32, 191
32, 189
32, 183
32, 184
32, 59
USART Baud Rate Generator
USART Receive Register
USART Transmit Register
0000 0000
0000 0000
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 -010
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
ADDEN
EEPROM Address Register
EEPROM Data Register
32, 59
EEPROM Control Register 2 (not a physical register)
32, 59
EEPGD
IRXIP
IRXIF
IRXIE
—
CFGS
WAKIP
WAKIF
WAKIE
CMIP
—
ERRIP
ERRIF
ERRIE
—
FREE
TXB2IP
TXB2IF
TXB2IE
EEIP
WRERR
TXB1IP
TXB1IF
TXB1IE
BCLIP
WREN
TXB0IP
TXB0IF
TXB0IE
LVDIP
WR
RD
xx-0 x000 32, 60, 67
RXB1IP
RXB1IF
RXB1IE
RXB0IP 1111 1111
RXB0IF 0000 0000
RXB0IE 0000 0000
32, 90
32, 84
32, 87
32, 89
32, 83
32, 86
PIR3
PIE3
IPR2
TMR3IP ECCP1IP(1) -1-1 1111
TMR3IF ECCP1IF(1) -0-0 0000
TMR3IE ECCP1IE(1) -0-0 0000
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
DS41159E-page 50
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
Value on Details on
Bit 0
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
POR, BOR
Page:
IPR1
PSPIP(1)
PSPIF(1)
PSPIE(1)
IBF
ADIP
ADIF
ADIE
OBF
RCIP
RCIF
RCIE
IBOV
TXIP
TXIF
SSPIP
SSPIF
SSPIE
—
CCP1IP
CCP1IF
CCP1IE
TMR2IP
TMR2IF
TMR2IE
TMR1IP 1111 1111
TMR1IF 0000 0000
TMR1IE 0000 0000
32, 88
32, 82
PIR1
PIE1
TXIE
32, 85
TRISE(1)
TRISD(1)
TRISC
TRISB
TRISA(3)
LATE(1)
PSPMODE
Data Direction bits for PORTE(1)
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111
---- -xxx
33, 105
33, 102
33, 100
33, 96
Data Direction Control Register for PORTD(1)
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
—
—
Data Direction Control Register for PORTA
33, 93
—
—
—
—
Read PORTE Data Latch, Write
PORTE Data Latch(1)
33, 104
LATD(1)
LATC
Read PORTD Data Latch, Write PORTD Data Latch(1)
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
33, 102
33, 100
33, 96
LATB
LATA(3)
PORTE(1)
—
—
Read PORTA Data Latch, Write PORTA Data Latch
33, 93
—
—
—
—
Read PORTE pins, Write PORTE Data ---- -xxx
33, 104
Latch(1)
PORTD(1)
PORTC
Read PORTD pins, Write PORTD Data Latch(1)
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000
33, 102
33, 100
33, 96
PORTB
PORTA(3)
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
—
Read PORTA pins, Write PORTA Data Latch
33, 93
TEC7
REC7
TEC6
REC6
TEC5
REC5
TEC4
REC4
TEC3
REC3
TEC2
REC2
TEC1
REC1
TEC0
REC0
0000 0000
0000 0000
33, 209
33, 214
33, 205
33, 221
33, 220
33, 219
33, 218
33, 201
33, 202
33, 214
33, 214
33, 214
33, 214
33, 214
33, 214
33, 214
33, 214
34, 213
34, 213
34, 212
34, 212
34, 212
34, 210
RXB0OVFL RXB1OVFL
TXBO
TXBP
RXBP
TXWARN RXWARN
EWARN 0000 0000
--00 ----
SEG2PH2 SEG2PH1 SEG2PH0 -0-- -000
—
—
—
ENDRHI
—
CANCAP
—
—
—
—
—
BRGCON3
BRGCON2
BRGCON1
CANCON
CANSTAT
RXB0D7
WAKFIL
SAM
—
SEG2PHTS
SJW1
SEG1PH2
BRP5
SEG1PH1
BRP4
SEG1PH0
BRP3
PRSEG2
BRP2
PRSEG1
BRP1
PRSEG0 0000 0000
SJW0
BRP0
—
0000 0000
xxxx xxx-
xxx- xxx-
REQOP2
REQOP1
REQOP0
ABAT
WIN2
WIN1
WIN0
OPMODE2 OPMODE1 OPMODE0
—
ICODE2
RXB0D73
RXB0D63
RXB0D53
RXB0D43
RXB0D33
RXB0D23
RXB0D13
RXB0D03
DLC3
ICODE1
ICODE0
—
RXB0D77
RXB0D67
RXB0D57
RXB0D47
RXB0D37
RXB0D27
RXB0D17
RXB0D07
—
RXB0D76
RXB0D66
RXB0D56
RXB0D46
RXB0D36
RXB0D26
RXB0D16
RXB0D06
RXRTR
EID6
RXB0D75
RXB0D65
RXB0D55
RXB0D45
RXB0D35
RXB0D25
RXB0D15
RXB0D05
RB1
RXB0D74
RXB0D64
RXB0D54
RXB0D44
RXB0D34
RXB0D24
RXB0D14
RXB0D04
RB0
RXB0D72 RXB0D71 RXB0D70 xxxx xxxx
RXB0D62 RXB0D61 RXB0D60 xxxx xxxx
RXB0D52 RXB0D51 RXB0D50 xxxx xxxx
RXB0D42 RXB0D41 RXB0D40 xxxx xxxx
RXB0D32 RXB0D31 RXB0D30 xxxx xxxx
RXB0D22 RXB0D21 RXB0D20 xxxx xxxx
RXB0D12 RXB0D11 RXB0D10 xxxx xxxx
RXB0D02 RXB0D01 RXB0D00 xxxx xxxx
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
DLC2
EID2
EID10
—
DLC1
EID1
DLC0
EID0
EID8
EID16
SID3
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
EID7
EID5
EID4
EID3
EID15
EID14
EID13
EID12
EID11
EID9
SID2
SID1
SID0
SRR
EXID
EID17
SID4
SID10
SID9
SID8
SID7
SID6
SID5
RXFUL
RXM1
RXM0
—
RXRTRRO RXB0DBEN
JTOFF
FILHIT0 000- 0000
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
© 2006 Microchip Technology Inc.
DS41159E-page 51
PIC18FXX8
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
Value on Details on
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
Page:
CANSTATRO1 OPMODE2 OPMODE1 OPMODE0
—
ICODE2
RXB1D73
RXB1D63
RXB1D53
RXB1D43
RXB1D33
RXB1D23
RXB1D13
RXB1D03
DLC3
ICODE1
ICODE0
—
xxx- xxx-
33, 202
34, 214
34, 214
34, 214
34, 214
34, 214
34, 214
34, 214
34, 214
34, 213
34, 213
34, 212
34, 212
34, 212
34, 211
33, 202
34, 208
34, 208
34, 208
34, 208
34, 208
34, 208
34, 208
34, 208
34, 209
34, 208
34, 207
34, 207
35, 207
35, 206
33, 202
35, 208
35, 208
35, 208
35, 208
35, 208
35, 208
35, 208
35, 208
35, 209
35, 208
35, 207
35, 207
35, 207
35, 206
RXB1D7
RXB1D77
RXB1D67
RXB1D57
RXB1D47
RXB1D37
RXB1D27
RXB1D17
RXB1D07
—
RXB1D76
RXB1D66
RXB1D56
RXB1D46
RXB1D36
RXB1D26
RXB1D16
RXB1D06
RXRTR
EID6
RXB1D75
RXB1D65
RXB1D55
RXB1D45
RXB1D35
RXB1D25
RXB1D15
RXB1D05
RB1
RXB1D74
RXB1D64
RXB1D54
RXB1D44
RXB1D34
RXB1D24
RXB1D14
RXB1D04
RB0
RXB1D72 RXB1D71 RXB1D70 xxxx xxxx
RXB1D62 RXB1D61 RXB1D60 xxxx xxxx
RXB1D52 RXB1D51 RXB1D50 xxxx xxxx
RXB1D42 RXB1D41 RXB1D40 xxxx xxxx
RXB1D32 RXB1D31 RXB1D30 xxxx xxxx
RXB1D22 RXB1D21 RXB1D20 xxxx xxxx
RXB1D12 RXB1D11 RXB1D10 xxxx xxxx
RXB1D02 RXB1D01 RXB1D00 xxxx xxxx
RXB1D6
RXB1D5
RXB1D4
RXB1D3
RXB1D2
RXB1D1
RXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
DLC2
EID2
DLC1
EID1
DLC0
EID0
EID8
EID16
SID3
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
EID7
EID5
EID4
EID3
EID15
EID14
EID13
EID12
EID11
EID10
—
EID9
SID2
SID1
SID0
SRR
EXID
EID17
SID4
SID10
SID9
SID8
SID7
SID6
SID5
RXFUL
RXM1
RXM0
—
RXRTRRO
ICODE2
TXB0D73
TXB0D63
TXB0D53
TXB0D43
TXB0D33
TXB0D23
TXB0D13
TXB0D03
DLC3
FILHIT2
ICODE1
FILHIT1
ICODE0
FILHIT0 000- 0000
xxx- xxx-
CANSTATRO2 OPMODE2 OPMODE1 OPMODE0
—
—
TXB0D7
TXB0D77
TXB0D67
TXB0D57
TXB0D47
TXB0D37
TXB0D27
TXB0D17
TXB0D07
—
TXB0D76
TXB0D66
TXB0D56
TXB0D46
TXB0D36
TXB0D26
TXB0D16
TXB0D06
TXRTR
EID6
TXB0D75
TXB0D65
TXB0D55
TXB0D45
TXB0D35
TXB0D25
TXB0D15
TXB0D05
—
TXB0D74
TXB0D64
TXB0D54
TXB0D44
TXB0D34
TXB0D24
TXB0D14
TXB0D04
—
TXB0D72 TXB0D71 TXB0D70 xxxx xxxx
TXB0D62 TXB0D61 TXB0D60 xxxx xxxx
TXB0D52 TXB0D51 TXB0D50 xxxx xxxx
TXB0D42 TXB0D41 TXB0D40 xxxx xxxx
TXB0D32 TXB0D31 TXB0D30 xxxx xxxx
TXB0D22 TXB0D21 TXB0D20 xxxx xxxx
TXB0D6
TXB0D5
TXB0D4
TXB0D3
TXB0D2
TXB0D1
TXB0D12
TXB0D11 TXB0D10 xxxx xxxx
TXB0D0
TXB0D02 TXB0D01 TXB0D00 xxxx xxxx
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
DLC2
EID2
EID10
—
DLC1
EID1
DLC0
EID0
EID8
EID16
SID3
TXPRI0
—
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
-000 0-00
xxx- xxx-
EID7
EID5
EID4
EID3
EID15
EID14
EID13
EID12
EID11
EID9
SID2
SID1
SID0
—
EXIDE
EID17
SID4
SID10
SID9
SID8
SID7
SID6
SID5
—
—
TXABT
TXLARB
TXERR
—
TXREQ
ICODE2
TXB1D73
TXB1D63
TXB1D53
TXB1D43
TXB1D33
TXB1D23
TXB1D13
TXB1D03
DLC3
TXPRI1
ICODE0
CANSTATRO3 OPMODE2 OPMODE1 OPMODE0
ICODE1
TXB1D7
TXB1D77
TXB1D67
TXB1D57
TXB1D47
TXB1D37
TXB1D27
TXB1D17
TXB1D07
—
TXB1D76
TXB1D66
TXB1D56
TXB1D46
TXB1D36
TXB1D26
TXB1D16
TXB1D06
TXRTR
EID6
TXB1D75
TXB1D65
TXB1D55
TXB1D45
TXB1D35
TXB1D25
TXB1D15
TXB1D05
—
TXB1D74
TXB1D64
TXB1D54
TXB1D44
TXB1D34
TXB1D24
TXB1D14
TXB1D04
—
TXB1D72 TXB1D71 TXB1D70 xxxx xxxx
TXB1D62 TXB1D61 TXB1D60 xxxx xxxx
TXB1D52 TXB1D51 TXB1D50 xxxx xxxx
TXB1D42 TXB1D41 TXB1D40 xxxx xxxx
TXB1D32 TXB1D31 TXB1D30 xxxx xxxx
TXB1D22 TXB1D21 TXB1D20 xxxx xxxx
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D12
TXB1D11 TXB1D10 xxxx xxxx
TXB1D0
TXB1D02 TXB1D01 TXB1D00 xxxx xxxx
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
DLC2
EID2
EID10
—
DLC1
EID1
DLC0
EID0
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
0000 0000
EID7
EID5
EID4
EID3
EID15
EID14
EID13
EID12
EID11
EID9
EID8
SID2
SID1
SID0
—
EXIDE
EID17
SID4
EID16
SID3
SID10
SID9
SID8
SID7
SID6
SID5
—
—
TXABT
TXLARB
TXERR
TXREQ
TXPRI1
TXPRI0
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
DS41159E-page 52
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
Value on Details on
Bit 0
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
POR, BOR
Page:
CANSTATRO4 OPMODE2 OPMODE1 OPMODE0
—
TXB2D74
TXB2D64
TXB2D54
TXB2D44
TXB2D34
TXB2D24
TXB2D14
TXB2D04
—
ICODE2
TXB2D73
TXB2D63
TXB2D53
TXB2D43
TXB2D33
TXB2D23
TXB2D13
TXB2D03
DLC3
ICODE1
ICODE0
—
xxx- xxx-
33, 202
35, 208
35, 208
35, 208
35, 208
35, 208
35, 208
35, 208
35, 208
35, 209
35, 208
35, 207
35, 207
35, 207
35, 206
35, 217
35, 217
36, 217
36, 216
36, 217
36, 217
36, 217
36, 216
36, 216
36, 216
36, 215
36, 215
36, 216
36, 216
36, 215
36, 215
36, 216
36, 216
36, 215
36, 215
36, 216
36, 216
36, 215
36, 215
36, 216
36, 216
36, 215
36, 215
36, 216
36, 216
36, 215
36, 215
TXB2D7
TXB2D77
TXB2D67
TXB2D57
TXB2D47
TXB2D37
TXB2D27
TXB2D17
TXB2D07
—
TXB2D76
TXB2D66
TXB2D56
TXB2D46
TXB2D36
TXB2D26
TXB2D16
TXB2D06
TXRTR
EID6
TXB2D75
TXB2D65
TXB2D55
TXB2D45
TXB2D35
TXB2D25
TXB2D15
TXB2D05
—
TXB2D72 TXB2D71 TXB2D70 xxxx xxxx
TXB2D62 TXB2D61 TXB2D60 xxxx xxxx
TXB2D52 TXB2D51 TXB2D50 xxxx xxxx
TXB2D42 TXB2D41 TXB2D40 xxxx xxxx
TXB2D32 TXB2D31 TXB2D30 xxxx xxxx
TXB2D22 TXB2D21 TXB2D20 xxxx xxxx
TXB2D6
TXB2D5
TXB2D4
TXB2D3
TXB2D2
TXB2D1
TXB2D12
TXB2D11 TXB2D10 xxxx xxxx
TXB2D0
TXB2D02 TXB2D01 TXB2D00 xxxx xxxx
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
RXM1EIDL
RXM1EIDH
RXM1SIDL
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
RXM0SIDH
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
RXF3SIDL
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
RXF1EIDL
RXF1EIDH
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
DLC2
EID2
EID10
—
DLC1
EID1
EID9
EID17
SID4
TXPRI1
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
DLC0
EID0
EID8
EID16
SID3
TXPRI0
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
-000 0-00
xxxx xxxx
xxxx xxxx
xxx- --xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- --xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
EID7
EID5
EID4
EID3
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EXIDE
SID6
SID10
—
SID9
SID8
SID7
SID5
—
TXABT
EID6
TXLARB
EID5
TXERR
EID4
TXREQ
EID3
EID7
EID2
EID10
—
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
—
SID10
EID7
SID9
SID8
SID7
SID6
SID5
EID2
EID10
—
EID6
EID5
EID4
EID3
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
—
SID10
EID7
SID9
SID8
SID7
SID6
SID5
EID2
EID10
—
EID6
EID5
EID4
EID3
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EXIDEN
SID6
SID10
EID7
SID9
SID8
SID7
SID5
EID2
EID10
—
EID6
EID5
EID4
EID3
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EXIDEN
SID6
SID10
EID7
SID9
SID8
SID7
SID5
EID2
EID10
—
EID6
EID5
EID4
EID3
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EXIDEN
SID6
SID10
EID7
SID9
SID8
SID7
SID5
EID2
EID10
—
EID6
EID5
EID4
EID3
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EXIDEN
SID6
SID10
EID7
SID9
SID8
SID7
SID5
EID2
EID10
—
EID6
EID5
EID4
EID3
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EXIDEN
SID6
SID10
EID7
SID9
SID8
SID7
SID5
EID2
EID10
—
EID6
EID5
EID4
EID3
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EXIDEN
SID6
SID10
SID9
SID8
SID7
SID5
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
© 2006 Microchip Technology Inc.
DS41159E-page 53
PIC18FXX8
4.10 Access Bank
4.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement that
is very useful for C compiler code optimization. The
techniques used by the C compiler are also useful for
programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect.
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
A
MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
• Faster evaluation/control of SFRs (no banking)
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access Bank
High and Access Bank Low, respectively. Figure 4-6
indicates the Access Bank areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank.
A MOVFFinstruction ignores the BSR since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = 0), the last
address in Access Bank Low is followed by the first
address in Access Bank High. Access Bank High maps
most of the Special Function Registers so that these
registers can be accessed without any software
overhead.
FIGURE 4-7:
DIRECT ADDRESSING
Direct Addressing
(3)
From Opcode
BSR<3:0>
7
0
(2)
(3)
Bank Select
Location Select
00h
000h
01h
100h
0Eh
0Fh
0E00h
0F00h
Data
Memory(1)
0FFh
1FFh
0EFFh
0FFFh
Bank 0
Bank 1
Bank 14 Bank 15
Note 1: For register file map detail, see Table 4-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
DS41159E-page 54
© 2006 Microchip Technology Inc.
PIC18FXX8
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
Status bits are not affected.
4.12 Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data mem-
ory where the data memory address in the instruction
is not fixed. A SFR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-8
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated with
it, plus four additional register addresses. Performing an
operation on one of these five registers determines how
the FSR will be modified during indirect addressing.
• When data access is done to one of the five
INDFn locations, the address selected will
configure the FSRn register to:
Indirect addressing is possible by using one of the INDF
registers. Any instruction using the INDF register actually
accesses the register indicated by the File Select Regis-
ter, FSR. Reading the INDF register itself, indirectly
(FSR = 0), will read 00h. Writing to the INDF register
indirectly, results in a no operation. The FSR register
contains a 12-bit address which is shown in Figure 4-8.
- Do nothing to FSRn after an indirect access
(no change) – INDFn
- Auto-decrement FSRn after an indirect
access (post-decrement) – POSTDECn
- Auto-increment FSRn after an indirect
access (post-increment) – POSTINCn
The INDFn (0 ≤ n ≤ 2) register is not a physical register.
Addressing INDFn actually addresses the register
whose address is contained in the FSRn register
(FSRn is a pointer). This is indirect addressing.
- Auto-increment FSRn before an indirect
access (pre-increment) – PREINCn
- Use the value in the WREG register as an
offset to FSRn. Do not modify the value of the
WREG or the FSRn register after an indirect
access (no change) – PLUSWn
Example 4-5 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
EXAMPLE 4-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
FSR0, 100h ;
LFSR
NEXT
CLRF
POSTINC0
; Clear INDF
; register
; & inc pointer
; All done
; w/ Bank1?
; NO, clear next
;
Incrementing or decrementing an FSR affects all
12 bits. That is, when FSRnL overflows from an
increment, FSRnH will be incremented automatically.
BTFSS
BRA
FSR0H, 1
NEXT
Adding these features allows the FSRn to be used as a
software stack pointer in addition to its uses for table
operations in data memory.
CONTINUE
:
; YES, continue
Each FSR has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the 2’s complement value in
the WREG register and the value in FSR to form the
address before an indirect access. The FSR value is not
changed.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
If an FSR register contains a value that indicates one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or
post-increment/decrement functions.
If an instruction writes a value to INDF0, the value will
be written to the address indicated by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
indicated by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
© 2006 Microchip Technology Inc.
DS41159E-page 55
PIC18FXX8
FIGURE 4-8:
INDIRECT ADDRESSING
Indirect Addressing
FSR Register
11
8
7
0
FSRnH
FSRnL
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-1.
DS41159E-page 56
© 2006 Microchip Technology Inc.
PIC18FXX8
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the Status register as
000u u1uu(where u= unchanged).
4.13 Status Register
The Status register, shown in Register 4-2, contains the
arithmetic status of the ALU. The Status register can be
the destination for any instruction, as with any other
register. If the Status register is the destination for an
instruction that affects the Z, DC, C, OV or N bits, then
the write to these five bits is disabled. These bits are set
or cleared according to the device logic. Therefore, the
result of an instruction with the Status register as
destination may be different than intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the Status register, because these instructions do
not affect the Z, C, DC, OV or N bits from the Status
register. For other instructions which do not affect the
status bits, see Table 25-2.
Note: The C and DC bits operate as a Borrow
and Digit Borrow bit respectively, in
subtraction.
REGISTER 4-2:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4
bit 3
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU
operation was negative (ALU MSb = 1).
1= Result was negative
0= Result was positive
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
Note:
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s
complement of the second operand. For rotate (RRCF, RRNCF, RLCF and RLNCF)
instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
bit 0
C: Carry/Borrow bit
For ADDWF, ADDLW, SUBLWand SUBWF instructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 57
PIC18FXX8
4.14 RCON Register
Note 1: If the BOREN configuration bit is set,
BOR is ‘1’ on Power-on Reset. If the
BOREN configuration bit is clear, BOR is
unknown on Power-on Reset.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bits. Thisregisteris readableandwritable.
The BOR status bit is a “don’t care” and is
not necessarily predictable if the brown-
out circuit is disabled (the BOREN config-
uration bit is clear). BOR must then be set
by the user and checked on subsequent
Resets to see if it is clear, indicating a
brown-out has occurred.
2: It is recommended that the POR bit be set
after
a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 4-3:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R/W
TO
R/W
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed
0= The RESETinstruction was executed causing a device Reset
(must be set in software after a Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down Detection Flag bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 58
© 2006 Microchip Technology Inc.
PIC18FXX8
5.1
EEADR Register
5.0
DATA EEPROM MEMORY
The address register can address up to a maximum of
256 bytes of data EEPROM.
The data EEPROM is readable and writable during
normal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
5.2
EECON1 and EECON2 Registers
EECON1 is the control register for EEPROM memory
accesses.
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
• EECON1
• EECON2
• EEDATA
• EEADR
Control bits, RD and WR, initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed. The
PIC18FXX8 devices have 256 bytes of data EEPROM
with an address range from 00h to FFh.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal oper-
ation. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR) due to the Reset condition forcing the
contents of the registers to zero.
The EEPROM data memory is rated for high erase/
write cycles. A byte write automatically erases the loca-
tion and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip-to-chip. Please refer to the specifications for
exact limits.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
© 2006 Microchip Technology Inc.
DS41159E-page 59
PIC18FXX8
REGISTER 5-1:
EECON1: EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access program Flash memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1= Access Configuration registers
0= Access program Flash or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(reset by hardware)
0= Perform write only
bit 3
WRERR: Write Error Flag bit
1= A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0= The write operation completed
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM or Flash memory
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
S = Settable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value at POR ‘1’ = Bit is set
‘0’ = Bit is cleared
DS41159E-page 60
© 2006 Microchip Technology Inc.
PIC18FXX8
5.3
Reading the Data EEPROM
Memory
5.4
Writing to the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD and
CFGS control bits (EECON1<7:6>) and then set
control bit RD (EECON1<0>). The data is available in
the very next instruction cycle of the EEDATA register;
therefore, it can be read by the next instruction.
EEDATA will hold this value until another read
operation or until it is written to by the user (during a
write operation).
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. Then, the sequence in
Example 5-2 must be followed to initiate the write cycle.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
EXAMPLE 5-1:
DATA EEPROM READ
MOVLW DATA_EE_ADDR
MOVWF EEADR
;
;Data Memory Address
;to read
BCF
BCS
BSF
MOVF
EECON1, EEPGD ;Point to DATA memory
EECON1, CFGS
EECON1, RD
EEDATA, W
;
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
;EEPROM Read
;W = EEDATA
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt or roll this bit. EEIF must be
cleared by software.
EXAMPLE 5-2:
DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BCF
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
;
; Data Memory Address to read
;
; Data Memory Value to write
EECON1, EEPGD ; Point to DATA memory
BCF
BSF
EECON1, CFGS
EECON1, WREN
; Access program FLASH or Data EEPROM memory
; Enable writes
BCF
INTCON, GIE
55h
EECON2
0AAh
EECON2
; Disable interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Enable interrupts
Required
Sequence
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, WR
INTCON, GIE
BSF
.
; user code execution
.
.
BCF
EECON1, WREN
; Disable writes on write complete (EEIF set)
© 2006 Microchip Technology Inc.
DS41159E-page 61
PIC18FXX8
5.5
Write Verify
5.7
Operation During Code-Protect
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
Data EEPROM memory has its own code-protect
mechanism. External read and write operations are
disabled if either of these mechanisms are enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 24.0
“Special Features of the CPU” for additional
information.
Generally, a write failure will be a bit which was written
as a ‘1’, but reads back as a ‘0’ (due to leakage off the
cell).
5.6
Protection Against Spurious Write
5.8
Using the Data EEPROM
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specification D124 or D124A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory. A simple data EEPROM
refresh routine is shown in Example 5-3.
The write initiate sequence and the WREN bit together
reduce the probability of an accidental write during
brown-out, power glitch or software malfunction.
Note:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.
EXAMPLE 5-3:
DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF
EEADR
; Start at address 0
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
Loop
BSF
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
EEADR, F
Loop
; Increment address
; Not zero, do it again
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
DS41159E-page 62
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 5-1:
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Value on
Value on:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
POR, BOR
Resets
INTCON
EEADR
GIE/GIEH PEIE/GIEL TMR0IE
EEPROM Address Register
INT0IE
RBIE
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
EEDATA EEPROM Data Register
EECON2 EEPROM Control Register 2 (not a physical register)
—
—
EECON1
IPR2
EEPGD
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR WREN
WR
RD
xx-0 x000 uu-0 u000
-1-1 1111 -1-1 1111
-0-0 0000 -0-0 0000
-0-0 0000 -0-0 0000
(1)
(1)
(1)
—
—
—
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP ECCP1IP
TMR3IF ECCP1IF
PIR2
PIE2
TMR3IE ECCP1IE
Legend:
x= unknown, u= unchanged, r = reserved, -= unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 63
PIC18FXX8
NOTES:
DS41159E-page 64
© 2006 Microchip Technology Inc.
PIC18FXX8
6.1
Table Reads and Table Writes
6.0
FLASH PROGRAM MEMORY
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease instruc-
tion fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5
“Writing to Flash Program Memory”. Figure 6-2
shows the operation of a table write with program
memory and data RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into program
memory, program instructions will need to be word
aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
© 2006 Microchip Technology Inc.
DS41159E-page 65
PIC18FXX8
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>.
The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash
Program Memory”.
The FREE bit, when set, will allow a program memory
6.2
Control Registers
erase operation. When the FREE bit is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR) due to Reset values of zero.
6.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bits, RD and WR, initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation. The RD
bit cannot be set when accessing program memory
(EEPGD = 1).
Control bit EEPGD determines if the access will be a
program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
Control bit CFGS determines if the access will be to the
Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 24.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
Note: Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
DS41159E-page 66
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 6-1:
EECON1: EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access program Flash memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1= Access Configuration registers
0= Access program Flash or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
bit 3
WRERR: Write Error Flag bit
1= A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0= The write operation completed
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM or Flash memory
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
S = Settable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
© 2006 Microchip Technology Inc.
DS41159E-page 67
PIC18FXX8
6.2.2
TABLAT – TABLE LATCH REGISTER
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program
memory into TABLAT.
6.2.3
TBLPTR – TABLE POINTER
REGISTER
When a TBLWTis executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer, TBLPTR
(TBLPTR<21:3>), will determine which program
memory block of 8 bytes is written to. For more detail,
see Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR<21:6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
The Table Pointer, TBLPTR, is used by the TBLRDand
TBLWTinstructions. These instructions can update the
TBLPTR in one of four ways based on the table
operation. These operations are shown in Table 6-1.
These operations on the TBLPTR only affect the
low-order 21 bits.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
ERASE – TBLPTR<21:6>
WRITE – TBLPTR<21:3>
READ – TBLPTR<21:0>
DS41159E-page 68
© 2006 Microchip Technology Inc.
PIC18FXX8
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
6.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
FETCH
TBLRD
(IR)
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_LSB
; read into TABLAT and increment
; get data
TABLAT, W
WORD_MSB
MOVWF
© 2006 Microchip Technology Inc.
DS41159E-page 69
PIC18FXX8
6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the Flash array is not
supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer with address of row being
erased.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
2. Set the EECON1 register for the erase operation:
• set the EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set the WREN bit to enable writes;
• set the FREE bit to enable the erase.
3. Disable interrupts.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
For protection, the write initiate sequence for EECON2
must be used.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
8. Re-enable interrupts.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
upper (CODE_ADDR)
TBLPTRU
high (CODE_ADDR)
TBLPTRH
low (CODE_ADDR)
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BCF
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write 55H
Required
Sequence
; write 0AAH
; start erase (CPU stall)
; NOP needed for proper code execution
; re-enable interrupts
NOP
BSF
INTCON, GIE
DS41159E-page 70
© 2006 Microchip Technology Inc.
PIC18FXX8
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
6.5
Writing to Flash Program Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
The sequence of events for programming an internal
program memory location should be:
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer with address being erased.
4. Do the row erase procedure.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
5. Load Table Pointer with address of first byte
being written.
6. Write the first 8 bytes into the holding registers
using the TBLWT instruction, auto-increment
may be used.
7. Set the EECON1 register for the write operation:
• set the EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set the WREN to enable byte writes.
8. Disable interrupts.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
9. Write 55h to EECON2.
10. Write AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6-14 seven times to write
64 bytes.
15. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 8 bytes in
the holding registers.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx2
Holding Register
TBLPTR = xxxxx7
TBLPTR = xxxxx1
Holding Register
Holding Register
Holding Register
Program Memory
© 2006 Microchip Technology Inc.
DS41159E-page 71
PIC18FXX8
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64
COUNTER
high (BUFFER_ADDR)
FSR0H
low (BUFFER_ADDR)
FSR0L
upper (CODE_ADDR)
TBLPTRU
high (CODE_ADDR)
TBLPTRH
low (CODE_ADDR)
TBLPTRL
; number of bytes in erase block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
TBLRD*+
MOVF
MOVWF
; read into TABLAT, and inc
; get data
; store data
; done?
TABLAT, W
POSTINC0
DECFSZ COUNTER
BRA
READ_BLOCK
; repeat
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
upper (CODE_ADDR)
TBLPTRU
high (CODE_ADDR)
TBLPTRH
low (CODE_ADDR)
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
; load TBLPTR with the base
; address of the memory block
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
Required
Sequence
EECON2
0AAh
EECON2
EECON1, WR
; write 55H
; write AAH
; start erase (CPU stall)
NOP
BSF
TBLRD*-
INTCON, GIE
; re-enable interrupts
; dummy read decrement
WRITE_BUFFER_BACK
MOVLW
8
; number of write buffer groups of 8 bytes
; point to buffer
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
COUNTER_HI
high (BUFFER_ADDR)
FSR0H
low (BUFFER_ADDR)
FSR0L
PROGRAM_LOOP
MOVLW
MOVWF
8
; number of bytes in holding register
COUNTER
WRITE_WORD_TO_HREGS
MOVFW
MOVWF
TBLWT+*
POSTINC0, W
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
DECFSZ COUNTER
BRA WRITE_WORD_TO_HREGS
DS41159E-page 72
© 2006 Microchip Technology Inc.
PIC18FXX8
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
WRITE_WORD_TO_HREGS
MOVFW
MOVWF
POSTINC0, W
TABLAT
; get low byte of buffer data
; present data to table latch
TBLWT+*
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
DECFSZ COUNTER
BRA
WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; disable interrupts
; write 55h
Required
Sequence
; write 0AAh
; start program (CPU stall)
NOP
BSF
INTCON, GIE
; re-enable interrupts
; loop until done
DECFSZ COUNTER_HI
BRA
BCF
PROGRAM_LOOP
EECON1, WREN
; disable write to memory
6.5.2
WRITE VERIFY
6.5.4
PROTECTION AGAINST SPURIOUS
WRITES
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
To reduce the probability against spurious writes to
Flash program memory, the write initiate sequence
must also be followed. See Section 24.0 “Special
Features of the CPU” for more detail.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
6.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset or a WDT
Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
See Section 24.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
© 2006 Microchip Technology Inc.
DS41159E-page 73
PIC18FXX8
TABLE 6-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
--00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
TABLAT
Program Memory Table Latch
INTCON GIE/GIEH PEIE/
GIEL
TMR0IE
INTE
RBIE
TMR0IF
INTF
WR
RBIF
RD
EECON2 EEPROM Control Register 2 (not a physical register)
—
—
EECON1
IPR2
EEPGD
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR
BCLIP
BCLIF
BCLIE
WREN
LVDIP
LVDIF
LVDIE
xx-0 x000 uu-0 u000
-1-1 1111 -1-1 1111
-0-0 0000 -0-0 0000
-0-0 0000 -0-0 0000
(1)
(1)
(1)
—
—
—
TMR3IP ECCP1IP
TMR3IF ECCP1IF
TMR3IE ECCP1IE
PIR2
PIE2
Legend:
x= unknown, u= unchanged, -= unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 74
© 2006 Microchip Technology Inc.
PIC18FXX8
7.2
Operation
7.0
7.1
8 x 8 HARDWARE MULTIPLIER
Introduction
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX8 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
MOVF
MULWF
ARG1, W
ARG2
;
• Higher computational throughput
; ARG1 * ARG2 ->
;
• Reduces code size requirements for multiply
algorithms
PRODH:PRODL
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Table 7-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
MOVF
ARG1, W
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC
SUBWF
ARG2, SB
PRODH
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
TABLE 7-1:
Routine
PERFORMANCE COMPARISON
Program
Time
@ 40 MHz @ 10 MHz @ 4 MHz
Cycles
(Max)
Multiply Method
Memory
(Words)
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 μs
100 ns
9.1 μs
600 ns
24.2 μs
2.4 μs
25.4 μs
3.6 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
96.8 μs
9.6 μs
69 μs
1 μs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 μs
6 μs
242 μs
24 μs
254 μs
36 μs
Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
102.6 μs
14.4 μs
© 2006 Microchip Technology Inc.
DS41159E-page 75
PIC18FXX8
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 7-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
EQUATION 7-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L)+
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
16
(ARG1H • ARG2H • 2 ) +
)
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L)
EXAMPLE 7-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
EXAMPLE 7-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
;
;
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
;
;
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
ADDWF
MOVF
PRODL, W
RES1
PRODH, W
;
MOVF
MULWF
ARG1L, W
ARG2H
; Add cross
; products
; ARG1L * ARG2H ->
; PRODH:PRODL
ADDWFC RES2
CLRF WREG
ADDWFC RES3
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1
PRODH, W
;
; Add cross
; products
;
ADDWFC RES2
CLRF WREG
ADDWFC RES3
;
;
;
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
;
MOVF
ADDWF
MOVF
PRODL, W
RES1
PRODH, W
;
MOVF
MULWF
ARG1H, W
ARG2L
;
; Add cross
; products
; ARG1H * ARG2L ->
; PRODH:PRODL
ADDWFC RES2
CLRF WREG
ADDWFC RES3
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1
PRODH, W
;
; Add cross
; products
;
;
ADDWFC RES2
CLRF WREG
ADDWFC RES3
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
Example 7-4 shows the sequence to do a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pair’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS41159E-page 76
© 2006 Microchip Technology Inc.
PIC18FXX8
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. The PEIE bit (INTCON register)
enables/disables all peripheral interrupt sources. The
GIE bit (INTCON register) enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
8.0
INTERRUPTS
The PIC18FXX8 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will
override any low priority interrupts that may be in
progress.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
There are 13 registers that are used to control interrupt
operation. These registers are:
• RCON
• INTCON
• INTCON2
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
• INTCON3
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files,
supplied with MPLAB® IDE, be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON register). When interrupt priority is
enabled, there are two bits that enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts. Setting the GIEL bit (INTCON register)
enables all interrupts that have the priority bit cleared.
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will vec-
tor immediately to address 000008h or 000018h,
depending on the priority level. Individual interrupts can
be disabled through their corresponding enable bits.
© 2006 Microchip Technology Inc.
DS41159E-page 77
PIC18FXX8
FIGURE 8-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
Wake-up if in Sleep mode
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Interrupt to CPU
Vector to Location
0008h
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIE/GIEH
TMR1IF
TMR1IE
TMR1IP
IPEN
IPEN
GIEL/PEIE
XXXXIF
XXXXIE
XXXXIP
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR0IF
TMR0IE
TMR0IP
Interrupt to CPU
Vector to Location
0018h
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
RBIP
PEIE/GIEL
GIE/GIEH
XXXXIF
XXXXIE
XXXXIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS41159E-page 78
© 2006 Microchip Technology Inc.
PIC18FXX8
8.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows software polling.
The INTCON registers are readable and writable regis-
ters which contain various enable, priority and flag bits.
Because of the number of interrupts to be controlled,
PIC18FXX8 devices have three INTCON registers.
They are detailed in Register 8-1 through Register 8-3.
REGISTER 8-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
GIE/GIEH PEIE/GIEL TMR0IE
bit 7
INT0IE
TMR0IF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN (RCON<7>) = 1:
1= Enables all high priority interrupts
0= Disables all priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN (RCON<7>) = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software by reading PORTB)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 79
PIC18FXX8
REGISTER 8-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
R/W-1
U-0
U-0
R/W-1
U-0
—
R/W-1
RBIP
RBPU
INTEDG0 INTEDG1
—
—
TMR0IP
bit 7
bit 0
bit 7
bit 6
bit 5
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 4-3 Unimplemented: Read as ‘0’
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows software polling.
DS41159E-page 80
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 8-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows software polling.
© 2006 Microchip Technology Inc.
DS41159E-page 81
PIC18FXX8
8.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON
register).
The Peripheral Interrupt Request (PIR) registers
contain the individual flag bits for the peripheral
interrupts (Register 8-4 through Register 8-6). Due to
the number of peripheral interrupt sources, there are
three Peripheral Interrupt Request (Flag) registers
(PIR1, PIR2, PIR3).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
REGISTER 8-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The USART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 82
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 8-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0
—
R/W-0
CMIF(1)
U-0
—
R/W-0
EEIF
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
TMR3IF ECCP1IF(1)
R/W-0
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit(1)
1= Comparator input has changed
0= Comparator input has not changed
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIF: EEPROM Write Operation Interrupt Flag bit
1= Write operation is complete (must be cleared in software)
0= Write operation is not complete
bit 3
bit 2
bit 1
bit 0
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
LVDIF: Low-Voltage Detect Interrupt Flag bit
1= A low-voltage condition occurred (must be cleared in software)
0= The device voltage is above the Low-Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
ECCP1IF: ECCP1 Interrupt Flag bit(1)
Capture mode:
1= A TMR1 (TMR3) register capture occurred (must be cleared in software)
0= No TMR1 (TMR3) register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 83
PIC18FXX8
REGISTER 8-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
IRXIF
R/W-0
R/W-0
ERRIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIF: Invalid Message Received Interrupt Flag bit
1= An invalid message has occurred on the CAN bus
0= An invalid message has not occurred on the CAN bus
WAKIF: Bus Activity Wake-up Interrupt Flag bit
1= Activity on the CAN bus has occurred
0= Activity on the CAN bus has not occurred
ERRIF: CAN bus Error Interrupt Flag bit
1= An error has occurred in the CAN module (multiple sources)
0= An error has not occurred in the CAN module
TXB2IF: Transmit Buffer 2 Interrupt Flag bit
1= Transmit Buffer 2 has completed transmission of a message and may be reloaded
0= Transmit Buffer 2 has not completed transmission of a message
TXB1IF: Transmit Buffer 1 Interrupt Flag bit
1= Transmit Buffer 1 has completed transmission of a message and may be reloaded
0= Transmit Buffer 1 has not completed transmission of a message
TXB0IF: Transmit Buffer 0 Interrupt Flag bit
1= Transmit Buffer 0 has completed transmission of a message and may be reloaded
0= Transmit Buffer 0 has not completed transmission of a message
RXB1IF: Receive Buffer 1 Interrupt Flag bit
1= Receive Buffer 1 has received a new message
0= Receive Buffer 1 has not received a new message
RXB0IF: Receive Buffer 0 Interrupt Flag bit
1= Receive Buffer 0 has received a new message
0= Receive Buffer 0 has not received a new message
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 84
© 2006 Microchip Technology Inc.
PIC18FXX8
8.3
PIE Registers
The Peripheral Interrupt Enable (PIE) registers contain
the individual enable bits for the peripheral interrupts
(Register 8-7 through Register 8-9). Due to the number
of peripheral interrupt sources, there are three Periph-
eral Interrupt Enable registers (PIE1, PIE2, PIE3).
When IPEN is clear, the PEIE bit must be set to enable
any of these peripheral interrupts.
REGISTER 8-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
CCP1IE
TMR2IE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 85
PIC18FXX8
REGISTER 8-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
—
R/W-0
CMIE(1)
U-0
—
R/W-0
EEIE
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
TMR3IE ECCP1IE(1)
R/W-0
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit(1)
1= Enables the comparator interrupt
0= Disables the comparator interrupt
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIE: EEPROM Write Interrupt Enable bit
1= Enabled
0= Disabled
bit 3
bit 2
bit 1
bit 0
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enables the TMR3 overflow interrupt
0= Disables the TMR3 overflow interrupt
ECCP1IE: ECCP1 Interrupt Enable bit(1)
1= Enables the ECCP1 interrupt
0= Disables the ECCP1 interrupt
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 86
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 8-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-1
IRXIE
R/W-1
R/W-1
ERRIE
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WAKIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIE: Invalid CAN Message Received Interrupt Enable bit
1= Enables the invalid CAN message received interrupt
0= Disables the invalid CAN message received interrupt
WAKIE: Bus Activity Wake-up Interrupt Enable bit
1= Enables the bus activity wake-up interrupt
0= Disables the bus activity wake-up interrupt
ERRIE: CAN bus Error Interrupt Enable bit
1= Enables the CAN bus error interrupt
0= Disables the CAN bus error interrupt
TXB2IE: Transmit Buffer 2 Interrupt Enable bit
1= Enables the Transmit Buffer 2 interrupt
0= Disables the Transmit Buffer 2 interrupt
TXB1IE: Transmit Buffer 1 Interrupt Enable bit
1= Enables the Transmit Buffer 1 interrupt
0= Disables the Transmit Buffer 1 interrupt
TXB0IE: Transmit Buffer 0 Interrupt Enable bit
1= Enables the Transmit Buffer 0 interrupt
0= Disables the Transmit Buffer 0 interrupt
RXB1IE: Receive Buffer 1 Interrupt Enable bit
1= Enables the Receive Buffer 1 interrupt
0= Disables the Receive Buffer 1 interrupt
RXB0IE: Receive Buffer 0 Interrupt Enable bit
1= Enables the Receive Buffer 0 interrupt
0= Disables the Receive Buffer 0 interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 87
PIC18FXX8
8.4
IPR Registers
The Interrupt Priority (IPR) registers contain the individ-
ual priority bits for the peripheral interrupts. Due to the
number of peripheral interrupt sources, there are three
Peripheral Interrupt Priority registers (IPR1, IPR2 and
IPR3). The operation of the priority bits requires that
the Interrupt Priority Enable bit (IPEN) be set.
REGISTER 8-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
bit 7
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
R/W-1
R/W-1
TMR1IP
bit 0
CCP1IP
TMR2IP
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: USART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: USART Transmit Interrupt Priority bit
1= High priority
0= Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 88
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 8-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0
—
R/W-1
CMIP(1)
U-0
—
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
TMR3IP ECCP1IP(1)
R/W-1
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIP: Comparator Interrupt Priority bit(1)
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIP: EEPROM Write Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
LVDIP: Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
ECCP1IP: ECCP1 Interrupt Priority bit(1)
1= High priority
0= Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 89
PIC18FXX8
REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
IRXIP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WAKIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIP: Invalid Message Received Interrupt Priority bit
1= High priority
0= Low priority
WAKIP: Bus Activity Wake-up Interrupt Priority bit
1= High priority
0= Low priority
ERRIP: CAN bus Error Interrupt Priority bit
1= High priority
0= Low priority
TXB2IP: Transmit Buffer 2 Interrupt Priority bit
1= High priority
0= Low priority
TXB1IP: Transmit Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
TXB0IP: Transmit Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
RXB1IP: Receive Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
RXB0IP: Receive Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 90
© 2006 Microchip Technology Inc.
PIC18FXX8
8.5
RCON Register
The Reset Control (RCON) register contains the IPEN
bit which is used to enable prioritized interrupts. The
functions of the other bits in this register are discussed
in more detail in Section 4.14 “RCON Register”.
REGISTER 8-13: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
bit 3
bit 2
bit 1
bit 0
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-3.
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-3.
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-3.
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-3.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-3.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 91
PIC18FXX8
8.6
INT Interrupts
8.8
PORTB Interrupt-on-Change
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/CANTX/INT2 pins are edge triggered: either rising
if the corresponding INTEDGx bit is set in the
INTCON2 register, or falling if the INTEDGx bit is clear.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit INTxIF is set. This interrupt can
be disabled by clearing the corresponding enable bit
INTxIE. Flag bit INTxIF must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1 and INT2)
can wake-up the processor from Sleep if bit INTxIE was
set prior to going into Sleep. If the Global Interrupt
Enable bit, GIE, is set, the processor will branch to the
interrupt vector following wake-up.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON register). The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE (INTCON
register). Interrupt priority for PORTB interrupt-on-
change is determined by the value contained in the
interrupt priority bit RBIP (INTCON2 register).
8.9
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, Status and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 4.3 “Fast
Register Stack”), the user may need to save the
WREG, Status and BSR registers in software. Depend-
ing on the user’s application, other registers may also
need to be saved. Example 8-1 saves and restores the
WREG, Status and BSR registers during an Interrupt
Service Routine.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0; it is always a high
priority interrupt source.
8.7
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow (FFh →
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh → 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit TMR0IE (INTCON register). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2 register). See
Section 11.0 “Timer0 Module” for further details.
EXAMPLE 8-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in Low Access bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
DS41159E-page 92
© 2006 Microchip Technology Inc.
PIC18FXX8
Read-modify-write operations on the LATA register
read and write the latched output value for PORTA.
9.0
I/O PORTS
Depending on the device selected, there are up to five
general purpose I/O ports available on PIC18FXX8
devices. Some pins of the I/O ports are multiplexed
with an alternate function from the peripheral features
on the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open-drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1). On a Power-on Reset, these pins are
configured as analog inputs and read as ‘0’.
Each port has three registers for its operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The data latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA6 and RA4 are configured as
digital inputs.
9.1
PORTA, TRISA and LATA
Registers
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set, when using them as analog inputs.
PORTA is a 7-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin). On
a Power-on Reset, these pins are configured as inputs
and read as ‘0’.
EXAMPLE 9-1:
INITIALIZING PORTA
CLRF
PORTA ; Initialize PORTA by
; clearing output data latches
CLRF
LATA
; Alternate method to clear
; output data latches
; Configure A/D
MOVLW 07h
MOVWF ADCON1; for digital inputs
MOVLW 0CFh
; Value used to initialize
; data direction
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
MOVWF TRISA ; Set RA3:RA0 as inputs,
; RA5:RA4 as outputs
© 2006 Microchip Technology Inc.
DS41159E-page 93
PIC18FXX8
FIGURE 9-1:
RA3:RA0 AND RA5 PINS
BLOCK DIAGRAM
FIGURE 9-2:
RA4/T0CKI PIN BLOCK
DIAGRAM
RD LATA
Data Bus
RD LATA
Data Bus
Q
D
Q
D
VDD
WR LATA or
WR PORTA
WR LATA or
WR PORTA
CK
Data Latch
Q
P
CK
Data Latch
Q
I/O pin(1)
N
I/O pin(1)
Q
D
N
D
Q
VSS
Schmitt
Trigger
Input
WR TRISA
CK
WR TRISA
RD TRISA
Q
VSS
CK
Q
Analog
Input Mode
TRIS Latch
Buffer
TRIS Latch
TTL
Input
Buffer
RD TRISA
TTL
Input
Buffer
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
TMR0 Clock Input
SS Input (RA5 only)
To A/D Converter and LVD Modules
Note 1: I/O pins have diode protection to VDD and VSS.
Note 1: I/O pin has diode protection to VSS only.
FIGURE 9-3:
OSC2/CLKO/RA6 PIN BLOCK DIAGRAM
(FOSC = 101, 111)
From OSC1
Oscillator
Circuit
CLKO (FOSC/4)
1
0
Data Latch
Data Bus
Q
D
VDD
P
WR PORTA
CK
Q
OSC2/CLKO
RA6 pin(2)
TRIS Latch
Q
D
N
WR TRISA
CK
Q
(FOSC = 100,
101, 110, 111)
VSS
Schmitt
Trigger
RD TRISA
Input Buffer
Q
D
EN
RD PORTA
(FOSC = 110, 100)
Note 1: CLKO is 1/4 of FOSC.
2: I/O pin has diode protection to VDD and VSS.
DS41159E-page 94
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 9-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0/CVREF
bit 0
TTL
Input/output, analog input or analog comparator voltage reference
output.
RA1/AN1
bit 1
bit 2
bit 3
bit 4
bit 5
TTL
TTL
TTL
Input/output or analog input.
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Input/output, analog input or VREF-.
Input/output, analog input or VREF+.
ST/OD Input/output, external clock input for Timer0, output is open-drain type.
RA5/AN4/SS/LVDIN
TTL
Input/output, analog input, slave select input for synchronous serial port
or Low-Voltage Detect input.
OSC2/CLKO/RA6
bit 6
TTL
Oscillator clock output or input/output.
Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open-Drain
TABLE 9-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
Resets
Value on
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
LATA
—
—
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
-00x 0000 -uuu uuuu
-xxx xxxx -uuu uuuu
-111 1111 -111 1111
Latch A Data Output Register
PORTA Data Direction Register
TRISA
ADCON1 ADFM ADCS2
—
—
PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 uu-- uuuu
Legend: x= unknown, u= unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
© 2006 Microchip Technology Inc.
DS41159E-page 95
PIC18FXX8
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
9.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Read-modify-write operations on the LATB register,
read and write the latched output value for PORTB.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
EXAMPLE 9-2:
CLRF
INITIALIZING PORTB
PORTB
; Initialize PORTB by
; clearing output
; data latches
Note 1: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purpose I/O pin and should not
be held low during normal operation to
protect against inadvertent ICSP mode
entry.
CLRF
LATB
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB3:RB0 as inputs
; RB5:RB4 as outputs
; RB7:RB6 as inputs
MOVLW
MOVWF
0CFh
TRISB
2: When using Low-Voltage ICSP Program-
ming (LVP), the pull-up on RB5 becomes
disabled. If TRISB bit 5 is cleared,
thereby setting RB5 as an output, LATB
bit 5 must also be cleared for proper
operation.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2 register).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with Flag bit RBIF (INTCON register).
DS41159E-page 96
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 9-4:
RB7:RB4 PINS BLOCK
DIAGRAM
FIGURE 9-5:
RB1:RB0 PINS BLOCK
DIAGRAM
VDD
VDD
RBPU(2)
RBPU(2)
Data Bus
Weak
P
Weak
Pull-up
P
Pull-up
Data Latch
Data Latch
Data Bus
WR Port
D
Q
D
Q
I/O pin(1)
I/O pin(1)
WR LATB
or
WR PORTB
CK
CK
TRIS Latch
D
Q
TRIS Latch
TTL
Input
Buffer
D
Q
WR TRISB
TTL
Input
Buffer
CK
WR TRIS
RD TRIS
ST
Buffer
CK
RD TRISB
RD LATB
Latch
Q
Q
D
Q
D
RD PORTB
Set RBIF
EN
Q1
Q3
EN
RD Port
D
From other
RB7:RB4 pins
RBx/INTx
EN
Schmitt Trigger
Buffer
RBx/INTx
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
© 2006 Microchip Technology Inc.
DS41159E-page 97
PIC18FXX8
FIGURE 9-6:
RB2/CANTX/INT2 PIN BLOCK DIAGRAM
OPMODE2:OPMODE0 = 000
ENDRHI
CANTX
0
1
RD LATB
Data Bus
VDD
P
Data Latch
D
Q
WR PORTB or
WR LATB
CK
Q
TRIS Latch
RB2/CANTX/
INT2 pin
(1)
Q
D
N
WR TRISB
RD TRISB
CK
Q
VSS
Schmitt
Trigger
Q
D
EN
RD PORTB
Note 1: I/O pin has diode protection to VDD and VSS.
FIGURE 9-7:
RB3/CANRX PIN BLOCK DIAGRAM
CANCON<7:5>
VDD
(2)
RBPU
Weak
P
Pull-up
Data Latch
Data Bus
D
Q
(1)
I/O pin
WR LATB or PORTB
WR TRISB
CK
TRIS Latch
D
Q
CK
TTL
Input
Buffer
RD TRISB
RD LATB
Q
D
EN
RD PORTB
RB3 or CANRX
Schmitt Trigger
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
.
DS41159E-page 98
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 9-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
Function
RB0/INT0
bit 0
TTL/ST(1) Input/output pin or external interrupt 0 input.
Internal software programmable weak pull-up.
RB1/INT1
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TTL/ST(1) Input/output pin or external interrupt 1 input.
Internal software programmable weak pull-up.
TTL/ST(1) Input/output pin, CAN bus transmit pin or external interrupt 2 input.
Internal software programmable weak pull-up.
RB2/CANTX/
INT2
RB3/CANRX
TTL
TTL
TTL
Input/output pin or CAN bus receive pin.
Internal software programmable weak pull-up.
RB4
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/PGM
RB6/PGC
RB7/PGD
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Low-voltage serial programming enable.
TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock.
TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 9-4:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
all other
Resets
Value on
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 000x 0000 000u
111- -1-1 111- -1-1
LATB
LATB Data Output Register
TRISB
PORTB Data Direction Register
GIE/GIEH PEIE/GIEL TMR0IE
INTCON
INTCON2
INTCON3
Legend:
INT0IE
—
RBIE
—
TMR0IF INT0IF
RBIF
RBIP
RBPU
INTEDG0 INTEDG1
INT1IP
TMR0IP
—
—
INT2IP
—
INT2IE
INT1IE
INT2IF INT1IF 11-0 0-00 11-1 0-00
x= unknown, u= unchanged. Shaded cells are not used by PORTB.
© 2006 Microchip Technology Inc.
DS41159E-page 99
PIC18FXX8
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
9.3
PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The pin override value is not loaded into the TRIS
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
EXAMPLE 9-3:
INITIALIZING PORTC
; Initialize PORTC by
; clearing output
; data latches
CLRF
PORTC
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
CLRF
LATC
; Alternate method
; to clear output
; data latches
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
MOVLW
MOVWF
0CFh
; Value used to
; initialize data
; direction
; Set RC3:RC0 as inputs
; RC5:RC4 as outputs
; RC7:RC6 as inputs
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
TRISC
FIGURE 9-8:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
RD LATC
Data Bus
D
Q
Q
WR LATC
or
WR PORTC
(1)
CK
I/O pin
TRIS OVERRIDE
Data Latch
N
D
Q
Q
Pin Override
Peripheral
VSS
TRIS
Override
WR TRISC
RC0
Yes
Timer1 Oscillator
for Timer1/Timer3
CK
TRIS Latch
RC1
Yes
Timer1 Oscillator
for Timer1/Timer3
RD TRISC
RC2
RC3
No
—
Schmitt
Trigger
Peripheral Enable
2
Yes
SPI™/I C™
Master Clock
Q
D
2
RC4
RC5
RC6
Yes
Yes
Yes
I C Data Out
EN
SPI Data Out
RD PORTC
USART Async
Peripheral Data In
Xmit, Sync Clock
RC7
Yes
USART Sync Data
Out
Note 1: I/O pins have diode protection to VDD and VSS.
DS41159E-page 100
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 9-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI
bit 0
ST
Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock
input.
RC1/T1OSI
RC2/CCP1
bit 1
bit 2
ST
ST
Input/output port pin or Timer1 oscillator input.
Input/output port pin or Capture 1 input/Compare 1 output/
PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
bit 3
bit 4
bit 5
bit 6
ST
ST
ST
ST
Input/output port pin or synchronous serial clock for SPI™/I2C™.
Input/output port pin or SPI data in (SPI mode) or data I/O (I2C mode).
Input/output port pin or synchronous serial port data output.
RC6/TX/CK
Input/output port pin, addressable USART asynchronous transmit or
addressable USART synchronous clock.
RC7/RX/DT
bit 7
ST
Input/output port pin, addressable USART asynchronous receive or
addressable USART synchronous data.
Legend: ST = Schmitt Trigger input
TABLE 9-6:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
Value on
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
PORTC
LATC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
LATC Data Output Register
PORTC Data Direction Register
TRISC
Legend: x= unknown, u= unchanged
© 2006 Microchip Technology Inc.
DS41159E-page 101
PIC18FXX8
PORTD can be configured as an 8-bit wide, micro-
processor port (Parallel Slave Port or PSP) by setting
the control bit PSPMODE (TRISE<4>). In this mode,
the input buffers are TTL. See Section 10.0 “Parallel
Slave Port” for additional information.
9.4
PORTD, TRISD and LATD
Registers
Note:
This port is only available on the
PIC18F448 and PIC18F458.
PORTD is also multiplexed with the analog comparator
module and the ECCP module.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register for the port is TRISD.
Setting a TRISD bit (= 1) will make the corresponding
PORTD pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISD
bit (= 0) will make the corresponding PORTD pin an
output (i.e., put the contents of the output latch on the
selected pin).
EXAMPLE 9-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
CLRF
LATD
; Alternate method
; to clear output
; data latches
Read-modify-write operations on the LATD register
read and write the latched output value for PORTD.
MOVLW
MOVWF
MOVLW
07h
CMCON
0CFh
; comparator off
PORTD uses Schmitt Trigger input buffers. Each pin is
individually configurable as an input or output.
; Value used to
; initialize data
; direction
MOVWF
TRISD
; Set RD3:RD0 as inputs
; RD5:RD4 as outputs
; RD7:RD6 as inputs
FIGURE 9-9:
PORTD BLOCK DIAGRAM IN I/O PORT MODE
PORT/PSP Select
PSP Data Out
RD LATD
VDD
P
Data Bus
D
Q
Q
WR LATD
or
PORTD
RD0/PSP0/
CK
(1)
C1IN+ pin
N
Data Latch
D
Q
Q
Vss
WR TRISD
CK
TRIS Latch
RD TRISD
PSP Read
Schmitt
Trigger
Q
D
EN
RD PORTD
PSP Write
C1IN+
Note 1: I/O pins have diode protection to VDD and VSS.
DS41159E-page 102
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 9-7:
Name
PORTD FUNCTIONS
Bit# Buffer Type
Function
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
RD2/PSP2/C2IN+
RD3/PSP3/C2IN-
bit 0
bit 1
bit 2
bit 3
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 0 or C1IN+ comparator
input.
Input/output port pin, Parallel Slave Port bit 1 or C1IN- comparator
input.
Input/output port pin, Parallel Slave Port bit 2 or C2IN+ comparator
input.
Input/output port pin, Parallel Slave Port bit 3 or C2IN- comparator
input.
RD4/PSP4/ECCP1/P1A bit 4
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 4 or ECCP1/P1A pin.
Input/output port pin, Parallel Slave Port bit 5 or P1B pin.
Input/output port pin, Parallel Slave Port bit 6 or P1C pin.
Input/output port pin, Parallel Slave Port bit 7 or P1D pin.
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
bit 5
bit 6
bit 7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 9-8:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
all other
Resets
Value on
POR, BOR
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
RD7 RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
LATD
LATD Data Output Register
PORTD Data Direction Register
IBF OBF IBOV PSPMODE
TRISD
TRISE
—
TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
© 2006 Microchip Technology Inc.
DS41159E-page 103
PIC18FXX8
When the Parallel Slave Port is active, the PORTE pins
function as its control inputs. For additional details,
refer to Section 10.0 “Parallel Slave Port”.
9.5
PORTE, TRISE and LATE
Registers
Note:
This port is only available on the
PIC18F448 and PIC18F458.
PORTE pins are also multiplexed with inputs for the A/D
converter and outputs for the analog comparators. When
selected as an analog input, these pins will read as ‘0’s.
Direction bits TRISE<2:0> control the direction of the RE
pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured as
inputs when using them as analog inputs.
PORTE is a 3-bit wide, bidirectional port. PORTE has
three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and
RE2/AN7/CS/C2OUT) which are individually config-
urable as inputs or outputs. These pins have Schmitt
Trigger input buffers.
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
EXAMPLE 9-5:
INITIALIZING PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE2 as an output
; (RE4=0 - PSPMODE Off)
CLRF
PORTE
LATE
03h
The corresponding Data Direction register for the port
is TRISE. Setting a TRISE bit (= 1) will make the
corresponding PORTE pin an input (i.e., put the corre-
sponding output driver in a high-impedance mode).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., put the contents of the
output latch on the selected pin).
CLRF
MOVLW
MOVWF
The TRISE register also controls the operation of the
Parallel Slave Port through the control bits in the upper
half of the register. These are shown in Register 9-1.
TRISE
FIGURE 9-10:
PORTE BLOCK DIAGRAM
Peripheral Out Select
Peripheral Data Out
VDD
0
1
P
RD LATE
Data Bus
D
Q
Q
(1)
I/O pin
WR LATE
or
WR PORTE
CK
Data Latch
N
D
Q
Q
VSS
TRIS
Override
WR TRISE
CK
TRIS Latch
RD TRISE
Schmitt
Trigger
TRIS OVERRIDE
Peripheral Enable
Pin Override Peripheral
Q
D
RE0
RE1
RE2
Yes
Yes
Yes
PSP
PSP
PSP
EN
RD PORTE
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
DS41159E-page 104
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 9-1:
TRISE REGISTER
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
TRISE2
TRISE1
TRISE0
bit 7
bit 0
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read
(must be cleared in software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General Purpose I/O mode
bit 3
bit 2
Unimplemented: Read as ‘0’
TRISE2: RE2 Direction Control bit
1= Input
0= Output
bit 1
bit 0
TRISE1: RE1 Direction Control bit
1= Input
0= Output
TRISE0: RE0 Direction Control bit
1= Input
0= Output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 105
PIC18FXX8
TABLE 9-9:
Name
RE0/AN5/RD
PORTE FUNCTIONS
Bit# Buffer Type
Function
bit 0
ST/TTL(1) Input/output port pin, analog input or read control input in Parallel
Slave Port mode.
RE1/AN6/WR/C1OUT bit 1
RE2/AN7/CS/C2OUT bit 2
ST/TTL(1) Input/output port pin, analog input, write control input in Parallel Slave
Port mode or Comparator 1 output.
ST/TTL(1) Input/output port pin, analog input, chip select control input in Parallel
Slave Port mode or Comparator 2 output.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
TRISE
IBF
—
OBF
—
IBOV PSPMODE
—
—
TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
PORTE
—
—
—
—
—
—
Read PORTE pin/
---- -xxx ---- -uuu
Write PORTE Data Latch
LATE
—
—
—
Read PORTE Data Latch/
Write PORTE Data Latch
---- -xxx ---- -uuu
ADCON1 ADFM ADCS2
PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
DS41159E-page 106
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 10-1:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
10.0 PARALLEL SLAVE PORT
Note:
The Parallel Slave Port is only available on
PIC18F4X8 devices.
One bit of PORTD
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is
controlled by the 4 upper bits of the TRISE register
(Register 9-1). Setting control bit PSPMODE
(TRISE<4>) enables PSP operation. In Slave mode,
the port is asynchronously readable and writable by the
external world.
Data Bus
D
Q
RDx pin
WR LATD
or
WR PORTD
CK
Data Latch
TTL
Q
D
RD PORTD
RD LATD
EN
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit PSPMODE enables the PORTE I/O pins
to become control inputs for the microprocessor port.
When set, port pin RE0 is the RD input, RE1 is the WR
input and RE2 is the CS (chip select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set).
Set Interrupt Flag
PSPIF (PIR1<7>)
PORTE pins
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The timing for the control signals in Write and Read
modes is shown in Figure 10-2 and Figure 10-3,
respectively.
Read
RD
CS
WR
TTL
Chip Select
TTL
Write
TTL
Note:
I/O pins have diode protection to VDD and VSS.
FIGURE 10-2:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
© 2006 Microchip Technology Inc.
DS41159E-page 107
PIC18FXX8
FIGURE 10-3:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 10-1: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD Port Data Latch when written; Port pins when read
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---- -xxx ---- -000
---- -xxx ---- -uuu
LATD
LATD Data Output bits
TRISD
PORTE
LATE
PORTD Data Direction bits
—
—
—
—
—
—
RE2
RE1
RE0
LATE Data Output bits
IBF OBF
TRISE
IBOV PSPMODE
PORTE Data Direction bits 0000 -111 0000 -111
RBIF 0000 000x 0000 000u
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE TMR0IF INT0IF
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
TXIE
TXIP
IPR1
Legend:
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
DS41159E-page 108
© 2006 Microchip Technology Inc.
PIC18FXX8
Register 11-1 shows the Timer0 Control register
(T0CON).
11.0 TIMER0 MODULE
The Timer0 module has the following features:
Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Software selectable as an 8-bit or
16-bit timer/counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
The T0CON register is a readable and writable register
that controls all the aspects of Timer0, including the
prescale selection.
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
Note:
Timer0 is enabled on POR.
• Edge select for external clock
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
T08BIT
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111=1:256 Prescale value
110=1:128 Prescale value
101=1:64 Prescale value
100=1:32 Prescale value
011=1:16 Prescale value
010=1:8 Prescale value
001=1:4 Prescale value
000=1:2 Prescale value
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 109
PIC18FXX8
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
8
1
0
RA4/T0CKI
pin(2)
1
T0SE
Sync with
Internal
Clocks
FOSC/4
TMR0L
Programmable
Prescaler
0
(2 TCY Delay)
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS(1)
Note 1: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
2: I/O pins have diode protection to VDD and VSS.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
T0CKI pin(2)
1
1
Sync with
Internal
Clocks
T0SE
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
0
TMR0L
FOSC/4
Programmable
Prescaler
0
8
(2 TCY Delay)
3
Read TMR0L
Write TMR0L
T0PS2, T0PS1, T0PS0
T0CS(1)
PSA
8
8
TMR0H
8
Data Bus<7:0>
Note 1: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
2: I/O pins have diode protection to VDD and VSS.
DS41159E-page 110
© 2006 Microchip Technology Inc.
PIC18FXX8
11.2.1
SWITCHING PRESCALER
ASSIGNMENT
11.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0L
register is written, the increment is inhibited for the
following two instruction cycles. The user can work
around this by writing an adjusted value to the TMR0L
register.
11.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module Interrupt Service
Routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from Sleep
since the timer is shut-off during Sleep.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.4 16-Bit Mode Timer Reads
and Writes
Timer0 can be set in 16-bit mode by clearing the
T08BIT in T0CON. Registers TMR0H and TMR0L are
used to access the 16-bit timer value.
11.2 Prescaler
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-1). The high byte
of the Timer0 timer/counter is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This
provides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of the buffered value of
TMR0H when a write occurs to TMR0L. This allows all
16 bits of Timer0 to be updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x.... etc.) will clear the prescaler
count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
TMR0H
Timer0 Module Low Byte Register
Timer0 Module High Byte Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 000x 0000 000u
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
PSA
TMR0IF INT0IF
T0PS2 T0PS1
RBIF
T0CON
TRISA
TMR0ON
—
T08BIT
T0CS
T0SE
T0PS0 1111 1111 1111 1111
(1)
PORTA Data Direction Register
-111 1111 -111 1111
Legend:
x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Note 1: Bit 6 of PORTA, LATA and TRISA is enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, it is
disabled and reads as ‘0’.
© 2006 Microchip Technology Inc.
DS41159E-page 111
PIC18FXX8
NOTES:
DS41159E-page 112
© 2006 Microchip Technology Inc.
PIC18FXX8
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN). Timer1 can be enabled/
disabled by setting/clearing control bit, TMR1ON
(T1CON register).
12.0 TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
Figure 12-1 is a simplified block diagram of the Timer1
module.
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
Note:
Timer1 is disabled on POR.
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
bit 6
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
Unimplemented: Read as ‘0’
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11=1:8 Prescale value
10=1:4 Prescale value
01=1:2 Prescale value
00=1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 113
PIC18FXX8
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1
increments on every rising edge of the external clock
input or the Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
Synchronized
Clock Input
TMR1
CLR
0
TMR1L
TMR1H
T1OSC
1
TMR1ON
On/Off
T1SYNC
1
T1CKI/T1OSO
T1OSI
Synchronize
det
T1OSCEN
Enable
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
(1)
Oscillator
0
2
Sleep Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
Special Event Trigger
Synchronized
Clock Input
0
TMR1IF
Overflow
Interrupt
TMR1
8
Timer 1
TMR1L
High Byte
Flag bit
1
TMR1ON
On/Off
T1SYNC
T1OSC
T1CKI/T1OSO
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
T1OSI
Oscillator
2
Sleep Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
DS41159E-page 114
© 2006 Microchip Technology Inc.
PIC18FXX8
12.2 Timer1 Oscillator
12.4 Resetting Timer1 Using a CCP
Trigger Output
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON register). The
oscillator is a low-power oscillator rated up to 50 kHz. It
will continue to run during Sleep. It is primarily intended
for a 32 kHz crystal. Table 12-1 shows the capacitor
selection for the Timer1 oscillator.
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR registers).
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
TABLE 12-1: CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR
Osc Type
Freq
C1
C2
In the event that a write to Timer1 coincides with a special
event trigger from CCP1, the write will take precedence.
LP
32 kHz
TBD(1)
TBD(1)
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A
In this mode of operation, the CCPR1H:CCPR1L register
pair effectively becomes the period register for Timer1.
20 PPM
12.5 Timer1 16-Bit Read/Write Mode
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit (T1CON
register) is set, the address for TMR1H is mapped to a
buffer register for the high byte of Timer1. A read from
TMR1L will load the contents of the high byte of Timer1
into the Timer1 High Byte Buffer register. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is valid
due to a rollover between reads.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
4: Capacitor values are for design guidance
only.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
12.3 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The TMR1
Interrupt, if enabled, is generated on overflow which is
latched in interrupt flag bit, TMR1IF (PIR registers). This
interrupt can be enabled/disabled by setting/clearing
TMR1 Interrupt Enable bit, TMR1IE (PIE registers).
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
© 2006 Microchip Technology Inc.
DS41159E-page 115
PIC18FXX8
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PIE1
IPR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
(1)
(1)
TXIE
TXIP
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Legend:
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 116
© 2006 Microchip Technology Inc.
PIC18FXX8
13.1 Timer2 Operation
13.0 TIMER2 MODULE
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON register). The match
output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, PIR
registers).
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to
generate clock shift
The prescaler and postscaler counters are cleared
when any of the following occurs:
Register 13-1 shows the Timer2 Control register.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON register) to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. The prescaler and postscaler selection of
Timer2 are controlled by this register.
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
Note:
Timer2 is disabled on POR.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000=1:1 Postscale
0001=1:2 Postscale
•
•
•
1111=1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 117
PIC18FXX8
13.2 Timer2 Interrupt
13.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The output of TMR2 (before the postscaler) is a clock
input to the Synchronous Serial Port module which
optionally uses it to generate the shift clock.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
bit TMR2IF
(1)
Output
Prescaler
Reset
EQ
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
1:1 to 1:16
2
Comparator
PR2
T2CKPS1:T2CKPS0
4
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
0000 0000 0000 0000
(1)
(1)
PIE1
TXIE
TXIP
IPR1
TMR2
T2CON
PR2
Timer2 Module Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Legend:
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 118
© 2006 Microchip Technology Inc.
PIC18FXX8
Figure 14-1 is a simplified block diagram of the Timer3
module.
14.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP1 and ECCP1 clock source.
• 16-bit timer/counter
(two 8-bit registers: TMR3H and TMR3L)
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN) which can be a clock source for
Timer3.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP1/ECCP1 module trigger
Note:
Timer3 is disabled on POR.
REGISTER 14-1: T3CON:TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6,3 T3ECCP1:T3CCP1: Timer3 and Timer1 to CCP1/ECCP1 Enable bits
1x= Timer3 is the clock source for compare/capture CCP1 and ECCP1 modules
01= Timer3 is the clock source for compare/capture of ECCP1,
Timer1 is the clock source for compare/capture of CCP1
00= Timer1 is the clock source for compare/capture CCP1 and ECCP1 modules
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
TMR3CS: Timer3 Clock Source Select bit
bit 1
bit 0
1= External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 119
PIC18FXX8
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
14.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC<1:0> value is ignored.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON register).
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
TMR3IF
T3CCPx
Synchronized
Clock Input
Overflow
0
Interrupt
Flag bit
CLR
TMR3L
TMR3H
T1OSC
1
TMR3ON
On/Off
T3SYNC
T1OSO/
T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
0
(1)
T1OSI
Oscillator
Clock
2
Sleep Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Trigger
T3CCPx
Synchronized
Clock Input
8
TMR3
TMR3IF Overflow
Interrupt Flag
bit
0
CLR
TMR3H
TMR3L
1
To Timer1 Clock Input
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
Oscillator
T1OSI
2
Sleep Input
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS41159E-page 120
© 2006 Microchip Technology Inc.
PIC18FXX8
14.2 Timer1 Oscillator
14.4 Resetting Timer3 Using a CCP
Trigger Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN bit (T1CON register). The oscillator is a
low-power oscillator rated up to 50 kHz. Refer to
Section 12.0 “Timer1 Module” for Timer1 oscillator
details.
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Note:
The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR registers).
14.3 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to 0FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR3IF (PIR regis-
ters). This interrupt can be enabled/disabled by setting/
clearing TMR3 Interrupt Enable bit, TMR3IE (PIE
registers).
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature. If
Timer3 is running in Asynchronous Counter mode, this
Reset operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L register pair becomes
the period register for Timer3. Refer to Section 15.0
“Capture/Compare/PWM (CCP) Modules” for CCP
details.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/ GIEH PEIE/GIEL TMR0IE
INT0IE
EEIF
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF
LVDIF
LVDIE
LVDIP
INT0IF
RBIF
0000 000x 0000 000u
PIR2
—
—
—
CMIF
CMIE
CMIP
—
—
—
TMR3IF ECCP1IF -0-0 0000 -0-0 0000
TMR3IE ECCP1IE -0-0 0000 -0-0 0000
TMR3IP ECCP1IP -1-1 1111 -1-1 1111
xxxx xxxx uuuu uuuu
PIE2
EEIE
EEIP
IPR2
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
T1CON
T3CON
Legend:
RD16
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
© 2006 Microchip Technology Inc.
DS41159E-page 121
PIC18FXX8
NOTES:
DS41159E-page 122
© 2006 Microchip Technology Inc.
PIC18FXX8
module has a Capture special event trigger that can be
used as a message received time-stamp for the CAN
module (refer to Section 19.0 “CAN Module” for CAN
operation) which the ECCP module does not. The
ECCP module, on the other hand, has Enhanced PWM
functionality and auto-shutdown capability. Aside from
these, the operation of the module described in this
section is the same as the ECCP.
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
The CCP (Capture/Compare/PWM) module contains a
16-bit register that can operate as a 16-bit Capture
register, as a 16-bit Compare register or as a PWM
Duty Cycle register.
The operation of the CCP module is identical to that
of the ECCP module (discussed in detail in
Section 16.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”) with two exceptions. The CCP
The control register for the CCP module is shown in
Register 15-1. Table 15-2 (following page) details the
interactions of the CCP and ECCP modules.
REGISTER 15-1: CCP1CON: CCP1 CONTROL REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Capture mode, CAN message received (CCP1 only)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, initialize CCP pin low, on compare match force CCP pin high
(CCPIF bit is set)
1001= Compare mode, initialize CCP pin high, on compare match force CCP pin low
(CCPIF bit is set)
1010= Compare mode, CCP pin is unaffected
(CCPIF bit is set)
1011= Compare mode, trigger special event (CCP1IF bit is set; CCP resets TMR1 or TMR3
and starts an A/D conversion if the A/D module is enabled)
11xx= PWM mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 123
PIC18FXX8
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the
interrupt request flag bit, CCP1IF (PIR registers), is set.
It must be cleared in software. If another capture
occurs before the value in register CCPR1 is read, the
old captured value will be lost.
15.1 CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Table 15-1 shows the timer resources of the CCP
module modes.
15.2.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
TABLE 15-1: CCP1 MODE – TIMER
RESOURCE
Note:
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
CCP1 Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
15.2.2
TIMER1/TIMER3 MODE SELECTION
The timers used with the capture feature (either Timer1
and/or Timer3) must be running in Timer mode or Syn-
chronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer
used with each CCP module is selected in the T3CON
register.
15.2 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit value of the TMR1 or TMR3 register when an event
occurs on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
TABLE 15-2: INTERACTION OF CCP1 AND ECCP1 MODULES
CCP1
Mode
ECCP1
Mode
Interaction
Capture
Capture
Capture
TMR1 or TMR3 time base. Time base can be different for each CCP.
Compare
The compare could be configured for the special event trigger which clears either TMR1
or TMR3, depending upon which time base is used.
Compare
Compare
The compare(s) could be configured for the special event trigger which clears TMR1 or
TMR3, depending upon which time base is used.
PWM
PWM
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
Capture
Compare
None.
None.
DS41159E-page 124
© 2006 Microchip Technology Inc.
PIC18FXX8
15.2.3
SOFTWARE INTERRUPT
15.2.5
CAN MESSAGE TIME-STAMP
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE registers) clear to avoid false interrupts
and should clear the flag bit CCP1IF, following any
such change in operating mode.
The CAN capture event occurs when a message is
received in either of the receive buffers. The CAN
module provides a rising edge to the CCP1 module to
cause a capture event. This feature is provided to
time-stamp the received CAN messages.
This feature is enabled by setting the CANCAP bit of
the CAN I/O control register (CIOCON<4>). The
message receive signal from the CAN module then
takes the place of the events on RC2/CCP1.
15.2.4
CCP1 PRESCALER
There are four prescaler settings specified by bits
CCP1M3:CCP1M0. Whenever the CCP1 module is
turned off, or the CCP1 module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the recom-
mended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
CLRF
MOVLW
CCP1CON, F
NEW_CAPT_PS
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
MOVWF
CCP1CON
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF
(PIR1<2>)
TMR3H
TMR3L
CCPR1L
TMR1L
T3CCP1
T3ECCP1
TMR3
Enable
Prescaler
÷ 1, 4, 16
CCP1 pin
CCPR1H
TMR1
and
Enable
Edge Detect
T3ECCP1
T3CCP1
TMR1H
CCP1CON<3:0>
Qs
Note: I/O pins have diode protection to VDD and VSS.
© 2006 Microchip Technology Inc.
DS41159E-page 125
PIC18FXX8
15.3.2
TIMER1/TIMER3 MODE SELECTION
15.3 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 and ECCPR1
register value is constantly compared against either the
TMR1 register pair value or the TMR3 register pair
value. When a match occurs, the CCP1 pin can have
one of the following actions:
15.3.3
SOFTWARE INTERRUPT MODE
• Driven high
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
• Driven low
• Toggle output (high-to-low or low-to-high)
• Remains unchanged
15.3.4
SPECIAL EVENT TRIGGER
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0. At the same time, interrupt flag
bit CCP1IF is set.
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets either
the TMR1 or TMR3 register pair. Additionally, the
ECCP1 special event trigger will start an A/D
conversion if the A/D module is enabled.
15.3.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRISC bit.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the data latch.
Note:
The special event trigger from the ECCP1
module will not set the Timer1 or Timer3
interrupt flag bits.
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)
Set bit GO/DONE which starts an A/D conversion (ECCP1 only)
TMR3H TMR3L
TMR1H TMR1L
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
T3CCP1
T3ECCP1
0
1
Q
S
R
Output
Logic
Comparator
CCPR1H
Match
CCP1
Output Enable
CCPR1L
CCP1CON<3:0>
Mode Select
Note 1: I/O pins have diode protection to VDD and VSS.
DS41159E-page 126
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF
CCP1IE
CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
(1)
PIE1
IPR1
TRISD
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
PIR2
PORTD Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
—
—
—
DC1B1
—
DC1B0
EEIF
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CMIF
CMIE
CMIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF ECCP1IF -0-0 0000 -0-0 0000
TMR3IE ECCP1IE -0-0 0000 -0-0 0000
TMR3IP ECCP1IP -1-1 1111 -1-1 1111
PIE2
—
EEIE
EEIP
IPR2
—
TMR3L
TMR3H
T3CON
Legend:
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 127
PIC18FXX8
15.4.1
PWM PERIOD
15.4 PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula.
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
EQUATION 15-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1/[PWM period].
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.3
“Setup for PWM Operation”.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L (Master)
CCPR1H (Slave)
Comparator
15.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
Q
R
S
RC2/CCP1
(Note 1)
TMR2
TRISC<2>
Comparator
PR2
Clear Timer,
set CCP1 pin and
latch D.C.
EQUATION 15-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock,
or 2 bits of the prescaler, to create 10-bit time base.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-4:
PWM OUTPUT
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
Period
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS41159E-page 128
© 2006 Microchip Technology Inc.
PIC18FXX8
The maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
15.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
EQUATION 15-3:
1. Set the PWM period by writing to the PR2
register.
FOSC
⎛
⎝
⎞
⎠
---------------
log
FPWM
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
PWM Resolution (max)
= ----------------------------- b i t s
log(2)
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
5. Configure the CCP1 module for PWM operation.
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 312.5 kHz 416.6 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
0FFh
10
0FFh
10
17h
5.5
Maximum Resolution (bits)
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
TMR2IF
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
(1)
PIE1
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
TRISD
TMR2
PORTD Data Direction Register
Timer2 Module Register
0000 0000 0000 0000
PR2
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
CCPR1L
CCPR1H
CCP1CON
Legend:
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 129
PIC18FXX8
NOTES:
DS41159E-page 130
© 2006 Microchip Technology Inc.
PIC18FXX8
The operation of the ECCP module differs from the
CCP (discussed in detail in Section 15.0 “Capture/
Compare/PWM (CCP) Modules”) with the addition of
an Enhanced PWM module which allows for up to 4
output channels and user selectable polarity. These
features are discussed in detail in Section 16.5
“Enhanced PWM Mode”. The module can also be
programmed for automatic shutdown in response to
various analog or digital events.
16.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
Note:
The ECCP (Enhanced Capture/Compare/
PWM) module is only available on
PIC18F448 and PIC18F458 devices.
This module contains a 16-bit register which can oper-
ate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
The control register for ECCP1 is shown in
Register 16-1.
REGISTER 16-1: ECCP1CON: ECCP1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0
EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
bit 7
bit 7-6
EPWM1M<1:0>: PWM Output Configuration bits
If ECCP1M<3:2> = 00, 01, 10:
xx= P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If ECCP1M<3:2> = 11:
00= Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01= Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output; P1A, P1B modulated with deadband control; P1C, P1D assigned as
port pins
11= Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
bit 3-0
EDC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in ECCPR1L.
ECCP1M<3:0>: ECCP1 Mode Select bits
0000= Capture/Compare/PWM off (resets ECCP module)
0001= Unused (reserved)
0010= Compare mode, toggle output on match (ECCP1IF bit is set)
0011= Unused (reserved)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (ECCP1IF bit is set)
1001= Compare mode, clear output on match (ECCP1IF bit is set)
1010= Compare mode, ECCP1 pin is unaffected (ECCP1IF bit is set)
1011= Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1or TMR3
and starts an A/D conversion if the A/D module is enabled)
1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 131
PIC18FXX8
In PWM mode, the ECCP module can have up to four
available outputs, depending on which operating mode
is selected. These outputs are multiplexed with PORTD
and the Parallel Slave Port. Both the operating mode
and the output pin assignments are configured by setting
PWM output configuration bits, EPWM1M1:EPWM1M0
(ECCP1CON<7:6>). The specific pin assignments for
the various output modes are shown in Table 16-3.
16.1 ECCP1 Module
Enhanced Capture/Compare/PWM Register 1 (ECCPR1)
is comprised of two 8-bit registers: ECCPR1L (low
byte) and ECCPR1H (high byte). The ECCP1CON
register controls the operation of ECCP1; the additional
registers, ECCPAS and ECCP1DEL, control Enhanced
PWM specific features. All registers are readable and
writable.
Table 16-1 shows the timer resources for the ECCP
module modes. Table 16-2 describes the interactions
of the ECCP module with the standard CCP module.
TABLE 16-1: ECCP1 MODE – TIMER
RESOURCE
ECCP1 Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TABLE 16-2: INTERACTION OF CCP1 AND ECCP1 MODULES
ECCP1 Mode CCP1 Mode Interaction
TMR1 or TMR3 time base. Time base can be different for each CCP.
Capture
Capture
Capture
Compare
The compare could be configured for the special event trigger which clears either
TMR1 or TMR3 depending upon which time base is used.
Compare
Compare
The compare(s) could be configured for the special event trigger which clears TMR1
or TMR3 depending upon which time base is used.
PWM
PWM
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
Capture
Compare
None
None
TABLE 16-3: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
ECCP1CON
ECCP Mode(1)
RD4
RD5
RD6
RD7
Configuration
Conventional CCP Compatible
00xx11xx
ECCP1
RD<5>,
PSP<5>
RD<6>,
PSP<6>
RD<7>,
PSP<7>
Dual Output PWM(2)
10xx11xx
P1A
P1B
RD<6>,
PSP<6>
RD<7>,
PSP<7>
Quad Output PWM(2)
x1xx11xx
P1A
P1B
P1C
P1D
Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1: In all cases, the appropriate TRISD bits must be cleared to make the corresponding pin an output.
2: In these modes, the PSP I/O control for PORTD is overridden by P1B, P1C and P1D.
DS41159E-page 132
© 2006 Microchip Technology Inc.
PIC18FXX8
16.2 Capture Mode
16.3 Compare Mode
The Capture mode of the ECCP module is virtually
identical in operation to that of the standard CCP mod-
ule as discussed in Section 15.1 “CCP1 Module”.
The differences are in the registers and port pins
involved:
The Compare mode of the ECCP module is virtually
identical in operation to that of the standard CCP
module as discussed in Section 15.2 “Capture
Mode”. The differences are in the registers and port
pins as described in Section 16.2 “Capture Mode”.
All other details are exactly the same.
• The 16-bit Capture register is ECCPR1
(ECCPR1H and ECCPR1L);
16.3.1
SPECIAL EVENT TRIGGER
• The capture event is selected by control bits
ECCP1M3:ECCP1M0 (ECCP1CON<3:0>);
Except as noted below, the special event trigger output
of ECCP1 functions identically to that of the standard
CCP module. It may be used to start an A/D conversion
if the A/D module is enabled.
• The interrupt bits are ECCP1IE (PIE2<0>) and
ECCP1IF (PIR2<0>); and
• The capture input pin is RD4 and its corresponding
direction control bit is TRISD<4>.
Note:
The special event trigger from the ECCP1
module will not set the Timer1 or Timer3
interrupt flag bits.
Other operational details, including timer selection,
output pin configuration and software interrupts, are
exactly the same as the standard CCP module.
16.2.1
CAN MESSAGE TIME-STAMP
The special capture event for the reception of CAN mes-
sages (Section 15.2.5 “CAN Message Time-Stamp”)
is not available with the ECCP module.
TABLE 16-4: REGISTERS ASSOCIATED WITH ENHANCED CAPTURE, COMPARE,
TIMER1 AND TIMER3
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
EEIF
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF
LVDIF
LVDIE
LVDIP
INT0IF
RBIF
0000 000x 0000 000u
—
—
—
CMIF
CMIE
CMIP
—
—
—
TMR3IF ECCP1IF -0-0 0000 -0-0 0000
TMR3IE ECCP1IE -0-0 0000 -0-0 0000
TMR3IP ECCP1IP -1-1 1111 -1-1 1111
xxxx xxxx uuuu uuuu
PIE2
EEIE
EEIP
IPR2
TMR1L
TMR1H
T1CON
TMR3L
TMR3H
T3CON
TRISD
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3ECCP1 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
PORTD Data Direction Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
ECCPR1L Capture/Compare/PWM Register1 (LSB)
ECCPR1H Capture/Compare/PWM Register1 (MSB)
ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module and Timer1.
© 2006 Microchip Technology Inc.
DS41159E-page 133
PIC18FXX8
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when the assigned timer resets) in
order to prevent glitches on any of the outputs. The
exception is the PWM Delay register, ECCP1DEL,
which is loaded at either the duty cycle boundary or the
boundary period (whichever comes first). Because of
the buffering, the module waits until the assigned timer
resets instead of starting immediately. This means that
Enhanced PWM waveforms do not exactly match the
standard PWM waveforms, but are instead offset by
one full instruction cycle (4 TOSC).
16.4 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 15.4
“PWM Mode”. The differences in registers and ports
are as described in Section 16.2 “Capture Mode”. In
addition, the two Least Significant bits of the 10-bit
PWM duty cycle value are represented by
ECCP1CON<5:4>.
Note:
When setting up single output PWM
operations, users are free to use either of
the processes described in Section 15.4.3
“Setup for PWM Operation” or
Section 16.5.8 “Setup for PWM Opera-
tion”. The latter is more generic, but will
work for either single or multi-output PWM.
As before, the user must manually configure the
appropriate TRISD bits for output.
16.5.1
PWM OUTPUT CONFIGURATIONS
The EPWM1M<1:0> bits in the ECCP1CON register
allow one of four configurations:
16.5 Enhanced PWM Mode
• Single Output
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is an upwardly compatible version of
the standard CCP module and is modified to provide up
to four outputs, designated P1A through P1D. Users
are also able to select the polarity of the signal (either
active-high or active-low). The module’s output mode
and polarity are configured by setting the
EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0 bits
of the ECCP1CON register (ECCP1CON<7:6> and
ECCP1CON<3:0>, respectively).
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 15.4 “PWM Mode”. The Half-
Bridge and Full-Bridge Output modes are covered in
detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
FIGURE 16-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
ECCP1CON<5:4>
ECCP1M<3:0>
4
EPWM1M1<1:0>
Duty Cycle Registers
2
ECCPR1L
ECCP1/P1A
RD4/PSP4/ECCP1/P1A
TRISD<4>
TRISD<5>
TRISD<6>
TRISD<7>
ECCPR1H (Slave)
Comparator
P1B
RD5/PSP5/P1B
RD6/PSP6/P1C
Output
R
Q
Controller
P1C
(Note 1)
TMR2
S
P1D
RD7/PSP7/P1D
Comparator
PR2
Clear Timer,
set ECCP1 pin and
latch D.C.
ECCP1DEL
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
DS41159E-page 134
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 16-2:
PWM OUTPUT RELATIONSHIPS
0
PR2 + 1
Duty
Cycle
SIGNAL
ECCP1CON
Period
<7:6>
P1A Modulated, Active-High
P1A Modulated, Active-Low
P1A Modulated, Active-High
P1A Modulated, Active-Low
P1B Modulated, Active-High
P1B Modulated, Active-Low
P1A Active, Active-High
P1A Active, Active-Low
00
Delay
10
Delay
P1B Inactive, Active-High
P1B Inactive, Active-Low
P1C Inactive, Active-High
P1C Inactive, Active-Low
P1D Modulated, Active-High
P1D Modulated, Active-Low
P1A Inactive, Active-High
P1A Inactive, Active-Low
P1B Modulated, Active-High
P1B Modulated, Active-Low
P1C Active, Active-High
P1C Active, Active-Low
01
11
P1D Inactive, Active-High
P1D Inactive, Active-Low
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * ECCP1DEL
© 2006 Microchip Technology Inc.
DS41159E-page 135
PIC18FXX8
16.5.2
HALF-BRIDGE MODE
FIGURE 16-3:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The RD4/PSP4/
ECCP1/P1A pin has the PWM output signal, while the
RD5/PSP5/P1B pin has the complementary PWM
output signal (Figure 16-3). This mode can be used for
half-bridge applications, as shown in Figure 16-4, or for
full-bridge applications where four power switches are
being modulated with two PWM signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
td
td
P1B
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in bridge power devices. The value of register
ECCP1DEL dictates the number of clock cycles before
the output is driven active. If the value is greater than
the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.5.4
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as asserted high.
Since the P1A and P1B outputs are multiplexed with
the PORTD<4> and PORTD<5> data latches, the
TRISD<4> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-4:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F448/458
FET
Driver
+
V
-
P1A
+
-
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F448/458
FET
FET
Driver
Driver
P1A
+
-
Load
FET
Driver
FET
Driver
P1B
V-
DS41159E-page 136
© 2006 Microchip Technology Inc.
PIC18FXX8
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTD<4:7> data latches. The TRISD<4:7> bits
must be cleared to make the P1A, P1B, P1C and P1D
pins output.
16.5.3
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as out-
puts; however, only two outputs are active at a time. In
the Forward mode, pin RD4/PSP4/ECCP1/P1A is con-
tinuously active and pin RD7/PSP7/P1D is modulated.
In the Reverse mode, RD6/PSP6/P1C pin is continu-
ously active and RD5/PSP5/P1B pin is modulated.
These are illustrated in Figure 16-5.
FIGURE 16-5:
FULL-BRIDGE PWM OUTPUT
FORWARD MODE
Period
(2)
(2)
(2)
P1A
Duty Cycle
P1B
P1C
(2)
P1D
(1)
(1)
REVERSE MODE
Period
Duty Cycle
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as asserted high.
© 2006 Microchip Technology Inc.
DS41159E-page 137
PIC18FXX8
FIGURE 16-6:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F448/458
QB
QD
FET
Driver
FET
Driver
P1D
+
-
Load
P1C
FET
Driver
FET
Driver
P1B
P1A
QA
QC
V-
Figure 16-8 shows an example where the PWM
direction changes from forward to reverse at a near
100% duty cycle. At time t1, the outputs P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current flows through power devices QB and QD (see
Figure 16-6) for the duration of ‘t’. The same phenom-
enon will occur to power devices QA and QC for PWM
direction change from reverse to forward.
16.5.3.1
Direction Change in Full-Bridge
Mode
In the Full-Bridge Output mode, the EPWM1M1 bit in
the ECCP1CON register allows the user to control the
forward/reverse direction. When the application firm-
ware changes this direction control bit, the ECCP1
module will assume the new direction on the next PWM
cycle. The current PWM cycle still continues, however,
the non-modulated outputs, P1A and P1C signals, will
transition to the new direction TOSC, 4 TOSC or 16 TOSC
earlier (for T2CKRS<1:0> = 00, 01or 1x, respectively)
before the end of the period. During this transition
cycle, the modulated outputs, P1B and P1D, will go to
the inactive state (Figure 16-7).
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Avoid changing PWM output direction at or near
100% duty cycle.
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any dead-band delay. In
general, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when all of the following
conditions are true:
2. Use switch drivers that compensate the slow
turn off of the power devices. The total turn-off
time (toff) of the power device and the driver
must be less than the turn-on time (ton).
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than turn-on time.
DS41159E-page 138
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 16-7:
PWM DIRECTION CHANGE
(1)
Period
Period
SIGNAL
DC
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
P1D (Active-High)
(2)
Note 1: The direction bit in the ECCP1 Control Register (ECCP1CON.EPWM1M1) is written any time during the PWM
cycle.
2: The P1A and P1C signals switch at intervals of TOSC, 4 TOSC or 16 TOSC, depending on the Timer2 prescaler
value earlier when changing direction. The modulated P1B and P1D signals are inactive at this time.
FIGURE 16-8:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
(1)
(1)
P1A
P1B
(PWM)
(1)
(1)
P1C
P1D
(PWM)
(2)
t
on
(1)
(1)
External Switch C
External Switch D
(3)
t
off
(2,3)
Potential
t = t – t
off
on
Shoot-Through
(1)
Current
t1
Note 1: All signals are shown as active-high.
2: t is the turn-on delay of power switch and driver.
on
3: t is the turn-off delay of power switch and driver.
off
© 2006 Microchip Technology Inc.
DS41159E-page 139
PIC18FXX8
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates
the PWM output(s).
16.5.4
PROGRAMMABLE DEAD-BAND
DELAY
In half-bridge or full-bridge applications, where all
power switches are modulated at the PWM frequency
at all times, the power switches normally require longer
time to turn off than to turn on. If both the upper and
lower power switches are switched at the same time
(one turned on and the other turned off), both switches
will be on for a short period of time until one switch
completely turns off. During this time, a very high
current (shoot-through current) flows through both
power switches, shorting the bridge supply. To avoid
this potentially destructive shoot-through current from
flowing during switching, turning on the power switch is
normally delayed to allow the other switch to
completely turn off.
16.5.6
START-UP CONSIDERATIONS
Prior to enabling the PWM outputs, the P1A, P1B, P1C
and P1D latches may not be in the proper states.
Enabling the TRISD bits for output at the same time
with the ECCP1 module may cause damage to the
power switch devices. The ECCP1 module must be
enabled in the proper output mode with the TRISD bits
enabled as inputs. Once the ECCP1 completes a full
PWM cycle, the P1A, P1B, P1C and P1D output
latches are properly initialized. At this time, the TRISD
bits can be enabled for outputs to start driving the
power switch devices. The completion of a full PWM
cycle is indicated by the TMR2IF bit going from a ‘0’ to
a ‘1’.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 16-3 for illustration.
The ECCP1DEL register (Register 16-2) sets the amount
of delay.
16.5.7
OUTPUT POLARITY
CONFIGURATION
The ECCP1M<1:0> bits in the ECCP1CON register
allow user to choose the logic conventions (asserted
high/low) for each of the outputs.
16.5.5
SYSTEM IMPLEMENTATION
The PWM output polarities must be selected before the
PWM outputs are enabled. Charging the polarity
configuration while the PWM outputs are active is not
recommended since it may result in unpredictable
operation.
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller powers up, all of the I/O pins
are in the high-impedance state. The external pull-up
and pull-down resistors must keep the power switch
REGISTER 16-2: ECCP1DEL: PWM DELAY REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EPDC7
EPDC6
EPDC5
EPDC4
EPDC3
EPDC2
EPDC1
EPDC0
bit 7
bit 0
bit 7-0
EPDC<7:0>: PWM Delay Count for Half-Bridge Output Mode bits
Number of FOSC/4 (TOSC * 4) cycles between the P1A transition and the P1B transition.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 140
© 2006 Microchip Technology Inc.
PIC18FXX8
2. Configure and start TMR2:
16.5.8
SETUP FOR PWM OPERATION
a) Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
b) Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
1. Configure the PWM module:
a) Disable the ECCP1/P1A, P1B, P1C and/or
P1D outputs by setting the respective TRISD
bits.
c) Enable Timer2 by setting the TMR2ON bit
(T2CON<2>) register.
3. Enable PWM outputs after a new cycle has
started:
b) Set the PWM period by loading the PR2
register.
a) Wait until TMR2 overflows (TMR2IF bit
becomes a ‘1’). The new PWM cycle begins
here.
c) Set the PWM duty cycle by loading the
ECCPR1L register and ECCP1CON<5:4>
bits.
b) Enable the ECCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISD bits.
d) Configure the ECCP1 module for the
desired PWM operation by loading the
ECCP1CON register with the appropriate
value. With the ECCP1M<3:0> bits, select
the active-high/low levels for each PWM
output. With the EPWM1M<1:0> bits, select
one of the available output modes.
e) For Half-Bridge Output mode, set the dead-
band delay by loading the ECCP1DEL
register with the appropriate value.
TABLE 16-5: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
IPR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 000x 0000 000u
0--1 110q 0--0 011q
IPEN
—
—
—
—
—
—
CMIP
CMIF
CMIE
EEIP
EEIF
EEIE
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP ECCP1IP -1-1 1111 -1-1 1111
TMR3IF ECCP1IF -0-0 0000 -0-0 0000
TMR3IE ECCP1IE -0-0 0000 -0-0 0000
0000 0000 0000 0000
PIR2
—
PIE2
—
TMR2
PR2
Timer2 Module Register
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
TRISD
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PORTD Data Direction Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
ECCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte
ECCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte
ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000
ECCPAS
ECCP1DEL
Legend:
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
EPDC7 EPDC6 EPDC5 EPDC4 EPDC3 EPDC2 EPDC1 EPDC0 0000 0000 uuuu uuuu
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module.
© 2006 Microchip Technology Inc.
DS41159E-page 141
PIC18FXX8
The internal shutdown signal is gated with the outputs
and will immediately and asynchronously disable the
outputs. If the internal shutdown is still in effect at the
16.6 Enhanced CCP Auto-Shutdown
When the ECCP is programmed for any of the PWM
modes, the output pins associated with its function may
be configured for auto-shutdown.
time
a new cycle begins, that entire cycle is
suppressed, thus eliminating narrow, glitchy pulses.
Auto-shutdown allows the internal output of either of
the two comparator modules, or the external
interrupt 0, to asynchronously disable the ECCP output
pins. Thus, an external analog or digital event can
discontinue an ECCP sequence. The comparator out-
put(s) to be used is selected by setting the proper mode
bits in the ECCPAS register. To use external interrupt
INT0 as a shutdown event, INT0IE must be set. To use
either of the comparator module outputs as a shutdown
event, corresponding comparators must be enabled.
When a shutdown occurs, the selected output values
(PSSACn, PSSBDn) are written to the ECCP port pins.
The ECCPASE bit is set by hardware upon a compara-
tor event and can only be cleared in software. The
ECCP outputs can be re-enabled only by clearing the
ECCPASE bit.
The Auto-Shutdown mode can be manually entered by
writing a ‘1’ to the ECCPASE bit.
REGISTER 16-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
bit 7
bit 0
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
0= ECCP outputs enabled, no shutdown event
1= A shutdown event has occurred, must be reset in software to re-enable ECCP
bit 6-4
ECCPAS<2:0>: ECCP Auto-Shutdown bits
000= No auto-shutdown enabled, comparators have no effect on ECCP
001= Comparator 1 output will cause shutdown
010= Comparator 2 output will cause shutdown
011= Either Comparator 1 or 2 can cause shutdown
100= INT0
101= INT0 or Comparator 1 output
110= INT0 or Comparator 2 output
111= INT0 or Comparator 1 or Comparator 2 output
bit 3-2
bit 1-0
PSSACn: Pins A and C Shutdown State Control bits
00= Drive Pins A and C to ‘0’
01= Drive Pins A and C to ‘1’
1x= Pins A and C tri-state
PSSBDn: Pins B and D Shutdown State Control bits
00= Drive Pins B and D to ‘0’
01= Drive Pins B and D to ‘1’
1x= Pins B and D tri-state
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 142
© 2006 Microchip Technology Inc.
PIC18FXX8
17.3 SPI Mode
17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four modes
of SPI are supported. To accomplish communication,
typically three pins are used:
17.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/LVDIN
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI™ MODE)
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
Read
Write
• Master mode
• Multi-Master mode
• Slave mode
SSPBUF reg
SSPSR reg
17.2 Control Registers
RC4/SDI/SDA
RC5/SDO
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Shift
Clock
bit0
RA5/AN4/
SS/LVDIN
Control
Enable
Additional details are provided under the individual
sections.
SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
RC3/SCK/
SCL
(
)
2
Edge
Select
TOSC
Prescaler
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
© 2006 Microchip Technology Inc.
DS41159E-page 143
PIC18FXX8
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
17.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Edge Select bit
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
bit 5
bit 4
D/A: Data/Address bit
Used in I2C mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3
bit 2
bit 1
bit 0
S: Start bit
Used in I2C mode only.
R/W: Read/Write Information bit
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 144
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user
must read the SSPBUF even if only transmitting data to avoid setting overflow (must be
cleared in software).
0= No overflow
Note:
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 145
PIC18FXX8
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
Full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit BF
(SSPSTAT<0>) and the interrupt flag bit SSPIF are set.
This double-buffering of the received data (SSPBUF)
allows the next byte to start reception before reading
the data that was just received. Any write to the
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 17-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF
;Has data been received(transmit complete)?
BRA
LOOP
;No
MOVF
SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF SSPBUF
TXDATA, W
;W reg = contents of TXDATA
;New data to xmit
DS41159E-page 146
© 2006 Microchip Technology Inc.
PIC18FXX8
17.3.3
ENABLING SPI I/O
17.3.4
TYPICAL CONNECTION
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the SSPCON
registers and then, set the SSPEN bit. This configures
the SDI, SDO, SCK and SS pins as serial port pins. For
the pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed as follows:
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISA<5> bit set
• Master sends dummy data – Slave sends data
Any serial port function that is not desired may be over-
ridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
SPI™ MASTER/SLAVE CONNECTION
SPI™ Master SSPM3:SSPM0 = 00xxb
SPI™ Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
© 2006 Microchip Technology Inc.
DS41159E-page 147
PIC18FXX8
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication as shown in
Figure 17-3, Figure 17-5 and Figure 17-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
17.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 17-3:
SPI™ MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
DS41159E-page 148
© 2006 Microchip Technology Inc.
PIC18FXX8
must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
may be desirable depending on the application.
17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep. Before enabling the module in SPI Slave
mode, the clock line must match the proper Idle state.
The clock line can be observed by reading the SCK pin.
The Idle state is determined by the CKP bit
(SSPCON1<4>).
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
17.3.7
SLAVE SELECT
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The data latch
FIGURE 17-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 7
bit 7
bit 0
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
© 2006 Microchip Technology Inc.
DS41159E-page 149
PIC18FXX8
FIGURE 17-5:
SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 3
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 17-6:
SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 3
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
DS41159E-page 150
© 2006 Microchip Technology Inc.
PIC18FXX8
17.3.8
SLEEP OPERATION
17.3.10 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1: SPI™ BUS MODES
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
17.3.9
EFFECTS OF A RESET
There is also an SMP bit which controls when the data
is sampled.
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
(1)
PIE1
IPR1
TRISC
PORTC Data Direction Register
TRISA6 TRISA5 TRISA4 TRISA3
Synchronous Serial Port Receive Buffer/Transmit Register
TRISA
—
TRISA2
TRISA1 TRISA0 -111 1111 -111 1111
xxxx xxxx uuuu uuuu
SSPBUF
SSPCON1
SSPSTAT
Legend:
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1 SSPM0 0000 0000 0000 0000
UA
BF
0000 0000 0000 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI™ mode.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 151
PIC18FXX8
2
17.4.1
REGISTERS
17.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
Internal
Data Bus
SSPADD register holds the slave device address
when the SSP is configured in I2C Slave mode. When
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate
Generator reload value.
Read
Write
RC3/SCK/
SCL
SSPBUF reg
Shift
Clock
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPSR reg
RC4/
SDI/
MSb
LSb
SDA
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
Addr Match
Match Detect
SSPADD reg
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit Detect
DS41159E-page 152
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
bit 5
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
S: Start bit
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
R/W: Read/Write Information bit (I2C mode only)
In Slave mode:
1= Read
0= Write
Note:
This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Idle mode.
bit 1
bit 0
UA: Update Address bit (10-bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
In Receive mode:
1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 153
PIC18FXX8
REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for
a transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPBUF register is still holding the previous byte (must
be cleared in software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDA and SCL pins must be properly configured as input or output.
CKP: SCK Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (Slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Note:
Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 154
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1= Not Acknowledge
0= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (Master Mode only)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (Master mode only)
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enable bit (Master mode only)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is enabled for slave transmit only (Legacy mode)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
© 2006 Microchip Technology Inc.
DS41159E-page 155
PIC18FXX8
17.4.2
OPERATION
17.4.3.1
Addressing
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I2C modes to be selected:
• I2C Master mode, clock = OSC/4 (SSPADD +1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit BF is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs
of the address. The sequence of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits.
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
7. Receive Repeated Start condition.
• The overflow bit, SSPOV (SSPCON1<6>), was
set before the transfer was received.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
DS41159E-page 156
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.3.2
Reception
17.4.3.3
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then, pin RC3/
SCK/SCL should be enabled by setting bit CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set or bit SSPOV (SSPCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit
CKP (SSPCON1<4>). See Section 17.4.4 “Clock
Stretching” for more detail.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
© 2006 Microchip Technology Inc.
DS41159E-page 157
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2
FIGURE 17-8:
I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
DS41159E-page 158
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2
FIGURE 17-9:
I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
© 2006 Microchip Technology Inc.
DS41159E-page 159
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FIGURE 17-10:
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
DS41159E-page 160
© 2006 Microchip Technology Inc.
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2
FIGURE 17-11:
I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
© 2006 Microchip Technology Inc.
DS41159E-page 161
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17.4.4
CLOCK STRETCHING
17.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
17.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON1 register is auto-
matically cleared, forcing the SCL output to be held
low. The CKP being cleared to ‘0’ will assert the SCL
line low. The CKP bit must be set in the user’s ISR
before reception is allowed to continue. By holding the
SCL line low, the user has time to service the ISR and
read the contents of the SSPBUF before the master
device can initiate another receive sequence. This will
prevent buffer overruns from occurring.
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
17.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-bit Slave
Receive mode. The first two addresses are followed
by a third address sequence which contains the high-
order bits of the 10-bit address and the R/W bit set to
‘1’. After the third address sequence is performed, the
UA bit is not set, the module is now configured in
Transmit mode and clock stretching is controlled by
the BF flag as in 7-bit Slave Transmit mode (see
Figure 17-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
17.4.4.2
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
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assert the SCL line until an external I2C master device
has already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other devices
on the I2C bus have deasserted SCL. This ensures that
a write to the CKP bit will not violate the minimum high
time requirement for SCL (see Figure 17-12).
17.4.4.5
Clock Synchronization and
the CKP bit
If a user clears the CKP bit, the SCL output is forced to
‘0’. Setting the CKP bit will not assert the SCL output
low until the SCL output is already sampled low. If the
user attempts to drive SCL low, the CKP bit will not
FIGURE 17-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX – 1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON1
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2
FIGURE 17-13:
I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
DS41159E-page 164
© 2006 Microchip Technology Inc.
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FIGURE 17-14:
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
© 2006 Microchip Technology Inc.
DS41159E-page 165
PIC18FXX8
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
17.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving data
D5 D4 D3 D2 D1
ACK
9
R/W = 0
General Call Address
ACK
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
‘0’
‘1’
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17.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start condition
• Stop condition
Once Master mode is enabled, the user has six
options.
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
2
FIGURE 17-16:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL in
Bus Collision
Set/Reset S, P, WCOL (SSPSTAT);
set SSPIF, BCLIF;
reset ACKSTAT, PEN (SSPCON2)
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
17.4.6.1
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition, or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDA while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning and
end of transmission.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate Generator” for more
details.
11. The user generates a Stop condition by setting
the Stop Enable bit PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
DS41159E-page 168
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Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
17.4.7
BAUD RATE GENERATOR
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 17-3: I2C™ CLOCK RATE w/BRG
FSCL
FOSC
FCY
FCY * 2
BRG Value
(2 Rollovers of BRG)
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Ch
27h
02h
09h
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
4 MHz
100kHz
1 MHz(1)
4 MHz
Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
© 2006 Microchip Technology Inc.
DS41159E-page 169
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SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-18).
17.4.7.1
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 17-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX – 1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
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17.4.8
I2C MASTER MODE START
CONDITION TIMING
17.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
To initiate a Start condition, the user sets the Start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<6:0>
and starts its count. If SCL and SDA are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the Start condition and
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the Baud Rate Generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
Note:
If, at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs;
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
FIGURE 17-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
At completion of Start bit,
Write to SEN bit occurs here
SDA = 1,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG
TBRG
Write to SSPBUF occurs here
1st bit
2nd bit
SDA
TBRG
SCL
TBRG
S
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I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode, or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
17.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Genera-
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
notbesetuntiltheBaudRateGeneratorhastimedout.
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 17-20:
REPEATED START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
SDA = 1,
SCL = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPBUF occurs here
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated Start
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17.4.10 I2C MASTER MODE
TRANSMISSION
17.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
#106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification
parameter #107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time, if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKDT bit
on the falling edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
17.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
Note:
The RCEN bit should be set after the ACK
sequence is complete or the RCEN bit will
be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate Gener-
ator is suspended from counting, holding SCL low. The
MSSP is now in Idle state awaiting the next command.
When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>).
17.4.11.1 BF Status Flag
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the
falling edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF bit is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
17.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
© 2006 Microchip Technology Inc.
DS41159E-page 173
PIC18FXX8
2
FIGURE 17-21:
I C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS41159E-page 174
© 2006 Microchip Technology Inc.
PIC18FXX8
2
FIGURE 17-22:
I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
© 2006 Microchip Technology Inc.
DS41159E-page 175
PIC18FXX8
17.4.12 ACKNOWLEDGE SEQUENCE
TIMING
17.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is
sampled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
sampled high while SCL is high, the
(SSPSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 17-24).
P
bit
17.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t occur).
FIGURE 17-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
ACK
SDA
SCL
D0
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 17-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
DS41159E-page 176
© 2006 Microchip Technology Inc.
PIC18FXX8
17.4.14 SLEEP OPERATION
17.4.17 MULTI -MASTER
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
COMMUNICATION, BUS COLLISION
AND BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag BCLIF and reset the I2C
port to its Idle state (Figure 17-25).
17.4.15 EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume communication
by asserting a Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register or
the bus is Idle and the S and P bits are cleared.
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
© 2006 Microchip Technology Inc.
DS41159E-page 177
PIC18FXX8
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0 and during this time, if the SCL pins
are sampled as ‘0’, a bus collision does not occur. At
the end of the BRG count, the SCLpin is asserted low.
17.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 17-26).
b) SCL is sampled low before SDA is asserted low
(Figure 17-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
•
the MSSP module is reset to its Idle state
(Figure 17-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 17-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software.
DS41159E-page 178
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPIF
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1,
set SSPIF
© 2006 Microchip Technology Inc.
DS41159E-page 179
PIC18FXX8
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
17.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(Figure 17-30).
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
FIGURE 17-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 17-30:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software
‘0’
S
SSPIF
DS41159E-page 180
© 2006 Microchip Technology Inc.
PIC18FXX8
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
17.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
© 2006 Microchip Technology Inc.
DS41159E-page 181
PIC18FXX8
NOTES:
DS41159E-page 182
© 2006 Microchip Technology Inc.
PIC18FXX8
The USART can be configured in the following modes:
18.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex).
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The SPEN (RCSTA register) and the TRISC<7> bits
have to be set and the TRISC<6> bit must be cleared
in order to configure pins RC6/TX/CK and RC7/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the three serial
I/O modules incorporated into PIC18FXX8 devices.
(USART is also known as a Serial Communications
Interface or SCI.) The USART can be configured as a
full-duplex asynchronous system that can communi-
cate with peripheral devices, such as CRT terminals
and personal computers, or it can be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
Register 18-1 shows the Transmit Status and Control
register (TXSTA) and Register 18-2 shows the Receive
Status and Control register (RCSTA).
REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as ‘0’
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 183
PIC18FXX8
REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive (this bit is cleared after reception is complete)
Synchronous mode – Slave:
Unused in this mode.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and load of the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 184
© 2006 Microchip Technology Inc.
PIC18FXX8
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
18.1 USART Baud Rate Generator
(BRG)
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running, 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA register) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 18-1 shows the formula for
computation of the baud rate for different USART
modes which only apply in Master mode (internal
clock).
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
18.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 18-1:
CALCULATING BAUD RATE ERROR
Desired Baud Rate
= FOSC/(64 (X + 1))
Solving for X:
X
X
X
= ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate
Error
= 16000000/(64 (25 + 1))
= 9615
= (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
TABLE 18-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64 (X + 1))
(Synchronous) Baud Rate = FOSC/(4 (X + 1))
Baud Rate = FOSC/(16 (X + 1))
NA
Legend: X = value in SPBRG (0 to 255)
TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA
RCSTA
SPBRG
CSRC
SPEN
TX9
RX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010
0000 -010
0000 000u
0000 0000
SREN CREN ADDEN FERR OERR RX9D 0000 000x
0000 0000
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
© 2006 Microchip Technology Inc.
DS41159E-page 185
PIC18FXX8
TABLE 18-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
-
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
-
NA
-
-
-
NA
-
-
-
NA
-
-
19.2
76.8
96
NA
-
-
NA
-
NA
-
NA
-
-
76.92
96.15
303.03
500
+0.16
129
103
32
19
0
77.10
95.93
294.64
485.30
8250
32.23
+0.39
-0.07
-1.79
-2.94
-
106
85
27
16
0
77.16
96.15
297.62
480.77
6250
24.41
+0.47
+0.16
-0.79
-3.85
-
80
64
20
12
0
76.92
96.15
294.12
500
+0.16
64
51
16
9
+0.16
+0.16
300
500
HIGH
LOW
+1.01
-1.96
0
-
0
-
10000
39.06
5000
19.53
0
-
255
-
255
-
255
-
255
FOSC = 16 MHz
10 MHz
7.15909 MHz
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
-
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
+0.16
+0.16
-0.79
+2.56
0
-
NA
-
+0.16
-1.36
+0.16
+4.17
0
-
9.62
+0.23
+0.23
+1.32
-1.88
-0.57
-10.51
-
185
92
22
18
5
9.60
0
0
131
65
16
12
3
19.2
76.8
96
19.23
76.92
95.24
307.70
500
207
51
41
12
7
19.23
75.76
96.15
312.50
500
129
32
25
7
19.24
77.82
94.20
298.35
447.44
1789.80
6.99
19.20
74.54
97.48
316.80
422.40
1267.20
4.95
-2.94
+1.54
+5.60
-15.52
-
300
500
HIGH
LOW
4
3
2
4000
15.63
-
0
2500
9.77
-
0
0
0
-
255
-
255
-
255
-
255
FOSC = 4 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
-
NA
1.20
2.40
9.62
19.23
83.33
83.33
250
-
-
207
103
25
12
2
0.30
1.17
2.73
8.20
NA
+1.14
26
-
-
+0.16
+0.16
+0.16
+0.16
+8.51
-13.19
-16.67
-
-2.48
6
2.4
NA
-
NA
-
-
+13.78
2
9.6
9.62
19.23
76.92
1000
333.33
500
+0.16
+0.16
+0.16
+4.17
+11.11
0
103
51
12
9
9.62
+0.23
-0.83
-2.90
+3.57
-0.57
-10.51
-
92
46
11
8
-14.67
0
19.2
76.8
96
19.04
74.57
99.43
298.30
447.44
894.89
3.50
-
-
-
-
-
-
-
-
NA
-
2
NA
-
300
500
HIGH
LOW
2
2
0
NA
-
-
1
1
NA
-
NA
1000
3.91
-
0
0
250
-
0
8.20
0.03
0
-
255
-
255
0.98
-
255
255
DS41159E-page 186
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 18-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
1.2
NA
NA
-
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
-
2.4
NA
-
-
2.40
-0.07
-0.54
-0.54
-4.09
+7.42
-14.06
-
214
53
26
6
2.40
9.53
19.53
78.13
97.66
NA
-0.15
162
40
19
4
2.40
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
-
129
32
15
3
9.6
9.62
18.94
78.13
89.29
312.50
625
+0.16
-1.36
+1.73
-6.99
+4.17
+25.00
-
64
32
7
9.55
-0.76
9.47
19.2
76.8
96
19.10
73.66
103.13
257.81
NA
+1.73
19.53
78.13
104.17
312.50
NA
+1.73
6
4
+1.73
3
2
300
500
HIGH
LOW
1
1
-
-
-
-
-
0
0
-
NA
-
-
625
0
515.63
2.01
-
0
390.63
1.53
0
312.50
1.22
-
0
2.44
-
255
-
255
255
-
255
FOSC = 16 MHz
10 MHz
7.15909 MHz
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
1.2
NA
1.20
2.40
9.62
19.23
83.33
83.33
250
-
-
207
103
25
12
2
NA
1.20
-
-
129
64
15
7
NA
1.20
2.38
9.32
18.64
111.86
NA
-
-
92
46
11
5
NA
1.20
2.40
9.90
19.80
79.20
NA
-
-
65
32
7
+0.16
+0.16
+0.16
+0.16
+8.51
-13.19
-16.67
-
+0.16
+0.16
+1.73
+1.73
+1.73
-18.62
-47.92
-
+0.23
0
2.4
2.40
-0.83
0
9.6
9.77
-2.90
+3.13
19.2
76.8
96
19.53
78.13
78.13
156.25
NA
-2.90
+3.13
3
1
+45.65
0
+3.13
0
2
1
-
-
-
-
-
-
-
-
-
-
-
-
300
500
HIGH
LOW
0
0
NA
-
NA
-
NA
-
-
NA
-
NA
-
250
-
0
156.25
0.61
-
0
111.86
0.44
0
79.20
0.31
0
0.98
-
255
-
255
255
255
FOSC = 4 MHz
3.579545 MHz
%
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
0.3
1.2
0.30
1.20
2.40
8.93
20.83
62.50
NA
-0.16
207
51
25
6
0.30
1.19
2.43
9.32
18.64
55.93
NA
+0.23
185
46
22
5
0.30
1.20
2.23
7.81
15.63
NA
+0.16
51
12
6
0.26
NA
-14.67
1
+1.67
-0.83
+0.16
-
-
-
-
-
-
-
-
-
-
-
2.4
+1.67
+1.32
-6.99
NA
-
9.6
-6.99
-2.90
-18.62
1
NA
-
19.2
76.8
96
+8.51
2
-2.90
2
-18.62
0
NA
-
-18.62
0
-27.17
0
-
-
-
-
-
-
-
NA
-
-
-
-
-
-
-
-
-
-
-
-
-
NA
-
NA
-
300
500
HIGH
LOW
NA
-
NA
-
NA
-
NA
-
-
NA
-
NA
-
NA
-
NA
62.50
0.24
0
55.93
0.22
0
15.63
0.06
0
0.51
0.002
0
255
255
255
255
© 2006 Microchip Technology Inc.
DS41159E-page 187
PIC18FXX8
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
+0.16
-1.36
+0.16
+4.17
0
-
9.60
-0.07
+0.39
-0.54
+2.31
-1.79
+3.13
-
214
106
26
20
6
9.59
-0.15
+0.47
+1.73
+1.73
+4.17
+4.17
-
162
80
19
15
4
9.62
+0.16
+0.16
+1.73
+0.16
+4.17
-16.67
-
129
64
15
12
3
19.2
76.8
96
19.23
75.76
96.15
312.50
500
129
32
25
7
19.28
76.39
98.21
294.64
515.63
2062.50
8,06
19.30
78.13
97.66
312.50
520.83
1562.50
6.10
19.23
78.13
96.15
312.50
416.67
1250
4.88
300
500
HIGH
LOW
4
3
2
2
2500
9.77
-
0
0
0
0
-
255
-
255
-
255
-
255
FOSC = 16 MHz
10 MHz
7.15909 MHz
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
-
-
2.4
NA
-
+0.16
+0.16
+0.16
+4.17
+11.11
0
-
NA
-
-
2.41
+0.23
-0.83
+1.32
-2.90
-6.78
+49.15
-10.51
-
185
46
22
5
2.40
0
131
32
16
3
9.6
9.62
19.23
76.92
100
103
51
12
9
9.62
18.94
78.13
89.29
312.50
625
+0.16
-1.36
+1.73
-6.99
+4.17
+25.00
-
64
32
7
9.52
9.60
0
-2.94
+3.13
+10.00
+5.60
-
19.2
76.8
96
19.45
74.57
89.49
447.44
447.44
447.44
1.75
18.64
79.20
105.60
316.80
NA
6
4
2
300
500
HIGH
LOW
333.33
500
2
1
0
0
1
0
0
-
1000
3.91
-
0
625
0
0
316.80
1.24
-
0
-
255
2.44
-
255
-
255
-
255
FOSC = 4 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
0.3
1.2
NA
1.20
2.40
9.62
19.23
NA
-
-
207
103
25
12
-
NA
1.20
-
+0.23
+0.23
+1.32
-2.90
-2.90
+16.52
-25.43
-
-
185
92
22
11
2
0.30
1.20
2.40
8.93
20.83
62.50
NA
+0.16
207
51
25
6
0.29
1.02
2.05
NA
-2.48
6
+0.16
+0.16
-14.67
1
2.4
+0.16
2.41
+0.16
-14.67
0
9.6
+0.16
9.73
-6.99
-
-
-
-
-
-
-
-
-
19.2
76.8
96
+0.16
18.64
74.57
111.86
223.72
NA
+8.51
2
NA
-
-
-
-
-
-
-
-18.62
0
NA
-
NA
-
1
-
-
-
-
-
-
NA
-
300
500
HIGH
LOW
NA
-
0
NA
-
NA
-
-
NA
-
-
NA
-
NA
250
0.98
0
55.93
0.22
-
0
62.50
0.24
0
2.05
0.008
0
255
-
255
255
255
DS41159E-page 188
© 2006 Microchip Technology Inc.
PIC18FXX8
interrupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE1 register). Flag bit TXIF will be set
regardless of the state of enable bit TXIE and cannot be
cleared in software. It will reset only when new data is
loaded into the TXREG register. While flag bit, TXIF,
indicated the status of the TXREG register, another bit,
TRMT (TXSTA register), shows the status of the TSR
register. Status bit TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit, so the user has to poll this bit in order to
determine if the TSR register is empty.
18.2 USART Asynchronous Mode
In this mode, the USART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip dedicated 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The USART transmits
and receives the LSb first. The USART’s transmitter
and receiver are functionally independent but use the
same data format and baud rate. The Baud Rate
Generator produces a clock, either x16 or x64 of the bit
shift rate, depending on the BRGH bit (TXSTA regis-
ter). Parity is not supported by the hardware but can be
implemented in software (and stored as the ninth data
bit). Asynchronous mode is stopped during Sleep.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
Asynchronous mode is selected by clearing the SYNC
bit (TXSTA register).
Steps to follow when setting up an Asynchronous
Transmission:
The USART Asynchronous module consists of the
following important elements:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.1 “USART Baud
Rate Generator (BRG)”).
• Baud Rate Generator
• Sampling Circuit
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• Asynchronous Transmitter
• Asynchronous Receiver.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
18.2.1
USART ASYNCHRONOUS
TRANSMITTER
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The TSR register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit TXIF (PIR1 register) is set. This
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
FIGURE 18-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
8
TXIE
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
© 2006 Microchip Technology Inc.
DS41159E-page 189
PIC18FXX8
FIGURE 18-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1
Word 2
Start bit
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
TXIF bit
(Interrupt Reg. Flag)
Word 1
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF 0000 000x 0000 000u
PIR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
IPR1
RCSTA
SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000u
TXREG USART Transmit Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
—
BRGH TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Legend: x= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 190
© 2006 Microchip Technology Inc.
PIC18FXX8
18.2.2
USART ASYNCHRONOUS
RECEIVER
18.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 18-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter, operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC. This mode would
typically be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enable:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
Steps to follow when setting up an Asynchronous
Reception:
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.1 “USART Baud
Rate Generator (BRG)”).
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
6. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
9. Read RCREG to determine if the device is being
addressed.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
FIGURE 18-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
or
÷ 16
RSR Register
LSb
Start
MSb
0
Baud Rate Generator
1
7
Stop (8)
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
Note: I/O pins have diode protection to VDD and VSS.
© 2006 Microchip Technology Inc.
DS41159E-page 191
PIC18FXX8
FIGURE 18-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit 0 bit 1
Stop
bit
Stop
bit
bit 7/8 Stop
bit
bit 0
bit 7/8
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
(1)
(1)
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend:
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000u
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
USART Receive Register
CSRC TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
Baud Rate Generator Register
x= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
DS41159E-page 192
© 2006 Microchip Technology Inc.
PIC18FXX8
software. It will reset only when new data is loaded into
the TXREG register. While flag bit, TXIF, indicates the
status of the TXREG register, another bit, TRMT
(TXSTA register), shows the status of the TSR register.
TRMT is a read-only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR
register is empty. The TSR is not mapped in data
memory, so it is not available to the user.
18.3 USART Synchronous
Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA register).
In addition, enable bit SPEN (RCSTA register) is set in
order to configure the RC6/TX/CK and RC7/RX/DT I/O
pins to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA register).
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
18.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG is empty and interrupt
bit TXIF (PIR1 register) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1 register). Flag bit TXIF will be set regardless of
the state of enable bit TXIE and cannot be cleared in
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
TMR2IF TMR1IF 0000 0000 0000 0000
(1)
(1)
PIE1
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
IPR1
RCSTA
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000u
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
TXREG USART Transmit Register
TXSTA CSRC TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
SPBRG Baud Rate Generator Register
Legend:
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
© 2006 Microchip Technology Inc.
DS41159E-page 193
PIC18FXX8
FIGURE 18-6:
SYNCHRONOUS TRANSMISSION
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 7
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
Word 1
RC6/TX/CK
pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode; SPBRG = 0; continuous transmission of two 8-bit words.
FIGURE 18-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
DS41159E-page 194
© 2006 Microchip Technology Inc.
PIC18FXX8
Steps to follow when setting up a Synchronous Master
Reception:
18.3.2
USART SYNCHRONOUS MASTER
RECEPTION
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register) or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CREN
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
(1)
(1)
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend:
SPEN
FERR
OERR
RX9D
0000 000x 0000 000u
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
USART Receive Register
CSRC TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
Baud Rate Generator Register
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q1 Q2 Q3
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4 Q1
Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
© 2006 Microchip Technology Inc.
DS41159E-page 195
PIC18FXX8
18.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
18.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in that the shift clock is supplied externally at the RC6/
TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA register).
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode and bit SREN, which is a “don’t care” in Slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector.
18.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will be set.
5. Flag bit RCIF will be set when reception is
complete. An interrupt will be generated if
enable bit RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Steps to follow when setting up a Synchronous Slave
Transmission:
7. Read the 8-bit received data by reading the
RCREG register.
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
8. If any error occurred, clear the error by clearing
bit CREN.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
DS41159E-page 196
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
(1)
PIE1
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
IPR1
TXIP
RCSTA
TXREG
TXSTA
SPBRG
Legend:
SPEN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000u
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
USART Transmit Register
CSRC TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
Baud Rate Generator Register
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
(1)
(1)
PIE1
IPR1
TXIP
RCSTA
RCREG
TXSTA
SPBRG
Legend:
SPEN
CREN
FERR
OERR
RX9D
0000 000x 0000 000u
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
USART Receive Register
CSRC TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
Baud Rate Generator Register
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
© 2006 Microchip Technology Inc.
DS41159E-page 197
PIC18FXX8
NOTES:
DS41159E-page 198
© 2006 Microchip Technology Inc.
PIC18FXX8
19.1.1
OVERVIEW OF THE MODULE
19.0 CAN MODULE
19.1 Overview
The CAN bus module consists of a protocol engine and
message buffering and control. The CAN protocol
engine handles all functions for receiving and transmit-
ting messages on the CAN bus. Messages are
transmitted by first loading the appropriate data
registers. Status and errors can be checked by reading
the appropriate registers. Any message detected on
the CAN bus is checked for errors and then matched
against filters to see if it should be received and stored
in one of the 2 receive registers.
The Controller Area Network (CAN) module is a serial
interface, useful for communicating with other peripher-
als or microcontroller devices. This interface/protocol
was designed to allow communications within noisy
environments.
The CAN module is a communication controller,
implementing the CAN 2.0 A/B protocol as defined in
the BOSCH specification. The module will support
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B
Active versions of the protocol. The module implemen-
tation is a full CAN system. The CAN specification is
not covered within this data sheet. The reader may
refer to the BOSCH CAN specification for further
details.
The CAN module supports the following frame types:
• Standard Data Frame
• Extended Data Frame
• Remote Frame
• Error Frame
• Overload Frame Reception
• Interframe Space
The module features are as follows:
• Complies with ISO CAN Conformance Test
CAN module uses RB3/CANRX and RB2/CANTX/INT2
pins to interface with CAN bus. In order to configure
CANRX and CANTX as CAN interface:
• Implementation of the CAN protocol CAN 1.2,
CAN 2.0A and CAN 2.0B
• Standard and extended data frames
• 0-8 bytes data length
• bit TRISB<3> must be set;
• bit TRISB<2> must be cleared.
• Programmable bit rate up to 1 Mbit/sec
• Support for remote frames
19.1.2
TRANSMIT/RECEIVE BUFFERS
• Double-buffered receiver with two prioritized
received message storage buffers
The PIC18FXX8 has three transmit and two receive
buffers, two acceptance masks (one for each receive
buffer) and a total of six acceptance filters. Figure 19-1
is a block diagram of these buffers and their connection
to the protocol engine.
• 6 full (standard/extended identifier) acceptance
filters, 2 associated with the high priority receive
buffer and 4 associated with the low priority
receive buffer
• 2 full acceptance filter masks, one each
associated with the high and low priority receive
buffers
• Three transmit buffers with application specified
prioritization and abort capability
• Programmable wake-up functionality with
integrated low-pass filter
• Programmable Loopback mode supports self-test
operation
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
• Programmable clock source
• Programmable link to timer module for
time-stamping and network synchronization
• Low-power Sleep mode
© 2006 Microchip Technology Inc.
DS41159E-page 199
PIC18FXX8
FIGURE 19-1:
CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
BUFFERS
Accept
Acceptance Mask
RXM1
Acceptance Filter
RXM2
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXB0
MESSAGE
Accept
Acceptance Mask
RXM0
Acceptance Filter
RXF3
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXB1
Acceptance Filter
RXF0
Acceptance Filter
RXF4
MESSAGE
Acceptance Filter
RXF5
Acceptance Filter
RXF1
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXB2
Message
Request
MESSAGE
RXB0
RXB1
Data and
Identifier
Data and
Identifier
Message
Queue
Identifier
Identifier
Control
Transmit Byte Sequencer
Message Assembly Buffer
PROTOCOL
ENGINE
Receive Shift
Transmit Shift
RXERRCNT
Comparator
CRC Register
Bus-Off
Err-Pas
Bit Timing
Generator
Transmit
Logic
Protocol
FSM
Bit Timing
Logic
Transmit
Error
Counter
Receive
Error
Counter
TXERRCNT
RX
TX
DS41159E-page 200
© 2006 Microchip Technology Inc.
PIC18FXX8
19.2.1
CAN CONTROL AND STATUS
REGISTERS
19.2 CAN Module Registers
Note:
Not all CAN registers are available in the
Access Bank.
The registers described in this section control the
overall operation of the CAN module and show its
operational status.
There are many control and data registers associated
with the CAN module. For convenience, their
descriptions have been grouped into the following
sections:
• Control and Status Registers
• Transmit Buffer Registers (Data and Control)
• Receive Buffer Registers (Data and Control)
• Baud Rate Control Registers
• I/O Control Register
• Interrupt Status and Control Registers
REGISTER 19-1: CANCON: CAN CONTROL REGISTER
R/W-1
R/W-0
R/W-0
R/W-0
ABAT
R/W-0
WIN2
R/W-0
WIN1
R/W-0
WIN0
U-0
—
REQOP2 REQOP1 REQOP0
bit 7
bit 0
bit 7-5
REQOP2:REQOP0: Request CAN Operation Mode bits
1xx= Request Configuration mode
011= Request Listen Only mode
010= Request Loopback mode
001= Request Disable mode
000= Request Normal mode
bit 4
ABAT: Abort All Pending Transmissions bit
1= Abort all pending transmissions (in all transmit buffers)
0= Transmissions proceeding as normal
bit 3-1
WIN2:WIN0: Window Address bits
This selects which of the CAN buffers to switch into the Access Bank area. This allows access
to the buffer registers from any data memory bank. After a frame has caused an interrupt, the
ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See
Example 19-1 for code example.
111= Receive Buffer 0
110= Receive Buffer 0
101= Receive Buffer 1
100= Transmit Buffer 0
011= Transmit Buffer 1
010= Transmit Buffer 2
001= Receive Buffer 0
000= Receive Buffer 0
bit 0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 201
PIC18FXX8
REGISTER 19-2: CANSTAT: CAN STATUS REGISTER
R-1
R-0
R-0
U-0
—
R-0
R-0
R-0
U-0
—
OPMODE2 OPMODE1 OPMODE0
bit 7
ICODE2 ICODE1 ICODE0
bit 0
bit 7-5
OPMODE2:OPMODE0: Operation Mode Status bits
111= Reserved
110= Reserved
101= Reserved
100= Configuration mode
011= Listen Only mode
010= Loopback mode
001= Disable mode
000= Normal mode
Note:
Before the device goes into Sleep mode, select Disable mode.
bit 4
Unimplemented: Read as ‘0’
bit 3-1
ICODE2:ICODE0: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in the
ICODE2:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE2:ICODE0
bits can be copied to the WIN2:WIN0 bits to select the correct buffer to map into the Access
Bank area. See Example 19-1 for code example.
111= Wake-up on interrupt
110= RXB0 interrupt
101= RXB1 interrupt
100= TXB0 interrupt
011= TXB1 interrupt
010= TXB2 interrupt
001= Error interrupt
000= No interrupt
bit 0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 202
© 2006 Microchip Technology Inc.
PIC18FXX8
EXAMPLE 19-1:
WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS
; Save application required context.
; Poll interrupt flags and determine source of interrupt
; This was found to be CAN interrupt
; TempCANCON and TempCANSTAT are variables defined in Access Bank low
MOVFF
CANCON, TempCANCON
; Save CANCON.WIN bits
; This is required to prevent CANCON
; from corrupting CAN buffer access
; in-progress while this interrupt
; occurred
MOVFF
CANSTAT, TempCANSTAT
; Save CANSTAT register
; This is required to make sure that
; we use same CANSTAT value rather
; than one changed by another CAN
; interrupt.
MOVF
ANDLW
ADDWF
TempCANSTAT, W
b’00001110’
PCL, F
; Retrieve ICODE bits
; Perform computed GOTO
; to corresponding interrupt cause
BRA
BRA
BRA
BRA
BRA
BRA
BRA
NoInterrupt
; 000 = No interrupt
ErrorInterrupt
TXB2Interrupt
TXB1Interrupt
TXB0Interrupt
RXB1Interrupt
RXB0Interrupt
; 001 = Error interrupt
; 010 = TXB2 interrupt
; 011 = TXB1 interrupt
; 100 = TXB0 interrupt
; 101 = RXB1 interrupt
; 110 = RXB0 interrupt
; 111 = Wake-up on interrupt
WakeupInterrupt
BCF
PIR3, WAKIF
; Clear the interrupt flag
;
; User code to handle wake-up procedure
;
;
; Continue checking for other interrupt source or return from here
…
NoInterrupt
…
; PC should never vector here. User may
; place a trap such as infinite loop or pin/port
; indication to catch this error.
ErrorInterrupt
BCF
…
PIR3, ERRIF
; Clear the interrupt flag
; Handle error.
RETFIE
TXB2Interrupt
BCF
GOTO
PIR3, TXB2IF
AccessBuffer
; Clear the interrupt flag
; Clear the interrupt flag
; Clear the interrupt flag
; Clear the interrupt flag
TXB1Interrupt
BCF
GOTO
PIR3, TXB1IF
AccessBuffer
TXB0Interrupt
BCF
GOTO
PIR3, TXB0IF
AccessBuffer
RXB1Interrupt
BCF
GOTO
PIR3, RXB1IF
Accessbuffer
© 2006 Microchip Technology Inc.
DS41159E-page 203
PIC18FXX8
EXAMPLE 19-1:
WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS (CONTINUED)
RXB0Interrupt
BCF
GOTO
PIR3, RXB0IF
AccessBuffer
; Clear the interrupt flag
AccessBuffer
; This is either TX or RX interrupt
; Copy CANCON.ICODE bits to CANSTAT.WIN bits
MOVF
CANCON, W
b’11110001’
CANCON
; Clear CANCON.WIN bits before copying
; new ones.
; Use previously saved CANCON value to
; make sure same value.
ANDLW
MOVWF
; Copy masked value back to TempCANCON
MOVF
ANDLW
TempCANSTAT, W
b’00001110’
; Retrieve ICODE bits
; Use previously saved CANSTAT value
; to make sure same value.
IORWF
CANCON
; Copy ICODE bits to WIN bits.
; Copy the result to actual CANCON
; Access current buffer…
; User code
; Restore CANCON.WIN bits
MOVF
ANDLW
IORWF
CANCON, W
b’11110001’
TempCANCON, W
; Preserve current non WIN bits
; Restore original WIN bits
MOVWF
CANCON
; Do not need to restore CANSTAT - it is read-only register.
; Return from interrupt or check for another module interrupt source
DS41159E-page 204
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-3: COMSTAT: COMMUNICATION STATUS REGISTER
R/C-0
R/C-0
R-0
R-0
R-0
R-0
TXWARN RXWARN EWARN
bit 0
R-0
R-0
RXB0OVFL RXB1OVFL
bit 7
TXBO
TXBP
RXBP
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RXB0OVFL: Receive Buffer 0 Overflow bit
1= Receive Buffer 0 overflowed
0= Receive Buffer 0 has not overflowed
RXB1OVFL: Receive Buffer 1 Overflow bit
1= Receive Buffer 1 overflowed
0= Receive Buffer 1 has not overflowed
TXBO: Transmitter Bus-Off bit
1= Transmit Error Counter > 255
0= Transmit Error Counter ≤ 255
TXBP: Transmitter Bus Passive bit
1= Transmission Error Counter > 127
0= Transmission Error Counter ≤ 127
RXBP: Receiver Bus Passive bit
1= Receive Error Counter > 127
0= Receive Error Counter ≤ 127
TXWARN: Transmitter Warning bit
1= 127 ≥ Transmit Error Counter > 95
0= Transmit Error Counter ≤ 95
RXWARN: Receiver Warning bit
1= 127 ≥ Receive Error Counter > 95
0= Receive Error Counter ≤ 95
EWARN: Error Warning bit
This bit is a flag of the RXWARN and TXWARN bits.
1= The RXWARN or the TXWARN bits are set
0= Neither the RXWARN or the TXWARN bits are set
Legend:
R = Readable bit
W = Writable bit C = Clearable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value at POR ‘1’ = Bit is set
© 2006 Microchip Technology Inc.
DS41159E-page 205
PIC18FXX8
19.2.2
CAN TRANSMIT BUFFER
REGISTERS
This section describes the CAN Transmit Buffer
registers and their associated control registers.
REGISTER 19-4: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS
U-0
—
R-0
R-0
R-0
R/W-0
U-0
—
R/W-0
R/W-0
TXABT
TXLARB
TXERR
TXREQ
TXPRI1
TXPRI0
bit 7
Unimplemented: Read as ‘0’
bit 0
bit 7
bit 6
TXABT: Transmission Aborted Status bit
1= Message was aborted
0= Message was not aborted
bit 5
bit 4
bit 3
TXLARB: Transmission Lost Arbitration Status bit
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1= A bus error occurred while the message was being sent
0= A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1= Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.
0= Automatically cleared when the message is successfully sent
Note:
Clearing this bit in software while the bit is set will request a message abort.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
TXPRI1:TXPRI0: Transmit Priority bits
11= Priority Level 3 (highest priority)
10= Priority Level 2
01= Priority Level 1
00= Priority Level 0 (lowest priority)
Note:
These bits set the order in which the Transmit Buffer will be transferred. They do
not alter the CAN message identifier.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 206
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-5: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
bit 7-0
SID10:SID3: Standard Identifier bits if EXIDE = 0(TXBnSID Register) or
Extended Identifier bits EID28:EID21 if EXIDE = 1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-6: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
R/W-x
—
R/W-x
EXIDE
R/W-x
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
bit 7-5
SID2:SID0: Standard Identifier bits if EXIDE = 0or
Extended Identifier bits EID20:EID18 if EXIDE = 1
bit 4
bit 3
Unimplemented: Read as ‘0’
EXIDE: Extended Identifier enable bit
1= Message will transmit extended ID, SID10:SID0 becomes EID28:EID18
0= Message will transmit standard ID, EID17:EID0 are ignored
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-7: TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
bit 7-0
EID15:EID8: Extended Identifier bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 207
PIC18FXX8
REGISTER 19-8: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
bit 7-0
EID7:EID0: Extended Identifier bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-9: TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0
bit 7 bit 0
R/W-x
bit 7-0
TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8)
Each Transmit Buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers:
TXB0D0 to TXB0D7.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 208
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-10: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS
U-0
—
R/W-x
U-0
—
U-0
—
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
TXRTR
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
TXRTR: Transmission Frame Remote Transmission Request bit
1= Transmitted message will have TXRTR bit set
0= Transmitted message will have TXRTR bit cleared
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
DLC3:DLC0: Data Length Code bits
1111= Reserved
1110= Reserved
1101= Reserved
1100= Reserved
1011= Reserved
1010= Reserved
1001= Reserved
1000= Data Length = 8 bytes
0111= Data Length = 7 bytes
0110= Data Length = 6 bytes
0101= Data Length = 5 bytes
0100= Data Length = 4 bytes
0011= Data Length = 3 bytes
0010= Data Length = 2 bytes
0001= Data Length = 1 bytes
0000= Data Length = 0 bytes
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-11: TXERRCNT: TRANSMIT ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
bit 7
bit 0
bit 7-0
TEC7:TEC0: Transmit Error Counter bits
This register contains a value which is derived from the rate at which errors occur. When the
error count overflows, the bus-off state occurs. When the bus has 128 occurrences of
11 consecutive recessive bits, the counter value is cleared.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 209
PIC18FXX8
19.2.3
CAN RECEIVE BUFFER
REGISTERS
This section shows the Receive Buffer registers with
their associated control registers.
REGISTER 19-12: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER
R/C-0
R/W-0
R/W-0
U-0
—
R-0
R/W-0
R-0
R-0
RXFUL(1) RXM1(1) RXM0(1)
RXRTRRO RXB0DBEN JTOFF
FILHIT0
bit 7
bit 0
bit 7
RXFUL: Receive Full Status bit(1)
1= Receive buffer contains a received message
0= Receive buffer is open to receive a new message
Note:
This bit is set by the CAN module and must be cleared by software after the buffer
is read.
bit 6-5
RXM1:RXM0: Receive Buffer Mode bits(1)
11= Receive all messages (including those with errors)
10= Receive only valid messages with extended identifier
01= Receive only valid messages with standard identifier
00= Receive all valid messages
bit 4
bit 3
Unimplemented: Read as ‘0’
RXRTRRO: Receive Remote Transfer Request Read-Only bit
1= Remote transfer request
0= No remote transfer request
bit 2
bit 1
RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit
1= Receive Buffer 0 overflow will write to Receive Buffer 1
0= No Receive Buffer 0 overflow to Receive Buffer 1
JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)
1= Allows jump table offset between 6 and 7
0= Allows jump table offset between 1 and 0
Note:
This bit allows same filter jump table for both RXB0CON and RXB1CON.
bit 0
FILHIT0: Filter Hit bit
This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0.
1= Acceptance Filter 1 (RXF1)
0= Acceptance Filter 0 (RXF0)
Note 1: Bits RXFUL, RXM1 and RXM0 of RXB0CON are not mirrored in RXB1CON.
Legend:
R = Readable bit
W = Writable bit C = Clearable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value at POR ‘1’ = Bit is set
DS41159E-page 210
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-13: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER
R/C-0
R/W-0
R/W-0
U-0
—
R-0
R-0
R-0
R-0
RXFUL(1) RXM1(1) RXM0(1)
RXRTRRO FILHIT2
FILHIT1
FILHIT0
bit 7
bit 0
bit 7
RXFUL: Receive Full Status bit(1)
1= Receive buffer contains a received message
0= Receive buffer is open to receive a new message
Note:
This bit is set by the CAN module and should be cleared by software after the buffer
is read.
bit 6-5
RXM1:RXM0: Receive Buffer Mode bits(1)
11= Receive all messages (including those with errors)
10= Receive only valid messages with extended identifier
01= Receive only valid messages with standard identifier
00= Receive all valid messages
bit 4
bit 3
Unimplemented: Read as ‘0’
RXRTRRO: Receive Remote Transfer Request bit (read-only)
1= Remote transfer request
0= No remote transfer request
bit 2-0
FILHIT2:FILHIT0: Filter Hit bits
These bits indicate which acceptance filter enabled the last message reception into Receive
Buffer 1.
111= Reserved
110= Reserved
101= Acceptance Filter 5 (RXF5)
100= Acceptance Filter 4 (RXF4)
011= Acceptance Filter 3 (RXF3)
010= Acceptance Filter 2 (RXF2)
001= Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set
000= Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set
Note 1: Bits RXFUL, RXM1 and RXM0 of RXB1CON are not mirrored in RXB0CON.
Legend:
R = Readable bit
W = Writable bit C = Clearable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value at POR ‘1’ = Bit is set
© 2006 Microchip Technology Inc.
DS41159E-page 211
PIC18FXX8
REGISTER 19-14: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
bit 7-0
SID10:SID3: Standard Identifier bits if EXID = 0(RXBnSIDL Register) or
Extended Identifier bits EID28:EID21 if EXID = 1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-15: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
R/W-x
SRR
R/W-x
EXID
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
bit 7-5
bit 4
SID2:SID0: Standard Identifier bits if EXID = 0or
Extended Identifier bits EID20:EID18 if EXID = 1
SRR: Substitute Remote Request bit
This bit is always ‘0’ when EXID = 1or equal to the value of RXRTRRO (RXnBCON<3>)
when EXID = 0.
bit 3
EXID: Extended Identifier bit
1= Received message is an extended data frame, SID10:SID0 are EID28:EID18
0= Received message is a standard data frame
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-16: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 0
bit 7
bit 7-0
EID15:EID8: Extended Identifier bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 212
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-17: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
bit 7-0
EID7:EID0: Extended Identifier bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-18: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS
U-0
—
R/W-x
R/W-x
RB1
R/W-x
RB0
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
RXRTR
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
RXRTR: Receiver Remote Transmission Request bit
1= Remote transfer request
0= No remote transfer request
bit 5
RB1: Reserved bit 1
Reserved by CAN spec and read as ‘0’.
RB0: Reserved bit 0
bit 4
Reserved by CAN spec and read as ‘0’.
DLC3:DLC0: Data Length Code bits
bit 3-0
1111= Invalid
1110= Invalid
1101= Invalid
1100= Invalid
1011= Invalid
1010= Invalid
1001= Invalid
1000= Data Length = 8 bytes
0111= Data Length = 7 bytes
0110= Data Length = 6 bytes
0101= Data Length = 5 bytes
0100= Data Length = 4 bytes
0011= Data Length = 3 bytes
0010= Data Length = 2 bytes
0001= Data Length = 1 bytes
0000= Data Length = 0 bytes
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 213
PIC18FXX8
REGISTER 19-19: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS
R/W-x
RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0
bit 7 bit 0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 7-0
RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers:
RXB0D0 to RXB0D7.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-20: RXERRCNT: RECEIVE ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
bit 7
bit 0
bit 7-0
REC7:REC0: Receive Error Counter bits
This register contains the receive error value as defined by the CAN specifications.
When RXERRCNT > 127, the module will go into an error passive state. RXERRCNT does not
have the ability to put the module in “Bus-Off” state.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 214
© 2006 Microchip Technology Inc.
PIC18FXX8
19.2.3.1
Message Acceptance Filters and
Masks
This subsection describes the message acceptance
filters and masks for the CAN receive buffers.
REGISTER 19-21: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER,
HIGH BYTE REGISTERS
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
bit 7-0
SID10:SID3: Standard Identifier Filter bits if EXIDEN = 0or
Extended Identifier Filter bits EID28:EID21 if EXIDEN = 1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-22: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER,
LOW BYTE REGISTERS
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
U-0
—
R/W-x
EID17
R/W-x
EID16
EXIDEN
bit 7
bit 0
bit 7-5
SID2:SID0: Standard Identifier Filter bits if EXIDEN = 0 or
Extended Identifier Filter bits EID20:EID18 if EXIDEN = 1
bit 4
bit 3
Unimplemented: Read as ‘0’
EXIDEN: Extended Identifier Filter Enable bit
1= Filter will only accept extended ID messages
0= Filter will only accept standard ID messages
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier Filter bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 215
PIC18FXX8
REGISTER 19-23: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER,
HIGH BYTE REGISTERS
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
bit 7-0
EID15:EID8: Extended Identifier Filter bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-24: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER,
LOW BYTE REGISTERS
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
bit 7-0
EID7:EID0: Extended Identifier Filter bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-25: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK,
HIGH BYTE REGISTERS
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
bit 7-0
SID10:SID3: Standard Identifier Mask bits or Extended Identifier Mask bits EID28:EID21
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 216
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-26: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK,
LOW BYTE REGISTERS
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
U-0
—
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
bit 7-5
bit 4-2
bit 1-0
SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18
Unimplemented: Read as ‘0’
EID17:EID16: Extended Identifier Mask bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-27: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK,
HIGH BYTE REGISTERS
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
bit 7-0
EID15:EID8: Extended Identifier Mask bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 19-28: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK,
LOW BYTE REGISTERS
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
bit 7-0
EID7:EID0: Extended Identifier Mask bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 217
PIC18FXX8
19.2.4
CAN BAUD RATE REGISTERS
This subsection describes the CAN Baud Rate
registers.
REGISTER 19-29: BRGCON1: BAUD RATE CONTROL REGISTER 1
R/W-0
SJW1
R/W-0
SJW0
R/W-0
BRP5
R/W-0
BRP4
R/W-0
BRP3
R/W-0
BRP2
R/W-0
BRP1
R/W-0
BRP0
bit 7
bit 0
bit 7-6
bit 5-0
SJW1:SJW0: Synchronized Jump Width bits
11= Synchronization Jump Width Time = 4 x TQ
10= Synchronization Jump Width Time = 3 x TQ
01= Synchronization Jump Width Time = 2 x TQ
00= Synchronization Jump Width Time = 1 x TQ
BRP5:BRP0: Baud Rate Prescaler bits
111111= TQ = (2 x 64)/FOSC
111110= TQ = (2 x 63)/FOSC
:
:
000001= TQ = (2 x 2)/FOSC
000000= TQ = (2 x 1)/FOSC
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Note:
This register is accessible in Configuration mode only.
DS41159E-page 218
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-30: BRGCON2: BAUD RATE CONTROL REGISTER 2
R/W-0
SEG2PHTS
bit 7
R/W-0
SAM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0
bit 0
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1= Freely programmable
0= Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN bus Line bit
1= Bus line is sampled three times prior to the sample point
0= Bus line is sampled once at the sample point
bit 5-3
SEG1PH2:SEG1PH0: Phase Segment 1 bits
111= Phase Segment 1 Time = 8 x TQ
110= Phase Segment 1 Time = 7 x TQ
101= Phase Segment 1 Time = 6 x TQ
100= Phase Segment 1 Time = 5 x TQ
011= Phase Segment 1 Time = 4 x TQ
010= Phase Segment 1 Time = 3 x TQ
001= Phase Segment 1 Time = 2 x TQ
000= Phase Segment 1 Time = 1 x TQ
bit 2-0
PRSEG2:PRSEG0: Propagation Time Select bits
111= Propagation Time = 8 x TQ
110= Propagation Time = 7 x TQ
101= Propagation Time = 6 x TQ
100= Propagation Time = 5 x TQ
011= Propagation Time = 4 x TQ
010= Propagation Time = 3 x TQ
001= Propagation Time = 2 x TQ
000= Propagation Time = 1 x TQ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
This register is accessible in Configuration mode only.
© 2006 Microchip Technology Inc.
DS41159E-page 219
PIC18FXX8
REGISTER 19-31: BRGCON3: BAUD RATE CONTROL REGISTER 3
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WAKFIL
SEG2PH2(1) SEG2PH1(1) SEG2PH0(1)
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
WAKFIL: Selects CAN bus Line Filter for Wake-up bit
1= Use CAN bus line filter for wake-up
0= CAN bus line filter is not used for wake-up
bit 5-3
bit 2-0
Unimplemented: Read as ‘0’
SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1)
111= Phase Segment 2 Time = 8 x TQ
110= Phase Segment 2 Time = 7 x TQ
101= Phase Segment 2 Time = 6 x TQ
100= Phase Segment 2 Time = 5 x TQ
011= Phase Segment 2 Time = 4 x TQ
010= Phase Segment 2 Time = 3 x TQ
001= Phase Segment 2 Time = 2 x TQ
000= Phase Segment 2 Time = 1 x TQ
Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is clear.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 220
© 2006 Microchip Technology Inc.
PIC18FXX8
19.2.5
CAN MODULE I/O CONTROL
REGISTER
This register controls the operation of the CAN module’s
I/O pins in relation to the rest of the microcontroller.
REGISTER 19-32: CIOCON: CAN I/O CONTROL REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
ENDRHI CANCAP
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
ENDRHI: Enable Drive High bit
1= CANTX pin will drive VDD when recessive
0= CANTX pin will tri-state when recessive
bit 4
CANCAP: CAN Message Receive Capture Enable bit
1= Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1
0= Disable CAN capture, RC2/CCP1 input to CCP1 module
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 221
PIC18FXX8
19.2.6
CAN INTERRUPT REGISTERS
The registers in this section are the same as described
in Section 8.0 “Interrupts”. They are duplicated here
for convenience.
REGISTER 19-33: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
IRXIF
R/W-0
R/W-0
ERRIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIF: CAN Invalid Received Message Interrupt Flag bit
1= An invalid message has occurred on the CAN bus
0= No invalid message on CAN bus
WAKIF: CAN bus Activity Wake-up Interrupt Flag bit
1= Activity on CAN bus has occurred
0= No activity on CAN bus
ERRIF: CAN bus Error Interrupt Flag bit
1= An error has occurred in the CAN module (multiple sources)
0= No CAN module errors
TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit
1= Transmit Buffer 2 has completed transmission of a message and may be reloaded
0= Transmit Buffer 2 has not completed transmission of a message
TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit
1= Transmit Buffer 1 has completed transmission of a message and may be reloaded
0= Transmit Buffer 1 has not completed transmission of a message
TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit
1= Transmit Buffer 0 has completed transmission of a message and may be reloaded
0= Transmit Buffer 0 has not completed transmission of a message
RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit
1= Receive Buffer 1 has received a new message
0= Receive Buffer 1 has not received a new message
RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit
1= Receive Buffer 0 has received a new message
0= Receive Buffer 0 has not received a new message
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 222
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 19-34: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
IRXIE
R/W-0
R/W-0
ERRIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIE: CAN Invalid Received Message Interrupt Enable bit
1= Enable invalid message received interrupt
0= Disable invalid message received interrupt
WAKIE: CAN bus Activity Wake-up Interrupt Enable bit
1= Enable bus activity wake-up interrupt
0= Disable bus activity wake-up interrupt
ERRIE: CAN bus Error Interrupt Enable bit
1= Enable CAN bus error interrupt
0= Disable CAN bus error interrupt
TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit
1= Enable Transmit Buffer 2 interrupt
0= Disable Transmit Buffer 2 interrupt
TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit
1= Enable Transmit Buffer 1 interrupt
0= Disable Transmit Buffer 1 interrupt
TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit
1= Enable Transmit Buffer 0 interrupt
0= Disable Transmit Buffer 0 interrupt
RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit
1= Enable Receive Buffer 1 interrupt
0= Disable Receive Buffer 1 interrupt
RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit
1= Enable Receive Buffer 0 interrupt
0= Disable Receive Buffer 0 interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 223
PIC18FXX8
REGISTER 19-35: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
IRXIP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WAKIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IRXIP: CAN Invalid Received Message Interrupt Priority bit
1= High priority
0= Low priority
WAKIP: CAN bus Activity Wake-up Interrupt Priority bit
1= High priority
0= Low priority
ERRIP: CAN bus Error Interrupt Priority bit
1= High priority
0= Low priority
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1= High priority
0= Low priority
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41159E-page 224
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 19-1: CAN CONTROLLER REGISTER MAP
Address
Name
Address
Name
Address
Name
Address
Name
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
—
—
—
—
—
—
—
—
—
F5Fh
—
F3Fh
—
F1Fh RXM1EIDL
F1Eh RXM1EIDH
F1Dh RXM1SIDL
F1Ch RXM1SIDH
F1Bh RXM0EIDL
F1Ah RXM0EIDH
F19h RXM0SIDL
F18h RXM0SIDH
F5Eh CANSTATRO1(2)
F3Eh CANSTATRO3(2)
F5Dh
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
F4Fh
RXB1D7
RXB1D6
RXB1D5
RXB1D4
RXB1D3
RXB1D2
RXB1D1
RXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
—
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
F2Fh
TXB1D7
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D0
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
—
F17h
F16h
F15h
F14h
F13h
F12h
F11h
F10h
F0Fh
F0Eh
F0Dh
F0Ch
F0Bh
F0Ah
F09h
F08h
F07h
F06h
F05h
F04h
F03h
F02h
F01h
F00h
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
RXF3SIDL
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
RXF1EIDL
RXF1EIDH
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
F76h TXERRCNT
F75h RXERRCNT
F74h COMSTAT
F73h
CIOCON
F72h BRGCON3
F71h BRGCON2
F70h BRGCON1
F6Fh CANCON
F6Eh CANSTAT
F4Eh CANSTATRO2(2)
F2Eh CANSTATRO4(2)
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
RXB0D7
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
TXB0D7
TXB0D6
F2Dh
F2Ch
F2Bh
F2Ah
F29h
F28h
F27h
F26h
F25h
F24h
F23h
F22h
F21h
F20h
TXB2D7
TXB2D6
TXB0D5
TXB2D5
TXB0D4
TXB2D4
TXB0D3
TXB2D3
TXB0D2
TXB2D2
TXB0D1
TXB2D1
TXB0D0
TXB2D0
F65h RXB0DLC
F64h RXB0EIDL
F63h RXB0EIDH
F62h RXB0SIDL
F61h RXB0SIDH
F60h RXB0CON
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.
2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the CANSTAT register due to the Microchip Header file requirement.
© 2006 Microchip Technology Inc.
DS41159E-page 225
PIC18FXX8
19.3.2
DISABLE MODE
19.3 CAN Modes of Operation
In Disable mode, the module will not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity, however, any pending interrupts will
remain and the error counters will retain their value.
The PIC18FXX8 has six main modes of operation:
• Configuration mode
• Disable mode
• Normal Operation mode
• Listen Only mode
• Loopback mode
If REQOP<2:0> is set to ‘001’, the module will enter the
Module Disable mode. This mode is similar to disabling
other peripheral modules by turning off the module
enables. This causes the module internal clock to stop
unless the module is active (i.e., receiving or transmit-
ting a message). If the module is active, the module will
wait for 11 recessive bits on the CAN bus, detect that
condition as an IDLE bus, then accept the module
disable command. OPMODE<2:0> = 001 indicates
whether the module successfully went into Module
Disable mode.
• Error Recognition mode
All modes, except Error Recognition, are requested by
setting the REQOP bits (CANCON<7:5>); Error Recog-
nition is requested through the RXM bits of the Receive
Buffer register(s). Entry into a mode is Acknowledged
by monitoring the OPMODE bits.
When changing modes, the mode will not actually
change until all pending message transmissions are
complete. Because of this, the user must verify that the
device has actually changed into the requested mode
before fUrther Operations Are Executed.
The WAKIF interrupt is the only module interrupt that is
still active in the Module Disable mode. If the WAKIE is
set, the processor will receive an interrupt whenever
the CAN bus detects a dominant state, as occurs with
a SOF. If the processor receives an interrupt while it is
sleeping, more than one message may get lost. User
firmware must anticipate this condition and request
retransmission. If the processor is running while it
receives an interrupt, only the first message may get
lost.
19.3.1
CONFIGURATION MODE
The CAN module has to be initialized before the
activation. This is only possible if the module is in the
Configuration mode. The Configuration mode is
requested by setting the REQOP2 bit. Only when the
OPMODE2 status bit has a high level can the initializa-
tion be performed. Afterwards, the Configuration
registers, the Acceptance Mask registers and the
Acceptance Filter registers can be written. The module
is activated by setting the REQOP control bits to zero.
The I/O pins will revert to normal I/O function when the
module is in the Module Disable mode.
19.3.3
NORMAL MODE
This is the standard operating mode of the PIC18FXX8.
In this mode, the device actively monitors all bus
messages and generates Acknowledge bits, error
frames, etc. This is also the only mode in which the
PIC18FXX8 will transmit messages over the CAN bus.
The module will protect the user from accidentally
violating the CAN protocol through programming
errors. All registers which control the configuration of
the module can not be modified while the module is on-
line. The CAN module will not be allowed to enter the
Configuration mode while a transmission is taking
place. The CONFIG bit serves as a lock to protect the
following registers.
19.3.4
LISTEN ONLY MODE
Listen Only mode provides
a
means for the
PIC18FXX8 to receive all messages, including
messages with errors. This mode can be used for bus
monitor applications or for detecting the baud rate in
‘hot plugging’ situations. For auto-baud detection, it is
necessary that there are at least two other nodes which
are communicating with each other. The baud rate can
be detected empirically by testing different values until
valid messages are received. The Listen Only mode is
a silent mode, meaning no messages will be trans-
mitted while in this state, including error flags or
Acknowledge signals. The filters and masks can be
used to allow only particular messages to be loaded
into the receive registers, or the filter masks can be set
to all zeros to allow a message with any identifier to
pass. The error counters are reset and deactivated in
this state. The Listen Only mode is activated by setting
the mode request bits in the CANCON register.
• Configuration registers
• Bus Timing registers
• Identifier Acceptance Filter registers
• Identifier Acceptance Mask registers
In the Configuration mode, the module will not transmit
or receive. The error counters are cleared and the
interrupt flags remain unchanged. The programmer will
have access to Configuration registers that are access
restricted in other modes.
DS41159E-page 226
© 2006 Microchip Technology Inc.
PIC18FXX8
19.3.5
LOOPBACK MODE
19.4.2
TRANSMIT PRIORITY
This mode will allow internal transmission of messages
from the transmit buffers to the receive buffers without
actually transmitting messages on the CAN bus. This
mode can be used in system development and testing.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself, just as if they
were coming from another node. The Loopback mode
is a silent mode, meaning no messages will be trans-
mitted while in this state, including error flags or
Acknowledge signals. The TXCAN pin will revert to port
I/O while the device is in this mode. The filters and
masks can be used to allow only particular messages
to be loaded into the receive registers. The masks can
be set to all zeros to provide a mode that accepts all
messages. The Loopback mode is activated by setting
the mode request bits in the CANCON register.
Transmit priority is
a
prioritization within the
PIC18FXX8 of the pending transmittable messages.
This is independent from and not related to any prioriti-
zation implicit in the message arbitration scheme built
into the CAN protocol. Prior to sending the SOF, the
priority of all buffers that are queued for transmission is
compared. The transmit buffer with the highest priority
will be sent first. If two buffers have the same priority
setting, the buffer with the highest buffer number will be
sent first. There are four levels of transmit priority. If
TXP bits for a particular message buffer are set to ‘11’,
that buffer has the highest possible priority. If TXP bits
for a particular message buffer are ‘00’, that buffer has
the lowest possible priority.
FIGURE 19-2:
TRANSMIT BUFFER
BLOCK DIAGRAM
19.3.6
ERROR RECOGNITION MODE
The module can be set to ignore all errors and receive
all message. The Error Recognition mode is activated
by setting the RXM<1:0> bits in the RXBnCON
registers to ‘11’. In this mode, all messages, valid or
invalid, are received and copied to the receive buffer.
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
TXB0
MESSAGE
TXB1
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
19.4 CAN Message Transmission
MESSAGE
19.4.1
TRANSMIT BUFFERS
The PIC18FXX8 implements three transmit buffers
(Figure 19-2). Each of these buffers occupies 14 bytes
of SRAM and are mapped into the device memory
map.
TXB2
TXREQ
TXABT
TXLARB
TXERR
TXBUFF
Message
Request
MESSAGE
Message
Queue
Control
For the MCU to have write access to the message
buffer, the TXREQ bit must be clear, indicating that the
message buffer is clear of any pending message to be
transmitted. At a minimum, the TXBnSIDH, TXBnSIDL
and TXBnDLC registers must be loaded. If data bytes
are present in the message, the TXBnDm registers
must also be loaded. If the message is to use extended
identifiers, the TXBnEIDm registers must also be
loaded and the EXIDE bit set.
Transmit Byte Sequencer
Prior to sending the message, the MCU must initialize
the TXInE bit to enable or disable the generation of an
interrupt when the message is sent. The MCU must
also initialize the TXP priority bits (see Section 19.4.2
“Transmit Priority”).
© 2006 Microchip Technology Inc.
DS41159E-page 227
PIC18FXX8
19.4.3
INITIATING TRANSMISSION
19.4.4
ABORTING TRANSMISSION
To initiate message transmission, the TXREQ bit must
be set for each buffer to be transmitted. When TXREQ
is set, the TXABT, TXLARB and TXERR bits will be
cleared.
The MCU can request to abort a message by clearing
the TXREQ bit associated with the corresponding
message buffer (TXBnCON<3>). Setting the ABAT bit
(CANCON<4>) will request an abort of all pending
messages. If the message has not yet started transmis-
sion, or if the message started but is interrupted by loss
of arbitration or an error, the abort will be processed.
The abort is indicated when the module sets the ABT
bits for the corresponding buffer (TXBnCON<6>). If the
message has started to transmit, it will attempt to
transmit the current message fully. If the current
message is transmitted fully and is not lost to arbitration
or an error, the ABT bit will not be set because the
message was transmitted successfully. Likewise, if a
message is being transmitted during an abort request
and the message is lost to arbitration or an error, the
message will not be retransmitted and the ABT bit will
be set, indicating that the message was successfully
aborted.
Setting the TXREQ bit does not initiate a message
transmission; it merely flags a message buffer as ready
for transmission. Transmission will start when the
device detects that the bus is available. The device will
then begin transmission of the highest priority message
that is ready.
When the transmission has completed successfully,
the TXREQ bit will be cleared, the TXBnIF bit will be set
and an interrupt will be generated if the TXBnIE bit is
set.
If the message transmission fails, the TXREQ will
remain set, indicating that the message is still pending
for transmission and one of the following condition flags
will be set. If the message started to transmit but
encountered an error condition, the TXERR and the
IRXIF bits will be set and an interrupt will be generated.
If the message lost arbitration, the TXLARB bit will be
set.
DS41159E-page 228
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 19-3:
INTERNAL TRANSMIT MESSAGE FLOWCHART
Start
The message transmission sequence begins when
the device determines that the TXREQ for any of the
transmit registers has been set.
Are any
TXREQ
bits = 1?
No
Clearing the TXREQ bit while it is set, or setting
the ABAT bit before the message has started
transmission, will abort the message.
Yes
Clear: TXABT, TXLARB
and TXERR
No
Is
Yes
Is CAN bus
Available to Start
Transmission?
No
TXREQ = 0
ABAT = 1?
Yes
Examine TXPRI <1:0> to
Determine Highest Priority Message
Begin Transmission (SOF)
Was
No
Set
TXERR = 1
Message Transmitted
Successfully?
Yes
Set TXREQ = 0
Is
Yes
Arbitration Lost During
Transmission
TXLARB = 1?
Yes
Is
Generate
Interrupt
TXIE = 1?
A message can also be
No
aborted if
a message
error or lost arbitration
condition occurred during
transmission.
No
Is
Yes
TXREQ = 0
or TXABT = 1?
Set
TXBUFE = 1
No
The TXIE bit determines if an inter-
rupt should be generated when a
message is successfully transmitted.
Abort Transmission:
Set TXABT = 1
END
© 2006 Microchip Technology Inc.
DS41159E-page 229
PIC18FXX8
The RXM bits set special Receive modes. Normally,
these bits are set to ‘00’ to enable reception of all valid
messages as determined by the appropriate accep-
tance filters. In this case, the determination of whether
or not to receive standard or extended messages is
determined by the EXIDE bit in the Acceptance Filter
register. If the RXM bits are set to ‘01’ or ‘10’, the
receiver will accept only messages with standard or
extended identifiers, respectively. If an acceptance
filter has the EXIDE bit set, such that it does not corre-
spond with the RXM mode, that acceptance filter is
rendered useless. These two modes of RXM bits can
be used in systems where it is known that only standard
or extended messages will be on the bus. If the RXM
bits are set to ‘11’, the buffer will receive all messages
regardless of the values of the acceptance filters. Also,
if a message has an error before the end of frame, that
portion of the message assembled in the MAB before
the error frame will be loaded into the buffer. This mode
has some value in debugging a CAN system and would
not be used in an actual system environment.
19.5 Message Reception
19.5.1
RECEIVE MESSAGE BUFFERING
The PIC18FXX8 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB) which acts
as a third receive buffer (see Figure 19-4).
19.5.2
RECEIVE BUFFERS
Of the three receive buffers, the MAB is always commit-
ted to receiving the next message from the bus. The
remaining two receive buffers are called RXB0 and
RXB1 and can receive a complete message from the
protocol engine. The MCU can access one buffer while
the other buffer is available for message reception or
holding a previously received message.
The MAB assembles all messages received. These
messages will be transferred to the RXBn buffers only
if the acceptance filter criteria are met.
Note:
The entire contents of the MAB are moved
into the receive buffer once a message is
accepted. This means that regardless of
the type of identifier (standard or
extended) and the number of data bytes
received, the entire receive buffer is over-
written with the MAB contents. Therefore,
the contents of all registers in the buffer
must be assumed to have been modified
when any message is received.
19.5.4
TIME-STAMPING
The CAN module can be programmed to generate a
time-stamp for every message that is received. When
enabled, the module generates a capture signal for
CCP1 which in turns captures the value of either
Timer1 or Timer3. This value can be used as the
message time-stamp.
To use the time-stamp capability, the CANCAP bit
(CIOCAN<4>) must be set. This replaces the capture
input for CCP1 with the signal generated from the CAN
module. In addition, CCP1CON<3:0> must be set to
‘0011’ to enable the CCP special event trigger for CAN
events.
When a message is moved into either of the receive
buffers, the appropriate RXBnIF bit is set. This bit must
be cleared by the MCU when it has completed process-
ing the message in the buffer in order to allow a new
message to be received into the buffer. This bit
provides a positive lockout to ensure that the MCU has
finished with the message before the PIC18FXX8
attempts to load a new message into the receive buffer.
If the RXBnIE bit is set, an interrupt will be generated to
indicate that a valid message has been received.
FIGURE 19-4:
RECEIVE BUFFER BLOCK
DIAGRAM
Accept
Acceptance Mask
RXM1
19.5.3
RECEIVE PRIORITY
Acceptance Filter
RXM2
RXB0 is the higher priority buffer and has two message
acceptance filters associated with it. RXB1 is the lower
priority buffer and has four acceptance filters associ-
ated with it. The lower number of acceptance filters
makes the match on RXB0 more restrictive and implies
a higher priority for that buffer. Additionally, the
RXB0CON register can be configured such if RXB0
contains a valid message and another valid message is
received, an overflow error will not occur and the new
message will be moved into RXB1 regardless of the
acceptance criteria of RXB1. There are also two
programmable acceptance filter masks available, one
for each receive buffer (see Section 19.6 “Message
Acceptance Filters and Masks”).
Accept
Acceptance Mask
Acceptance Filter
RXF3
RXM0
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF5
Acceptance Filter
RXF1
RXB0
RXB1
Data and Data and
Identifier
Identifier
Identifier
Identifier
When a message is received, bits <3:0> of the
RXBnCON register will indicate the acceptance filter
number that enabled reception and whether the
received message is a remote transfer request.
Message Assembly Buffer
DS41159E-page 230
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 19-5:
INTERNAL MESSAGE RECEPTION FLOWCHART
Start
Detect
No
Start of
Message?
Yes
Begin Loading Message into
Message Assembly Buffer (MAB)
Valid
Message
Received?
Generate
Error
Frame
No
Yes
Yes, meets criteria
for RXB1
Yes, meets criteria
for RXBO
Message
Identifier meets a
Filter Criteria?
No
Go to Start
The RXFUL bit determines if the
receive register is empty and able
to accept a new message.
The RXB0DBEN bit determines if
RXB0 can rollover into RXB1 if it is
full.
Is
No
Is
Yes
RXFUL = 0?
RX0DBEN = 1?
Yes
No
Is
No
Generate Overrun Error:
Set RXB1OVFL
Generate Overrun Error:
Set RXB0OVFL
Move Message into RXB0
RXFUL = 0?
Set RXRDY = 1
Yes
Move Message into RXB1
No
Is
Set FILHIT <0>
according to which Filter
Criteria was met
ERRIE = 1?
Set RXRDY = 1
Yes
Go to Start
Set FILHIT <2:0>
according to which Filter
Criteria was met
Yes
Is
Is
Yes
Generate
Interrupt
RXIE = 1?
RXIE = 1?
No
No
Set CANSTAT <3:0> according
to which Receive Buffer the
Message was loaded into
© 2006 Microchip Technology Inc.
DS41159E-page 231
PIC18FXX8
For RXB1, the RXB1CON register contains the
FILHIT<2:0> bits. They are coded as follows:
19.6 Message Acceptance Filters
and Masks
• 101= Acceptance Filter 5 (RXF5)
• 100= Acceptance Filter 4 (RXF4)
• 011= Acceptance Filter 3 (RXF3)
• 010= Acceptance Filter 2 (RXF2)
• 001= Acceptance Filter 1 (RXF1)
• 000= Acceptance Filter 0 (RXF0)
The message acceptance filters and masks are used to
determine if a message in the message assembly
buffer should be loaded into either of the receive buff-
ers. Once a valid message has been received into the
MAB, the identifier fields of the message are compared
to the filter values. If there is a match, that message will
be loaded into the appropriate receive buffer. The filter
masks are used to determine which bits in the identifier
are examined with the filters. A truth table is shown
below in Table 19-2 that indicates how each bit in the
identifier is compared to the masks and filters to deter-
mine if a message should be loaded into a receive
buffer. The mask essentially determines which bits to
apply the acceptance filters to. If any mask bit is set to
a zero, then that bit will automatically be accepted
regardless of the filter bit.
Note:
‘000’ and ‘001’ can only occur if the
RXB0DBEN bit is set in the RXB0CON
register allowing RXB0 messages to
rollover into RXB1.
The coding of the RXB0DBEN bit enables these three
bits to be used similarly to the FILHIT bits and to
distinguish a hit on filter RXF0 and RXF1, in either
RXB0, or after a rollover into RXB1.
• 111= Acceptance Filter 1 (RXF1)
• 110= Acceptance Filter 0 (RXF0)
• 001= Acceptance Filter 1 (RXF1)
• 000= Acceptance Filter 0
TABLE 19-2: FILTER/MASK TRUTH TABLE
Message
Identifier
bit n001
Accept or
Reject
bit n
Mask
bit n
Filter bit n
If the RXB0DBEN bit is clear, there are six codes
corresponding to the six filters. If the RXB0DBEN bit is
set, there are six codes corresponding to the six filters
plus two additional codes corresponding to RXF0 and
RXF1 filters that rollover into RXB1.
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Accept
Accept
Reject
Reject
Accept
If more than one acceptance filter matches, the FILHIT
bits will encode the binary value of the lowest
numbered filter that matched. In other words, if filter
RXF2 and filter RXF4 match, FILHIT will be loaded with
the value for RXF2. This essentially prioritizes the
acceptance filters with a lower number filter having
higher priority. Messages are compared to filters in
ascending order of filter number.
Legend: x= don’t care
As shown in the receive buffer block diagram
(Figure 19-4), acceptance filters RXF0 and RXF1 and
filter mask RXM0 are associated with RXB0. Filters
RXF2, RXF3, RXF4 and RXF5 and mask RXM1 are
associated with RXB1. When a filter matches and a
message is loaded into the receive buffer, the filter
number that enabled the message reception is loaded
into the FILHIT bit(s).
The mask and filter registers can only be modified
when the PIC18FXX8 is in Configuration mode. The
mask and filter registers cannot be read outside of
Configuration mode. When outside of Configuration
mode, all mask and filter registers will be read as ‘0’.
FIGURE 19-6:
MESSAGE ACCEPTANCE MASK AND FILTER OPERATION
Acceptance Filter Register
Acceptance Mask Register
RXFn
RXMn
0
0
RXMn
RxRqst
1
RXFn
1
RXFn
RXMn
n
n
Message Assembly Buffer
Identifier
DS41159E-page 232
© 2006 Microchip Technology Inc.
PIC18FXX8
The Nominal Bit Time is defined as:
19.7 Baud Rate Setting
TBIT = 1/Nominal Bit Rate
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Return-
to-Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitters clock.
The nominal bit time can be thought of as being divided
into separate, non-overlapping time segments. These
segments (Figure 19-7) include:
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The time segments (and thus, the nominal bit time) are,
in turn, made up of integer units of time called time
quanta or TQ (see Figure 19-7). By definition, the
nominal bit time is programmable from a minimum of
8 TQ to a maximum of 25 TQ. Also, by definition, the
minimum nominal bit time is 1 μs corresponding to a
maximum 1 Mb/s rate. The actual duration is given by
the relationship:
The bit timing of the PIC18FXX8 is implemented using
a DPLL that is configured to synchronize to the
incoming data and provides the nominal timing for the
transmitted data. The DPLL breaks each bit time into
multiple segments made up of minimal periods of time
called the Time Quanta (TQ).
Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg +
Phase_Seg1 + Phase_Seg2)
The time quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler, with integer values from 1 to 64, in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
TQ (μs) = (2 * (BRP + 1))/FOSC (MHz)
or
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
prescaler and number of time quanta in each segment.
TQ (μs) = (2 * (BRP + 1)) * TOSC (μs)
where FOSC is the clock frequency, TOSC is the
corresponding oscillator period and BRP is an integer
(0 through 63) represented by the binary values of
BRGCON1<5:0>.
The Nominal Bit Rate is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
FIGURE 19-7:
BIT TIME PARTITIONING
Input
Signal
Propagation
Segment
Phase
Segment 1
Phase
Segment 2
Sync
Segment
Bit
Time
Intervals
TQ
Sample Point
Nominal Bit Time
© 2006 Microchip Technology Inc.
DS41159E-page 233
PIC18FXX8
19.7.1
TIME QUANTA
19.7.2
SYNCHRONIZATION SEGMENT
As already mentioned, the time quanta is a fixed unit
derived from the oscillator period and baud rate
prescaler. Its relationship to TBIT and the nominal bit
rate is shown in Example 19-2.
This part of the bit time is used to synchronize the
various CAN nodes on the bus. The edge of the input
signal is expected to occur during the sync segment.
The duration is 1 TQ.
19.7.3
PROPAGATION SEGMENT
EXAMPLE 19-2:
CALCULATING TQ,
NOMINAL BIT RATE AND
NOMINAL BIT TIME
This part of the bit time is used to compensate for
physical delay times within the network. These delay
times consist of the signal propagation time on the bus
line and the internal delay time of the nodes. The length
of the Propagation Segment can be programmed from
1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits.
TQ (μs) = (2 * (BRP + 1))/FOSC (MHz)
TBIT (μs) = TQ (μs) * number of TQ per bit interval
Nominal Bit Rate (bits/s) = 1/TBIT
19.7.4
PHASE BUFFER SEGMENTS
CASE 1:
The phase buffer segments are used to optimally
locate the sampling point of the received bit within the
nominal bit time. The sampling point occurs between
Phase Segment 1 and Phase Segment 2. These
segments can be lengthened or shortened by the
resynchronization process. The end of Phase Segment
1 determines the sampling point within a bit time.
Phase Segment 1 is programmable from 1 TQ to 8 TQ
in duration. Phase Segment 2 provides delay before
the next transmitted data transition and is also
programmable from 1 TQ to 8 TQ in duration. However,
due to IPT requirements, the actual minimum length of
Phase Segment 2 is 2 TQ or it may be defined to be
equal to the greater of Phase Segment 1 or the
Information Processing Time (IPT).
For FOSC = 16 MHz, BRP<5:0> = 00h and
Nominal Bit Time = 8 TQ:
TQ = (2 * 1)/16 = 0.125 μs (125 ns)
TBIT = 8 * 0.125 = 1 μs (10-6s)
Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s)
CASE 2:
For FOSC = 20 MHz, BRP<5:0> = 01h and
Nominal Bit Time = 8 TQ:
TQ = (2 * 2)/20 = 0.2 μs (200 ns)
TBIT = 8 * 0.2 = 1.6 μs (1.6 * 10-6s)
Nominal Bit Rate = 1/1.6 * 10-6s = 625,000 bits/s
19.7.5
SAMPLE POINT
(625 Kb/s)
The sample point is the point of time at which the bus
level is read and the value of the received bit is deter-
mined. The sampling point occurs at the end of Phase
Segment 1. If the bit timing is slow and contains many
TQ, it is possible to specify multiple sampling of the bus
line at the sample point. The value of the received bit is
determined to be the value of the majority decision of
three values. The three samples are taken at the sam-
ple point and twice before, with a time of TQ/2 between
each sample.
CASE 3:
For FOSC = 25 MHz, BRP<5:0> = 3Fh and
Nominal Bit Time = 25 TQ:
TQ = (2 * 64)/25 = 5.12 μs
TBIT = 25 * 5.12 = 128 μs (1.28 * 10-4s)
Nominal Bit Rate = 1/1.28 * 10-4
=
7813 bits/s
(7.8 Kb/s)
19.7.6
INFORMATION PROCESSING TIME
The frequencies of the oscillators in the different nodes
must be coordinated in order to provide a system wide
specified nominal bit time. This means that all oscilla-
tors must have a TOSC that is an integral divisor of TQ.
It should also be noted that although the number of TQ
is programmable from 4 to 25, the usable minimum is
8 TQ. A bit time of less than 8 TQ in length is not
ensured to operate correctly.
The Information Processing Time (IPT) is the time
segment, starting at the sample point, that is reserved
for calculation of the subsequent bit level. The CAN
specification defines this time to be less than or equal
to 2 TQ. The PIC18FXX8 defines this time to be 2 TQ.
Thus, Phase Segment 2 must be at least 2 TQ long.
DS41159E-page 234
© 2006 Microchip Technology Inc.
PIC18FXX8
The phase error of an edge is given by the position of
the edge relative to Sync_Seg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
19.8 Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
• e = 0 if the edge lies within Sync_Seg.
• e > 0 if the edge lies before the sample point.
• e < 0 if the edge lies after the sample point of the
previous bit.
If the magnitude of the phase error is less than or equal
to the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
Phase Segment
1 and Phase Segment 2, as
necessary. There are two mechanisms used for
synchronization.
If the magnitude of the phase error is larger than the
synchronization jump width and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the synchronization jump width.
19.8.1
HARD SYNCHRONIZATION
Hard synchronization is only done when there is a reces-
sive to dominant edge during a bus Idle condition, indi-
cating the start of
a
message. After hard
If the magnitude of the phase error is larger than the
resynchronization jump width and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the synchronization jump width.
synchronization, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge which
has occurred to lie within the synchronization segment of
the restarted bit time. Due to the rules of synchroniza-
tion, if a hard synchronization occurs, there will not be a
resynchronization within that bit time.
19.8.3
SYNCHRONIZATION RULES
• Only one synchronization within one bit time is
allowed.
19.8.2
RESYNCHRONIZATION
As a result of resynchronization, Phase Segment 1
may be lengthened or Phase Segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure 19-8) or subtracted from Phase Segment 2 (see
Figure 19-9). The SJW is programmable between 1 TQ
and 4 TQ.
• An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
• All other recessive to dominant edges, fulfilling
rules 1 and 2, will be used for resynchronization
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
Clocking information will only be derived from reces-
sive to dominant transitions. The property, that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
FIGURE 19-8:
LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)
Input
Signal
Bit
Time
Segments
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sync
≤ SJW
TQ
Sample Point
Nominal Bit Length
Actual Bit Length
© 2006 Microchip Technology Inc.
DS41159E-page 235
PIC18FXX8
FIGURE 19-9:
SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sync
≤ SJW
TQ
Sample Point
Actual Bit Length
Nominal Bit Length
19.11.1 BRGCON1
19.9 Programming Time Segments
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of multiples of TQ.
Some requirements for programming of the time
segments:
• Prop Seg + Phase Seg 1 ≥ Phase Seg 2
• Phase Seg 2 ≥ Sync Jump Width
19.11.2 BRGCON2
For example, assume that a 125 kHz CAN baud rate is
desired using 20 MHz for FOSC. With a TOSC of 50 ns,
a baud rate prescaler value of 04h gives a TQ of 500 ns.
To obtain a nominal bit rate of 125 kHz, the nominal bit
time must be 8 μs or 16 TQ.
The PRSEG bits set the length of the Propagation Seg-
ment in terms of TQ. The SEG1PH bits set the length of
Phase Segment 1 in TQ. The SAM bit controls how
many times the RXCAN pin is sampled. Setting this bit
to a ‘1’ causes the bus to be sampled three times; twice
at TQ/2 before the sample point and once at the normal
sample point (which is at the end of Phase Segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of Phase Segment 2 is determined. If this bit is
set to a ‘1’, then the length of Phase Segment 2 is
determined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of Phase
Segment 2 is the greater of Phase Segment 1 and the
information processing time (which is fixed at 2 TQ for
the PIC18FXX8).
Using 1 TQ for the Sync Segment, 2 TQ for the Propa-
gation Segment and 7 TQ for Phase Segment 1 would
place the sample point at 10 TQ after the transition.
This leaves 6 TQ for Phase Segment 2.
By the rules above, the Sync Jump Width could be the
maximum of 4 TQ. However, normally a large SJW is
only necessary when the clock generation of the differ-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. Typically, an SJW of 1 is enough.
19.10 Oscillator Tolerance
As a rule of thumb, the bit timing requirements allow
ceramic resonators to be used in applications with
transmission rates of up to 125 Kbit/sec. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
19.11.3 BRGCON3
The PHSEG2<2:0> bits set the length (in TQ) of Phase
Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the
SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>
bits have no effect.
19.11 Bit Timing Configuration
Registers
The Configuration registers (BRGCON1, BRGCON2,
BRGCON3) control the bit timing for the CAN bus
interface. These registers can only be modified when
the PIC18FXX8 is in Configuration mode.
DS41159E-page 236
© 2006 Microchip Technology Inc.
PIC18FXX8
19.12.6 ERROR STATES
19.12 Error Detection
Detected errors are made public to all other nodes via
error frames. The transmission of the erroneous
message is aborted and the frame is repeated as soon
as possible. Furthermore, each CAN node is in one of
the three error states “error-active”, “error-passive” or
“bus-off” according to the value of the internal error
counters. The error-active state is the usual state,
where the bus node can transmit messages and
activate error frames (made of dominant bits) without
any restrictions. In the error-passive state, messages
and passive error frames (made of recessive bits) may
be transmitted. The bus-off state makes it temporarily
impossible for the station to participate in the bus
communication. During this state, messages can
neither be received nor transmitted.
The CAN protocol provides sophisticated error detection
mechanisms. The following errors can be detected.
19.12.1 CRC ERROR
With the Cyclic Redundancy Check (CRC), the
transmitter calculates special check bits for the bit
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC field. The receiving node also calculates the CRC
sequence using the same formula and performs a
comparison to the received sequence. If a mismatch is
detected, a CRC error has occurred and an error frame
is generated. The message is repeated.
19.12.2 ACKNOWLEDGE ERROR
In the Acknowledge field of a message, the transmitter
checks if the Acknowledge slot (which was sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An Acknowl-
edge Error has occurred; an error frame is generated
and the message will have to be repeated.
19.12.7 ERROR MODES AND ERROR
COUNTERS
The PIC18FXX8 contains two error counters: the
Receive Error Counter (RXERRCNT) and the Transmit
Error Counter (TXERRCNT). The values of both
counters can be read by the MCU. These counters are
incremented or decremented in accordance with the
CAN bus specification.
19.12.3 FORM ERROR
If a node detects a dominant bit in one of the four
segments, including end of frame, interframe space,
Acknowledge delimiter or CRC delimiter, then a Form
Error has occurred and an error frame is generated.
The message is repeated.
The PIC18FXX8 is error-active if both error counters
are below the error-passive limit of 128. It is error-
passive if at least one of the error counters equals or
exceeds 128. It goes to bus-off if the transmit error
counter equals or exceeds the bus-off limit of 256. The
device remains in this state until the bus-off recovery
sequence is received. The bus-off recovery sequence
consists of 128 occurrences of 11 consecutive
recessive bits (see Figure 19-10). Note that the CAN
module, after going bus-off, will recover back to error-
active without any intervention by the MCU if the bus
remains Idle for 128 x 11 bit times. If this is not desired,
the error Interrupt Service Routine should address this.
The current error mode of the CAN module can be read
by the MCU via the COMSTAT register.
19.12.4 BIT ERROR
A Bit Error occurs if a transmitter sends a dominant bit
and detects a recessive bit, or if it sends a recessive bit
and detects a dominant bit, when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the Acknowledge slot, no Bit Error is
generated because normal arbitration is occurring.
Additionally, there is an Error State Warning flag bit,
EWARN, which is set if at least one of the error
counters equals or exceeds the error warning limit of
96. EWARN is reset if both error counters are less than
the error warning limit.
19.12.5 STUFF BIT ERROR
If, between the start of frame and the CRC delimiter, six
consecutive bits with the same polarity are detected,
the bit stuffing rule has been violated. A Stuff Bit Error
occurs and an error frame is generated. The message
is repeated.
© 2006 Microchip Technology Inc.
DS41159E-page 237
PIC18FXX8
FIGURE 19-10:
ERROR MODES STATE DIAGRAM
Reset
Error-
Active
RXERRCNT < 127 or
TXERRCNT < 127
128 occurrences of
11 consecutive
“recessive” bits
RXERRCNT > 127 or
TXERRCNT > 127
Error-
Passive
TXERRCNT > 255
Bus-
Off
19.13.1 INTERRUPT CODE BITS
19.13 CAN Interrupts
The source of a pending interrupt is indicated in the
ICODE (Interrupt Code) bits of the CANSTAT register
(ICODE<2:0>). Interrupts are internally prioritized such
that the higher priority interrupts are assigned lower
ICODE values. Once the highest priority interrupt con-
dition has been cleared, the code for the next highest
priority interrupt that is pending (if any) will be reflected
by the ICODE bits (see Table 19-3, following page).
Note that only those interrupt sources that have their
associated CANINTE enable bit set will be reflected in
the ICODE bits.
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or
disabled. The CANINTF register contains interrupt
flags. The CANINTE register contains the enables for
the 8 main interrupts. A special set of read-only bits in
the CANSTAT register, the ICODE bits, can be used in
combination with a jump table for efficient handling of
interrupts.
All interrupts have one source, with the exception of the
error interrupt. Any of the error interrupt sources can set
the error interrupt flag. The source of the error interrupt
can be determined by reading the Communication
Status register, COMSTAT.
19.13.2 TRANSMIT INTERRUPT
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the TXBnIF bit to a ‘0’.
The interrupts can be broken up into two categories:
receive and transmit interrupts.
The receive related interrupts are:
• Receive Interrupts
• Wake-up Interrupt
• Receiver Overrun Interrupt
• Receiver Warning Interrupt
• Receiver Error-Passive Interrupt
19.13.3 RECEIVE INTERRUPT
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the EOF field. The RXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the RXBnIF bit to a ‘0’.
The transmit related interrupts are:
• Transmit Interrupts
• Transmitter Warning Interrupt
• Transmitter Error-Passive Interrupt
• Bus-Off Interrupt
DS41159E-page 238
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 19-3: VALUES FOR ICODE<2:0>
ICOD
19.13.6 ERROR INTERRUPT
When the error interrupt is enabled, an interrupt is
generated if an overflow condition occurs or if the error
state of transmitter or receiver has changed. The error
flags in COMSTAT will indicate one of the following
conditions.
Interrupt
Boolean Expression
<2:0>
ERR•WAK•TX0•TX1•TX2•RX0•
RX1
000
None
001
010
011
100
101
110
Error
TXB2
TXB1
TXB0
RXB1
RXB0
ERR
19.13.6.1 Receiver Overflow
An overflow condition occurs when the MAB has
assembled a valid received message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
COMSTAT.RXnOVFL bit will be set to indicate the
overflow condition. This bit must be cleared by the
MCU.
ERR•TX0•TX1•TX2
ERR•TX0•TX1
ERR•TX0
ERR•TX0•TX1•TX2•RX0•RX1
ERR•TX0•TX1•TX2•RX0
19.13.6.2 Receiver Warning
Wake on ERR•TX0•TX1•TX2•RX0•RX1•
Interrupt WAK
111
The receive error counter has reached the MCU
warning limit of 96.
Key:
ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE
TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE
TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE
TX2 = TXB2IF * TXB2IE
19.13.6.3 Transmitter Warning
The transmit error counter has reached the MCU
warning limit of 96.
19.13.6.4 Receiver Bus Passive
The receive error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
19.13.4 MESSAGE ERROR INTERRUPT
When an error occurs during transmission or reception
of a message, the message error flag IRXIF will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
19.13.6.5 Transmitter Bus Passive
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
19.13.5 BUS ACTIVITY WAKE-UP
INTERRUPT
19.13.6.6 Bus-Off
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
When the PIC18FXX8 is in Sleep mode and the bus
activity wake-up interrupt is enabled, an interrupt will be
generated and the WAKIF bit will be set when activity is
detected on the CAN bus. This interrupt causes the
PIC18FXX8 to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
19.13.7 INTERRUPT ACKNOWLEDGE
Interrupts are directly associated with one or more
status flags in the PIR register. Interrupts are pending
as long as one of the flags is set. Once an interrupt flag
is set by the device, the flag cannot be reset by the
microcontroller until the interrupt condition is removed.
© 2006 Microchip Technology Inc.
DS41159E-page 239
PIC18FXX8
NOTES:
DS41159E-page 240
© 2006 Microchip Technology Inc.
PIC18FXX8
The A/D module has four registers. These registers are:
20.0 COMPATIBLE 10-BIT ANALOG-
TO-DIGITAL CONVERTER (A/D)
MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The Analog-to-Digital (A/D) Converter module has five
inputs for the PIC18F2X8 devices and eight for the
PIC18F4X8 devices. This module has the ADCON0
and ADCON1 register definitions that are compatible
with the PICmicro® mid-range A/D module.
The ADCON0 register, shown in Register 20-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 20-2, configures
the functions of the port pins.
The A/D allows conversion of an analog input signal to
a corresponding 10-bit digital number.
REGISTER 20-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
—
R/W-0
ADON
ADCS1
ADCS0
GO/DONE
bit 7
bit 0
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
ADCON1
<ADCS2>
ADCON0
<ADCS1:ADCS0>
Clock Conversion
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
bit 5-3 CHS2:CHS0: Analog Channel Select bits
000= Channel 0 (AN0)
001= Channel 1 (AN1)
010= Channel 2 (AN2)
011= Channel 3 (AN3)
100= Channel 4 (AN4)
101= Channel 5 (AN5)(1)
110= Channel 6 (AN6)(1)
111= Channel 7 (AN7)(1)
Note 1: These channels are unimplemented on PIC18F2X8 (28-pin) devices. Do not select
any unimplemented channel.
bit 2
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0= A/D conversion not in progress
bit 1
bit 0
Unimplemented: Read as ‘0’
ADON: A/D On bit
1= A/D converter module is powered up
0= A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 241
PIC18FXX8
REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0
ADFM
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
ADCS2
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
bit 6
ADFM: A/D Result Format Select bit
1= Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0= Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
ADCON1
<ADCS2> <ADCS1:ADCS0>
ADCON0
Clock Conversion
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VREF+
VREF-
C/R
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VDD
AN3
VDD
AN3
VDD
AN3
—
VSS
VSS
VSS
VSS
VSS
VSS
—
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
VREF+
A
A
VREF+
A
A
D
VREF+
D
D
D
VREF+
A
VREF-
A
AN3
VDD
AN3
AN3
AN3
AN3
VDD
AN3
AN2
VSS
VSS
AN2
AN2
AN2
VSS
AN2
VREF+
VREF+
VREF+
VREF+
D
A
VREF-
VREF-
VREF-
D
VREF+
VREF-
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Note: Shaded cells indicate channels available only on PIC18F4X8 devices.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be analog inputs.
DS41159E-page 242
© 2006 Microchip Technology Inc.
PIC18FXX8
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS) or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF- pin.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a
voltage reference) or as a digital I/O.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The ADRESH and ADRESL registers contain the result
of the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0<2>) is cleared
and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 20-1.
The output of the sample and hold is the input into the
converter which generates the result via successive
approximation.
FIGURE 20-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
111
AN7(1)
110
AN6(1)
101
AN5(1)
100
AN4
VAIN
011
(Input Voltage)
AN3
010
AN2
10-bit
Converter
A/D
001
AN1
PCFG0
000
AN0
VDD
VREF+
VREF-
Reference
voltage
VSS
Note 1: Channels AN5 through AN7 are not available on PIC18F2X8 devices.
2: All I/O pins have diode protection to VDD and VSS.
© 2006 Microchip Technology Inc.
DS41159E-page 243
PIC18FXX8
The value that is in the ADRESH/ADRESL registers is
not modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
6. Read A/D Result registers (ADRESH/ADRESL);
clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 20.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. The following steps should be followed for
doing an A/D conversion:
20.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 20-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
FIGURE 20-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
5 pF
I LEAKAGE
500 nA
VAIN
CHOLD = 120 pF
VSS
VT = 0.6V
Legend:CPIN
= input capacitance
= threshold voltage
6V
5V
VDD 4V
VT
I LEAKAGE = leakage current at the pin due to
various junctions
3V
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5
6 7 8 9 10 11
Sampling Switch (kΩ)
DS41159E-page 244
© 2006 Microchip Technology Inc.
PIC18FXX8
To calculate the minimum acquisition time,
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 20-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assumptions:
• CHOLD
• Rs
=
=
120 pF
2.5 kΩ
• Conversion Error ≤ 1/2 LSb
• VDD
=
=
=
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
• Temperature
• VHOLD
EQUATION 20-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 20-2: A/D MINIMUM CHARGING TIME
VHOLD
or
=
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))
)
Tc
=
-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 20-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ
TC
=
=
2 μs + TC + [(Temp – 25°C)(0.05 μs/°C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 μs (-7.6241)
9.61 μs
TACQ
=
2 μs + 9.61 μs + [(50°C – 25°C)(0.05 μs/°C)]
11.61 μs + 1.25 μs
12.86 μs
Note:
When using external voltage references with the A/D converter, the source impedance of the external
voltage references must be less than 20Ω to obtain the specified A/D resolution. Higher reference source
impedances will increase both offset and gain errors. Resistive voltage dividers will not provide a sufficiently
low source impedance.
To maintain the best possible performance in A/D conversions, external VREF inputs should be buffered with
an operational amplifier or other low output impedance circuit.
© 2006 Microchip Technology Inc.
DS41159E-page 245
PIC18FXX8
20.2 Selecting the A/D Conversion
Clock
20.3 Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. The seven possible options for TAD are:
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
• 2 TOSC
• 4 TOSC
• 8 TOSC
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC oscillator.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 μs.
2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to
consume current that is out of the
device’s specification.
Table 20-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency
AD Clock Source (TAD)
Operation ADCS2:ADCS0
000
20 MHz
100 ns(2)
200 ns(2)
400 ns(2)
800 ns(2)
1.6 μs
5 MHz
400 ns(2)
800 ns(2)
1.6 μs
1.25 MHz
1.6 μs
333.33 kHz
6 μs
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC
100
001
101
010
110
011
3.2 μs
12 μs
6.4 μs
24 μs(3)
48 μs(3)
96 μs(3)
192 μs(3)
2-6 μs(1)
3.2 μs
12.8 μs
25.6 μs(3)
51.2 μs(3)
2-6 μs(1)
6.4 μs
3.2 μs
2-6 μs(1)
12.8 μs
2-6 μs(1)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4 μs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
TABLE 20-2: TAD vs. DEVICE OPERATING FREQUENCIES (FOR EXTENDED, LF DEVICES)
Device Frequency
AD Clock Source (TAD)
Operation ADCS2:ADCS0
000
4 MHz
500 ns(2)
1.0 μs(2)
2.0 μs(2)
4.0 μs(2)
8.0 μs
2 MHz
1.25 MHz
1.6 μs(2)
3.2 μs(2)
6.4 μs
333.33 kHz
6 μs
2 TOSC
1.0 μs(2)
2.0 μs(2)
4.0 μs
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC
100
001
101
010
110
011
12 μs
24 μs(3)
48 μs(3)
96 μs(3)
192 μs(3)
3-9 μs(1)
8.0 μs
12.8 μs
16.0 μs
32.0 μs
3-9 μs(1)
25.6 μs(3)
51.2 μs(3)
3-9 μs(1)
16.0 μs
3-9 μs(1)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 6 μs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
DS41159E-page 246
© 2006 Microchip Technology Inc.
PIC18FXX8
20.4.1
A/D RESULT REGISTERS
20.4 A/D Conversions
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 20-3 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ‘0’s. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
Figure 20-4 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D Result register pair will not be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL
registers). After the A/D conversion is aborted, a 2 TAD
wait is required before the next acquisition is started.
After this 2 TAD wait, acquisition on the selected
channel is automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 20-3:
A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 0
ADFM = 1
0
7
7
2 1 0 7
0 7 6 5
0
0000 00
0000 00
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result
10-bit Result
Left Justified
Right Justified
© 2006 Microchip Technology Inc.
DS41159E-page 247
PIC18FXX8
acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location). The
appropriate analog input channel must be selected and
the minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
20.5 Use of the ECCP Trigger
An A/D conversion can be started by the “special event
trigger” of the ECCP module. This requires that the
ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and the
Timer1 (or Timer3) counter will be reset to zero. Timer1
(or Timer3) is reset to automatically repeat the A/D
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
FIGURE 20-4:
A/D CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b0
b3
b2
b1
b0
b7
b6
b5
b4
b8
b9
Conversion Starts
Holding capacitor is disconnected from analog input
(typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
TABLE 20-3: SUMMARY OF A/D REGISTERS
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
RBIE
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
LVDIF
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
-0-0 0000 -0-0 0000
-0-0 0000 -0-0 0000
-1-1 1111 -1-1 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
00-- 0000 00-- 0000
-x0x 0000 -u0u 0000
-111 1111 -111 1111
---- -xxx ---- -000
---- -xxx ---- -uuu
0000 -111 0000 -111
(1)
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
—
TMR1IF
TMR1IE
TMR1IP
(1)
(1)
(1)
(1)
(1)
(1)
CMIF
CMIE
CMIP
TMR3IF ECCP1IF
TMR3IE ECCP1IE
TMR3IP ECCP1IP
(1)
(1)
—
—
LVDIE
—
—
LVDIP
ADRESH A/D Result Register
ADRESL A/D Result Register
ADCON0 ADCS1
ADCS0
ADCS2
RA6
CHS2
—
CHS1
—
CHS0 GO/DONE
—
ADON
PCFG0
RA0
ADCON1
PORTA
TRISA
ADFM
—
PCFG3
RA3
PCFG2
RA2
PCFG1
RA1
RA5
RA4
—
PORTA Data Direction Register
PORTE
LATE
—
—
—
—
—
—
—
—
—
—
RE2
RE1
RE0
—
LATE2
TRISE2
LATE1
TRISE1
LATE0
TRISE
IBF
OBF
IBOV
PSPMODE
TRISE0
Legend:
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.
DS41159E-page 248
© 2006 Microchip Technology Inc.
PIC18FXX8
The CMCON register, shown in Register 21-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 21-1.
21.0 COMPARATOR MODULE
Note:
The analog comparators are only
available on the PIC18F448 and
PIC18F458.
The comparator module contains two analog com-
parators. The inputs to the comparators are
multiplexed with the RD0 through RD3 pins. The on-chip
voltage reference (Section 22.0 “Comparator Voltage
Reference Module”) can also be an input to the
comparators.
REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
C2OUT
C1OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RD0/PSP0
C2 VIN- connects to RD2/PSP2
0= C1 VIN- connects to RD1/PSP1
C2 VIN- connects to RD3/PSP3
bit 2-0 CM2:CM0: Comparator Mode bits
Figure 21-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 249
PIC18FXX8
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 27.0 “Electrical Characteristics”.
21.1 Comparator Configuration
There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 21-1 shows the eight possible modes.
The TRISD register controls the data direction of the
comparator pins for each mode. If the Comparator
Note:
Comparator interrupts should be disabled
during Comparator mode change;
otherwise, a false interrupt may occur.
a
FIGURE 21-1:
COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
CM2:CM0 = 000
Comparators Off
CM2:CM0 = 111
A
D
VIN-
VIN-
RD1/PSP1
RD0/PSP0
RD1/PSP1
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
RD0/PSP0
A
A
D
VIN-
VIN-
RD3/PSP3
RD2/PSP2
RD3/PSP3
VIN+
VIN+
D
RD2/PSP2
Two Independent Comparators with Outputs
CM2:CM0 = 011
Two Independent Comparators
CM2:CM0 = 010
A
VIN-
A
VIN-
RD1/PSP1
RD0/PSP0
RD1/PSP1
RD0/PSP0
C1OUT
C2OUT
C1
C2
VIN+
A
C1OUT
C2OUT
C1
C2
VIN+
A
RE1/AN6/WR/C1OUT
A
A
VIN-
A
A
VIN-
RD3/PSP3
RD2/PSP2
RD3/PSP3
RD2/PSP2
VIN+
VIN+
RE2/AN7/CS/C2OUT
Two Common Reference Comparators
CM2:CM0 = 100
Two Common Reference Comparators with Outputs
CM2:CM0 = 101
A
A
VIN-
VIN-
RD1/PSP1
RD0/PSP0
RD1/PSP1
RD0/PSP0
C1OUT
C2OUT
C1OUT
C1
C2
C1
VIN+
VIN+
A
A
RE1/AN6/WR/
C1OUT
A
D
VIN-
RD3/PSP3
RD2/PSP2
A
VIN-
VIN+
RD3/PSP3
C2OUT
C2
VIN+
D
RD2/PSP2
RE2/AN7/CS/C2OUT
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 110
One Independent Comparator with Output
CM2:CM0 = 001
A
A
A
VIN-
RD1/PSP1
RD1/PSP1
RD0/PSP0
CIS = 0
CIS = 1
VIN-
A
C1OUT
C1
C2
VIN+
RD0/PSP0
C1OUT
C2OUT
C1
C2
VIN+
RE1/AN6/WR/C1OUT
A
A
RD3/PSP3
RD2/PSP2
VIN-
CIS = 0
CIS = 1
VIN+
D
D
VIN-
RD3/PSP3
RD2/PSP2
Off (Read as ‘0’)
VIN+
CVREF
From VREF Module
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
DS41159E-page 250
© 2006 Microchip Technology Inc.
PIC18FXX8
21.3.2
INTERNAL REFERENCE SIGNAL
21.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference for the compara-
tors. Section 22.0 “Comparator Voltage Reference
Module” contains a detailed description of the module
that provides this signal. The internal reference signal is
used when comparators are in mode CM<2:0> = 110
(Figure 21-1). In this mode, the internal voltage
reference is applied to the VIN+ pin of both comparators.
A single comparator is shown in Figure 21-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 21-2 represent
the uncertainty due to input offsets and response time.
21.4 Comparator Response Time
21.3 Comparator Reference
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (Section 27.0
“Electrical Characteristics”).
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingly (Figure 21-2).
FIGURE 21-2:
SINGLE COMPARATOR
21.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RE1 and RE2
I/O pins. When enabled, multiplexors in the output path
of the RE1 and RE2 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 21-3 shows the comparator output block
diagram.
VIN+
VIN-
+
-
Output
VIN-
V
VIN+
The TRISE bits will still function as an output enable/
disable for the RE1 and RE2 pins while in this mode.
Output
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5>).
Note 1: When reading the Port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
21.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume more current than is specified.
© 2006 Microchip Technology Inc.
DS41159E-page 251
PIC18FXX8
FIGURE 21-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
-
CxINV
To RE1 or
RE2 pin
Bus
Data
Q
D
Read CMCON
EN
Q
Set
CMIF
bit
D
From
Other
Comparator
EN
CL
Read CMCON
Reset
21.6 Comparator Interrupts
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2 register) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing ‘0’. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
The CMIE bit (PIE2 register) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DS41159E-page 252
© 2006 Microchip Technology Inc.
PIC18FXX8
21.7 Comparator Operation During
Sleep
21.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the
Comparator Reset mode, CM<2:0> = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at Reset time. The comparators will be
powered down during the Reset interval.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the com-
parator specifications. To minimize power consumption
while in Sleep mode, turn off the comparators,
CM<2:0> = 111, before entering Sleep. If the device
wakes up from Sleep, the contents of the CMCON
register are not affected.
21.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 21-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 21-4:
ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
I LEAKAGE
500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend:
CPIN
VT
=
=
Input Capacitance
Threshold Voltage
I LEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
© 2006 Microchip Technology Inc.
DS41159E-page 253
PIC18FXX8
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
all other
Resets
Value on
POR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON C2OUT C1OUT C2INV
CVRCON CVREN CVROE CVRR
C1INV
CVRSS
INT0IE
CIS
CM2
CM1
CM0
CVR0
RBIF
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
CVR3 CVR2
CVR1
INTCON
GIE/
PEIE/ TMR0IE
GIEL
RBIE TMR0IF INT0IF
GIEH
PIR2
—
—
CMIF(1)
CMIE(1)
CMIP(1)
RD6
—
—
EEIF
EEIE
EEIP
RD4
BCLIF LVDIF TMR3IF ECCP1IF(1) -0-0 0000 -0-0 0000
BCLIE LVDIE TMR3IE ECCP1IE(1) -0-0 0000 -0-0 0000
BCLIP LVDIP TMR3IP ECCP1IP(1) -1-1 1111 -1-1 1111
PIE2
IPR2
—
—
PORTD
LATD
TRISD
PORTE
LATE
RD7
RD5
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---- -xxx ---- -000
---- -xxx ---- -uuu
LATD7 LATD6 LATD5
LATD4
LATD3 LATD2 LATD1
LATD0
PORTD Data Direction Register
—
—
—
—
—
—
—
—
RE2
RE1
RE0
—
—
—
LATE2 LATE1
LATE0
TRISE
IBF(1) OBF(1) IBOV(1) PSPMODE(1)
TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’
Note 1: These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.
DS41159E-page 254
© 2006 Microchip Technology Inc.
PIC18FXX8
22.1 Configuring the Comparator
22.0 COMPARATOR VOLTAGE
REFERENCE MODULE
Voltage Reference
The comparator voltage reference can output 16 distinct
voltage levels for each range. The equations used to
calculate the output of the comparator voltage reference
are as follows.
Note:
The comparator voltage reference is only
available on the PIC18F448 and
PIC18F458.
This module is a 16-tap resistor ladder network that
provides a selectable voltage reference. The resistor
ladder is segmented to provide two ranges of CVREF
values and has a power-down function to conserve
power when the reference is not being used. The
CVRCON register controls the operation of the
reference, as shown in Register 22-1. The block
diagram is shown in Figure 22-1.
EQUATION 22-1:
If CVRR = 1:
CVREF = (CVR<3:0>/24) x CVRSRC
where:
CVRSS = 1, CVRSRC = (VREF+) – (VREF-)
CVRSS = 0, CVRSRC = AVDD – AVSS
The comparator and reference supply voltage can
come from either VDD and VSS, or the external VREF+
and VREF-, that are multiplexed with RA3 and RA2. The
comparator reference supply voltage is controlled by
the CVRSS bit.
EQUATION 22-2:
If CVRR = 0:
CVREF = (CVRSRC x 1/4) + (CVR<3:0>/32) x CVRSRC
where:
CVRSS = 1, CVRSRC = (VREF+) – (VREF-)
CVRSS = 0, CVRSRC = AVDD – AVSS
The settling time of the Comparator Voltage Reference
must be considered when changing the RA0/AN0/
CVREF output (see Table 27-4 in Section 27.2 “DC
Characteristics”).
REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVROE
CVRSS
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit
1= CVREF voltage level is also output on the RA0/AN0/CVREF pin
0= CVREF voltage is disconnected from the RA0/AN0/CVREF pin
CVRR: Comparator VREF Range Selection bit
1= 0.00 CVRSRC to 0.625 CVRSRC with CVRSRC/24 step size
0= 0.25 CVRSRC to 0.719 CVRSRC with CVRSRC/32 step size
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator reference source, CVRSRC = VDD – VSS
bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits
When CVRR = 1:
CVREF = (CVR3:CVR0/24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (CVR3:CVR0/32) • (CVRSRC)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 255
PIC18FXX8
FIGURE 22-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
VREF+
16 Stages
CVRSS = 1
CVRSS = 0
CVREN
R
R
R
8R
R
CVRR
CVRSS = 1
8R
CVRSS = 0
RA2/AN2/VREF-
CVR3
RA0/AN0/CVREF
or CVREF of Comparator
(From CVRCON<3:0>)
CVR0
16-to-1 Analog MUX
22.2 Voltage Reference Accuracy/Error
22.4 Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 22-1) keep VREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the VREF output
changes with fluctuations in that source. The absolute
accuracy of the voltage reference can be found in
Section 27.0 “Electrical Characteristics”.
A device Reset disables the voltage reference by
clearing bit CVREN (CVRCON register). This Reset
also disconnects the reference from the RA2 pin by
clearing bit CVROE (CVRCON register) and selects the
high-voltage range by clearing bit CVRR (CVRCON
register). The CVRSS value select bits, CVRCON<3:0>,
are also cleared.
22.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA0/AN0 pin if the
TRISA<0> bit is set and the CVROE bit (CVRCON<6>)
is set. Enabling the voltage reference output onto the
RA0/AN0 pin, with an input signal present, will increase
current consumption. Connecting RA0/AN0 as a digital
output, with CVRSS enabled, will also increase current
consumption.
22.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
The RA0/AN0 pin can be used as a simple D/A output
with limited drive capability. Due to the limited current
drive capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 22-2 shows an example buffering technique.
DS41159E-page 256
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 22-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
R
RA0/AN0
CVREF
Module
+
–
•
CVREF Output
•
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration CVRCON<3:0> and CVRCON<5>.
TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Value on
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
CVRCON CVREN CVROE CVRR CVRSS CVR3
CVR2
CM2
CVR1
CM1
CVR0 0000 0000 0000 0000
CM0 0000 0000 0000 0000
CMCON
TRISA
C2OUT C1OUT C2INV C1INV
CIS
—
TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 -111 1111
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
© 2006 Microchip Technology Inc.
DS41159E-page 257
PIC18FXX8
NOTES:
DS41159E-page 258
© 2006 Microchip Technology Inc.
PIC18FXX8
Figure 23-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shutdown the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference TB – TA is the total
time for shutdown.
23.0 LOW-VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application
software can do “housekeeping tasks” before the
device voltage exits the valid operating range. This can
be done using the Low-Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower than the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the
interrupt vector address and the software can then
respond to that interrupt source.
The block diagram for the LVD module is shown in
Figure 23-2. A comparator uses an internally gener-
ated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a “trip point”
voltage. The “trip point” voltage is the minimum supply
voltage level at which the device can operate before the
LVD module asserts an interrupt. When the supply
voltage is equal to the trip point, the voltage tapped off of
the resistor array is equal to the internal reference
voltage generated by the voltage reference module. The
comparator then generates an interrupt signal, setting
the LVDIF bit. This voltage is software programmable to
any one of 16 values (see Figure 23-2). The trip point is
selected by programming the LVDL3:LVDL0 bits
(LVDCON<3:0>).
The Low-Voltage Detect circuitry is completely under
software control. This allows the circuitry to be “turned
off” by the software which minimizes the current
consumption for the device.
FIGURE 23-1:
TYPICAL LOW-VOLTAGE DETECT APPLICATION
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TB
TA
Time
© 2006 Microchip Technology Inc.
DS41159E-page 259
PIC18FXX8
FIGURE 23-2:
LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD
LVDIN
LVDL3:LVDL0
LVDCON
Register
LVDIF
Internally Generated
LVDEN
Reference Voltage,
1.2V Typical
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from an
external source. This mode is enabled when bits
LVDL3:LVDL0 are set to ‘1111’. In this state, the com-
parator input is multiplexed from the external input pin
LVDIN to one input of the comparator (Figure 23-3).
The other input is connected to the internally generated
voltage reference (parameter #D423 in Section 27.2
“DC Characteristics”). This gives users flexibility,
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
FIGURE 23-3:
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVDL3:LVDL0
LVDCON
Register
LVDEN
LVDIN
Externally Generated
Trip Point
LVD
VxEN
BODEN
EN
BGAP
DS41159E-page 260
© 2006 Microchip Technology Inc.
PIC18FXX8
23.1 Control Register
The Low-Voltage Detect Control register controls the
operation of the Low Voltage Detect circuitry.
REGISTER 23-1: LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER
U-0
—
U-0
—
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0= Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low-Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low-Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.45V min.-4.83V max.
1101= 4.16V min.-4.5V max.
1100= 3.96V min.-4.2V max.
1011= 3.76V min.-4.08V max.
1010= 3.57V min.-3.87V max.
1001= 3.47V min.-3.75V max.
1000= 3.27V min.-3.55V max.
0111= 2.98V min.-3.22V max.
0110= 2.77V min.-3.01V max.
0101= 2.67V min.-2.89V max.
0100= 2.48V min.-2.68V max.
0011= 2.37V min.-2.57V max.
0010= 2.18V min.-2.36V max.
0001= 1.98V min.-2.14V max.
0000= Reserved
Note:
LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage
of the device, are not tested.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2006 Microchip Technology Inc.
DS41159E-page 261
PIC18FXX8
The following steps are needed to set up the LVD
module:
23.2 Operation
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be
constantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods where the voltage is checked. After doing
the check, the LVD module may be disabled.
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register) which selects the desired
LVD trip point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 23-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 23-4:
LOW-VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIRVST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
TIRVST
Internally Generated
Reference Stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS41159E-page 262
© 2006 Microchip Technology Inc.
PIC18FXX8
23.2.1
REFERENCE VOLTAGE SET POINT
23.3 Operation During Sleep
The internal reference voltage of the LVD module may be
used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low-voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low-voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 23-4.
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
23.4 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
23.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
© 2006 Microchip Technology Inc.
DS41159E-page 263
PIC18FXX8
NOTES:
DS41159E-page 264
© 2006 Microchip Technology Inc.
PIC18FXX8
Sleep mode is designed to offer a very Low-Current
Power-Down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits is used to select various options.
24.0 SPECIAL FEATURES OF
THE CPU
There are several features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection. These are:
• Oscillator Selection
• Reset
24.1 Configuration Bits
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh)
which can only be accessed using table reads and
table writes.
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
Configuration register. In normal operation mode, a
TBLWT instruction, with the TBLPTR pointed to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWTinstruction
can write a ‘1’ or a ‘0’ into the cell.
All PIC18FXX8 devices have a Watchdog Timer which
is permanently enabled via the configuration bits or
software controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT) which provides a fixed
delay on power-up only, designed to keep the part in
Reset while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry.
TABLE 24-1: CONFIGURATION BITS AND DEVICE IDS
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300001h
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
—
—
—
—
—
—
OSCSEN
—
—
—
—
FOSC2
BORV0
FOSC1
BOREN
FOSC0
PWRTEN
WDTEN
--1- -111
---- 1111
---- 1111
300002h
300003h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
—
BORV1
WDTPS2 WDTPS1 WDTPS0
DEBUG
—
—
—
—
—
—
—
—
CP3
—
LVP
CP2
—
—
CP1
—
STVREN
CP0
1--- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
(1)
CPD
—
CPB
—
—
—
—
—
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
WRTD
—
WRTB
—
WRTC
—
—
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
—
EBTRB
DEV1
DEV9
—
—
3FFFFEh DEVID1
3FFFFFh DEVID2
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
0000 1000
Legend:
Note 1:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
See Register 24-11 for DEVID1 values.
© 2006 Microchip Technology Inc.
DS41159E-page 265
PIC18FXX8
REGISTER 24-1: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTEADDRESS300001h)
U-0
—
U-0
—
R/P-1
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
OSCSEN
FOSC2 FOSC1 FOSC0
bit 0
bit 7
bit 7-6
bit 5
Unimplemented: Read as ‘0’
OSCSEN: Oscillator System Clock Switch Enable bit
1= Oscillator system clock switch option is disabled (main oscillator is source)
0= Oscillator system clock switch option is enabled (oscillator switching is enabled)
bit 4-3
bit 2-0
Unimplemented: Read as ‘0’
FOSC2:FOSC0: Oscillator Selection bits
111= RC oscillator w/OSC2 configured as RA6
110= HS oscillator with PLL enabled/clock frequency = (4 x FOSC)
101= EC oscillator w/OSC2 configured as RA6
100= EC oscillator w/OSC2 configured as divide-by-4 clock output
011= RC oscillator
010= HS oscillator
001= XT oscillator
000= LP oscillator
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
REGISTER 24-2: CONFIG2L:CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS300002h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
BORV1
BORV0 BOREN PWRTEN
bit 0
bit 7
bit 7-4
bit 3-2
Unimplemented: Read as ‘0’
BORV1:BORV0: Brown-out Reset Voltage bits
11= VBOR set to 2.0V
10= VBOR set to 2.7V
01= VBOR set to 4.2V
00= VBOR set to 4.5V
bit 1
bit 0
BOREN: Brown-out Reset Enable bit
1= Brown-out Reset enabled
0= Brown-out Reset disabled
PWRTEN: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
DS41159E-page 266
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 0
bit 7
bit 7-4
bit 3-1
Unimplemented: Read as ‘0’
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111= 1:128
110= 1:64
101= 1:32
100= 1:16
011= 1:8
010= 1:4
001= 1:2
000= 1:1
Note:
The Watchdog Timer postscale select bits configuration used in the PIC18FXXX
devices has changed from the configuration used in the PIC18CXXX devices.
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 24-4: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
LVP
U-0
—
R/P-1
STVREN
bit 0
DEBUG
bit 7
bit 7
DEBUG: Background Debugger Enable bit
1= Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0= Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
bit 6-3
bit 2
Unimplemented: Read as ‘0’
LVP: Low-Voltage ICSP Enable bit
1= Low-Voltage ICSP enabled
0= Low-Voltage ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack Full/Underflow will cause Reset
0= Stack Full/Underflow will not cause Reset
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
© 2006 Microchip Technology Inc.
DS41159E-page 267
PIC18FXX8
REGISTER 24-5: CONFIG5L:CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS300008h)
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
CP3(1)
R/C-1
CP2(1)
R/C-1
CP1
R/C-1
CP0
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as ‘0’
CP3: Code Protection bit(1)
1= Block 3 (006000-007FFFh) not code-protected
0= Block 3 (006000-007FFFh) code-protected
bit 2
bit 1
bit 0
CP2: Code Protection bit(1)
1= Block 2 (004000-005FFFh) not code-protected
0= Block 2 (004000-005FFFh) code-protected
CP1: Code Protection bit
1= Block 1 (002000-003FFFh) not code-protected
0= Block 1 (002000-003FFFh) code-protected
CP0: Code Protection bit
1= Block 0 (000200-001FFFh) not code-protected
0= Block 0 (000200-001FFFh) code-protected
Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.
Legend:
R = Readable bit
-n = Value when device is unprogrammed
C = Clearable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 24-6: CONFIG5H:CONFIGURATION REGISTER5 HIGH (BYTEADDRESS300009h)
R/C-1
CPD
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
CPD: Data EEPROM Code Protection bit
1= Data EEPROM not code-protected
0= Data EEPROM code-protected
bit 6
CPB: Boot Block Code Protection bit
1= Boot Block (000000-0001FFh) not code-protected
0= Boot Block (000000-0001FFh) code-protected
bit 5-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
DS41159E-page 268
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 24-7: CONFIG6L:CONFIGURATIONREGISTER6 LOW(BYTEADDRESS30000Ah)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
WRT3(1) WRT2(1)
R/P-1
R/P-1
R/P-1
WRT1
WRT0
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as ‘0’
WRT3: Write Protection bit(1)
1= Block 3 (006000-007FFFh) not write-protected
0= Block 3 (006000-007FFFh) write-protected
bit 2
bit 1
bit 0
WRT2: Write Protection bit(1)
1= Block 2 (004000-005FFFh) not write-protected
0= Block 2 (004000-005FFFh) write-protected
WRT1: Write Protection bit
1= Block 1 (002000-003FFFh) not write-protected
0= Block 1 (002000-003FFFh) write-protected
WRT0: Write Protection bit
1= Block 0 (000200-001FFFh) not write-protected
0= Block 0 (000200-001FFFh) write-protected
Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.
Legend:
R = Readable bit
-n = Value when device is unprogrammed
P = Programmable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
REGISTER 24-8: CONFIG6H:CONFIGURATION REGISTER6 HIGH(BYTEADDRESS30000Bh)
R/P-1
R/P-1
R-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
WRTD
WRTB
WRTC
bit 7
bit 0
bit 7
bit 6
bit 5
WRTD: Data EEPROM Write Protection bit
1= Data EEPROM not write-protected
0= Data EEPROM write-protected
WRTB: Boot Block Write Protection bit
1= Boot Block (000000-0001FFh) not write-protected
0= Boot Block (000000-0001FFh) write-protected
WRTC: Configuration Register Write Protection bit
1= Configuration registers (300000-3000FFh) not write-protected
0= Configuration registers (300000-3000FFh) write-protected
Note:
This bit is read-only and cannot be changed in user mode.
bit 4-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
© 2006 Microchip Technology Inc.
DS41159E-page 269
PIC18FXX8
REGISTER 24-9: CONFIG7L:CONFIGURATIONREGISTER7 LOW(BYTE ADDRESS30000Ch)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
EBTR3(1) EBTR2(1)
R/P-1
R/P-1
R/P-1
EBTR1
EBTR0
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as ‘0’
EBTR3: Table Read Protection bit(1)
1= Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
0= Block 3 (006000-007FFFh) protected from table reads executed in other blocks
bit 2
bit 1
bit 0
EBTR2: Table Read Protection bit(1)
1= Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
0= Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
1= Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
0= Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
1= Block 0 (000200-001FFFh) not protected from table reads executed in other blocks
0= Block 0 (000200-001FFFh) protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
REGISTER 24-10: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0
—
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
EBTRB
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1= Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
0= Boot Block (000000-0001FFh) protected from table reads executed in other blocks
bit 5-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
DS41159E-page 270
© 2006 Microchip Technology Inc.
PIC18FXX8
REGISTER 24-11: DEVID1: DEVICE ID REGISTER 1 FOR PIC18FXX8 DEVICES
(BYTE ADDRESS 3FFFFEh)
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5
DEV2:DEV0: Device ID bits
These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the
part number.
000= PIC18F248
001= PIC18F448
010= PIC18F258
011= PIC18F458
bit 4-0
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
REGISTER 24-12: DEVID2: DEVICE ID REGISTER 2 FOR PIC18FXX8 DEVICES
(BYTE ADDRESS 3FFFFFh)
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 0
bit 7
bit 7-0
DEV10:DEV3: Device ID bits
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the
part number.
00001000= PIC18FXX8
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
© 2006 Microchip Technology Inc.
DS41159E-page 271
PIC18FXX8
The WDT time-out period values may be found in
Section 27.0 “Electrical Characteristics” under
parameter #31. Values for the WDT postscaler may be
assigned using the configuration bits.
24.2 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEPinstruction.
Note:
The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler if assigned to
the WDT and prevent it from timing out
and generating a device Reset condition.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation
(Watchdog Timer wake-up). The TO bit in the RCON
register will be cleared upon a WDT time-out.
Note:
When a CLRWDT instruction is executed
and the postscaler is assigned to the WDT,
the postscaler count will be cleared but the
postscaler assignment is not changed.
24.2.1
CONTROL REGISTER
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software
execution may not disable this function. When the
WDTEN configuration bit is cleared, the SWDTEN bit
enables/disables the operation of the WDT.
Register 24-13 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit only when the configuration bit has
disabled the WDT.
REGISTER 24-13: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN
bit 0
bit 7
bit 7-1
bit 0
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
DS41159E-page 272
© 2006 Microchip Technology Inc.
PIC18FXX8
24.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
device programming by the value written to the
CONFIG2H Configuration register.
FIGURE 24-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
8
WDTPS2:WDTPS0
8-to-1 MUX
WDTEN
Configuration bit
SWDTEN bit
WDT
Time-out
Note:
WDTPS2:WDTPS0 are bits in register CONFIG2H.
TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG2H
RCON
—
IPEN
—
—
—
—
—
—
—
—
RI
—
WDTPS2 WDTPS1 WDTPS0
WDTEN
BOR
TO
—
PD
—
POR
—
WDTCON
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
© 2006 Microchip Technology Inc.
DS41159E-page 273
PIC18FXX8
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
24.3 Power-Down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (RCON<2>) is cleared, the
TO bit (RCON<3>) is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
When the SLEEPinstruction is being executed, the next
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry
is drawing current from the I/O pin, power-down the A/D
and disable external clocks. Pull all I/O pins that are
high-impedance inputs, high or low externally, to avoid
switching currents caused by floating inputs. The T0CKI
input should also be at VDD or VSS for lowest current
consumption. The contribution from on-chip pull-ups on
PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
24.3.2
WAKE-UP USING INTERRUPTS
24.3.1
WAKE-UP FROM SLEEP
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin.
• If an interrupt condition (interrupt flag bit and
interrupt enable bits are set) occurs before the
execution of a SLEEPinstruction, the SLEEP
instruction will complete as a NOP. Therefore, the
WDT and WDT postscaler will not be cleared, the
TO bit will not be set and the PD bit will not be
cleared.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
peripheral interrupt.
The following peripheral interrupts can wake the device
from Sleep:
• If the interrupt condition occurs during or after
the execution of a SLEEPinstruction, the device
will immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
4. CCP Capture mode interrupt.
5. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
6. MSSP (Start/Stop) bit detect interrupt.
7. MSSP transmit or receive in Slave mode
(SPI/I2C).
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
10. EEPROM write operation complete.
11. LVD interrupt.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
DS41159E-page 274
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 24-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO(4)
INT pin
(2)
TOST
INTF Flag
(INTCON<1>)
Interrupt Latency(3)
GIEH bit
Processor in
Sleep
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC + 2
PC + 4
PC + 4
PC + 4
0008h
000Ah
Instruction
Fetched
Inst(0008h)
Inst(PC + 2)
Inst(PC + 4)
Inst(PC + 2)
Inst(000Ah)
Inst(PC) = Sleep
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst(0008h)
Sleep
Inst(PC – 1)
Note 1: XT, HS or LP Oscillator mode assumed.
2: GIE = 1assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
4: CLKO is not available in these oscillator modes but shown here for timing reference.
© 2006 Microchip Technology Inc.
DS41159E-page 275
PIC18FXX8
Each of the five blocks has three code protection bits
associated with them. They are:
24.4 Program Verification and
Code Protection
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro devices.
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into four blocks on binary
boundaries.
FIGURE 24-3:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8
MEMORY SIZE/DEVICE
Block Code Protection
16 Kbytes
(PIC18FX48)
32 Kbytes
(PIC18FX58)
Address
Range
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000000h
0001FFh
Boot Block
Boot Block
Block 0
000200h
Block 0
Block 1
001FFFh
002000h
Block 1
Block 2
Block 3
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
003FFFh
004000h
Unimplemented
Read ‘0’s
005FFFh
006000h
Unimplemented
Read ‘0’s
007FFFh
008000h
Unimplemented
Unimplemented
Read ‘0’s
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
CONFIG5L
CONFIG5H
CONFIG6L
—
CPD
—
—
CPB
—
—
—
—
—
—
—
—
—
CP3
—
CP2
—
CP1
—
CP0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
CONFIG6H WRTD
WRTB
—
WRTC
—
CONFIG7L
CONFIG7H
—
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
EBTRB
—
Legend: Shaded cells are unimplemented.
DS41159E-page 276
© 2006 Microchip Technology Inc.
PIC18FXX8
24.4.1
PROGRAM MEMORY
CODE PROTECTION
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The device ID may be read with table reads. The
Configuration registers may be read and written with
the table read and table write instructions.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 24-4 through 24-6
illustrate table write and table read protection.
FIGURE 24-4:
TABLE WRITE (WRTn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
WRTB, EBTRB = 11
000200h
TBLPTR = 000FFF
PC = 001FFE
WRT0, EBTR0 = 01
TBLWT *
TBLWT *
001FFFh
002000h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
003FFFh
004000h
PC = 004FFE
005FFFh
006000h
007FFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
© 2006 Microchip Technology Inc.
DS41159E-page 277
PIC18FXX8
FIGURE 24-5:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0001FFh
000200h
TBLPTR = 000FFF
PC = 002FFE
WRT0, EBTR0 = 10
001FFFh
002000h
TBLRD *
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
003FFFh
004000h
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 24-6:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
0001FFh
000200h
TBLPTR = 000FFF
PC = 001FFE
TBLRD *
001FFFh
002000h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
003FFFh
004000h
005FFFh
006000h
007FFFh
Results: Table reads permitted within Blockn even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
DS41159E-page 278
© 2006 Microchip Technology Inc.
PIC18FXX8
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies. The
Microchip In-Circuit Debugger (ICD) used with the
PIC18FXXX microcontrollers is the MPLAB® ICD 2.
24.4.2
DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM
regardless of the protection bit settings.
24.8 Low-Voltage ICSP Programming
24.4.3
CONFIGURATION REGISTER
PROTECTION
The LVP bit in Configuration register, CONFIG4L,
enables Low-Voltage ICSP Programming. This mode
allows the microcontroller to be programmed via ICSP
using a VDD source in the operating voltage range. This
only means that VPP does not have to be brought to
VIHH but can instead be left at the normal operating
voltage. In this mode, the RB5/PGM pin is dedicated to
the programming function and ceases to be a general
purpose I/O pin. During programming, VDD is applied to
the MCLR/VPP pin. To enter Programming mode, VDD
must be applied to the RB5/PGM pin, provided the LVP
bit is set. The LVP bit defaults to a (‘1’) from the factory.
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In user mode, the WRTC bit is readable only.
WRTC can only be written via ICSP or an external
programmer.
24.5 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations where the user can store
checksum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD and TBLWT instructions or during
program/verify. The ID locations can be read when the
device is code-protected.
Note 1: The High-Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purpose I/O pin.
24.6
In-Circuit Serial Programming
PIC18FXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
3: When using Low-Voltage ICSP Program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
If Low-Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be
programmed when programming is entered with VIHH
on MCLR/VPP. The LVP bit can only be charged when
using high voltage on MCLR.
24.7 In-Circuit Debugger
When the DEBUG bit in Configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with
MPLAB® IDE. When the microcontroller has this fea-
ture enabled, some of the resources are not available
for general use. Resources used include 2 I/O pins,
stack locations, program memory and data memory.
For more information on the resources required, see
the User’s Guide for the In-Circuit Debugger you are
using.
It should be noted that once the LVP bit is programmed
to ‘0’, only the High-Voltage Programming mode is
available and only High-Voltage Programming mode
can be used to program the device.
When using Low-Voltage ICSP Programming, the part
must be supplied 4.5V to 5.5V if a bulk erase will be
executed. This includes reprogramming of the code-
protect bits from an ON state to an OFF state. For all
other cases of Low-Voltage ICSP Programming, the
part may be programmed at the normal operating
voltage. This means unique user IDs or user code can
be reprogrammed or added.
© 2006 Microchip Technology Inc.
DS41159E-page 279
PIC18FXX8
NOTES:
DS41159E-page 280
© 2006 Microchip Technology Inc.
PIC18FXX8
The control instructions may use some of the following
operands:
25.0 INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PICmicro instruction sets, while maintaining
an easy migration from these PICmicro instruction sets.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
Most instructions are a single program memory word
(16 bits) but there are three instructions that require two
program memory locations.
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information is available in these 32 bits. In the
second word, the 4 MSbs are ‘1’s. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
The double-word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
2. The destination of the result
(specified by ‘d’)
3. The accessed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
Figure 25-1 shows the general formats that the
instructions can have.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
All examples use the format ‘nnh’ to represent a hexa-
decimal number, where ‘h’ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 25-2,
lists the instructions recognized by the Microchip
MPASMTM Assembler.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
Section 25.2 “Instruction Set” provides a description
of each instruction.
2. The bit in the file register
(specified by ‘b’)
3. The accessed memory
(specified by ‘a’)
25.1 Read-Modify-Write Operations
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction or
the destination designator ‘d’. A read operation is
performed on a register even if the instruction writes to
that register.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the
unintended result that the condition that sets the RBIF
flag would be cleared.
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
© 2006 Microchip Technology Inc.
DS41159E-page 281
PIC18FXX8
TABLE 25-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
BSR
d
Bit address within an 8-bit file register (0 to 7).
Bank Select Register. Used to select the current RAM bank.
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination either the WREG register or the specified register file location.
8-bit register file address (0x00 to 0xFF).
fs
12-bit register file address (0x000 to 0xFFF). This is the source address.
12-bit register file address (0x000 to 0xFFF). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
fd
k
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or unchanged.
WREG
x
Working register (accumulator).
Don’t care (0 or 1).
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a program memory location).
8-bit Table Latch.
TABLAT
TOS
Top-of-Stack.
PC
Program Counter
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Global Interrupt Enable bit.
Watchdog Timer.
PCH
PCLATH
PCLATU
GIE
WDT
TO
Time-out bit.
PD
Power-Down bit.
C, DC, Z, OV, N
ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative.
Optional.
[
]
)
(
Contents.
→
< >
∈
Assigned to.
Register bit field.
In the set of.
italics
User defined term (font is courier).
DS41159E-page 282
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 25-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
Example Instruction
15
10
OPCODE
9
8
7
0
ADDWF MYREG, W, B
d
a
f (FILE #)
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 0x7F
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
© 2006 Microchip Technology Inc.
DS41159E-page 283
PIC18FXX8
TABLE 25-2: PIC18FXXX INSTRUCTION SET
Mnemonic,
16-Bit Instruction Word
MSb LSb
Status
Affected
Description
Cycles
Notes
Operands
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
1
1
1
1
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
CPFSEQ f, a
CPFSGT f, a
CPFSLT f, a
Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None
Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None
Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
DECF
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0
DCFSNZ f, d, a Decrement f, Skip if Not 0
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
INCF
f, d, a Increment f
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
fs, fd Move fs (source) to 1st word 2
fd (destination) 2nd word
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
MOVWF f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N 1, 2
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
f, a
f, a
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
1, 2
f, a
Set f
SUBFWB f, d, a Subtract f from WREG with
borrow
0101 01da ffff ffff C, DC, Z, OV, N 1, 2
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N
0101 10da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ f, a
XORWF f, d, a Exclusive OR WREG with f
BIT-ORIENTED FILE REGISTER OPERATIONS
f, d, a Swap nibbles in f
1
0011 10da ffff ffff None
4
1, 2
Test f, skip if 0
1 (2 or 3) 0110 011a ffff ffff None
1
0001 10da ffff ffff Z, N
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS41159E-page 284
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
16-Bit Instruction Word
LSb
Status
Affected
Description
Cycles
Notes
Operands
MSb
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
CALL
Call subroutine1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS) 1
Relative Call
Software device Reset
Return from interrupt enable
1
1
1
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
2
1
2
s
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
© 2006 Microchip Technology Inc.
DS41159E-page 285
PIC18FXX8
TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG 1
Move literal (12-bit)2nd word
to FSRx 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
1
1
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
2
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
Exclusive OR literal with WREG 1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2 (5)
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS41159E-page 286
© 2006 Microchip Technology Inc.
PIC18FXX8
25.2 Instruction Set
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ADDWF
f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are added to the 8-bit
literal ‘k’ and the result is placed in W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected. If ‘a’ is ‘1’, the BSR is
used.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
Example:
ADDLW
0x15
Q Cycle Activity:
Q1
Before Instruction
0x10
After Instruction
0x25
Q2
Q3
Q4
W
=
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
=
Example:
ADDWF
REG, W
Before Instruction
W
REG
=
=
0x17
0xC2
After Instruction
W
REG
=
=
0xD9
0xC2
© 2006 Microchip Technology Inc.
DS41159E-page 287
PIC18FXX8
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
[ label ] ADDWFC
f [,d [,a]]
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is placed
in W. If ‘d’ is ‘1’, the result is placed in
data memory location ‘f’. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
Example:
ANDLW
0x5F
Q Cycle Activity:
Q1
Q2
Q3
Q4
Before Instruction
W
=
0xA3
0x03
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
Example:
ADDWFC
REG, W
Before Instruction
Carry bit =
1
REG
W
=
=
0x02
0x4D
After Instruction
Carry bit =
0
0x02
0x50
REG
W
=
=
DS41159E-page 288
© 2006 Microchip Technology Inc.
PIC18FXX8
ANDWF
AND W with f
BC
Branch if Carry
[ label ] BC
Syntax:
[ label ] ANDWF
f [,d [,a]]
Syntax:
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the program
will branch.
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
Q1
Q2
Q3
Q4
destination
Decode
Read literal
‘n’
Process
Data
Write to PC
Example:
ANDWF
REG, W
No
operation
No
operation
No
operation
No
operation
Before Instruction
W
=
=
0x17
0xC2
If No Jump:
Q1
REG
Q2
Q3
Q4
After Instruction
W
REG
=
=
0x02
0xC2
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BC JUMP
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
© 2006 Microchip Technology Inc.
DS41159E-page 289
PIC18FXX8
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
[ label ] BCF f,b[,a]
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
Description:
Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’,
the Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value (default).
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
Process
Data
Write
register ‘f’
register ‘f’
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Example:
BCF
FLAG_REG, 7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS41159E-page 290
© 2006 Microchip Technology Inc.
PIC18FXX8
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 ≤ n ≤ 127
if Carry bit is ‘0’
n
Syntax:
[ label ] BNN
n
Operands:
Operation:
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
will branch.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Negative
PC
If Carry
PC
If Carry
PC
=
=
=
=
0;
=
=
=
=
0;
address (Jump)
address (Jump)
1;
address (HERE + 2)
1;
If Negative
PC
address (HERE + 2)
© 2006 Microchip Technology Inc.
DS41159E-page 291
PIC18FXX8
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
n
Syntax:
[ label ] BNZ
-128 ≤ n ≤ 127
if Zero bit is ‘0’
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
if Overflow bit is ‘0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
Description:
If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
DS41159E-page 292
© 2006 Microchip Technology Inc.
PIC18FXX8
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
[ label ] BSF f,b[,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
No
No
No
No
operation
operation
operation
operation
Example:
BSF
FLAG_REG, 7
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Example:
HERE
BRA Jump
=
=
0x0A
0x8A
Before Instruction
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
© 2006 Microchip Technology Inc.
DS41159E-page 293
PIC18FXX8
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruction
fetched during the current instruction
execution is discarded and a NOPis
executed instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
If bit ‘b’ is ‘1’, then the next instruction
fetched during the current instruction
execution is discarded and a NOPis
executed instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
DS41159E-page 294
© 2006 Microchip Technology Inc.
PIC18FXX8
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected as
per the BSR value (default).
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
Q Cycle Activity:
Q1
1(2)
Q2
Q3
Q4
Q Cycle Activity:
If Jump:
Decode
Read
Process
Data
Write
register ‘f’
register ‘f’
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Example:
BTG
PORTC,
4
Before Instruction:
PORTC
After Instruction:
PORTC
No
operation
No
operation
No
operation
No
operation
=
0111 0101 [0x75]
0110 0101 [0x65]
If No Jump:
Q1
=
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BOV JUMP
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
© 2006 Microchip Technology Inc.
DS41159E-page 295
PIC18FXX8
BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
[ label ] CALL k [,s]
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(Status) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
No
No
Words:
Cycles:
2
2
operation
operation
operation
If No Jump:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
‘n’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
‘k’<7:0>,
stack
‘k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
=
address (HERE)
After Instruction
Example:
HERE
CALL THERE,FAST
If Zero
PC
If Zero
PC
=
=
=
=
1;
address (Jump)
Before Instruction
PC
After Instruction
0;
=
address (HERE)
address (HERE + 2)
PC
=
address (THERE)
TOS
WS
=
=
=
address (HERE + 4)
W
BSR
Status
BSRS
STATUSS=
DS41159E-page 296
© 2006 Microchip Technology Inc.
PIC18FXX8
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRF f [,a]
Syntax:
[ label ] CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be selected
as per the BSR value (default).
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits TO
and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Decode
No
operation
Process
Data
No
operation
Example:
CLRF
FLAG_REG
Example:
CLRWDT
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Before Instruction
WDT Counter
After Instruction
=
=
0x5A
0x00
=
?
WDT Counter
WDT Postscaler
TO
PD
=
=
=
=
0x00
0
1
1
© 2006 Microchip Technology Inc.
DS41159E-page 297
PIC18FXX8
COMF
Complement f
CPFSEQ
Compare f with W, Skip if f = W
Syntax:
[ label ] COMF f [,d [,a]]
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
Operation:
(f) → dest
skip if (f) = (W)
(unsigned comparison)
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, W
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
=
0x13
After Instruction
If skip:
Q1
REG
W
=
=
0x13
0xEC
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
=
=
HERE
?
?
W
REG
After Instruction
If REG
PC
If REG
PC
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
DS41159E-page 298
© 2006 Microchip Technology Inc.
PIC18FXX8
CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (W),
Operation:
(f) – (W),
skip if (f) > (W)
skip if (f) < (W)
(unsigned comparison)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1(2)
Words:
Cycles:
1
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
No
No
No
No
operation
Q1
Q2
Q3
Q4
operation
operation
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
HERE
CPFSGT REG
NGREATER
GREATER
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
Before Instruction
After Instruction
PC
W
=
=
Address (HERE)
?
If REG
PC
If REG
PC
<
=
≥
=
W;
Address (LESS)
After Instruction
W;
If REG
PC
If REG
PC
>
=
≤
=
W;
Address (NLESS)
Address (GREATER)
W;
Address (NGREATER)
© 2006 Microchip Technology Inc.
DS41159E-page 299
PIC18FXX8
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
[ label ] DAW
None
Syntax:
[ label ] DECF f [,d [,a]]
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
Operation:
(f) – 1 → dest
(W<3:0>) → W<3:0>
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> > 9] or [C = 1] then
(W<7:4>) + 6 → W<7:4>;
else
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
(W<7:4>) → W<7:4>
Status Affected:
Encoding:
C
0000
0000
0000
0111
Description:
DAWadjusts the eight-bit value in W
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example:
DECF
CNT,
Decode
Read
register W
Process
Data
Write
W
Before Instruction
CNT
Z
After Instruction
=
0x01
0
Example 1:
DAW
=
Before Instruction
W
=
=
=
0xA5
0
0
CNT
Z
=
=
0x00
1
C
DC
After Instruction
W
=
=
=
0x05
1
0
C
DC
Example 2:
Before Instruction
W
=
=
=
0xCE
0
0
C
DC
After Instruction
W
=
=
=
0x34
1
0
C
DC
DS41159E-page 300
© 2006 Microchip Technology Inc.
PIC18FXX8
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[ label ] DCFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
Operation:
(f) – 1 → dest,
skip if result = 0
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as per
the BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
=
Address (HERE)
=
?
After Instruction
CNT
=
CNT – 1
0;
If CNT
=
=
≠
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1,
0;
PC
Address (CONTINUE)
0;
If CNT
PC
Address (ZERO)
0;
Address (HERE + 2)
Address (NZERO)
© 2006 Microchip Technology Inc.
DS41159E-page 301
PIC18FXX8
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ] GOTO
0 ≤ k ≤ 1048575
k → PC<20:1>
None
k
Syntax:
[ label ] INCF f [,d [,a]]
Operands:
Operation:
Status Affected:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional branch
Description:
The contents of register ‘f’ are
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>. GOTOis always a two-cycle
instruction.
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>
No
operation
Read literal
‘k’<19:8>,
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
No
operation
No
operation
No
operation
No
operation
Example:
INCF
CNT,
Example:
GOTO THERE
Before Instruction
After Instruction
PC Address (THERE)
CNT
Z
=
0xFF
=
=
=
=
0
?
?
C
DC
After Instruction
CNT
Z
=
0x00
=
=
=
1
1
1
C
DC
DS41159E-page 302
© 2006 Microchip Technology Inc.
PIC18FXX8
INCFSZ
Increment f, Skip if 0
INFSNZ
Increment f, Skip if not 0
Syntax:
[ label ] INCFSZ f [,d [,a]]
Syntax:
[ label ] INFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT
Example:
HERE
ZERO
NZERO
INFSNZ REG
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
REG
If REG
PC
If REG
PC
=
REG + 1
=
=
≠
=
0;
≠
=
=
=
0;
Address (ZERO)
0;
Address (NZERO)
Address (NZERO)
0;
Address (ZERO)
© 2006 Microchip Technology Inc.
DS41159E-page 303
PIC18FXX8
IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
[ label ] IORLW
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
k
Syntax:
[ label ] IORWF f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
Example:
IORLW
0x35
Q Cycle Activity:
Q1
Q2
Q3
Q4
Before Instruction
W
=
0x9A
0xBF
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
Example:
IORWF RESULT, W
Before Instruction
RESULT =
0x13
0x91
W
=
After Instruction
RESULT =
0x13
0x93
W
=
DS41159E-page 304
© 2006 Microchip Technology Inc.
PIC18FXX8
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ] LFSR f,k
Syntax:
[ label ] MOVF f [,d [,a]]
Operands:
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Words:
Cycles:
1
1
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Q Cycle Activity:
Q1
Example:
LFSR 2, 0x3AB
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write W
After Instruction
FSR2H
FSR2L
=
=
0x03
0xAB
Example:
MOVF
REG, W
Before Instruction
REG
W
=
=
0x22
0xFF
After Instruction
REG
W
=
=
0x22
0x22
© 2006 Microchip Technology Inc.
DS41159E-page 305
PIC18FXX8
MOVFF
Move f to f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
[ label ] MOVFF f ,f
Syntax:
[ label ] MOVLB
0 ≤ k ≤ 255
k → BSR
k
s
d
Operands:
0 ≤ f ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
s
0 ≤ f ≤ 4095
d
Operation:
(f ) → f
s
d
None
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
The 8-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
1100
1111
ffff
ffff
ffff
ffff
ffff
ffff
s
d
Words:
Cycles:
1
1
Description:
The contents of source register ‘f ’ are
s
moved to destination register ‘f ’.
d
Location of source ‘f ’ can be anywhere
in the 4096-byte data space (000h to
s
Q Cycle Activity:
Q1
Q2
Q3
Q4
FFFh) and location of destination ‘f ’
d
Decode
Read literal
‘k’
Process
Data
Write
literal ‘k’ to
BSR
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
Example:
MOVLB
5
Before Instruction
BSR register
After Instruction
BSR register
=
=
0x02
0x05
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
The MOVFFinstruction should not be
used to modify interrupt settings while
any interrupt is enabled (see page 77).
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x33
0x11
After Instruction
REG1
REG2
=
=
0x33
0x33
DS41159E-page 306
© 2006 Microchip Technology Inc.
PIC18FXX8
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
[ label ] MOVLW
0 ≤ k ≤ 255
k → W
k
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
None
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight-bit literal ‘k’ is loaded into W.
Description:
Move data from W to register ‘f’.
1
1
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
Example:
MOVLW
0x5A
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x5A
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG
Before Instruction
W
REG
=
=
0x4F
0xFF
After Instruction
W
REG
=
=
0x4F
0x4F
© 2006 Microchip Technology Inc.
DS41159E-page 307
PIC18FXX8
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
[ label ] MULLW
k
Syntax:
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried out
between the contents of W and the 8-bit
literal ‘k’. The 16-bit result is placed in
the PRODH:PRODL register pair.
PRODH contains the high byte. W is
unchanged.
None of the status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Description:
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result
is stored in the PRODH:PRODL
register pair. PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’= 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
Words:
Cycles:
1
1
registers
PRODH:
PRODL
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example:
MULLW
0xC4
Decode
Read
register ‘f’
Process
Data
Write
Before Instruction
registers
PRODH:
PRODL
W
PRODH
PRODL
=
=
=
0xE2
?
?
After Instruction
Example:
MULWF
REG
W
PRODH
PRODL
=
=
=
0xE2
0xAD
0x08
Before Instruction
W
=
=
=
=
0xC4
0xB5
REG
PRODH
PRODL
?
?
After Instruction
W
=
=
=
=
0xC4
0xB5
0x8A
0x94
REG
PRODH
PRODL
DS41159E-page 308
© 2006 Microchip Technology Inc.
PIC18FXX8
NEGF
Negate f
NOP
No Operation
Syntax:
[ label ] NEGF f [,a]
Syntax:
[ label ] NOP
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
No operation
None
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Description:
Words:
No operation.
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
No
Q4
Decode
No
operation
No
Words:
Cycles:
1
1
operation
operation
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [0x3A]
1100 0110 [0xC6]
=
© 2006 Microchip Technology Inc.
DS41159E-page 309
PIC18FXX8
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ] POP
None
Syntax:
[ label ] PUSH
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
(TOS) → bit bucket
None
(PC + 2) → TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows the user to
implement a software stack by
modifying TOS and then pushing it onto
the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
Decode
PUSH PC + 2
onto return
stack
No
operation
No
operation
Example:
POP
GOTO
NEW
Example:
PUSH
Before Instruction
TOS
Stack (1 level down)
Before Instruction
=
=
0x0031A2
0x014332
TOS
PC
=
=
0x00345A
0x000124
After Instruction
After Instruction
TOS
PC
=
=
0x014332
NEW
PC
=
=
=
0x000126
0x000126
0x00345A
TOS
Stack (1 level down)
DS41159E-page 310
© 2006 Microchip Technology Inc.
PIC18FXX8
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 ≤ n ≤ 1023
(PC) + 2 → TOS,
n
Syntax:
[ label ] RESET
None
Operands:
Operation:
Operands:
Operation:
Reset all registers and flags that are
affected by a MCLR Reset.
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
No
No
Reset
operation
operation
Words:
Cycles:
1
2
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode
Read literal ‘n’
Process
Data
Write to
PC
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC
After Instruction
PC
TOS =
=
Address (HERE)
=
Address (Jump)
Address (HERE + 2)
© 2006 Microchip Technology Inc.
DS41159E-page 311
PIC18FXX8
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ] RETFIE [s]
Syntax:
[ label ] RETLW k
Operands:
Operation:
s ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W, Status
and BSR. If ‘s’ = 0, no update of these
registers occurs (default).
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Pop PC
from stack,
Write to W
No
operation
No
No
No
Words:
Cycles:
1
2
operation
operation
operation
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
Pop PC from
stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
Example:
RETFIE 1
After Interrupt
:
PC
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
RETLW kn
; End of table
W
BSR
Status
Before Instruction
W
=
0x07
GIE/GIEH, PEIE/GIEL
After Instruction
W
=
value of kn
DS41159E-page 312
© 2006 Microchip Technology Inc.
PIC18FXX8
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ] RETURN [s]
Syntax:
[ label ]
RLCF f [,d [,a]]
Operands:
Operation:
s ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
(STATUSS) → Status,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, Status and BSR. If ‘s’ = 0,
no update of these registers occurs
(default).
register f
C
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Decode
No
operation
Process
Data
Pop PC
from stack
Decode
Write to
destination
No
No
No
No
operation
operation
operation
operation
Example:
RLCF
REG, W
Before Instruction
Example:
RETURN
REG
C
=
=
1110 0110
0
After Interrupt
PC = TOS
After Instruction
REG
=
=
=
1110 0110
1100 1100
1
W
C
© 2006 Microchip Technology Inc.
DS41159E-page 313
PIC18FXX8
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ]
RLNCF f [,d [,a]]
Syntax:
[ label ] RRCF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG
Before Instruction
REG
After Instruction
Example:
RRCF
REG, W
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
=
=
1110 0110
0111 0011
0
W
C
DS41159E-page 314
© 2006 Microchip Technology Inc.
PIC18FXX8
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ] RRNCF f [,d [,a]]
Syntax:
[ label ] SETF f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ is ‘1’, then the bank will
be selected as per the BSR value
(default).
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
REG
After Instruction
REG
=
=
0x5A
0xFF
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
=
1110 1011
RRNCF REG, W
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2006 Microchip Technology Inc.
DS41159E-page 315
PIC18FXX8
SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
[ label ] SLEEP
None
Syntax:
[ label ] SUBFWB f [,d [,a]]
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
No
operation
Process
Data
Go to
Sleep
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
SLEEP
Example 1:
SUBFWB REG
Before Instruction
TO
PD
=
=
?
?
Before Instruction
REG
W
C
=
=
=
0x03
0x02
0x01
After Instruction
TO
PD
=
=
1 †
0
After Instruction
REG
W
C
=
0xFF
0x02
0x00
0x00
=
=
=
=
†
If WDT causes wake-up, this bit is cleared.
Z
N
0x01 ; result is negative
Example 2:
Before Instruction
SUBFWB
REG, 0, 0
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
=
2
3
1
0
0
=
=
=
=
Z
N
; result is positive
Example 3:
Before Instruction
SUBFWB
REG, 1, 0
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
DS41159E-page 316
© 2006 Microchip Technology Inc.
PIC18FXX8
SUBLW
Subtract W from Literal
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ] SUBLW
0 ≤ k ≤ 255
k
[ label ] SUBWF f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example 1:
SUBLW 0x02
Words:
Cycles:
1
1
Before Instruction
W
C
=
=
1
?
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
C
Z
=
1
=
=
=
1
0
0
; result is positive
Decode
Read
register ‘f’
Process
Data
Write to
destination
N
Example 1:
SUBWF REG
Example 2:
Before Instruction
SUBLW 0x02
Before Instruction
REG
W
=
3
2
?
W
C
=
=
2
?
=
=
C
After Instruction
After Instruction
W
C
Z
=
0
REG
W
C
Z
N
=
1
2
1
0
0
=
=
=
1
1
0
; result is zero
=
=
=
=
; result is positive
N
Example 3:
Before Instruction
SUBLW 0x02
Example 2:
SUBWF REG, W
W
C
=
=
3
?
Before Instruction
REG
W
C
=
=
=
2
2
?
After Instruction
W
C
Z
=
FF ; (2’s complement)
=
=
=
0
0
1
; result is negative
After Instruction
REG
W
C
=
2
0
1
1
0
N
=
=
=
=
; result is zero
Z
N
Example 3:
SUBWF REG
Before Instruction
REG
W
C
=
=
=
0x01
0x02
?
After Instruction
REG
W
C
=
0xFFh ;(2’s complement)
=
=
=
=
0x02
0x00 ; result is negative
0x00
0x01
Z
N
© 2006 Microchip Technology Inc.
DS41159E-page 317
PIC18FXX8
SUBWFB
Syntax:
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
[ label ] SWAPF f [,d [,a]]
[ label ] SUBWFB f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Operation:
(f) – (W) – (C) → dest
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
None
0101
10da
ffff
ffff
0011
10da
ffff
ffff
Description:
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per the
BSR value (default).
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default). If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Example:
SWAPF
REG
Before Instruction
Before Instruction
REG
=
=
=
0x19
0x0D
0x01
(0001 1001)
(0000 1101)
REG
=
0x53
0x35
W
C
After Instruction
After Instruction
REG
=
REG
W
=
0x0C
0x0D
0x01
0x00
0x00
(0000 1011)
(0000 1101)
=
=
=
=
C
Z
N
; result is positive
Example 2:
Before Instruction
SUBWFB REG, 0, 0
REG
=
=
=
0x1B
0x1A
0x00
(0001 1011)
(0001 1010)
W
C
After Instruction
REG
W
C
=
0x1B
0x00
0x01
0x01
0x00
(0001 1011)
=
=
=
=
Z
; result is zero
N
Example 3:
Before Instruction
SUBWFB REG, 1, 0
REG
=
=
=
0x03
0x0E
0x01
(0000 0011)
(0000 1101)
W
C
After Instruction
REG
=
0xF5
(1111 0100)
; [2’s comp]
W
=
=
=
=
0x0E
0x00
0x00
0x01
(0000 1101)
C
Z
N
; result is negative
DS41159E-page 318
© 2006 Microchip Technology Inc.
PIC18FXX8
TBLRD
Table Read
Syntax:
[ label ]
None
TBLRD ( *; *+; *-; +*)
Operands:
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) + 1 → TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) – 1 → TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to each
byte in the program memory. TBLPTR has a
2-Mbyte address range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
No
No operation
No
No operation
(Write
TABLAT)
operation (Read Program operation
Memory)
Example 1:
TBLRD *+ ;
Before Instruction
TABLAT
=
=
=
0x55
0x00A356
0x34
TBLPTR
MEMORY(0x00A356)
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
Example 2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
=
=
=
=
0xAA
0x01A357
0x12
MEMORY(0x01A357)
MEMORY(0x01A358)
After Instruction
0x34
TABLAT
TBLPTR
=
=
0x34
0x01A358
© 2006 Microchip Technology Inc.
DS41159E-page 319
PIC18FXX8
TBLWT
Table Write
TBLWT Table Write (Continued)
Syntax:
[ label ]
None
TBLWT ( *; *+; *-; +*)
Words: 1
Operands:
Operation:
Cycles: 2
if TBLWT*,
Q Cycle Activity:
(TABLAT) → Holding Register;
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register;
(TBLPTR) + 1 → TBLPTR;
if TBLWT*-,
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read
TABLAT)
No
No operation
(TABLAT) → Holding Register;
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
operation (Write to Holding
Register)
(TBLPTR) + 1 → TBLPTR;
(TABLAT) → Holding Register;
Example 1:
TBLWT *+;
Status Affected: None
Before Instruction
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
TABLAT
TBLPTR
=
=
0x55
0x00A356
HOLDING REGISTER
(0x00A356)
=
0xFF
After Instructions (table write completion)
TABLAT
=
=
0x55
Description:
This instruction uses the 3 LSBs of TBLPTR to
determine which of the 8 holding registers the
TABLAT is written to. The holding registers are
used to program the contents of Program
Memory (P.M.). (Refer to Section 6.0 “Flash
Program Memory” for additional details.)
The TBLPTR (a 21-bit pointer) points to each
byte in the program memory. TBLPTR has a
2-Mbyte address range. The LSb of the
TBLPTR selects which byte of the program
memory location to access.
TBLPTR
0x00A357
HOLDING REGISTER
(0x00A356)
=
0x55
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
=
=
0x34
0x01389A
HOLDING REGISTER
(0x01389A)
=
0xFF
0xFF
HOLDING REGISTER
(0x01389B)
=
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
After Instruction (table write completion)
Word
TABLAT
=
=
0x34
TBLPTR
0x01389B
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0xFF
0x34
Word
The TBLWT instruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
DS41159E-page 320
© 2006 Microchip Technology Inc.
PIC18FXX8
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] TSTFSZ f [,a]
Syntax:
[ label ] XORLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction. If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Example:
XORLW 0xAF
Before Instruction
Q Cycle Activity:
Q1
W
=
0xB5
0x1A
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
W
=
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
0x00,
Address (ZERO)
0x00,
Address (NZERO)
© 2006 Microchip Technology Inc.
DS41159E-page 321
PIC18FXX8
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS41159E-page 322
© 2006 Microchip Technology Inc.
PIC18FXX8
26.1 MPLAB Integrated Development
Environment Software
26.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• An interface to debugging tools
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
• Customizable data windows with direct edit of
contents
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
• High-level source code debugging
• Mouse over variable inspection
• Extensive on-line help
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
- MPLAB ICD 2
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
• Debug using:
- source files (assembly or C)
- mixed assembly and C
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
26.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
®
- KEELOQ Evaluation and Programming Tools
- PICDEM MSC
- microID® Developer Kits
- CAN
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol ref-
erence, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
- PowerSmart® Developer Kits
- Analog
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
© 2006 Microchip Technology Inc.
DS41159E-page 323
PIC18FXX8
26.3 MPLAB C17 and MPLAB C18
C Compilers
26.6 MPLAB ASM30 Assembler, Linker
and Librarian
The MPLAB C17 and MPLAB C18 Code Development
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Systems are complete ANSI
C
compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
26.4 MPLINK Object Linker/
MPLIB Object Librarian
• Rich directive set
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
• Flexible macro language
• MPLAB IDE compatibility
26.7 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execu-
tion can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
26.5 MPLAB C30 C Compiler
26.8 MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabili-
ties and afford fine control of the compiler code
generator.
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping and math functions (trigonometric, exponential
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
DS41159E-page 324
© 2006 Microchip Technology Inc.
PIC18FXX8
26.9 MPLAB ICE 2000
High-Performance Universal
26.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
In-Circuit Emulator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM
)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
26.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
26.10 MPLAB ICE 4000
High-Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
26.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
a large LCD display (128 x 64) for menus and error
messages and a modular detachable socket assembly
to support various package types. The ICSP™ cable
assembly is included as a standard item. In Stand-
Alone mode, the MPLAB PM3 device programmer can
read, verify and program PICmicro devices without a
PC connection. It can also set code protection in this
mode. MPLAB PM3 connects to the host PC via an RS-
232 or USB cable. MPLAB PM3 has high-speed com-
munications and optimized algorithms for quick pro-
gramming of large memory devices and incorporates
an SD/MMC card for file storage and secure data appli-
cations.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
© 2006 Microchip Technology Inc.
DS41159E-page 325
PIC18FXX8
26.14 PICSTART Plus Development
Programmer
26.17 PICDEM 2 Plus
Demonstration Board
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary hardware and software is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
26.15 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device program-
mer or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional appli-
cation components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
26.18 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
26.19 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low-power operation
with the supercapacitor circuit and jumpers allow on-
board hardware to be disabled to eliminate current
draw in this mode. Included on the demo board are pro-
visions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liquid crystal display, PCB footprints for
H-Bridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a proto-
typing area. Included with the kit is a PIC16F627A and
a PIC18F1320. Tutorial firmware is included along
with the User’s Guide.
26.16 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
DS41159E-page 326
© 2006 Microchip Technology Inc.
PIC18FXX8
26.20 PICDEM 17 Demonstration Board
26.24 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development pro-
grammer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
26.25 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
26.21 PICDEM 18R PIC18C601/801
Demonstration Board
• CAN developers kit for automotive network
applications
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
26.22 PICDEM LIN PIC16C43X
Demonstration Board
• PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
on-board LIN transceivers.
A PIC16F874 Flash
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN bus communication.
26.23 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit™
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC® microcontrollers. Powered via USB,
the board operates under a simple Windows GUI. The
PICkit 1 Starter Kit includes the User’s Guide (on CD
ROM), PICkit 1 tutorial software and code for various
applications. Also included are MPLAB® IDE (Integrated
Development Environment) software, software and
hardware “Tips 'n Tricks for 8-pin Flash PIC®
Microcontrollers” Handbook and a USB interface cable.
Supports all current 8/14-pin Flash PIC microcontrollers,
as well as many future planned devices.
© 2006 Microchip Technology Inc.
DS41159E-page 327
PIC18FXX8
NOTES:
DS41159E-page 328
© 2006 Microchip Technology Inc.
PIC18FXX8
27.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to VSS............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).......................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ................................................................................................... 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports (combined) ....................................................................................................200 mA
Maximum current sourced by all ports (combined) ...............................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
© 2006 Microchip Technology Inc.
DS41159E-page 329
PIC18FXX8
FIGURE 27-1:
PIC18FXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18FXX8
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 27-2:
PIC18FXX8 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18FXX8
4.2V
3.5V
3.0V
2.5V
2.0V
25 MHz
Frequency
DS41159E-page 330
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-3:
PIC18LFXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18LFXX8
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V = 40 MHz, if VDDAPPMIN > 4.2V
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
© 2006 Microchip Technology Inc.
DS41159E-page 331
PIC18FXX8
27.1 DC Characteristics
PIC18LFXX8
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18FXX8
(Industrial, Extended)
Param
No.
Characteristic/
Symbol
Min Typ Max Units
Conditions
Device
VDD
Supply Voltage
D001
D001
D002
PIC18LFXX8 2.0
PIC18FXX8 4.2
—
—
—
5.5
5.5
—
V
V
V
HS, XT, RC and LP Oscillator modes
VDR
RAM Data Retention
1.5
Voltage(1)
D003
D004
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
—
0.7
—
V
See section on Power-on Reset for details
SVDD
VBOR
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
V/ms See section on Power-on Reset for details
Brown-out Reset Voltage
PIC18LFXX8
D005
D005
BORV1:BORV0 = 11 1.96
BORV1:BORV0 = 10 2.64
BORV1:BORV0 = 01 4.07
BORV1:BORV0 = 00 4.36
PIC18FXX8
—
—
—
—
2.16
2.92
4.59
4.92
V
V
V
V
BORV1:BORV0 = 1x N.A.
BORV1:BORV0 = 01 4.07
BORV1:BORV0 = 00 4.36
—
—
—
N.A.
4.59
4.92
V
V
V
Not in operating voltage range of device
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kOhm.
5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
DS41159E-page 332
© 2006 Microchip Technology Inc.
PIC18FXX8
27.1 DC Characteristics (Continued)
PIC18LFXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18FXX8
(Industrial, Extended)
Param
Symbol
No.
Characteristic/
Device
Min Typ Max Units
Conditions
IDD
Supply Current(2,3,4)
D010
PIC18LFXX8
XT oscillator configuration
—
—
—
.7
.7
1.7
2
2
4
mA VDD = 2.0V, +25°C, FOSC = 4 MHz
mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
RC oscillator configuration
—
—
—
1
1
2.5
2.5
2.5
5
mA VDD = 2.0V, +25°C, FOSC = 4 MHz
mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
RCIO oscillator configuration
—
—
—
.7
.7
1.8
2.5
2.5
4
mA VDD = 2.0V, +25°C, FOSC = 4 MHz
mA VDD = 2.0V, -40°C to +85°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
D010
PIC18FXX8
XT oscillator configuration
—
—
—
1.7
1.7
1.7
4
4
4
mA VDD = 4.2V, +25°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz
RC oscillator configuration
—
—
—
2.5
2.5
2.5
5
5
6
mA VDD = 4.2V, +25°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz
RCIO oscillator configuration
—
—
—
1.8
1.8
1.8
4
5
5
mA VDD = 4.2V, +25°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +85°C, FOSC = 4 MHz
mA VDD = 4.2V, -40°C to +125°C, FOSC = 4 MHz
D010A
D010A
PIC18LFXX8
PIC18FXX8
LP oscillator, FOSC = 32 kHz, WDT disabled
μA VDD = 2.0V, -40°C to +85°C
—
18
40
LP oscillator, FOSC = 32 kHz, WDT disabled
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +125°C
—
—
60
60
150
180
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kOhm.
5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
© 2006 Microchip Technology Inc.
DS41159E-page 333
PIC18FXX8
27.1 DC Characteristics (Continued)
PIC18LFXX8
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18FXX8
(Industrial, Extended)
Param
Symbol
No.
Characteristic/
Device
Min Typ Max Units
Conditions
IDD
Supply Current(2,3,4)
D010C
D010C
PIC18LFXX8
EC, ECIO oscillator configurations
mA VDD = 4.2V, -40°C to +85°C
—
—
21
21
28
30
PIC18FXX8
EC, ECIO oscillator configurations
mA VDD = 4.2V, -40°C to +125°C,
FOSC = 25 MHz
D013
D013
PIC18LFXX8
HS oscillator configurations
mA FOSC = 6 MHz, VDD = 2.0V
mA FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configuration
—
—
1.3
18
3
28
—
28
40
mA FOSC = 10 MHz, VDD = 5.5V
PIC18FXX8
HS oscillator configurations
mA FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configuration
—
—
18
28
28
40
mA FOSC = 10 MHz, VDD = 5.5V
D014
D014
PIC18LFXX8
PIC18FXX8
Timer1 oscillator configuration
μA FOSC = 32 kHz, VDD = 2.0V
—
32
65
Timer1 oscillator configuration
—
—
62
62
250
310
μA FOSC = 32 kHz, VDD = 4.2V, -40°C to +85°C
μA FOSC = 32 kHz, VDD = 4.2V, -40°C to +125°C
IPD
Power-Down Current(3)
D020
PIC18LFXX8
—
—
0.3
2
4
10
μA VDD = 2.0V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +85°C
D020
PIC18FXX8
—
—
2
6
10
40
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +125°C
D021B
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kOhm.
5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
DS41159E-page 334
© 2006 Microchip Technology Inc.
PIC18FXX8
27.1 DC Characteristics (Continued)
PIC18LFXX8
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC18FXX8
(Industrial, Extended)
Param
Symbol
No.
Characteristic/
Device
Min Typ Max Units
Conditions
ΔIWDT
Module Differential Current
D022
D022
Watchdog Timer
—
—
—
0.75 1.5
μA VDD = 2.5V, +25°C
μA VDD = 2.0V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, +25°C
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +125°C
μA VDD = 2.0V, +25°C
μA VDD = 2.0V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, +25°C
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +125°C
μA VDD = 2.0V, +25°C
μA VDD = 2.0V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, +25°C
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +125°C
PIC18LFXX8
0.8
7
8
25
Watchdog Timer
—
—
—
7
7
7
25
25
45
PIC18FXX8
D022A ΔIBOR
D022A
Brown-out Reset(5)
—
—
—
38
42
49
50
55
65
PIC18LFXX8
Brown-out Reset(5)
—
—
—
46
49
50
65
65
75
PIC18FXX8
D022B ΔILVD
D022B
Low-Voltage Detect(5)
—
—
—
36
40
47
50
55
65
PIC18LFXX8
Low-Voltage Detect(5)
—
—
—
44
47
47
65
65
75
PIC18FXX8
D025
D025
ΔITMR1
Timer1 Oscillator
—
—
—
6.2
6.2
7.5
40
45
55
μA VDD = 2.0V, +25°C
μA VDD = 2.0V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, +25°C
μA VDD = 4.2V, -40°C to +85°C
μA VDD = 4.2V, -40°C to +125°C
PIC18LFXX8
Timer1 Oscillator
—
—
—
7.5
7.5
7.5
55
55
65
PIC18FXX8
Legend: Rows are shaded for improved readability.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS
and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...).
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2 REXT (mA) with REXT in kOhm.
5: The LVD and BOR modules share a large portion of circuitry. The ΔIBOR and ΔILVD currents are not
additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
© 2006 Microchip Technology Inc.
DS41159E-page 335
PIC18FXX8
27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended)
PIC18LFXX8 (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
Characteristic/
Device
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
D030
D030A
D031
with TTL buffer
VSS
—
0.15 VDD
0.8
V
V
VDD < 4.5V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
0.2 VDD
0.3 VDD
V
V
D032
MCLR
VSS
VSS
0.2 VDD
0.3 VDD
V
V
D032A
OSC1 (in XT, HS and LP modes)
and T1OSI
D033
OSC1 (in RC mode)(1)
Input High Voltage
I/O ports:
VSS
0.2 VDD
V
VIH
D040
D040A
D041
with TTL buffer
0.25 VDD + 0.8V
2.0
VDD
VDD
V
V
VDD < 4.5V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
0.8 VDD
0.7 VDD
VDD
VDD
V
V
D042
MCLR
0.8 VDD
0.7 VDD
VDD
VDD
V
V
D042A
OSC1 (in XT, HS and LP modes)
and T1OSI
D043
D060
OSC1 (RC mode)(1)
Input Leakage Current(2,3)
I/O ports
0.9 VDD
—
VDD
1
V
IIL
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
D063
MCLR
—
—
5
5
μA Vss ≤ VPIN ≤ VDD
μA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070 IPURB
50
450
μA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS41159E-page 336
© 2006 Microchip Technology Inc.
PIC18FXX8
27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended)
PIC18LFXX8 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic/
Device
Min
Max
Units
Conditions
VOL
Output Low Voltage
D080
I/O ports
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.2V,
-40°C to +85°C
D080A
D083
IOL = 7.0 mA, VDD = 4.2V,
-40°C to +125°C
OSC2/CLKO
(RC mode)
IOL = 1.6 mA, VDD = 4.2V,
-40°C to +85°C
D083A
IOL = 1.2 mA, VDD = 4.2V,
-40°C to +125°C
VOH
Output High Voltage(3)
D090
I/O ports
VDD – 0.7
VDD – 0.7
VDD – 0.7
VDD – 0.7
—
—
—
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.2V,
-40°C to +85°C
D090A
D092
IOH = -2.5 mA, VDD = 4.2V,
-40°C to +125°C
OSC2/CLKO
(RC mode)
—
IOH = -1.3 mA, VDD = 4.2V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.2V,
-40°C to +125°C
D092A
—
D150 VOD
Open-Drain High Voltage
7.5
RA4 pin
Capacitive Loading Specs on
Output Pins
D101 CIO
D102 CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC Timing
Specifications
pF In I2C™ mode
SCL, SDA
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
© 2006 Microchip Technology Inc.
DS41159E-page 337
PIC18FXX8
FIGURE 27-4:
LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
37
LVDIF
TABLE 27-1: LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Low-Voltage Detect Characteristics
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
D420 VLVD
LVD Voltage
LVV = 0001
LVV = 0010
LVV = 0011
LVV = 0100
LVV = 0101
LVV = 0110
LVV = 0111
LVV = 1000
LVV = 1001
LVV = 1010
LVV = 1011
LVV = 1100
LVV = 1101
LVV = 1110
1.96
2.16
2.35
2.43
2.64
2.75
2.95
3.24
3.43
3.53
3.72
3.92
4.07
4.36
2.06
2.27
2.47
2.58
2.78
2.89
3.1
2.16
2.38
2.59
2.69
2.92
3.03
3.26
3.58
3.79
3.91
4.12
4.34
4.59
4.92
V
V
V
V
V
V
V
V
V
V
V
V
V
V
T ≥ 25°C
T ≥ 25°C
T ≥ 25°C
3.41
3.61
3.72
3.92
4.13
4.33
4.64
DS41159E-page 338
© 2006 Microchip Technology Inc.
PIC18FXX8
TABLE 27-2: DC CHARACTERISTICS: EEPROM AND ENHANCED FLASH
DC Characteristics
Standard Operating Conditions
Param
Sym
No.
Characteristic
Min
Typ†
Max Units
Conditions
Internal Program Memory
Programming Specifications
D110
D113
VPP
Voltage on MCLR/VPP pin
9.00
—
—
—
13.25
10
V
IDDP
Supply Current during
Programming
mA
Data EEPROM Memory
Cell Endurance
D120
ED
100K
10K
1M
100K
—
—
—
E/W -40°C to +85°C
E/W +85°C to +125°C
D120A ED
Byte Endurance
D121
VDRW VDD for Read/Write
VMIN
5.5
V
Using EECON to read/write
VMIN = Minimum operating voltage
D122
D123
TDEW Erase/Write Cycle Time
TRETD Characteristic Retention
—
4
—
—
ms
40
—
Year Provided no other specifications
are violated
D124
TREF
Number of Total Erase/Write
Cycles to Data EEPROM before
Refresh*
1M
10M
1M
—
—
Cycles -40°C to +85°C
D124A TREF Number of Total Erase/Write
Cycles before Refresh*
100K
Cycles +85°C to +125°C
Program Flash Memory
D130
EP
Cell Endurance
Cell Endurance
VDD for Read
10K
1000
VMIN
4.5
100K
10K
—
—
—
E/W -40°C to +85°C
E/W +85°C to +125°C
D130A EP
D131
D132
VPR
VIE
5.5
5.5
5.5
V
V
V
VMIN = Minimum operating voltage
Using ICSP™ port
VDD for Block Erase
—
D132A VIW
VDD for Externally Timed Erase
or Write
4.5
—
Using ICSP port
D132B VPEW VDD for Self-Timed Write
VMIN
—
—
4
5.5
—
V
VMIN = Minimum operating voltage
D133
TIE
ICSP Erase Cycle Time
ms VDD ≥ 4.5V
ms VDD ≥ 4.5V
D133A TIW
ICSP Erase or Write Cycle Time
(externally timed)
1
—
—
D133A TIW
Self-Timed Write Cycle Time
—
2
—
—
ms
D134
TRETD Characteristic Retention
40
—
Year Provided no other specifications
are violated
†
*
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
See Section 5.8 “Using the Data EEPROM” for more information.
© 2006 Microchip Technology Inc.
DS41159E-page 339
PIC18FXX8
TABLE 27-3: COMPARATOR SPECIFICATIONS
Operating Conditions: VDD range as described in Section 27.1 “DC Characteristics”, -40°C < TA < +125°C
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
D300
VIOFF
Input Offset Voltage
Input Common Mode Voltage
CMRR CMRR
—
0
5.0
—
10
VDD – 1.5
—
mV
V
D301
D302
D300
VICM
+55*
—
—
db
TRESP
Response Time(1)
300*
350*
400*
600*
ns
ns
PIC18FXX8
PIC18LFXX8
D301
TMC2OV Comparator Mode Change to
Output Valid
—
—
10*
μs
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from
VSS to VDD.
TABLE 27-4: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: VDD range as described in Section 27.1 “DC Characteristics”, -40°C < TA < +125°C
Param No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
D311
D312
D310
*
VRES
VDD/24
—
—
—
VDD/32
0.5
LSB
LSB
Ω
VRAA
VRUR
TSET
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
—
2K*
—
—
—
10*
μs
These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1and CVR<3:0> transitions from 0000to 1111.
DS41159E-page 340
© 2006 Microchip Technology Inc.
PIC18FXX8
27.3 AC (Timing) Characteristics
27.3.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-Impedance)
Low
Valid
L
High-Impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
Hold
SU
Setup
DAT
STA
DATA input hold
Start condition
STO
Stop condition
© 2006 Microchip Technology Inc.
DS41159E-page 341
PIC18FXX8
27.3.2
TIMING CONDITIONS
The temperature and voltages specified in Table 27-5
apply to all timing specifications unless otherwise
noted. Figure 27-5 specifies the load conditions for the
timing specifications.
TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC specification,
AC CHARACTERISTICS
Section 27.1 “DC Characteristics”.
LF parts operate for industrial temperatures only.
FIGURE 27-5:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
DS41159E-page 342
© 2006 Microchip Technology Inc.
PIC18FXX8
27.3.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-6:
EXTERNAL CLOCK TIMING
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
CLKO
3
4
3
2
TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
Oscillator Frequency(1)
DC
DC
DC
0.1
4
40
25
MHz EC, ECIO oscillator, -40°C to +85°C
MHz EC, ECIO oscillator, +85°C to +125°C
MHz RC oscillator
4
4
MHz XT oscillator
25
MHz HS oscillator, -40°C to +85°C
MHz HS oscillator, +85°C to +125°C
MHz HS + PLL oscillator, -40°C to +85°C
MHz HS + PLL oscillator, +85°C to +125°C
kHz LP oscillator
4
25
4
10
4
6.25
200
—
DC
25
40
250
250
40
40
100
160
5
1
TOSC
External CLKI Period(1)
Oscillator Period(1)
ns EC, ECIO oscillator, -40°C to +85°C
ns EC, ECIO oscillator, +85°C to +125°C
ns RC oscillator
—
—
10,000
—
ns XT oscillator
ns HS oscillator, -40°C to +85°C
ns HS oscillator, +85°C to +125°C
ns HS + PLL oscillator, -40°C to +85°C
ns HS + PLL oscillator, +85°C to +125°C
μs LP oscillator
—
250
250
200
2
3
TCY
Instruction Cycle Time(1)
100
160
—
—
ns TCY = 4/FOSC, -40°C to +85°C
ns TCY = 4/FOSC, +85°C to +125°C
TosL,
TosH
External Clock in (OSC1)
High or Low Time
30
2.5
10
—
—
—
ns XT oscillator
ns LP oscillator
μs HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
—
4
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
20
50
7.5
—
—
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
© 2006 Microchip Technology Inc.
DS41159E-page 343
PIC18FXX8
TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)
Param No. Sym
Characteristic
Min
Typ†
Max
Units
Conditions
—
—
—
—
FOSC Oscillator Frequency Range
4
—
—
—
—
10
40
2
MHz HS mode only
FSYS On-Chip VCO System Frequency
16
—
-2
MHz HS mode only
trc
PLL Start-up Time (Lock Time)
ms
%
ΔCLK CLKO Stability (Jitter)
+2
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 27-7:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
12
13
14
19
18
16
I/O Pin
(Input)
15
17
I/O Pin
(Output)
New Value
Old Value
20, 21
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS
Param No. Symbol
Characteristic
TosH2ckL OSC1 ↑ to CLKO ↓
TosH2ckH OSC1 ↑ to CLKO ↑
Min
Typ
Max
Units Conditions
10
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
—
10
—
10
—
—
—
—
200
200
100
100
ns
ns
ns
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
11
12
TckR
TckF
CLKO Rise Time
CLKO Fall Time
13
14
TckL2ioV CLKO ↓ to Port Out Valid
TioV2ckH Port In Valid before CLKO ↑
TckH2ioI Port In Hold after CLKO ↑
TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
0.5 TCY + 20 ns
15
0.25 TCY + 25
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
0
—
17
150
—
18
TosH2ioI OSC1 ↑ (Q2 cycle) to Port
PIC18FXX8
PIC18LFXX8
100
200
0
Input Invalid (I/O in hold time)
18A
19
—
TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time)
—
20
TIOR
Port Output Rise Time
Port Output Fall Time
INT pin High or Low Time
PIC18FXX8
PIC18LFXX8
PIC18FXX8
PIC18LFXX8
—
25
60
25
60
—
20A
21
—
TIOF
—
21A
22†
23†
24†
—
TINP
TCY
TCY
20
TRBP
TRCP
RB7:RB4 Change INT High or Low Time
RC7:RC4 Change INT High or Low Time
—
—
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKO pin output is 4 x TOSC.
DS41159E-page 344
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 27-5 for load conditions.
FIGURE 27-9:
BROWN-OUT RESET AND LOW-VOLTAGE DETECT TIMING
BVDD (for 35)
VDD
VLVD (for 37)
35, 37
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 27-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
BROWN-OUT RESET AND LOW-VOLTAGE DETECT REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
7
—
—
μs
31
Watchdog Timer Time-out Period
(no prescaler)
18
33
ms
32
33
34
TOST
Oscillation Start-up Timer Period
Power-up Timer Period
1024 TOSC
—
72
2
1024 TOSC
—
ms
μs
TOSC = OSC1 period
TPWRT
28
—
132
—
TIOZ
I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
μs
μs
For VDD ≤ BVDD (see D005)
For VDD ≤ VLVD (see D420)
TIRVST
Time for Internal Reference
Voltage to become stable
20
50
37
TLVD
Low-Voltage Detect Pulse Width
200
—
—
μs
© 2006 Microchip Technology Inc.
DS41159E-page 345
PIC18FXX8
FIGURE 27-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
Tt0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or TCY + 40
N
ns N = prescale value
(1, 2, 4,..., 256)
45
46
Tt1H
Tt1L
T1CKI
High Time
Synchronous, no prescaler
0.5 TCY + 20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Synchronous, PIC18FXX8
10
with prescaler
PIC18LFXX8
25
—
Asynchronous PIC18FXX8
PIC18LFXX8
30
—
50
0.5 TCY + 5
10
—
T1CKI
Low Time
Synchronous, no prescaler
Synchronous, PIC18FXX8
—
—
with prescaler
PIC18LFXX8
25
—
Asynchronous PIC18FXX8
PIC18LFXX8
30
—
TBD
TBD
—
47
48
Tt1P
Ft1
T1CKI
Input Period
Synchronous
Greater of:
20 ns or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T1CKI Oscillator Input Frequency Range
Tcke2tmrI Delay from External T1CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
Legend: TBD = To Be Determined
DS41159E-page 346
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND ECCP1)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-11: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND ECCP1)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TccL
CCPx Input Low Time No prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
With
prescaler
PIC18FXX8
PIC18LFXX8
10
20
51
TccH
CCPx Input High Time No prescaler
0.5 TCY + 20
With
PIC18FXX8
10
20
prescaler
PIC18LFXX8
52
53
TccP
TccR
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
CCPx Output Fall Time
PIC18FXX8
PIC18LFXX8
PIC18FXX8
PIC18LFXX8
—
—
—
—
25
45
25
45
ns
ns
ns
ns
54
TccF
CCPx Output Fall Time
© 2006 Microchip Technology Inc.
DS41159E-page 347
PIC18FXX8
FIGURE 27-12:
PARALLEL SLAVE PORT TIMING (PIC18F248 AND PIC18F458)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-12: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F248 AND PIC18F458)
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH Data-In Valid before WR ↑ or CS ↑
20
25
—
—
ns
(setup time)
ns Extended Temp. range
63
64
TwrH2dtI
WR ↑ or CS ↑ to Data-In Invalid PIC18FXX8
20
35
—
—
ns
ns
(hold time)
PIC18LFXX8
TrdL2dtV RD ↓ and CS ↓ to Data-Out Valid
—
—
80
90
ns
ns Extended Temp. range
65
66
TrdH2dtI
TibfINH
RD ↑ or CS ↓ to Data-Out Invalid
10
—
30
ns
ns
Inhibit the IBF flag bit being cleared from
3 TCY
WR ↑ or CS ↑
DS41159E-page 348
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-13:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
Bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
Bit 6 - - - -1
LSb In
73
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-13: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
ns
71
TscH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TscL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
ns
75
TdoR
SDO Data Output Rise Time PIC18FXX8
PIC18LFXX8
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO Data Output Fall Time
SCK Output Rise Time
(Master mode)
PIC18FXX8
PIC18LFXX8
79
80
TscF
SCK Output Fall Time (Master mode)
TscH2doV, SDO Data Output Valid after PIC18FXX8
TscL2doV SCK Edge
PIC18LFXX8
Note 1: Requires the use of parameter #73A.
2: Only if parameter #71A and #72A are used.
© 2006 Microchip Technology Inc.
DS41159E-page 349
PIC18FXX8
FIGURE 27-14:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
Bit 6 - - - - - -1
SDO
SDI
75, 76
MSb In
74
LSb In
Bit 6 - - - -1
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-14: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param
No.
Symbol
TscH
TscL
Characteristic
Min
Max Units Conditions
71
SCK Input High Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
ns
75
TdoR
SDO Data Output Rise Time PIC18FXX8
PIC18LFXX8
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO Data Output Fall Time
—
SCK Output Rise Time
(Master mode)
PIC18FXX8
—
PIC18LFXX8
—
79
80
TscF
SCK Output Fall Time (Master mode)
—
TscH2doV, SDO Data Output Valid after PIC18FXX8
TscL2doV SCK Edge
—
PIC18LFXX8
—
81
TdoV2scH, SDO Data Output Setup to SCK Edge
TdoV2scL
TCY
Note 1: Requires the use of parameter #73A.
2: Only if parameter #71A and #72A are used.
DS41159E-page 350
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-15:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
SDO
SDI
MSb
Bit 6 - - - - - -1
LSb
77
75, 76
MSb In
74
Bit 6 - - - -1
LSb In
73
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-15: EXAMPLE SPI™ MODE REQUIREMENTS, SLAVE MODE TIMING (CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
ns
71
TscH
SCK Input High Time (Slave mode)
SCK Input Low Time (Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TscL
ns
72A
73
ns (Note 1)
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
ns
75
TdoR
SDO Data Output Rise Time
PIC18FXX8
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LFXX8
76
77
78
TdoF
SDO Data Output Fall Time
—
10
—
TssH2doZ SS ↑ to SDO Output High-Impedance
TscR
SCK Output Rise Time (Master mode) PIC18FXX8
PIC18LFXX8
79
80
TscF
SCK Output Fall Time (Master mode)
—
—
TscH2doV, SDO Data Output Valid after SCK
TscL2doV Edge
PIC18FXX8
PIC18LFXX8
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of parameter #73A.
2: Only if parameter #71A and #72A are used.
© 2006 Microchip Technology Inc.
DS41159E-page 351
PIC18FXX8
FIGURE 27-16:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
LSb
MSb
Bit 6 - - - - - -1
SDO
SDI
77
75, 76
MSb In
74
Bit 6 - - - -1
LSb In
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-16: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
ns
71
TscH
TscL
TB2B
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCK Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
75
TdoR
SDO Data Output Rise Time
PIC18FXX8
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LFXX8
—
76
77
78
TdoF
SDO Data Output Fall Time
—
TssH2doZ SS ↑ to SDO Output High-Impedance
10
TscR
SCK Output Rise Time
(Master mode)
PIC18FXX8
—
PIC18LFXX8
—
79
80
TscF
SCK Output Fall Time (Master mode)
—
TscH2doV, SDO Data Output Valid after SCK
TscL2doV Edge
PIC18FXX8
PIC18LFXX8
PIC18FXX8
PIC18LFXX8
—
—
82
83
TssL2doV SDO Data Output Valid after SS ↓
—
—
Edge
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of parameter #73A.
2: Only if parameter #71A and #72A are used.
DS41159E-page 352
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-17:
I2C™ BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-17: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
FIGURE 27-18:
I2C™ BUS DATA TIMING
103
102
100
101
106
SCL
90
107
92
91
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 27-5 for load conditions.
© 2006 Microchip Technology Inc.
DS41159E-page 353
PIC18FXX8
TABLE 27-18: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time
100 kHz mode
4.0
—
—
μs
μs
PIC18FXX8 must operate
at a minimum of 1.5 MHz
400 kHz mode
0.6
PIC18FXX8 must operate
at a minimum of 10 MHz
SSP Module
1.5 TCY
4.7
—
—
101
TLOW
Clock Low Time
100 kHz mode
μs
μs
PIC18FXX8 must operate
at a minimum of 1.5 MHz
400 kHz mode
SSP module
1.3
—
PIC18FXX8 must operate
at a minimum of 10 MHz
1.5 TCY
—
—
ns
ns
ns
102
103
TR
TF
SDA and SCL Rise 100 kHz mode
Time
1000
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
SDA and SCL Fall 100 kHz mode
Time
—
300
ns
ns
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
90
TSU:STA
THD:STA
Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
Only relevant for Repeated
Start condition
91
Start Condition
Hold Time
—
After this period the first
clock pulse is generated
—
106
107
92
THD:DAT Data Input Hold
Time
—
0
0.9
—
TSU:DAT
TSU:STO
TAA
Data Input Setup
Time
250
100
4.7
0.6
—
(Note 2)
—
Stop Condition
Setup Time
—
—
109
110
Output Valid from
Clock
3500
—
(Note 1)
—
TBUF
Bus Free Time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
D102
CB
Bus Capacitive Loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement
TSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output
the next data bit to the SDA line.
Before the SCL line is released, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard
mode I2C bus specification).
DS41159E-page 354
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-19:
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-19: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 27-20:
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 27-5 for load conditions.
© 2006 Microchip Technology Inc.
DS41159E-page 355
PIC18FXX8
TABLE 27-20: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
2(TOSC)(BRG + 1)
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
101
102
103
90
TLOW
TR
Clock Low Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
SDA and SCL
Rise Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
1000
300
300
300
300
100
—
CB is specified to be
from 10 to 400 pF
20 + 0.1 CB
ns
—
ns
TF
SDA and SCL
Fall Time
—
ns
CB is specified to be
from 10 to 400 pF
20 + 0.1 CB
ns
—
ns
TSU:STA
THD:STA
Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
ms Only relevant for
Setup Time
Repeated Start
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
condition
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
91
Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
—
ms After this period, the
Hold Time
first clock pulse is
generated
ms
400 kHz mode
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
2(TOSC)(BRG + 1)
—
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
0
—
ns
0
0.9
—
ms
TSU:DAT
Data Input
250
ns
ns
(Note 2)
Setup Time
100
—
TSU:STO
Stop Condition
Setup Time
2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
2(TOSC)(BRG + 1)
—
2(TOSC)(BRG + 1)
—
109
110
TAA
Output Valid
from Clock
—
—
3500
1000
—
ns
—
ns
TBUF
Bus Free Time
4.7
1.3
—
ms
ms
Time the bus must be
free before a new
transmission can start
—
D102 CB
Bus Capacitive Loading
—
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the low period of the SCL
signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the
SDA line.
Before the SCL line is released, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode).
DS41159E-page 356
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-21:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 27-5 for load conditions.
122
TABLE 27-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TckH2dtV SYNC XMIT (Master & Slave)
Clock High to Data-Out Valid
PIC18FXX8
—
—
—
—
—
—
50
150
25
ns
ns
ns
ns
ns
ns
PIC18LFXX8
121
122
Tckrf
Tdtrf
Clock Out Rise Time and Fall Time PIC18FXX8
(Master mode)
PIC18LFXX8
60
Data-Out Rise Time and Fall Time
PIC18FXX8
25
PIC18LFXX8
60
FIGURE 27-22:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (Master & Slave)
Data-Hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
Data-Hold after CK ↓ (DT hold time)
© 2006 Microchip Technology Inc.
DS41159E-page 357
PIC18FXX8
TABLE 27-23: A/D CONVERTER CHARACTERISTICS: PIC18FXX8 (INDUSTRIAL, EXTENDED)
PIC18LFXX8 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
A01
NR
Resolution
—
—
—
—
—
—
10
< 1
bit VREF = VDD ≥ 3.0V
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD ≥ 3.0V
A03
A04
A05
A06
A10
A20
A20A
A21
A22
A25
A30
EIL
Integral Linearity Error
Differential Linearity Error
Full Scale Error
—
EDL
EFS
EOFF
—
—
< 1
—
< 1
Offset Error
Monotonicity(3)
—
< 1.5
guaranteed
—
V
VSS ≤ VAIN ≤ VREF
VREF
Reference Voltage
(VREFH – VREFL)
0V
3V
—
—
—
—
V
For 10-bit resolution
VREFH
VREFL
VAIN
Reference Voltage High
Reference Voltage Low
Analog Input Voltage
VSS
—
—
—
—
VDD + 0.3V
VDD
V
VSS – 0.3V
VSS – 0.3V
—
V
VREF + 0.3V
10.0
V
ZAIN
Recommended Impedance of
Analog Voltage Source
kΩ
A40
A50
IAD
A/D Conversion PIC18FXX8
—
—
180
90
—
—
μA Average current
Current (VDD)
consumption when
PIC18LFXX8
μA
A/D is on (Note 1)
IREF
VREF Input Current (Note 2)
0
—
5
μA During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To
charge CHOLD.
—
—
150
μA During A/D conversion
cycle.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
specification includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or VDD and VSS pins, whichever is selected
as reference input.
2: VSS ≤ VAIN ≤ VREF
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
DS41159E-page 358
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 27-23:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
TABLE 27-24: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/d Clock Period
PIC18FXX8
1.6
3.0
2.0
3.0
11
20(5)
20(5)
6.0
μs TOSC based, VREF ≥ 3.0V
μs TOSC based, VREF full range
μs A/D RC mode
PIC18LFXX8
PIC18FXX8
PIC18LFXX8
9.0
μs A/D RC mode
131
132
TCNV
TACQ
Conversion Time
(not including acquisition time) (Note 1)
Acquisition Time (Note 3)
12
TAD
15
10
—
—
μs -40°C ≤ Temp ≤ +125°C
μs 0°C ≤ Temp ≤ +125°C
135
136
TSWC
TAMP
Switching Time from Convert → Sample
Amplifier Settling Time (Note 2)
—
1
(Note 4)
—
μs This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 20.0 “Compatible 10-Bit Analog-to-Digital Converter (A/D) Module” for minimum
conditions when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS or AVSS to AVDD). The source impedance (RS) on the input channels
is 50Ω.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
© 2006 Microchip Technology Inc.
DS41159E-page 359
PIC18FXX8
NOTES:
DS41159E-page 360
© 2006 Microchip Technology Inc.
PIC18FXX8
28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean – 3σ)
respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 28-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
24
5.5V
5.0V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
22
20
18
16
14
12
10
8
4.5V
4.0V
3.5V
6
3.0V
4
2.5V
2
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 28-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
28
26
24
22
20
18
16
14
12
10
8
5.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.0V
4.5V
4.0V
3.5V
3.0V
6
4
2.5V
2
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
© 2006 Microchip Technology Inc.
DS41159E-page 361
PIC18FXX8
FIGURE 28-3:
TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
26
24
22
20
18
16
14
12
10
8
5.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.0V
4.5V
4.2V
6
4
2
0
4
5
6
7
8
9
10
FOSC (MHz)
FIGURE 28-4:
MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE)
28
26
24
22
20
18
16
14
12
10
8
5.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.0V
4.5V
4.2V
6
4
2
0
4
5
6
7
8
9
10
FOSC (MHz)
DS41159E-page 362
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 28-5:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
3.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
3.0
2.5
2.0
1.5
1.0
0.5
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.0
0.5
1.0
1.5
2.0
(MHz)
2.5
3.0
3.5
4.0
F
OSC
FIGURE 28-6:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
4.0
5.5V
5.0V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
© 2006 Microchip Technology Inc.
DS41159E-page 363
PIC18FXX8
FIGURE 28-7:
TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
700
5.5V
5.0V
4.5V
600
500
400
300
200
4.0V
3.5V
3.0V
2.5V
2.0V
Typical:
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
statistical mean @ 25°C
100
0
20
30
40
50
60
70
80
90
100
FOSC (kHz)
FIGURE 28-8:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
900
800
700
600
500
400
300
200
100
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0
20
30
40
50
60
70
80
90
100
FOSC (kHz)
DS41159E-page 364
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 28-9:
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
24
22
5.5V
5.0V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
20
18
16
14
12
10
8
4.5V
4.2V
4.0V
3.5V
6
3.0V
4
2.5V
2
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 28-10:
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
28
26
5.5V
5.0V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
24
22
20
18
16
14
12
10
8
4.5V
4.2V
4.0V
3.5V
3.0V
6
4
2.5V
2
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
© 2006 Microchip Technology Inc.
DS41159E-page 365
PIC18FXX8
FIGURE 28-11:
TYPICAL AND MAXIMUM IDD vs. VDD
(TIMER1 AS MAIN OSCILLATOR 32.768 kHz, C1 AND C2 = 47 pF)
1200
1000
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-10°C to +70°C)
Minimum: mean – 3σ (-10°C to +70°C)
800
600
400
200
0
Max (70°C)
Typ (25°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 28-12:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 20 pF, +25°C)
4,500
4,000
3,500
3,000
2,500
2,000
1,500
1,000
500
Operation above 4 MHz is not recommended.
Ω
3.3k
Ω
5.1k
Ω
10k
Ω
100k
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41159E-page 366
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 28-13:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, +25°C)
2,000
1,800
1,600
1,400
1,200
1,000
800
Ω
3.3k
Ω
5.1k
600
Ω
10k
400
200
Ω
100k
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 28-14:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, +25°C)
800
700
600
500
400
300
200
100
Ω
Ω
3.3k
5.1k
Ω
10k
Ω
100k
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2006 Microchip Technology Inc.
DS41159E-page 367
PIC18FXX8
FIGURE 28-15:
IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED)
100
Max
(-40°C to +125°C)
10
Max
(+85°C)
1
Typ (+25°C)
0.1
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VD D (V)
FIGURE 28-16:
ΔIBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00-2.16V)
90
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
80
70
60
50
40
30
20
10
0
Minimum: mean – 3σ (-40°C to +125°C)
Max (+125°C)
Device
Held in
Reset
Max (+85°C)
Typ (+25°C)
C
Device
in
Sleep
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41159E-page 368
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 28-17:
TYPICAL AND MAXIMUM ΔITMR1 vs. VDD OVER TEMPERATURE (-10°C TO +70°C,
TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF)
14
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-10°C to +70°C)
Minimum: mean – 3σ (-10°C to +70°C)
12
10
8
Max (+70°C)
Typ (+25°C)
Typ (25C)
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 28-18:
TYPICAL AND MAXIMUM ΔIWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)
70
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
60
50
40
30
20
10
0
Max (+125°C)
x
Max (+85°C)
Typ (+25°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2006 Microchip Technology Inc.
DS41159E-page 369
PIC18FXX8
FIGURE 28-19:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C)
50
Typical:
statistical mean @ 25°C
45
40
35
30
25
20
15
10
5
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Max
(+125°C)
Max
(+85°C)
Typ
Typ
(+25°C)
Min
(-40°C)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 28-20:
ΔILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5 - 4.78V)
90
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
80
70
60
50
40
30
20
10
0
Minimum: mean – 3σ (-40°C to +125°C)
Max (+125°C)
Max (+125°C)
Typ (+25°C)
Typ (+25°C)
(5)
LVDIF can be
cleared by
firmware
LVDIF state
is unknown
LVDIF is set
by hardware
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41159E-page 370
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 28-21:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max
Typ (+25°C)
Typ (25C)
Min
Min
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 28-22:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C)
3.0
2.5
2.0
1.5
1.0
0.5
Max
Typ (+25°C)
Min
0.0
0
5
10
15
20
25
IOH (-mA)
© 2006 Microchip Technology Inc.
DS41159E-page 371
PIC18FXX8
FIGURE 28-23:
TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C)
1.8
1.6
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Max
Max
TyTpy(p+(2255°CC))
0
5
10
15
20
25
IOL (-mA)
FIGURE 28-24:
TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C)
2.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
2.0
1.5
1.0
0.5
0.0
Max
Typ (+25°C)
Typ (25C)
0
5
10
15
20
25
IOL (-mA)
DS41159E-page 372
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 28-25:
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C)
4.0
Typical:
statistical mean @ 25°C
VIH Max
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIH Min
VIL Max
VIL Min
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 28-26:
MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C)
1.6
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VTH (Max)
VTH (Min)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2006 Microchip Technology Inc.
DS41159E-page 373
PIC18FXX8
FIGURE 28-27:
MINIMUM AND MAXIMUM VIN vs. VDD (I2C™ INPUT, -40°C TO +125°C)
3.5
VIH Max
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Minimum: mean – 3σ (-40°C to +125°C)
VIL Max
x
VIH Min
VIL Min
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 28-28:
A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C)
4
3.5
3
-40°C
+25°C
25C
2.5
2
+85°C
85C
1.5
1
0.5
0
+125°C
125C
2
2.5
3
3.5
4
4.5
5
5.5
VDD and VREFH (V)
DS41159E-page 374
© 2006 Microchip Technology Inc.
PIC18FXX8
FIGURE 28-29:
A/D NONLINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C)
3
2.5
2
1.5
1
Max (-40°C to +125°C)
)
TTyypp((+2255C°)C)
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
VREFH (V)
© 2006 Microchip Technology Inc.
DS41159E-page 375
PIC18FXX8
NOTES:
DS41159E-page 376
© 2006 Microchip Technology Inc.
PIC18FXX8
29.0 PACKAGING INFORMATION
29.1 Package Marking Information
28-Lead SPDIP
Example
Example
e
3
PIC18F258-I/SP
0610017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
e
3
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC18F248-E/SO
0610017
YYWWNNN
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
e3
PIC18F448-I/P
0610017
YYWWNNN
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS41159E-page 377
PIC18FXX8
29.1 Package Marking Information (Continued)
44-Lead PLCC
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F458
-I/L
0610017
e
3
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F448
3
e
-I/PT
0610017
DS41159E-page 378
© 2006 Microchip Technology Inc.
PIC18FXX8
29.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
B
p
Units
INCHES
*
MILLIMETERS
Dimension Limits
MIN
NOM
28
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.140
.150
.130
.160
3.56
3.18
3.81
3.30
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.43
0.38
7.62
6.99
34.16
3.18
0.20
1.02
0.41
8.13
5
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
34.67
3.30
0.29
1.33
0.48
8.89
10
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
*
Controlling Parameter
§
Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
© 2006 Microchip Technology Inc.
DS41159E-page 379
PIC18FXX8
28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
MILLIMETERS
Dimension Limits
MIN
NOM
28
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
.050
1.27
Overall Height
Molded Package Thickness
A
.093
.099
.091
.008
.407
.295
.704
.020
.033
4
.104
2.36
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
2.64
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
Standoff
Overall Width
§
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle Top
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
E1
D
h
L
φ
c
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS41159E-page 380
© 2006 Microchip Technology Inc.
PIC18FXX8
40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
1
α
n
E
A2
A
L
c
B1
B
β
A1
p
eB
Units
Dimension Limits
INCHES*
NOM
40
MILLIMETERS
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
.100
2.54
Top to Seating Plane
A
.160
.175
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
.150
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
Lower Lead Width
B1
B
Overall Row Spacing
§
eB
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
5
10
15
5
10
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
© 2006 Microchip Technology Inc.
DS41159E-page 381
PIC18FXX8
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
#leads=n1
D
D1
n 1 2
CH2 x 45°
CH1 x 45°
α
A3
A2
A
35°
B1
B
c
A1
β
p
E2
D2
Units
INCHES*
NOM
44
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
.050
1.27
11
Pins per Side
Overall Height
n1
A
11
.173
.153
.028
.029
.045
.005
.690
.690
.653
.653
.620
.620
.011
.029
.020
5
.165
.145
.020
.024
.040
.000
.685
.685
.650
.650
.590
.590
.008
.026
.013
0
.180
4.19
3.68
0.51
0.61
1.02
0.00
17.40
17.40
16.51
16.51
14.99
14.99
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
0.27
0.74
0.51
5
4.57
Molded Package Thickness
A2
A1
A3
CH1
CH2
E
.160
.035
.034
.050
.010
.695
.695
.656
.656
.630
.630
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
Standoff
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
DS41159E-page 382
© 2006 Microchip Technology Inc.
PIC18FXX8
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45°
α
A
c
φ
β
A1
A2
L
F
Units
Dimension Limits
INCHES
NOM
44
MILLIMETERS
*
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
n1
A
Overall Height
.039
.043
.039
.004
.024
.039 REF.
3.5
.047
1.00
1.10
1.20
Molded Package Thickness
Standoff
A2
A1
L
.037
.002
.018
.041
.006
.030
0.95
0.05
0.45
1.00
0.10
0.60
1.05
0.15
0.75
Foot Length
Footprint (Reference)
Foot Angle
F
φ
1.00 REF.
3.5
12.00
0
7
0
7
Overall Width
E
D
.463
.463
.390
.390
.004
.012
.025
.472
.472
.394
.394
.006
.015
.035
10
.482
.482
.398
.398
.008
.017
.045
11.75
11.75
9.90
9.90
0.09
0.30
0.64
12.25
12.25
10.10
10.10
0.20
Overall Length
12.00
10.00
10.00
0.15
0.38
0.89
10
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
B
CH
α
0.44
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
1.14
5
15
15
5
15
15
β
5
10
5
10
*
Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MS-026
Revised 07-22-05
Drawing No. C04-076
© 2006 Microchip Technology Inc.
DS41159E-page 383
PIC18FXX8
NOTES:
DS41159E-page 384
© 2006 Microchip Technology Inc.
PIC18FXX8
APPENDIX A: DATA SHEET
REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
Revision A (June 2001)
Original data sheet for the PIC18FXX8 family.
Revision B (May 2002)
Updated information on CAN module, device memory
and register maps, I/O ports and Enhanced CCP.
Revision C (January 2003)
This revision includes the DC and AC Characteristics
Graphs and Tables (see Section 28.0 “DC and AC
Characteristics Graphs and Tables”), Section 27.0
“Electrical Characteristics” have been updated and
CAN certification information has been added.
Revision D (September 2004)
Data Sheet Errata (DS80134 and DS80161) issues
have been addressed and corrected along with minor
corrections to the data sheet text.
Revision E (October 2006)
Packaging diagrams updated.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F248
PIC18F258
PIC18F448
PIC18F458
Internal
Program
Memory
Bytes
16K
32K
16K
32K
# of Single-Word
Instructions
8192
16384
8192
16384
Data Memory (Bytes)
I/O Ports
768
Ports A, B, C
—
1536
Ports A, B, C
—
768
1536
Ports A, B, C, D, E Ports A, B, C, D, E
Enhanced Capture/Compare/PWM
Modules
1
1
Parallel Slave Port
No
No
Yes
Yes
10-bit Analog-to-Digital Converter
Analog Comparators
5 input channels 5 input channels 8 input channels 8 input channels
No
No
2
2
Analog Comparators VREF Output
Packages
N/A
N/A
Yes
Yes
28-pin SPDIP
28-pin SOIC
28-pin SPDIP
28-pin SOIC
40-pin PDIP
44-pin PLCC
44-pin TQFP
40-pin PDIP
44-pin PLCC
44-pin TQFP
© 2006 Microchip Technology Inc.
DS41159E-page 385
PIC18FXX8
APPENDIX C: DEVICE MIGRATIONS
APPENDIX D: MIGRATING FROM
OTHER PICmicro®
This section is intended to describe the functional and
electrical specification differences when migrating
between functionally similar devices (such as from a
PIC16C74A to a PIC16C74B).
DEVICES
This discusses some of the issues in migrating from
other PICmicro devices to the PIC18FXX8 family of
devices.
Not Applicable
D.1
PIC16CXXX to PIC18FXX8
See Application Note AN716 “Migrating Designs from
PIC16C74A/74B to PIC18C442” (DS00716).
D.2
PIC17CXXX to PIC18FXX8
See Application Note AN726 “PIC17CXXX to
PIC18CXXX Migration” (DS00726).
DS41159E-page 386
© 2006 Microchip Technology Inc.
PIC18FXX8
INDEX
Block Diagrams
A
A/D............................................................................ 243
Analog Input Model........................................... 244, 253
Baud Rate Generator ............................................... 169
CAN Buffers and Protocol Engine ............................ 200
CAN Receive Buffer ................................................. 230
CAN Transmit Buffer ................................................ 227
Capture Mode Operation.......................................... 125
Comparator I/O Operating Modes ............................ 250
Comparator Output................................................... 252
Comparator Voltage Reference
A/D.................................................................................... 241
A/D Converter Flag (ADIF Bit) .................................. 243
A/D Converter Interrupt, Configuring ........................ 244
Acquisition Requirements ......................................... 244
Acquisition Time........................................................ 245
ADCON0 Register..................................................... 241
ADCON1 Register..................................................... 241
ADRESH Register..................................................... 241
ADRESH/ADRESL Registers ................................... 243
ADRESL Register ..................................................... 241
Analog Port Pins, Configuring................................... 246
Associated Registers Summary................................ 248
Calculating the Minimum Required
Output Buffer Example ..................................... 257
Compare (CCP Module) Mode Operation ................ 126
Enhanced PWM........................................................ 134
Interrupt Logic............................................................. 78
Low-Voltage Detect (LVD)........................................ 260
Low-Voltage Detect with External Input.................... 260
Acquisition Time ............................................... 245
Configuring the Module............................................. 244
Conversion Clock (TAD) ............................................ 246
Conversion Status (GO/DONE Bit)........................... 243
Conversion TAD Cycles............................................. 248
Conversions.............................................................. 247
Minimum Charging Time........................................... 245
Result Registers........................................................ 247
Selecting the Conversion Clock................................ 246
Special Event Trigger (CCP)..................................... 126
Special Event Trigger (ECCP) .......................... 133, 248
TAD vs. Device Operating Frequencies
2
MSSP (I C Master Mode)......................................... 167
2
MSSP (I C Mode)..................................................... 152
MSSP (SPI Mode) .................................................... 143
On-Chip Reset Circuit................................................. 25
OSC2/CLKO/RA6 Pin................................................. 94
PIC18F248/258 Architecture ........................................ 8
PIC18F448/458 Architecture ........................................ 9
PLL ............................................................................. 19
PORTC (Peripheral Output Override)....................... 100
PORTD and PORTE (Parallel Slave Port)................ 107
PORTD in I/O Port Mode.......................................... 102
PORTE ..................................................................... 104
PWM (CCP Module)................................................. 128
RA3:RA0 and RA5 Pins.............................................. 94
RA4/T0CKI Pin ........................................................... 94
RB1:RB0 Pins............................................................. 97
RB2/CANTX/INT2 Pin ................................................ 98
RB3/CANRX Pin......................................................... 98
RB7:RB4 Pins............................................................. 97
Reads from Flash Program Memory .......................... 69
Table Read Operation ................................................ 65
Table Write Operation ................................................ 66
Table Writes to Flash Program Memory..................... 71
Timer0 in 16-bit Mode............................................... 110
Timer0 in 8-bit Mode................................................. 110
Timer1 ...................................................................... 114
Timer1 (16-bit Read/Write Mode)............................. 114
Timer2 ...................................................................... 118
Timer3 ...................................................................... 120
Timer3 (16-bit Read/Write Mode)............................. 120
USART Receive ....................................................... 191
USART Transmit ...................................................... 189
Voltage Reference.................................................... 256
Watchdog Timer ....................................................... 273
BN..................................................................................... 290
BNC .................................................................................. 291
BNN .................................................................................. 291
BNOV ............................................................................... 292
BNZ .................................................................................. 292
BOR. See Brown-out Reset.
(For Extended, LF Devices) (table)................... 246
TAD vs. Device Operating
Frequencies (table)........................................... 246
Use of the ECCP Trigger .......................................... 248
Absolute Maximum Ratings .............................................. 329
AC (Timing) Characteristics.............................................. 341
Parameter Symbology .............................................. 341
Access Bank ....................................................................... 54
ACKSTAT ......................................................................... 173
ACKSTAT Status Flag ...................................................... 173
ADCON0 Register............................................................. 241
GO/DONE Bit............................................................ 243
ADCON1 Register............................................................. 241
ADDLW ............................................................................. 287
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See USART.
ADDWF............................................................................. 287
ADDWFC .......................................................................... 288
ADRESH Register............................................................. 241
ADRESH/ADRESL Registers ........................................... 243
ADRESL Register ............................................................. 241
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................. 288
ANDWF............................................................................. 289
Assembler
MPASM Assembler................................................... 323
Associated Registers ................................................ 192, 197
B
Bank Select Register (BSR)................................................ 54
Baud Rate Generator........................................................ 169
BC ..................................................................................... 289
BCF................................................................................... 290
BF ..................................................................................... 173
BF Status Flag .................................................................. 173
BOV .................................................................................. 295
BRA .................................................................................. 293
BRG. See Baud Rate Generator.
Brown-out Reset (BOR).............................................. 26, 265
© 2006 Microchip Technology Inc.
DS41159E-page 387
PIC18FXX8
BSF ...................................................................................293
BTFSC ..............................................................................294
BTFSS...............................................................................294
BTG...................................................................................295
BZ......................................................................................296
Listen Only Mode...................................................... 226
Loopback Mode ........................................................ 227
Message Acceptance Filters
and Masks ................................................ 215, 232
Message Acceptance Mask and
Filter Operation (diagram) ................................ 232
Message Reception.................................................. 230
Message Time-Stamping.......................................... 230
Message Transmission............................................. 227
Modes of Operation .................................................. 226
Normal Mode ............................................................ 226
Oscillator Tolerance.................................................. 236
Overview................................................................... 199
Phase Buffer Segments............................................ 234
Programming Time Segments.................................. 236
Propagation Segment............................................... 234
Receive Buffer Registers.......................................... 210
Receive Buffers ........................................................ 230
Receive Message Buffering...................................... 230
Receive Priority......................................................... 230
Registers .................................................................. 201
Resynchronization .................................................... 235
Sample Point ............................................................ 234
Shortening a Bit Period (diagram) ............................ 236
Stuff Bit Error ............................................................ 237
Synchronization ........................................................ 235
Synchronization Rules.............................................. 235
Synchronization Segment......................................... 234
Time Quanta............................................................. 234
Transmit Buffer Registers......................................... 206
Transmit Buffers ....................................................... 227
Transmit Priority........................................................ 227
Transmit/Receive Buffers ......................................... 199
Values for ICODE (table).......................................... 239
Capture (CCP Module) ..................................................... 124
CAN Message Time-Stamp...................................... 125
CCP Pin Configuration.............................................. 124
CCP1 Prescaler........................................................ 125
CCPR1H:CCPR1L Registers.................................... 124
Software Interrupt ..................................................... 125
Timer1/Timer3 Mode Selection................................. 124
Capture (ECCP Module)................................................... 133
CAN Message Time-Stamp...................................... 133
Capture/Compare/PWM (CCP) ........................................ 123
Capture Mode. See Capture
C
C Compilers
MPLAB C17 ..............................................................324
MPLAB C18 ..............................................................324
MPLAB C30 ..............................................................324
CALL .................................................................................296
CAN Module
Aborting Transmission ..............................................228
Acknowledge Error....................................................237
Baud Rate Registers.................................................218
Baud Rate Setting.....................................................233
Bit Error.....................................................................237
Bit Time Partitioning (diagram) .................................233
Bit Timing Configuration Registers ...........................236
BRGCON1 ........................................................236
BRGCON2 ........................................................236
BRGCON3 ........................................................236
Calculating TQ, Nominal Bit Rate and
Nominal Bit Time...............................................234
Configuration Mode...................................................226
Control and Status Registers....................................201
Controller Register Map ............................................225
CRC Error .................................................................237
Disable Mode ............................................................226
Error Detection..........................................................237
Error Modes and Error Counters...............................237
Error Modes State (diagram) ....................................238
Error Recognition Mode ............................................227
Error States...............................................................237
Filter/Mask Truth (table)............................................232
Form Error.................................................................237
Hard Synchronization................................................235
I/O Control Register ..................................................221
Information Processing Time ....................................234
Initiating Transmission ..............................................228
Internal Message Reception
Flowchart ..........................................................231
Internal Transmit Message
Flowchart ..........................................................229
Interrupt Acknowledge ..............................................239
Interrupt Registers ....................................................222
Interrupts...................................................................238
Bus Activity Wake-up........................................239
Bus-Off..............................................................239
Code Bits ..........................................................238
Error..................................................................239
Message Error ..................................................239
Receive.............................................................238
Receiver Bus Passive.......................................239
Receiver Overflow.............................................239
Receiver Warning .............................................239
Transmit............................................................238
Transmitter Bus Passive...................................239
Transmitter Warning .........................................239
Lengthening a Bit Period
(CCP Module).
CCP1 Module ........................................................... 124
Timer Resources .............................................. 124
CCPR1H Register..................................................... 124
CCPR1L Register ..................................................... 124
Compare Mode. See Compare
(CCP Module).
Interaction of CCP1 and
ECCP1 Modules............................................... 124
PWM Mode. See PWM (CCP Module).
Ceramic Resonators
Ranges Tested ........................................................... 17
Clocking Scheme................................................................ 41
CLRF ................................................................................ 297
CLRWDT .......................................................................... 297
(diagram)...........................................................235
DS41159E-page 388
© 2006 Microchip Technology Inc.
PIC18FXX8
Code Examples
16 x 16 Signed Multiply Routine ................................. 76
CPFSGT ........................................................................... 299
CPFSLT............................................................................ 299
Crystal Oscillator
16 x 16 Unsigned Multiply Routine ............................. 76
8 x 8 Signed Multiply Routine ..................................... 75
8 x 8 Unsigned Multiply Routine ................................. 75
Changing Between Capture Prescalers.................... 125
Data EEPROM Read .................................................. 61
Data EEPROM Refresh Routine................................. 62
Data EEPROM Write .................................................. 61
Erasing a Flash Program Memory Row...................... 70
Fast Register Stack..................................................... 40
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................. 55
Initializing PORTA....................................................... 93
Initializing PORTB....................................................... 96
Initializing PORTC..................................................... 100
Initializing PORTD..................................................... 102
Initializing PORTE..................................................... 104
Loading the SSPBUF Register ................................. 146
Reading a Flash Program
Capacitor Selection .................................................... 18
D
Data EEPROM Memory...................................................... 59
Associated Registers.................................................. 63
EEADR Register......................................................... 59
EECON1 Register ...................................................... 59
EECON2 Register ...................................................... 59
Operation During Code-Protect.................................. 62
Protection Against Spurious Writes............................ 62
Reading ...................................................................... 61
Usage ......................................................................... 62
Write Verify................................................................. 62
Writing to .................................................................... 61
Data Memory ...................................................................... 44
General Purpose Registers ........................................ 44
Special Function Registers......................................... 44
Data Memory Map
Memory Word ..................................................... 69
Saving Status, WREG and BSR
Registers in RAM................................................ 92
WIN and ICODE Bits Usage in
PIC18F248/448 .......................................................... 45
PIC18F258/458 .......................................................... 46
DAW ................................................................................. 300
DC and AC Characteristics
Interrupt Service Routine to
Graphs and Tables................................................... 361
DC Characteristics............................................................ 332
EEPROM and Enhanced Flash................................ 339
PIC18FXX8 (Ind., Ext.) and
PIC18LFXX8 (Ind.)........................................... 336
DCFSNZ ........................................................................... 301
DECF................................................................................ 300
DECFSZ ........................................................................... 301
Demonstration Boards
PICDEM 1................................................................. 326
PICDEM 17............................................................... 327
PICDEM 18R............................................................ 327
PICDEM 2 Plus......................................................... 326
PICDEM 3................................................................. 326
PICDEM 4................................................................. 326
PICDEM LIN............................................................. 327
PICDEM USB ........................................................... 327
PICDEM.net Internet/Ethernet.................................. 326
Development Support....................................................... 323
Device Differences............................................................ 385
Device Migrations ............................................................. 386
Device Overview................................................................... 7
Features ....................................................................... 7
Direct Addressing ............................................................... 56
Disable Mode (CAN Module)............................................ 226
Access TX/RX Buffers ...................................... 203
Writing to Flash Program Memory ........................ 72–73
Code Protection ................................................................ 265
COMF ............................................................................... 298
Comparator Module .......................................................... 249
Analog Input Connection Considerations.................. 253
Associated Registers ................................................ 254
Configuration............................................................. 250
Effects of a Reset...................................................... 253
External Reference Signal ........................................ 251
Internal Reference Signal ......................................... 251
Interrupts................................................................... 252
Operation .................................................................. 251
Operation During Sleep ............................................ 253
Outputs ..................................................................... 251
Reference ................................................................. 251
Response Time......................................................... 251
Comparator Specifications................................................ 340
Comparator Voltage Reference Module ........................... 255
Accuracy/Error .......................................................... 256
Associated Registers ................................................ 257
Configuring................................................................ 255
Connection Considerations....................................... 256
Effects of a Reset...................................................... 256
Operation During Sleep ............................................ 256
Compare (CCP Module) ................................................... 126
CCP1 Pin Configuration............................................ 126
CCPR1 and ECCPR1 Registers............................... 126
Registers Associated with Capture,
E
Electrical Characteristics .................................................. 329
Enhanced Capture/Compare/PWM (ECCP)..................... 131
Auto-Shutdown......................................................... 142
Capture Mode. See Capture
Compare, Timer1 and Timer3........................... 127
Software Interrupt ..................................................... 126
Special Event Trigger........................ 115, 121, 126, 248
Timer1/Timer3 Mode Selection................................. 126
Compare (ECCP Module)................................................. 133
Registers Associated with Enhanced
Capture, Compare, Timer1 and Timer3............ 133
Special Event Trigger................................................ 133
Compatible 10-Bit Analog-to-Digital
(ECCP Module).
Compare Mode. See Compare
(ECCP Module).
ECCPR1H Register.................................................. 132
ECCPR1L Register................................................... 132
Interaction of CCP1 and
ECCP1 Modules............................................... 132
Pin Assignments for Various Modes......................... 132
PWM Mode. See PWM (ECCP Module).
Timer Resources ...................................................... 132
Converter (A/D) Module. See A/D.
Configuration Mode (CAN Module)................................... 226
CPFSEQ ........................................................................... 298
© 2006 Microchip Technology Inc.
DS41159E-page 389
PIC18FXX8
Enhanced CCP Auto-Shutdown........................................142
Enhanced PWM Mode.
Slave Mode............................................................... 156
Addressing........................................................ 156
See PWM (ECCP Module).
Reception ......................................................... 157
Errata ....................................................................................5
Error Recognition Mode (CAN Module) ............................226
Evaluation and Programming Tools..................................327
External Clock Input............................................................19
Transmission .................................................... 157
Sleep Operation........................................................ 177
Stop Condition Timing .............................................. 176
ID Locations.............................................................. 265, 279
INCF ................................................................................. 302
INCFSZ............................................................................. 303
In-Circuit Debugger........................................................... 279
In-Circuit Serial Programming (ICSP)....................... 265, 279
Indirect Addressing............................................................. 56
FSR Register.............................................................. 55
INDF Register............................................................. 55
Operation.................................................................... 55
INFSNZ............................................................................. 303
Initialization Conditions for All Registers............................. 30
Instruction Cycle ................................................................. 41
Instruction Flow/Pipelining.................................................. 41
Instruction Format............................................................. 283
Instruction Set................................................................... 281
ADDLW..................................................................... 287
ADDWF..................................................................... 287
ADDWFC.................................................................. 288
ANDLW..................................................................... 288
ANDWF..................................................................... 289
BC............................................................................. 289
BCF .......................................................................... 290
BN............................................................................. 290
BNC .......................................................................... 291
BNN .......................................................................... 291
BNOV ....................................................................... 292
BNZ .......................................................................... 292
BOV .......................................................................... 295
BRA .......................................................................... 293
BSF........................................................................... 293
BTFSC...................................................................... 294
BTFSS ...................................................................... 294
BTG .......................................................................... 295
BZ ............................................................................. 296
CALL......................................................................... 296
CLRF ........................................................................ 297
CLRWDT .................................................................. 297
COMF ....................................................................... 298
CPFSEQ................................................................... 298
CPFSGT ................................................................... 299
CPFSLT.................................................................... 299
DAW ......................................................................... 300
DCFSNZ ................................................................... 301
DECF........................................................................ 300
DECFSZ ................................................................... 301
GOTO ....................................................................... 302
INCF ......................................................................... 302
INCFSZ..................................................................... 303
INFSNZ..................................................................... 303
IORLW...................................................................... 304
IORWF...................................................................... 304
LFSR ........................................................................ 305
MOVF ....................................................................... 305
MOVFF ..................................................................... 306
MOVLB..................................................................... 306
MOVLW .................................................................... 307
MOVWF.................................................................... 307
MULLW..................................................................... 308
MULWF..................................................................... 308
F
Firmware Instructions........................................................281
Flash Program Memory.......................................................65
Associated Registers ..................................................74
Control Registers ........................................................66
Erase Sequence .........................................................70
Erasing........................................................................70
Operation During Code-Protect ..................................73
Reading.......................................................................69
TABLAT (Table Latch) Register..................................68
Table Pointer
Boundaries Based on Operation.........................68
Table Pointer Boundaries ...........................................68
Table Reads and Table Writes ...................................65
TBLPTR (Table Pointer) Register ...............................68
Write Sequence ..........................................................71
Writing to.....................................................................71
Protection Against Spurious Writes ....................73
Unexpected Termination.....................................73
Write Verify .........................................................73
G
GOTO................................................................................302
H
Hardware Multiplier .............................................................75
Operation ....................................................................75
Performance Comparison (table)................................75
HS4 (PLL) ...........................................................................19
I
I/O Ports..............................................................................93
2
I C Mode...........................................................................152
ACK Pulse......................................................... 156, 157
Acknowledge Sequence Timing................................176
Baud Rate Generator................................................169
Bus Collision During a
Repeated Start Condition..................................180
Bus Collision During a Start Condition......................178
Bus Collision During a Stop Condition ......................181
Clock Arbitration........................................................170
Clock Stretching........................................................162
Effect of a Reset .......................................................177
General Call Address Support ..................................166
Master Mode.............................................................167
Operation ..........................................................168
Reception..........................................................173
Repeated Start Condition Timing......................172
Start Condition Timing ......................................171
Transmission.....................................................173
Multi-Master Mode ....................................................177
Communication, Bus Collision
and Bus Arbitration ...................................177
Operation ..................................................................156
Read/Write Bit Information (R/W Bit) ................ 156, 157
Registers...................................................................152
Serial Clock (RC3/SCK/SCL)....................................157
DS41159E-page 390
© 2006 Microchip Technology Inc.
PIC18FXX8
NEGF........................................................................ 309
NOP .......................................................................... 309
POP .......................................................................... 310
PUSH........................................................................ 310
RCALL ...................................................................... 311
RESET...................................................................... 311
RETFIE ..................................................................... 312
RETLW ..................................................................... 312
RETURN................................................................... 313
RLCF......................................................................... 313
RLNCF...................................................................... 314
RRCF........................................................................ 314
RRNCF ..................................................................... 315
SETF......................................................................... 315
SLEEP ...................................................................... 316
SUBFWB................................................................... 316
SUBLW ..................................................................... 317
SUBWF..................................................................... 317
SUBWFB................................................................... 318
SWAPF ..................................................................... 318
TBLRD ...................................................................... 319
TBLWT...................................................................... 320
TSTFSZ .................................................................... 321
XORLW..................................................................... 321
XORWF..................................................................... 322
Summary Table......................................................... 284
Low-Voltage Detect .......................................................... 259
Characteristics.......................................................... 338
Current Consumption ............................................... 263
Effects of a Reset ..................................................... 263
Operation.................................................................. 262
Operation During Sleep............................................ 263
Reference Voltage Set Point .................................... 263
Typical Application.................................................... 259
Low-Voltage ICSP Programming...................................... 279
LVD. See Low-Voltage Detect.
M
Master Synchronous Serial Port (MSSP).
See MSSP.
Master Synchronous Serial Port.
See MSSP.
Memory Organization ......................................................... 37
Data Memory.............................................................. 44
Internal Program Memory Operation.......................... 37
Program Memory........................................................ 37
Migrating from other PICmicro Devices............................ 386
MOVF ............................................................................... 305
MOVFF ............................................................................. 306
MOVLB............................................................................. 306
MOVLW ............................................................................ 307
MOVWF............................................................................ 307
MPLAB ASM30 Assembler,
INTCON Register
Linker, Librarian........................................................ 324
MPLAB ICD 2 In-Circuit Debugger................................... 325
MPLAB ICE 2000 High-Performance
RBIF Bit....................................................................... 96
Inter-Integrated Circuit. See I C.
Interrupt Sources
2
Universal In-Circuit Emulator.................................... 325
MPLAB ICE 4000 High-Performance
Universal In-Circuit Emulator.................................... 325
MPLAB Integrated Development
Environment Software .............................................. 323
MPLAB PM3 Device Programmer .................................... 325
MPLINK Object Linker/
A/D Conversion Complete ........................................ 244
CAN Module.............................................................. 238
Capture Complete (CCP).......................................... 125
Compare Complete (CCP)........................................ 126
Interrupt-on-Change (RB7:RB4) ................................. 96
TMR0 Overflow......................................................... 111
TMR1 Overflow................................................. 113, 115
TMR2 to PR2 Match ................................................. 118
TMR2 to PR2 Match (PWM) ............................. 117, 128
TMR3 Overflow................................................. 119, 121
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) .................................................................... 96
Interrupts..................................................................... 77, 265
Context Saving During................................................ 92
Enable Registers......................................................... 85
Flag Registers............................................................. 82
INT .............................................................................. 92
PORTB Interrupt-on-Change ...................................... 92
Priority Registers......................................................... 88
TMR0 .......................................................................... 92
Interrupts, Flag Bits
MPLIB Object Librarian ............................................ 324
MSSP ............................................................................... 143
Control Registers...................................................... 143
Enabling SPI I/O....................................................... 147
Operation.................................................................. 146
Overview................................................................... 143
SPI Master Mode...................................................... 148
SPI Master/Slave Connection................................... 147
SPI Mode.................................................................. 143
SPI Slave Mode........................................................ 149
TMR2 Output for Clock Shift............................. 117, 118
Typical Connection................................................... 147
2
MSSP. See also I C Mode, SPI Mode.
MULLW............................................................................. 308
MULWF............................................................................. 308
A/D Converter Flag (ADIF Bit) .................................. 243
CCP1 Flag (CCP1IF Bit)........................... 124, 125, 126
IORLW .............................................................................. 304
IORWF .............................................................................. 304
N
NEGF................................................................................ 309
NOP.................................................................................. 309
Normal Operation Mode (CAN Module)............................ 226
L
LFSR................................................................................. 305
Listen Only Mode (CAN Module) ...................................... 226
Look-up Tables ................................................................... 43
Computed GOTO........................................................ 43
Table Reads/Table Writes .......................................... 43
Loopback Mode (CAN Module)......................................... 226
© 2006 Microchip Technology Inc.
DS41159E-page 391
PIC18FXX8
RD0/PSP0/C1IN+....................................................... 14
RD1/PSP1/C1IN-........................................................ 14
RD2/PSP2/C2IN+....................................................... 14
RD3/PSP3/C2IN-........................................................ 14
RD4/PSP4/ECCP1/P1A.............................................. 14
RD5/PSP5/P1B .......................................................... 14
RD6/PSP6/P1C .......................................................... 14
RD7/PSP7/P1D .......................................................... 14
RE0/AN5/RD............................................................... 15
RE1/AN6/WR/C1OUT................................................. 15
RE2/AN7/CS/C2OUT.................................................. 15
VDD ............................................................................. 15
VSS ............................................................................. 15
Pinout I/O Descriptions....................................................... 10
Pointer, FSRn ..................................................................... 55
POP .................................................................................. 310
POR. See Power-on Reset.
O
Opcode Field Descriptions................................................282
Oscillator
Effects of Sleep Mode.................................................23
Power-up Delays.........................................................23
Switching Feature .......................................................20
System Clock Switch Bit .............................................20
Transitions ..................................................................21
Oscillator Configurations.....................................................17
Crystal Oscillator, Ceramic Resonators ......................17
EC ...............................................................................17
ECIO ...........................................................................17
HS...............................................................................17
HS4 .............................................................................17
LP................................................................................17
RC......................................................................... 17, 18
RCIO...........................................................................17
XT ...............................................................................17
Oscillator Selection ...........................................................265
Oscillator, Timer1..............................................113, 115, 121
Oscillator, WDT.................................................................272
PORTA
Associated Register Summary ................................... 95
Functions .................................................................... 95
LATA Register ............................................................ 93
PORTA Register......................................................... 93
TRISA Register........................................................... 93
PORTB
P
Packaging Information ......................................................377
Details.......................................................................379
Marking .....................................................................377
Parallel Slave Port (PSP).......................................... 102, 107
Associated Registers ................................................108
PORTD .....................................................................107
PSP Mode Select (PSPMODE) Bit ...........................102
RE2/AN7/CS/C2OUT................................................107
PIC18FXX8 Voltage-Frequency
Associated Register Summary ................................... 99
Functions .................................................................... 99
LATB Register ............................................................ 96
PORTB Register......................................................... 96
RB7:RB4 Interrupt-on-Change
Flag (RBIF Bit).................................................... 96
TRISB Register........................................................... 96
PORTC
Associated Register Summary ................................. 101
Functions .................................................................. 101
LATC Register.......................................................... 100
PORTC Register....................................................... 100
RC3/SCK/SCL Pin.................................................... 157
RC7/RX/DT pin......................................................... 185
TRISC Register................................................. 100, 183
PORTD
Associated Register Summary ................................. 103
Functions .................................................................. 103
LATD Register.......................................................... 102
Parallel Slave Port (PSP) Function........................... 102
PORTD Register....................................................... 102
TRISD Register......................................................... 102
PORTE
Associated Register Summary ................................. 106
Functions .................................................................. 106
LATE Register .......................................................... 104
PORTE Register....................................................... 104
PSP Mode Select (PSPMODE) Bit........................... 102
RE2/AN7/CS/C2OUT................................................ 107
TRISE Register......................................................... 104
Power-Down Mode. See Sleep.
Power-on Reset (POR)............................................... 26, 265
MCLR ......................................................................... 26
Oscillator Start-up Timer (OST).......................... 26, 265
PLL Lock Time-out...................................................... 26
Power-up Timer (PWRT).................................... 26, 265
Time-out Sequence .................................................... 27
Power-up Delays
Graph (Industrial)......................................................330
PIC18LFXX8 Voltage-Frequency
Graph (Industrial)......................................................331
PICkit 1 Flash Starter Kit...................................................327
PICSTART Plus Development
Programmer ..............................................................326
Pin Functions
MCLR/VPP...................................................................10
OSC1/CLKI .................................................................10
OSC2/CLKO/RA6 .......................................................10
RA0/AN0/CVREF .........................................................11
RA1/AN1 .....................................................................11
RA2/AN2/VREF-...........................................................11
RA3/AN3/VREF+..........................................................11
RA4/T0CKI..................................................................11
RA5/AN4/SS/LVDIN....................................................11
RA6 .............................................................................11
RB0/INT0 ....................................................................12
RB1/INT1 ....................................................................12
RB2/CANTX/INT2.......................................................12
RB3/CANRX ...............................................................12
RB4 .............................................................................12
RB5/PGM....................................................................12
RB6/PGC ....................................................................12
RB7/PGD ....................................................................12
RC0/T1OSO/T1CKI ....................................................13
RC1/T1OSI .................................................................13
RC2/CCP1 ..................................................................13
RC3/SCK/SCL ............................................................13
RC4/SDI/SDA .............................................................13
RC5/SDO ....................................................................13
RC6/TX/CK .................................................................13
RC7/RX/DT.................................................................13
OSC1 and OSC2 Pin States
in Sleep Mode..................................................... 23
Prescaler, Timer0 ............................................................. 111
DS41159E-page 392
© 2006 Microchip Technology Inc.
PIC18FXX8
Prescaler, Timer2.............................................................. 128
PRO MATE II Universal Device
Register File Summary ....................................................... 49
Registers
Programmer.............................................................. 325
Program Counter
ADCON0 (A/D Control 0).......................................... 241
ADCON1 (A/D Control 1).......................................... 242
BRGCON1 (Baud Rate Control 1)............................ 218
BRGCON2 (Baud Rate Control 2)............................ 219
BRGCON3 (Baud Rate Control 3)............................ 220
CANCON (CAN Control) .......................................... 201
CANSTAT (CAN Status)........................................... 202
CCP1CON (CCP1 Control) ...................................... 123
CIOCON (CAN I/O Control)...................................... 221
CMCON (Comparator Control)................................. 249
COMSTAT (CAN
Communication Status) .................................... 205
CONFIG1H (Configuration 1 High)........................... 266
CONFIG2H (Configuration 2 High)........................... 267
CONFIG2L (Configuration 2 Low) ............................ 266
CONFIG4L (Configuration 4 Low) ............................ 267
CONFIG5H (Configuration 5 High)........................... 268
CONFIG5L (Configuration 5 Low) ............................ 268
CONFIG6H (Configuration 6 High)........................... 269
CONFIG6L (Configuration 6 Low) ............................ 269
CONFIG7H (Configuration 7 High)........................... 270
CONFIG7L (Configuration 7 Low) ............................ 270
CVRCON (Comparator Voltage
Reference Control)........................................... 255
DEVID1 (Device ID 1)............................................... 271
DEVID2 (Device ID 2)............................................... 271
ECCP1CON (ECCP1 Control).................................. 131
ECCP1DEL (PWM Delay) ........................................ 140
ECCPAS (Enhanced Capture/Compare/PWM
Auto-Shutdown Control)................................... 142
EECON1 (EEPROM Control 1) ............................ 60, 67
INTCON (Interrupt Control) ........................................ 79
INTCON2 (Interrupt Control 2) ................................... 80
INTCON3 (Interrupt Control 3) ................................... 81
IPR1 (Peripheral Interrupt Priority 1) .......................... 88
IPR2 (Peripheral Interrupt Priority 2) .......................... 89
IPR3 (Peripheral Interrupt Priority 3) .................. 90, 224
LVDCON (LVD Control)............................................ 261
OSCCON (Oscillator Control)..................................... 20
PIE1 (Peripheral Interrupt Enable 1) .......................... 85
PIE2 (Peripheral Interrupt Enable 2) .......................... 86
PIE3 (Peripheral Interrupt Enable 3) .................. 87, 223
PIR1 (Peripheral Interrupt Request
PCL Register............................................................... 40
PCLATH Register ....................................................... 40
PCLATU Register ....................................................... 40
Program Memory ................................................................ 37
Fast Register Stack..................................................... 40
Instructions.................................................................. 41
Two-Word ........................................................... 43
Map and Stack for PIC18F248/448............................. 37
Map and Stack for PIC18F258/458............................. 37
PUSH and POP Instructions....................................... 40
Return Address Stack................................................. 38
Return Stack Pointer (STKPTR) ................................. 38
Stack Full/Underflow Resets....................................... 40
Top-of-Stack Access................................................... 38
Program Verification and
Code Protection ........................................................ 276
Associated Registers Summary................................ 276
Configuration Register Protection............................. 279
Data EEPROM Code Protection............................... 279
Program Memory Code Protection ........................... 277
Programming, Device Instructions .................................... 281
PUSH ................................................................................ 310
PWM (CCP Module) ......................................................... 128
CCPR1H:CCPR1L Registers.................................... 128
Duty Cycle................................................................. 128
Example Frequencies/Resolutions ........................... 129
Period........................................................................ 128
Registers Associated with
PWM and Timer2.............................................. 129
Setup for PWM Operation......................................... 129
TMR2 to PR2 Match ......................................... 117, 128
PWM (ECCP Module) ....................................................... 134
Full-Bridge Application Example............................... 138
Full-Bridge Mode....................................................... 137
Direction Change .............................................. 138
Half-Bridge Mode...................................................... 136
Half-Bridge Output Mode
Applications Example ....................................... 136
Output Configurations............................................... 134
Output Polarity Configuration.................................... 140
Output Relationships Diagram.................................. 135
Programmable Dead-Band Delay............................. 140
Registers Associated with Enhanced PWM
(Flag) 1).............................................................. 82
PIR2 (Peripheral Interrupt Request
and Timer2........................................................ 141
Setup for PWM Operation......................................... 141
Standard Mode ......................................................... 134
Start-up Considerations ............................................ 140
System Implementation ............................................ 140
(Flag) 2).............................................................. 83
PIR3 (Peripheral Interrupt Request
(Flag) 3)...................................................... 84, 222
RCON (Reset Control).......................................... 58, 91
RCSTA (Receive Status and Control) ...................... 184
RXB0CON (Receive Buffer 0 Control)...................... 210
RXB1CON (Receive Buffer 1 Control)...................... 211
RXBnDLC (Receive Buffer n
Q
Q Clock ............................................................................. 128
Data Length Code)........................................... 213
RXBnDm (Receive Buffer n
Data Field Byte m)............................................ 214
RXBnEIDH (Receive Buffer n
Extended Identifier, High Byte)......................... 212
RXBnEIDL (Receive Buffer n
R
RAM. See Data Memory.
RCALL .............................................................................. 311
RCON Register
Significance of Status Bits vs.
Initialization Condition......................................... 27
RCSTA Register ............................................................... 183
SPEN Bit................................................................... 183
Receiver Warning ............................................................. 239
Register File........................................................................ 44
Extended Identifier, Low Byte).......................... 213
RXBnSIDH (Receive Buffer n
Standard Identifier, High Byte) ......................... 212
© 2006 Microchip Technology Inc.
DS41159E-page 393
PIC18FXX8
RXBnSIDL (Receive Buffer n
S
Standard Identifier, Low Byte)...........................212
RXERRCNT (Receive Error Count) ..........................214
RXFnEIDH (Receive Acceptance Filter n
Extended Identifier, High Byte) .........................216
RXFnEIDL (Receive Acceptance Filter n
Extended Identifier, Low Byte)..........................216
RXFnSIDH (Receive Acceptance Filter n
Standard Identifier Filter, High Byte).................215
RXFnSIDL (Receive Acceptance Filter n
Standard Identifier Filter, Low Byte)..................215
RXMnEIDH (Receive Acceptance Mask n
Extended Identifier Mask, High Byte)................217
RXMnEIDL (Receive Acceptance Mask n
Extended Identifier Mask, Low Byte) ................217
RXMnSIDH (Receive Acceptance Mask n
SCI. See USART.
SCK Pin ............................................................................ 143
SDI Pin.............................................................................. 143
SDO Pin............................................................................ 143
Serial Clock (SCK) Pin...................................................... 143
Serial Communication Interface.
See USART.
Serial Peripheral Interface. See SPI.
SETF................................................................................. 315
Slave Select (SS) Pin ....................................................... 143
Slave Select, SS Pin......................................................... 143
SLEEP .............................................................................. 316
Sleep......................................................................... 265, 274
Software Simulator (MPLAB SIM) .................................... 324
Software Simulator (MPLAB SIM30) ................................ 324
Special Event Trigger. See Compare.
Special Features of the CPU ............................................ 265
Configuration Bits ..................................................... 265
Configuration Bits and
Device IDs ........................................................ 265
Configuration Registers.................................... 266–271
Special Function Register Map........................................... 47
Special Function Registers................................................. 44
SPI Mode
Associated Registers................................................ 151
Bus Mode Compatibility............................................ 151
Effects of a Reset ..................................................... 151
Master Mode............................................................. 148
Master/Slave Connection.......................................... 147
Registers .................................................................. 144
Serial Clock............................................................... 143
Serial Data In (SDI) Pin ............................................ 143
Serial Data Out (SDO) Pin........................................ 143
Slave Select.............................................................. 143
Slave Select Synchronization ................................... 149
Sleep Operation........................................................ 151
SPI Clock.................................................................. 148
SSPBUF Register..................................................... 148
SSPSR Register ....................................................... 148
SSPOV ............................................................................. 173
SSPOV Status Flag .......................................................... 173
SSPSTAT Register
Standard Identifier Mask, High Byte) ................216
RXMnSIDL (Receive Acceptance Mask n
Standard Identifier Mask, Low Byte).................217
SSPCON1 (MSSP Control 1, I C Mode) ..................154
2
SSPCON1 (MSSP Control 1, SPI Mode)..................145
2
SSPCON2 (MSSP Control 2, I C Mode) ..................155
2
SSPSTAT (MSSP Status, I C Mode)........................153
SSPSTAT (MSSP Status, SPI Mode) .......................144
Status..........................................................................57
STKPTR (Stack Pointer).............................................39
T0CON (Timer0 Control)...........................................109
T1CON (Timer1 Control)...........................................113
T2CON (Timer2 Control)...........................................117
T3CON (Timer3 Control)...........................................119
TRISE (PORTE Direction/PSP Control)....................105
TXBnCON (Transmit Buffer n Control) .....................206
TXBnDLC (Transmit Buffer n
Data Length Code)............................................209
TXBnDm (Transmit Buffer n
Data Field Byte m) ............................................208
TXBnEIDH (Transmit Buffer n
Extended Identifier, High Byte) .........................207
TXBnEIDL (Transmit Buffer n
Extended Identifier, Low Byte)..........................208
TXBnSIDH (Transmit Buffer n
Standard Identifier, High Byte)..........................207
TXBnSIDL (Transmit Buffer n
Standard Identifier, Low Byte)...........................207
TXERRCNT (Transmit Error Count)..........................209
TXSTA (Transmit Status and Control) ......................183
WDTCON (Watchdog Timer Control)........................272
RESET ..............................................................................311
Reset........................................................................... 25, 265
MCLR Reset During Normal Operation ......................25
MCLR Reset During Sleep..........................................25
Power-on Reset (POR)...............................................25
Programmable Brown-out Reset (PBOR)...................25
RESET Instruction ......................................................25
Stack Full Reset..........................................................25
Stack Underflow Reset ...............................................25
Watchdog Timer (WDT) Reset....................................25
RETFIE .............................................................................312
RETLW..............................................................................312
RETURN ...........................................................................313
Revision History ................................................................385
RLCF.................................................................................313
RLNCF ..............................................................................314
RRCF ................................................................................314
RRNCF..............................................................................315
R/W Bit ............................................................. 156, 157
SUBFWB .......................................................................... 316
SUBLW............................................................................. 317
SUBWF............................................................................. 317
SUBWFB .......................................................................... 318
SWAPF............................................................................. 318
T
Table Pointer Operations (table)......................................... 68
TBLRD.............................................................................. 319
TBLWT.............................................................................. 320
Timer0............................................................................... 109
16-bit Mode Timer Reads and Writes....................... 111
Associated Registers................................................ 111
Operation.................................................................. 111
Overflow Interrupt ..................................................... 111
Prescaler .................................................................. 111
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment .............................. 111
DS41159E-page 394
© 2006 Microchip Technology Inc.
PIC18FXX8
Timer1............................................................................... 113
16-bit Read/Write Mode............................................ 115
Associated Registers ................................................ 116
Operation .................................................................. 114
Oscillator........................................................... 113, 115
Overflow Interrupt ............................................. 113, 115
Special Event Trigger (CCP)............................. 115, 126
Special Event Trigger (ECCP) .................................. 133
TMR1H Register ....................................................... 113
TMR1L Register........................................................ 113
TMR3L Register........................................................ 119
Timer2............................................................................... 117
Associated Registers ................................................ 118
Operation .................................................................. 117
Postscaler. See Postscaler, Timer2.
Half-Bridge PWM Output.......................................... 136
2
I C Bus Data............................................................. 353
2
I C Bus Start/Stop Bits ............................................. 353
2
I C Master Mode (Reception,
7-bit Address) ................................................... 175
I C Master Mode (Transmission,
2
7 or 10-bit Address).......................................... 174
I C Slave Mode (Transmission,
2
10-bit Address) ................................................. 161
I C Slave Mode (Transmission,
2
7-bit Address) ................................................... 159
I C Slave Mode with SEN = 0 (Reception,
2
10-bit Address) ................................................. 160
I C Slave Mode with SEN = 0 (Reception,
2
7-bit Address) ................................................... 158
I C Slave Mode with SEN = 1 (Reception,
2
PR2 Register..................................................... 117, 128
Prescaler. See Prescaler, Timer2.
10-bit Address) ................................................. 165
I C Slave Mode with SEN = 1 (Reception,
2
SSP Clock Shift................................................. 117, 118
TMR2 Register.......................................................... 117
TMR2 to PR2 Match Interrupt................... 117, 118, 128
Timer3............................................................................... 119
Associated Registers ................................................ 121
Operation .................................................................. 120
Oscillator................................................................... 121
Overflow Interrupt ............................................. 119, 121
Special Event Trigger (CCP)..................................... 121
TMR3H Register ....................................................... 119
Timing Conditions ............................................................. 342
Load Conditions for Device
7-bit Address) ................................................... 164
Low-Voltage Detect .................................................. 262
2
Master SSP I C Bus Data ........................................ 355
2
Master SSP I C Bus Start/Stop Bits......................... 355
Parallel Slave Port (PIC18F248
and PIC18F458)............................................... 348
Parallel Slave Port Read .......................................... 108
Parallel Slave Port Write........................................... 107
PWM Direction Change............................................ 139
PWM Direction Change at Near
100% Duty Cycle.............................................. 139
PWM Output............................................................. 128
Repeated Start Condition ......................................... 172
Reset, Watchdog Timer (WDT),
Timing Specifications........................................ 342
Temperature and Voltage
Specifications – AC........................................... 342
Timing Diagrams
Oscillator Start-up Timer (OST),
A/D Conversion......................................................... 359
Acknowledge Sequence ........................................... 176
Baud Rate Generator with
Clock Arbitration ............................................... 170
BRG Reset Due to SDA Arbitration
During Start Condition ...................................... 179
Brown-out Reset (BOR) and
Low-Voltage Detect .......................................... 345
Bus Collision During a Repeated
Start Condition (Case 1) ................................... 180
Bus Collision During a Repeated
Start Condition (Case2) .................................... 180
Bus Collision During a Stop
Power-up Timer (PWRT).................................. 345
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode)............................... 166
Slave Synchronization.............................................. 149
Slow Rise Time (MCLR Tied to VDD) ......................... 29
SPI Master Mode...................................................... 148
SPI Master Mode Example (CKE = 0)...................... 349
SPI Master Mode Example (CKE = 1)...................... 350
SPI Slave Mode (with CKE = 0)................................ 150
SPI Slave Mode (with CKE = 1)................................ 150
SPI Slave Mode Example (CKE = 0)........................ 351
SPI Slave Mode Example (CKE = 1)........................ 352
Stop Condition Receive or
Condition (Case 1)............................................ 181
Bus Collision During a
Stop Condition (Case 2) ................................... 181
Bus Collision During
Transmit Mode.................................................. 176
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................... 29
Time-out Sequence on Power-up
Start Condition (SCL = 0).................................. 179
Bus Collision During
Start Condition (SDA Only)............................... 178
Bus Collision for Transmit and
(MCLR Not Tied to VDD)
Case 1 ................................................................ 28
Case 2 ................................................................ 28
Time-out Sequence on Power-up
Acknowledge .................................................... 177
Capture/Compare/PWM
(MCLR Tied to VDD) ........................................... 28
Timer0 and Timer1 External Clock........................... 346
Transition Between Timer1 and
OSC1 (HS with PLL)........................................... 22
Transition Between Timer1 and
(CCP1 and ECCP1).......................................... 347
CLKO and I/O ........................................................... 344
Clock Synchronization .............................................. 163
Clock/Instruction Cycle ............................................... 41
External Clock........................................................... 343
First Start Bit ............................................................. 171
Full-Bridge PWM Output........................................... 137
OSC1 (HS, XT, LP) ............................................ 21
Transition Between Timer1 and
OSC1 (RC, EC).................................................. 22
© 2006 Microchip Technology Inc.
DS41159E-page 395
PIC18FXX8
Transition from OSC1 to
U
Timer1 Oscillator.................................................21
USART.............................................................................. 183
Asynchronous Mode................................................. 189
Reception ......................................................... 191
Setting Up 9-Bit Mode with
USART Asynchronous Reception.............................192
USART Asynchronous Transmission........................190
USART Asynchronous Transmission
(Back to Back)...................................................190
USART Synchronous Receive
(Master/Slave)...................................................357
USART Synchronous Reception
(Master Mode, SREN).......................................195
USART Synchronous Transmission .........................194
USART Synchronous Transmission
Address Detect......................................... 191
Transmission .................................................... 189
Asynchronous Reception.......................................... 192
Asynchronous Transmission
Associated Registers........................................ 190
Baud Rate Generator (BRG) .................................... 185
Associated Registers........................................ 185
Baud Rate Error, Calculating............................ 185
Baud Rate Formula .......................................... 185
Baud Rates for Asynchronous Mode
(Master/Slave)...................................................357
USART Synchronous Transmission
(Through TXEN)................................................194
Wake-up from Sleep via Interrupt .............................275
Timing Diagrams and Specifications.................................343
A/D Conversion Requirements .................................359
A/D Converter Characteristics ..................................358
Capture/Compare/PWM Requirements
(BRGH = 0)............................................... 187
Baud Rates for Asynchronous Mode
(BRGH = 1)............................................... 188
Baud Rates for Synchronous Mode.................. 186
High Baud Rate Select (BRGH Bit) .................. 185
Sampling........................................................... 185
Serial Port Enable (SPEN) Bit .................................. 183
Synchronous Master Mode....................................... 193
Reception ......................................................... 195
Transmission .................................................... 193
Synchronous Master Reception
(CCP1 and ECCP1)..........................................347
CLKO and I/O Timing
Requirements....................................................344
Example SPI Mode Requirements
(Master Mode, CKE = 0)...................................349
Example SPI Mode Requirements
(Master Mode, CKE = 1)...................................350
Example SPI Mode Requirements
Associated Registers........................................ 195
Synchronous Master Transmission
(Slave Mode, CKE = 0).....................................351
Example SPI Slave Mode
Associated Registers........................................ 193
Synchronous Slave Mode......................................... 196
Reception ......................................................... 196
Transmission .................................................... 196
Synchronous Slave Reception.................................. 197
Synchronous Slave Transmission
Requirements (CKE = 1)...................................352
External Clock Timing Requirements........................343
2
I C Bus Data Requirements
(Slave Mode).....................................................354
I C Bus Start/Stop Bits Requirements
2
Associated Registers........................................ 197
(Slave Mode).....................................................353
2
Master SSP I C Bus Data
V
Requirements....................................................356
Voltage Reference Specifications..................................... 340
2
Master SSP I C Bus Start/Stop Bits
W
Requirements....................................................355
Parallel Slave Port Requirements
Wake-up from Sleep................................................. 265, 274
Using Interrupts ........................................................ 274
Watchdog Timer (WDT)............................................ 265, 272
Associated Registers................................................ 273
Control Register........................................................ 272
Postscaler................................................................. 273
Programming Considerations ................................... 272
RC Oscillator............................................................. 272
Time-out Period ........................................................ 272
WCOL....................................................... 171, 172, 173, 176
WCOL Status Flag.................................... 171, 172, 173, 176
WDT. See Watchdog Timer.
(PIC18F248 and PIC18F458) ...........................348
PLL Clock..................................................................344
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer,
Brown-out Reset and Low-Voltage
Detect Requirements ........................................345
Timer0 and Timer1 External
Clock Requirements..........................................346
USART Synchronous Receive
Requirements....................................................357
USART Synchronous Transmission
Requirements....................................................357
TSTFSZ.............................................................................321
TXSTA Register
WWW, On-Line Support ....................................................... 5
X
BRGH Bit ..................................................................185
XORLW............................................................................. 321
XORWF ............................................................................ 322
DS41159E-page 396
© 2006 Microchip Technology Inc.
PIC18FXX8
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CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
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Advance Information
DS41159E-page 397
PIC18FXX8
READER RESPONSE
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PIC18FXX8
DS41159E
Literature Number:
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Questions:
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DS41159E-page 398
Advance Information
© 2006 Microchip Technology Inc.
PIC18FXX8
PIC18FXX8 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
PIC18LF258-I/L 301 = Industrial temp., PLCC
package, Extended VDD limits, QTP pattern
#301.
b)
c)
PIC18LF458-I/PT = Industrial temp., TQFP
package, Extended VDD limits.
Device
PIC18F248/258(1), PIC18F448/458(1), PIC18F248/258T(2)
PIC18F448/458T(2)
,
PIC18F258-E/L = Extended temp., PLCC
package, normal VDD limits.
;
VDD range 4.2V to 5.5V
PIC18LF248/258(1), PIC18LF448/458(1), PIC18LF248/258T(2)
PIC18LF448/458T(2);
,
VDD range 2.0V to 5.5V
Temperature Range
Package
I
E
= -40°C to +85°C (Industrial)
= -40°C to +125°C (Extended)
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Wide Voltage Range
in tape and reel PLCC and TQFP
packages only.
PT
L
SO
SP
P
=
=
=
=
=
TQFP (Thin Quad Flatpack)
PLCC
SOIC
Skinny Plastic DIP
PDIP
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2006 Microchip Technology Inc.
DS41159E-page 399
WORLDWIDE SALES AND SERVICE
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08/29/06
DS41159E-page 400
© 2006 Microchip Technology Inc.
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MICROCHIP
PIC18F258-I/SPSQTP
28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
MICROCHIP
PIC18F2580
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2580-E/ML
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2580-E/P
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2580-E/PT
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2580-E/SO
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
MICROCHIP
PIC18F2580-E/SP
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
MICROCHIP
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